├── BSP_Settings └── settings.bsp ├── FPGA ├── CXD2545.qpf ├── CXD2545.qsf ├── CXD2545.sdc ├── CXD2545.v ├── CXD2545_EMU.sopc ├── Cores │ ├── CXD2545S_OUT.v │ ├── CXD2545S_OUT_hw.tcl │ ├── CXD2545S_SUBQ.v │ ├── CXD2545S_SUBQ_hw.tcl │ ├── CXD2545_CPU.v │ ├── CXD2545_CPU_hw.tcl │ ├── CXD2545_DATAOUT.v │ ├── CXD2545_DATAOUT_hw.tcl │ ├── avalon_st_drainer.v │ └── avalon_st_drainer_hw.tcl └── Modules │ ├── CXD2545_CLKGEN.v │ ├── CXD2545_SENS.v │ ├── CXD2545_SOCT.v │ └── CXD2545_TRACK_COUNTER.v ├── NIOS_SOFT ├── Drivers │ ├── cxd2545_cpu │ │ └── cxd2545_cpu.c │ ├── sdcard_spi │ │ ├── sdcard_spi.c │ │ └── sdcard_spi.h │ ├── sens_ctrl │ │ └── sens_ctrl.c │ ├── sgdma │ │ └── sgdma.c │ └── spi │ │ └── nios_spi_command.c ├── Includes │ ├── cxd2545.h │ ├── cxd2545_ctrl.h │ ├── dbg_printf.h │ ├── display.h │ ├── nios_spi_command.h │ ├── sdcard.h │ ├── sector_reader.h │ ├── sens_ctrl.h │ └── sgdma.h ├── Makefile ├── libs │ ├── cxd2545 │ │ └── cxd2545.c │ ├── display │ │ └── display.c │ └── sectors │ │ └── sector_reader.c └── main.c ├── README.md ├── emu_image_creator ├── headers │ ├── nrg5_parser.h │ └── tools.h ├── libs │ └── nrg5 │ │ └── nrg5_parser.c ├── main.c ├── psx_image_from_nrg.cbp └── src │ └── tools.c ├── pcb_photos ├── SUB-CPU_emu_plus.JPG ├── Sony_Playstation_1_SCPH-5502_motherboard_bottom.jpg └── Sony_Playstation_1_SCPH-5502_motherboard_top.jpg └── research ├── Forsaken_play_track_12.dsl ├── Forsaken_play_track_6.dsl ├── Forsaken_read_toc.dsl ├── GPolice2_read_toc.dsl ├── emf_c16m_100.dsl └── html_logs ├── track_10.htm ├── track_10_files └── jquery.min.js ├── track_7.htm └── track_7_files └── jquery.min.js /FPGA/CXD2545.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2012 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 32-bit 20 | # Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version 21 | # Date created = 16:40:10 May 31, 2022 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "12.1" 26 | DATE = "16:40:10 May 31, 2022" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "CXD2545" 31 | -------------------------------------------------------------------------------- /FPGA/CXD2545.qsf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2006 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | 16 | # The default values for assignments are stored in the file 17 | # CII_Starter_TOP_assignment_defaults.qdf 18 | # If this file doesn't exist, and for assignments not listed, see file 19 | # assignment_defaults.qdf 20 | 21 | # Altera recommends that you do not modify this file. This 22 | # file is updated automatically by the Quartus II software 23 | # and any changes you make may be lost or overwritten. 24 | 25 | 26 | set_global_assignment -name FAMILY "Cyclone II" 27 | set_global_assignment -name DEVICE EP2C20F484C7 28 | set_global_assignment -name TOP_LEVEL_ENTITY CXD2545 29 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.1 SP2" 30 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:25:28 APRIL 24, 2006" 31 | set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1" 32 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 33 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 34 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 35 | set_location_assignment PIN_A13 -to GPIO_0[0] 36 | set_location_assignment PIN_B13 -to GPIO_0[1] 37 | set_location_assignment PIN_A14 -to GPIO_0[2] 38 | set_location_assignment PIN_B14 -to GPIO_0[3] 39 | set_location_assignment PIN_A15 -to GPIO_0[4] 40 | set_location_assignment PIN_B15 -to GPIO_0[5] 41 | set_location_assignment PIN_A16 -to GPIO_0[6] 42 | set_location_assignment PIN_B16 -to GPIO_0[7] 43 | set_location_assignment PIN_A17 -to GPIO_0[8] 44 | set_location_assignment PIN_B17 -to GPIO_0[9] 45 | set_location_assignment PIN_A18 -to GPIO_0[10] 46 | set_location_assignment PIN_B18 -to GPIO_0[11] 47 | set_location_assignment PIN_A19 -to GPIO_0[12] 48 | set_location_assignment PIN_B19 -to GPIO_0[13] 49 | set_location_assignment PIN_A20 -to GPIO_0[14] 50 | set_location_assignment PIN_B20 -to GPIO_0[15] 51 | set_location_assignment PIN_C21 -to GPIO_0[16] 52 | set_location_assignment PIN_C22 -to GPIO_0[17] 53 | set_location_assignment PIN_D21 -to GPIO_0[18] 54 | set_location_assignment PIN_D22 -to GPIO_0[19] 55 | set_location_assignment PIN_E21 -to GPIO_0[20] 56 | set_location_assignment PIN_E22 -to GPIO_0[21] 57 | set_location_assignment PIN_F21 -to GPIO_0[22] 58 | set_location_assignment PIN_F22 -to GPIO_0[23] 59 | set_location_assignment PIN_G21 -to GPIO_0[24] 60 | set_location_assignment PIN_G22 -to GPIO_0[25] 61 | set_location_assignment PIN_J21 -to GPIO_0[26] 62 | set_location_assignment PIN_J22 -to GPIO_0[27] 63 | set_location_assignment PIN_K21 -to GPIO_0[28] 64 | set_location_assignment PIN_K22 -to GPIO_0[29] 65 | set_location_assignment PIN_J19 -to GPIO_0[30] 66 | set_location_assignment PIN_J20 -to GPIO_0[31] 67 | set_location_assignment PIN_J18 -to GPIO_0[32] 68 | set_location_assignment PIN_K20 -to GPIO_0[33] 69 | set_location_assignment PIN_L19 -to GPIO_0[34] 70 | set_location_assignment PIN_L18 -to GPIO_0[35] 71 | set_location_assignment PIN_H12 -to GPIO_1[0] 72 | set_location_assignment PIN_H13 -to GPIO_1[1] 73 | set_location_assignment PIN_H14 -to GPIO_1[2] 74 | set_location_assignment PIN_G15 -to GPIO_1[3] 75 | set_location_assignment PIN_E14 -to GPIO_1[4] 76 | set_location_assignment PIN_E15 -to GPIO_1[5] 77 | set_location_assignment PIN_F15 -to GPIO_1[6] 78 | set_location_assignment PIN_G16 -to GPIO_1[7] 79 | set_location_assignment PIN_F12 -to GPIO_1[8] 80 | set_location_assignment PIN_F13 -to GPIO_1[9] 81 | set_location_assignment PIN_C14 -to GPIO_1[10] 82 | set_location_assignment PIN_D14 -to GPIO_1[11] 83 | set_location_assignment PIN_D15 -to GPIO_1[12] 84 | set_location_assignment PIN_D16 -to GPIO_1[13] 85 | set_location_assignment PIN_C17 -to GPIO_1[14] 86 | set_location_assignment PIN_C18 -to GPIO_1[15] 87 | set_location_assignment PIN_C19 -to GPIO_1[16] 88 | set_location_assignment PIN_C20 -to GPIO_1[17] 89 | set_location_assignment PIN_D19 -to GPIO_1[18] 90 | set_location_assignment PIN_D20 -to GPIO_1[19] 91 | set_location_assignment PIN_E20 -to GPIO_1[20] 92 | set_location_assignment PIN_F20 -to GPIO_1[21] 93 | set_location_assignment PIN_E19 -to GPIO_1[22] 94 | set_location_assignment PIN_E18 -to GPIO_1[23] 95 | set_location_assignment PIN_G20 -to GPIO_1[24] 96 | set_location_assignment PIN_G18 -to GPIO_1[25] 97 | set_location_assignment PIN_G17 -to GPIO_1[26] 98 | set_location_assignment PIN_H17 -to GPIO_1[27] 99 | set_location_assignment PIN_J15 -to GPIO_1[28] 100 | set_location_assignment PIN_H18 -to GPIO_1[29] 101 | set_location_assignment PIN_N22 -to GPIO_1[30] 102 | set_location_assignment PIN_N21 -to GPIO_1[31] 103 | set_location_assignment PIN_P15 -to GPIO_1[32] 104 | set_location_assignment PIN_N15 -to GPIO_1[33] 105 | set_location_assignment PIN_P17 -to GPIO_1[34] 106 | set_location_assignment PIN_P18 -to GPIO_1[35] 107 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0] 108 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1] 109 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2] 110 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3] 111 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4] 112 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5] 113 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6] 114 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7] 115 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8] 116 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9] 117 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10] 118 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11] 119 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12] 120 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13] 121 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14] 122 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15] 123 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16] 124 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17] 125 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18] 126 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19] 127 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20] 128 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21] 129 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22] 130 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23] 131 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24] 132 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25] 133 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26] 134 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27] 135 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28] 136 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29] 137 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30] 138 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31] 139 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32] 140 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33] 141 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34] 142 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35] 143 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0] 144 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1] 145 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2] 146 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3] 147 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4] 148 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5] 149 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6] 150 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7] 151 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8] 152 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9] 153 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10] 154 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11] 155 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12] 156 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13] 157 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14] 158 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15] 159 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16] 160 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17] 161 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18] 162 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19] 163 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20] 164 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21] 165 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22] 166 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23] 167 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24] 168 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25] 169 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26] 170 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27] 171 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28] 172 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29] 173 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30] 174 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31] 175 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32] 176 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33] 177 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34] 178 | set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35] 179 | set_location_assignment PIN_L22 -to SW[0] 180 | set_location_assignment PIN_L21 -to SW[1] 181 | set_location_assignment PIN_M22 -to SW[2] 182 | set_location_assignment PIN_V12 -to SW[3] 183 | set_location_assignment PIN_W12 -to SW[4] 184 | set_location_assignment PIN_U12 -to SW[5] 185 | set_location_assignment PIN_U11 -to SW[6] 186 | set_location_assignment PIN_M2 -to SW[7] 187 | set_location_assignment PIN_M1 -to SW[8] 188 | set_location_assignment PIN_L2 -to SW[9] 189 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[0] 190 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[1] 191 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[2] 192 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[3] 193 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[4] 194 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[5] 195 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[6] 196 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[7] 197 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[8] 198 | set_instance_assignment -name IO_STANDARD LVTTL -to SW[9] 199 | set_location_assignment PIN_J2 -to HEX0[0] 200 | set_location_assignment PIN_J1 -to HEX0[1] 201 | set_location_assignment PIN_H2 -to HEX0[2] 202 | set_location_assignment PIN_H1 -to HEX0[3] 203 | set_location_assignment PIN_F2 -to HEX0[4] 204 | set_location_assignment PIN_F1 -to HEX0[5] 205 | set_location_assignment PIN_E2 -to HEX0[6] 206 | set_location_assignment PIN_E1 -to HEX1[0] 207 | set_location_assignment PIN_H6 -to HEX1[1] 208 | set_location_assignment PIN_H5 -to HEX1[2] 209 | set_location_assignment PIN_H4 -to HEX1[3] 210 | set_location_assignment PIN_G3 -to HEX1[4] 211 | set_location_assignment PIN_D2 -to HEX1[5] 212 | set_location_assignment PIN_D1 -to HEX1[6] 213 | set_location_assignment PIN_G5 -to HEX2[0] 214 | set_location_assignment PIN_G6 -to HEX2[1] 215 | set_location_assignment PIN_C2 -to HEX2[2] 216 | set_location_assignment PIN_C1 -to HEX2[3] 217 | set_location_assignment PIN_E3 -to HEX2[4] 218 | set_location_assignment PIN_E4 -to HEX2[5] 219 | set_location_assignment PIN_D3 -to HEX2[6] 220 | set_location_assignment PIN_F4 -to HEX3[0] 221 | set_location_assignment PIN_D5 -to HEX3[1] 222 | set_location_assignment PIN_D6 -to HEX3[2] 223 | set_location_assignment PIN_J4 -to HEX3[3] 224 | set_location_assignment PIN_L8 -to HEX3[4] 225 | set_location_assignment PIN_F3 -to HEX3[5] 226 | set_location_assignment PIN_D4 -to HEX3[6] 227 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0] 228 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1] 229 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2] 230 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3] 231 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4] 232 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5] 233 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6] 234 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0] 235 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1] 236 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2] 237 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3] 238 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4] 239 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5] 240 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6] 241 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0] 242 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1] 243 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2] 244 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3] 245 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4] 246 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5] 247 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6] 248 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0] 249 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1] 250 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2] 251 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3] 252 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4] 253 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5] 254 | set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6] 255 | set_location_assignment PIN_R22 -to KEY[0] 256 | set_location_assignment PIN_R21 -to KEY[1] 257 | set_location_assignment PIN_T22 -to KEY[2] 258 | set_location_assignment PIN_T21 -to KEY[3] 259 | set_location_assignment PIN_R20 -to LEDR[0] 260 | set_location_assignment PIN_R19 -to LEDR[1] 261 | set_location_assignment PIN_U19 -to LEDR[2] 262 | set_location_assignment PIN_Y19 -to LEDR[3] 263 | set_location_assignment PIN_T18 -to LEDR[4] 264 | set_location_assignment PIN_V19 -to LEDR[5] 265 | set_location_assignment PIN_Y18 -to LEDR[6] 266 | set_location_assignment PIN_U18 -to LEDR[7] 267 | set_location_assignment PIN_R18 -to LEDR[8] 268 | set_location_assignment PIN_R17 -to LEDR[9] 269 | set_location_assignment PIN_U22 -to LEDG[0] 270 | set_location_assignment PIN_U21 -to LEDG[1] 271 | set_location_assignment PIN_V22 -to LEDG[2] 272 | set_location_assignment PIN_V21 -to LEDG[3] 273 | set_location_assignment PIN_W22 -to LEDG[4] 274 | set_location_assignment PIN_W21 -to LEDG[5] 275 | set_location_assignment PIN_Y22 -to LEDG[6] 276 | set_location_assignment PIN_Y21 -to LEDG[7] 277 | set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0] 278 | set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1] 279 | set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2] 280 | set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3] 281 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0] 282 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1] 283 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2] 284 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3] 285 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4] 286 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5] 287 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6] 288 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7] 289 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8] 290 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9] 291 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0] 292 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1] 293 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2] 294 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3] 295 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4] 296 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5] 297 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6] 298 | set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7] 299 | set_location_assignment PIN_D12 -to CLOCK_27[0] 300 | set_location_assignment PIN_E12 -to CLOCK_27[1] 301 | set_location_assignment PIN_B12 -to CLOCK_24[0] 302 | set_location_assignment PIN_A12 -to CLOCK_24[1] 303 | set_location_assignment PIN_L1 -to CLOCK_50 304 | set_location_assignment PIN_M21 -to EXT_CLOCK 305 | set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1] 306 | set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0] 307 | set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1] 308 | set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50 309 | set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK 310 | set_location_assignment PIN_H15 -to PS2_CLK 311 | set_location_assignment PIN_J14 -to PS2_DAT 312 | set_location_assignment PIN_F14 -to UART_RXD 313 | set_location_assignment PIN_G12 -to UART_TXD 314 | set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK 315 | set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT 316 | set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD 317 | set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD 318 | set_location_assignment PIN_E8 -to TDI 319 | set_location_assignment PIN_D8 -to TCS 320 | set_location_assignment PIN_C7 -to TCK 321 | set_location_assignment PIN_D7 -to TDO 322 | set_instance_assignment -name IO_STANDARD LVTTL -to TDI 323 | set_instance_assignment -name IO_STANDARD LVTTL -to TCS 324 | set_instance_assignment -name IO_STANDARD LVTTL -to TCK 325 | set_instance_assignment -name IO_STANDARD LVTTL -to TDO 326 | set_location_assignment PIN_D9 -to VGA_R[0] 327 | set_location_assignment PIN_C9 -to VGA_R[1] 328 | set_location_assignment PIN_A7 -to VGA_R[2] 329 | set_location_assignment PIN_B7 -to VGA_R[3] 330 | set_location_assignment PIN_B8 -to VGA_G[0] 331 | set_location_assignment PIN_C10 -to VGA_G[1] 332 | set_location_assignment PIN_B9 -to VGA_G[2] 333 | set_location_assignment PIN_A8 -to VGA_G[3] 334 | set_location_assignment PIN_A9 -to VGA_B[0] 335 | set_location_assignment PIN_D11 -to VGA_B[1] 336 | set_location_assignment PIN_A10 -to VGA_B[2] 337 | set_location_assignment PIN_B10 -to VGA_B[3] 338 | set_location_assignment PIN_A11 -to VGA_HS 339 | set_location_assignment PIN_B11 -to VGA_VS 340 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0] 341 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1] 342 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2] 343 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3] 344 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0] 345 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1] 346 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2] 347 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3] 348 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0] 349 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1] 350 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2] 351 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3] 352 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS 353 | set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS 354 | set_location_assignment PIN_A3 -to I2C_SCLK 355 | set_location_assignment PIN_B3 -to I2C_SDAT 356 | set_location_assignment PIN_A6 -to AUD_ADCLRCK 357 | set_location_assignment PIN_B6 -to AUD_ADCDAT 358 | set_location_assignment PIN_A5 -to AUD_DACLRCK 359 | set_location_assignment PIN_B5 -to AUD_DACDAT 360 | set_location_assignment PIN_B4 -to AUD_XCK 361 | set_location_assignment PIN_A4 -to AUD_BCLK 362 | set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK 363 | set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT 364 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK 365 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT 366 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK 367 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT 368 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK 369 | set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK 370 | set_location_assignment PIN_W4 -to DRAM_ADDR[0] 371 | set_location_assignment PIN_W5 -to DRAM_ADDR[1] 372 | set_location_assignment PIN_Y3 -to DRAM_ADDR[2] 373 | set_location_assignment PIN_Y4 -to DRAM_ADDR[3] 374 | set_location_assignment PIN_R6 -to DRAM_ADDR[4] 375 | set_location_assignment PIN_R5 -to DRAM_ADDR[5] 376 | set_location_assignment PIN_P6 -to DRAM_ADDR[6] 377 | set_location_assignment PIN_P5 -to DRAM_ADDR[7] 378 | set_location_assignment PIN_P3 -to DRAM_ADDR[8] 379 | set_location_assignment PIN_N4 -to DRAM_ADDR[9] 380 | set_location_assignment PIN_W3 -to DRAM_ADDR[10] 381 | set_location_assignment PIN_N6 -to DRAM_ADDR[11] 382 | set_location_assignment PIN_U3 -to DRAM_BA_0 383 | set_location_assignment PIN_V4 -to DRAM_BA_1 384 | set_location_assignment PIN_T3 -to DRAM_CAS_N 385 | set_location_assignment PIN_N3 -to DRAM_CKE 386 | set_location_assignment PIN_U4 -to DRAM_CLK 387 | set_location_assignment PIN_T6 -to DRAM_CS_N 388 | set_location_assignment PIN_U1 -to DRAM_DQ[0] 389 | set_location_assignment PIN_U2 -to DRAM_DQ[1] 390 | set_location_assignment PIN_V1 -to DRAM_DQ[2] 391 | set_location_assignment PIN_V2 -to DRAM_DQ[3] 392 | set_location_assignment PIN_W1 -to DRAM_DQ[4] 393 | set_location_assignment PIN_W2 -to DRAM_DQ[5] 394 | set_location_assignment PIN_Y1 -to DRAM_DQ[6] 395 | set_location_assignment PIN_Y2 -to DRAM_DQ[7] 396 | set_location_assignment PIN_N1 -to DRAM_DQ[8] 397 | set_location_assignment PIN_N2 -to DRAM_DQ[9] 398 | set_location_assignment PIN_P1 -to DRAM_DQ[10] 399 | set_location_assignment PIN_P2 -to DRAM_DQ[11] 400 | set_location_assignment PIN_R1 -to DRAM_DQ[12] 401 | set_location_assignment PIN_R2 -to DRAM_DQ[13] 402 | set_location_assignment PIN_T1 -to DRAM_DQ[14] 403 | set_location_assignment PIN_T2 -to DRAM_DQ[15] 404 | set_location_assignment PIN_R7 -to DRAM_LDQM 405 | set_location_assignment PIN_T5 -to DRAM_RAS_N 406 | set_location_assignment PIN_M5 -to DRAM_UDQM 407 | set_location_assignment PIN_R8 -to DRAM_WE_N 408 | set_location_assignment PIN_AB20 -to FL_ADDR[0] 409 | set_location_assignment PIN_AA14 -to FL_ADDR[1] 410 | set_location_assignment PIN_Y16 -to FL_ADDR[2] 411 | set_location_assignment PIN_R15 -to FL_ADDR[3] 412 | set_location_assignment PIN_T15 -to FL_ADDR[4] 413 | set_location_assignment PIN_U15 -to FL_ADDR[5] 414 | set_location_assignment PIN_V15 -to FL_ADDR[6] 415 | set_location_assignment PIN_W15 -to FL_ADDR[7] 416 | set_location_assignment PIN_R14 -to FL_ADDR[8] 417 | set_location_assignment PIN_Y13 -to FL_ADDR[9] 418 | set_location_assignment PIN_R12 -to FL_ADDR[10] 419 | set_location_assignment PIN_T12 -to FL_ADDR[11] 420 | set_location_assignment PIN_AB14 -to FL_ADDR[12] 421 | set_location_assignment PIN_AA13 -to FL_ADDR[13] 422 | set_location_assignment PIN_AB13 -to FL_ADDR[14] 423 | set_location_assignment PIN_AA12 -to FL_ADDR[15] 424 | set_location_assignment PIN_AB12 -to FL_ADDR[16] 425 | set_location_assignment PIN_AA20 -to FL_ADDR[17] 426 | set_location_assignment PIN_U14 -to FL_ADDR[18] 427 | set_location_assignment PIN_V14 -to FL_ADDR[19] 428 | set_location_assignment PIN_U13 -to FL_ADDR[20] 429 | set_location_assignment PIN_R13 -to FL_ADDR[21] 430 | set_location_assignment PIN_AB16 -to FL_DQ[0] 431 | set_location_assignment PIN_AA16 -to FL_DQ[1] 432 | set_location_assignment PIN_AB17 -to FL_DQ[2] 433 | set_location_assignment PIN_AA17 -to FL_DQ[3] 434 | set_location_assignment PIN_AB18 -to FL_DQ[4] 435 | set_location_assignment PIN_AA18 -to FL_DQ[5] 436 | set_location_assignment PIN_AB19 -to FL_DQ[6] 437 | set_location_assignment PIN_AA19 -to FL_DQ[7] 438 | set_location_assignment PIN_AA15 -to FL_OE_N 439 | set_location_assignment PIN_W14 -to FL_RST_N 440 | set_location_assignment PIN_Y14 -to FL_WE_N 441 | set_location_assignment PIN_AA3 -to SRAM_ADDR[0] 442 | set_location_assignment PIN_AB3 -to SRAM_ADDR[1] 443 | set_location_assignment PIN_AA4 -to SRAM_ADDR[2] 444 | set_location_assignment PIN_AB4 -to SRAM_ADDR[3] 445 | set_location_assignment PIN_AA5 -to SRAM_ADDR[4] 446 | set_location_assignment PIN_AB10 -to SRAM_ADDR[5] 447 | set_location_assignment PIN_AA11 -to SRAM_ADDR[6] 448 | set_location_assignment PIN_AB11 -to SRAM_ADDR[7] 449 | set_location_assignment PIN_V11 -to SRAM_ADDR[8] 450 | set_location_assignment PIN_W11 -to SRAM_ADDR[9] 451 | set_location_assignment PIN_R11 -to SRAM_ADDR[10] 452 | set_location_assignment PIN_T11 -to SRAM_ADDR[11] 453 | set_location_assignment PIN_Y10 -to SRAM_ADDR[12] 454 | set_location_assignment PIN_U10 -to SRAM_ADDR[13] 455 | set_location_assignment PIN_R10 -to SRAM_ADDR[14] 456 | set_location_assignment PIN_T7 -to SRAM_ADDR[15] 457 | set_location_assignment PIN_Y6 -to SRAM_ADDR[16] 458 | set_location_assignment PIN_Y5 -to SRAM_ADDR[17] 459 | set_location_assignment PIN_AB5 -to SRAM_CE_N 460 | set_location_assignment PIN_AA6 -to SRAM_DQ[0] 461 | set_location_assignment PIN_AB6 -to SRAM_DQ[1] 462 | set_location_assignment PIN_AA7 -to SRAM_DQ[2] 463 | set_location_assignment PIN_AB7 -to SRAM_DQ[3] 464 | set_location_assignment PIN_AA8 -to SRAM_DQ[4] 465 | set_location_assignment PIN_AB8 -to SRAM_DQ[5] 466 | set_location_assignment PIN_AA9 -to SRAM_DQ[6] 467 | set_location_assignment PIN_AB9 -to SRAM_DQ[7] 468 | set_location_assignment PIN_Y9 -to SRAM_DQ[8] 469 | set_location_assignment PIN_W9 -to SRAM_DQ[9] 470 | set_location_assignment PIN_V9 -to SRAM_DQ[10] 471 | set_location_assignment PIN_U9 -to SRAM_DQ[11] 472 | set_location_assignment PIN_R9 -to SRAM_DQ[12] 473 | set_location_assignment PIN_W8 -to SRAM_DQ[13] 474 | set_location_assignment PIN_V8 -to SRAM_DQ[14] 475 | set_location_assignment PIN_U8 -to SRAM_DQ[15] 476 | set_location_assignment PIN_Y7 -to SRAM_LB_N 477 | set_location_assignment PIN_T8 -to SRAM_OE_N 478 | set_location_assignment PIN_W7 -to SRAM_UB_N 479 | set_location_assignment PIN_AA10 -to SRAM_WE_N 480 | set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 481 | set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" 482 | set_global_assignment -name IP_TOOL_NAME sopc -qip CXD2545_EMU.qip 483 | set_global_assignment -name IP_TOOL_VERSION 12.1sp1 -qip CXD2545_EMU.qip 484 | set_global_assignment -name IP_TOOL_ENV sopc -qip CXD2545_EMU.qip 485 | set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 486 | set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 487 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 488 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 489 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 490 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 491 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 492 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 493 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 494 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 495 | set_location_assignment PIN_U20 -to SD_DAT3 496 | set_location_assignment PIN_V20 -to SD_CLK 497 | set_location_assignment PIN_Y20 -to SD_CMD 498 | set_location_assignment PIN_W20 -to SD_DAT 499 | set_location_assignment PIN_AB15 -to FL_CE_N 500 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON 501 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 502 | set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS OFF 503 | set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF 504 | set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" 505 | set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON 506 | set_global_assignment -name FITTER_EFFORT "STANDARD FIT" 507 | set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED 508 | set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF 509 | set_global_assignment -name SDC_FILE CXD2545.sdc 510 | set_global_assignment -name VERILOG_FILE CXD2545.v 511 | set_global_assignment -name VERILOG_FILE Modules/CXD2545_TRACK_COUNTER.v 512 | set_global_assignment -name VERILOG_FILE Modules/CXD2545_SOCT.v 513 | set_global_assignment -name VERILOG_FILE Modules/CXD2545_SENS.v 514 | set_global_assignment -name VERILOG_FILE Modules/CXD2545_CLKGEN.v 515 | set_global_assignment -name SOURCE_FILE db/CXD2545.cmp.rdb 516 | set_global_assignment -name QIP_FILE CXD2545_EMU.qip 517 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /FPGA/CXD2545.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name CLOCK_50 -period 50MHz [get_ports CLOCK_50] 2 | create_clock -name EXT_CLK -period 17MHz [get_ports GPIO_0[11]] 3 | 4 | create_generated_clock -name CD_SINGLE_SPEED -source [get_ports {GPIO_0[11]}] -divide_by 8 [get_registers {CLK_SINGLE_SPEED}] 5 | create_generated_clock -name CD_DOUBLE_SPEED -source [get_ports {GPIO_0[11]}] -divide_by 4 [get_registers {CLK_DOUBLE_SPEED}] 6 | #create_generated_clock -name CD_CLK -source [get_ports {GPIO_0[11]}] -divide_by 4 [get_registers {CD_CLK}] 7 | 8 | 9 | set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CD_SINGLE_SPEED}] 10 | set_false_path -from [get_clocks {CLOCK_50}] -to [get_clocks {CD_DOUBLE_SPEED}] 11 | 12 | #set_false_path -from [get_clocks {CLOCK_50}] -to [get_registers {SENS_OUT[*]}] 13 | #set_false_path -from [get_clocks {SYS_CLK}] -to [get_registers {track_count_r[*]}] 14 | 15 | #set_false_path -from [get_clocks {CLOCK_50}] -to [get_registers {trc_cnt_en_reg}] 16 | 17 | #set_false_path -from [all_clocks] -to [get_registers {GPIO_01[*]}] 18 | -------------------------------------------------------------------------------- /FPGA/CXD2545.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | 14 | module CXD2545 ( 15 | //////////////////// Clock Input //////////////////// 16 | input [1:0] CLOCK_24, // 24 MHz 17 | input [1:0] CLOCK_27, // 27 MHz 18 | input CLOCK_50, // 50 MHz 19 | input EXT_CLOCK, // External Clock 20 | 21 | //////////////////// Push Button //////////////////// 22 | input [3:0] KEY, // Pushbutton[3:0] 23 | 24 | //////////////////// DPDT Switch //////////////////// 25 | input [9:0] SW, // Toggle Switch[9:0] 26 | 27 | //////////////////// 7-SEG Dispaly //////////////////// 28 | output [6:0] HEX0, // Seven Segment Digit 0 29 | output [6:0] HEX1, // Seven Segment Digit 1 30 | output [6:0] HEX2, // Seven Segment Digit 2 31 | output [6:0] HEX3, // Seven Segment Digit 3 32 | 33 | //////////////////////// LED //////////////////////// 34 | output [7:0] LEDG, // LED Green[7:0] 35 | output [9:0] LEDR, // LED Red[9:0] 36 | 37 | //////////////////////// UART //////////////////////// 38 | output UART_TXD, // UART Transmitter 39 | input UART_RXD, // UART Receiver 40 | 41 | ///////////////////// SDRAM Interface //////////////// 42 | inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits 43 | output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits 44 | output DRAM_LDQM, // SDRAM Low-byte Data Mask 45 | output DRAM_UDQM, // SDRAM High-byte Data Mask 46 | output DRAM_WE_N, // SDRAM Write Enable 47 | output DRAM_CAS_N, // SDRAM Column Address Strobe 48 | output DRAM_RAS_N, // SDRAM Row Address Strobe 49 | output DRAM_CS_N, // SDRAM Chip Select 50 | output DRAM_BA_0, // SDRAM Bank Address 0 51 | output DRAM_BA_1, // SDRAM Bank Address 0 52 | output DRAM_CLK, // SDRAM Clock 53 | output DRAM_CKE, // SDRAM Clock Enable 54 | 55 | //////////////////// Flash Interface //////////////// 56 | inout [7:0] FL_DQ, // FLASH Data bus 8 Bits 57 | output [21:0] FL_ADDR, // FLASH Address bus 22 Bits 58 | output FL_WE_N, // FLASH Write Enable 59 | output FL_RST_N, // FLASH Reset 60 | output FL_OE_N, // FLASH Output Enable 61 | output FL_CE_N, // FLASH Chip Enable 62 | 63 | //////////////////// SRAM Interface //////////////// 64 | inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits 65 | output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits 66 | output SRAM_UB_N, // SRAM High-byte Data Mask 67 | output SRAM_LB_N, // SRAM Low-byte Data Mask 68 | output SRAM_WE_N, // SRAM Write Enable 69 | output SRAM_CE_N, // SRAM Chip Enable 70 | output SRAM_OE_N, // SRAM Output Enable 71 | 72 | //////////////////// SD_Card Interface //////////////// 73 | inout SD_DAT, // SD Card Data 74 | inout SD_DAT3, // SD Card Data 3 75 | inout SD_CMD, // SD Card Command Signal 76 | output SD_CLK, // SD Card Clock 77 | 78 | //////////////////// USB JTAG link //////////////////// 79 | input TDI, // CPLD -> FPGA (data in) 80 | input TCK, // CPLD -> FPGA (clk) 81 | input TCS, // CPLD -> FPGA (CS) 82 | output TDO, // FPGA -> CPLD (data out) 83 | 84 | //////////////////// I2C //////////////////////////// 85 | inout I2C_SDAT, // I2C Data 86 | output I2C_SCLK, // I2C Clock 87 | 88 | //////////////////// PS2 //////////////////////////// 89 | input PS2_DAT, // PS2 Data 90 | input PS2_CLK, // PS2 Clock 91 | 92 | //////////////////// VGA //////////////////////////// 93 | output VGA_HS, // VGA H_SYNC 94 | output VGA_VS, // VGA V_SYNC 95 | output [3:0] VGA_R, // VGA Red[3:0] 96 | output [3:0] VGA_G, // VGA Green[3:0] 97 | output [3:0] VGA_B, // VGA Blue[3:0] 98 | 99 | //////////////// Audio CODEC //////////////////////// 100 | inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock 101 | input AUD_ADCDAT, // Audio CODEC ADC Data 102 | inout AUD_DACLRCK, // Audio CODEC DAC LR Clock 103 | output AUD_DACDAT, // Audio CODEC DAC Data 104 | inout AUD_BCLK, // Audio CODEC Bit-Stream Clock 105 | output AUD_XCK, // Audio CODEC Chip Clock 106 | 107 | //////////////////// GPIO //////////////////////////// 108 | inout [35:0] GPIO_0, // GPIO Connection 0 109 | inout [35:0] GPIO_1 // GPIO Connection 1 110 | ); 111 | 112 | 113 | // Turn on all display 114 | /*assign HEX0 = 7'h7f; 115 | assign HEX1 = 7'h7f; 116 | assign HEX2 = 7'h7f; 117 | assign HEX3 = 7'h7f;*/ 118 | //assign LEDG = 8'h00; 119 | //assign LEDR = 10'h00; 120 | 121 | 122 | // All inout port turn to tri-state 123 | //assign DRAM_DQ = 16'hzzzz; 124 | assign FL_DQ = 8'hzz; 125 | assign SRAM_DQ = 16'hzzzz; 126 | assign SD_DAT = 1'bz; 127 | assign I2C_SDAT = 1'bz; 128 | assign AUD_ADCLRCK = 1'bz; 129 | assign AUD_DACLRCK = 1'bz; 130 | assign AUD_BCLK = 1'bz; 131 | //assign GPIO_0 = 36'bz; 132 | //assign GPIO_1 = 36'bz; 133 | 134 | 135 | // CDX2545 Controll pins 136 | localparam PIN_CLK = 18; 137 | localparam PIN_DATA = 19; 138 | localparam PIN_XLAT = 17; 139 | localparam PIN_SENS = 16; 140 | localparam PIN_SCLK = 15; 141 | 142 | // CDX2545 SUBQ Pins 143 | localparam PIN_SQCK = 14; 144 | localparam PIN_SUBQ = 13; 145 | localparam PIN_SCOR = 12; 146 | 147 | // CDX2545 Data Pins 148 | localparam PIN_EMPH = 0; 149 | localparam PIN_C2PO = 1; 150 | localparam PIN_CDCLK = 4; 151 | localparam PIN_CDLRCK = 2; 152 | localparam PIN_CDDATA = 3; 153 | 154 | // CXD2545 Clocks 155 | localparam PIN_MCLK = 5; // Clock SUBCPU 156 | localparam PIN_SYSCLK = 11; // System Clock 16.9xxx MHz 157 | 158 | // CXD2545 Status pin 159 | localparam PIN_LMTSW = 10; 160 | localparam PIN_DOOR = 7; 161 | 162 | reg w; 163 | 164 | //assign LEDG[3] = w; 165 | 166 | wire CPU_CLK = CLOCK_50; 167 | wire ext_clk = GPIO_0[PIN_SYSCLK]; 168 | 169 | reg [2:0] clk_div; 170 | reg [7:0] clk_div2; 171 | 172 | wire clk_44100; 173 | wire cdr_dat_clk; 174 | wire lbit; 175 | wire cdr_data; 176 | wire scor, sqck, sqso; 177 | 178 | reg CLK_DOUBLE_SPEED, CLK_SINGLE_SPEED; 179 | wire CD_CLK; 180 | //wire cd_clk = ext_clk; 181 | 182 | reg SUB_CPU_CLK; 183 | always @(negedge ext_clk) begin 184 | clk_div <= clk_div + 1'b1; 185 | 186 | SUB_CPU_CLK <= clk_div[1]; 187 | CLK_SINGLE_SPEED <= clk_div[1]; 188 | CLK_DOUBLE_SPEED <= clk_div[0]; 189 | end 190 | 191 | assign CD_CLK = (DSPB == 0) ? CLK_SINGLE_SPEED : CLK_DOUBLE_SPEED; 192 | 193 | 194 | assign GPIO_0[PIN_EMPH] = SW[0]; // EMPH 195 | assign GPIO_0[PIN_C2PO] = c2po; // C2PO 196 | assign GPIO_0[PIN_CDLRCK] = clk_44100; // LRCK (44100 / 88200) 197 | assign GPIO_0[PIN_CDDATA] = cdr_data; // DATA 198 | assign GPIO_0[PIN_CDCLK] = cdr_dat_clk; // BCLK / D15 (2.12M / 4.23) 199 | assign GPIO_0[PIN_MCLK] = SUB_CPU_CLK; // SUBCPU CLK 200 | 201 | assign GPIO_0[PIN_SCOR] = (SOCT_SEL == 1'b0) ? scor : 0; //scor; 202 | assign sqck = GPIO_0[PIN_SQCK]; 203 | 204 | assign GPIO_0[PIN_SUBQ] = (SOCT_SEL == 1'b0) ? sqso : SOCT_OUT; 205 | 206 | reg [35:0] GPIO_01; 207 | 208 | always @(posedge CPU_CLK) begin 209 | GPIO_01 <= GPIO_0; 210 | end 211 | 212 | assign GPIO_0[35:0] = {30'bz, /*clk_div[1]*/1'bz, 5'bz}; 213 | 214 | wire c2po; 215 | 216 | 217 | assign GPIO_1[0] = GPIO_01[PIN_CLK]; // CLK 218 | assign GPIO_1[1] = GPIO_01[PIN_DATA]; // DATA 219 | assign GPIO_1[2] = GPIO_01[PIN_XLAT]; // LATCH 220 | assign GPIO_1[3] = GPIO_01[PIN_SENS]; // SENS 221 | 222 | /* 223 | assign GPIO_1[0] = SD_DAT3; // CS 224 | assign GPIO_1[1] = SD_CLK; // CLK 225 | assign GPIO_1[2] = SD_CMD; // MOSI 226 | assign GPIO_1[3] = SD_DAT; // MISO 227 | */ 228 | assign GPIO_1[4] = c2po;//time_check;//SD_CLK;//cd_clk;//GPIO_01[15]; // SCLK 229 | assign GPIO_1[5] = GPIO_01[PIN_SQCK]; // SQCK 230 | assign GPIO_1[6] = GPIO_01[PIN_SUBQ]; // SUBQ 231 | assign GPIO_1[7] = scor;// GPIO_01[12]; // SQCR 232 | 233 | assign GPIO_1[8] = cdr_dat_clk; 234 | assign GPIO_1[9] = clk_44100; 235 | assign GPIO_1[10] = cdr_data; 236 | 237 | 238 | 239 | assign AUD_XCK = CLOCK_24[0]; 240 | 241 | wire I2C_CLK; 242 | wire I2C_DAT; 243 | 244 | 245 | assign I2C_SCLK = (I2C_CLK == 1) ? 1'bz : 1'b0; 246 | assign I2C_SDAT = (I2C_DAT == 1) ? 1'bz : 1'b0; 247 | wire TRK0, DSPB; 248 | 249 | assign GPIO_0[PIN_LMTSW] = (TRK0 == 1) ? 1'b0 : 1'b1; 250 | 251 | 252 | wire door; 253 | assign LEDG[0] = door; 254 | assign LEDR[0] = TRK0; 255 | assign LEDR[1] = DSPB; 256 | assign GPIO_0[PIN_DOOR] = ((door == 1) || (SW[1] == 1)) ? 1'b0 : 1'bz; 257 | assign LEDG[1] = SW[1]; 258 | 259 | assign LEDR[9] = SW[9]; 260 | 261 | assign LEDG[7:4] = ~KEY; 262 | 263 | wire sens_out; 264 | 265 | wire trc_toggle; 266 | wire [31:0] track_count; 267 | 268 | wire [15:0] trc_div; 269 | CXD2545_TRACK_COUNTER trc_cnt_inst( 270 | .clk(CPU_CLK), 271 | .div(trc_div), 272 | .toggle_cnt(256), 273 | .toggle_clk(trc_toggle), 274 | 275 | .trigger(trc_cnt_en), 276 | .track_count(track_count) 277 | ); 278 | 279 | 280 | 281 | wire [15:0] SENS_PIN; 282 | 283 | 284 | reg REG_CLK1; 285 | reg REG_DATA1; 286 | reg REG_XLAT1; 287 | reg REG_SQCK1; 288 | 289 | reg REG_CLK2; 290 | reg REG_DATA2; 291 | reg REG_XLAT2; 292 | reg REG_SQCK2; 293 | 294 | reg REG_CLK; 295 | reg REG_DATA; 296 | reg REG_XLAT; 297 | reg REG_SQCK; 298 | 299 | 300 | always @(posedge CPU_CLK) begin 301 | REG_CLK1 <= GPIO_0[PIN_CLK]; 302 | REG_DATA1 <= GPIO_0[PIN_DATA]; 303 | REG_XLAT1 <= GPIO_0[PIN_XLAT]; 304 | REG_SQCK1 <= GPIO_0[PIN_SQCK]; 305 | 306 | 307 | REG_CLK2 <= REG_CLK1; 308 | REG_DATA2 <= REG_DATA1; 309 | REG_XLAT2 <= REG_XLAT1; 310 | REG_SQCK2 <= REG_SQCK1; 311 | 312 | REG_CLK <= REG_CLK2; 313 | REG_DATA <= REG_DATA2; 314 | REG_XLAT <= REG_XLAT2; 315 | REG_SQCK <= REG_SQCK2; 316 | 317 | end 318 | 319 | 320 | CXD2545_SENS sens_inst( 321 | .sclk(CPU_CLK), 322 | .clk(REG_CLK), 323 | .data(REG_DATA), 324 | .xlat(REG_XLAT), 325 | .sens_data({SENS_PIN[15:14], c2po, trc_toggle, SENS_PIN[11], ~c2po, SENS_PIN[9:0]}), 326 | .sens(sens_out) 327 | ); 328 | 329 | 330 | wire SOCT_OUT, SOCT_SEL; 331 | 332 | CXD2545_SOCT soct_inst( 333 | .sclk(CPU_CLK), 334 | .xlat(REG_XLAT), 335 | 336 | .PER(8'hff), 337 | .C1(3'b000), 338 | .C2(3'b000), 339 | 340 | .FOK(SENS_PIN[5]), 341 | .GFS(~c2po), 342 | .LOCK(~c2po), 343 | .EMPH(1'b0), 344 | 345 | .clk(REG_SQCK), 346 | .out(SOCT_OUT), 347 | ); 348 | 349 | assign GPIO_0[PIN_SENS] = sens_out; 350 | 351 | assign DRAM_CLK = CPU_CLK; 352 | 353 | wire DRAIN_DMA; 354 | 355 | wire time_check; 356 | 357 | CXD2545_EMU CXD2545_TS( 358 | .sys_clk (CPU_CLK), 359 | .reset_n (SW[9]), 360 | 361 | .cd_clk(CD_CLK), 362 | 363 | .rxd_to_the_UART_DEBUG (GPIO_1[29]), 364 | .txd_from_the_UART_DEBUG (GPIO_1[31]), 365 | 366 | .out_port_from_the_HEX4 ({1'bz, HEX3, 1'bz, HEX2, 1'bz, HEX1, 1'bz, HEX0}), 367 | .in_port_to_the_BUTTONS (KEY), 368 | 369 | 370 | 371 | .in_port_to_the_TRACK_COUNTER (track_count), 372 | .out_port_from_the_CXD2545_CTRL ({SOCT_SEL, time_check, trc_cnt_en, door, DSPB, TRK0, I2C_CLK, DRAIN_DMA}), 373 | .out_port_from_the_SENS_OUT (SENS_PIN), 374 | 375 | .CLOK_to_the_CXD2545_CPU_0 (GPIO_0[PIN_CLK]), 376 | .DATA_to_the_CXD2545_CPU_0 (GPIO_0[PIN_DATA]), 377 | .XLAT_to_the_CXD2545_CPU_0 (GPIO_0[PIN_XLAT]), 378 | 379 | .MISO_to_the_SDCARD_SPI (SD_DAT), 380 | .MOSI_from_the_SDCARD_SPI (SD_CMD), 381 | .SCLK_from_the_SDCARD_SPI (SD_CLK), 382 | .SS_n_from_the_SDCARD_SPI (SD_DAT3), 383 | 384 | .drain_to_the_CXD2545_DRAIN (DRAIN_DMA), 385 | 386 | .cd_c2po_from_the_CXD2545S (c2po), 387 | .cd_clk_from_the_CXD2545S (cdr_dat_clk), 388 | .cd_lr_from_the_CXD2545S (clk_44100), 389 | .cd_data_from_the_CXD2545S (cdr_data), 390 | 391 | .in_sqck_to_the_CXD2545S_SUBQ_OUT (REG_SQCK), 392 | .out_scor_from_the_CXD2545S_SUBQ_OUT (scor), 393 | .out_sqso_from_the_CXD2545S_SUBQ_OUT (sqso), 394 | 395 | .out_port_from_the_CXD_TRACK_CTRL (trc_div) 396 | ); 397 | 398 | endmodule -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545S_OUT.v: -------------------------------------------------------------------------------- 1 | // CXD2545S_OUT.v 2 | 3 | // This file was auto-generated as a prototype implementation of a module 4 | // created in component editor. It ties off all outputs to ground and 5 | // ignores all inputs. It needs to be edited to make it do something 6 | // useful. 7 | // 8 | // This file will not be automatically regenerated. You should check it in 9 | // to your version control system if you want to keep it. 10 | 11 | `timescale 1 ps / 1 ps 12 | 13 | module CXD2545S_OUT ( 14 | input wire clk, // clock.clk 15 | input wire rst, // .reset_n 16 | output wire in_ready, // .ready 17 | input wire in_valid, // .valid 18 | input wire [31:0] in_data, // .data 19 | input wire in_sof, // .startofpacket 20 | input wire in_eof, // .endofpacket 21 | input wire [1:0] in_empty, // .empty 22 | 23 | 24 | 25 | output reg cd_c2po, 26 | output wire cd_clk, 27 | output reg cd_lr, 28 | output reg cd_data 29 | ); 30 | 31 | assign in_ready = wait_data; 32 | 33 | reg [47:0] cddata; 34 | reg [47:0] cddata_new; 35 | 36 | reg wait_data; 37 | 38 | 39 | reg [9:0] word_cnt; 40 | 41 | reg new_c2po; 42 | 43 | always @(negedge clk) begin 44 | if(rst == 0) begin 45 | wait_data <= 1'b1; 46 | word_cnt <= 10'h000; 47 | new_c2po <= 1'b0; 48 | end else begin 49 | 50 | if((wait_data == 1) && (in_valid == 1)) begin 51 | if(in_sof == 1'b1) begin 52 | word_cnt <= 10'h000; 53 | end else begin 54 | word_cnt <= word_cnt + 1'b1; 55 | end 56 | 57 | if((word_cnt < 587) || (in_sof == 1'b1)) begin 58 | cddata_new <= { in_data[31], in_data[31], in_data[31], in_data[31], in_data[31], in_data[31], in_data[31], in_data[31], in_data[31:16], 59 | in_data[15], in_data[15], in_data[15], in_data[15], in_data[15], in_data[15], in_data[15], in_data[15], in_data[15:0] 60 | }; 61 | wait_data <= 1'b0; 62 | end 63 | end 64 | 65 | if((cd_cnt == 0) && (clk_out == 1)) begin 66 | if(wait_data == 0) begin 67 | wait_data <= 1'b1; 68 | cddata <= cddata_new; 69 | new_c2po <= 1'b0; 70 | end else begin 71 | cddata <= 48'h000000000000; 72 | new_c2po <= 1'b1; 73 | end 74 | end 75 | 76 | end 77 | end 78 | 79 | reg [5:0] cd_cnt; 80 | reg clk_out; 81 | reg [47:0] cdout_data; 82 | reg c2po_delay; 83 | always @(negedge clk) begin 84 | clk_out <= ~clk_out; 85 | if(clk_out == 1'b1) begin 86 | cd_c2po <= c2po_delay; 87 | if(cd_cnt > 0) begin 88 | cd_cnt <= cd_cnt - 1'b1; 89 | end else begin 90 | cd_cnt <= 47; 91 | cdout_data <= cddata; 92 | c2po_delay <= new_c2po; 93 | end 94 | cd_lr <= (cd_cnt < 24) ? 1'b0 : 1'b1; 95 | cd_data <= cdout_data[cd_cnt]; 96 | end; 97 | end 98 | 99 | assign cd_clk = clk_out; 100 | 101 | endmodule 102 | 103 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545S_OUT_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 12.1sp1 2 | # Fri Mar 19 19:44:59 MSK 2021 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # CXD2545S_OUT "CXD2545S_OUT" v1.8 8 | # VBKesha 2021.03.19.19:44:59 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 11.0 14 | # 15 | package require -exact sopc 11.0 16 | 17 | 18 | # 19 | # module CXD2545S_OUT 20 | # 21 | set_module_property NAME CXD2545S_OUT 22 | set_module_property VERSION 1.8 23 | set_module_property INTERNAL false 24 | set_module_property OPAQUE_ADDRESS_MAP true 25 | set_module_property GROUP Interfaces 26 | set_module_property AUTHOR VBKesha 27 | set_module_property DISPLAY_NAME CXD2545S_OUT 28 | set_module_property TOP_LEVEL_HDL_FILE CXD2545S_OUT.v 29 | set_module_property TOP_LEVEL_HDL_MODULE CXD2545S_OUT 30 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 31 | set_module_property EDITABLE true 32 | set_module_property ANALYZE_HDL AUTO 33 | set_module_property STATIC_TOP_LEVEL_MODULE_NAME CXD2545S_OUT 34 | set_module_property FIX_110_VIP_PATH false 35 | set_module_property REPORT_TO_TALKBACK false 36 | set_module_property ALLOW_GREYBOX_GENERATION false 37 | 38 | 39 | # 40 | # files 41 | # 42 | add_file CXD2545S_OUT.v {SYNTHESIS SIMULATION} 43 | 44 | 45 | # 46 | # file sets 47 | # 48 | 49 | # 50 | # parameters 51 | # 52 | 53 | 54 | # 55 | # display items 56 | # 57 | 58 | 59 | # 60 | # connection point clock 61 | # 62 | add_interface clock clock end 63 | set_interface_property clock clockRate 0 64 | set_interface_property clock ENABLED true 65 | 66 | add_interface_port clock clk clk Input 1 67 | 68 | 69 | # 70 | # connection point clock_reset 71 | # 72 | add_interface clock_reset reset end 73 | set_interface_property clock_reset associatedClock clock 74 | set_interface_property clock_reset synchronousEdges DEASSERT 75 | set_interface_property clock_reset ENABLED true 76 | 77 | add_interface_port clock_reset rst reset_n Input 1 78 | 79 | 80 | # 81 | # connection point data_in 82 | # 83 | add_interface data_in avalon_streaming end 84 | set_interface_property data_in associatedClock clock 85 | set_interface_property data_in associatedReset clock_reset 86 | set_interface_property data_in dataBitsPerSymbol 8 87 | set_interface_property data_in errorDescriptor "" 88 | set_interface_property data_in firstSymbolInHighOrderBits true 89 | set_interface_property data_in maxChannel 0 90 | set_interface_property data_in readyLatency 0 91 | set_interface_property data_in ENABLED true 92 | 93 | add_interface_port data_in in_valid valid Input 1 94 | add_interface_port data_in in_data data Input 32 95 | add_interface_port data_in in_eof endofpacket Input 1 96 | add_interface_port data_in in_sof startofpacket Input 1 97 | add_interface_port data_in in_ready ready Output 1 98 | add_interface_port data_in in_empty empty Input 2 99 | 100 | 101 | # 102 | # connection point cd_data_bus 103 | # 104 | add_interface cd_data_bus conduit end 105 | set_interface_property cd_data_bus associatedClock "" 106 | set_interface_property cd_data_bus associatedReset "" 107 | set_interface_property cd_data_bus ENABLED true 108 | 109 | add_interface_port cd_data_bus cd_clk export Output 1 110 | add_interface_port cd_data_bus cd_lr export Output 1 111 | add_interface_port cd_data_bus cd_data export Output 1 112 | add_interface_port cd_data_bus cd_c2po export Output 1 113 | 114 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545S_SUBQ.v: -------------------------------------------------------------------------------- 1 | // CXD2545S_SUBQ.v 2 | 3 | // This file was auto-generated as a prototype implementation of a module 4 | // created in component editor. It ties off all outputs to ground and 5 | // ignores all inputs. It needs to be edited to make it do something 6 | // useful. 7 | // 8 | // This file will not be automatically regenerated. You should check it in 9 | // to your version control system if you want to keep it. 10 | 11 | `timescale 1 ps / 1 ps 12 | module CXD2545S_SUBQ ( 13 | input wire clk, // Clock.clk 14 | input wire reset, // Reset.reset 15 | 16 | input wire in_eof, // SUBQ_Sink.endofpacket 17 | input wire in_sof, // .startofpacket 18 | output wire out_ready, // .ready 19 | input wire in_valid, // .valid 20 | input wire [31:0] in_data, // .data 21 | input wire [1:0] in_empty, // .empty 22 | 23 | input wire in_sqck, // SUBQ_OUT.export 24 | output reg out_sqso, // .export 25 | output reg out_scor, // .export 26 | output wire out_emph // .export 27 | ); 28 | 29 | assign out_ready = 1'b1; 30 | 31 | reg [95:0] sub_q; 32 | reg [31:0] sub_q_2; 33 | reg [31:0] sub_q_1; 34 | 35 | reg sqck_cur; 36 | reg sqck_prev; 37 | reg [3:0] scor_latch; 38 | 39 | assign out_emph = 1'b0; 40 | 41 | always @(negedge clk) begin 42 | 43 | if(in_valid == 1'b1) begin 44 | sub_q_1 <= in_data; 45 | sub_q_2 <= sub_q_1; 46 | 47 | if(in_eof == 1'b1) begin 48 | sub_q <= {sub_q_2, sub_q_1, in_data}; 49 | out_sqso <= 1'b1; 50 | end 51 | end 52 | 53 | if((in_valid == 1'b1) && (in_eof == 1'b1)) begin 54 | scor_latch <= 4'b1111; 55 | out_scor <= 1'b1; 56 | end else begin 57 | 58 | if(scor_latch > 0) begin 59 | scor_latch <= scor_latch - 1'b1; 60 | end else begin 61 | out_scor <= 1'b0; 62 | end 63 | 64 | end 65 | 66 | if((sqck_cur == 1'b0) && (sqck_prev == 1'b1)) begin 67 | out_sqso <= sub_q[95]; 68 | sub_q <= {sub_q[94:0], 1'b0}; 69 | end 70 | 71 | sqck_cur <= in_sqck; 72 | sqck_prev <= sqck_cur; 73 | end 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545S_SUBQ_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 12.1sp1 2 | # Sun Apr 18 11:19:23 MSD 2021 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # CXD2545S_SUBQ "CXD2545S_SUBQ" v1.4 8 | # null 2021.04.18.11:19:23 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 11.0 14 | # 15 | package require -exact sopc 11.0 16 | 17 | 18 | # 19 | # module CXD2545S_SUBQ 20 | # 21 | set_module_property NAME CXD2545S_SUBQ 22 | set_module_property VERSION 1.4 23 | set_module_property INTERNAL false 24 | set_module_property OPAQUE_ADDRESS_MAP true 25 | set_module_property GROUP Interfaces 26 | set_module_property DISPLAY_NAME CXD2545S_SUBQ 27 | set_module_property TOP_LEVEL_HDL_FILE CXD2545S_SUBQ.v 28 | set_module_property TOP_LEVEL_HDL_MODULE CXD2545S_SUBQ 29 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 30 | set_module_property EDITABLE true 31 | set_module_property ANALYZE_HDL AUTO 32 | set_module_property STATIC_TOP_LEVEL_MODULE_NAME CXD2545S_SUBQ 33 | set_module_property FIX_110_VIP_PATH false 34 | set_module_property REPORT_TO_TALKBACK false 35 | set_module_property ALLOW_GREYBOX_GENERATION false 36 | 37 | 38 | # 39 | # files 40 | # 41 | add_file CXD2545S_SUBQ.v {SYNTHESIS SIMULATION} 42 | 43 | 44 | # 45 | # file sets 46 | # 47 | 48 | # 49 | # parameters 50 | # 51 | 52 | 53 | # 54 | # display items 55 | # 56 | 57 | 58 | # 59 | # connection point SUBQ_OUT 60 | # 61 | add_interface SUBQ_OUT conduit end 62 | set_interface_property SUBQ_OUT associatedClock "" 63 | set_interface_property SUBQ_OUT associatedReset "" 64 | set_interface_property SUBQ_OUT ENABLED true 65 | 66 | add_interface_port SUBQ_OUT in_sqck export Input 1 67 | add_interface_port SUBQ_OUT out_scor export Output 1 68 | add_interface_port SUBQ_OUT out_sqso export Output 1 69 | add_interface_port SUBQ_OUT out_emph export Output 1 70 | 71 | 72 | # 73 | # connection point SUBQ_Sink 74 | # 75 | add_interface SUBQ_Sink avalon_streaming end 76 | set_interface_property SUBQ_Sink associatedClock Clock 77 | set_interface_property SUBQ_Sink dataBitsPerSymbol 8 78 | set_interface_property SUBQ_Sink errorDescriptor "" 79 | set_interface_property SUBQ_Sink firstSymbolInHighOrderBits true 80 | set_interface_property SUBQ_Sink maxChannel 0 81 | set_interface_property SUBQ_Sink readyLatency 0 82 | set_interface_property SUBQ_Sink ENABLED true 83 | 84 | add_interface_port SUBQ_Sink in_eof endofpacket Input 1 85 | add_interface_port SUBQ_Sink in_sof startofpacket Input 1 86 | add_interface_port SUBQ_Sink out_ready ready Output 1 87 | add_interface_port SUBQ_Sink in_valid valid Input 1 88 | add_interface_port SUBQ_Sink in_data data Input 32 89 | add_interface_port SUBQ_Sink in_empty empty Input 2 90 | 91 | 92 | # 93 | # connection point Clock 94 | # 95 | add_interface Clock clock end 96 | set_interface_property Clock clockRate 0 97 | set_interface_property Clock ENABLED true 98 | 99 | add_interface_port Clock clk clk Input 1 100 | 101 | 102 | # 103 | # connection point Reset 104 | # 105 | add_interface Reset reset end 106 | set_interface_property Reset associatedClock Clock 107 | set_interface_property Reset synchronousEdges DEASSERT 108 | set_interface_property Reset ENABLED true 109 | 110 | add_interface_port Reset reset reset Input 1 111 | 112 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545_CPU.v: -------------------------------------------------------------------------------- 1 | // CXD2545_CPU.v 2 | 3 | // This file was auto-generated as a prototype implementation of a module 4 | // created in component editor. It ties off all outputs to ground and 5 | // ignores all inputs. It needs to be edited to make it do something 6 | // useful. 7 | // 8 | // This file will not be automatically regenerated. You should check it in 9 | // to your version control system if you want to keep it. 10 | 11 | `timescale 1 ps / 1 ps 12 | module CXD2545_CPU ( 13 | input wire clk, // clock.clk 14 | input wire rst_n, // .reset 15 | input wire [3:0] m_addr, // avalon_slave.address 16 | output wire [31:0] m_read_data, // .readdata 17 | input wire [31:0] m_write_data,// .writedata 18 | input wire m_read, // .read_n 19 | input wire m_write, // .write_n 20 | output wire m_irq, // interrupt_sender.irq_n 21 | 22 | input wire CLOK, // cxd_cpu.export 23 | input wire DATA, // .export 24 | input wire XLAT // .export 25 | ); 26 | 27 | reg [23:0] cxd_cmd; 28 | reg [23:0] cxd_cur_cmd; 29 | 30 | 31 | reg reg_cur_clok; 32 | reg reg_prev_clok; 33 | reg reg_data_cur; 34 | reg reg_cur_xlat; 35 | reg reg_prev_xlat; 36 | 37 | reg irq; 38 | 39 | assign m_read_data[23:0] = cxd_cmd; 40 | assign m_irq = irq; 41 | 42 | always @(posedge clk) begin 43 | if(rst_n == 1) begin 44 | irq <= 1'b1; 45 | end else begin 46 | reg_prev_clok <= reg_cur_clok; 47 | reg_cur_clok <= CLOK; 48 | 49 | reg_prev_xlat <= reg_cur_xlat; 50 | reg_cur_xlat <= XLAT; 51 | 52 | reg_data_cur <= DATA; 53 | 54 | if((reg_prev_clok == 1'b0) && (reg_cur_clok == 1'b1)) begin 55 | cxd_cur_cmd[23:0] <= {reg_data_cur, cxd_cur_cmd[23:1]}; 56 | end 57 | 58 | if((reg_prev_xlat == 1'b1) && (reg_cur_xlat == 1'b0)) begin 59 | cxd_cmd <= cxd_cur_cmd; 60 | irq <= 1'b0; 61 | end 62 | 63 | if((m_read == 1'b0) && (m_addr == 4'h1)) begin 64 | irq <= 1'b1; 65 | end 66 | 67 | end 68 | 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545_CPU_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 12.1sp1 2 | # Thu Mar 04 01:31:12 MSK 2021 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # CXD2545_CPU "CXD2545_CPU" v1.0 8 | # VBKesha 2021.03.04.01:31:12 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 11.0 14 | # 15 | package require -exact sopc 11.0 16 | 17 | 18 | # 19 | # module CXD2545_CPU 20 | # 21 | set_module_property NAME CXD2545_CPU 22 | set_module_property VERSION 1.0 23 | set_module_property INTERNAL false 24 | set_module_property OPAQUE_ADDRESS_MAP true 25 | set_module_property GROUP Interfaces 26 | set_module_property AUTHOR VBKesha 27 | set_module_property DISPLAY_NAME CXD2545_CPU 28 | set_module_property TOP_LEVEL_HDL_FILE CXD2545_CPU.v 29 | set_module_property TOP_LEVEL_HDL_MODULE CXD2545_CPU 30 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 31 | set_module_property EDITABLE true 32 | set_module_property ANALYZE_HDL AUTO 33 | set_module_property STATIC_TOP_LEVEL_MODULE_NAME CXD2545_CPU 34 | set_module_property FIX_110_VIP_PATH false 35 | set_module_property REPORT_TO_TALKBACK false 36 | set_module_property ALLOW_GREYBOX_GENERATION false 37 | 38 | 39 | # 40 | # files 41 | # 42 | add_file CXD2545_CPU.v {SYNTHESIS SIMULATION} 43 | 44 | 45 | # 46 | # file sets 47 | # 48 | 49 | # 50 | # parameters 51 | # 52 | 53 | 54 | # 55 | # display items 56 | # 57 | 58 | 59 | # 60 | # connection point clock 61 | # 62 | add_interface clock clock end 63 | set_interface_property clock clockRate 0 64 | set_interface_property clock ENABLED true 65 | 66 | add_interface_port clock clk clk Input 1 67 | 68 | 69 | # 70 | # connection point clock_reset 71 | # 72 | add_interface clock_reset reset end 73 | set_interface_property clock_reset associatedClock clock 74 | set_interface_property clock_reset synchronousEdges BOTH 75 | set_interface_property clock_reset ENABLED true 76 | 77 | add_interface_port clock_reset rst_n reset Input 1 78 | 79 | 80 | # 81 | # connection point avalon_slave 82 | # 83 | add_interface avalon_slave avalon end 84 | set_interface_property avalon_slave addressAlignment DYNAMIC 85 | set_interface_property avalon_slave addressUnits WORDS 86 | set_interface_property avalon_slave associatedClock clock 87 | set_interface_property avalon_slave associatedReset clock_reset 88 | set_interface_property avalon_slave burstOnBurstBoundariesOnly false 89 | set_interface_property avalon_slave explicitAddressSpan 0 90 | set_interface_property avalon_slave holdTime 0 91 | set_interface_property avalon_slave isMemoryDevice false 92 | set_interface_property avalon_slave isNonVolatileStorage false 93 | set_interface_property avalon_slave linewrapBursts false 94 | set_interface_property avalon_slave maximumPendingReadTransactions 0 95 | set_interface_property avalon_slave printableDevice false 96 | set_interface_property avalon_slave readLatency 0 97 | set_interface_property avalon_slave readWaitTime 1 98 | set_interface_property avalon_slave setupTime 0 99 | set_interface_property avalon_slave timingUnits Cycles 100 | set_interface_property avalon_slave writeWaitTime 0 101 | set_interface_property avalon_slave ENABLED true 102 | 103 | add_interface_port avalon_slave m_addr address Input 4 104 | add_interface_port avalon_slave m_read_data readdata Output 32 105 | add_interface_port avalon_slave m_read read_n Input 1 106 | add_interface_port avalon_slave m_write_data writedata Input 32 107 | add_interface_port avalon_slave m_write write_n Input 1 108 | set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 109 | set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 110 | set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 111 | set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 112 | 113 | 114 | # 115 | # connection point interrupt_sender 116 | # 117 | add_interface interrupt_sender interrupt end 118 | set_interface_property interrupt_sender associatedAddressablePoint avalon_slave 119 | set_interface_property interrupt_sender associatedClock clock 120 | set_interface_property interrupt_sender associatedReset clock_reset 121 | set_interface_property interrupt_sender ENABLED true 122 | 123 | add_interface_port interrupt_sender m_irq irq_n Output 1 124 | 125 | 126 | # 127 | # connection point cxd_cpu 128 | # 129 | add_interface cxd_cpu conduit end 130 | set_interface_property cxd_cpu associatedClock "" 131 | set_interface_property cxd_cpu associatedReset "" 132 | set_interface_property cxd_cpu ENABLED true 133 | 134 | add_interface_port cxd_cpu CLOK export Input 1 135 | add_interface_port cxd_cpu DATA export Input 1 136 | add_interface_port cxd_cpu XLAT export Input 1 137 | 138 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545_DATAOUT.v: -------------------------------------------------------------------------------- 1 | // CXD2545_DATAOUT.v 2 | 3 | // This file was auto-generated as a prototype implementation of a module 4 | // created in component editor. It ties off all outputs to ground and 5 | // ignores all inputs. It needs to be edited to make it do something 6 | // useful. 7 | // 8 | // This file will not be automatically regenerated. You should check it in 9 | // to your version control system if you want to keep it. 10 | 11 | `timescale 1 ps / 1 ps 12 | module CXD2545_DATAOUT ( 13 | input wire clk, // clock_sink.clk 14 | input wire rst_n, // .reset_n 15 | input wire [3:0] addr, // avalon_slave.address 16 | output wire [31:0] read_data, // .readdata 17 | input wire [31:0] write_data, // .writedata 18 | input wire read_n, // .read_n 19 | input wire write_n, // .write_n 20 | output wire emph, // CXD_DATA.export 21 | output wire c2po, // .export 22 | input wire lrck, // .export 23 | input wire cdclk, // .export 24 | input wire cdlbit, // .export 25 | output wire cddat, // .export 26 | output wire scor, // CXD_SUBQ.export 27 | input wire sqck, // .export 28 | output wire sqso, // .export 29 | output wire irq_n // irq.irq_n 30 | ); 31 | 32 | // TODO: Auto-generated HDL template 33 | 34 | parameter DIV_REG = 4'h0; 35 | parameter FIFO_REG = 4'h1; 36 | parameter FIFO_READ = 4'h2; 37 | parameter FIFO_RESET = 4'h3; 38 | 39 | reg [31:0] out; 40 | assign read_data = out; 41 | reg cddat_reg; 42 | //assign cdclk = 1'b0; 43 | //assign lrck = 1'b0; 44 | assign cddat = cddat_reg; 45 | 46 | assign c2po = 1'b0; 47 | assign emph = 1'b0; 48 | 49 | assign sqso = sqso_reg; 50 | assign scor = scor_reg; 51 | 52 | reg [31:0] clk_divisor; 53 | reg [31:0] clk_counter; 54 | reg [6:0] lrclk_div; 55 | 56 | reg [31:0] cd_data; 57 | 58 | reg clk_bit; 59 | reg clk_lr; 60 | 61 | /*assign cdclk = clk_bit; 62 | assign lrck = clk_lr;*/ 63 | 64 | reg wrreq_sig, rdreq_sig; 65 | wire empty_sig, full_sig; 66 | wire [6:0] wrusedw_sig; 67 | wire [31:0] q_sig; 68 | wire [6:0] usedw_sig; 69 | reg fifo_reset; 70 | 71 | reg err_seq, err_out; 72 | 73 | assign irq_n = ~err_out; 74 | 75 | fifo fifo_inst ( 76 | .clock ( clk ), 77 | .data ( write_data ), 78 | .rdreq ( rdreq_sig ), 79 | .sclr ( fifo_reset ), 80 | .wrreq ( wrreq_sig ), 81 | .empty ( empty_sig ), 82 | .full ( full_sig ), 83 | //.usedw_sig(usedw_sig), 84 | .q ( q_sig ) 85 | ); 86 | 87 | always @(negedge clk) begin 88 | wrreq_sig <= 1'b0; 89 | fifo_reset <= 1'b0; 90 | if(err_seq == 1'b1) begin 91 | err_out <= 1'b1; 92 | end 93 | 94 | if(write_n == 1'b0) begin 95 | case(addr) 96 | DIV_REG: clk_divisor <= write_data; 97 | FIFO_REG: begin 98 | wrreq_sig <= 1'b1; 99 | end 100 | 2: begin 101 | //cd_data <= write_data; 102 | end 103 | FIFO_RESET: begin 104 | fifo_reset <= 1'b1; 105 | end 106 | endcase 107 | end 108 | 109 | if(read_n == 1'b0) begin 110 | case(addr) 111 | 5: begin 112 | err_out <= 0; 113 | end 114 | 115 | FIFO_REG: begin 116 | out <= {29'h0000000, err_out, empty_sig, full_sig}; 117 | end 118 | 119 | 3: begin 120 | out <= cddata[31:0]; 121 | end 122 | 123 | 4: begin 124 | out <= cddata[47:41]; 125 | end 126 | 127 | 128 | 129 | default: begin 130 | out <= {32'hdeadbeef}; 131 | end 132 | endcase 133 | end 134 | end 135 | 136 | 137 | reg [47:0] cddata; 138 | reg [31:0] ff_read; 139 | reg [7:0] state; 140 | reg [97:0] q_subchan; 141 | reg [97:0] q_subchan_buff; 142 | reg [6:0] q_cnt_read; 143 | reg [6:0] q_cnt; 144 | reg [4:0] byte_cnt; 145 | 146 | reg prev_cdlbit, cur_cdlbit; 147 | reg prev_cdclk, cur_cdclk; 148 | reg [5:0] cddatbit_cnt; 149 | 150 | reg cddata_ready; 151 | reg scor_reg; 152 | reg sqso_reg; 153 | reg sub_q_prep; 154 | reg sqck_reg, sqck_reg_prev; 155 | reg fifo_ready; 156 | 157 | always @(negedge clk) begin 158 | //scor_reg <= (q_cnt == 7'h61) ? 1 : 0; 159 | err_seq <= 1'h0; 160 | 161 | if((full_sig == 1'b1) && (fifo_reset == 1'b0)) begin 162 | fifo_ready = 1'b1; 163 | end 164 | 165 | if(fifo_reset == 1'b0) begin 166 | if((cddata_ready == 1'b0) && (fifo_ready == 1'b1))begin 167 | rdreq_sig <= 1'b1; 168 | end 169 | 170 | if(rdreq_sig == 1'b1) begin 171 | if(byte_cnt == 0) begin 172 | q_subchan[q_cnt] <= q_sig[6]; 173 | err_seq <= ((q_sig & 32'hFFFFFFBF) != 0); 174 | 175 | if(q_cnt > 0) begin 176 | q_cnt <= q_cnt - 1'b1; 177 | end else begin 178 | q_cnt <= 7'h61; 179 | scor_reg <= 1'b1; 180 | 181 | if(sub_q_prep == 1'b1) begin 182 | sqso_reg <= 1'b1; 183 | q_subchan_buff <= q_subchan; 184 | q_cnt_read <= 8'h60; 185 | end else begin 186 | sqso_reg <= 1'b0; 187 | end 188 | end 189 | 190 | end else begin 191 | cd_data <= q_sig; 192 | cddata_ready <= 1'b1; 193 | end 194 | 195 | if(byte_cnt < 6) begin 196 | byte_cnt <= byte_cnt + 1'b1; 197 | end else begin 198 | byte_cnt <= 5'h00; 199 | sub_q_prep <= 1'b1; 200 | end 201 | rdreq_sig <= 1'b0; 202 | end 203 | 204 | 205 | cur_cdlbit <= cdlbit; 206 | prev_cdlbit <= cur_cdlbit; 207 | if((prev_cdlbit == 1'b0) && (cur_cdlbit == 1'b1)) begin 208 | if(cddata_ready == 1'b1) begin 209 | cddata <= { cd_data[31], cd_data[31], cd_data[31], cd_data[31], cd_data[31], cd_data[31], cd_data[31], cd_data[31], cd_data[31:16], 210 | cd_data[15], cd_data[15], cd_data[15], cd_data[15], cd_data[15], cd_data[15], cd_data[15], cd_data[15], cd_data[15:0] 211 | }; 212 | cddata_ready <= 1'b0; 213 | end else begin 214 | fifo_ready <= 1'b0; 215 | q_cnt <= 8'h61; 216 | q_cnt_read <= 8'h60; 217 | byte_cnt <= 1'b0; 218 | sub_q_prep <= 1'b0; 219 | //cddata <= 48'h001BAD00B001; 220 | cddata <= 48'h000000000000; 221 | end; 222 | cddatbit_cnt <= 47; 223 | end 224 | 225 | 226 | 227 | cur_cdclk <= cdclk; 228 | prev_cdclk <= cur_cdclk; 229 | 230 | if((prev_cdclk == 1'b1) && (cur_cdclk == 1'b0) && (scor_reg == 1'b1)) begin 231 | scor_reg <= 1'b0; 232 | end 233 | 234 | if((prev_cdclk == 1'b1) && (cur_cdclk == 1'b0)) begin 235 | 236 | cddat_reg <= cddata[cddatbit_cnt]; 237 | if(cddatbit_cnt > 0) begin 238 | cddatbit_cnt <= cddatbit_cnt - 1'b1; 239 | end 240 | end 241 | 242 | sqck_reg <= sqck; 243 | sqck_reg_prev <= sqck_reg; 244 | if((sqck_reg_prev == 1'b1) && (sqck_reg == 1'b0)) begin 245 | if(q_cnt_read > 0) begin 246 | sqso_reg <= q_subchan_buff[q_cnt_read - 1]; 247 | q_cnt_read <= q_cnt_read - 1'b1; 248 | end else begin 249 | sqso_reg <= 1'b0; 250 | sub_q_prep <= 1'b0; 251 | end 252 | end 253 | 254 | end else begin 255 | q_cnt <= 8'h61; 256 | q_cnt_read <= 8'h60; 257 | byte_cnt <= 1'b0; 258 | sub_q_prep <= 1'b0; 259 | cddata <= 48'h001BAD00B001; 260 | sqso_reg <= 1'b0; 261 | q_subchan_buff <= 0; 262 | cddata_ready <= 1'b0; 263 | fifo_ready <= 1'b0; 264 | end 265 | 266 | end 267 | 268 | 269 | endmodule 270 | -------------------------------------------------------------------------------- /FPGA/Cores/CXD2545_DATAOUT_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 12.1sp1 2 | # Wed Jan 30 20:32:07 GMT+03:00 2019 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # CXD2545_DATAOUT "CXD2545_DATAOUT" v1.0 8 | # VBKesha 2019.01.30.20:32:07 9 | # 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 11.0 14 | # 15 | package require -exact sopc 11.0 16 | 17 | 18 | # 19 | # module CXD2545_DATAOUT 20 | # 21 | set_module_property NAME CXD2545_DATAOUT 22 | set_module_property VERSION 1.0 23 | set_module_property INTERNAL false 24 | set_module_property OPAQUE_ADDRESS_MAP true 25 | set_module_property GROUP Interfaces 26 | set_module_property AUTHOR VBKesha 27 | set_module_property DISPLAY_NAME CXD2545_DATAOUT 28 | set_module_property TOP_LEVEL_HDL_FILE CXD2545_DATAOUT.v 29 | set_module_property TOP_LEVEL_HDL_MODULE CXD2545_DATAOUT 30 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 31 | set_module_property EDITABLE true 32 | set_module_property ANALYZE_HDL AUTO 33 | set_module_property STATIC_TOP_LEVEL_MODULE_NAME CXD2545_DATAOUT 34 | set_module_property FIX_110_VIP_PATH false 35 | set_module_property REPORT_TO_TALKBACK false 36 | set_module_property ALLOW_GREYBOX_GENERATION false 37 | 38 | 39 | # 40 | # files 41 | # 42 | add_file CXD2545_DATAOUT.v {SYNTHESIS SIMULATION} 43 | 44 | 45 | # 46 | # file sets 47 | # 48 | 49 | # 50 | # parameters 51 | # 52 | add_parameter DIV_REG STD_LOGIC_VECTOR 0 53 | set_parameter_property DIV_REG DEFAULT_VALUE 0 54 | set_parameter_property DIV_REG DISPLAY_NAME DIV_REG 55 | set_parameter_property DIV_REG TYPE STD_LOGIC_VECTOR 56 | set_parameter_property DIV_REG UNITS None 57 | set_parameter_property DIV_REG ALLOWED_RANGES 0:31 58 | set_parameter_property DIV_REG HDL_PARAMETER true 59 | add_parameter FIFO_REG STD_LOGIC_VECTOR 1 60 | set_parameter_property FIFO_REG DEFAULT_VALUE 1 61 | set_parameter_property FIFO_REG DISPLAY_NAME FIFO_REG 62 | set_parameter_property FIFO_REG TYPE STD_LOGIC_VECTOR 63 | set_parameter_property FIFO_REG UNITS None 64 | set_parameter_property FIFO_REG ALLOWED_RANGES 0:31 65 | set_parameter_property FIFO_REG HDL_PARAMETER true 66 | add_parameter FIFO_READ STD_LOGIC_VECTOR 2 67 | set_parameter_property FIFO_READ DEFAULT_VALUE 2 68 | set_parameter_property FIFO_READ DISPLAY_NAME FIFO_READ 69 | set_parameter_property FIFO_READ TYPE STD_LOGIC_VECTOR 70 | set_parameter_property FIFO_READ UNITS None 71 | set_parameter_property FIFO_READ ALLOWED_RANGES 0:31 72 | set_parameter_property FIFO_READ HDL_PARAMETER true 73 | 74 | 75 | # 76 | # display items 77 | # 78 | 79 | 80 | # 81 | # connection point clock_sink 82 | # 83 | add_interface clock_sink clock end 84 | set_interface_property clock_sink clockRate 0 85 | set_interface_property clock_sink ENABLED true 86 | 87 | add_interface_port clock_sink clk clk Input 1 88 | 89 | 90 | # 91 | # connection point clock_sink_reset 92 | # 93 | add_interface clock_sink_reset reset end 94 | set_interface_property clock_sink_reset associatedClock clock_sink 95 | set_interface_property clock_sink_reset synchronousEdges DEASSERT 96 | set_interface_property clock_sink_reset ENABLED true 97 | 98 | add_interface_port clock_sink_reset rst_n reset_n Input 1 99 | 100 | 101 | # 102 | # connection point avalon_slave 103 | # 104 | add_interface avalon_slave avalon end 105 | set_interface_property avalon_slave addressAlignment DYNAMIC 106 | set_interface_property avalon_slave addressUnits WORDS 107 | set_interface_property avalon_slave associatedClock clock_sink 108 | set_interface_property avalon_slave associatedReset clock_sink_reset 109 | set_interface_property avalon_slave burstOnBurstBoundariesOnly false 110 | set_interface_property avalon_slave explicitAddressSpan 0 111 | set_interface_property avalon_slave holdTime 0 112 | set_interface_property avalon_slave isMemoryDevice false 113 | set_interface_property avalon_slave isNonVolatileStorage false 114 | set_interface_property avalon_slave linewrapBursts false 115 | set_interface_property avalon_slave maximumPendingReadTransactions 0 116 | set_interface_property avalon_slave printableDevice false 117 | set_interface_property avalon_slave readLatency 0 118 | set_interface_property avalon_slave readWaitTime 1 119 | set_interface_property avalon_slave setupTime 0 120 | set_interface_property avalon_slave timingUnits Cycles 121 | set_interface_property avalon_slave writeWaitTime 0 122 | set_interface_property avalon_slave ENABLED true 123 | 124 | add_interface_port avalon_slave addr address Input 4 125 | add_interface_port avalon_slave read_data readdata Output 32 126 | add_interface_port avalon_slave write_data writedata Input 32 127 | add_interface_port avalon_slave read_n read_n Input 1 128 | add_interface_port avalon_slave write_n write_n Input 1 129 | set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 130 | set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 131 | set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 132 | set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 133 | 134 | 135 | # 136 | # connection point CXD_DATA 137 | # 138 | add_interface CXD_DATA conduit end 139 | set_interface_property CXD_DATA associatedClock "" 140 | set_interface_property CXD_DATA associatedReset "" 141 | set_interface_property CXD_DATA ENABLED true 142 | 143 | add_interface_port CXD_DATA emph export Output 1 144 | add_interface_port CXD_DATA c2po export Output 1 145 | add_interface_port CXD_DATA lrck export Input 1 146 | add_interface_port CXD_DATA cddat export Output 1 147 | add_interface_port CXD_DATA cdlbit export Input 1 148 | add_interface_port CXD_DATA cdclk export Input 1 149 | 150 | 151 | # 152 | # connection point CXD_SUBQ 153 | # 154 | add_interface CXD_SUBQ conduit end 155 | set_interface_property CXD_SUBQ associatedClock "" 156 | set_interface_property CXD_SUBQ associatedReset "" 157 | set_interface_property CXD_SUBQ ENABLED true 158 | 159 | add_interface_port CXD_SUBQ scor export Output 1 160 | add_interface_port CXD_SUBQ sqck export Input 1 161 | add_interface_port CXD_SUBQ sqso export Output 1 162 | 163 | 164 | # 165 | # connection point irq 166 | # 167 | add_interface irq interrupt end 168 | set_interface_property irq associatedAddressablePoint avalon_slave 169 | set_interface_property irq associatedClock clock_sink 170 | set_interface_property irq associatedReset clock_sink_reset 171 | set_interface_property irq ENABLED true 172 | 173 | add_interface_port irq irq_n irq_n Output 1 174 | 175 | -------------------------------------------------------------------------------- /FPGA/Cores/avalon_st_drainer.v: -------------------------------------------------------------------------------- 1 | // avalon_st_drainer.v 2 | 3 | // This file was auto-generated as a prototype implementation of a module 4 | // created in component editor. It ties off all outputs to ground and 5 | // ignores all inputs. It needs to be edited to make it do something 6 | // useful. 7 | // 8 | // This file will not be automatically regenerated. You should check it in 9 | // to your version control system if you want to keep it. 10 | 11 | `timescale 1 ps / 1 ps 12 | module avalon_st_drainer ( 13 | input wire clk, // clock.clk 14 | input wire reset, // reset_sink.reset_n 15 | 16 | output wire out_valid, // out.valid 17 | output wire out_sof, // .startofpacket 18 | output wire out_eof, // .endofpacket 19 | output wire [31:0] out_data, // .data 20 | output wire [1:0] out_empty, // .empty 21 | input wire out_ready, // .ready 22 | 23 | input wire in_valid, // in.valid 24 | input wire in_sof, // .startofpacket 25 | input wire in_eof, // .endofpacket 26 | input wire [31:0] in_data, // .data 27 | input wire [1:0] in_empty, // .empty 28 | output wire in_ready, // .ready 29 | input wire drain // conduit_end.export 30 | ); 31 | 32 | 33 | assign out_eof = (lock_drain == 1'b0) ? in_eof : 1'b0; 34 | assign out_valid = (lock_drain == 1'b0) ? in_valid : 1'b0; 35 | assign in_ready = ((drain == 1'b0) || (in_sof == 1'b1)) ? out_ready : 1'b1; 36 | assign out_sof = in_sof; 37 | assign out_empty = in_empty; 38 | assign out_data = in_data; 39 | 40 | 41 | reg lock_drain; 42 | 43 | always @(negedge clk) begin 44 | if(drain == 1'b1) begin 45 | lock_drain <= 1'b1; 46 | end else begin 47 | if(in_sof == 1'b1) begin 48 | lock_drain <= 1'b0; 49 | end 50 | end 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /FPGA/Cores/avalon_st_drainer_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 12.1sp1 2 | # Sun Mar 21 12:15:46 MSK 2021 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # avalon_st_drainer "Avalon-ST Drainer" v1.0 8 | # VBKesha 2021.03.21.12:15:46 9 | # Avalon-ST Packet Drainer 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 11.0 14 | # 15 | package require -exact sopc 11.0 16 | 17 | 18 | # 19 | # module avalon_st_drainer 20 | # 21 | set_module_property DESCRIPTION "Avalon-ST Packet Drainer" 22 | set_module_property NAME avalon_st_drainer 23 | set_module_property VERSION 1.0 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property GROUP "Bridges and Adapters/Streaming" 27 | set_module_property AUTHOR VBKesha 28 | set_module_property DISPLAY_NAME "Avalon-ST Drainer" 29 | set_module_property TOP_LEVEL_HDL_FILE avalon_st_drainer.v 30 | set_module_property TOP_LEVEL_HDL_MODULE avalon_st_drainer 31 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 32 | set_module_property EDITABLE true 33 | set_module_property ANALYZE_HDL AUTO 34 | set_module_property STATIC_TOP_LEVEL_MODULE_NAME avalon_st_drainer 35 | set_module_property FIX_110_VIP_PATH false 36 | set_module_property REPORT_TO_TALKBACK false 37 | set_module_property ALLOW_GREYBOX_GENERATION false 38 | 39 | 40 | # 41 | # files 42 | # 43 | add_file avalon_st_drainer.v {SYNTHESIS SIMULATION} 44 | 45 | 46 | # 47 | # file sets 48 | # 49 | 50 | # 51 | # parameters 52 | # 53 | 54 | 55 | # 56 | # display items 57 | # 58 | 59 | 60 | # 61 | # connection point clock 62 | # 63 | add_interface clock clock end 64 | set_interface_property clock clockRate 0 65 | set_interface_property clock ENABLED true 66 | 67 | add_interface_port clock clk clk Input 1 68 | 69 | 70 | # 71 | # connection point reset_sink 72 | # 73 | add_interface reset_sink reset end 74 | set_interface_property reset_sink associatedClock clock 75 | set_interface_property reset_sink synchronousEdges DEASSERT 76 | set_interface_property reset_sink ENABLED true 77 | 78 | add_interface_port reset_sink reset reset_n Input 1 79 | 80 | 81 | # 82 | # connection point in 83 | # 84 | add_interface in avalon_streaming end 85 | set_interface_property in associatedClock clock 86 | set_interface_property in associatedReset reset_sink 87 | set_interface_property in dataBitsPerSymbol 8 88 | set_interface_property in errorDescriptor "" 89 | set_interface_property in firstSymbolInHighOrderBits true 90 | set_interface_property in maxChannel 0 91 | set_interface_property in readyLatency 0 92 | set_interface_property in ENABLED true 93 | 94 | add_interface_port in in_valid valid Input 1 95 | add_interface_port in in_sof startofpacket Input 1 96 | add_interface_port in in_eof endofpacket Input 1 97 | add_interface_port in in_data data Input 32 98 | add_interface_port in in_empty empty Input 2 99 | add_interface_port in in_ready ready Output 1 100 | 101 | # 102 | # connection point out 103 | # 104 | add_interface out avalon_streaming start 105 | set_interface_property out associatedClock clock 106 | set_interface_property out associatedReset reset_sink 107 | set_interface_property out dataBitsPerSymbol 8 108 | set_interface_property out errorDescriptor "" 109 | set_interface_property out firstSymbolInHighOrderBits true 110 | set_interface_property out maxChannel 0 111 | set_interface_property out readyLatency 0 112 | set_interface_property out ENABLED true 113 | 114 | add_interface_port out out_valid valid Output 1 115 | add_interface_port out out_sof startofpacket Output 1 116 | add_interface_port out out_eof endofpacket Output 1 117 | add_interface_port out out_data data Output 32 118 | add_interface_port out out_empty empty Output 2 119 | add_interface_port out out_ready ready Input 1 120 | 121 | 122 | # 123 | # connection point control 124 | # 125 | add_interface control conduit end 126 | set_interface_property control associatedClock clock 127 | set_interface_property control associatedReset "" 128 | set_interface_property control ENABLED true 129 | 130 | add_interface_port control drain export Input 1 131 | 132 | -------------------------------------------------------------------------------- /FPGA/Modules/CXD2545_CLKGEN.v: -------------------------------------------------------------------------------- 1 | module CXD2545_CLKGEN( 2 | input clk, 3 | output reg cdr_dat, 4 | output reg cdr_lr, 5 | output reg cdr_lbit 6 | ); 7 | 8 | reg [7:0] cnt; 9 | 10 | always @(negedge clk) begin 11 | 12 | if(cnt < 95) begin 13 | cnt <= cnt + 1'b1; 14 | end else begin 15 | cnt <= 0; 16 | end 17 | 18 | cdr_lr <= (cnt < 48) ? 1'b1 : 1'b0; 19 | cdr_lbit <= (cnt == 95); 20 | cdr_dat <= cnt[0]; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /FPGA/Modules/CXD2545_SENS.v: -------------------------------------------------------------------------------- 1 | module CXD2545_SENS( 2 | input sclk, 3 | 4 | input clk, 5 | input data, 6 | input xlat, 7 | 8 | input [15:0] sens_data, 9 | 10 | output reg sens 11 | ); 12 | 13 | reg [3:0] cnt; 14 | reg [7:0] shift_reg; 15 | reg [3:0] select_reg; 16 | 17 | reg prev_clk; 18 | reg prev_xlat; 19 | /* 20 | always @(posedge sclk or negedge xlat) begin 21 | 22 | if(xlat == 1'b0) begin 23 | cnt <= 0; 24 | shift_reg[7:0] <= 0; 25 | end else begin 26 | if((prev_clk == 1'b0) && (clk == 1'b1)) begin 27 | shift_reg[7:0] <= {data, shift_reg[7:1]}; 28 | if(cnt < 7) begin 29 | cnt <= cnt + 1'b1; 30 | end else begin 31 | select_reg <= {data, shift_reg[7:5]}; 32 | cnt <= 0; 33 | end 34 | end 35 | 36 | prev_clk <= clk; 37 | sens <= sens_data[select_reg]; 38 | end 39 | 40 | end 41 | */ 42 | /* 43 | always @(posedge clk or negedge xlat) begin 44 | if(xlat == 1'b0) begin 45 | cnt <= 0; 46 | shift_reg[7:0] <= 0; 47 | end else begin 48 | shift_reg[7:0] <= {data, shift_reg[7:1]}; 49 | if(cnt < 7) begin 50 | cnt <= cnt + 1'b1; 51 | end else begin 52 | select_reg <= {data, shift_reg[7:5]}; 53 | cnt <= 0; 54 | end 55 | end 56 | end 57 | 58 | assign sens = sens_data[select_reg]; 59 | */ 60 | 61 | always @(posedge sclk) begin 62 | 63 | if((prev_xlat == 1'b1) && (xlat == 1'b0)) begin 64 | cnt <= 0; 65 | shift_reg[7:0] <= 0; 66 | end else begin 67 | if((prev_clk == 1'b0) && (clk == 1'b1)) begin 68 | shift_reg[7:0] <= {data, shift_reg[7:1]}; 69 | if(cnt < 7) begin 70 | cnt <= cnt + 1'b1; 71 | end else begin 72 | select_reg <= {data, shift_reg[7:5]}; 73 | cnt <= 0; 74 | end 75 | end 76 | 77 | end 78 | 79 | prev_xlat <= xlat; 80 | prev_clk <= clk; 81 | sens <= sens_data[select_reg]; 82 | 83 | end 84 | 85 | endmodule -------------------------------------------------------------------------------- /FPGA/Modules/CXD2545_SOCT.v: -------------------------------------------------------------------------------- 1 | module CXD2545_SOCT( 2 | input sclk, 3 | input xlat, 4 | 5 | input [7:0] PER, 6 | input [2:0] C1, 7 | input [2:0] C2, 8 | input FOK, 9 | input GFS, 10 | input LOCK, 11 | input EMPH, 12 | 13 | input clk, 14 | output reg out 15 | ); 16 | 17 | reg [16:0] soct; 18 | reg prev_xlat; 19 | reg prev_clk; 20 | 21 | /* 22 | always @(posedge sclk or negedge xlat) begin 23 | if(xlat == 1'b0) begin 24 | soct <= {PER[0], PER[1], PER[2], PER[3], PER[4], PER[5], PER[6], PER[7], 25 | C1[2:0], C2[2:0], FOK, GFS, LOCK, EMPH}; 26 | end else begin 27 | if((prev_clk == 1'b1) && (clk == 1'b0)) begin 28 | // out <= soct[16]; 29 | soct <= {soct[16:0], 1'b0}; 30 | end 31 | 32 | prev_clk <= clk; 33 | out <= soct[17]; 34 | end 35 | end 36 | */ 37 | 38 | always @(posedge sclk) begin 39 | if((prev_xlat == 1'b1) && (xlat == 1'b0)) begin 40 | soct <= {PER[1], PER[2], PER[3], PER[4], PER[5], PER[6], PER[7], 41 | C1[2:0], C2[2:0], FOK, GFS, LOCK, EMPH}; 42 | out <= PER[0]; 43 | end 44 | 45 | if((clk == 1'b0) && (prev_clk == 1'b1)) begin 46 | soct <= {soct[15:0], 1'b0}; 47 | out <= soct[16]; 48 | end 49 | 50 | //out <= soct[17]; 51 | prev_clk <= clk; 52 | prev_xlat <= xlat; 53 | 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /FPGA/Modules/CXD2545_TRACK_COUNTER.v: -------------------------------------------------------------------------------- 1 | module CXD2545_TRACK_COUNTER( 2 | input clk, 3 | input [15:0] div, 4 | input [15:0] toggle_cnt, 5 | input trigger, 6 | 7 | output reg toggle_clk, 8 | output reg [31:0] track_count 9 | ); 10 | 11 | reg [32:0] cnt_50; 12 | reg [32:0] cnt_div_50; 13 | reg prev_trigger; 14 | reg [30:0] trc_cnt; 15 | 16 | 17 | reg trk_clk; 18 | 19 | always @(posedge clk) begin 20 | if(cnt_50 < div) begin 21 | cnt_50 <= cnt_50 + 1'b1; 22 | end else begin 23 | cnt_50 <= 0; 24 | trk_clk <= ~trk_clk; 25 | 26 | if(cnt_div_50 < 256) begin 27 | cnt_div_50 <= cnt_div_50 + 1'b1; 28 | end else begin 29 | cnt_div_50 <= 0; 30 | toggle_clk <= ~toggle_clk; 31 | end 32 | 33 | if((prev_trigger == 1'b1) && (trigger == 1'b0)) begin 34 | track_count <= {1'b1, trc_cnt}; 35 | end else if((prev_trigger == 1'b0) && (trigger == 1'b1)) begin 36 | trc_cnt <= 0; 37 | track_count <= 0; 38 | end else begin 39 | trc_cnt <= trc_cnt + 1'b1; 40 | end 41 | 42 | 43 | prev_trigger <= trigger; 44 | end 45 | end 46 | 47 | 48 | 49 | /* 50 | always @(posedge trk_clk) begin 51 | if(cnt_div_50 < 256) begin 52 | cnt_div_50 <= cnt_div_50 + 1'b1; 53 | end else begin 54 | cnt_div_50 <= 0; 55 | toggle_clk <= ~toggle_clk; 56 | end 57 | 58 | if((prev_trigger == 1'b1) && (trigger == 1'b0)) begin 59 | track_count <= trc_cnt; 60 | end else if((prev_trigger == 1'b0) && (trigger == 1'b1)) begin 61 | trc_cnt <= 0; 62 | end else begin 63 | trc_cnt <= trc_cnt + 1'b1; 64 | end 65 | 66 | 67 | prev_trigger <= trigger; 68 | end*/ 69 | 70 | endmodule -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/cxd2545_cpu/cxd2545_cpu.c: -------------------------------------------------------------------------------- 1 | /* 2 | * cxd2545_cpu.c 3 | * 4 | * Created on: 07.09.2020 5 | * Author: VBKesha 6 | */ 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | 13 | #include "cxd2545.h" 14 | #include "cxd2545_ctrl.h" 15 | #include "sens_ctrl.h" 16 | 17 | static const uint32_t cxd2545_cpu_addr = CXD2545_CPU_0_BASE; 18 | static const uint32_t cxd2545_cpu_int_num = CXD2545_CPU_0_IRQ; 19 | 20 | #define CXD2545_CPU_CMD_REG (0x00) 21 | #define CXD2545_CPU_IRQ_CLR (0x04) 22 | 23 | 24 | static uint8_t dir = 0; 25 | static uint8_t sled_work = 0; 26 | static uint8_t prev_dir = 0; 27 | static uint8_t sled_break = 0; 28 | 29 | static enum CXD2545_STATES prev_state; 30 | 31 | static void cxd2545_cpu_isr(void * in, uint32_t id){ 32 | cxd2545_cmd command; 33 | uint32_t scount; 34 | 35 | command.raw = IORD_32DIRECT(cxd2545_cpu_addr, CXD2545_CPU_CMD_REG); 36 | IORD_32DIRECT(cxd2545_cpu_addr, CXD2545_CPU_IRQ_CLR); 37 | 38 | switch(command.cmd.id){ 39 | case CXD2545_CMD_TRACKING_MODE: 40 | cxd2545_dma_drain_on(); 41 | 42 | if(sled_work == 1){ 43 | cxd2545_track_counter_stop(); 44 | printf("%c", (dir == 0) ? '+' : '-'); 45 | do{ 46 | scount = IORD(TRACK_COUNTER_BASE, 0); 47 | } while((scount & 0x80000000) == 0); 48 | 49 | scount &= 0x7FFFFFFF; 50 | 51 | if((sled_break == 0) || (prev_dir == dir)){ 52 | cxd2545_change_sector(scount & 0x7FFFFFFF, dir); 53 | } 54 | sled_work = 0; 55 | sled_break = 1; 56 | prev_dir = dir; 57 | } 58 | 59 | switch(command.tracking_mode.sled){ 60 | case SLED_FORWARD: 61 | cxd2545_set_state(CXD_2545_IDLE); 62 | cxd2545_track_counter_start(); 63 | dir = 0; 64 | sled_work = 1; 65 | prev_state = cxd2545_get_state(); 66 | cxd2545_set_state(CXD_2545_IDLE); 67 | break; 68 | 69 | case SLED_REVERSE: 70 | cxd2545_set_state(CXD_2545_IDLE); 71 | cxd2545_track_counter_start(); 72 | dir = 1; 73 | sled_work = 1; 74 | prev_state = cxd2545_get_state(); 75 | cxd2545_set_state(CXD_2545_IDLE); 76 | break; 77 | } 78 | 79 | break; 80 | 81 | 82 | case CXD2545_CMD_AUTO_SEQUENCE: 83 | cxd2545_dma_drain_on(); 84 | cxd2545_set_state(CXD_2545_IDLE); 85 | 86 | switch(command.aseq_cmd.cmd){ 87 | case ASEQ_CMD_CANCEL: 88 | sens_XBUSY_on(); 89 | break; 90 | 91 | case ASEQ_CMD_FINE_SEARCH: 92 | break; 93 | 94 | 95 | case ASEQ_CMD_FOCUS_ON: 96 | sens_FOK_on(); 97 | sens_XBUSY_on(); 98 | break; 99 | 100 | 101 | case ASEQ_CMD_1TRK_JUMP: 102 | cxd2545_change_sector(1, command.aseq_cmd.dir); 103 | break; 104 | 105 | case ASEQ_CMD_10TRK_JUMP: 106 | cxd2545_change_sector(10, command.aseq_cmd.dir); 107 | break; 108 | 109 | 110 | case ASEQ_CMD_2NTRK_JUMP: 111 | cxd2545_change_sector(cxd2545_get_asq_jump() * 2, command.aseq_cmd.dir); 112 | break; 113 | 114 | case ASEQ_CMD_MTRK_JUMP: 115 | cxd2545_change_sector(cxd2545_get_asq_jump(), command.aseq_cmd.dir); 116 | break; 117 | 118 | } 119 | break; 120 | 121 | case CXD2545_CMD_ASEQ_TRACK_COUNT: 122 | cxd2545_set_asq_jump(command.aseq_track_count.count); 123 | break; 124 | 125 | case CXD2545_CMD_MODE_SPECIFICATION: 126 | cxd2545_set_soct(command.mode_specification.SOCT); 127 | break; 128 | 129 | case CXD2545_CMD_FUNCTION_SPECIFICATION: 130 | cxd2545_set_cd_speed(command.function_specification.DSPB); 131 | break; 132 | 133 | case CXD2545_CMD_CLV_MODE: 134 | sled_break = 0; 135 | switch(command.clv_mode.mode){ 136 | case CLV_MODE_STOP: 137 | case CLV_MODE_BRAKE: 138 | cxd2545_dma_drain_on(); 139 | cxd2545_set_state(CXD_2545_IDLE); 140 | printf("T"); 141 | break; 142 | 143 | case CLV_MODE_KICK: 144 | printf("K"); 145 | break; 146 | 147 | 148 | case CLV_MODE_CLVS: 149 | case CLV_MODE_CLVH: 150 | case CLV_MODE_CLVP: 151 | case CLV_MODE_CLVA: 152 | if(cxd2545_servo_valid() != 0){ 153 | cxd2545_set_state(CXD_2545_WAITDATA); 154 | printf("S"); 155 | } else { 156 | printf("E"); 157 | } 158 | break; 159 | } 160 | break; 161 | } 162 | } 163 | 164 | void cxd2545_cpu_init(){ 165 | alt_irq_register(cxd2545_cpu_int_num, NULL, cxd2545_cpu_isr); 166 | alt_irq_enable(cxd2545_cpu_int_num); 167 | 168 | sled_work = 0; 169 | } 170 | -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/sdcard_spi/sdcard_spi.c: -------------------------------------------------------------------------------- 1 | /* 2 | * sdcard_spi.c 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include "sdcard_spi.h" 14 | #include 15 | #include "display.h" 16 | 17 | //#define DEBUG 18 | #include 19 | 20 | static uint8_t stub[8]; 21 | static uint8_t wait = 0xFF; 22 | static uint8_t wait_ret[4]; 23 | 24 | int nios_spi32_wr(const uint32_t base, const uint32_t slave, const uint32_t write_length, const uint8_t * write_data, const uint32_t read_length, uint8_t * read_data, const uint32_t flags); 25 | 26 | #define spi_wr nios_spi32_wr 27 | 28 | uint8_t sdcard_init(sdcard_inst * inst, uint32_t spi_addr){ 29 | uint16_t count; 30 | inst->spi_base_addr = spi_addr; 31 | dbg_printf("Start sdcard init\r\n"); 32 | 33 | count = 0; 34 | do{ 35 | dbg_printf("X\r\n"); 36 | sdcard_warmup(inst); 37 | dbg_printf("Y\r\n"); 38 | sdcard_send_cmd(inst, 0, 0, 0x95, 1, 0); 39 | dbg_printf("RET: %02X\r\n", inst->ret_buff[0]); 40 | count++; 41 | if(count > 254){ 42 | diaplay_sd_err(1); 43 | while(1){} 44 | } 45 | } while(inst->ret_buff[0] != 0x01); 46 | 47 | sdcard_send_cmd(inst, 8, 0x1AA, 0x87, 5, 0); 48 | 49 | count = 0; 50 | do{ 51 | sdcard_send_cmd(inst, 55, 0x0, 0x0, 1, 0); 52 | dbg_printf("RET55: %02X\r\n", inst->ret_buff[0]); 53 | sdcard_send_cmd(inst, 41, 0x40000000, 0x77, 1, 0); 54 | dbg_printf("RETA41: %02X\r\n", inst->ret_buff[0]); 55 | count++; 56 | if(count > 8192){ 57 | diaplay_sd_err(2); 58 | while(1){} 59 | } 60 | }while(inst->ret_buff[0] != 0); 61 | 62 | dbg_printf("Sdcard Inited\r\n"); 63 | inst->state = SDCARD_IDLE; 64 | 65 | return 0; 66 | }; 67 | 68 | 69 | uint8_t sdcard_read_sector(sdcard_inst * inst, uint32_t sector, uint8_t * buff){ 70 | dbg_printf("START READ SECTOR\r\n"); 71 | if((inst->state == SDCARD_READ_SECTOR) && (inst->cur_sector != sector)){ 72 | dbg_printf("Stop previous read\r\n"); 73 | sdcard_stop_read(inst); 74 | } 75 | 76 | if(inst->state == SDCARD_IDLE){ 77 | dbg_printf("Send read command\r\n"); 78 | sdcard_start_read(inst, sector); 79 | } 80 | dbg_printf("Get data from card\r\n"); 81 | sdcard_read_data(inst, buff); 82 | dbg_printf("STOP READ SECTOR\r\n"); 83 | return 0; 84 | } 85 | 86 | static void sdcard_warmup(sdcard_inst * inst){ 87 | memset(inst->cmd_buff, 0xFF, 8); 88 | spi_wr(inst->spi_base_addr, 1 /* Dirty hack for CS been up*/, 89 | 8, inst->cmd_buff, 90 | 0, stub, 0); 91 | spi_wr(inst->spi_base_addr, 1 /* Dirty hack for CS been up*/, 92 | 8, inst->cmd_buff, 93 | 0, stub, 0); 94 | 95 | } 96 | 97 | static void sdcard_send_cmd(sdcard_inst * inst, uint8_t cmd, uint32_t args, uint8_t crc, uint8_t resp_bytes, uint8_t hold_cs){ 98 | uint8_t dp, count; 99 | /*memset(inst->cmd_buff, 0xFF, 4); 100 | nios_spi_rw(inst->spi_base_addr, 0, 101 | 1, inst->cmd_buff, stub, ((hold_cs == 0) ? 0 : ALT_AVALON_SPI_COMMAND_MERGE));*/ 102 | inst->cmd_buff[0] = 0xFF; 103 | inst->cmd_buff[1] = 0xFF; 104 | 105 | inst->cmd_buff[2] = (SDCARD_CMD_START | (cmd & SDCARD_CMD_MSK)); 106 | inst->cmd_buff[3] = (args >> 24); 107 | inst->cmd_buff[4] = (args >> 16) & 0xFF; 108 | inst->cmd_buff[5] = (args >> 8) & 0xFF; 109 | inst->cmd_buff[6] = args & 0xFF; 110 | inst->cmd_buff[7] = crc | 1; 111 | 112 | spi_wr(inst->spi_base_addr, 0, 113 | 8, inst->cmd_buff, 114 | 0, stub, ALT_AVALON_SPI_COMMAND_MERGE); 115 | 116 | count = 0; 117 | do{ 118 | spi_wr(inst->spi_base_addr, 0, 119 | 0, &wait, 120 | 1, wait_ret, ALT_AVALON_SPI_COMMAND_MERGE); 121 | count++; 122 | if(count > 254){ 123 | diaplay_sd_err(3); 124 | while(1){} 125 | } 126 | } while(wait_ret[0] == 0xFF); 127 | 128 | dp = 0; 129 | inst->ret_buff[dp] = wait_ret[0]; 130 | dp++; 131 | resp_bytes--; 132 | while(resp_bytes > 0) { 133 | spi_wr(inst->spi_base_addr, 0, 134 | 0, &wait, 135 | 1, wait_ret, ALT_AVALON_SPI_COMMAND_MERGE); 136 | inst->ret_buff[dp] = wait_ret[0]; 137 | dp++; 138 | resp_bytes--; 139 | }; 140 | 141 | IOWR_ALTERA_AVALON_SPI_CONTROL(inst->spi_base_addr, 0); 142 | } 143 | 144 | 145 | static void sdcard_start_read(sdcard_inst * inst, uint32_t sector){ 146 | sdcard_send_cmd(inst, 18, sector, 0xFF, 1, 1); 147 | inst->cur_sector = sector; 148 | inst->state = SDCARD_READ_SECTOR; 149 | inst->data_pos = 4; 150 | } 151 | 152 | static void sdcard_stop_read(sdcard_inst * inst){ 153 | inst->cmd_buff[0] = 0xFF; 154 | inst->cmd_buff[1] = 0xFF; 155 | inst->cmd_buff[2] = 0x40 | 12; 156 | inst->cmd_buff[3] = 0; 157 | inst->cmd_buff[4] = 0; 158 | inst->cmd_buff[5] = 0; 159 | inst->cmd_buff[6] = 0; 160 | inst->cmd_buff[7] = 1; 161 | 162 | spi_wr(inst->spi_base_addr, 0, 163 | 8, inst->cmd_buff, 164 | 1, inst->ret_buff, 0); 165 | inst->state = SDCARD_IDLE; 166 | } 167 | 168 | static void sdcard_read_data(sdcard_inst * inst, uint8_t * buff){ 169 | uint16_t i; 170 | dbg_printf("SDCARD_WAIT_DATA\r\n"); 171 | //printf("AI[%d]: %02X %02X %02X %02X\r\n", inst->data_pos, inst->ret_buff[0], inst->ret_buff[1], inst->ret_buff[2],inst->ret_buff[3]); 172 | 173 | do{ 174 | spi_wr(inst->spi_base_addr, 0, 175 | 0, inst->cmd_buff, 176 | 1, inst->ret_buff, ALT_AVALON_SPI_COMMAND_MERGE); 177 | } while(inst->ret_buff[0] != 0xFE); 178 | 179 | dbg_printf("SDCARD_READ_DATA\r\n"); 180 | i=0; 181 | //printf("OFFSET I: %d\r\n", i); 182 | spi_wr(inst->spi_base_addr, 0, 183 | 0, inst->cmd_buff, 184 | 512, buff, 185 | ALT_AVALON_SPI_COMMAND_MERGE); 186 | 187 | //dbg_printf("SDCARD_READ_CRC[%d]\r\n", offset); 188 | dbg_printf("OFFDATA: %02X %02X %02X %02X\r\n", inst->ret_buff[0], inst->ret_buff[1], inst->ret_buff[2], inst->ret_buff[3]); 189 | // printf("AW[%d]: %02X %02X %02X %02X --- ", inst->data_pos, inst->ret_buff[0], inst->ret_buff[1], inst->ret_buff[2],inst->ret_buff[3]); 190 | 191 | spi_wr(inst->spi_base_addr, 0, 192 | 0, inst->cmd_buff, 193 | 2, inst->ret_buff, ALT_AVALON_SPI_COMMAND_MERGE); 194 | 195 | /*for(i=0; i<4; i++){ 196 | printf("%02X ",inst->ret_buff[i]); 197 | } 198 | printf("\r\n Offset: %d, DP: %d\r\n", offset, inst->data_pos);*/ 199 | /*nios_spi_command(inst->spi_base_addr, 0,0, inst->cmd_buff, 200 | 2, inst->ret_buff, ALT_AVALON_SPI_COMMAND_MERGE);*/ 201 | inst->cur_sector++; 202 | } 203 | -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/sdcard_spi/sdcard_spi.h: -------------------------------------------------------------------------------- 1 | /* 2 | * sdcard_spi.h 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef SDCARD_SPI_H_ 9 | #define SDCARD_SPI_H_ 10 | 11 | #define SDCARD_CMD_START 0x40 12 | #define SDCARD_CMD_MSK 0x3F 13 | #define SDCARD_CMD_STOP 0x01 14 | 15 | enum SDCARD_STATE { 16 | SDCARD_IDLE, 17 | SDCARD_READ_SECTOR, 18 | }; 19 | 20 | static void sdcard_warmup(sdcard_inst * inst); 21 | static void sdcard_send_cmd(sdcard_inst * inst, uint8_t cmd, uint32_t args, uint8_t crc, uint8_t resp_bytes, uint8_t hold_cs); 22 | static void sdcard_start_read(sdcard_inst * inst, uint32_t sector); 23 | static void sdcard_stop_read(sdcard_inst * inst); 24 | static void sdcard_read_data(sdcard_inst * inst, uint8_t * buff); 25 | 26 | #endif /* SDCARD_SPI_H_ */ 27 | -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/sens_ctrl/sens_ctrl.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #include 5 | #include 6 | 7 | #define SENS_FCZ 0x0001 8 | #define SENS_AS 0x0002 9 | #define SENS_TZC 0x0004 10 | #define SENS_SSTP 0x0008 11 | #define SENS_XBUSY 0x0010 12 | #define SENS_FOK 0x0020 13 | #define SENS_GFS 0x0400 14 | #define SENS_COMP 0x0800 15 | #define SENS_COUT 0x1000 16 | #define SENS_XOV64 0x2000 17 | #define SENS_ZERO 0xC3C0 18 | 19 | 20 | void sens_init(){ 21 | IOWR(SENS_OUT_BASE, 4, 0xFFFF); 22 | IOWR(SENS_OUT_BASE, 5, SENS_COMP); 23 | IOWR(SENS_OUT_BASE, 5, SENS_COUT); 24 | IOWR(SENS_OUT_BASE, 5, SENS_ZERO); 25 | IOWR(SENS_OUT_BASE, 5, SENS_GFS); 26 | IOWR(SENS_OUT_BASE, 5, SENS_FOK); 27 | IOWR(SENS_OUT_BASE, 5, SENS_XOV64); 28 | } 29 | 30 | void sens_FOK_on(){ 31 | IOWR(SENS_OUT_BASE, 4, SENS_FOK); 32 | } 33 | 34 | void sens_FOK_off(){ 35 | IOWR(SENS_OUT_BASE, 5, SENS_FOK); 36 | } 37 | 38 | void sens_XBUSY_on(){ 39 | IOWR(SENS_OUT_BASE, 4, SENS_XBUSY); 40 | } 41 | 42 | void sens_XBUSY_off(){ 43 | IOWR(SENS_OUT_BASE, 5, SENS_XBUSY); 44 | } 45 | 46 | -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/sgdma/sgdma.c: -------------------------------------------------------------------------------- 1 | /* 2 | * sgdma.c 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | #include 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include "sdcard.h" 17 | #include "sector_reader.h" 18 | #include "cxd2545.h" 19 | 20 | static volatile alt_sgdma_descriptor dma_data_desc __attribute__((section(".sgdma"))); 21 | static volatile alt_sgdma_descriptor dma_end_desc __attribute__((section(".sgdma"))); 22 | static uint8_t is_dma_work; 23 | 24 | //#define printf(fmt, ...) 25 | 26 | // static volatile uint8_t sector[2364] __attribute__((section(".sdram"))); 27 | uint8_t sgdma_is_working(){ 28 | return is_dma_work; 29 | } 30 | 31 | uint8_t sgdma_send_buffer(uint8_t * buffer, uint16_t length){ 32 | 33 | if(is_dma_work != 0){ 34 | return 1; 35 | } 36 | 37 | dma_data_desc.bytes_to_transfer = length; 38 | dma_data_desc.read_addr = (uint32_t *) buffer; 39 | dma_data_desc.next = (uint32_t *) &dma_end_desc; 40 | dma_data_desc.control = 0x85; 41 | dma_end_desc.control = 0x00; 42 | 43 | IOWR(SGDMA_CXD2545_DATA_BASE, 4, ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK); 44 | IOWR(SGDMA_CXD2545_DATA_BASE, 8, (int)&dma_data_desc); 45 | IOWR(SGDMA_CXD2545_DATA_BASE, 4, ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_RUN_MSK); 46 | /* 47 | alt_avalon_sgdma_construct_mem_to_stream_desc((alt_sgdma_descriptor *)&dma_data_desc, (alt_sgdma_descriptor *)&dma_end_desc, (uint32_t *)buffer, length, 0, 1, 1 ,0); 48 | if(alt_avalon_sgdma_do_async_transfer(dma, (alt_sgdma_descriptor *)&dma_data_desc) != 0){ 49 | printf("SGDAM ASYNC: ERRR!\r\n"); 50 | } 51 | */ 52 | 53 | is_dma_work = 1; 54 | 55 | return 0; 56 | } 57 | 58 | static void sgdma_irq(){ 59 | //IOWR(CXD2545_CTRL_BASE, 5, CTRL_DRAIN_DMA); 60 | uint32_t * data; 61 | IOWR(SGDMA_CXD2545_DATA_BASE, 4, ALTERA_AVALON_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK); 62 | 63 | is_dma_work = 0; 64 | if(cxd2545_get_state() == CXD_2545_OUTPUT){ 65 | if(sector_reader_is_done(&data) != 0){ 66 | sgdma_send_buffer((uint8_t *)data, 2364); 67 | cxd2545_next_sector(); 68 | sector_reader_swap(); 69 | printf("C"); 70 | } else { 71 | cxd2545_set_state(CXD_2545_WAITDATA); 72 | printf("M"); 73 | } 74 | } else { 75 | printf("P"); 76 | } 77 | 78 | } 79 | 80 | void sgdma_init(){ 81 | //dma = alt_avalon_sgdma_open("/dev/SGDMA_CXD2545_DATA"); 82 | is_dma_work = 0; 83 | IOWR(SGDMA_CXD2545_DATA_BASE, 4, ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK); 84 | 85 | 86 | alt_irq_register(SGDMA_CXD2545_DATA_IRQ, NULL, sgdma_irq); 87 | alt_irq_enable(SGDMA_CXD2545_DATA_IRQ); 88 | //alt_avalon_sgdma_init(dma, 0, 0); 89 | //alt_avalon_sgdma_register_callback(dma, sgdma_irq, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), /*inst*/0); 90 | } 91 | -------------------------------------------------------------------------------- /NIOS_SOFT/Drivers/spi/nios_spi_command.c: -------------------------------------------------------------------------------- 1 | /* 2 | * niso_spi_command.c 3 | * 4 | * Created on: 03.04.2019 5 | * Author: VBKesha 6 | */ 7 | 8 | /****************************************************************************** 9 | * * 10 | * License Agreement * 11 | * * 12 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * 13 | * All rights reserved. * 14 | * * 15 | * Permission is hereby granted, free of charge, to any person obtaining a * 16 | * copy of this software and associated documentation files (the "Software"), * 17 | * to deal in the Software without restriction, including without limitation * 18 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 19 | * and/or sell copies of the Software, and to permit persons to whom the * 20 | * Software is furnished to do so, subject to the following conditions: * 21 | * * 22 | * The above copyright notice and this permission notice shall be included in * 23 | * all copies or substantial portions of the Software. * 24 | * * 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 28 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 29 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 30 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 31 | * DEALINGS IN THE SOFTWARE. * 32 | * * 33 | * This agreement shall be governed in all respects by the laws of the State * 34 | * of California and by the laws of the United States of America. * 35 | * * 36 | ******************************************************************************/ 37 | 38 | #include 39 | #include "alt_types.h" 40 | 41 | #include 42 | #include 43 | 44 | /* This is a very simple routine which performs one SPI master transaction. 45 | * It would be possible to implement a more efficient version using interrupts 46 | * and sleeping threads but this is probably not worthwhile initially. 47 | */ 48 | #if 0 49 | int nios_spi_command3(uint32_t base, uint32_t slave, uint32_t write_length, 50 | const uint8_t * write_data, uint32_t read_length, uint8_t * read_data, 51 | uint32_t flags) { 52 | 53 | const alt_u8 * write_end = write_data + write_length; 54 | alt_u8 * read_end = read_data + read_length; 55 | 56 | alt_u32 write_zeros = read_length; 57 | alt_u32 read_ignore = write_length; 58 | alt_u32 status; 59 | 60 | /* We must not send more than two bytes to the target before it has 61 | * returned any as otherwise it will overflow. */ 62 | /* Unfortunately the hardware does not seem to work with credits > 1, 63 | * leave it at 1 for now. */ 64 | alt_32 credits = 1; 65 | 66 | /* Warning: this function is not currently safe if called in a multi-threaded 67 | * environment, something above must perform locking to make it safe if more 68 | * than one thread intends to use it. 69 | */ 70 | 71 | IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, 1 << slave); 72 | 73 | /* Set the SSO bit (force chipselect) only if the toggle flag is not set */ 74 | if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) { 75 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); 76 | } 77 | 78 | /* 79 | * Discard any stale data present in the RXDATA register, in case 80 | * previous communication was interrupted and stale data was left 81 | * behind. 82 | */ 83 | IORD_ALTERA_AVALON_SPI_RXDATA(base); 84 | 85 | /* Keep clocking until all the data has been processed. */ 86 | for (;;) { 87 | 88 | do { 89 | status = IORD_ALTERA_AVALON_SPI_STATUS(base); 90 | } while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 91 | || credits == 0) 92 | && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); 93 | 94 | if ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) != 0 && credits > 0) { 95 | credits--; 96 | 97 | if (write_data < write_end) 98 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, *write_data++); 99 | else if (write_zeros > 0) { 100 | write_zeros--; 101 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFF); 102 | } else 103 | credits = -1024; 104 | }; 105 | 106 | if ((status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) != 0) { 107 | alt_u32 rxdata = IORD_ALTERA_AVALON_SPI_RXDATA(base); 108 | 109 | if (read_ignore > 0) 110 | read_ignore--; 111 | else 112 | *read_data++ = (alt_u8) rxdata; 113 | credits++; 114 | 115 | if (read_ignore == 0 && read_data == read_end) 116 | break; 117 | } 118 | 119 | } 120 | 121 | /* Wait until the interface has finished transmitting */ 122 | do { 123 | status = IORD_ALTERA_AVALON_SPI_STATUS(base); 124 | } while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0); 125 | 126 | /* Clear SSO (release chipselect) unless the caller is going to 127 | * keep using this chip 128 | */ 129 | if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0) 130 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); 131 | 132 | return read_length; 133 | } 134 | 135 | void nios_spi_rw1(uint32_t base, uint32_t slave, uint32_t w_length, 136 | const uint32_t * write_data, uint32_t r_length, uint32_t * read_data, 137 | uint32_t flags) { 138 | 139 | /* Warning: this function is not currently safe if called in a multi-threaded 140 | * environment, something above must perform locking to make it safe if more 141 | * than one thread intends to use it. 142 | */ 143 | 144 | IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, 1 << slave); 145 | 146 | /* Set the SSO bit (force chipselect) only if the toggle flag is not set */ 147 | if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) { 148 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); 149 | } 150 | 151 | /* 152 | * Discard any stale data present in the RXDATA register, in case 153 | * previous communication was interrupted and stale data was left 154 | * behind. 155 | */ 156 | IORD_ALTERA_AVALON_SPI_RXDATA(base); 157 | 158 | /* Keep clocking until all the data has been processed. */ 159 | 160 | for (uint32_t i = 0; i < w_length; i++) { 161 | // Wait TX ready 162 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) 163 | & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) { 164 | } 165 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, write_data[i]); 166 | } 167 | 168 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) 169 | & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) { 170 | } 171 | 172 | uint32_t ret, ret2; 173 | if (r_length > 0) { 174 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFFFFFFFF); 175 | } 176 | for (uint32_t i = 0; i < r_length; i++) { 177 | 178 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) 179 | & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) { 180 | } 181 | ret = IORD_ALTERA_AVALON_SPI_RXDATA(base); 182 | if (i + 1 < r_length) { 183 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFFFFFFFF); 184 | } 185 | ret2 = 0; 186 | for (uint8_t j = 0; j < 4; j++) { 187 | ret2 = ret2 << 8; 188 | ret2 |= ret & 0xFF; 189 | ret = ret >> 8; 190 | } 191 | read_data[i] = ret2; 192 | } 193 | 194 | /* Clear SSO (release chipselect) unless the caller is going to 195 | * keep using this chip 196 | */ 197 | if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0) 198 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); 199 | 200 | } 201 | 202 | uint8_t nios_spi_r1(uint32_t base, uint32_t slave, uint32_t r_length, 203 | uint8_t * read_data, uint32_t * data_end, uint8_t * data_pos, 204 | uint32_t flags) { 205 | 206 | /* Warning: this function is not currently safe if called in a multi-threaded 207 | * environment, something above must perform locking to make it safe if more 208 | * than one thread intends to use it. 209 | */ 210 | uint16_t wpos; 211 | uint32_t ret, ret2; 212 | uint32_t i; 213 | IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, 1 << slave); 214 | 215 | /* Set the SSO bit (force chipselect) only if the toggle flag is not set */ 216 | if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) { 217 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); 218 | } 219 | 220 | IORD_ALTERA_AVALON_SPI_RXDATA(base); 221 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) 222 | & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) { 223 | } 224 | 225 | if (r_length > 0) { 226 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFFFFFFFF); 227 | } 228 | wpos = 0; 229 | ret2 = 0; 230 | for (i = 0; i < r_length; i += 4) { 231 | 232 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) 233 | & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) { 234 | } 235 | ret = IORD_ALTERA_AVALON_SPI_RXDATA(base); 236 | if (i + 4 < r_length) { 237 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFFFFFFFF); 238 | } 239 | ret2 = ret; 240 | for (uint8_t j = 0; j < 4; j++) { 241 | read_data[wpos] = ((ret2 & 0xFF000000) >> 24); 242 | wpos++; 243 | if (wpos >= r_length) { 244 | break; 245 | } 246 | ret2 = ret2 << 8; 247 | } 248 | 249 | } 250 | for (uint8_t j = 0; j < 4; j++) { 251 | ret2 = ret2 << 8; 252 | ret2 |= ret & 0xFF; 253 | ret = ret >> 8; 254 | } 255 | *data_end = ret2; 256 | *data_pos = i - wpos; 257 | 258 | /* Clear SSO (release chipselect) unless the caller is going to 259 | * keep using this chip 260 | */ 261 | if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0) { 262 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); 263 | } 264 | return 0; 265 | } 266 | #endif 267 | typedef union { 268 | uint8_t s[4]; 269 | uint16_t m[2]; 270 | uint32_t l; 271 | } uint32_u; 272 | 273 | int nios_spi32_wr(const uint32_t base, const uint32_t slave, const uint32_t write_length, const uint8_t * write_data, const uint32_t read_length, uint8_t * read_data, const uint32_t flags) { 274 | 275 | uint32_u tx_data; 276 | 277 | static uint32_u rx_data; 278 | static uint32_t wp; 279 | 280 | if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) { 281 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); 282 | } 283 | /* 284 | IORD_ALTERA_AVALON_SPI_RXDATA(base); 285 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) {} // wait ready 286 | */ 287 | if(write_length > 0){ 288 | wp = 0; 289 | while(wp < write_length ){ 290 | register uint8_t i = 4; 291 | do{ 292 | tx_data.s[--i] = (wp < write_length) ? write_data[wp] : 0xFF; 293 | wp++; 294 | } while(i>0); 295 | 296 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) {} // wait ready transmited 297 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, tx_data.l); 298 | } 299 | wp -= write_length; 300 | if(wp > 0){ 301 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) {} // wait ready receive 302 | rx_data.l = IORD_ALTERA_AVALON_SPI_RXDATA(base); 303 | //printf("SPI: doread data %04X\r\n", rx_data.l); 304 | } 305 | } 306 | 307 | if(read_length > 0){ 308 | register uint32_t rd = 0; 309 | while(rd < read_length){ 310 | if(rd + wp < read_length){ 311 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) {} // wait ready receive 312 | IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0xFFFFFFFF); 313 | //printf("SPI: Preget new data\r\n"); 314 | } 315 | 316 | while((wp > 0) && (rd < read_length)){ 317 | //printf("SPI: Read data\r\n"); 318 | wp--; 319 | read_data[rd++] = rx_data.s[wp]; 320 | } 321 | 322 | if(rd < read_length){ 323 | while ((IORD_ALTERA_AVALON_SPI_STATUS(base) & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) {} // wait ready receive 324 | rx_data.l = IORD_ALTERA_AVALON_SPI_RXDATA(base); 325 | wp = 4; 326 | //printf("SPI: Wait data %04X\r\n", rx_data.l); 327 | } 328 | } 329 | } 330 | 331 | if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0) { 332 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); 333 | } 334 | 335 | //printf("SPI WP[%d]: %d\r\n", write_length, wp); 336 | return 0; 337 | } 338 | 339 | void nios_spi_cs_off(uint32_t base){ 340 | IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0); 341 | } 342 | 343 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/cxd2545.h: -------------------------------------------------------------------------------- 1 | /* 2 | * cxd2545.h 3 | * 4 | * Created on: 14.02.2021 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef CXD2545_H_ 9 | #define CXD2545_H_ 10 | 11 | enum CXD2545_COMMAND { 12 | CXD2545_CMD_FOCUS_CONTROL = 0x0, 13 | CXD2545_CMD_TRACKING_CONTROL = 0x1, 14 | CXD2545_CMD_TRACKING_MODE = 0x2, 15 | CXD2545_CMD_SELECT = 0x3, 16 | CXD2545_CMD_AUTO_SEQUENCE = 0x4, 17 | CXD2545_CMD_BLIND_BRAKE_OVERFLOW = 0x5, 18 | CXD2545_CMD_SLED_KICK = 0x6, 19 | CXD2545_CMD_ASEQ_TRACK_COUNT = 0x7, 20 | CXD2545_CMD_MODE_SPECIFICATION = 0x8, 21 | CXD2545_CMD_FUNCTION_SPECIFICATION = 0x9, 22 | CXD2545_CMD_AUDIO_CONTROL = 0xA, 23 | CXD2545_CMD_TRAVERS_MONITOR_COUNTER = 0xB, 24 | CXD2545_CMD_SPINDLE_SERVO_SETTING = 0xC, 25 | CXD2545_CMD_CLV_CTRL = 0xD, 26 | CXD2545_CMD_CLV_MODE = 0xE, 27 | }; 28 | 29 | enum TRACKING_MODE { 30 | SLED_FORWARD = 0x2, 31 | SLED_REVERSE = 0x3, 32 | }; 33 | 34 | enum ASEQ_CMD { 35 | ASEQ_CMD_CANCEL = 0x0, 36 | ASEQ_CMD_FINE_SEARCH = 0x2, 37 | ASEQ_CMD_FOCUS_ON = 0x3, 38 | ASEQ_CMD_1TRK_JUMP = 0x4, 39 | ASEQ_CMD_10TRK_JUMP = 0x5, 40 | ASEQ_CMD_2NTRK_JUMP = 0x6, 41 | ASEQ_CMD_MTRK_JUMP = 0x7, 42 | }; 43 | 44 | enum CLV_MODE { 45 | CLV_MODE_STOP = 0x0, 46 | CLV_MODE_KICK = 0x8, 47 | CLV_MODE_BRAKE = 0xA, 48 | CLV_MODE_CLVS = 0xE, 49 | CLV_MODE_CLVH = 0xC, 50 | CLV_MODE_CLVP = 0xF, 51 | CLV_MODE_CLVA = 0x6, 52 | }; 53 | 54 | typedef union cxd2545_cmd_t { 55 | struct { 56 | uint32_t :20; 57 | uint32_t id:4; 58 | uint32_t :8; 59 | } cmd; 60 | 61 | struct { 62 | uint32_t :16; 63 | uint32_t sled:2; 64 | uint32_t tracking:2; 65 | uint32_t :12; 66 | } tracking_mode; 67 | 68 | struct { 69 | uint32_t :11; 70 | uint32_t LSSL:1; 71 | uint32_t MT:4; 72 | uint32_t dir:1; 73 | uint32_t cmd:3; 74 | uint32_t :12; 75 | } aseq_cmd; 76 | 77 | struct { 78 | uint32_t :4; 79 | uint32_t count:16; 80 | uint32_t :12; 81 | } aseq_track_count; 82 | 83 | struct { 84 | uint32_t :13; 85 | uint32_t SOCT:1; 86 | uint32_t ASHS:1; 87 | uint32_t VCOSEL:1; 88 | uint32_t WSEL:1; 89 | uint32_t DOUT_MuteF:1; 90 | uint32_t DOUT_Mute:1; 91 | uint32_t CDROM:1; 92 | uint32_t :12; 93 | } mode_specification; 94 | 95 | struct { 96 | uint32_t :13; 97 | uint32_t FLFC:1; 98 | uint32_t BiliGL_SUB:1; 99 | uint32_t BiliGL_Main:1; 100 | uint32_t DPLL:1; 101 | uint32_t ASEQ:1; 102 | uint32_t DSPB:1; 103 | uint32_t DCLV:1; 104 | uint32_t :12; 105 | } function_specification; 106 | 107 | struct { 108 | uint32_t :16; 109 | uint32_t mode:4; 110 | uint32_t :12; 111 | } clv_mode; 112 | 113 | uint32_t raw; 114 | } cxd2545_cmd; 115 | 116 | enum CXD2545_STATES { 117 | CXD_2545_IDLE, 118 | CXD_2545_WAITDATA, 119 | CXD_2545_OUTPUT, 120 | }; 121 | 122 | 123 | void cxd2545_init(uint32_t offset, uint32_t lead_out, uint32_t max_sector); 124 | uint32_t cxd2545_cur_sector(); 125 | void cxd2545_set_state(enum CXD2545_STATES state); 126 | uint32_t cxd2545_get_state(); 127 | uint32_t cxd2545_get_offset(); 128 | uint32_t cxd2545_get_sector(); 129 | void cxd2545_next_sector(); 130 | void cxd2545_change_sector(uint32_t step, uint8_t rev); 131 | void cxd2545_set_asq_jump(uint16_t jump); 132 | uint16_t cxd2545_get_asq_jump(); 133 | uint8_t cxd2545_servo_valid(); 134 | 135 | 136 | void cxd2545_cpu_init(); 137 | 138 | #endif /* CXD2545_H_ */ 139 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/cxd2545_ctrl.h: -------------------------------------------------------------------------------- 1 | /* 2 | * cxd2545_ctrl.h 3 | * 4 | * Created on: 15.02.2023 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef CXD2545_CTRL_H_ 9 | #define CXD2545_CTRL_H_ 10 | #include 11 | #include 12 | 13 | #define CTRL_DRAIN_DMA 0x0001 14 | #define CTRL_TRK0 0x0004 15 | #define CTRL_DBL_SPEED 0x0008 16 | #define CTRL_DOOR 0x0010 17 | #define CTRL_TRC_CNT 0x0020 18 | #define CTRL_TST 0x0040 19 | #define CTRL_SOCT 0x0080 20 | 21 | static inline void cxd2545_dma_drain_on(){ 22 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_DRAIN_DMA); 23 | } 24 | 25 | static inline void cxd2545_dma_drain_off(){ 26 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_DRAIN_DMA); 27 | } 28 | 29 | static inline void cxd2545_set_cd_speed(uint32_t speed){ 30 | if(speed){ 31 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_DBL_SPEED); 32 | } else { 33 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_DBL_SPEED); 34 | } 35 | } 36 | 37 | static inline void cxd2545_set_trk0(uint32_t sector){ 38 | if(sector){ 39 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_TRK0); 40 | } else { 41 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_TRK0); 42 | } 43 | } 44 | 45 | static inline void cxd2545_set_door(uint32_t door){ 46 | if(door){ 47 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_DOOR); 48 | } else { 49 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_DOOR); 50 | } 51 | } 52 | 53 | static inline void cxd2545_track_counter_start(){ 54 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_TRC_CNT); 55 | } 56 | 57 | static inline void cxd2545_track_counter_stop(){ 58 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_TRC_CNT); 59 | } 60 | 61 | 62 | static inline void cxd2545_tst_start(){ 63 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_TST); 64 | } 65 | 66 | static inline void cxd2545_tst_stop(){ 67 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_TST); 68 | } 69 | 70 | static inline void cxd2545_set_soct(uint32_t soct){ 71 | if(soct){ 72 | IOWR(CXD2545_CTRL_BASE, 4, CTRL_SOCT); 73 | } else { 74 | IOWR(CXD2545_CTRL_BASE, 5, CTRL_SOCT); 75 | } 76 | } 77 | 78 | #undef CTRL_DRAIN_DMA 79 | #undef CTRL_TRK0 80 | #undef CTRL_DBL_SPEED 81 | #undef CTRL_DOOR 82 | #undef CTRL_TRC_CNT 83 | #undef CTRL_TST 84 | #undef CTRL_SOCT 85 | 86 | #endif /* CXD2545_CTRL_H_ */ 87 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/dbg_printf.h: -------------------------------------------------------------------------------- 1 | /* 2 | * dbg_printf.h 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef DBG_PRINTF_H_ 9 | #define DBG_PRINTF_H_ 10 | 11 | #ifndef DEBUG 12 | #define dbg_printf(fmt, ...) 13 | #else 14 | #define dbg_printf(fmt, ...) printf("%s:%d:" fmt, __FILE__, __LINE__, ##__VA_ARGS__) 15 | #endif 16 | 17 | #endif /* DBG_PRINTF_H_ */ 18 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/display.h: -------------------------------------------------------------------------------- 1 | /* 2 | * display.h 3 | * 4 | * Created on: 27.02.2023 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef DISPLAY_H_ 9 | #define DISPLAY_H_ 10 | 11 | void display_set_open(); 12 | void display_set_close(); 13 | void display_num_game(uint8_t num); 14 | 15 | void diaplay_sd_err(uint8_t num); 16 | 17 | #endif /* DISPLAY_H_ */ 18 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/nios_spi_command.h: -------------------------------------------------------------------------------- 1 | /* 2 | * nios_spi_command.h 3 | * 4 | * Created on: 03.04.2019 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef NIOS_SPI_COMMAND_H_ 9 | #define NIOS_SPI_COMMAND_H_ 10 | 11 | #include 12 | 13 | int nios_spi_command2(uint32_t base, uint32_t slave, 14 | uint32_t write_length, const uint8_t * write_data, 15 | uint32_t read_length, uint8_t * read_data, 16 | uint32_t flags); 17 | 18 | void nios_spi_rw(uint32_t base, uint32_t slave, 19 | uint32_t w_length, const uint32_t * write_data, 20 | uint32_t r_length, uint32_t * read_data, 21 | uint32_t flags); 22 | 23 | void nios_spi_r(uint32_t base, uint32_t slave, 24 | uint32_t r_length, uint8_t * read_data, 25 | uint32_t * data_end, uint8_t * data_pos, 26 | uint32_t flags); 27 | 28 | #define ALT_AVALON_SPI_COMMAND_MERGE (0x01) 29 | 30 | #endif /* NIOS_SPI_COMMAND_H_ */ 31 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/sdcard.h: -------------------------------------------------------------------------------- 1 | /* 2 | * sdcard.h 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef SDCARD_H_ 9 | #define SDCARD_H_ 10 | 11 | typedef struct sdcard_inst_t{ 12 | uint32_t spi_base_addr; 13 | uint8_t cmd_buff[8]; 14 | uint8_t ret_buff[8]; 15 | uint32_t cur_sector; 16 | uint8_t state; 17 | 18 | // uint8_t i; 19 | // uint8_t data_ready; 20 | uint8_t data_pos; 21 | } sdcard_inst; 22 | 23 | uint8_t sdcard_init(sdcard_inst * inst, uint32_t spi_addr); 24 | uint8_t sdcard_read_sector(sdcard_inst * inst, uint32_t sector, uint8_t * buff); 25 | 26 | #endif /* SDCARD_H_ */ 27 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/sector_reader.h: -------------------------------------------------------------------------------- 1 | /* 2 | * sector_reader.h 3 | * 4 | * Created on: 21.03.2021 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef SECTOR_READER_H_ 9 | #define SECTOR_READER_H_ 10 | 11 | void sector_reader_init(sdcard_inst * inst); 12 | void sector_reader_read(uint32_t sector, uint32_t ** buff_addr); 13 | uint8_t sector_reader_is_done(uint32_t ** buff_addr); 14 | void sector_reader_swap(); 15 | 16 | #endif /* SECTOR_READER_H_ */ 17 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/sens_ctrl.h: -------------------------------------------------------------------------------- 1 | /* 2 | * sens_pin.h 3 | * 4 | * Created on: 31.05.2022 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef SENS_PIN_H_ 9 | #define SENS_PIN_H_ 10 | 11 | void sens_init(); 12 | 13 | void sens_FOK_on(); 14 | void sens_FOK_off(); 15 | 16 | void sens_XBUSY_on(); 17 | void sens_XBUSY_off(); 18 | 19 | #endif /* SENS_PIN_H_ */ 20 | -------------------------------------------------------------------------------- /NIOS_SOFT/Includes/sgdma.h: -------------------------------------------------------------------------------- 1 | /* 2 | * sgdma.h 3 | * 4 | * Created on: 04.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | #ifndef SGDMA_H_ 9 | #define SGDMA_H_ 10 | 11 | void sgdma_init(); 12 | uint8_t sgdma_send_buffer(uint8_t * buffer, uint16_t length); 13 | uint8_t sgdma_is_working(); 14 | 15 | #endif /* SGDMA_H_ */ 16 | -------------------------------------------------------------------------------- /NIOS_SOFT/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------ 2 | # VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS 3 | #------------------------------------------------------------------------------ 4 | 5 | # List of include directories for -I compiler option (-I added when used). 6 | # Includes the BSP. 7 | ALT_INCLUDE_DIRS := 8 | 9 | # List of library directories for -L linker option (-L added when used). 10 | # Includes the BSP. 11 | ALT_LIBRARY_DIRS := 12 | 13 | # List of library names for -l linker option (-l added when used). 14 | # Includes the BSP. 15 | ALT_LIBRARY_NAMES := 16 | 17 | # List of library names for -msys-lib linker option (-msys-lib added when used). 18 | # These are libraries that might be located in the BSP and depend on the BSP 19 | # library, or vice versa 20 | ALT_BSP_DEP_LIBRARY_NAMES := 21 | 22 | # List of dependencies for the linker. This is usually the full pathname 23 | # of each library (*.a) file. 24 | # Includes the BSP. 25 | ALT_LDDEPS := 26 | 27 | # List of root library directories that support running make to build them. 28 | # Includes the BSP and any ALT libraries. 29 | MAKEABLE_LIBRARY_ROOT_DIRS := 30 | 31 | # Generic flags passed to the compiler for different types of input files. 32 | ALT_CFLAGS := 33 | ALT_CXXFLAGS := 34 | ALT_CPPFLAGS := 35 | ALT_ASFLAGS := 36 | ALT_LDFLAGS := 37 | 38 | 39 | #------------------------------------------------------------------------------ 40 | # The adjust-path macro 41 | # 42 | # If COMSPEC/ComSpec is defined, Make is launched from Windows through 43 | # Cygwin. The adjust-path macro converts absolute windows paths into 44 | # unix style paths (Example: c:/dir -> /c/dir). This will ensture 45 | # paths are readable by GNU Make. 46 | # 47 | # If COMSPEC/ComSpec is not defined, Make is launched from linux, and no 48 | # adjustment is necessary 49 | # 50 | #------------------------------------------------------------------------------ 51 | 52 | ifndef COMSPEC 53 | ifdef ComSpec 54 | COMSPEC = $(ComSpec) 55 | endif # ComSpec 56 | endif # COMSPEC 57 | 58 | ifdef COMSPEC # if Windows OS 59 | 60 | ifeq ($(MAKE_VERSION),3.81) 61 | # 62 | # adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows 63 | # 64 | # Example Usage: 65 | # $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb 66 | # $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb 67 | # $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb 68 | # 69 | 70 | # 71 | # adjust-path 72 | # - converts back slash characters into forward slashes 73 | # - if input arg ($1) is an empty string then return the empty string 74 | # - if input arg ($1) does not contain the string ":/", then return input arg 75 | # - using sed, convert mixed path [c:/...] into mingw path [/c/...] 76 | define adjust-path 77 | $(strip \ 78 | $(if $1,\ 79 | $(if $(findstring :/,$(subst \,/,$1)),\ 80 | $(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\ 81 | $(subst \,/,$1)))) 82 | endef 83 | 84 | # 85 | # adjust-path-mixed 86 | # - converts back slash characters into forward slashes 87 | # - if input arg ($1) is an empty string then return the empty string 88 | # - if input arg ($1) does not begin with a forward slash '/' char, then 89 | # return input arg 90 | # - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] 91 | # into a mixed path [c:/...] 92 | define adjust-path-mixed 93 | $(strip \ 94 | $(if $1,\ 95 | $(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ 96 | $(subst \,/,$1),\ 97 | $(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) 98 | endef 99 | 100 | else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) 101 | # 102 | # adjust-path for Cygwin Gnu Make 103 | # $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb 104 | # $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb 105 | # 106 | adjust-path = $(if $1,$(shell cygpath -u "$1"),) 107 | adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) 108 | endif 109 | 110 | else # !COMSPEC 111 | 112 | adjust-path = $1 113 | adjust-path-mixed = $1 114 | 115 | endif # COMSPEC 116 | 117 | 118 | #vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv 119 | # GENERATED SETTINGS START v 120 | #vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv 121 | 122 | #START GENERATED 123 | ACTIVE_BUILD_CONFIG := default 124 | BUILD_CONFIGS := default 125 | 126 | # The following TYPE comment allows tools to identify the 'type' of target this 127 | # makefile is associated with. 128 | # TYPE: APP_MAKEFILE 129 | 130 | # This following VERSION comment indicates the version of the tool used to 131 | # generate this makefile. A makefile variable is provided for VERSION as well. 132 | # ACDS_VERSION: 12.1sp1 133 | ACDS_VERSION := 12.1sp1 134 | 135 | # This following BUILD_NUMBER comment indicates the build number of the tool 136 | # used to generate this makefile. 137 | # BUILD_NUMBER: 243 138 | 139 | # Define path to the application ELF. 140 | # It may be used by the makefile fragments so is defined before including them. 141 | # 142 | ELF := CXD2545_EMU.elf 143 | 144 | # Paths to C, C++, and assembly source files. 145 | C_SRCS += Drivers/cxd2545_cpu/cxd2545_cpu.c 146 | C_SRCS += Drivers/sdcard_spi/sdcard_spi.c 147 | C_SRCS += Drivers/sens_ctrl/sens_ctrl.c 148 | C_SRCS += Drivers/sgdma/sgdma.c 149 | C_SRCS += Drivers/spi/nios_spi_command.c 150 | C_SRCS += libs/cxd2545/cxd2545.c 151 | C_SRCS += libs/sectors/sector_reader.c 152 | C_SRCS += main.c 153 | C_SRCS += libs/display/display.c 154 | CXX_SRCS := 155 | ASM_SRCS := 156 | 157 | 158 | # Path to root of object file tree. 159 | OBJ_ROOT_DIR := obj 160 | 161 | # Options to control objdump. 162 | CREATE_OBJDUMP := 1 163 | OBJDUMP_INCLUDE_SOURCE := 0 164 | OBJDUMP_FULL_CONTENTS := 0 165 | 166 | # Options to enable/disable optional files. 167 | CREATE_ELF_DERIVED_FILES := 0 168 | CREATE_LINKER_MAP := 1 169 | 170 | # Common arguments for ALT_CFLAGSs 171 | APP_CFLAGS_DEFINED_SYMBOLS := 172 | APP_CFLAGS_UNDEFINED_SYMBOLS := 173 | APP_CFLAGS_OPTIMIZATION := -O3 174 | APP_CFLAGS_DEBUG_LEVEL := 175 | APP_CFLAGS_WARNINGS := -Wall 176 | APP_CFLAGS_USER_FLAGS := -std=c99 -fdata-sections -ffunction-sections 177 | 178 | APP_ASFLAGS_USER := 179 | APP_LDFLAGS_USER := -Wl,--gc-sections 180 | 181 | # Linker options that have default values assigned later if not 182 | # assigned here. 183 | LINKER_SCRIPT := 184 | CRT0 := 185 | SYS_LIB := 186 | 187 | # Define path to the root of the BSP. 188 | BSP_ROOT_DIR := ../CXD2545_EMU_BSP/ 189 | 190 | # List of application specific include directories, library directories and library names 191 | APP_INCLUDE_DIRS := Includes 192 | APP_LIBRARY_DIRS := 193 | APP_LIBRARY_NAMES := 194 | 195 | # Pre- and post- processor settings. 196 | BUILD_PRE_PROCESS := 197 | BUILD_POST_PROCESS := 198 | 199 | 200 | 201 | #END GENERATED 202 | 203 | #^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 204 | # GENERATED SETTINGS END ^ 205 | #^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 206 | 207 | 208 | #------------------------------------------------------------------------------ 209 | # DEFAULT TARGET 210 | #------------------------------------------------------------------------------ 211 | 212 | # Define the variable used to echo output if not already defined. 213 | ifeq ($(ECHO),) 214 | ECHO := echo 215 | endif 216 | 217 | # Put "all" rule before included makefile fragments because they may 218 | # define rules and we don't want one of those to become the default rule. 219 | .PHONY : all 220 | 221 | all: 222 | @$(ECHO) [$(APP_NAME) build complete] 223 | 224 | all : build_pre_process libs app build_post_process 225 | 226 | 227 | #------------------------------------------------------------------------------ 228 | # VARIABLES DEPENDENT ON GENERATED CONTENT 229 | #------------------------------------------------------------------------------ 230 | 231 | # Define object file directory per build configuration 232 | CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) 233 | 234 | ifeq ($(BSP_ROOT_DIR),) 235 | $(error Edit Makefile and provide a value for BSP_ROOT_DIR) 236 | endif 237 | 238 | ifeq ($(wildcard $(BSP_ROOT_DIR)),) 239 | $(error BSP directory does not exist: $(BSP_ROOT_DIR)) 240 | endif 241 | 242 | # Define absolute path to the root of the BSP. 243 | ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) 244 | 245 | # Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before 246 | # including each makefile fragment so that it knows the path to itself. 247 | BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk 248 | ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) 249 | include $(BSP_INCLUDE_FILE) 250 | # C2H will need this to touch the BSP public.mk and avoid the sopc file 251 | # out-of-date error during a BSP make 252 | ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk 253 | 254 | 255 | ifneq ($(WARNING.SMALL_STACK_SIZE),) 256 | # This WARNING is here to protect you from unknowingly using a very small stack 257 | # If the warning is set, increase your stack size or enable the BSP small stack 258 | # setting to eliminate the warning 259 | $(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) 260 | endif 261 | 262 | 263 | # If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF 264 | # by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. 265 | ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) 266 | ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) 267 | endif 268 | 269 | # If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to 270 | # download_elf target 271 | ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) 272 | GMON_OUT_FILENAME := gmon.out 273 | WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) 274 | endif 275 | 276 | # Name of ELF application. 277 | APP_NAME := $(basename $(ELF)) 278 | 279 | # Set to defaults if variables not already defined in settings. 280 | ifeq ($(LINKER_SCRIPT),) 281 | LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) 282 | endif 283 | ifeq ($(CRT0),) 284 | CRT0 := $(BSP_CRT0) 285 | endif 286 | ifeq ($(SYS_LIB),) 287 | SYS_LIB := $(BSP_SYS_LIB) 288 | endif 289 | 290 | OBJDUMP_NAME := $(APP_NAME).objdump 291 | OBJDUMP_FLAGS := --disassemble --syms --all-header 292 | ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) 293 | OBJDUMP_FLAGS += --source 294 | endif 295 | ifeq ($(OBJDUMP_FULL_CONTENTS),1) 296 | OBJDUMP_FLAGS += --full-contents 297 | endif 298 | 299 | # Create list of linker dependencies (*.a files). 300 | APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) 301 | 302 | # Take lists and add required prefixes. 303 | APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) 304 | ASM_INC_PREFIX := -Wa,-I 305 | APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) 306 | APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) 307 | APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) 308 | 309 | ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) 310 | 311 | # 312 | # Avoid Nios II GCC 3.X options. 313 | # 314 | 315 | # Detect if small newlib C library is requested. 316 | # If yes, remove the -msmallc option because it is 317 | # now handled by other means. 318 | ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) 319 | ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) 320 | ALT_C_LIBRARY := smallc 321 | else 322 | ALT_C_LIBRARY := c 323 | endif 324 | 325 | # Put each BSP dependent library in a group to avoid circular dependencies. 326 | APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) 327 | 328 | else # !AVOID_NIOS2_GCC3_OPTIONS 329 | 330 | # 331 | # Use Nios II GCC 3.X options. 332 | # 333 | APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) 334 | 335 | endif # !AVOID_NIOS2_GCC3_OPTIONS 336 | 337 | # Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. 338 | APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ 339 | $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ 340 | $(APP_CFLAGS_OPTIMIZATION) \ 341 | $(APP_CFLAGS_DEBUG_LEVEL) \ 342 | $(APP_CFLAGS_WARNINGS) \ 343 | $(APP_CFLAGS_USER_FLAGS) \ 344 | $(ALT_CFLAGS) \ 345 | $(CFLAGS) 346 | 347 | # Arguments only for the C++ compiler. 348 | APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) 349 | 350 | # Arguments only for the C preprocessor. 351 | # Prefix each include directory with -I. 352 | APP_CPPFLAGS := $(APP_INC_DIRS) \ 353 | $(ALT_CPPFLAGS) \ 354 | $(CPPFLAGS) 355 | 356 | # Arguments only for the assembler. 357 | APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ 358 | $(ALT_ASFLAGS) \ 359 | $(APP_ASFLAGS_USER) \ 360 | $(ASFLAGS) 361 | 362 | # Arguments only for the linker. 363 | APP_LDFLAGS := $(APP_LDFLAGS_USER) 364 | 365 | ifneq ($(LINKER_SCRIPT),) 366 | APP_LDFLAGS += -T'$(LINKER_SCRIPT)' 367 | endif 368 | 369 | ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) 370 | 371 | # Avoid Nios II GCC 3.x options. 372 | ifneq ($(CRT0),) 373 | APP_LDFLAGS += $(CRT0) 374 | endif 375 | 376 | # The equivalent of the -msys-lib option is provided 377 | # by the GROUP() command in the linker script. 378 | # Note this means the SYS_LIB variable is now ignored. 379 | 380 | else # !AVOID_NIOS2_GCC3_OPTIONS 381 | 382 | # Use Nios II GCC 3.x options. 383 | ifneq ($(CRT0),) 384 | APP_LDFLAGS += -msys-crt0='$(CRT0)' 385 | endif 386 | ifneq ($(SYS_LIB),) 387 | APP_LDFLAGS += -msys-lib=$(SYS_LIB) 388 | endif 389 | 390 | endif # !AVOID_NIOS2_GCC3_OPTIONS 391 | 392 | APP_LDFLAGS += \ 393 | $(APP_LIB_DIRS) \ 394 | $(ALT_LDFLAGS) \ 395 | $(LDFLAGS) 396 | 397 | LINKER_MAP_NAME := $(APP_NAME).map 398 | ifeq ($(CREATE_LINKER_MAP), 1) 399 | APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) 400 | endif 401 | 402 | # QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the 403 | # mem_init_install target of the mem_init.mk (located in the associated BSP) 404 | # to know how to copy memory initialization files (e.g. .dat, .hex) into 405 | # directories required for Quartus compilation or RTL simulation. 406 | 407 | # Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory 408 | # initialization files into your Quartus project directory. This is required 409 | # to provide the initial memory contents of FPGA memories that can be 410 | # initialized by the programming file (.sof) or Hardcopy ROMs. It is also used 411 | # for VHDL simulation of on-chip memories. 412 | 413 | # Defining SOPC_NAME causes the mem_init_install target to copy memory 414 | # initialization files into your RTL simulation directory. This is required 415 | # to provide the initial memory contents of all memories that can be 416 | # initialized by RTL simulation. This variable should be set to the same name 417 | # as your SOPC Builder system name. For example, if you have a system called 418 | # "foo.sopc", this variable should be set to "foo". 419 | 420 | # If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. 421 | ifeq ($(SOPC_NAME),) 422 | ifneq ($(QUARTUS_PROJECT_DIR),) 423 | SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) 424 | endif 425 | endif 426 | 427 | # Defining JDI_FILE is required to specify the JTAG Debug Information File 428 | # path. This file is generated by Quartus, and is needed along with the 429 | # .sopcinfo file to resolve processor instance ID's from names in a multi-CPU 430 | # systems. For multi-CPU systems, the processor instance ID is used to select 431 | # from multiple CPU's during ELF download. 432 | 433 | # Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during 434 | # BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then 435 | # derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be 436 | # multiple .sopcinfo files in a Quartus project. 437 | ifeq ($(JDI_FILE),) 438 | ifneq ($(QUARTUS_PROJECT_DIR),) 439 | JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) 440 | endif 441 | endif 442 | 443 | # Path to root runtime directory used for hdl simulation 444 | RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime 445 | 446 | 447 | 448 | #------------------------------------------------------------------------------ 449 | # MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT 450 | #------------------------------------------------------------------------------ 451 | # mem_init.mk is a generated makefile fragment. This file defines all targets 452 | # used to generate HDL initialization simulation files and pre-initialized 453 | # onchip memory files. 454 | MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk 455 | include $(MEM_INIT_FILE) 456 | 457 | # Create list of object files to be built using the list of source files. 458 | # The source file hierarchy is preserved in the object tree. 459 | # The supported file extensions are: 460 | # 461 | # .c - for C files 462 | # .cxx .cc .cpp - for C++ files 463 | # .S .s - for assembler files 464 | # 465 | # Handle source files specified by --src-dir & --src-rdir differently, to 466 | # save some processing time in calling the adjust-path macro. 467 | 468 | OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) 469 | OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) 470 | OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) 471 | OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) 472 | OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) 473 | OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) 474 | 475 | OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ 476 | $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) 477 | 478 | SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) 479 | SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) 480 | SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) 481 | SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) 482 | SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) 483 | SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) 484 | 485 | SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ 486 | $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ 487 | $(SDIR_OBJ_LIST_SS)) 488 | 489 | # Relative-pathed objects that being with "../" are handled differently. 490 | # 491 | # Regular objects are created as 492 | # $(CONFIG_OBJ_DIR)//.o 493 | # where the path structure is maintained under the obj directory. This 494 | # applies for both absolute and relative paths; in the absolute path 495 | # case this means the entire source path will be recreated under the obj 496 | # directory. This is done to allow two source files with the same name 497 | # to be included as part of the project. 498 | # 499 | # Note: On Cygwin, the path recreated under the obj directory will be 500 | # the cygpath -u output path. 501 | # 502 | # Relative-path objects that begin with "../" cause problems under this 503 | # scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object 504 | # files anywhere in the system, creating clutter and polluting the source tree. 505 | # As such, their paths are flattened - the object file created will be 506 | # $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with 507 | # "../" in the beginning cannot have the same name in the project. VPATH 508 | # will be set for these sources to allow make to relocate the source file 509 | # via %.o rules. 510 | # 511 | # The following lines separate the object list into the flatten and regular 512 | # lists, and then handles them as appropriate. 513 | 514 | FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) 515 | FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) 516 | 517 | REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) 518 | REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) 519 | REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) 520 | REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) 521 | REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) 522 | REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) 523 | REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) 524 | 525 | FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) 526 | FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) 527 | 528 | REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) 529 | REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) 530 | REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) 531 | REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) 532 | REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) 533 | REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) 534 | REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) 535 | 536 | VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) 537 | 538 | APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ 539 | $(REGULAR_SDIR_OBJ_LIST_C) \ 540 | $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) 541 | 542 | APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ 543 | $(REGULAR_SDIR_OBJ_LIST_CPP) \ 544 | $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) 545 | 546 | APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ 547 | $(REGULAR_SDIR_OBJ_LIST_CXX) \ 548 | $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) 549 | 550 | APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ 551 | $(REGULAR_SDIR_OBJ_LIST_CC) \ 552 | $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) 553 | 554 | APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ 555 | $(REGULAR_SDIR_OBJ_LIST_S) \ 556 | $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) 557 | 558 | APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ 559 | $(REGULAR_SDIR_OBJ_LIST_SS) \ 560 | $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) 561 | 562 | APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ 563 | $(APP_OBJS_S) $(APP_OBJS_SS) \ 564 | $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) 565 | 566 | # Add any extra user-provided object files. 567 | APP_OBJS += $(OBJS) 568 | 569 | # Create list of dependancy files for each object file. 570 | APP_DEPS := $(APP_OBJS:.o=.d) 571 | 572 | # Patch the Elf file with system specific information 573 | 574 | # Patch the Elf with the name of the sopc system 575 | ifneq ($(SOPC_NAME),) 576 | ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) 577 | endif 578 | 579 | # Patch the Elf with the absolute path to the Quartus Project Directory 580 | ifneq ($(QUARTUS_PROJECT_DIR),) 581 | ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) 582 | ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" 583 | endif 584 | 585 | # Patch the Elf and download args with the JDI_FILE if specified 586 | ifneq ($(wildcard $(JDI_FILE)),) 587 | ELF_PATCH_FLAG += --jdi $(JDI_FILE) 588 | DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) 589 | endif 590 | 591 | # Patch the Elf with the SOPCINFO_FILE if specified 592 | ifneq ($(wildcard $(SOPCINFO_FILE)),) 593 | ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) 594 | endif 595 | 596 | # Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. 597 | # This is not needed if you only have one cable. 598 | ifneq ($(DOWNLOAD_CABLE),) 599 | DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' 600 | endif 601 | 602 | 603 | #------------------------------------------------------------------------------ 604 | # BUILD PRE/POST PROCESS 605 | #------------------------------------------------------------------------------ 606 | build_pre_process : 607 | $(BUILD_PRE_PROCESS) 608 | 609 | build_post_process : 610 | $(BUILD_POST_PROCESS) 611 | 612 | .PHONY: build_pre_process build_post_process 613 | 614 | 615 | #------------------------------------------------------------------------------ 616 | # TOOLS 617 | #------------------------------------------------------------------------------ 618 | 619 | # 620 | # Set tool default variables if not already defined. 621 | # If these are defined, they would typically be defined in an 622 | # included makefile fragment. 623 | # 624 | ifeq ($(DEFAULT_CROSS_COMPILE),) 625 | DEFAULT_CROSS_COMPILE := nios2-elf- 626 | endif 627 | 628 | ifeq ($(DEFAULT_STACK_REPORT),) 629 | DEFAULT_STACKREPORT := nios2-stackreport 630 | endif 631 | 632 | ifeq ($(DEFAULT_DOWNLOAD),) 633 | DEFAULT_DOWNLOAD := nios2-download 634 | endif 635 | 636 | ifeq ($(DEFAULT_FLASHPROG),) 637 | DEFAULT_FLASHPROG := nios2-flash-programmer 638 | endif 639 | 640 | ifeq ($(DEFAULT_ELFPATCH),) 641 | DEFAULT_ELFPATCH := nios2-elf-insert 642 | endif 643 | 644 | ifeq ($(DEFAULT_RM),) 645 | DEFAULT_RM := rm -f 646 | endif 647 | 648 | ifeq ($(DEFAULT_CP),) 649 | DEFAULT_CP := cp -f 650 | endif 651 | 652 | ifeq ($(DEFAULT_MKDIR),) 653 | DEFAULT_MKDIR := mkdir -p 654 | endif 655 | 656 | # 657 | # Set tool variables to defaults if not already defined. 658 | # If these are defined, they would typically be defined by a 659 | # setting in the generated portion of this makefile. 660 | # 661 | ifeq ($(CROSS_COMPILE),) 662 | CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) 663 | endif 664 | 665 | ifeq ($(origin CC),default) 666 | CC := $(CROSS_COMPILE)gcc -xc 667 | endif 668 | 669 | ifeq ($(origin CXX),default) 670 | CXX := $(CROSS_COMPILE)gcc -xc++ 671 | endif 672 | 673 | ifeq ($(origin AS),default) 674 | AS := $(CROSS_COMPILE)gcc 675 | endif 676 | 677 | ifeq ($(origin AR),default) 678 | AR := $(CROSS_COMPILE)ar 679 | endif 680 | 681 | ifeq ($(origin LD),default) 682 | LD := $(CROSS_COMPILE)gcc 683 | endif 684 | 685 | ifeq ($(origin NM),default) 686 | NM := $(CROSS_COMPILE)nm 687 | endif 688 | 689 | ifeq ($(origin RM),default) 690 | RM := $(DEFAULT_RM) 691 | endif 692 | 693 | ifeq ($(origin CP),default) 694 | CP := $(DEFAULT_CP) 695 | endif 696 | 697 | ifeq ($(OBJDUMP),) 698 | OBJDUMP := $(CROSS_COMPILE)objdump 699 | endif 700 | 701 | ifeq ($(OBJCOPY),) 702 | OBJCOPY := $(CROSS_COMPILE)objcopy 703 | endif 704 | 705 | ifeq ($(STACKREPORT),) 706 | ifeq ($(CROSS_COMPILE),nios2-elf-) 707 | STACKREPORT := $(DEFAULT_STACKREPORT) 708 | else 709 | DISABLE_STACKREPORT := 1 710 | endif 711 | endif 712 | 713 | ifeq ($(DOWNLOAD),) 714 | DOWNLOAD := $(DEFAULT_DOWNLOAD) 715 | endif 716 | 717 | ifeq ($(FLASHPROG),) 718 | FLASHPROG := $(DEFAULT_FLASHPROG) 719 | endif 720 | 721 | ifeq ($(ELFPATCH),) 722 | ELFPATCH := $(DEFAULT_ELFPATCH) 723 | endif 724 | 725 | ifeq ($(MKDIR),) 726 | MKDIR := $(DEFAULT_MKDIR) 727 | endif 728 | 729 | #------------------------------------------------------------------------------ 730 | # PATTERN RULES TO BUILD OBJECTS 731 | #------------------------------------------------------------------------------ 732 | 733 | define compile.c 734 | @$(ECHO) Info: Compiling $< to $@ 735 | @$(MKDIR) $(@D) 736 | $(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< 737 | $(CC_POST_PROCESS) 738 | endef 739 | 740 | define compile.cpp 741 | @$(ECHO) Info: Compiling $< to $@ 742 | @$(MKDIR) $(@D) 743 | $(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 744 | $(CXX_POST_PROCESS) 745 | endef 746 | 747 | # If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS 748 | ifeq ($(AS),$(patsubst %as,%,$(AS))) 749 | COMMA := , 750 | APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) 751 | endif 752 | 753 | define compile.s 754 | @$(ECHO) Info: Assembling $< to $@ 755 | @$(MKDIR) $(@D) 756 | $(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< 757 | $(AS_POST_PROCESS) 758 | endef 759 | 760 | ifeq ($(MAKE_VERSION),3.81) 761 | .SECONDEXPANSION: 762 | 763 | $(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) 764 | $(compile.c) 765 | 766 | $(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) 767 | $(compile.cpp) 768 | 769 | $(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) 770 | $(compile.cpp) 771 | 772 | $(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) 773 | $(compile.cpp) 774 | 775 | $(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) 776 | $(compile.s) 777 | 778 | $(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) 779 | $(compile.s) 780 | 781 | endif # MAKE_VERSION != 3.81 782 | 783 | $(CONFIG_OBJ_DIR)/%.o: %.c 784 | $(compile.c) 785 | 786 | $(CONFIG_OBJ_DIR)/%.o: %.cpp 787 | $(compile.cpp) 788 | 789 | $(CONFIG_OBJ_DIR)/%.o: %.cc 790 | $(compile.cpp) 791 | 792 | $(CONFIG_OBJ_DIR)/%.o: %.cxx 793 | $(compile.cpp) 794 | 795 | $(CONFIG_OBJ_DIR)/%.o: %.S 796 | $(compile.s) 797 | 798 | $(CONFIG_OBJ_DIR)/%.o: %.s 799 | $(compile.s) 800 | 801 | 802 | #------------------------------------------------------------------------------ 803 | # PATTERN RULES TO INTERMEDIATE FILES 804 | #------------------------------------------------------------------------------ 805 | 806 | $(CONFIG_OBJ_DIR)/%.s: %.c 807 | @$(ECHO) Info: Compiling $< to $@ 808 | @$(MKDIR) $(@D) 809 | $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< 810 | 811 | $(CONFIG_OBJ_DIR)/%.s: %.cpp 812 | @$(ECHO) Info: Compiling $< to $@ 813 | @$(MKDIR) $(@D) 814 | $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 815 | 816 | $(CONFIG_OBJ_DIR)/%.s: %.cc 817 | @$(ECHO) Info: Compiling $< to $@ 818 | @$(MKDIR) $(@D) 819 | $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 820 | 821 | $(CONFIG_OBJ_DIR)/%.s: %.cxx 822 | @$(ECHO) Info: Compiling $< to $@ 823 | @$(MKDIR) $(@D) 824 | $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 825 | 826 | $(CONFIG_OBJ_DIR)/%.i: %.c 827 | @$(ECHO) Info: Compiling $< to $@ 828 | @$(MKDIR) $(@D) 829 | $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< 830 | 831 | $(CONFIG_OBJ_DIR)/%.i: %.cpp 832 | @$(ECHO) Info: Compiling $< to $@ 833 | @$(MKDIR) $(@D) 834 | $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 835 | 836 | $(CONFIG_OBJ_DIR)/%.i: %.cc 837 | @$(ECHO) Info: Compiling $< to $@ 838 | @$(MKDIR) $(@D) 839 | $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 840 | 841 | $(CONFIG_OBJ_DIR)/%.i: %.cxx 842 | @$(ECHO) Info: Compiling $< to $@ 843 | @$(MKDIR) $(@D) 844 | $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< 845 | 846 | 847 | #------------------------------------------------------------------------------ 848 | # TARGET RULES 849 | #------------------------------------------------------------------------------ 850 | 851 | .PHONY : help 852 | help : 853 | @$(ECHO) "Summary of Makefile targets" 854 | @$(ECHO) " Build targets:" 855 | @$(ECHO) " all (default) - Application and all libraries (including BSP)" 856 | @$(ECHO) " bsp - Just the BSP" 857 | @$(ECHO) " libs - All libraries (including BSP)" 858 | @$(ECHO) " flash - All flash files" 859 | @$(ECHO) " mem_init_generate - All memory initialization files" 860 | ifeq ($(QSYS),1) 861 | @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" 862 | @$(ECHO) " --> Use the mem_init_generate target and then" 863 | @$(ECHO) " add the generated meminit.qip file to your" 864 | @$(ECHO) " Quartus II Project." 865 | else # if QSYS != 1 866 | @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" 867 | endif # QSYS == 1 868 | @$(ECHO) 869 | @$(ECHO) " Clean targets:" 870 | @$(ECHO) " clean_all - Application and all libraries (including BSP)" 871 | @$(ECHO) " clean - Just the application" 872 | @$(ECHO) " clean_bsp - Just the BSP" 873 | @$(ECHO) " clean_libs - All libraries (including BSP)" 874 | @$(ECHO) 875 | @$(ECHO) " Run targets:" 876 | @$(ECHO) " download-elf - Download and run your elf executable" 877 | @$(ECHO) " program-flash - Program flash contents to the board" 878 | 879 | # Handy rule to skip making libraries and just make application. 880 | .PHONY : app 881 | app : $(ELF) 882 | 883 | ifeq ($(CREATE_OBJDUMP), 1) 884 | app : $(OBJDUMP_NAME) 885 | endif 886 | 887 | ifeq ($(CREATE_ELF_DERIVED_FILES),1) 888 | app : elf_derived_files 889 | endif 890 | 891 | .PHONY: elf_derived_files 892 | elf_derived_files: default_mem_init 893 | 894 | # Handy rule for making just the BSP. 895 | .PHONY : bsp 896 | bsp : 897 | @$(ECHO) Info: Building $(BSP_ROOT_DIR) 898 | @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) 899 | 900 | 901 | # Make sure all makeable libraries (including the BSP) are up-to-date. 902 | LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) 903 | 904 | .PHONY : libs 905 | libs : $(LIB_TARGETS) 906 | 907 | ifneq ($(strip $(LIB_TARGETS)),) 908 | $(LIB_TARGETS): %-recurs-make-lib: 909 | @$(ECHO) Info: Building $* 910 | $(MAKE) --no-print-directory -C $* 911 | endif 912 | 913 | ifneq ($(strip $(APP_LDDEPS)),) 914 | $(APP_LDDEPS): libs 915 | @true 916 | endif 917 | 918 | # Rules to force your project to rebuild or relink 919 | # .force_relink file will cause any application that depends on this project to relink 920 | # .force_rebuild file will cause this project to rebuild object files 921 | # .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files 922 | 923 | FORCE_RELINK_DEP := .force_relink 924 | FORCE_REBUILD_DEP := .force_rebuild 925 | FORCE_REBUILD_ALL_DEP := .force_rebuild_all 926 | FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) 927 | 928 | $(FORCE_REBUILD_DEP_LIST): 929 | 930 | $(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) 931 | 932 | $(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) 933 | 934 | 935 | # Clean just the application. 936 | .PHONY : clean 937 | ifeq ($(CREATE_ELF_DERIVED_FILES),1) 938 | clean : clean_elf_derived_files 939 | endif 940 | 941 | clean : 942 | @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) 943 | @$(ECHO) [$(APP_NAME) clean complete] 944 | 945 | # Clean just the BSP. 946 | .PHONY : clean_bsp 947 | clean_bsp : 948 | @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) 949 | @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean 950 | 951 | # Clean all makeable libraries including the BSP. 952 | LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) 953 | 954 | .PHONY : clean_libs 955 | clean_libs : $(LIB_CLEAN_TARGETS) 956 | 957 | ifneq ($(strip $(LIB_CLEAN_TARGETS)),) 958 | $(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: 959 | @$(ECHO) Info: Cleaning $* 960 | $(MAKE) --no-print-directory -C $* clean 961 | endif 962 | 963 | .PHONY: clean_elf_derived_files 964 | clean_elf_derived_files: mem_init_clean 965 | 966 | # Clean application and all makeable libraries including the BSP. 967 | .PHONY : clean_all 968 | clean_all : clean mem_init_clean clean_libs 969 | 970 | # Include the dependency files unless the make goal is performing a clean 971 | # of the application. 972 | ifneq ($(firstword $(MAKECMDGOALS)),clean) 973 | ifneq ($(firstword $(MAKECMDGOALS)),clean_all) 974 | -include $(APP_DEPS) 975 | endif 976 | endif 977 | 978 | .PHONY : download-elf 979 | download-elf : $(ELF) 980 | @if [ "$(DOWNLOAD)" = "none" ]; \ 981 | then \ 982 | $(ECHO) Downloading $(ELF) not supported; \ 983 | else \ 984 | $(ECHO) Info: Downloading $(ELF); \ 985 | $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ 986 | fi 987 | 988 | # Delete the target of a rule if it has changed and its commands exit 989 | # with a nonzero exit status. 990 | .DELETE_ON_ERROR: 991 | 992 | # Rules for flash programming commands 993 | PROGRAM_FLASH_SUFFIX := -program 994 | PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) 995 | 996 | .PHONY : program-flash 997 | program-flash : $(PROGRAM_FLASH_TARGET) 998 | 999 | .PHONY : $(PROGRAM_FLASH_TARGET) 1000 | $(PROGRAM_FLASH_TARGET) : flash 1001 | @if [ "$(FLASHPROG)" = "none" ]; \ 1002 | then \ 1003 | $(ECHO) Programming flash not supported; \ 1004 | else \ 1005 | $(ECHO) Info: Programming $(basename $@).flash; \ 1006 | if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ 1007 | then \ 1008 | $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ 1009 | $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ 1010 | else \ 1011 | $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ 1012 | $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ 1013 | fi \ 1014 | fi 1015 | 1016 | 1017 | # Rules for simulating with an HDL Simulator [QSYS only] 1018 | ifeq ($(QSYS),1) 1019 | IP_MAKE_SIMSCRIPT := ip-make-simscript 1020 | 1021 | ifeq ($(VSIM),) 1022 | VSIM_EXE := $(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim 1023 | ifeq ($(ENABLE_VSIM_GUI),1) 1024 | VSIM := $(VSIM_EXE) -gui 1025 | else 1026 | VSIM := $(VSIM_EXE) -c 1027 | endif # ENABLE_VSIM_GUI == 1 1028 | endif # VSIM not set 1029 | 1030 | ifeq ($(SPD),) 1031 | ifneq ($(ABS_QUARTUS_PROJECT_DIR),) 1032 | ifneq ($(SOPC_NAME),) 1033 | SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd 1034 | endif # SOPC_NAME set 1035 | endif # ABS_QUARTUS_PROJECT_DIR set 1036 | endif # SPD == empty string 1037 | 1038 | ifeq ($(MSIM_SCRIPT),) 1039 | SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim 1040 | MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl 1041 | endif # MSIM_SCRIPT == empty string 1042 | 1043 | ifeq ($(MAKE_VERSION),3.81) 1044 | ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) 1045 | else 1046 | ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) 1047 | endif 1048 | 1049 | $(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) 1050 | ifeq ($(SPD),) 1051 | $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) 1052 | endif 1053 | @$(MKDIR) $(SIM_SCRIPT_DIR) 1054 | $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) 1055 | 1056 | VSIM_COMMAND = \ 1057 | cd $(dir $(MSIM_SCRIPT)) && \ 1058 | $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" 1059 | 1060 | .PHONY: sim 1061 | sim: $(MSIM_SCRIPT) mem_init_generate 1062 | ifeq ($(MSIM_SCRIPT),) 1063 | $(error MSIM_SCRIPT not set) 1064 | endif 1065 | $(VSIM_COMMAND) 1066 | 1067 | endif # QSYS == 1 1068 | 1069 | 1070 | #------------------------------------------------------------------------------ 1071 | # ELF TARGET RULE 1072 | #------------------------------------------------------------------------------ 1073 | # Rule for constructing the executable elf file. 1074 | $(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) 1075 | @$(ECHO) Info: Linking $@ 1076 | $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) 1077 | ifneq ($(DISABLE_ELFPATCH),1) 1078 | $(ELFPATCH) $@ $(ELF_PATCH_FLAG) 1079 | endif 1080 | ifneq ($(DISABLE_STACKREPORT),1) 1081 | @bash -c "$(STACKREPORT) $@" 1082 | endif 1083 | 1084 | $(OBJDUMP_NAME) : $(ELF) 1085 | @$(ECHO) Info: Creating $@ 1086 | $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ 1087 | 1088 | # Rule for printing the name of the elf file 1089 | .PHONY: print-elf-name 1090 | print-elf-name: 1091 | @$(ECHO) $(ELF) 1092 | 1093 | 1094 | -------------------------------------------------------------------------------- /NIOS_SOFT/libs/cxd2545/cxd2545.c: -------------------------------------------------------------------------------- 1 | /* 2 | * cxd2545.c 3 | * 4 | * Created on: 20.03.2021 5 | * Author: VBKesha 6 | */ 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | 13 | #include "cxd2545.h" 14 | #include "cxd2545_ctrl.h" 15 | 16 | uint32_t zone[] = {13500, 27000, 45000, 63000, 85500, 103500, 130500, 153000, 175500, 207000, 234000, 265500, 297000, 999999}; 17 | uint32_t sect_pet_track[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23}; 18 | 19 | typedef struct cxd2545_t { 20 | uint8_t state; 21 | uint32_t sector; 22 | uint16_t asq_jump; 23 | uint8_t cur_zone; 24 | 25 | uint32_t offset; 26 | uint32_t lead_out; 27 | uint32_t max_sector; 28 | } cxd2545; 29 | 30 | static cxd2545 cxd_inst; 31 | static alt_irq_context ictx; 32 | 33 | void cxd2545_init(uint32_t offset, uint32_t lead_out, uint32_t max_sector){ 34 | cxd_inst.state = 0; 35 | cxd_inst.sector = 0; 36 | cxd_inst.asq_jump = 0; 37 | cxd_inst.cur_zone = 0; 38 | 39 | cxd_inst.offset = offset; 40 | cxd_inst.lead_out = lead_out; 41 | cxd_inst.max_sector = max_sector; 42 | cxd2545_set_trk0(cxd_inst.sector); 43 | printf("Offset %lu, Out %lu, max_sector %lu\r\n", offset, lead_out, max_sector); 44 | } 45 | 46 | uint32_t cxd2545_cur_sector(){ 47 | return cxd_inst.sector; 48 | } 49 | 50 | uint32_t cxd2545_get_offset(){ 51 | return cxd_inst.offset; 52 | } 53 | 54 | void cxd2545_set_state(enum CXD2545_STATES state){ 55 | cxd_inst.state = state; 56 | } 57 | 58 | uint32_t cxd2545_get_state(){ 59 | return cxd_inst.state; 60 | } 61 | 62 | void cxd2545_set_asq_jump(uint16_t jump){ 63 | cxd_inst.asq_jump = jump; 64 | } 65 | 66 | 67 | uint16_t cxd2545_get_asq_jump(){ 68 | return cxd_inst.asq_jump; 69 | } 70 | 71 | uint32_t cxd2545_get_sector(){ 72 | return cxd_inst.sector; 73 | } 74 | 75 | void cxd2545_next_sector(){ 76 | if(cxd_inst.sector < cxd_inst.max_sector){ 77 | cxd_inst.sector++; 78 | } else { 79 | cxd2545_dma_drain_on(); 80 | cxd2545_set_state(CXD_2545_IDLE); 81 | } 82 | } 83 | 84 | uint8_t cxd2545_servo_valid(){ 85 | return cxd_inst.sector < cxd_inst.max_sector; 86 | 87 | } 88 | 89 | void cxd2545_change_sector(uint32_t step, uint8_t rev){ 90 | ictx = alt_irq_disable_all(); 91 | 92 | cxd2545_set_state(CXD_2545_IDLE); 93 | cxd2545_dma_drain_on(); 94 | 95 | while(step != 0){ 96 | if(rev == 0){ 97 | uint32_t sbze = zone[cxd_inst.cur_zone] - cxd_inst.sector; 98 | uint32_t sbreq = step*sect_pet_track[cxd_inst.cur_zone]; 99 | uint32_t do_steps = ((sbze > sbreq) ? sbreq : sbze) / sect_pet_track[cxd_inst.cur_zone]; 100 | cxd_inst.sector += do_steps*sect_pet_track[cxd_inst.cur_zone]; 101 | if(cxd_inst.sector > cxd_inst.max_sector){ 102 | cxd_inst.sector = cxd_inst.lead_out; 103 | break; 104 | } 105 | step -= do_steps; 106 | if(step > 0){ 107 | cxd_inst.cur_zone++; 108 | } 109 | } else { 110 | uint32_t sect_before_ze; 111 | uint32_t do_steps; 112 | uint32_t req_sect_step = step*sect_pet_track[cxd_inst.cur_zone]; 113 | 114 | if(cxd_inst.cur_zone > 0){ 115 | sect_before_ze = cxd_inst.sector - zone[cxd_inst.cur_zone-1]; 116 | } else { 117 | sect_before_ze = req_sect_step; 118 | } 119 | 120 | do_steps = ((sect_before_ze > req_sect_step) ? req_sect_step : sect_before_ze) / sect_pet_track[cxd_inst.cur_zone]; 121 | if(cxd_inst.sector > (do_steps*sect_pet_track[cxd_inst.cur_zone])){ 122 | cxd_inst.sector -= do_steps*sect_pet_track[cxd_inst.cur_zone]; 123 | } else { 124 | cxd_inst.sector = 0; 125 | break; 126 | } 127 | step -= do_steps; 128 | if((cxd_inst.cur_zone > 0) && (step > 0)){ 129 | cxd_inst.cur_zone--; 130 | } 131 | } 132 | } 133 | 134 | cxd2545_set_trk0(cxd_inst.sector); 135 | 136 | alt_irq_enable_all(ictx); 137 | } 138 | -------------------------------------------------------------------------------- /NIOS_SOFT/libs/display/display.c: -------------------------------------------------------------------------------- 1 | /* 2 | * display.c 3 | * 4 | * Created on: 26.02.2023 5 | * Author: VBKesha 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | 12 | #include "display.h" 13 | 14 | #define HEX_CLOSE 0x46FF0000 15 | #define HEX_OPEN 0x40FF0000 16 | #define HEX_SDE 0x12210600 17 | static uint8_t hexseg[] = {0x40, 0x79, 0x24, 0x30, 0x19, 0x12, 0x02, 0x78, 0x00, 0x10}; 18 | static uint32_t isOpen = 1; 19 | static uint8_t save_num = 0; 20 | 21 | void display_set_open(){ 22 | isOpen = 1; 23 | display_num_game(save_num); 24 | } 25 | 26 | void display_set_close(){ 27 | isOpen = 0; 28 | display_num_game(save_num); 29 | } 30 | 31 | 32 | void display_num_game(uint8_t num){ 33 | uint8_t r,l; 34 | 35 | save_num = num; 36 | 37 | l = num % 10; 38 | r = num / 10; 39 | 40 | IOWR(HEX4_BASE, 0, ((isOpen) ? HEX_OPEN : HEX_CLOSE) | (hexseg[r] << 8) | hexseg[l]); 41 | } 42 | 43 | void diaplay_sd_err(uint8_t num){ 44 | IOWR(HEX4_BASE, 0, HEX_SDE | hexseg[num]); 45 | 46 | } 47 | -------------------------------------------------------------------------------- /NIOS_SOFT/libs/sectors/sector_reader.c: -------------------------------------------------------------------------------- 1 | /* 2 | * sector_reader.c 3 | * 4 | * Created on: 07.09.2020 5 | * Author: VBKesha 6 | */ 7 | 8 | #include 9 | #include 10 | #include 11 | #include 12 | //#define DEBUG 13 | #include 14 | 15 | #define CD_SECTOR_SIZE (2364) 16 | #define SD_SECTOR_SIZE (512) 17 | 18 | 19 | static sdcard_inst * sdcard; 20 | static uint32_t cur_sector_in_buff = 0xFFFFFFFF; 21 | static uint8_t sdbuff[SD_SECTOR_SIZE] __attribute__((section(".sgdma"))); 22 | 23 | static volatile uint8_t sectors[2][CD_SECTOR_SIZE] __attribute__((section(".sgdma"))); 24 | 25 | static uint8_t cur_buff_t; 26 | static uint8_t cur_Buff_d; 27 | 28 | void sector_reader_init(sdcard_inst * inst){ 29 | sdcard = inst; 30 | 31 | cur_buff_t = 0; 32 | cur_Buff_d = 0; 33 | } 34 | 35 | void sector_reader_swap(){ 36 | cur_buff_t = (cur_buff_t == 0) ? 1 : 0; 37 | cur_Buff_d = 0; 38 | } 39 | 40 | uint8_t sector_reader_is_done(uint32_t ** buff_addr){ 41 | *buff_addr = (uint32_t *)§ors[cur_buff_t][0]; 42 | return cur_Buff_d; 43 | } 44 | 45 | void sector_reader_read(uint32_t sector, uint32_t ** buff_addr){ 46 | uint32_t need_sector; 47 | uint16_t offset; 48 | uint16_t byte_readed; 49 | uint16_t len; 50 | 51 | need_sector = (sector * CD_SECTOR_SIZE) / SD_SECTOR_SIZE; 52 | offset = (sector * CD_SECTOR_SIZE) % SD_SECTOR_SIZE; 53 | dbg_printf("RD[%08u] %08u:%03u\t\n", sector, need_sector, offset); 54 | byte_readed = 0; 55 | while(byte_readed < CD_SECTOR_SIZE){ 56 | if(cur_sector_in_buff != need_sector){ 57 | sdcard_read_sector(sdcard, need_sector, sdbuff); 58 | cur_sector_in_buff = need_sector; 59 | } 60 | need_sector++; 61 | len = (SD_SECTOR_SIZE - offset) < (CD_SECTOR_SIZE - byte_readed) ? 62 | (SD_SECTOR_SIZE - offset) : (CD_SECTOR_SIZE - byte_readed); 63 | dbg_printf("Len: %03u\r\n", len); 64 | for(uint16_t i=0; i 8 | #include 9 | #include 10 | #include 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | #include 17 | 18 | #include "sdcard.h" 19 | #include "sector_reader.h" 20 | #include "cxd2545.h" 21 | #include "cxd2545_ctrl.h" 22 | #include "sens_ctrl.h" 23 | #include "sgdma.h" 24 | #include "display.h" 25 | 26 | 27 | 28 | #define SDCARD_SPI_ADDR SDCARD_SPI_BASE 29 | 30 | #define DOOR_OPEN 0x01 31 | #define DOOR_CLOSE 0x02 32 | #define PREV_GAME 0x08 33 | #define NEXT_GAME 0x04 34 | 35 | sdcard_inst sdcard; 36 | 37 | typedef struct image_item_t { 38 | uint32_t offset; 39 | uint32_t lead_out; 40 | uint32_t disk_size; 41 | char name[20]; 42 | } image_item; 43 | 44 | typedef struct image_game_list_t { 45 | uint32_t magic; 46 | image_item item[73]; 47 | } image_game_list; 48 | 49 | typedef union toc_sector_t { 50 | image_game_list games; 51 | uint8_t raw[2364]; 52 | } toc_sector; 53 | 54 | toc_sector * game_list; 55 | 56 | static void alt_putchar(char c){ 57 | while((IORD(UART_DEBUG_BASE, 2) & ALTERA_AVALON_UART_STATUS_TRDY_MSK) == 0){} 58 | IOWR(UART_DEBUG_BASE, 1, c); 59 | } 60 | 61 | char inkey(){ 62 | 63 | return ((IORD(UART_DEBUG_BASE, 2) & ALTERA_AVALON_UART_STATUS_RRDY_MSK) != 0) ? IORD(UART_DEBUG_BASE, 0) : 0x00 ; 64 | } 65 | 66 | int write(int file, const void *ptr, size_t len){ 67 | const char * cptr = ptr; 68 | int i; 69 | for(i=0; igames.magic); 116 | if(game_list->games.magic != 0xAB031337){ 117 | diaplay_sd_err(9); 118 | while(1){}; 119 | } 120 | 121 | uint8_t max_games; 122 | while(game_list->games.item[sel].offset != 0){ 123 | get_gname(game_list->games.item[sel].name, game_name); 124 | printf("%u - %s[%lu:%lu:%lu]\r\n", sel, game_name, game_list->games.item[sel].offset, game_list->games.item[sel].lead_out, game_list->games.item[sel].disk_size); 125 | sel++; 126 | } 127 | max_games = sel; 128 | 129 | usleep(100000); 130 | 131 | sel=0; 132 | old_sel = sel; 133 | 134 | while(1){ 135 | cxd2545_set_state(CXD_2545_IDLE); 136 | cxd2545_dma_drain_off(); 137 | sector_reader_read(0, &data); 138 | game_list = (toc_sector *) (uint32_t *)data; 139 | display_set_open(); 140 | cxd2545_set_door(0); 141 | while(1){ 142 | key = IORD(BUTTONS_BASE, 3); 143 | IOWR(BUTTONS_BASE, 3, key); 144 | uart_key = inkey(); 145 | if((key & NEXT_GAME) || (uart_key == '/')){ 146 | sel++; 147 | if(game_list->games.item[sel].offset == 0){ 148 | sel = 0; 149 | } 150 | } 151 | 152 | if((key & PREV_GAME) || (uart_key == '.')){ 153 | if(sel == 0){ 154 | sel = max_games - 1; 155 | } else { 156 | sel--; 157 | } 158 | 159 | } 160 | if(old_sel != sel){ 161 | get_gname(game_list->games.item[sel].name, game_name); 162 | printf("%u - %s[%lu:%lu:%lu]\r\n", sel, game_name, game_list->games.item[sel].offset, game_list->games.item[sel].lead_out, game_list->games.item[sel].disk_size); 163 | old_sel=sel; 164 | } 165 | 166 | if((key & DOOR_CLOSE) || (uart_key == ']')){ 167 | display_set_close(); 168 | get_gname(game_list->games.item[sel].name, game_name); 169 | printf("%u - %s[%lu:%lu:%lu]\r\n", sel, game_name, game_list->games.item[sel].offset, game_list->games.item[sel].lead_out, game_list->games.item[sel].disk_size); 170 | cxd2545_init(game_list->games.item[sel].offset, game_list->games.item[sel].lead_out, game_list->games.item[sel].disk_size); 171 | cxd2545_set_door(1); 172 | break; 173 | } 174 | 175 | display_num_game(sel); 176 | } 177 | 178 | printf("Start emulation!\r\n"); 179 | while(1){ 180 | 181 | if(cxd2545_get_state() == CXD_2545_WAITDATA){ 182 | cxd2545_dma_drain_off(); 183 | if(sgdma_is_working() != 1){ 184 | cxd2545_tst_start(); 185 | 186 | sector_reader_read(cxd2545_cur_sector() + cxd2545_get_offset(), &data); 187 | sgdma_send_buffer((uint8_t *)data, 2364); 188 | cxd2545_set_state(CXD_2545_OUTPUT); 189 | cxd2545_next_sector(); 190 | sector_reader_swap(); 191 | 192 | cxd2545_tst_stop(); 193 | } 194 | } 195 | 196 | if(cxd2545_get_state() == CXD_2545_OUTPUT){ 197 | if(sector_reader_is_done(&data) == 0){ 198 | sector_reader_read(cxd2545_cur_sector() + cxd2545_get_offset(), &data); 199 | } 200 | } 201 | 202 | key = IORD(BUTTONS_BASE, 3); 203 | IOWR(BUTTONS_BASE, 3, key); 204 | uart_key = inkey(); 205 | if((key & DOOR_OPEN) || (uart_key == '[')){ 206 | printf("Stop emulation!\r\n"); 207 | break; 208 | } 209 | } 210 | } 211 | return 0; 212 | } 213 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PSX_CDEMU_1 -------------------------------------------------------------------------------- /emu_image_creator/headers/nrg5_parser.h: -------------------------------------------------------------------------------- 1 | #ifndef NRG5_PARSER_H_INCLUDED 2 | #define NRG5_PARSER_H_INCLUDED 3 | 4 | /* 5 | 12 Text ISRC (or NULLs) 6 | 2 16bit Sector size in the image file (bytes) 7 | 2 16bit Mode of the data in the image file (values already found: 0x0700 for audio; 0x1000 for audio with sub-channel; 0x0000 for data; 0x0500 for raw data; 0x0f00 for raw data with sub-channel; 0x0300 for Mode 2 Form 1 data; 0x0600 for raw Mode 2/form 1 data; 0x1100 for raw Mode 2/form 1 data with sub-channel) 8 | 2 16bit Unknown (always 0x0001 found) 9 | 8 64bit Index0 (Pre-gap) (bytes) 10 | 8 64bit Index1 (Start of track) (bytes) 11 | 8 64bit End of track + 1 (bytes) 12 | */ 13 | typedef struct nrg_daox_item_t{ 14 | char ISRC[12]; 15 | uint16_t Sector_Size; 16 | uint16_t Mode; 17 | uint16_t Unknow; 18 | uint64_t PreGap_Offset; 19 | uint64_t Track_Offset; 20 | uint64_t Next_Track_Offset; 21 | } nrg_daox_item; 22 | 23 | /* 24 | 13 Text UPC (or NULLs) 25 | 1 8-bit Padding? (always NULL found)(Zero termination??) 26 | 2 16-bit Toc type (values already found: 0x0000 for audio; 0x0001 for data; 0x2001 for Mode 2/form 1 data) 27 | 1 8bit First track in the session 28 | 1 8bit Last track in the session 29 | */ 30 | 31 | typedef struct nrg_daox_t { 32 | char UPC[14]; 33 | uint16_t TOC_Type; 34 | uint8_t First_Track; 35 | uint8_t Last_Track; 36 | nrg_daox_item items[99]; 37 | } nrg_daox; 38 | 39 | uint8_t parse_nrg(FILE * nrg, nrg_daox * disk_daox); 40 | 41 | 42 | #endif // NRG5_PARSER_H_INCLUDED 43 | -------------------------------------------------------------------------------- /emu_image_creator/headers/tools.h: -------------------------------------------------------------------------------- 1 | #ifndef TOOLS_H_INCLUDED 2 | #define TOOLS_H_INCLUDED 3 | 4 | #define IMAGE_SECTOR_SIZE (2352) 5 | #define IMAGE_SUBQ_SIZE (12) 6 | 7 | void lba_to_msf(const uint32_t lba, uint8_t * min, uint8_t * sec, uint8_t * frame); 8 | uint8_t bcd_to_hex(uint8_t num); 9 | void swap_bytes(uint8_t in_sector[IMAGE_SECTOR_SIZE]); 10 | void l2b(uint8_t in_sector[IMAGE_SECTOR_SIZE]); 11 | void gen_subq(uint8_t track_mode, uint8_t track_num, uint32_t abs_sect, uint32_t rel_sect, uint8_t subq[IMAGE_SUBQ_SIZE]); 12 | void print_subq(uint8_t subq[IMAGE_SUBQ_SIZE]); 13 | void scramb(uint8_t in_sector[IMAGE_SECTOR_SIZE]); 14 | void msb_to_lsb(uint8_t * inout, uint8_t len); 15 | 16 | 17 | #endif // TOOLS_H_INCLUDED 18 | -------------------------------------------------------------------------------- /emu_image_creator/libs/nrg5/nrg5_parser.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "nrg5_parser.h" 4 | 5 | uint8_t NER5_HDR[4] = {'N', 'E', 'R', '5'}; 6 | uint8_t CUEX_HDR[4] = {'C', 'U', 'E', 'X'}; 7 | uint8_t DAOX_HDR[4] = {'D', 'A', 'O', 'X'}; 8 | uint8_t END_HDR[4] = {'E', 'N', 'D', '!'}; 9 | 10 | static uint8_t check_header(const uint8_t * hdr1, const uint8_t * hdr2); 11 | static void read_be_uint(void * value, uint8_t size, FILE * file); 12 | static void parse_nrg_daox(FILE * file, nrg_daox * daox); 13 | 14 | 15 | uint8_t parse_nrg(FILE* nrg, nrg_daox * disk_daox) { 16 | uint8_t buff[4]; 17 | uint64_t chunks_offset; 18 | uint32_t chunk_size; 19 | uint8_t ret = 3; 20 | 21 | int32_t fsize; 22 | fseek(nrg, 0, SEEK_END); 23 | fsize = ftell(nrg); 24 | printf("File size: %d\r\n", fsize); 25 | 26 | // READ HEADER 27 | 28 | fseek(nrg, fsize - 12, SEEK_SET); 29 | fread(buff, 4, 1, nrg); 30 | if(check_header(buff, NER5_HDR) != 1) { 31 | printf("UNKNOW FILE FORMAT\r\n"); 32 | fclose(nrg); 33 | return 2; 34 | } 35 | 36 | read_be_uint(&chunks_offset, sizeof(chunks_offset), nrg); 37 | printf("First chunk: %ld\r\n", chunks_offset); 38 | 39 | fseek(nrg, chunks_offset, SEEK_SET); 40 | 41 | 42 | do { 43 | fread(buff, 4, 1, nrg); 44 | read_be_uint(&chunk_size, sizeof(chunk_size), nrg); 45 | 46 | printf("Found chunk: "); 47 | for(uint8_t i=0; i<4; i++) { 48 | printf("%c", buff[i]); 49 | } 50 | printf(" size: %d\r\n", chunk_size); 51 | 52 | if(check_header(buff, DAOX_HDR) == 1){ 53 | parse_nrg_daox(nrg, disk_daox); 54 | ret = 0; 55 | } else { 56 | fseek(nrg, chunk_size, SEEK_CUR); 57 | }; 58 | 59 | } while(check_header(buff, END_HDR) != 1); 60 | 61 | return ret; 62 | } 63 | 64 | void print_nrg_daox_item(nrg_daox_item * item){ 65 | printf("\t Sector size: %u\r\n", item->Sector_Size); 66 | printf("\t Mode: %04X\r\n", item->Mode); 67 | printf("\t Unknow: %04X\r\n", item->Unknow); 68 | printf("\t PreGap Offset: %llu Size: %llu Sectors: %llu\r\n", item->PreGap_Offset, item->Track_Offset - item->PreGap_Offset, (item->Track_Offset - item->PreGap_Offset) / item->Sector_Size); 69 | printf("\t Track Offset: %llu Size: %llu Sectors: %llu\r\n", item->Track_Offset, item->Next_Track_Offset - item->Track_Offset, (item->Next_Track_Offset - item->Track_Offset) / item->Sector_Size); 70 | } 71 | 72 | void print_nrg_daox(nrg_daox * daox){ 73 | printf("TOC Type: %04X\r\n", daox->TOC_Type); 74 | printf("FirstTrack: %u\r\n", daox->First_Track); 75 | printf("LastTrack: %u\r\n", daox->Last_Track); 76 | for(uint8_t i=0; iLast_Track; i++){ 77 | printf("Track: %u\r\n", i+1); 78 | print_nrg_daox_item(&daox->items[i]); 79 | } 80 | } 81 | 82 | void parse_nrg_daox_item(FILE * file, nrg_daox_item * daox_item){ 83 | fread(daox_item->ISRC, sizeof(daox_item->ISRC), 1, file); 84 | read_be_uint(&daox_item->Sector_Size, sizeof(daox_item->Sector_Size), file); 85 | read_be_uint(&daox_item->Mode, sizeof(daox_item->Mode), file); 86 | read_be_uint(&daox_item->Unknow, sizeof(daox_item->Unknow), file); 87 | 88 | read_be_uint(&daox_item->PreGap_Offset, sizeof(daox_item->PreGap_Offset), file); 89 | read_be_uint(&daox_item->Track_Offset, sizeof(daox_item->Track_Offset), file); 90 | read_be_uint(&daox_item->Next_Track_Offset, sizeof(daox_item->Next_Track_Offset), file); 91 | } 92 | 93 | void parse_nrg_daox(FILE * file, nrg_daox * daox){ 94 | uint32_t tmp; 95 | fread(&tmp, 4, 1, file); 96 | fread(daox->UPC, sizeof(daox->UPC), 1, file); 97 | read_be_uint(&daox->TOC_Type, sizeof(daox->TOC_Type), file); 98 | read_be_uint(&daox->First_Track, sizeof(daox->First_Track), file); 99 | read_be_uint(&daox->Last_Track, sizeof(daox->Last_Track), file); 100 | 101 | 102 | for(uint8_t i=0; iLast_Track; i++){ 103 | parse_nrg_daox_item(file, &daox->items[i]); 104 | } 105 | print_nrg_daox(daox); 106 | } 107 | 108 | static void read_be_uint(void * value, uint8_t size, FILE * file){ 109 | uint8_t buff[32]; 110 | uint8_t * val = value; 111 | fread(buff, size, 1, file); 112 | for(uint8_t i=0; i 2 | #include 3 | #include 4 | 5 | #include "tools.h" 6 | #include "nrg5_parser.h" 7 | 8 | typedef struct toc_struct_t { 9 | uint8_t items; 10 | uint8_t subq[101][IMAGE_SUBQ_SIZE]; 11 | } toc_struct; 12 | 13 | typedef struct image_item_t { 14 | uint32_t offset; 15 | uint32_t lead_out; 16 | uint32_t disk_size; 17 | char name[20]; 18 | } image_item; 19 | 20 | typedef struct image_game_list_t { 21 | uint32_t magic; 22 | image_item item[73]; 23 | } image_game_list; 24 | 25 | typedef union toc_sector_t { 26 | image_game_list games; 27 | uint8_t raw[2364]; 28 | } toc_sector; 29 | 30 | #define SUBQ_CTRL_ADDR (0) 31 | #define SUBQ_TNO (1) 32 | #define SUBQ_INDEX (2) 33 | #define SUBQ_MIN (3) 34 | #define SUBQ_SEC (4) 35 | #define SUBQ_FRAME (5) 36 | #define SUBQ_ZERO (6) 37 | #define SUBQ_AMIN (7) 38 | #define SUBQ_ASEC (8) 39 | #define SUBQ_AFRAME (9) 40 | #define SUBQ_CRC_L (10) 41 | #define SUBQ_CRC_H (11) 42 | 43 | uint8_t sector_header[12] = {0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00}; 44 | 45 | nrg_daox disk_daox; 46 | toc_struct st_toc; 47 | 48 | uint8_t generate_toc(toc_struct * toc, nrg_daox * disk_daox); 49 | uint8_t write_leadin(FILE * out_file, toc_struct * toc); 50 | uint8_t write_tracks(nrg_daox * disk_daox, FILE * read_data, FILE * out_file, uint32_t * abs_pos); 51 | uint8_t write_track_part(uint8_t track, nrg_daox_item * item, uint8_t type, FILE * read_data, FILE * out_file, uint32_t * abs_pos); 52 | uint8_t write_leadout(FILE * out_image, uint32_t * abs_pos); 53 | 54 | 55 | 56 | int main(int argc, char *argv[]) { 57 | 58 | FILE * nrg; 59 | FILE * out_image; 60 | uint32_t abs_pos; 61 | uint32_t img_num; 62 | uint32_t img_offset; 63 | char img_name[21]; 64 | 65 | toc_sector image_toc; 66 | printf("Sizeof: %u\r\n", sizeof(image_toc)); 67 | memset(image_toc.raw, 0, sizeof(image_toc)); 68 | image_toc.games.magic=0xAB031337; 69 | 70 | if(argc < 2){ 71 | printf("No images select\r\n"); 72 | return 0; 73 | } 74 | 75 | 76 | out_image = fopen("sd_image.img", "wb"); 77 | fwrite(image_toc.raw, sizeof(image_toc), 1, out_image); 78 | 79 | img_offset = 1; 80 | img_num = 0; 81 | 82 | for(uint8_t i=1; iLast_Track; trk++) { 124 | printf("Write track: %d\r\n", trk); 125 | if((disk_daox->items[trk].Sector_Size != 2352) && (disk_daox->items[trk].Sector_Size != 2336)) { 126 | printf("Unknow sector size: %u\r\n", disk_daox->items[trk].Sector_Size); 127 | return 1; 128 | } 129 | write_track_part(trk+1, &disk_daox->items[trk], 0, read_data, out_file, abs_pos); 130 | write_track_part(trk+1, &disk_daox->items[trk], 1, read_data, out_file, abs_pos); 131 | } 132 | printf("ABS: %u\r\n", abs_pos); 133 | return 0; 134 | } 135 | 136 | uint8_t write_track_part(uint8_t track, nrg_daox_item * item, uint8_t type, FILE * read_data, FILE * out_file, uint32_t * abs_pos) { 137 | uint64_t start_offset; 138 | uint64_t end_offset; 139 | uint64_t pregap_size; 140 | uint64_t sector_count; 141 | 142 | uint8_t rm, rs, rf; 143 | uint8_t am, as, af; 144 | uint8_t subq[IMAGE_SUBQ_SIZE]; 145 | uint8_t sector[IMAGE_SECTOR_SIZE]; 146 | 147 | start_offset = (type == 0) ? item->PreGap_Offset : item->Track_Offset; 148 | end_offset = (type == 0) ? item->Track_Offset : item->Next_Track_Offset; 149 | pregap_size = (item->Track_Offset - item->PreGap_Offset) / item->Sector_Size; 150 | 151 | sector_count = (end_offset - start_offset) / item->Sector_Size; 152 | 153 | fseek(read_data, start_offset, SEEK_SET); 154 | printf("Sector count: %llu\r\n", start_offset); 155 | 156 | memset(sector, 0, sizeof(sector)); 157 | 158 | for(uint32_t i=0; iSector_Size], item->Sector_Size, 1, read_data); 160 | 161 | switch(item->Mode) { 162 | case 0x0300: 163 | memcpy(sector, sector_header, sizeof(sector_header)); 164 | lba_to_msf(((type == 0) ? i : i + pregap_size), &rm, &rs, &rf); 165 | 166 | sector[12] = bcd_to_hex(rm); 167 | sector[13] = bcd_to_hex(rs); 168 | sector[14] = bcd_to_hex(rf); 169 | sector[15] = 0x02; 170 | 171 | case 0x0600: // Mode 2 Form 1 172 | scramb(sector); 173 | subq[SUBQ_CTRL_ADDR] = 0x41; 174 | break; 175 | 176 | case 0x0700: // audio 177 | subq[SUBQ_CTRL_ADDR] = 0x01; 178 | break; 179 | 180 | default: 181 | printf("ERROR[%04X]: No PS1 Image file????\r\n", item->Mode); 182 | return 1; 183 | break; 184 | } 185 | 186 | l2b(sector); 187 | 188 | subq[SUBQ_TNO] = bcd_to_hex(track); 189 | subq[SUBQ_INDEX] = (type == 0) ? 0 : 1; 190 | 191 | lba_to_msf(((type == 0) ? sector_count - i : i), &rm, &rs, &rf); 192 | 193 | subq[SUBQ_MIN] = bcd_to_hex(rm); 194 | subq[SUBQ_SEC] = bcd_to_hex(rs); 195 | subq[SUBQ_FRAME] = bcd_to_hex(rf); 196 | 197 | subq[SUBQ_ZERO] = 0x00; 198 | 199 | lba_to_msf(*abs_pos, &am, &as, &af); 200 | subq[SUBQ_AMIN] = bcd_to_hex(am); 201 | subq[SUBQ_ASEC] = bcd_to_hex(as); 202 | subq[SUBQ_AFRAME] = bcd_to_hex(af); 203 | 204 | subq[SUBQ_CRC_L] = 0xFF; 205 | subq[SUBQ_CRC_H] = 0xFF; 206 | 207 | msb_to_lsb(subq, sizeof(subq)); 208 | 209 | fwrite(sector, sizeof(sector), 1, out_file); 210 | fwrite(subq, sizeof(subq), 1, out_file); 211 | (*abs_pos)++; 212 | //fread(§or[2352 - item->Sector_Size], item->Sector_Size, 1, read_data); 213 | } 214 | 215 | return 0; 216 | } 217 | 218 | uint8_t write_leadout(FILE * out_file, uint32_t * abs_pos) { 219 | uint8_t rm,rs,rf; 220 | uint8_t am,as,af; 221 | uint8_t subq[IMAGE_SUBQ_SIZE]; 222 | uint8_t sector[IMAGE_SECTOR_SIZE]; 223 | 224 | uint16_t i; 225 | for(i=0; i<6750; i++){ 226 | memset(sector, 0, sizeof(sector)); 227 | subq[SUBQ_CTRL_ADDR] = 0x01; 228 | subq[SUBQ_TNO] = 0xAA; 229 | subq[SUBQ_INDEX] = 0x00; 230 | 231 | lba_to_msf(i, &rm, &rs, &rf); 232 | subq[SUBQ_MIN] = bcd_to_hex(rm); 233 | subq[SUBQ_SEC] = bcd_to_hex(rs); 234 | subq[SUBQ_FRAME] = bcd_to_hex(rf); 235 | 236 | subq[SUBQ_ZERO] = 0x00; 237 | 238 | lba_to_msf(*abs_pos, &am, &as, &af); 239 | subq[SUBQ_AMIN] = bcd_to_hex(am); 240 | subq[SUBQ_ASEC] = bcd_to_hex(as); 241 | subq[SUBQ_AFRAME] = bcd_to_hex(af); 242 | 243 | subq[SUBQ_CRC_L] = 0xFF; 244 | subq[SUBQ_CRC_H] = 0xFF; 245 | 246 | msb_to_lsb(subq, sizeof(subq)); 247 | 248 | fwrite(sector, sizeof(sector), 1, out_file); 249 | fwrite(subq, sizeof(subq), 1, out_file); 250 | (*abs_pos)++; 251 | } 252 | 253 | return 0; 254 | } 255 | 256 | uint8_t write_leadin(FILE * out_file, toc_struct * toc) { 257 | uint8_t sector[IMAGE_SECTOR_SIZE]; 258 | uint8_t subq[IMAGE_SUBQ_SIZE]; 259 | uint8_t tok_item; 260 | uint8_t m, s, f; 261 | tok_item = st_toc.items; 262 | memset(sector, 0, sizeof(sector)); 263 | for(uint16_t i=0; i<4500; i++) { 264 | if((i % 4) == 0) { 265 | tok_item++; 266 | if(tok_item > st_toc.items) { 267 | tok_item = 0; 268 | } 269 | } 270 | 271 | memcpy(subq, st_toc.subq[tok_item], sizeof(subq)); 272 | lba_to_msf(i, &m, &s, &f); 273 | subq[SUBQ_MIN] = bcd_to_hex(m); 274 | subq[SUBQ_SEC] = bcd_to_hex(s); 275 | subq[SUBQ_FRAME] = bcd_to_hex(f); 276 | subq[SUBQ_CRC_L] = 0xFF; 277 | subq[SUBQ_CRC_H] = 0xFF; 278 | fwrite(sector, sizeof(sector), 1, out_file); 279 | msb_to_lsb(subq, sizeof(subq)); 280 | fwrite(subq, sizeof(subq), 1, out_file); 281 | } 282 | return 0; 283 | } 284 | 285 | uint8_t generate_toc(toc_struct * toc, nrg_daox * disk_daox) { 286 | uint32_t cur_pos; 287 | uint8_t m, s, f; 288 | uint8_t i; 289 | 290 | toc->items = 0; 291 | 292 | /* A0 DISK MODE + First Track */ 293 | toc->subq[toc->items][SUBQ_CTRL_ADDR] = 0x41; 294 | toc->subq[toc->items][SUBQ_TNO] = 0x00; 295 | toc->subq[toc->items][SUBQ_INDEX] = 0xA0; 296 | toc->subq[toc->items][SUBQ_ZERO] = 0x00; 297 | toc->subq[toc->items][SUBQ_AMIN] = bcd_to_hex(disk_daox->First_Track); 298 | toc->subq[toc->items][SUBQ_ASEC] = (disk_daox->TOC_Type >> 8) & 0xFF; 299 | toc->subq[toc->items][SUBQ_AFRAME] = 0x00; 300 | toc->items++; 301 | 302 | /* A! Last Track */ 303 | toc->subq[toc->items][SUBQ_CTRL_ADDR] = 0x41; 304 | toc->subq[toc->items][SUBQ_TNO] = 0x00; 305 | toc->subq[toc->items][SUBQ_INDEX] = 0xA1; 306 | toc->subq[toc->items][SUBQ_ZERO] = 0x00; 307 | toc->subq[toc->items][SUBQ_AMIN] = bcd_to_hex(disk_daox->Last_Track); 308 | toc->subq[toc->items][SUBQ_ASEC] = 0x00; 309 | toc->subq[toc->items][SUBQ_AFRAME] = 0x00; 310 | toc->items++; 311 | 312 | /* TOC Items */ 313 | cur_pos = 0; 314 | for(i=0; i<(disk_daox->Last_Track); i++) { 315 | uint32_t track_start = (disk_daox->items[i].Track_Offset - disk_daox->items[i].PreGap_Offset) / disk_daox->items[i].Sector_Size; 316 | cur_pos += track_start; 317 | lba_to_msf(cur_pos, &m, &s, &f); 318 | printf("Track Start[%04X][%02X:%02X:%02X]: %d \r\n", disk_daox->items[i].Mode, bcd_to_hex(m), bcd_to_hex(s), bcd_to_hex(f), cur_pos); 319 | 320 | switch(disk_daox->items[i].Mode) { 321 | case 0x0300: 322 | case 0x0600: // Mode 2 Form 1 323 | toc->subq[toc->items][SUBQ_CTRL_ADDR] = 0x41; 324 | break; 325 | 326 | case 0x0700: // audio 327 | toc->subq[toc->items][SUBQ_CTRL_ADDR] = 0x01; 328 | break; 329 | 330 | default: 331 | printf("ERROR[%04X]: No PS1 Image file????\r\n", disk_daox->items[i].Mode); 332 | return 1; 333 | break; 334 | } 335 | toc->subq[toc->items][SUBQ_TNO] = 0x00; 336 | toc->subq[toc->items][SUBQ_INDEX] = bcd_to_hex(i+1); 337 | toc->subq[toc->items][SUBQ_ZERO] = 0x00; 338 | toc->subq[toc->items][SUBQ_AMIN] = bcd_to_hex(m); 339 | toc->subq[toc->items][SUBQ_ASEC] = bcd_to_hex(s); 340 | toc->subq[toc->items][SUBQ_AFRAME] = bcd_to_hex(f); 341 | 342 | 343 | uint32_t track_size = (disk_daox->items[i].Next_Track_Offset - disk_daox->items[i].Track_Offset) / disk_daox->items[i].Sector_Size; 344 | cur_pos += track_size; 345 | toc->items++; 346 | } 347 | lba_to_msf(cur_pos, &m, &s, &f); 348 | 349 | printf("Track Start[%04X][%02X:%02X:%02X]: %d \r\n", 0x0600, bcd_to_hex(m), bcd_to_hex(s), bcd_to_hex(f), cur_pos); 350 | 351 | /* A2 Lead out time*/ 352 | toc->subq[toc->items][SUBQ_CTRL_ADDR] = 0x41; 353 | toc->subq[toc->items][SUBQ_TNO] = 0x00; 354 | toc->subq[toc->items][SUBQ_INDEX] = 0xA2; 355 | toc->subq[toc->items][SUBQ_ZERO] = 0x00; 356 | toc->subq[toc->items][SUBQ_AMIN] = bcd_to_hex(m); 357 | toc->subq[toc->items][SUBQ_ASEC] = bcd_to_hex(s); 358 | toc->subq[toc->items][SUBQ_AFRAME] = bcd_to_hex(f); 359 | 360 | 361 | return 0; 362 | } 363 | -------------------------------------------------------------------------------- /emu_image_creator/psx_image_from_nrg.cbp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 44 | 45 | -------------------------------------------------------------------------------- /emu_image_creator/src/tools.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "tools.h" 4 | 5 | static const uint8_t msb2lsb[256]; 6 | static const uint8_t scrambler[IMAGE_SECTOR_SIZE]; 7 | 8 | void msb_to_lsb(uint8_t * inout, uint8_t len) { 9 | uint8_t i; 10 | for(i=0; i