├── .appveyor.yml ├── .editorconfig ├── .gitattributes ├── .github └── CONTRIBUTING.md ├── .gitignore ├── .gitlab-ci.yml ├── .gitlab ├── issue_templates │ └── .gitempty └── merge_request_templates │ └── .gitempty ├── .gitmodules ├── .landscape.yml ├── .pyIPCMI ├── Hooks │ └── README.md ├── config.boards.ini ├── config.defaults.ini ├── config.entity.ini └── config.structure.ini ├── .readthedocs.yml ├── .travis.yml ├── AUTHORS.md ├── CHANGES.md ├── LICENSE.md ├── README.md ├── README.tpl ├── docs ├── CCLA.md ├── ChangeLog │ ├── 2014 │ │ ├── index.rst │ │ └── v0.0.0.rst │ ├── 2015 │ │ ├── index.rst │ │ ├── v0.1.0.rst │ │ ├── v0.10.0.rst │ │ ├── v0.11.0.rst │ │ ├── v0.12.0.rst │ │ ├── v0.13.0.rst │ │ ├── v0.14.0.rst │ │ ├── v0.15.0.rst │ │ ├── v0.16.0.rst │ │ ├── v0.17.0.rst │ │ ├── v0.18.0.rst │ │ ├── v0.2.0.rst │ │ ├── v0.3.0.rst │ │ ├── v0.4.0.rst │ │ ├── v0.5.0.rst │ │ ├── v0.6.0.rst │ │ ├── v0.7.0.rst │ │ ├── v0.8.0.rst │ │ └── v0.9.0.rst │ ├── 2016 │ │ ├── index.rst │ │ ├── v0.19.0.rst │ │ ├── v0.20.0.rst │ │ ├── v0.21.0.rst │ │ ├── v1.0.0.rst │ │ ├── v1.0.1.rst │ │ ├── v1.1.0.rst │ │ └── v1.x.rst │ ├── index.rst │ └── template.rst ├── ConstraintFiles │ ├── Altera │ │ ├── CycloneIII │ │ │ ├── DE0.rst │ │ │ ├── DE0nano.rst │ │ │ └── index.rst │ │ ├── StratixIV │ │ │ ├── DE4.rst │ │ │ └── index.rst │ │ ├── StratixV │ │ │ ├── DE5.rst │ │ │ └── index.rst │ │ └── index.rst │ ├── Lattice │ │ ├── ECP5 │ │ │ ├── ECP5Versa.rst │ │ │ └── index.rst │ │ └── index.rst │ ├── Xilinx │ │ ├── Artix7 │ │ │ ├── AC701.rst │ │ │ └── index.rst │ │ ├── Kintex7 │ │ │ ├── KC705.rst │ │ │ └── index.rst │ │ ├── Spartan3 │ │ │ ├── S3ESK.rst │ │ │ ├── S3SK.rst │ │ │ └── index.rst │ │ ├── Spartan6 │ │ │ ├── Atlys.rst │ │ │ └── index.rst │ │ ├── Virtex5 │ │ │ ├── ML505.rst │ │ │ ├── ML506.rst │ │ │ ├── XUPV5.rst │ │ │ └── index.rst │ │ ├── Virtex6 │ │ │ ├── ML605.rst │ │ │ └── index.rst │ │ ├── Virtex7 │ │ │ ├── VC707.rst │ │ │ └── index.rst │ │ ├── Zynq7000 │ │ │ ├── ZC706.rst │ │ │ ├── ZedBoard.rst │ │ │ └── index.rst │ │ └── index.rst │ ├── fifo │ │ ├── fifo_ic_got.rst │ │ └── index.rst │ ├── index.rst │ ├── misc │ │ ├── index.rst │ │ └── sync │ │ │ ├── index.rst │ │ │ ├── sync_Bits.rst │ │ │ ├── sync_Command.rst │ │ │ ├── sync_Reset.rst │ │ │ └── sync_Vector.rst │ └── net │ │ ├── eth │ │ ├── eth_RSLayer_GMII_GMII_KC705.rst │ │ ├── eth_RSLayer_GMII_GMII_ML505.rst │ │ ├── eth_RSLayer_GMII_GMII_ML605.rst │ │ └── index.rst │ │ └── index.rst ├── Entity.template ├── Examples │ └── index.rst ├── GetInvolved │ └── index.rst ├── ICLA.md ├── IPCores │ ├── alt │ │ └── index.rst │ ├── arith │ │ ├── arith.pkg.rst │ │ ├── arith_addw.rst │ │ ├── arith_bcdcollect.rst │ │ ├── arith_carrychain_inc.rst │ │ ├── arith_cca.rst │ │ ├── arith_convert_bin2bcd.rst │ │ ├── arith_counter_bcd.rst │ │ ├── arith_counter_free.rst │ │ ├── arith_counter_gray.rst │ │ ├── arith_counter_ring.rst │ │ ├── arith_div.rst │ │ ├── arith_firstone.rst │ │ ├── arith_muls_wide.rst │ │ ├── arith_prefix_and.rst │ │ ├── arith_prefix_or.rst │ │ ├── arith_prng.rst │ │ ├── arith_same.rst │ │ ├── arith_scaler.rst │ │ ├── arith_shifter_barrel.rst │ │ ├── arith_sqrt.rst │ │ └── index.rst │ ├── bus │ │ ├── bus_Arbiter.rst │ │ ├── index.rst │ │ ├── stream │ │ │ ├── index.rst │ │ │ ├── stream.pkg.rst │ │ │ ├── stream_Buffer.rst │ │ │ ├── stream_DeMux.rst │ │ │ ├── stream_FrameGenerator.rst │ │ │ ├── stream_Mirror.rst │ │ │ ├── stream_Mux.rst │ │ │ ├── stream_Sink.rst │ │ │ └── stream_Source.rst │ │ └── wb │ │ │ ├── index.rst │ │ │ ├── wb.pkg.rst │ │ │ ├── wb_fifo_adapter.rst │ │ │ ├── wb_ocram.rst │ │ │ └── wb_uart_wrapper.rst │ ├── cache │ │ ├── cache_cpu.rst │ │ ├── cache_mem.rst │ │ ├── cache_par.rst │ │ ├── cache_par2.rst │ │ ├── cache_replacement_policy.rst │ │ ├── cache_tagunit_par.rst │ │ ├── cache_tagunit_seq.rst │ │ └── index.rst │ ├── comm │ │ ├── comm.pkg.rst │ │ ├── comm_crc.rst │ │ ├── comm_scramble.rst │ │ ├── index.rst │ │ └── remote │ │ │ ├── index.rst │ │ │ └── remote_terminal_control.rst │ ├── common │ │ ├── components.rst │ │ ├── config.rst │ │ ├── context.rst │ │ ├── fileio.rst │ │ ├── index.rst │ │ ├── math.rst │ │ ├── strings.rst │ │ ├── utils.rst │ │ └── vectors.rst │ ├── dstruct │ │ ├── dstruct_deque.rst │ │ ├── dstruct_stack.rst │ │ └── index.rst │ ├── fifo │ │ ├── fifo.pkg.rst │ │ ├── fifo_cc_got.rst │ │ ├── fifo_cc_got_tempgot.rst │ │ ├── fifo_cc_got_tempput.rst │ │ ├── fifo_dc_got_sm.rst │ │ ├── fifo_glue.rst │ │ ├── fifo_ic_assembly.rst │ │ ├── fifo_ic_got.rst │ │ ├── fifo_shift.rst │ │ └── index.rst │ ├── index.rst │ ├── io │ │ ├── ddrio │ │ │ ├── ddrio.pkg.rst │ │ │ ├── ddrio_in.rst │ │ │ ├── ddrio_inout.rst │ │ │ ├── ddrio_out.rst │ │ │ └── index.rst │ │ ├── iic │ │ │ ├── iic.pkg.rst │ │ │ ├── iic_BusController.rst │ │ │ ├── iic_Controller.rst │ │ │ ├── iic_Controller_SFF8431.rst │ │ │ ├── iic_Switch_PCA9548A.rst │ │ │ └── index.rst │ │ ├── index.rst │ │ ├── io.pkg.rst │ │ ├── io_7SegmentMux_BCD.rst │ │ ├── io_7SegmentMux_HEX.rst │ │ ├── io_Debounce.rst │ │ ├── io_FanControl.rst │ │ ├── io_FrequencyCounter.rst │ │ ├── io_GlitchFilter.rst │ │ ├── io_KeyPadScanner.rst │ │ ├── io_PulseWidthModulation.rst │ │ ├── io_TimingCounter.rst │ │ ├── jtag │ │ │ └── index.rst │ │ ├── lcd │ │ │ ├── BCDDigit.rst │ │ │ ├── index.rst │ │ │ ├── lcd.pkg.rst │ │ │ ├── lcd_LCDBuffer.rst │ │ │ ├── lcd_LCDBusController.rst │ │ │ ├── lcd_LCDController_KS0066U.rst │ │ │ ├── lcd_LCDSynchronizer.rst │ │ │ └── lcd_dotmatrix.rst │ │ ├── mdio │ │ │ ├── index.rst │ │ │ ├── mdio_BusController.rst │ │ │ ├── mdio_Controller.rst │ │ │ └── mdio_IIC_Adapter.rst │ │ ├── ow │ │ │ ├── index.rst │ │ │ ├── ow_BusController.rst │ │ │ └── ow_Controller.rst │ │ ├── pio │ │ │ ├── index.rst │ │ │ ├── pio_fifo_in.rst │ │ │ ├── pio_fifo_out.rst │ │ │ ├── pio_in.rst │ │ │ └── pio_out.rst │ │ ├── pmod │ │ │ ├── index.rst │ │ │ ├── pmod.pkg.rst │ │ │ ├── pmod_KYPD.rst │ │ │ ├── pmod_SSD.rst │ │ │ └── pmod_USBUART.rst │ │ ├── ps2 │ │ │ └── index.rst │ │ ├── uart │ │ │ ├── index.rst │ │ │ ├── uart.pkg.rst │ │ │ ├── uart_bclk.rst │ │ │ ├── uart_fifo.rst │ │ │ ├── uart_ft245.rst │ │ │ ├── uart_rx.rst │ │ │ └── uart_tx.rst │ │ └── vga │ │ │ ├── index.rst │ │ │ ├── vga.pkg.rst │ │ │ ├── vga_phy.rst │ │ │ ├── vga_phy_ch7301c.rst │ │ │ └── vga_timing.rst │ ├── mem │ │ ├── ddr2 │ │ │ ├── ddr2_mem2mig_adapter_Spartan6.rst │ │ │ └── index.rst │ │ ├── ddr3 │ │ │ ├── ddr3_mem2mig_adapter_Series7.rst │ │ │ └── index.rst │ │ ├── index.rst │ │ ├── lut │ │ │ ├── index.rst │ │ │ └── lut_Sine.rst │ │ ├── mem.pkg.rst │ │ ├── ocram │ │ │ ├── index.rst │ │ │ ├── ocram.pkg.rst │ │ │ ├── ocram_esdp.rst │ │ │ ├── ocram_sdp.rst │ │ │ ├── ocram_sdp_wf.rst │ │ │ ├── ocram_sp.rst │ │ │ ├── ocram_tdp.rst │ │ │ ├── ocram_tdp_sim.rst │ │ │ └── ocram_tdp_wf.rst │ │ ├── ocrom │ │ │ ├── index.rst │ │ │ ├── ocrom.pkg.rst │ │ │ ├── ocrom_dp.rst │ │ │ └── ocrom_sp.rst │ │ └── sdram │ │ │ ├── index.rst │ │ │ ├── sdram_ctrl_de0.rst │ │ │ ├── sdram_ctrl_fsm.rst │ │ │ ├── sdram_ctrl_phy_de0.rst │ │ │ ├── sdram_ctrl_phy_s3esk.rst │ │ │ └── sdram_ctrl_s3esk.rst │ ├── misc │ │ ├── filter │ │ │ ├── filter_and.rst │ │ │ ├── filter_mean.rst │ │ │ ├── filter_or.rst │ │ │ └── index.rst │ │ ├── gearbox │ │ │ ├── gearbox_down_cc.rst │ │ │ ├── gearbox_down_dc.rst │ │ │ ├── gearbox_up_cc.rst │ │ │ ├── gearbox_up_dc.rst │ │ │ └── index.rst │ │ ├── index.rst │ │ ├── misc.pkg.rst │ │ ├── misc_BitwidthConverter.rst │ │ ├── misc_ByteAligner.rst │ │ ├── misc_Delay.rst │ │ ├── misc_FrequencyMeasurement.rst │ │ ├── misc_PulseTrain.rst │ │ ├── misc_Sequencer.rst │ │ ├── misc_StrobeGenerator.rst │ │ ├── misc_StrobeLimiter.rst │ │ ├── misc_WordAligner.rst │ │ ├── misc_bit_lz.rst │ │ ├── stat │ │ │ ├── index.rst │ │ │ ├── stat_Average.rst │ │ │ ├── stat_Histogram.rst │ │ │ ├── stat_Maximum.rst │ │ │ └── stat_Minimum.rst │ │ └── sync │ │ │ ├── index.rst │ │ │ ├── sync.pkg.rst │ │ │ ├── sync_Bits.rst │ │ │ ├── sync_Command.rst │ │ │ ├── sync_Pulse.rst │ │ │ ├── sync_Reset.rst │ │ │ ├── sync_Strobe.rst │ │ │ └── sync_Vector.rst │ ├── net │ │ ├── arp │ │ │ ├── arp_BroadCast_Receiver.rst │ │ │ ├── arp_BroadCast_Requester.rst │ │ │ ├── arp_Cache.rst │ │ │ ├── arp_IPPool.rst │ │ │ ├── arp_Tester.rst │ │ │ ├── arp_UniCast_Receiver.rst │ │ │ ├── arp_UniCast_Responder.rst │ │ │ ├── arp_Wrapper.rst │ │ │ └── index.rst │ │ ├── eth │ │ │ ├── eth_GEMAC_GMII.rst │ │ │ ├── eth_GEMAC_RX.rst │ │ │ ├── eth_GEMAC_TX.rst │ │ │ ├── eth_PHYController.rst │ │ │ ├── eth_PHYController_Marvell_88E1111.rst │ │ │ ├── eth_Wrapper.rst │ │ │ └── index.rst │ │ ├── icmpv4 │ │ │ ├── icmpv4_RX.rst │ │ │ ├── icmpv4_TX.rst │ │ │ ├── icmpv4_Wrapper.rst │ │ │ └── index.rst │ │ ├── icmpv6 │ │ │ ├── icmpv6_RX.rst │ │ │ ├── icmpv6_TX.rst │ │ │ ├── icmpv6_Wrapper.rst │ │ │ └── index.rst │ │ ├── index.rst │ │ ├── ipv4 │ │ │ ├── index.rst │ │ │ ├── ipv4_FrameLoopback.rst │ │ │ ├── ipv4_RX.rst │ │ │ ├── ipv4_TX.rst │ │ │ └── ipv4_Wrapper.rst │ │ ├── ipv6 │ │ │ ├── index.rst │ │ │ ├── ipv6_FrameLoopback.rst │ │ │ ├── ipv6_RX.rst │ │ │ ├── ipv6_TX.rst │ │ │ └── ipv6_Wrapper.rst │ │ ├── mac │ │ │ ├── index.rst │ │ │ ├── mac_FrameLoopback.rst │ │ │ ├── mac_RX_DestMAC_Switch.rst │ │ │ ├── mac_RX_SrcMAC_Filter.rst │ │ │ ├── mac_RX_Type_Switch.rst │ │ │ ├── mac_TX_DestMAC_Prepender.rst │ │ │ ├── mac_TX_SrcMAC_Prepender.rst │ │ │ ├── mac_TX_Type_Prepender.rst │ │ │ └── mac_Wrapper.rst │ │ ├── ndp │ │ │ ├── index.rst │ │ │ ├── ndp_DestinationCache.rst │ │ │ ├── ndp_FSMQuery.rst │ │ │ ├── ndp_NeighborCache.rst │ │ │ └── ndp_Wrapper.rst │ │ ├── net.pkg.rst │ │ ├── net_FrameChecksum.rst │ │ ├── net_FrameLoopback.rst │ │ ├── net_FramePerformanceCounter.rst │ │ ├── stack │ │ │ ├── index.rst │ │ │ ├── stack_IPv4.rst │ │ │ ├── stack_IPv6.rst │ │ │ ├── stack_MAC.rst │ │ │ ├── stack_UDPv4.rst │ │ │ └── stack_UDPv6.rst │ │ └── udp │ │ │ ├── index.rst │ │ │ ├── udp_FrameLoopback.rst │ │ │ ├── udp_RX.rst │ │ │ ├── udp_TX.rst │ │ │ └── udp_Wrapper.rst │ ├── sim │ │ ├── index.rst │ │ ├── sim_global.v08.rst │ │ ├── sim_global.v93.rst │ │ ├── sim_protected.v08.rst │ │ ├── sim_simulation.v08.rst │ │ ├── sim_simulation.v93.rst │ │ ├── sim_types.rst │ │ ├── sim_unprotected.v93.rst │ │ └── sim_waveform.rst │ ├── sort │ │ ├── index.rst │ │ ├── sort_ExpireList.rst │ │ ├── sort_InsertSort.rst │ │ ├── sort_LeastFrequentlyUsed.rst │ │ ├── sort_lru_cache.rst │ │ ├── sort_lru_list.rst │ │ └── sortnet │ │ │ ├── index.rst │ │ │ ├── sortnet.pkg.rst │ │ │ ├── sortnet_BitonicSort.rst │ │ │ ├── sortnet_MergeSort_Streamed.rst │ │ │ ├── sortnet_OddEvenMergeSort.rst │ │ │ ├── sortnet_OddEvenSort.rst │ │ │ ├── sortnet_Stream_Adapter.rst │ │ │ ├── sortnet_Stream_Adapter2.rst │ │ │ └── sortnet_Transform.rst │ └── xil │ │ ├── index.rst │ │ ├── mig │ │ ├── index.rst │ │ ├── mig_Atlys_1x128.rst │ │ └── mig_KC705_MT8JTF12864HZ_1G6.rst │ │ ├── reconfig │ │ ├── index.rst │ │ ├── reconfig_icap_fsm.rst │ │ └── reconfig_icap_wrapper.rst │ │ ├── xil.pkg.rst │ │ ├── xil_BSCAN.rst │ │ ├── xil_ChipScopeICON.rst │ │ ├── xil_DRP_BusMux.rst │ │ ├── xil_DRP_BusSync.rst │ │ ├── xil_ICAP.rst │ │ ├── xil_Reconfigurator.rst │ │ └── xil_SystemMonitor.rst ├── Interfaces │ ├── CommandStatusError.rst │ ├── FIFO.rst │ ├── Memory.rst │ ├── Stream.rst │ └── index.rst ├── Makefile ├── Miscelaneous │ └── ThirdParty.rst ├── PoCSphinx.py ├── QuickStart.rst ├── References │ ├── CmdRefs │ │ ├── Compile-Altera-ps1.rst │ │ ├── Compile-Altera-sh.rst │ │ ├── Compile-Lattice-ps1.rst │ │ ├── Compile-Lattice-sh.rst │ │ ├── Compile-OSVVM-ps1.rst │ │ ├── Compile-OSVVM-sh.rst │ │ ├── Compile-UVVM-ps1.rst │ │ ├── Compile-UVVM-sh.rst │ │ ├── Compile-Xilinx-ISE-ps1.rst │ │ ├── Compile-Xilinx-ISE-sh.rst │ │ ├── Compile-Xilinx-Vivado-ps1.rst │ │ ├── Compile-Xilinx-Vivado-sh.rst │ │ ├── Compile.rst │ │ ├── PoC.rst │ │ └── Wrapper.rst │ ├── CommandReference.rst │ ├── Database.rst │ ├── FileFormats │ │ ├── FilesFormat.rst │ │ ├── IniFormat.rst │ │ ├── RulesFormat.rst │ │ └── index.rst │ ├── KnownIssues.rst │ ├── Licenses │ │ ├── ApacheLicense2.0.rst │ │ ├── ApacheLicense2.0_CCLA.rst │ │ ├── ApacheLicense2.0_ICLA.rst │ │ ├── ArtisticLicense2.0.rst │ │ ├── Cocotb_BSDLicense.rst │ │ ├── License.rst │ │ ├── MozillaPublicLicense2.0.rst │ │ ├── UVVM_MIT.rst │ │ └── index.rst │ ├── ListOfBoards.rst │ ├── ListOfDevices.rst │ ├── NamingConventions.rst │ ├── WrapperScriptHookFiles.rst │ └── more.rst ├── ToolChains │ └── index.rst ├── UsingPoC │ ├── AddingIPCores.rst │ ├── Download.rst │ ├── Integration.rst │ ├── Miscellaneous.rst │ ├── PoCConfiguration.rst │ ├── PrecompilingVendorLibraries.rst │ ├── ProjectManagement.rst │ ├── Requirements.rst │ ├── Simulation.rst │ ├── Synthesis.rst │ ├── VHDLConfiguration.rst │ └── index.rst ├── WhatIsPoC │ ├── History.rst │ ├── SupportedToolChains.rst │ ├── WhoUsesPoC.rst │ ├── WhyShouldIUsePoC.rst │ └── index.rst ├── _extensions │ ├── DocumentMember.py │ ├── autoapi │ │ ├── __init__.py │ │ ├── apinode.py │ │ └── sphinx.py │ └── autoprogram.py ├── _static │ ├── .gitempty │ ├── css │ │ ├── custom.css │ │ └── railroad-diagrams.css │ ├── icons │ │ └── ZIP.png │ ├── images │ │ ├── .gitempty │ │ ├── active-hdl │ │ │ └── multiple.png │ │ ├── ghdl │ │ │ ├── PoC_all.png │ │ │ └── arith_prng_tb.posh.png │ │ ├── gtkwave │ │ │ └── arith_prng_tb.png │ │ └── xst │ │ │ └── arith_prng.posh.png │ ├── io │ │ ├── iic_Controller_Usage.graphml │ │ └── iic_Controller_Usage.png │ ├── javascript │ │ └── railroad-diagrams.js │ ├── logos │ │ ├── GitHub-Mark-32px.png │ │ ├── tu-dresden-resized.jpg │ │ └── tu-dresden.jpg │ ├── misc │ │ └── sync │ │ │ ├── sync_Strobe.png │ │ │ └── sync_Strobe.svg │ └── sort │ │ └── sortnet │ │ ├── sortnet_BitonicSort.png │ │ └── sortnet_BitonicSort.svg ├── _templates │ ├── .gitempty │ └── autoapi │ │ ├── module.rst │ │ └── script.rst ├── _themes │ └── .gitempty ├── _tools │ └── inventory.py ├── conf.py ├── genindex.rst ├── index.rst ├── make.ps1 ├── poc.py ├── prolog.inc ├── pyIPCMI │ └── index.rst └── shields.inc ├── lib ├── Altera.files ├── Apache License 2.0.md ├── Artistic License 2.0.md ├── Cocotb BSD License.md ├── MIT UVVM.md ├── Mozilla Public License 2.0.md ├── OSVVM.files ├── README.md ├── UVVM.files ├── Xilinx-Vivado.files └── Xilinx.files ├── netlist ├── README.md └── template.cgc ├── poc.ps1 ├── poc.sh ├── py └── .idea │ ├── .name │ ├── codeStyleSettings.xml │ ├── codeStyles │ └── codeStyleConfig.xml │ ├── encodings.xml │ ├── inspectionProfiles │ └── Project_Default.xml │ ├── markdown-exported-files.xml │ ├── markdown-navigator.xml │ ├── markdown-navigator │ └── profiles_settings.xml │ ├── misc.xml │ ├── modules.xml │ ├── py.iml │ ├── runConfigurations │ ├── __dryrun_ghdl_PoC_arith_prng.xml │ ├── __dryrun_isim_PoC_arith_prng.xml │ ├── __dryrun_rpro_PoC_arith_prng.xml │ ├── __dryrun_xsim_PoC_arith_prng.xml │ ├── asim_PoC_arith_prng.xml │ ├── configure.xml │ ├── configure___set_default_tools.xml │ ├── configure_altera.xml │ ├── configure_ghdl.xml │ ├── configure_git.xml │ ├── configure_intel.xml │ ├── configure_lattice.xml │ ├── configure_mentor_modelsim.xml │ ├── coregen_PoC_xil_mig_Atlys_1x128.xml │ ├── ghdl_PoC_arith_prng.xml │ ├── isim_PoC_arith_prng.xml │ ├── list_netlist_PoC__.xml │ ├── list_testbench_PoC__.xml │ ├── list_testbench_PoC_sort_____kind_cocotb.xml │ ├── lse_PoC_arith_prng.xml │ ├── quartus_PoC_arith_prng.xml │ ├── query_Xilinx_ISE_SettingsFile.xml │ ├── rpro_PoC_arith_prng.xml │ ├── vsim_PoC_arith_prng.xml │ ├── xsim_PoC_arith_prng___std_08.xml │ └── xst_PoC_cache_par.xml │ ├── vcs.xml │ └── workspace.xml ├── requirements.txt ├── sim ├── README.md ├── aSim.batch.tcl ├── aSim.gui.tcl ├── arith │ ├── arith_addw_tb.gtkw │ ├── arith_addw_tb.wcfg │ ├── arith_convert_bin2bcd_tb.ghdl │ ├── arith_convert_bin2bcd_tb.gtkw │ ├── arith_convert_bin2bcd_tb.wcfg │ ├── arith_convert_bin2bcd_tb.wdo │ ├── arith_counter_gray_tb.wcfg │ ├── arith_prefix_and_tb.ghdl │ ├── arith_prefix_and_tb.gtkw │ ├── arith_prefix_or_tb.ghdl │ ├── arith_prefix_or_tb.gtkw │ ├── arith_prng_tb.ghdl │ ├── arith_prng_tb.gtkw │ ├── arith_prng_tb.wcfg │ └── arith_prng_tb.wdo ├── dstruct │ ├── dstruct_deque_tb.ghdl │ ├── dstruct_deque_tb.gtkw │ ├── dstruct_stack_tb.ghdl │ └── dstruct_stack_tb.gtkw ├── iSim.batch.tcl ├── iSim.gui.tcl ├── io │ └── uart │ │ ├── uart_rx_tb.ghdl │ │ ├── uart_rx_tb.gtkw │ │ └── uart_rx_tb.wcfg ├── mem │ ├── lut │ │ ├── lut_Sine_tb.ghdl │ │ ├── lut_Sine_tb.gtkw │ │ ├── lut_Sine_tb.wcfg │ │ └── lut_Sine_tb.wdo │ └── ocram │ │ ├── ocram_sdp_tb.ghdl │ │ └── ocram_sdp_tb.gtkw ├── misc │ ├── gearbox │ │ ├── gearbox_down_cc_tb.ghdl │ │ ├── gearbox_down_cc_tb.gtkw │ │ ├── gearbox_down_cc_tb.wdo │ │ ├── gearbox_down_dc_tb.ghdl │ │ ├── gearbox_down_dc_tb.gtkw │ │ ├── gearbox_down_dc_tb.wdo │ │ ├── gearbox_up_cc_tb.ghdl │ │ ├── gearbox_up_cc_tb.gtkw │ │ ├── gearbox_up_cc_tb.wdo │ │ ├── gearbox_up_dc_tb.ghdl │ │ ├── gearbox_up_dc_tb.gtkw │ │ └── gearbox_up_dc_tb.wdo │ ├── stat │ │ ├── stat_Maximum_tb.ghdl │ │ ├── stat_Maximum_tb.gtkw │ │ ├── stat_Maximum_tb.wcfg │ │ ├── stat_Minimum_tb.ghdl │ │ ├── stat_Minimum_tb.gtkw │ │ └── stat_Minimum_tb.wcfg │ └── sync │ │ ├── sync_Bits_tb.ghdl │ │ ├── sync_Bits_tb.gtkw │ │ ├── sync_Command_tb.ghdl │ │ ├── sync_Command_tb.gtkw │ │ ├── sync_Command_tb.wcfg │ │ ├── sync_Reset_tb.ghdl │ │ ├── sync_Reset_tb.gtkw │ │ ├── sync_Reset_tb.wcfg │ │ ├── sync_Strobe_tb.ghdl │ │ ├── sync_Strobe_tb.gtkw │ │ ├── sync_Strobe_tb.wcfg │ │ ├── sync_Vector_tb.ghdl │ │ ├── sync_Vector_tb.gtkw │ │ └── sync_Vector_tb.wcfg ├── sort │ └── sortnet │ │ ├── sortnet_BitonicSort_tb.ghdl │ │ ├── sortnet_BitonicSort_tb.gtkw │ │ ├── sortnet_BitonicSort_tb.wcfg │ │ ├── sortnet_BitonicSort_tb.wdo │ │ ├── sortnet_OddEvenMergeSort_tb.ghdl │ │ ├── sortnet_OddEvenMergeSort_tb.gtkw │ │ ├── sortnet_OddEvenMergeSort_tb.wdo │ │ ├── sortnet_OddEvenSort_tb.ghdl │ │ ├── sortnet_OddEvenSort_tb.gtkw │ │ ├── sortnet_OddEvenSort_tb.wcfg │ │ ├── sortnet_OddEvenSort_tb.wdo │ │ ├── sortnet_Stream_Adapter2_tb.ghdl │ │ ├── sortnet_Stream_Adapter2_tb.gtkw │ │ ├── sortnet_Stream_Adapter_tb.ghdl │ │ └── sortnet_Stream_Adapter_tb.gtkw ├── vSim.batch.tcl ├── vSim.default.wdo ├── vSim.gui.tcl ├── xSim.batch.tcl └── xSim.gui.tcl ├── src ├── README.md ├── alt │ └── README.md ├── arith │ ├── README.md │ ├── arith.pkg.vhdl │ ├── arith_addw.files │ ├── arith_addw.vhdl │ ├── arith_carrychain_inc.files │ ├── arith_carrychain_inc.vhdl │ ├── arith_cca.files │ ├── arith_cca.vhdl │ ├── arith_convert_bin2bcd.files │ ├── arith_convert_bin2bcd.vhdl │ ├── arith_counter_bcd.files │ ├── arith_counter_bcd.vhdl │ ├── arith_counter_free.files │ ├── arith_counter_free.vhdl │ ├── arith_counter_gray.files │ ├── arith_counter_gray.vhdl │ ├── arith_counter_ring.files │ ├── arith_counter_ring.vhdl │ ├── arith_div.files │ ├── arith_div.vhdl │ ├── arith_firstone.files │ ├── arith_firstone.vhdl │ ├── arith_prefix_and.files │ ├── arith_prefix_and.vhdl │ ├── arith_prefix_or.files │ ├── arith_prefix_or.vhdl │ ├── arith_prng.files │ ├── arith_prng.vhdl │ ├── arith_same.files │ ├── arith_same.vhdl │ ├── arith_scaler.files │ ├── arith_scaler.vhdl │ ├── arith_shifter_barrel.files │ ├── arith_shifter_barrel.vhdl │ ├── arith_sqrt.files │ ├── arith_sqrt.vhdl │ ├── arith_trng.files │ ├── arith_trng.vhdl │ └── xilinx │ │ ├── arith_addw_xilinx.vhdl │ │ ├── arith_carrychain_inc_xilinx.vhdl │ │ ├── arith_cca_xilinx.vhdl │ │ ├── arith_inc_ovcy_xilinx.vhdl │ │ ├── arith_prefix_and_xilinx.vhdl │ │ └── arith_prefix_or_xilinx.vhdl ├── bus │ ├── README.md │ ├── bus_Arbiter.files │ ├── bus_Arbiter.vhdl │ ├── stream │ │ ├── README.md │ │ ├── stream.pkg.vhdl │ │ ├── stream_Buffer.files │ │ ├── stream_Buffer.vhdl │ │ ├── stream_DeMux.files │ │ ├── stream_DeMux.vhdl │ │ ├── stream_FrameGenerator.files │ │ ├── stream_FrameGenerator.vhdl │ │ ├── stream_Mirror.files │ │ ├── stream_Mirror.vhdl │ │ ├── stream_Mux.files │ │ ├── stream_Mux.vhdl │ │ ├── stream_Source.files │ │ └── stream_Source.vhdl │ └── wb │ │ └── README.md ├── cache │ ├── README.md │ ├── cache.pkg.vhdl │ ├── cache_cpu.files │ ├── cache_cpu.vhdl │ ├── cache_mem.files │ ├── cache_mem.vhdl │ ├── cache_par.files │ ├── cache_par.vhdl │ ├── cache_par2.files │ ├── cache_par2.vhdl │ ├── cache_replacement_policy.vhdl │ ├── cache_tagunit_par.vhdl │ └── cache_tagunit_seq.vhdl ├── comm │ ├── README.md │ ├── comm.pkg.vhdl │ ├── comm_crc.files │ ├── comm_crc.vhdl │ ├── comm_scramble.files │ ├── comm_scramble.vhdl │ └── remote │ │ └── remote_terminal_control.vhdl ├── common │ ├── README.md │ ├── common.files │ ├── common.vhdl │ ├── components.vhdl │ ├── config.vhdl │ ├── debug.vhdl │ ├── fileio.v08.vhdl │ ├── fileio.v93.vhdl │ ├── math.vhdl │ ├── my_config.vhdl.template │ ├── my_project.vhdl.template │ ├── physical.vhdl │ ├── protected.v08.vhdl │ ├── strings.vhdl │ ├── utils.vhdl │ └── vectors.vhdl ├── dstruct │ ├── README.md │ ├── dstruct.pkg.vhdl │ ├── dstruct_deque.files │ ├── dstruct_deque.vhdl │ ├── dstruct_stack.files │ └── dstruct_stack.vhdl ├── fifo │ ├── README.md │ ├── fifo.pkg.vhdl │ ├── fifo_cc_got.files │ ├── fifo_cc_got.vhdl │ ├── fifo_cc_got_tempgot.files │ ├── fifo_cc_got_tempgot.vhdl │ ├── fifo_cc_got_tempput.files │ ├── fifo_cc_got_tempput.vhdl │ ├── fifo_glue.files │ ├── fifo_glue.vhdl │ ├── fifo_ic_assembly.files │ ├── fifo_ic_assembly.vhdl │ ├── fifo_ic_got.files │ ├── fifo_ic_got.vhdl │ └── fifo_shift.vhdl ├── io │ ├── README.md │ ├── ddrio │ │ ├── README.md │ │ ├── ddrio.pkg.vhdl │ │ ├── ddrio_in.files │ │ ├── ddrio_in.vhdl │ │ ├── ddrio_in_altera.vhdl │ │ ├── ddrio_in_xilinx.vhdl │ │ ├── ddrio_inout.files │ │ ├── ddrio_inout.vhdl │ │ ├── ddrio_inout_altera.vhdl │ │ ├── ddrio_inout_xilinx.vhdl │ │ ├── ddrio_out.files │ │ ├── ddrio_out.vhdl │ │ ├── ddrio_out_altera.vhdl │ │ └── ddrio_out_xilinx.vhdl │ ├── iic │ │ ├── README.md │ │ └── iic.pkg.vhdl │ ├── io.pkg.vhdl │ ├── io_7SegmentMux_BCD.files │ ├── io_7SegmentMux_BCD.vhdl │ ├── io_7SegmentMux_HEX.files │ ├── io_7SegmentMux_HEX.vhdl │ ├── io_Debounce.files │ ├── io_Debounce.vhdl │ ├── io_FanControl.files │ ├── io_FanControl.vhdl │ ├── io_FrequencyCounter.files │ ├── io_FrequencyCounter.vhdl │ ├── io_GlitchFilter.files │ ├── io_GlitchFilter.vhdl │ ├── io_KeyPadScanner.files │ ├── io_KeyPadScanner.vhdl │ ├── io_PulseWidthModulation.files │ ├── io_PulseWidthModulation.vhdl │ ├── io_TimingCounter.files │ ├── io_TimingCounter.vhdl │ ├── lcd │ │ └── README.md │ ├── mdio │ │ └── README.md │ ├── ow │ │ └── README.md │ ├── pmod │ │ ├── README.md │ │ ├── pmod.pkg.vhdl │ │ ├── pmod_KYPD.files │ │ ├── pmod_KYPD.vhdl │ │ ├── pmod_SSD.files │ │ ├── pmod_SSD.vhdl │ │ ├── pmod_USBUART.files │ │ └── pmod_USBUART.vhdl │ ├── ps2 │ │ └── README.md │ ├── uart │ │ ├── README.md │ │ ├── uart.pkg.vhdl │ │ ├── uart_bclk.vhdl │ │ ├── uart_fifo.files │ │ ├── uart_fifo.vhdl │ │ ├── uart_ft245.vhdl │ │ ├── uart_rx.vhdl │ │ └── uart_tx.vhdl │ └── vga │ │ └── README.md ├── mem │ ├── README.md │ ├── ddr2 │ │ ├── README.md │ │ ├── ddr2_mem2mig_adapter_Spartan6.files │ │ └── ddr2_mem2mig_adapter_Spartan6.vhdl │ ├── ddr3 │ │ ├── README.md │ │ ├── ddr3_mem2mig_adapter_Series7.files │ │ └── ddr3_mem2mig_adapter_Series7.vhdl │ ├── lut │ │ ├── README.md │ │ ├── lut_Sine.files │ │ └── lut_Sine.vhdl │ ├── mem.pkg.vhdl │ ├── ocram │ │ ├── README.md │ │ ├── altera │ │ │ ├── ocram_sp_altera.vhdl │ │ │ └── ocram_tdp_altera.vhdl │ │ ├── ocram.pkg.vhdl │ │ ├── ocram_esdp.files │ │ ├── ocram_esdp.vhdl │ │ ├── ocram_sdp.files │ │ ├── ocram_sdp.vhdl │ │ ├── ocram_sdp_wf.files │ │ ├── ocram_sdp_wf.vhdl │ │ ├── ocram_sp.files │ │ ├── ocram_sp.vhdl │ │ ├── ocram_tdp.files │ │ ├── ocram_tdp.vhdl │ │ ├── ocram_tdp_sim.vhdl │ │ ├── ocram_tdp_wf.files │ │ └── ocram_tdp_wf.vhdl │ ├── ocrom │ │ ├── README.md │ │ ├── ocrom.pkg.vhdl │ │ ├── ocrom_dp.files │ │ ├── ocrom_dp.vhdl │ │ ├── ocrom_sp.files │ │ └── ocrom_sp.vhdl │ └── sdram │ │ ├── README.md │ │ ├── sdram_ctrl_de0.files │ │ ├── sdram_ctrl_de0.vhdl │ │ ├── sdram_ctrl_fsm.vhdl │ │ ├── sdram_ctrl_phy_de0.vhdl │ │ ├── sdram_ctrl_phy_s3esk.vhdl │ │ ├── sdram_ctrl_s3esk.files │ │ └── sdram_ctrl_s3esk.vhdl ├── misc │ ├── README.md │ ├── filter │ │ ├── README.md │ │ ├── filter_and.files │ │ ├── filter_and.vhdl │ │ ├── filter_mean.files │ │ ├── filter_mean.vhdl │ │ ├── filter_or.files │ │ └── filter_or.vhdl │ ├── gearbox │ │ ├── README.md │ │ ├── gearbox_down_cc.files │ │ ├── gearbox_down_cc.vhdl │ │ ├── gearbox_down_dc.files │ │ ├── gearbox_down_dc.vhdl │ │ ├── gearbox_up_cc.files │ │ ├── gearbox_up_cc.vhdl │ │ ├── gearbox_up_dc.files │ │ └── gearbox_up_dc.vhdl │ ├── misc_Delay.files │ ├── misc_Delay.vhdl │ ├── misc_FrequencyMeasurement.files │ ├── misc_FrequencyMeasurement.vhdl │ ├── misc_bit_lz.vhdl │ ├── stat │ │ ├── README.md │ │ ├── stat_Average.files │ │ ├── stat_Average.vhdl │ │ ├── stat_Histogram.files │ │ ├── stat_Histogram.vhdl │ │ ├── stat_Maximum.files │ │ ├── stat_Maximum.vhdl │ │ ├── stat_Minimum.files │ │ └── stat_Minimum.vhdl │ └── sync │ │ ├── README.md │ │ ├── sync.pkg.vhdl │ │ ├── sync_Bits.files │ │ ├── sync_Bits.vhdl │ │ ├── sync_Bits_Altera.vhdl │ │ ├── sync_Bits_Xilinx.vhdl │ │ ├── sync_Command.files │ │ ├── sync_Command.vhdl │ │ ├── sync_Pulse.files │ │ ├── sync_Pulse.vhdl │ │ ├── sync_Pulse_Altera.vhdl │ │ ├── sync_Pulse_Xilinx.vhdl │ │ ├── sync_Reset.files │ │ ├── sync_Reset.vhdl │ │ ├── sync_Reset_Altera.vhdl │ │ ├── sync_Reset_Xilinx.vhdl │ │ ├── sync_Strobe.files │ │ ├── sync_Strobe.vhdl │ │ ├── sync_Vector.files │ │ └── sync_Vector.vhdl ├── net │ ├── README.md │ ├── arp │ │ ├── README.md │ │ ├── arp_BroadCast_Receiver.vhdl │ │ ├── arp_BroadCast_Requester.vhdl │ │ ├── arp_Cache.vhdl │ │ ├── arp_IPPool.vhdl │ │ ├── arp_UniCast_Receiver.vhdl │ │ ├── arp_UniCast_Responder.vhdl │ │ └── arp_Wrapper.vhdl │ ├── eth │ │ └── README.md │ ├── icmpv4 │ │ ├── README.md │ │ ├── icmpv4_RX.vhdl │ │ ├── icmpv4_TX.vhdl │ │ └── icmpv4_Wrapper.vhdl │ ├── icmpv6 │ │ └── README.md │ ├── ipv4 │ │ ├── README.md │ │ ├── ipv4_FrameLoopback.vhdl │ │ ├── ipv4_RX.vhdl │ │ ├── ipv4_TX.vhdl │ │ └── ipv4_Wrapper.vhdl │ ├── ipv6 │ │ ├── README.md │ │ ├── ipv6_FrameLoopback.vhdl │ │ ├── ipv6_RX.vhdl │ │ ├── ipv6_TX.vhdl │ │ └── ipv6_Wrapper.vhdl │ ├── mac │ │ ├── README.md │ │ ├── mac_FrameLoopback.vhdl │ │ ├── mac_RX_DestMAC_Switch.vhdl │ │ ├── mac_RX_SrcMAC_Filter.vhdl │ │ ├── mac_RX_Type_Switch.vhdl │ │ ├── mac_TX_DestMAC_Prepender.vhdl │ │ ├── mac_TX_SrcMAC_Prepender.vhdl │ │ └── mac_Wrapper.vhdl │ ├── ndp │ │ └── README.md │ ├── net.pkg.vhdl │ ├── net_FrameChecksum.vhdl │ ├── net_FrameLoopback.vhdl │ ├── stack │ │ └── README.md │ └── udp │ │ ├── README.md │ │ ├── udp_FrameLoopback.vhdl │ │ ├── udp_RX.vhdl │ │ ├── udp_TX.vhdl │ │ └── udp_Wrapper.vhdl ├── sim │ ├── README.md │ ├── sim.files │ ├── sim_VCDParser.vhdl │ ├── sim_global.v08.vhdl │ ├── sim_global.v93.vhdl │ ├── sim_protected.v08.vhdl │ ├── sim_random.v08.vhdl │ ├── sim_random.v93.vhdl │ ├── sim_simulation.v08.vhdl │ ├── sim_simulation.v93.vhdl │ ├── sim_types.vhdl │ ├── sim_unprotected.v93.vhdl │ └── sim_waveform.vhdl ├── sort │ ├── README.md │ ├── sort_lru_cache.files │ ├── sort_lru_cache.vhdl │ ├── sort_lru_list.files │ ├── sort_lru_list.vhdl │ └── sortnet │ │ ├── README.md │ │ ├── sortnet.pkg.vhdl │ │ ├── sortnet_BitonicSort.files │ │ ├── sortnet_BitonicSort.vhdl │ │ ├── sortnet_MergeSort_Streamed.files │ │ ├── sortnet_MergeSort_Streamed.vhdl │ │ ├── sortnet_OddEvenMergeSort.files │ │ ├── sortnet_OddEvenMergeSort.vhdl │ │ ├── sortnet_OddEvenSort.files │ │ ├── sortnet_OddEvenSort.vhdl │ │ ├── sortnet_Stream_Adapter.files │ │ ├── sortnet_Stream_Adapter.vhdl │ │ ├── sortnet_Stream_Adapter2.files │ │ ├── sortnet_Stream_Adapter2.vhdl │ │ └── sortnet_Transform.vhdl └── xil │ ├── README.md │ ├── mig │ ├── README.md │ ├── mig_Atlys_1x128.prj │ ├── mig_Atlys_1x128.rules │ ├── mig_Atlys_1x128.xco │ ├── mig_KC705_MT8JTF12864HZ_1G6.prj │ ├── mig_KC705_MT8JTF12864HZ_1G6.rules │ └── mig_KC705_MT8JTF12864HZ_1G6.xco │ ├── reconfig │ ├── reconfig_icap_fsm.vhdl │ └── reconfig_icap_wrapper.vhdl │ ├── xil.pkg.vhdl │ ├── xil_BSCAN.files │ ├── xil_BSCAN.vhdl │ ├── xil_ChipScopeICON.files │ ├── xil_ChipScopeICON.vhdl │ ├── xil_ChipScopeICON_1.xco │ ├── xil_ChipScopeICON_10.xco │ ├── xil_ChipScopeICON_11.xco │ ├── xil_ChipScopeICON_12.xco │ ├── xil_ChipScopeICON_13.xco │ ├── xil_ChipScopeICON_14.xco │ ├── xil_ChipScopeICON_15.xco │ ├── xil_ChipScopeICON_2.xco │ ├── xil_ChipScopeICON_3.xco │ ├── xil_ChipScopeICON_4.xco │ ├── xil_ChipScopeICON_5.xco │ ├── xil_ChipScopeICON_6.xco │ ├── xil_ChipScopeICON_7.xco │ ├── xil_ChipScopeICON_8.xco │ ├── xil_ChipScopeICON_9.xco │ ├── xil_ICAP.files │ ├── xil_ICAP.vhdl │ ├── xil_Reconfigurator.vhdl │ └── xil_SystemMonitor.vhdl ├── tb ├── README.md ├── arith │ ├── arith_addw_tb.files │ ├── arith_addw_tb.vhdl │ ├── arith_convert_bin2bcd_tb.files │ ├── arith_convert_bin2bcd_tb.vhdl │ ├── arith_counter_bcd_tb.files │ ├── arith_counter_bcd_tb.vhdl │ ├── arith_div_tb.files │ ├── arith_div_tb.vhdl │ ├── arith_firstone_tb.files │ ├── arith_firstone_tb.vhdl │ ├── arith_prefix_and_tb.files │ ├── arith_prefix_and_tb.vhdl │ ├── arith_prefix_or_tb.files │ ├── arith_prefix_or_tb.vhdl │ ├── arith_prng_tb.files │ ├── arith_prng_tb.isim.vhdl │ ├── arith_prng_tb.vhdl │ ├── arith_scaler_tb.files │ └── arith_scaler_tb.vhdl ├── cache │ ├── cache_cpu_tb.files │ ├── cache_cpu_tb.vhdl │ ├── cache_mem_tb.files │ ├── cache_mem_tb.vhdl │ ├── cache_par2_cocotb.py │ ├── cache_par2_tb.files │ ├── cache_par_cocotb.py │ └── cache_par_tb.files ├── common │ ├── config_tb.files │ ├── config_tb.vhdl │ ├── lru_dict.py │ ├── my_config.files │ ├── my_config_AC701.vhdl │ ├── my_config_Atlys.vhdl │ ├── my_config_DE0.vhdl │ ├── my_config_DE4.vhdl │ ├── my_config_DE5.vhdl │ ├── my_config_ECP5Versa.vhdl │ ├── my_config_GENERIC.vhdl │ ├── my_config_KC705.vhdl │ ├── my_config_ML505.vhdl │ ├── my_config_ML506.vhdl │ ├── my_config_ML605.vhdl │ ├── my_config_Nexys4.vhdl │ ├── my_config_Nexys4DDR.vhdl │ ├── my_config_S2GXAV.vhdl │ ├── my_config_S3ESK500.vhdl │ ├── my_config_S3SK1000.vhdl │ ├── my_config_VC707.vhdl │ ├── my_config_VC709.vhdl │ ├── my_config_XUPV5.vhdl │ ├── my_config_ZC706.vhdl │ ├── my_config_ZedBoard.vhdl │ ├── physical_tb.files │ ├── physical_tb.vhdl │ ├── strings_tb.files │ ├── strings_tb.vhdl │ └── utils.py ├── dstruct │ ├── dstruct_deque_tb.files │ ├── dstruct_deque_tb.vhdl │ ├── dstruct_stack_tb.files │ └── dstruct_stack_tb.vhdl ├── fifo │ ├── fifo_cc_got_tb.files │ ├── fifo_cc_got_tb.vhdl │ ├── fifo_cc_got_tempput_tb.files │ ├── fifo_cc_got_tempput_tb.vhdl │ ├── fifo_ic_assembly_tb.files │ ├── fifo_ic_assembly_tb.vhdl │ ├── fifo_ic_got_tb.files │ └── fifo_ic_got_tb.vhdl ├── io │ ├── ddrio │ │ ├── ddrio_in_tb.files │ │ ├── ddrio_in_tb.vhdl │ │ ├── ddrio_inout_tb.files │ │ ├── ddrio_inout_tb.vhdl │ │ ├── ddrio_out_tb.files │ │ └── ddrio_out_tb.vhdl │ ├── io_Debounce_tb.files │ ├── io_Debounce_tb.vhdl │ └── uart │ │ ├── uart_rx_tb.files │ │ └── uart_rx_tb.vhdl ├── mem │ ├── lut │ │ ├── lut_Sine_tb.files │ │ └── lut_Sine_tb.vhdl │ ├── mem_model.vhdl │ └── ocram │ │ ├── ocram_esdp_tb.files │ │ ├── ocram_esdp_tb.vhdl │ │ ├── ocram_sdp_tb.files │ │ ├── ocram_sdp_tb.vhdl │ │ ├── ocram_sdp_wf_tb.files │ │ ├── ocram_sdp_wf_tb.vhdl │ │ ├── ocram_sp_tb.files │ │ ├── ocram_sp_tb.vhdl │ │ ├── ocram_tdp_tb.files │ │ ├── ocram_tdp_tb.vhdl │ │ ├── ocram_tdp_wf_tb.files │ │ └── ocram_tdp_wf_tb.vhdl ├── misc │ ├── gearbox │ │ ├── gearbox_down_cc_tb.files │ │ ├── gearbox_down_cc_tb.vhdl │ │ ├── gearbox_down_dc_tb.files │ │ ├── gearbox_down_dc_tb.vhdl │ │ ├── gearbox_up_cc_tb.files │ │ ├── gearbox_up_cc_tb.vhdl │ │ ├── gearbox_up_dc_tb.files │ │ └── gearbox_up_dc_tb.vhdl │ ├── misc_bit_lz_tb.vhdl │ ├── stat │ │ ├── stat_Average_tb.files │ │ ├── stat_Average_tb.vhdl │ │ ├── stat_Histogram_tb.files │ │ ├── stat_Histogram_tb.vhdl │ │ ├── stat_Maximum_tb.files │ │ ├── stat_Maximum_tb.vhdl │ │ ├── stat_Minimum_tb.files │ │ └── stat_Minimum_tb.vhdl │ └── sync │ │ ├── sync_Bits_tb.files │ │ ├── sync_Bits_tb.vhdl │ │ ├── sync_Command_tb.files │ │ ├── sync_Command_tb.vhdl │ │ ├── sync_Reset_tb.files │ │ ├── sync_Reset_tb.vhdl │ │ ├── sync_Strobe_tb.files │ │ ├── sync_Strobe_tb.vhdl │ │ ├── sync_Vector_tb.files │ │ └── sync_Vector_tb.vhdl ├── sim │ ├── sim_ClockGenerator_tb.files │ ├── sim_ClockGenerator_tb.vhdl │ ├── sim_VCDParser_tb.files │ ├── sim_VCDParser_tb.vcd │ ├── sim_VCDParser_tb.vhdl │ ├── sim_Waveform_tb.files │ └── sim_Waveform_tb.vhdl └── sort │ ├── sort_lru_cache_cocotb.py │ ├── sort_lru_cache_tb.files │ ├── sort_lru_cache_tb.vhdl │ ├── sort_lru_list_cocotb.py │ ├── sort_lru_list_tb.files │ └── sortnet │ ├── sortnet_BitonicSort_tb.files │ ├── sortnet_BitonicSort_tb.vhdl │ ├── sortnet_OddEvenMergeSort_tb.files │ ├── sortnet_OddEvenMergeSort_tb.vhdl │ ├── sortnet_OddEvenSort_tb.files │ ├── sortnet_OddEvenSort_tb.vhdl │ ├── sortnet_Stream_Adapter2_tb.files │ ├── sortnet_Stream_Adapter2_tb.vhdl │ ├── sortnet_Stream_Adapter_tb.files │ ├── sortnet_Stream_Adapter_tb.vhdl │ └── sortnet_tb.pkg.vhdl ├── tcl ├── README.md ├── common │ └── utils.tcl └── vivado │ └── utils.tcl ├── temp ├── .gitempty ├── README.md └── precompiled │ └── .gitempty ├── tools ├── AppVeyor │ ├── PoC.dryrun.ps1 │ ├── PoC.list.ps1 │ ├── config.private.ini │ ├── modelsim.ini │ ├── my_project.vhdl │ └── requirements.txt ├── GitLab-CI │ ├── config.private.ini │ ├── ghdl.setup.sh │ ├── grc.setup.sh │ ├── modelsim.ini │ ├── my_project.vhdl │ ├── poc.run.sh │ ├── poc.setup.sh │ └── requirements.txt ├── Notepad++ │ ├── Syntax Highlighting - PoC Config.xml │ ├── Syntax Highlighting - PoC Files.xml │ ├── Syntax Highlighting - PoC Rules.xml │ ├── Syntax Highlighting - Xilinx UCF.xml │ └── Syntax Highlighting - Xilinx XDC.xml ├── README.md ├── ReadTheDocs │ └── requirements.txt ├── Travis-CI │ ├── config.private.ini │ ├── ghdl.setup.sh │ ├── grc.setup.sh │ ├── modelsim.ini │ ├── my_project.vhdl │ ├── poc.dryrun.sh │ ├── poc.run.grcrules │ ├── poc.run.sh │ ├── poc.setup.sh │ └── requirements.txt ├── git │ ├── build_md.py │ ├── filters │ │ └── normalize.pl │ ├── git-alias.setup.ps1 │ ├── git-alias.setup.sh │ └── hooks │ │ ├── pre-commit.d │ │ └── whitespace.sh │ │ └── run-hook.sh └── precompile │ ├── compile-altera.ps1 │ ├── compile-altera.sh │ ├── compile-lattice.ps1 │ ├── compile-lattice.sh │ ├── compile-osvvm.ps1 │ ├── compile-osvvm.sh │ ├── compile-uvvm.ps1 │ ├── compile-uvvm.sh │ ├── compile-xilinx-ise.ps1 │ ├── compile-xilinx-ise.sh │ ├── compile-xilinx-vivado.ps1 │ ├── compile-xilinx-vivado.sh │ ├── ghdl.grcrules │ ├── ghdl.skipwarning.grcrules │ ├── precompile.psm1 │ └── precompile.sh ├── ucf ├── AC701 │ ├── Bus.IIC.xdc │ ├── Clock.SystemClock.xdc │ ├── FanControl.xdc │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.xdc │ └── USB_UART.xdc ├── Arty │ ├── Bus.SPI.xdc │ ├── Clock.SystemClock.xdc │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.RGB.xdc │ ├── GPIO.LED.xdc │ └── USB_UART.xdc ├── ArtyS7 │ ├── Bus.SPI.xdc │ ├── Clock.SystemClock.xdc │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.RGB.xdc │ ├── GPIO.LED.xdc │ └── USB_UART.xdc ├── Atlys │ ├── Bus.IIC.ucf │ ├── Clock.SystemClock.ucf │ ├── Default.ucf │ ├── EthernetPHY.GMII.ucf │ ├── EthernetPHY.RGMII.ucf │ ├── EthernetPHY.ucf │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Special.ucf │ ├── GPIO.LED.ucf │ ├── GPIO.Switch.ucf │ ├── HDMI.RX.ucf │ ├── HDMI.TX.ucf │ └── USB_UART.ucf ├── DE4 │ ├── Bus.IIC.EEPROM.sdc │ ├── Bus.SMBus.sdc │ ├── Clock.SystemClock.sdc │ ├── FanControl.sdc │ ├── GPIO.Button.Special.sdc │ ├── GPIO.Button.sdc │ ├── GPIO.DipSwitch.sdc │ ├── GPIO.LED.sdc │ ├── GPIO.Seg7.sdc │ ├── GPIO.SlideSwitch.sdc │ └── UART.sdc ├── KC705 │ ├── Bus.IIC.ucf │ ├── Bus.IIC.xdc │ ├── Bus.LCDisplay.ucf │ ├── Bus.PMBus.ucf │ ├── Clock.ProgUserClock.ucf │ ├── Clock.ProgUserClock.xdc │ ├── Clock.Si5324.ucf │ ├── Clock.SystemClock.ucf │ ├── Clock.SystemClock.xdc │ ├── Default.ucf │ ├── EthernetPHY.GMII.ucf │ ├── EthernetPHY.RGMII.ucf │ ├── EthernetPHY.SGMII.ucf │ ├── EthernetPHY.ucf │ ├── FMC-HPC │ │ └── FasterTechnology │ │ │ └── S14 │ │ │ ├── FMC-HPC.Clock.RefClock0.xdc │ │ │ ├── FMC-HPC.Clock.RefClock1.xdc │ │ │ ├── FMC-HPC.GPIO.LED.xdc │ │ │ ├── FMC-HPC.GPIO.Switch.xdc │ │ │ ├── FMC-HPC.SFP_Channel0.xdc │ │ │ ├── FMC-HPC.SFP_Channel1.xdc │ │ │ ├── FMC-HPC.SFP_Channel2.xdc │ │ │ └── FMC-HPC.SFP_Channel3.xdc │ ├── FMC-LPC │ │ └── FasterTechnology │ │ │ └── S14 │ │ │ └── FMC-LPC.SFP_Channel3.xdc │ ├── FanControl.ucf │ ├── FanControl.xdc │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Cursor.xdc │ ├── GPIO.Button.Special.ucf │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.ucf │ ├── GPIO.LED.xdc │ ├── GPIO.Rotary.ucf │ ├── GPIO.Rotary.xdc │ ├── GPIO.SMA.ucf │ ├── GPIO.SMA.xdc │ ├── GPIO.Switch.ucf │ ├── GPIO.Switch.xdc │ ├── Transceiver.SFP.ucf │ ├── Transceiver.SFP.xdc │ ├── Transceiver.SMA.ucf │ ├── Transceiver.SMA_RefClock.ucf │ ├── USB_UART.ucf │ └── USB_UART.xdc ├── ML505 │ ├── Bus.IIC.Main.ucf │ ├── Bus.IIC.Monitor.ucf │ ├── Bus.LCDisplay.ucf │ ├── Bus.PS2.Keyboard.ucf │ ├── Bus.PS2.Mouse.ucf │ ├── Clock.SMA.ucf │ ├── Clock.SystemClock.ucf │ ├── Clock.UserClock.ucf │ ├── Default.ucf │ ├── EthernetPHY.GMII.ucf │ ├── EthernetPHY.RGMII.ucf │ ├── EthernetPHY.SGMII.ucf │ ├── EthernetPHY.ucf │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Special.ucf │ ├── GPIO.LED.Cursor.ucf │ ├── GPIO.LED.Error.ucf │ ├── GPIO.LED.ucf │ ├── GPIO.Rotary.ucf │ ├── GPIO.Switch.ucf │ ├── Monitor.DVI.Output.ucf │ ├── Transceiver.SFP.ucf │ ├── Transceiver.SMA.ucf │ ├── Transceiver.SMA_RefClock.ucf │ └── UART.ucf ├── ML506 │ ├── Default.ucf │ └── README.md ├── ML605 │ ├── Bus.IIC.ucf │ ├── Bus.LCDisplay.ucf │ ├── Bus.PMBus.ucf │ ├── Clock.SystemClock.ucf │ ├── Clock.UserClock.ucf │ ├── Default.ucf │ ├── EthernetPHY.GMII.ucf │ ├── EthernetPHY.RGMII.ucf │ ├── EthernetPHY.SGMII.ucf │ ├── EthernetPHY.ucf │ ├── FanControl.ucf │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Special.ucf │ ├── GPIO.LED.ucf │ ├── GPIO.Rotary.ucf │ ├── GPIO.Switch.ucf │ ├── Transceiver.SFP.ucf │ ├── Transceiver.SMA.ucf │ ├── Transceiver.SMA_RefClock.ucf │ └── USB_UART.ucf ├── MetaStability.ucf ├── Nexys4 │ ├── Clock.SystemClock.xdc │ ├── GPIO.7Segment.xdc │ ├── GPIO.Button.Cursor.xdc │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.RGB.xdc │ ├── GPIO.LED.xdc │ ├── GPIO.Switch.xdc │ └── Video.VGA.xdc ├── Nexys4DDR │ ├── Bus.IIC.xdc │ ├── Bus.PS2.xdc │ ├── Bus.QSPIFlash.xdc │ ├── Clock.SystemClock.xdc │ ├── EthernetPHY.RMII.xdc │ ├── EthernetPHY.xdc │ ├── GPIO.7Segment.xdc │ ├── GPIO.Button.Cursor.xdc │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.RGB.xdc │ ├── GPIO.LED.xdc │ ├── GPIO.Switch.xdc │ ├── PMOD.PortA.xdc │ ├── USB_UART.xdc │ └── Video.VGA.xdc ├── README.md ├── S3SK │ ├── buttons.ucf │ ├── default.ucf │ ├── leds.ucf │ ├── switches.ucf │ ├── uart.ucf │ └── vga.ucf ├── VC707 │ ├── Bus.IIC.ucf │ ├── Bus.LCDisplay.ucf │ ├── Bus.PMBus.ucf │ ├── Clock.ProgUserClock.ucf │ ├── Clock.ProgUserClock.xdc │ ├── Clock.SystemClock.ucf │ ├── Clock.SystemClock.xdc │ ├── Default.ucf │ ├── EthernetPHY.SGMII.ucf │ ├── EthernetPHY.ucf │ ├── FanControl.ucf │ ├── FanControl.xdc │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Cursor.xdc │ ├── GPIO.Button.Special.ucf │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.ucf │ ├── GPIO.LED.xdc │ ├── GPIO.Rotary.ucf │ ├── GPIO.Rotary.xdc │ ├── GPIO.SMA.ucf │ ├── GPIO.SMA.xdc │ ├── GPIO.Switch.ucf │ ├── GPIO.Switch.xdc │ ├── Transceiver.SFP.ucf │ ├── Transceiver.SMA.ucf │ ├── Transceiver.SMA_RefClock.ucf │ ├── USB_UART.ucf │ └── USB_UART.xdc ├── XUPV5 │ ├── Default.ucf │ └── README.md ├── Xilinx │ ├── Disable_DRC_Rules_GTHE3_Common.xdc │ ├── Disable_DRC_Rules_GTPE2_Channel.xdc │ └── Disable_DRC_Rules_GTXE2_Channel.xdc ├── ZC706 │ ├── Bus.IIC.ucf │ ├── Bus.IIC.xdc │ ├── Clock.ProgUserClock.ucf │ ├── Clock.ProgUserClock.xdc │ ├── Clock.SMAClock.ucf │ ├── Clock.SMAClock.xdc │ ├── Clock.SystemClock.ucf │ ├── Clock.SystemClock.xdc │ ├── Default.ucf │ ├── FanControl.ucf │ ├── FanControl.xdc │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.Button.Cursor.xdc │ ├── GPIO.Button.Special.ucf │ ├── GPIO.Button.Special.xdc │ ├── GPIO.LED.ucf │ ├── GPIO.LED.xdc │ ├── PMOD.Port1.ucf │ ├── PMOD.Port1.xdc │ ├── Transceiver.SFP.ucf │ ├── Transceiver.SFP.xdc │ ├── Transceiver.SMA_RefClock.ucf │ └── Transceiver.SMA_RefClock.xdc ├── ZedBoard │ ├── Clock.SystemClock.ucf │ ├── Default.ucf │ ├── GPIO.Button.Cursor.ucf │ ├── GPIO.LED.ucf │ ├── GPIO.Switch.ucf │ ├── PMOD.PortA.ucf │ ├── PMOD.PortB.ucf │ ├── PMOD.PortC.ucf │ └── PMOD.PortD.ucf ├── arith │ └── arith_trng.xdc ├── fifo │ └── fifo_ic_got.xdc ├── misc │ └── sync │ │ ├── sync_Bits_Xilinx.ucf │ │ ├── sync_Bits_Xilinx.xdc │ │ ├── sync_Command.xdc │ │ ├── sync_Reset_Xilinx.ucf │ │ ├── sync_Reset_Xilinx.xdc │ │ └── sync_Vector.xdc └── net │ └── eth │ ├── eth_RSLayer_GMII_GMII_KC705.ucf │ └── eth_RSLayer_GMII_GMII_ML605.ucf ├── vhdl_coding.md └── xst ├── README.md ├── Series-7.xst ├── Spartan-3.xst ├── Spartan-6.xst ├── default.filter ├── empty.xcf └── xil └── mig ├── mig_Atlys_1x128.files ├── mig_Atlys_1x128.rules ├── mig_Atlys_1x128.xcf ├── mig_KC705_MT8JTF12864HZ_1G6.files └── mig_KC705_MT8JTF12864HZ_1G6.rules /.editorconfig: -------------------------------------------------------------------------------- 1 | root = true 2 | 3 | [*] 4 | indent_style = tab 5 | indent_size = 2 6 | tab_width = 2 7 | trim_trailing_whitespace = true 8 | insert_final_newline = true 9 | 10 | [*.md] 11 | indent_style = space 12 | indent_size = 2 13 | trim_trailing_whitespace = false 14 | 15 | [*.rst] 16 | indent_style = space 17 | indent_size = 3 18 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.tpl -whitespace 2 | *.md -whitespace 3 | *.rst -whitespace 4 | *.ini -whitespace 5 | *.pl filter=normalize 6 | *.ps1 filter=normalize 7 | *.psm1 filter=normalize 8 | *.py filter=normalize 9 | *.sh filter=normalize 10 | *.rst filter=normalize_rest 11 | *.vhdl filter=normalize_vhdl 12 | *.ucf filter=normalize 13 | *.xcf filter=normalize 14 | *.ldc filter=normalize 15 | *.sdc filter=normalize 16 | *.xdc filter=normalize 17 | -------------------------------------------------------------------------------- /.github/CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing to the PoC-Library 2 | 3 | Currently, we have no contribution rules, so feel free to submit pull requests. 4 | 5 | 6 | ### Contributor License Agreement 7 | 8 | We require all contributers to sign a Contributor License Agreement (CLA). If you don't know 9 | what for a CLA is needed and how it prevents legal issues on both sides, read [this short 10 | blog](https://www.clahub.com/pages/why_cla) post. 11 | 12 | So to get started, [sign the Contributor License Agreement (CLA)][CLAHub]. 13 | 14 | 15 | [CLAHub]: https://www.clahub.com/agreements/VLSI-EDA/PoC 16 | -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | stages: 2 | - Selftest 3 | 4 | variables: 5 | GIT_SUBMODULE_STRATEGY: recursive 6 | 7 | pyIPCMI-Selftest: 8 | stage: Selftest 9 | before_script: 10 | - pip3 install -r tools/GitLab-CI/requirements.txt 11 | # - ./tools/GitLab-CI/ghdl.setup.sh 12 | - ./tools/GitLab-CI/poc.setup.sh 13 | script: 14 | # - ./tools/GitLab-CI/poc.dryrun.sh 15 | - ./tools/GitLab-CI/poc.run.sh "PoC.*" 16 | -------------------------------------------------------------------------------- /.gitlab/issue_templates/.gitempty: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/.gitlab/issue_templates/.gitempty -------------------------------------------------------------------------------- /.gitlab/merge_request_templates/.gitempty: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/.gitlab/merge_request_templates/.gitempty -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "lib/vunit"] 2 | path = lib/vunit 3 | url = ../vunit.git 4 | [submodule "lib/osvvm"] 5 | path = lib/osvvm 6 | url = ../OSVVM.git 7 | [submodule "lib/cocotb"] 8 | path = lib/cocotb 9 | url = ../cocotb.git 10 | [submodule "docs/_themes/sphinx_rtd_theme"] 11 | path = docs/_themes/sphinx_rtd_theme 12 | url = ../sphinx_rtd_theme.git 13 | [submodule "lib/uvvm"] 14 | path = lib/uvvm 15 | url = ../UVVM.git 16 | [submodule "lib/pyIPCMI"] 17 | path = lib/pyIPCMI 18 | url = ../pyIPCMI.git 19 | -------------------------------------------------------------------------------- /.landscape.yml: -------------------------------------------------------------------------------- 1 | python-targets: 2 | - 3 3 | # requirements: 4 | # - colorama 5 | # - py-flags 6 | # doc-warnings: yes 7 | test-warnings: no 8 | strictness: medium 9 | max-line-length: 180 10 | pylint: 11 | disable: 12 | - too-many-arguments 13 | # options: 14 | # docstring-min-length: 10 15 | pep8: 16 | disable: 17 | - E704 18 | enable: 19 | options: 20 | max-line-length: 180 21 | mccabe: 22 | options: 23 | max-complexity: 20 24 | # vulture: 25 | # run: true 26 | ignore-paths: 27 | - lib 28 | - netlist 29 | - prj 30 | - sim 31 | - src 32 | # - tb 33 | - tcl 34 | - temp 35 | # - tools 36 | - ucf 37 | - xst 38 | -------------------------------------------------------------------------------- /.readthedocs.yml: -------------------------------------------------------------------------------- 1 | #formats: 2 | # - pdf 3 | requirements_file: tools/ReadTheDocs/requirements.txt 4 | python: 5 | version: 3 6 | -------------------------------------------------------------------------------- /AUTHORS.md: -------------------------------------------------------------------------------- 1 | # List of Authors and Contributors (in alphabetical order) 2 | 3 | Contributor | Contact E-Mail 4 | ------------------|------------------------------------------------------------ 5 | Genßler, Paul | paul.genssler@tu-dresden.de 6 | Köhler, Steffen | steffen.koehler@tu-dresden.de 7 | Lehmann, Patrick | patrick.lehmann@tu-dresden.de; paebbels@gmail.com 8 | Preußer, Thomas B.| thomas.preusser@tu-dresden.de; thomas.preusser@utexas.edu 9 | Reichel, Peter | peter.reichel@eas.iis.fraunhofer.de; peter@peterreichel.info 10 | Schirok, Jan | janschirok@gmx.net 11 | Voß, Jens | jens.voss@mailbox.tu-dresden.de 12 | Zabel, Martin | martin.zabel@tu-dresden.de 13 | -------------------------------------------------------------------------------- /docs/ChangeLog/2014/index.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:2014: 2 | 3 | 2014 4 | #### 5 | 6 | .. contents:: Content of this page 7 | :local: 8 | 9 | .. toctree:: 10 | 11 | v0.0.0 12 | -------------------------------------------------------------------------------- /docs/ChangeLog/2014/v0.0.0.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:v0.0.0: 2 | 3 | New in v0.0.0 (16.12.2014) 4 | ================================================================================================================================================================ 5 | 6 | * Initial commit 7 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.10.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.10.0: 2 | 3 | New in v0.10.0 (23.07.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.11.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.11.0: 2 | 3 | New in v0.11.0 (07.08.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.12.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.12.0: 2 | 3 | New in v0.12.0 (25.08.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.13.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.13.0: 2 | 3 | New in v0.13.0 (04.09.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.14.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.14.0: 2 | 3 | New in v0.14.0 (28.09.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.15.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.15.0: 2 | 3 | New in v0.15.0 (13.11.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.16.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.16.0: 2 | 3 | New in v0.16.0 (01.12.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.17.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.17.0: 2 | 3 | New in v0.17.0 (08.12.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.18.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.18.0: 2 | 3 | New in v0.18.0 (16.12.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.5.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.5.0: 2 | 3 | New in v0.5 (27.05.2015) 4 | ================================================================================================================================================================ 5 | 6 | * Updated Python infrastructure 7 | * New testbenches: 8 | 9 | * sync_Reset_tb 10 | * sync_Flag_tb 11 | * sync_Strobe_tb 12 | * sync_Vector_tb 13 | * sync_Command_tb 14 | 15 | * Updated modules: 16 | 17 | * sync_Vector 18 | * sync_Command 19 | 20 | * Updated packages: 21 | 22 | * physical 23 | * utils 24 | * vectors 25 | * xil 26 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.6.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.6.0: 2 | 3 | New in v0.6 (09.06.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.7.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.7.0: 2 | 3 | New in v0.7 (27.06.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.8.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.8.0: 2 | 3 | New in v0.8.0 (03.07.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2015/v0.9.0.rst: -------------------------------------------------------------------------------- 1 | .. :CHANGE:v0.9.0: 2 | 3 | New in v0.9.0 (21.07.2015) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2016/index.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:2016: 2 | 3 | 2016 4 | #### 5 | 6 | .. contents:: Content of this page 7 | :local: 8 | 9 | .. only:: html 10 | 11 | .. toctree:: 12 | 13 | v1.x 14 | v1.1.0 15 | v1.0.1 16 | v1.0.0 17 | v0.21.0 18 | v0.20.0 19 | v0.19.0 20 | 21 | 22 | 23 | .. only:: latex 24 | 25 | .. toctree:: 26 | 27 | v0.19.0 28 | v0.20.0 29 | v0.21.0 30 | v1.0.0 31 | v1.0.1 32 | v1.1.0 33 | v1.x 34 | -------------------------------------------------------------------------------- /docs/ChangeLog/2016/v0.19.0.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:v0.10: 2 | 3 | New in 0.19 (16.01.2016) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2016/v0.20.0.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:v0.20: 2 | 3 | New in 0.20 (16.01.2016) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/2016/v0.21.0.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE:v0.21: 2 | 3 | New in 0.21 (17.02.2016) 4 | ================================================================================================================================================================ 5 | -------------------------------------------------------------------------------- /docs/ChangeLog/index.rst: -------------------------------------------------------------------------------- 1 | .. _CHANGE: 2 | 3 | Change Log 4 | ########## 5 | 6 | .. only:: html 7 | 8 | .. toctree:: 9 | 10 | 2016/index 11 | 2015/index 12 | 2014/index 13 | 14 | 15 | 16 | .. only:: latex 17 | 18 | .. toctree:: 19 | 20 | 2014/index 21 | 2015/index 22 | 2016/index 23 | 24 | .. # 2017/index 25 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/CycloneIII/DE0.rst: -------------------------------------------------------------------------------- 1 | 2 | ECP5 Versa 3 | ########## 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/CycloneIII/DE0nano.rst: -------------------------------------------------------------------------------- 1 | 2 | ECP5 Versa 3 | ########## 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/CycloneIII/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Cyclone III 3 | ########### 4 | 5 | * DE0 6 | * DE0 nano 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | DE0 12 | DE0nano 13 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/StratixIV/DE4.rst: -------------------------------------------------------------------------------- 1 | 2 | DE4 3 | ### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/StratixIV/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Stratix IV 3 | ########## 4 | 5 | * DE4 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | DE4 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/StratixV/DE5.rst: -------------------------------------------------------------------------------- 1 | 2 | DE5 3 | ### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/StratixV/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Stratix V 3 | ######### 4 | 5 | * DE5 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | DE5 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Altera/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Altera 3 | ###### 4 | 5 | * Cyclone III 6 | * DE0 7 | * DE0 nano 8 | * Stratix IV 9 | * DE4 10 | * Stratix V 11 | * DE5 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | CycloneIII/index 17 | StratixIV/index 18 | StratixV/index 19 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Lattice/ECP5/ECP5Versa.rst: -------------------------------------------------------------------------------- 1 | 2 | ECP5 Versa 3 | ########## 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Lattice/ECP5/index.rst: -------------------------------------------------------------------------------- 1 | 2 | ECP5 3 | #### 4 | 5 | * ECP5 Versa 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | ECP5Versa 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Lattice/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Lattice 3 | ####### 4 | 5 | * ECP5 6 | * ECP5 Versa 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | ECP5/index 12 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Artix7/AC701.rst: -------------------------------------------------------------------------------- 1 | 2 | AC701 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Artix7/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Artix-7 3 | ####### 4 | 5 | * AC701 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | AC701 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Kintex7/KC705.rst: -------------------------------------------------------------------------------- 1 | 2 | KC705 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Kintex7/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Kintex-7 3 | ######## 4 | 5 | * KC705 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | KC705 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Spartan3/S3ESK.rst: -------------------------------------------------------------------------------- 1 | 2 | S3ESK 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Spartan3/S3SK.rst: -------------------------------------------------------------------------------- 1 | 2 | S3SK 3 | #### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Spartan3/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Spartan-3 3 | ######### 4 | 5 | * Spartan-3 Starter Kit (S3SK) 6 | * Spartan-3E Starter Kit (S3ESK) 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | S3SK 12 | S3ESK 13 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Spartan6/Atlys.rst: -------------------------------------------------------------------------------- 1 | 2 | Atlys 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Spartan6/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Spartan-6 3 | ######### 4 | 5 | * Atlys 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | Atlys 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex5/ML505.rst: -------------------------------------------------------------------------------- 1 | 2 | ML505 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex5/ML506.rst: -------------------------------------------------------------------------------- 1 | 2 | ML506 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex5/XUPV5.rst: -------------------------------------------------------------------------------- 1 | 2 | XUPV5 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex5/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Virtex-5 3 | ######## 4 | 5 | * ML505 6 | * ML506 7 | * XUPV5 8 | 9 | .. toctree:: 10 | :hidden: 11 | 12 | ML505 13 | ML506 14 | XUPV5 15 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex6/ML605.rst: -------------------------------------------------------------------------------- 1 | 2 | ML605 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex6/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Virtex-6 3 | ######## 4 | 5 | * ML605 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | ML605 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex7/VC707.rst: -------------------------------------------------------------------------------- 1 | 2 | VC707 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Virtex7/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Virtex-7 3 | ######## 4 | 5 | * VC707 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | VC707 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Zynq7000/ZC706.rst: -------------------------------------------------------------------------------- 1 | 2 | ZC706 3 | ##### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Zynq7000/ZedBoard.rst: -------------------------------------------------------------------------------- 1 | 2 | ZedBoard 3 | ######## 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/Zynq7000/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Zynq-7000 3 | ######### 4 | 5 | * ZC706 6 | * ZedBoard 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | ZC706 12 | ZedBoard 13 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/Xilinx/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Xilinx 3 | ###### 4 | 5 | * Spartan-3 Boards 6 | * Spartan-3 Starter Kit (S3SK) 7 | * Spartan-3E Starter Kit (S3ESK) 8 | * Spartan-6 Boards 9 | * Atlys 10 | * Artix-7 11 | * AC701 12 | * Kintex-7 13 | * KC705 14 | * Virtex-5 15 | * ML505 16 | * ML506 17 | * XUPV5 18 | * Virtex-6 19 | * ML605 20 | * Virtex-7 21 | * VC707 22 | * Zynq-7000 23 | * ZC706 24 | * ZedBoard 25 | 26 | .. toctree:: 27 | :hidden: 28 | 29 | Spartan3/index 30 | Spartan6/index 31 | Artix7/index 32 | Kintex7/index 33 | Virtex5/index 34 | Virtex6/index 35 | Virtex7/index 36 | Zynq7000/index 37 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/fifo/fifo_ic_got.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo_ic_got 3 | ########### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/fifo/index.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo 3 | #### 4 | 5 | * fifo_ic_got 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | fifo_ic_got 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/index.rst: -------------------------------------------------------------------------------- 1 | 2 | misc 3 | #### 4 | 5 | * sync 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | sync/index 11 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/sync/index.rst: -------------------------------------------------------------------------------- 1 | 2 | sync 3 | #### 4 | 5 | * sync_Bits 6 | * sync_Reset 7 | * sync_Vector 8 | * sync_Command 9 | 10 | .. toctree:: 11 | :hidden: 12 | 13 | sync_Bits 14 | sync_Reset 15 | sync_Vector 16 | sync_Command 17 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/sync/sync_Bits.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo_ic_got 3 | ########### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/sync/sync_Command.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo_ic_got 3 | ########### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/sync/sync_Reset.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo_ic_got 3 | ########### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/misc/sync/sync_Vector.rst: -------------------------------------------------------------------------------- 1 | 2 | fifo_ic_got 3 | ########### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_KC705.rst: -------------------------------------------------------------------------------- 1 | 2 | eth_RSLayer_GMII_GMII_KC705 3 | ########################### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML505.rst: -------------------------------------------------------------------------------- 1 | 2 | eth_RSLayer_GMII_GMII_ML505 3 | ########################### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/net/eth/eth_RSLayer_GMII_GMII_ML605.rst: -------------------------------------------------------------------------------- 1 | 2 | eth_RSLayer_GMII_GMII_ML605 3 | ########################### 4 | 5 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/net/eth/index.rst: -------------------------------------------------------------------------------- 1 | 2 | eth 3 | ### 4 | 5 | * eth_RSLayer_GMII_GMII_KC705 6 | * eth_RSLayer_GMII_GMII_ML505 7 | * eth_RSLayer_GMII_GMII_ML605 8 | 9 | .. toctree:: 10 | :hidden: 11 | 12 | eth_RSLayer_GMII_GMII_KC705 13 | eth_RSLayer_GMII_GMII_ML505 14 | eth_RSLayer_GMII_GMII_ML605 15 | -------------------------------------------------------------------------------- /docs/ConstraintFiles/net/index.rst: -------------------------------------------------------------------------------- 1 | 2 | net 3 | ### 4 | 5 | * eth 6 | 7 | .. toctree:: 8 | :hidden: 9 | 10 | eth/index 11 | -------------------------------------------------------------------------------- /docs/Examples/index.rst: -------------------------------------------------------------------------------- 1 | .. _EX: 2 | 3 | Examples 4 | ######## 5 | 6 | .. note:: 7 | 8 | Under construction. 9 | 10 | PoC-Exmaples repository on GitHub. 11 | -------------------------------------------------------------------------------- /docs/IPCores/alt/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:alt: 2 | 3 | PoC.alt 4 | ======== 5 | 6 | .. TODO:: This namespace is reserved for Altera specific entities. 7 | -------------------------------------------------------------------------------- /docs/IPCores/bus/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:bus: 2 | 3 | PoC.bus 4 | ======== 5 | 6 | These are bus entities.... 7 | 8 | **Sub-namespaces** 9 | 10 | * :ref:`NS:stream` 11 | * :ref:`NS:wb` 12 | 13 | **Entities** 14 | 15 | * :ref:`IP:bus_Arbiter` 16 | 17 | .. toctree:: 18 | :hidden: 19 | 20 | stream 21 | wb 22 | 23 | .. toctree:: 24 | :hidden: 25 | 26 | bus_Arbiter 27 | -------------------------------------------------------------------------------- /docs/IPCores/bus/stream/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:stream: 2 | 3 | PoC.bus.stream 4 | ============== 5 | 6 | PoC.Stream modules ... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | Package 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | stream_Buffer 17 | stream_DeMux 18 | stream_Mux 19 | stream_Mirror 20 | stream_Sink 21 | stream_Source 22 | stream_FrameGenerator 23 | -------------------------------------------------------------------------------- /docs/IPCores/bus/stream/stream.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/stream/stream.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:stream: 13 | 14 | PoC.bus.stream Package 15 | ====================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`stream.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/bus/wb/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:wb: 2 | 3 | PoC.bus.wb 4 | ========== 5 | 6 | WishBone modules ... 7 | 8 | **Entities:** 9 | 10 | .. toctree:: 11 | :hidden: 12 | 13 | Package 14 | 15 | .. toctree:: 16 | :hidden: 17 | 18 | wb_ocram 19 | wb_fifo_adapter 20 | wb_uart_wrapper 21 | -------------------------------------------------------------------------------- /docs/IPCores/bus/wb/wb.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/bus/wb/wb.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:wb: 13 | 14 | PoC.bus.wb Package 15 | ====================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`wb.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/comm/comm.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/comm/comm.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:comm: 13 | 14 | PoC.comm Package 15 | ================ 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`comm.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/comm/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:comm: 2 | 3 | PoC.comm 4 | ======== 5 | 6 | These are communication entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | Package 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | comm_crc 17 | comm_scramble 18 | -------------------------------------------------------------------------------- /docs/IPCores/comm/remote/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:comm:remote: 2 | 3 | PoC.comm.remote 4 | =============== 5 | 6 | These are communication entities.... 7 | 8 | .. # 9 | toctree:: 10 | :hidden: 11 | .. # 12 | Package 13 | 14 | .. toctree:: 15 | :hidden: 16 | 17 | remote_terminal_control 18 | -------------------------------------------------------------------------------- /docs/IPCores/common/components.rst: -------------------------------------------------------------------------------- 1 | 2 | components 3 | ^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/config.rst: -------------------------------------------------------------------------------- 1 | 2 | config 3 | ^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/context.rst: -------------------------------------------------------------------------------- 1 | 2 | context 3 | ^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/fileio.rst: -------------------------------------------------------------------------------- 1 | 2 | fileio 3 | ^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/index.rst: -------------------------------------------------------------------------------- 1 | .. _PKG_Common: 2 | 3 | Common Packages 4 | =============== 5 | 6 | These are common packages.... 7 | 8 | .. toctree:: 9 | 10 | components 11 | context 12 | config 13 | fileio 14 | math 15 | strings 16 | utils 17 | vectors 18 | -------------------------------------------------------------------------------- /docs/IPCores/common/math.rst: -------------------------------------------------------------------------------- 1 | 2 | math 3 | ^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/strings.rst: -------------------------------------------------------------------------------- 1 | 2 | strings 3 | ^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/utils.rst: -------------------------------------------------------------------------------- 1 | 2 | utils 3 | ^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/common/vectors.rst: -------------------------------------------------------------------------------- 1 | 2 | vectors 3 | ^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/dstruct/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:dstruct: 2 | 3 | PoC.dstruct 4 | =========== 5 | 6 | The namespace `PoC.dstruct` offers different data structure implementations. 7 | 8 | **Package** 9 | 10 | The package :ref:`NS:dstruct` holds all component declarations for this namespace. 11 | 12 | **Entities** 13 | 14 | * :ref:`IP:dstruct_deque` implements a deque (two-sided FIFO). 15 | * :ref:`IP:dstruct_stack` implements a regular stack. 16 | 17 | .. toctree:: 18 | :hidden: 19 | 20 | Package 21 | 22 | .. toctree:: 23 | :hidden: 24 | 25 | dstruct_deque 26 | dstruct_stack 27 | -------------------------------------------------------------------------------- /docs/IPCores/fifo/fifo.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/fifo/fifo.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:fifo: 13 | 14 | PoC.fifo Package 15 | ================ 16 | 17 | This package holds all component declarations for this namespace. 18 | 19 | .. only:: latex 20 | 21 | Source file: :pocsrc:`fifo.pkg.vhdl ` 22 | -------------------------------------------------------------------------------- /docs/IPCores/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS: 2 | 3 | IP Core Documentations 4 | ###################### 5 | 6 | Namespace for Packages: 7 | 8 | .. toctree:: 9 | 10 | common 11 | sim 12 | 13 | Namespaces for Entities: 14 | 15 | .. toctree:: 16 | 17 | alt 18 | arith 19 | bus 20 | cache 21 | comm 22 | dstruct 23 | fifo 24 | io 25 | mem 26 | misc 27 | net 28 | sort 29 | xil 30 | -------------------------------------------------------------------------------- /docs/IPCores/io/ddrio/ddrio.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/ddrio/ddrio.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:ddrio: 13 | 14 | PoC.io.ddrio Package 15 | ==================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`ddrio.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/ddrio/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ddrio: 2 | 3 | PoC.io.ddrio 4 | ============ 5 | 6 | These are :abbr:`DDR-I/O (Double Data Rate - Input/Output)` entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:ddrio_in` 11 | * :ref:`IP:ddrio_inout` 12 | * :ref:`IP:ddrio_out` 13 | 14 | 15 | .. toctree:: 16 | :hidden: 17 | 18 | Package 19 | 20 | .. toctree:: 21 | :hidden: 22 | 23 | ddrio_in 24 | ddrio_inout 25 | ddrio_out 26 | -------------------------------------------------------------------------------- /docs/IPCores/io/iic/iic.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/iic/iic.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:iic: 13 | 14 | PoC.io.iic Package 15 | ================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`iic.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/iic/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:iic: 2 | 3 | PoC.io.iic 4 | ========== 5 | 6 | These are I2C entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | Package 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | iic_BusController 17 | iic_Controller 18 | iic_Switch_PCA9548A 19 | -------------------------------------------------------------------------------- /docs/IPCores/io/io.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/io.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:io: 13 | 14 | PoC.io Package 15 | ============== 16 | 17 | This package holds all component declarations for this namespace. 18 | 19 | .. only:: latex 20 | 21 | Source file: :pocsrc:`io.pkg.vhdl ` 22 | -------------------------------------------------------------------------------- /docs/IPCores/io/jtag/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:jtag: 2 | 3 | PoC.io.jtag 4 | =========== 5 | 6 | These are JTAG entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | -------------------------------------------------------------------------------- /docs/IPCores/io/lcd/BCDDigit.rst: -------------------------------------------------------------------------------- 1 | 2 | BCDDigit 3 | ######## 4 | 5 | 6 | 7 | .. rubric:: Entity Declaration: 8 | 9 | .. literalinclude:: ../../../../src/io/lcd/BCDDigit.vhdl 10 | :language: vhdl 11 | :tab-width: 2 12 | :linenos: 13 | :lines: 10-22 14 | 15 | Source file: `io/lcd/BCDDigit.vhdl `_ 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /docs/IPCores/io/lcd/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:lcd: 2 | 3 | PoC.io.lcd 4 | ========== 5 | 6 | These are LCD entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | Package 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | lcd_LCDBuffer 17 | lcd_LCDBusController 18 | lcd_LCDController_KS0066U 19 | lcd_LCDSynchronizer 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/lcd/lcd.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/lcd/lcd.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:lcd: 13 | 14 | PoC.io.lcd Package 15 | ================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`lcd.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/mdio/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:mdio: 2 | 3 | PoC.io.mdio 4 | =========== 5 | 6 | These are MDIO entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | mdio_BusController 12 | mdio_Controller 13 | mdio_IIC_Adapter 14 | -------------------------------------------------------------------------------- /docs/IPCores/io/mdio/mdio_BusController.rst: -------------------------------------------------------------------------------- 1 | 2 | mdio_BusController 3 | ^^^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/io/ow/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ow: 2 | 3 | PoC.io.ow 4 | ========= 5 | 6 | These are OneWire entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | ow_BusController 12 | ow_Controller 13 | -------------------------------------------------------------------------------- /docs/IPCores/io/ow/ow_BusController.rst: -------------------------------------------------------------------------------- 1 | 2 | ow_BusController 3 | ^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/io/ow/ow_Controller.rst: -------------------------------------------------------------------------------- 1 | 2 | ow_Controller 3 | ^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/io/pio/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:pio: 2 | 3 | PoC.io.pio 4 | ========== 5 | 6 | These are Pmod entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | pio_in 12 | pio_out 13 | pio_fifo_in 14 | pio_fifo_out 15 | -------------------------------------------------------------------------------- /docs/IPCores/io/pmod/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:pmod: 2 | 3 | PoC.io.pmod 4 | =========== 5 | 6 | These are Pmod entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:pmod_KYPD` 11 | * :ref:`IP:pmod_SSD` 12 | * :ref:`IP:pmod_USBUART` 13 | 14 | 15 | .. toctree:: 16 | :hidden: 17 | 18 | Package 19 | 20 | .. toctree:: 21 | :hidden: 22 | 23 | pmod_KYPD 24 | pmod_SSD 25 | pmod_USBUART 26 | -------------------------------------------------------------------------------- /docs/IPCores/io/pmod/pmod.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/pmod/pmod.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:pmod: 13 | 14 | PoC.io.pmod Package 15 | =================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`pmod.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/ps2/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ps2: 2 | 3 | PoC.io.ps2 4 | ========== 5 | 6 | These are PS/2 entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | -------------------------------------------------------------------------------- /docs/IPCores/io/uart/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:uart: 2 | 3 | PoC.io.uart 4 | =========== 5 | 6 | These are :abbr:`UART (Universal Asynchronous Receiver Transmitter)` entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:uart_bclk` 11 | * :ref:`IP:uart_rx` 12 | * :ref:`IP:uart_tx` 13 | * :ref:`IP:uart_fifo` 14 | 15 | 16 | .. toctree:: 17 | :hidden: 18 | 19 | Package 20 | 21 | .. toctree:: 22 | :hidden: 23 | 24 | uart_bclk 25 | uart_rx 26 | uart_tx 27 | uart_fifo 28 | -------------------------------------------------------------------------------- /docs/IPCores/io/uart/uart.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/uart/uart.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:uart: 13 | 14 | PoC.io.uart Package 15 | =================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`uart.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/io/vga/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:vga: 2 | 3 | PoC.io.vga 4 | ========== 5 | 6 | These are VGA entities.... 7 | 8 | .. toctree:: 9 | :hidden: 10 | 11 | Package 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | vga_phy 17 | vga_phy_ch7301c 18 | vga_timing 19 | -------------------------------------------------------------------------------- /docs/IPCores/io/vga/vga.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/io/vga/vga.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:vga: 13 | 14 | PoC.io.vga Package 15 | ================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`vga.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/mem/ddr2/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ddr2: 2 | 3 | PoC.mem.ddr2 4 | ============ 5 | 6 | The namespace ``PoC.mem.ddr2`` is designated for own implementations of 7 | DDR2 memory controllers as well as for adapters for vendor-specific 8 | implementations. At the top-level, all controllers and adapters 9 | provide the same simple memory interface to the user application. 10 | 11 | .. **Package** 12 | 13 | **Entities** 14 | 15 | * :ref:`IP:ddr2_mem2mig_adapter_Spartan6` - Adapter for the Xilinx MIG core 16 | for Spartan-6 FPGAs 17 | 18 | 19 | .. toctree:: 20 | :hidden: 21 | 22 | ddr2_mem2mig_adapter_Spartan6 23 | -------------------------------------------------------------------------------- /docs/IPCores/mem/ddr3/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ddr3: 2 | 3 | PoC.mem.ddr3 4 | ============ 5 | 6 | The namespace ``PoC.mem.ddr3`` is designated for own implementations of 7 | DDR3 memory controllers as well as for adapters for vendor-specific 8 | implementations. At the top-level, all controllers and adapters 9 | provide the same simple memory interface to the user application. 10 | 11 | .. **Package** 12 | 13 | **Entities** 14 | 15 | * :ref:`IP:ddr3_mem2mig_adapter_Series7` - Adapter for the Xilinx MIG core 16 | for 7-Series FPGAs 17 | 18 | 19 | .. toctree:: 20 | :hidden: 21 | 22 | ddr3_mem2mig_adapter_Series7 23 | -------------------------------------------------------------------------------- /docs/IPCores/mem/lut/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:lut: 2 | 3 | PoC.mem.lut 4 | =========== 5 | 6 | The namespace ``PoC.mem.lut`` offers different lookup-tables (LUTs). 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:lut_Sine` - a Sine implementation with 1,2 or 4 quadrants. 11 | 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | lut_Sine 17 | -------------------------------------------------------------------------------- /docs/IPCores/mem/ocram/ocram.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocram/ocram.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:ocram: 13 | 14 | PoC.mem.ocram Package 15 | ===================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`ocram.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/mem/ocrom/ocrom.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:ocrom: 13 | 14 | PoC.mem.ocrom Package 15 | ===================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`ocrom.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/misc/filter/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:filter: 2 | 3 | PoC.misc.filter 4 | =============== 5 | 6 | These are filter entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:filter_and` 11 | * :ref:`IP:filter_mean` 12 | * :ref:`IP:filter_or` 13 | 14 | .. toctree:: 15 | :hidden: 16 | 17 | filter_and 18 | filter_mean 19 | filter_or 20 | -------------------------------------------------------------------------------- /docs/IPCores/misc/gearbox/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:gearbox: 2 | 3 | PoC.misc.gearbox 4 | ================ 5 | 6 | These are gearbox entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:gearbox_down_cc` 11 | * :ref:`IP:gearbox_down_dc` 12 | * :ref:`IP:gearbox_up_cc` 13 | * :ref:`IP:gearbox_up_dc` 14 | 15 | .. toctree:: 16 | :hidden: 17 | 18 | gearbox_down_cc 19 | gearbox_down_dc 20 | gearbox_up_cc 21 | gearbox_up_dc 22 | -------------------------------------------------------------------------------- /docs/IPCores/misc/misc.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/misc.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:misc: 13 | 14 | PoC.misc Package 15 | ================ 16 | 17 | This package holds all component declarations for this namespace. 18 | 19 | .. only:: latex 20 | 21 | Source file: :pocsrc:`misc.pkg.vhdl ` 22 | -------------------------------------------------------------------------------- /docs/IPCores/misc/misc_WordAligner.rst: -------------------------------------------------------------------------------- 1 | 2 | WordAligner 3 | ########### 4 | 5 | .. TODO:: No documentation available. 6 | 7 | 8 | .. rubric:: Entity Declaration: 9 | 10 | .. literalinclude:: ../../../src/misc/misc_WordAligner.vhdl 11 | :language: vhdl 12 | :tab-width: 2 13 | :linenos: 14 | :lines: 39-52 15 | 16 | Source file: `misc/misc_WordAligner.vhdl `_ 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /docs/IPCores/misc/stat/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:stat: 2 | 3 | PoC.misc.stat 4 | ============= 5 | 6 | These are stat entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:stat_Average` 11 | * :ref:`IP:stat_Histogram` 12 | * :ref:`IP:stat_Maximum` 13 | * :ref:`IP:stat_Minimum` 14 | 15 | 16 | .. toctree:: 17 | :hidden: 18 | 19 | stat_Average 20 | stat_Histogram 21 | stat_Maximum 22 | stat_Minimum 23 | -------------------------------------------------------------------------------- /docs/IPCores/misc/sync/sync.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:sync: 13 | 14 | PoC.misc.sync Package 15 | ===================== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`sync.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/net/arp/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:arp: 2 | 3 | PoC.net.arp 4 | =========== 5 | 6 | These are ARP entities.... 7 | 8 | .. toctree:: 9 | 10 | arp_BroadCast_Receiver 11 | arp_BroadCast_Requester 12 | arp_Cache 13 | arp_IPPool 14 | arp_Tester 15 | arp_UniCast_Receiver 16 | arp_UniCast_Responder 17 | arp_Wrapper 18 | -------------------------------------------------------------------------------- /docs/IPCores/net/eth/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:eth: 2 | 3 | PoC.net.eth 4 | =========== 5 | 6 | These are eth entities.... 7 | 8 | .. toctree:: 9 | 10 | eth_GEMAC_GMII 11 | eth_GEMAC_RX 12 | eth_GEMAC_TX 13 | eth_PHYController 14 | eth_PHYController_Marvell_88E1111 15 | eth_Wrapper 16 | -------------------------------------------------------------------------------- /docs/IPCores/net/icmpv4/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:icmpv4: 2 | 3 | PoC.net.icmpv4 4 | ============== 5 | 6 | These are icmpv4 entities.... 7 | 8 | .. toctree:: 9 | 10 | icmpv4_RX 11 | icmpv4_TX 12 | icmpv4_Wrapper 13 | -------------------------------------------------------------------------------- /docs/IPCores/net/icmpv6/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:icmpv6: 2 | 3 | PoC.net.icmpv6 4 | ============== 5 | 6 | These are icmpv6 entities.... 7 | 8 | .. toctree:: 9 | 10 | icmpv6_RX 11 | icmpv6_TX 12 | icmpv6_Wrapper 13 | -------------------------------------------------------------------------------- /docs/IPCores/net/ipv4/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ipv4: 2 | 3 | PoC.net.ipv4 4 | ============ 5 | 6 | These are ipv4 entities.... 7 | 8 | .. toctree:: 9 | 10 | ipv4_RX 11 | ipv4_TX 12 | ipv4_FrameLoopback 13 | ipv4_Wrapper 14 | -------------------------------------------------------------------------------- /docs/IPCores/net/ipv6/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ipv6: 2 | 3 | PoC.net.ipv6 4 | ============ 5 | 6 | These are ipv6 entities.... 7 | 8 | .. toctree:: 9 | 10 | ipv6_RX 11 | ipv6_TX 12 | ipv6_FrameLoopback 13 | ipv6_Wrapper 14 | -------------------------------------------------------------------------------- /docs/IPCores/net/mac/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:mac: 2 | 3 | PoC.net.mac 4 | =========== 5 | 6 | These are mac entities.... 7 | 8 | .. toctree:: 9 | 10 | mac_RX_DestMAC_Switch 11 | mac_RX_SrcMAC_Filter 12 | mac_RX_Type_Switch 13 | mac_TX_SrcMAC_Prepender 14 | mac_TX_DestMAC_Prepender 15 | mac_TX_Type_Prepender 16 | mac_FrameLoopback 17 | mac_Wrapper 18 | -------------------------------------------------------------------------------- /docs/IPCores/net/ndp/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:ndp: 2 | 3 | PoC.net.ndp 4 | =========== 5 | 6 | These are ndp entities.... 7 | 8 | .. toctree:: 9 | 10 | ndp_DestinationCache 11 | ndp_FSMQuery 12 | ndp_NeighborCache 13 | ndp_Wrapper 14 | -------------------------------------------------------------------------------- /docs/IPCores/net/net.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/net/net.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:net: 13 | 14 | PoC.net Package 15 | =============== 16 | 17 | .. only:: latex 18 | 19 | Source file: :pocsrc:`net.pkg.vhdl ` 20 | -------------------------------------------------------------------------------- /docs/IPCores/net/stack/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:stack: 2 | 3 | PoC.net.stack 4 | ============= 5 | 6 | These are udp entities.... 7 | 8 | .. toctree:: 9 | 10 | stack_IPv4 11 | stack_IPv6 12 | stack_UDPv4 13 | stack_UDPv6 14 | stack_MAC 15 | -------------------------------------------------------------------------------- /docs/IPCores/net/stack/stack_IPv4.rst: -------------------------------------------------------------------------------- 1 | 2 | stack_IPv4 3 | ^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/net/stack/stack_IPv6.rst: -------------------------------------------------------------------------------- 1 | 2 | stack_IPv6 3 | ^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/net/stack/stack_MAC.rst: -------------------------------------------------------------------------------- 1 | 2 | stack_MAC 3 | ^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/net/stack/stack_UDPv6.rst: -------------------------------------------------------------------------------- 1 | 2 | stack_UDPv6 3 | ^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/net/udp/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:udp: 2 | 3 | PoC.net.udp 4 | =========== 5 | 6 | These are udp entities.... 7 | 8 | .. toctree:: 9 | 10 | udp_RX 11 | udp_TX 12 | udp_FrameLoopback 13 | udp_Wrapper 14 | -------------------------------------------------------------------------------- /docs/IPCores/sim/index.rst: -------------------------------------------------------------------------------- 1 | .. _PKG_Sim: 2 | 3 | Simulation Packages 4 | ################### 5 | 6 | .. toctree:: 7 | 8 | sim_types 9 | sim_global.v93 10 | sim_global.v08 11 | sim_unprotected.v93 12 | sim_protected.v08 13 | sim_simulation.v93 14 | sim_simulation.v08 15 | sim_waveform 16 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_global.v08.rst: -------------------------------------------------------------------------------- 1 | 2 | sim_global (VHDL-2008) 3 | ^^^^^^^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_global.v93.rst: -------------------------------------------------------------------------------- 1 | 2 | sim_global (VHDL-93) 3 | ^^^^^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_simulation.v08.rst: -------------------------------------------------------------------------------- 1 | 2 | simulation (VHDL-2008) 3 | ^^^^^^^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_simulation.v93.rst: -------------------------------------------------------------------------------- 1 | 2 | simulation (VHDL-93) 3 | ^^^^^^^^^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_types.rst: -------------------------------------------------------------------------------- 1 | 2 | sim_types 3 | ^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/sim/sim_waveform.rst: -------------------------------------------------------------------------------- 1 | 2 | sim_waveform 3 | ^^^^^^^^^^^^ 4 | 5 | Lorem ipsum dolor sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. 6 | At vero eos et accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet. Lorem ipsum dolor 7 | sit amet, consetetur sadipscing elitr, sed diam nonumy eirmod tempor invidunt ut labore et dolore magna aliquyam erat, sed diam voluptua. At vero eos et 8 | accusam et justo duo dolores et ea rebum. Stet clita kasd gubergren, no sea takimata sanctus est Lorem ipsum dolor sit amet 9 | 10 | -------------------------------------------------------------------------------- /docs/IPCores/xil/reconfig/index.rst: -------------------------------------------------------------------------------- 1 | .. _NS:reconfig: 2 | 3 | PoC.xil.reconfig 4 | ================ 5 | 6 | These are reconfig entities.... 7 | 8 | **Entities** 9 | 10 | * :ref:`IP:reconfig_icap_fsm` 11 | * :ref:`IP:reconfig_icap_wrapper` 12 | 13 | .. toctree:: 14 | :hidden: 15 | 16 | reconfig_icap_fsm 17 | reconfig_icap_wrapper 18 | -------------------------------------------------------------------------------- /docs/IPCores/xil/xil.pkg.rst: -------------------------------------------------------------------------------- 1 | .. only:: html 2 | 3 | .. |gh-src| image:: /_static/logos/GitHub-Mark-32px.png 4 | :scale: 40 5 | :target: https://github.com/VLSI-EDA/PoC/blob/master/src/xil/xil.pkg.vhdl 6 | :alt: Source Code on GitHub 7 | 8 | .. sidebar:: GitHub Links 9 | 10 | |gh-src| :pocsrc:`Sourcecode ` 11 | 12 | .. _PKG:xil: 13 | 14 | PoC.xil Package 15 | ================ 16 | 17 | This package holds all component declarations for this namespace. 18 | 19 | .. only:: latex 20 | 21 | Source file: :pocsrc:`xil.pkg.vhdl ` 22 | -------------------------------------------------------------------------------- /docs/Interfaces/CommandStatusError.rst: -------------------------------------------------------------------------------- 1 | .. _INT:PoC.CSE: 2 | 3 | Command-Status-Error (PoC.CSE) Interface 4 | ######################################## 5 | 6 | .. TODO:: 7 | Define the PoC.CSE (Command-Status-Error) interface used in ... 8 | -------------------------------------------------------------------------------- /docs/Interfaces/FIFO.rst: -------------------------------------------------------------------------------- 1 | .. _INT:PoC.FIFO: 2 | 3 | PoC.FIFO Interface 4 | ################## 5 | 6 | .. TODO:: 7 | Define the PoC.FIFO interface (writer and reader) used in ``PoC.fifo.*`` ... 8 | -------------------------------------------------------------------------------- /docs/Interfaces/Stream.rst: -------------------------------------------------------------------------------- 1 | .. _INT:PoC.Stream: 2 | 3 | PoC.Stream Interface 4 | #################### 5 | 6 | .. TODO:: 7 | Define the PoC.Stream interface used in PoC.net.* and ``PoC.bus.stream.*`` ... 8 | -------------------------------------------------------------------------------- /docs/Interfaces/index.rst: -------------------------------------------------------------------------------- 1 | .. _INT: 2 | 3 | IP Core Interfaces 4 | ################## 5 | 6 | PoC defines a set of on-chip interfaces described in the next sections. 7 | 8 | .. toctree:: 9 | :maxdepth: 1 10 | 11 | PoC.CSE 12 | PoC.FIFO 13 | PoC.Mem 14 | PoC.Stream 15 | -------------------------------------------------------------------------------- /docs/References/CommandReference.rst: -------------------------------------------------------------------------------- 1 | .. _CmdRef: 2 | 3 | Command Reference 4 | ################# 5 | 6 | This is the command line option reference for all provided scripts 7 | (Bash, PowerShell, Perl) and programs (Python) shipped with PoC. 8 | 9 | .. toctree:: 10 | 11 | CmdRefs/Wrapper 12 | Main Program 13 | CmdRefs/Compile 14 | -------------------------------------------------------------------------------- /docs/References/FileFormats/index.rst: -------------------------------------------------------------------------------- 1 | .. _FileFormats: 2 | 3 | File Formats 4 | ############ 5 | 6 | .. toctree:: 7 | :maxdepth: 1 8 | 9 | IniFormat 10 | FilesFormat 11 | RulesFormat 12 | -------------------------------------------------------------------------------- /docs/References/more.rst: -------------------------------------------------------------------------------- 1 | 2 | More References 3 | ############### 4 | 5 | .. toctree:: 6 | :maxdepth: 1 7 | 8 | ListOfDevices 9 | ListOfBoards 10 | WrapperScriptHookFiles 11 | FileFormats/index 12 | NamingConventions 13 | KnownIssues 14 | Licenses/index 15 | -------------------------------------------------------------------------------- /docs/ToolChains/index.rst: -------------------------------------------------------------------------------- 1 | .. _CHAIN: 2 | 3 | Tool Chain Specifics 4 | #################### 5 | 6 | .. attention:: 7 | 8 | This page is under construction. 9 | 10 | 11 | Aldec Active-HDL 12 | ================ 13 | 14 | .. todo:: 15 | 16 | * No GUI mode supported 17 | * VHDL-2008 parser bug in Active-HDL 10.3 18 | 19 | 20 | Mentor QuestaSim 21 | ================ 22 | 23 | Special feature: embedded poc prodecures to recompile relaunch, rerun and save waveforms... 24 | 25 | Xilinx ISE 26 | ========== 27 | 28 | * Describe the ``use_new_parser yes`` option 29 | 30 | Xilinx Vivado 31 | ============= 32 | 33 | * Describe the ``vivado`` branch (Git). 34 | 35 | -------------------------------------------------------------------------------- /docs/UsingPoC/AddingIPCores.rst: -------------------------------------------------------------------------------- 1 | .. _USING:AddIP: 2 | 3 | Adding IP Cores to a Project 4 | ############################ 5 | 6 | Manually Addind IP Cores 7 | ************************ 8 | 9 | Adding IP Cores to Altera Quartus 10 | ================================= 11 | 12 | .. TODO:: No documentation available. 13 | 14 | Adding IP Cores to Lattice Diamond 15 | ================================== 16 | 17 | .. TODO:: No documentation available. 18 | 19 | Adding IP Cores to Xilinx ISE 20 | ============================= 21 | 22 | .. TODO:: No documentation available. 23 | 24 | Adding IP Cores to Xilinx Vivado 25 | ================================ 26 | 27 | .. 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11 | 12 | .. |hr| raw:: html 13 | 14 |
15 | -------------------------------------------------------------------------------- /docs/pyIPCMI/index.rst: -------------------------------------------------------------------------------- 1 | 2 | Python Infrastructure 3 | ##################### 4 | 5 | .. toctree:: 6 | 7 | pyIPCMI 8 | 9 | 10 | .. toctree:: 11 | 12 | Base 13 | Compiler 14 | DataBase 15 | Parser 16 | Simulator 17 | ToolChain 18 | lib 19 | 20 | .. # 21 | automodule:: pyIPCMI 22 | :members: 23 | :undoc-members: 24 | :inherited-members: 25 | :show-inheritance: -------------------------------------------------------------------------------- /lib/Xilinx-Vivado.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | if (Tool = "GHDL") then 8 | library unisim "temp/ghdl/xilinx-vivado" 9 | elseif (Tool = "Xilinx_iSim") then 10 | # implecitely referenced; nothing to reference 11 | elseif (Tool = "Mentor_vSim") then 12 | library unisim "temp/vSim/xilinx-vivado" 13 | else 14 | report "Tool not supported" 15 | end if 16 | -------------------------------------------------------------------------------- /py/.idea/.name: -------------------------------------------------------------------------------- 1 | py -------------------------------------------------------------------------------- /py/.idea/codeStyleSettings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 7 | 9 | -------------------------------------------------------------------------------- /py/.idea/codeStyles/codeStyleConfig.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 5 | -------------------------------------------------------------------------------- /py/.idea/encodings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /py/.idea/inspectionProfiles/Project_Default.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | -------------------------------------------------------------------------------- /py/.idea/markdown-exported-files.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /py/.idea/markdown-navigator/profiles_settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /py/.idea/misc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /py/.idea/modules.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /py/.idea/py.iml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 15 | -------------------------------------------------------------------------------- /py/.idea/vcs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | colorama>=0.3.7 2 | py-flags>=1.1.2 3 | -------------------------------------------------------------------------------- /sim/README.md: -------------------------------------------------------------------------------- 1 | # Simulator and Waveform Files 2 | 3 | *No documentation available.* -------------------------------------------------------------------------------- /sim/aSim.batch.tcl: -------------------------------------------------------------------------------- 1 | asim -lib {VHDLLibraryName} -asdb {TestbenchName}.asdb -log {TestbenchName}.asim.log -t 1fs -ieee_nowarn {TestbenchName} 2 | run -all 3 | bye 4 | -------------------------------------------------------------------------------- /sim/aSim.gui.tcl: -------------------------------------------------------------------------------- 1 | asim -lib {VHDLLibraryName} -asdb {TestbenchName}.asdb -log {TestbenchName}.asim.log -t 1fs -ieee_nowarn {TestbenchName} 2 | trace -rec add * 3 | run -all 4 | asdb2vcd {TestbenchName}.asdb {TestbenchName}.vcd 5 | bye 6 | -------------------------------------------------------------------------------- /sim/arith/arith_prefix_and_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /arith_prefix_and_tb/clock 7 | /arith_prefix_and_tb/x 8 | /arith_prefix_and_tb/y 9 | -------------------------------------------------------------------------------- /sim/arith/arith_prefix_or_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /arith_prefix_or_tb/clock 7 | /arith_prefix_or_tb/x 8 | /arith_prefix_or_tb/y 9 | -------------------------------------------------------------------------------- /sim/arith/arith_prng_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | /arith_prng_tb/* 4 | -------------------------------------------------------------------------------- /sim/iSim.batch.tcl: -------------------------------------------------------------------------------- 1 | run all 2 | show time 3 | exit 4 | -------------------------------------------------------------------------------- /sim/iSim.gui.tcl: -------------------------------------------------------------------------------- 1 | run all 2 | show time 3 | -------------------------------------------------------------------------------- /sim/io/uart/uart_rx_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /uart_rx_tb/clock 7 | /uart_rx_tb/reset 8 | /uart_rx_tb/bitclock 9 | /uart_rx_tb/bitclock_x8 10 | /uart_rx_tb/uart_rx 11 | /uart_rx_tb/rx_strobe 12 | /uart_rx_tb/rx_data 13 | /uart_rx_tb/rx/rst 14 | /uart_rx_tb/rx/rx 15 | /uart_rx_tb/rx/do 16 | /uart_rx_tb/rx/stb 17 | /uart_rx_tb/rx/rxs 18 | /uart_rx_tb/rx/buf 19 | /uart_rx_tb/rx/cnt 20 | /uart_rx_tb/rx/vld 21 | -------------------------------------------------------------------------------- /sim/mem/lut/lut_Sine_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /lut_sine_tb/clock 7 | /lut_sine_tb/sim_stop 8 | /lut_sine_tb/lut_in 9 | /lut_sine_tb/lut_q1_in 10 | /lut_sine_tb/lut_q1_out 11 | /lut_sine_tb/lut_q2_in 12 | /lut_sine_tb/lut_q2_out 13 | /lut_sine_tb/lut_q3_in 14 | /lut_sine_tb/lut_q3_out 15 | /lut_sine_tb/lut_q4_in 16 | /lut_sine_tb/lut_q4_out 17 | /lut_sine_tb/lutq1/input 18 | /lut_sine_tb/lutq1/output 19 | /lut_sine_tb/lutq2/input 20 | /lut_sine_tb/lutq2/output 21 | /lut_sine_tb/lutq3/input 22 | /lut_sine_tb/lutq3/output 23 | /lut_sine_tb/lutq4/input 24 | /lut_sine_tb/lutq4/output 25 | -------------------------------------------------------------------------------- /sim/mem/ocram/ocram_sdp_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /ocram_sdp_tb/rce 7 | /ocram_sdp_tb/wce 8 | /ocram_sdp_tb/we 9 | /ocram_sdp_tb/ra 10 | /ocram_sdp_tb/wa 11 | /ocram_sdp_tb/d 12 | /ocram_sdp_tb/q 13 | /ocram_sdp_tb/clk 14 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Bits_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /sync_bits_tb/clock1 7 | /sync_bits_tb/clock2 8 | /sync_bits_tb/sync_in 9 | /sync_bits_tb/sync_out 10 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Bits_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.69 (w)1999-2016 BSI 3 | [*] Sun Mar 20 14:12:41 2016 4 | [*] 5 | [dumpfile_mtime] "Sun Mar 20 14:12:23 2016" 6 | [dumpfile_size] 2602 7 | [timestart] 0 8 | [size] 1680 997 9 | [pos] -1 -1 10 | *-26.329563 85600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] top. 12 | [treeopen] top.sync_bits_tb. 13 | [sst_width] 197 14 | [signals_width] 155 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 293 17 | @28 18 | top.sync_bits_tb.clock1 19 | top.sync_bits_tb.clock2 20 | top.sync_bits_tb.sync_in[0] 21 | top.sync_bits_tb.sync_out[0] 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Command_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /sync_command_tb/clock1 7 | /sync_command_tb/clock2 8 | /sync_command_tb/sync_in 9 | /sync_command_tb/sync_out 10 | /sync_command_tb/sync_busy 11 | /sync_command_tb/sync_changed 12 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Reset_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /sync_reset_tb/clock1 7 | /sync_reset_tb/clock2 8 | /sync_reset_tb/sync_in 9 | /sync_reset_tb/sync_out 10 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Reset_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI 3 | [*] Mon Feb 08 14:40:50 2016 4 | [*] 5 | [dumpfile_mtime] "Mon Feb 08 14:39:23 2016" 6 | [dumpfile_size] 2407 7 | [timestart] 0 8 | [size] 1680 997 9 | [pos] -61 -61 10 | *-26.154070 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] top. 12 | [treeopen] top.sync_reset_tb. 13 | [sst_width] 197 14 | [signals_width] 124 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 293 17 | @28 18 | top.sync_reset_tb.clock1 19 | top.sync_reset_tb.clock2 20 | @29 21 | top.sync_reset_tb.sync_in 22 | @28 23 | top.sync_reset_tb.sync_out 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Strobe_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /sync_strobe_tb/clock1 7 | /sync_strobe_tb/clock2 8 | /sync_strobe_tb/sync_in 9 | /sync_strobe_tb/sync_out 10 | /sync_strobe_tb/sync_busy 11 | -------------------------------------------------------------------------------- /sim/misc/sync/sync_Vector_tb.ghdl: -------------------------------------------------------------------------------- 1 | $ version 1.1 2 | 3 | # Signals in packages : 4 | 5 | # Signals in entities : 6 | /sync_vector_tb/clock1 7 | /sync_vector_tb/clock2 8 | /sync_vector_tb/sync_in 9 | /sync_vector_tb/sync_out 10 | /sync_vector_tb/sync_busy 11 | /sync_vector_tb/sync_changed 12 | -------------------------------------------------------------------------------- /sim/vSim.batch.tcl: -------------------------------------------------------------------------------- 1 | run -all 2 | #coverage report -html -htmldir CoverageReport -details=abcdefgs -threshL 50 -threshH 90 3 | quit 4 | -------------------------------------------------------------------------------- /sim/vSim.default.wdo: -------------------------------------------------------------------------------- 1 | add wave * 2 | -------------------------------------------------------------------------------- /sim/vSim.gui.tcl: -------------------------------------------------------------------------------- 1 | run -all 2 | wave zoom full 3 | puts "Provided files:" 4 | puts "- 'do recompile.do' compile all sources from scratch and restart the simulation" 5 | puts "- 'do relaunch.do' recompile, restart and rerun the simulation" 6 | puts "- 'do saveWaveform.do' save current waveform selection to a *.wdo file" 7 | -------------------------------------------------------------------------------- /sim/xSim.batch.tcl: -------------------------------------------------------------------------------- 1 | run all 2 | quit 3 | -------------------------------------------------------------------------------- /sim/xSim.gui.tcl: -------------------------------------------------------------------------------- 1 | run all 2 | -------------------------------------------------------------------------------- /src/alt/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.alt` 2 | 3 | No files published, yet. 4 | -------------------------------------------------------------------------------- /src/arith/arith_convert_bin2bcd.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_convert_bin2bcd.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_counter_bcd.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_counter_bcd.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_counter_free.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_counter_free.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_counter_gray.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_counter_gray.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_counter_ring.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_counter_ring.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_div.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_div.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_prng.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_prng.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_same.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_same.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_scaler.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_scaler.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_shifter_barrel.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_shifter_barrel.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_sqrt.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/arith/arith_sqrt.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/arith/arith_trng.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" 9 | include "src/misc/sync/sync_Bits.files" 10 | 11 | # PoC.arith 12 | vhdl PoC "src/arith/arith.pkg.vhdl" # PoC.arith package 13 | vhdl PoC "src/arith/arith_trng.vhdl" # Top-Level 14 | -------------------------------------------------------------------------------- /src/bus/bus_Arbiter.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus 11 | # vhdl PoC "src/bus/bus.pkg.vhdl" # PoC.bus package 12 | vhdl PoC "src/bus/bus_Arbiter.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_Buffer.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_Buffer.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_DeMux.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_DeMux.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_FrameGenerator.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_FrameGenerator.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_Mirror.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_Mirror.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_Mux.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_Mux.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/bus/stream/stream_Source.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.bus.stream 11 | vhdl PoC "src/bus/stream/stream.pkg.vhdl" # PoC.bus.stream package 12 | vhdl PoC "src/bus/stream/stream_Source.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/cache/cache_cpu.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.cache 11 | include "src/cache/cache_par2.files" # Embedded Cache 12 | vhdl poc "src/cache/cache_cpu.vhdl" # Top Level 13 | -------------------------------------------------------------------------------- /src/comm/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.comm` 2 | 3 | The namespace `PoC.comm` offers different communication modules. 4 | 5 | 6 | ## Package 7 | 8 | The package [`PoC.comm`][comm.pkg] holds all component declarations for this namespace. 9 | 10 | 11 | ## Entities 12 | 13 | - [`comm_crc`][comm_crc] - implements a generic Cyclic Redundancy Check (CRC). 14 | - [`comm_scramble`][comm_scramble] - implements a generic LFSR based scrambler. 15 | 16 | 17 | [comm.pkg]: comm.pkg.vhdl 18 | 19 | [comm_crc]: comm_crc.vhdl 20 | [comm_scramble]: comm_scramble.vhdl 21 | -------------------------------------------------------------------------------- /src/comm/comm_crc.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.comm 11 | vhdl PoC "src/comm/comm.pkg.vhdl" # PoC.bus package 12 | vhdl PoC "src/comm/comm_crc.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/comm/comm_scramble.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.comm 11 | vhdl PoC "src/comm/comm.pkg.vhdl" # PoC.bus package 12 | vhdl PoC "src/comm/comm_scramble.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/dstruct/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.dstruct` 2 | 3 | The namespace `PoC.dstruct` offers syntheziable data structures. 4 | 5 | 6 | ## Package 7 | 8 | The package [`PoC.dstruct`][dstruct.pkg] holds all component declarations for this namespace. 9 | 10 | 11 | ## Entities 12 | 13 | - [`dstruct_deque`][dstruct_deque] - implements a deque (double-ended queue) 14 | - [`dstruct_stack`][dstruct_stack] - implements a stack (LIFO) 15 | 16 | *Note*: For FIFO storage elements see the namespace [`PoC.fifo`][src_fifo]. 17 | 18 | [dstruct.pkg]: dstruct.pkg.vhdl 19 | 20 | [dstruct_deque]: dstruct_deque.vhdl 21 | [dstruct_stack]: dstruct_stack.vhdl 22 | 23 | [src_fifo]: ../fifo 24 | -------------------------------------------------------------------------------- /src/fifo/fifo_glue.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.fifo 11 | vhdl PoC "src/fifo/fifo_glue.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/fifo/fifo_ic_assembly.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.mem.orcram 11 | include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM 12 | 13 | # PoC.fifo 14 | vhdl PoC "src/fifo/fifo_ic_assembly.vhdl" # Top-Level 15 | -------------------------------------------------------------------------------- /src/fifo/fifo_ic_got.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.mem.orcram 11 | include "src/mem/ocram/ocram_sdp.files" # Simple dual-port RAM 12 | 13 | # PoC.fifo 14 | vhdl PoC "src/fifo/fifo_ic_got.vhdl" # Top-Level 15 | -------------------------------------------------------------------------------- /src/io/iic/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.iic` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/io/io_7SegmentMux_BCD.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_7SegmentMux_BCD.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_7SegmentMux_HEX.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_7SegmentMux_HEX.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_FanControl.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_FanControl.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_FrequencyCounter.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_frequencyCounter.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_GlitchFilter.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_GlitchFilter.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_KeyPadScanner.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_KeyPadScanner.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_PulseWidthModulation.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_PulseWidthModulation.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/io_TimingCounter.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io 11 | vhdl PoC "src/io/io.pkg.vhdl" # PoC.io package 12 | vhdl PoC "src/io/io_TimingCounter.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/io/lcd/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.lcd` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/io/mdio/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.mdio` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/io/ow/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.ow` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/io/pmod/pmod_SSD.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.io.pmod 11 | vhdl PoC "src/io/pmod/pmod.pkg.vhdl" # PoC.arith package 12 | vhdl PoC "src/io/pmod/pmod_SSD.vhdl" # Top-Level 13 | 14 | -------------------------------------------------------------------------------- /src/io/ps2/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.ps2` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/io/vga/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.io.vga` 2 | 3 | *No files published, yet.* 4 | -------------------------------------------------------------------------------- /src/mem/ddr2/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.ddr2` 2 | 3 | The namespace `PoC.mem.ddr2` is designated for own implementations of 4 | DDR2 memory controllers as well as for adapters for vendor-specific 5 | implementations. At the top-level, all controllers and adapters 6 | provide the same simple memory interface to the user application. 7 | 8 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr2/index.html). 9 | -------------------------------------------------------------------------------- /src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | vhdl poc "src/mem/ddr2/ddr2_mem2mig_adapter_Spartan6.vhdl" 11 | -------------------------------------------------------------------------------- /src/mem/ddr3/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.ddr3` 2 | 3 | The namespace `PoC.mem.ddr3` is designated for own implementations of 4 | DDR3 memory controllers as well as for adapters for vendor-specific 5 | implementations. At the top-level, all controllers and adapters 6 | provide the same simple memory interface to the user application. 7 | 8 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ddr3/index.html). 9 | -------------------------------------------------------------------------------- /src/mem/ddr3/ddr3_mem2mig_adapter_Series7.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | vhdl poc "src/mem/ddr3/ddr3_mem2mig_adapter_Series7.vhdl" 11 | -------------------------------------------------------------------------------- /src/mem/lut/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.lut` 2 | 3 | The namespace `PoC.mem.lut` offers different lookup-tables (LUTs). 4 | 5 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/lut/index.html). 6 | -------------------------------------------------------------------------------- /src/mem/lut/lut_Sine.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.mem.lut 11 | vhdl poc "src/mem/lut/lut_Sine.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/mem/lut/lut_Sine.vhdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/src/mem/lut/lut_Sine.vhdl -------------------------------------------------------------------------------- /src/mem/ocram/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.ocram` 2 | 3 | The namespace `PoC.mem.ocram` offers different on-chip RAM abstractions. 4 | 5 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ocram/index.html). 6 | -------------------------------------------------------------------------------- /src/mem/ocram/ocram_sdp_wf.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" 9 | 10 | # PoC.mem.ocram 11 | include "src/mem/ocram/ocram_sdp.files" 12 | vhdl poc "src/mem/ocram/ocram_sdp_wf.vhdl" 13 | -------------------------------------------------------------------------------- /src/mem/ocram/ocram_tdp_wf.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" 9 | 10 | # PoC.mem.ocram 11 | include "src/mem/ocram/ocram_tdp.files" 12 | vhdl poc "src/mem/ocram/ocram_tdp_wf.vhdl" 13 | -------------------------------------------------------------------------------- /src/mem/ocrom/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.ocrom` 2 | 3 | The namespace `PoC.mem.ocrom` offers different on-chip ROM abstractions. 4 | 5 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/ocrom/index.html). 6 | -------------------------------------------------------------------------------- /src/mem/sdram/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.mem.sdram` 2 | 3 | The namespace `PoC.mem.sdram` offers components for the access of external SDRAMs. 4 | A common finite state-machine is used to address the memory via banks, rows and 5 | columns. Different physical layers are provide for the single-data-rate (SDR) or 6 | double-data-rate (DDR, DDR2, ...) data bus. One has to instantiate the specific 7 | module required by the FPGA board. 8 | 9 | Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/sdram/index.html). 10 | -------------------------------------------------------------------------------- /src/misc/filter/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.misc.filter` 2 | 3 | The namespace `PoC.misc.filter` offers different 1-bit filter algorthims. 4 | 5 | 6 | ## Package(s) 7 | 8 | The package [`PoC.filter`][filter.pkg] holds all component declarations for this namespace. 9 | 10 | 11 | ## Entities 12 | 13 | - [`filter_and`][filter_and] 14 | - [`filter_or`][filter_or] 15 | - [`filter_mean`][filter_mean] 16 | 17 | 18 | [filter.pkg]: filter.pkg.vhdl 19 | [filter_and]: filter_and.vhdl 20 | [filter_or]: filter_or.vhdl 21 | [filter_mean]: filter_mean.vhdl 22 | -------------------------------------------------------------------------------- /src/misc/filter/filter_and.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.filter 11 | vhdl poc "src/misc/filter/filter_and.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/filter/filter_mean.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.filter 11 | vhdl poc "src/misc/filter/filter_mean.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/filter/filter_or.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.filter 11 | vhdl poc "src/misc/filter/filter_or.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/gearbox/gearbox_down_cc.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.gearbox 11 | vhdl poc "src/misc/gearbox/gearbox_down_cc.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/gearbox/gearbox_down_dc.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.gearbox 11 | vhdl poc "src/misc/gearbox/gearbox_down_dc.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/gearbox/gearbox_up_cc.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.gearbox 11 | vhdl poc "src/misc/gearbox/gearbox_up_cc.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/gearbox/gearbox_up_dc.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.gearbox 11 | vhdl poc "src/misc/gearbox/gearbox_up_dc.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/misc_Delay.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc 11 | vhdl poc "src/misc/misc_Delay.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/misc_FrequencyMeasurement.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc 11 | vhdl poc "src/misc/misc_FrequencyMeasurement.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/stat/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.misc.stat` 2 | 3 | The namespace `PoC.misc.stat` offers different statistic modules. 4 | 5 | 6 | ## Package(s) 7 | 8 | The package [`PoC.stat`][stat.pkg] holds all component declarations for this namespace. 9 | 10 | 11 | ## Entities 12 | 13 | - [`stat_Average`][stat_Average] 14 | - [`stat_Histogram`][stat_Histogram] 15 | - [`stat_Maximum`][stat_Maximum] 16 | - [`stat_Minimum`][stat_Minimum] 17 | 18 | [stat.pkg]: stat.pkg.vhdl 19 | [stat_Average]: stat_Average.vhdl 20 | [stat_Histogram]: stat_Histogram.vhdl 21 | [stat_Maximum]: stat_Maximum.vhdl 22 | [stat_Minimum]: stat_Minimum.vhdl 23 | -------------------------------------------------------------------------------- /src/misc/stat/stat_Average.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | include "src/arith/arith_div.files" # pipelined division 12 | 13 | # PoC.misc.stat 14 | vhdl poc "src/misc/stat/stat_Average.vhdl" # Top-Level 15 | -------------------------------------------------------------------------------- /src/misc/stat/stat_Histogram.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.stat 11 | vhdl poc "src/misc/stat/stat_Histogram.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/stat/stat_Maximum.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.stat 11 | vhdl poc "src/misc/stat/stat_Maximum.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/stat/stat_Minimum.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.stat 11 | vhdl poc "src/misc/stat/stat_Minimum.vhdl" # Top-Level 12 | -------------------------------------------------------------------------------- /src/misc/sync/sync_Command.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.sync 11 | include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer 12 | vhdl poc "src/misc/sync/sync_Command.vhdl" # 13 | -------------------------------------------------------------------------------- /src/misc/sync/sync_Strobe.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.sync 11 | include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer 12 | vhdl poc "src/misc/sync/sync_Strobe.vhdl" # 13 | -------------------------------------------------------------------------------- /src/misc/sync/sync_Vector.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.misc.sync 11 | include "src/misc/sync/sync_Bits.files" # Generic 2-FF synchronizer 12 | vhdl poc "src/misc/sync/sync_Vector.vhdl" # 13 | -------------------------------------------------------------------------------- /src/net/eth/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.net.eth` 2 | 3 | The namespace `PoC.net.eth` offers an Ethernet (CSMA/CD; IEEE 802.3) implementation. 4 | 5 | ## Package 6 | 7 | *No files published, yet.* 8 | 9 | 10 | ## Entities 11 | 12 | *No files published, yet.* 13 | -------------------------------------------------------------------------------- /src/net/icmpv6/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.net.icmpv6` 2 | 3 | The namespace `PoC.net.icmpv6` offers an "Internet Control Message Protocol - Version 6" (ICMPv6) implementation. 4 | 5 | ## Package 6 | 7 | *No files published, yet.* 8 | 9 | 10 | ## Entities 11 | 12 | *No files published, yet.* 13 | -------------------------------------------------------------------------------- /src/net/ndp/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.net.ndp` 2 | 3 | The namespace `PoC.net.ndp` offers a "Neighbor Discovery Protocol" (NDP) implementation. 4 | 5 | ## Package 6 | 7 | *No files published, yet.* 8 | 9 | 10 | ## Entities 11 | 12 | *No files published, yet.* 13 | -------------------------------------------------------------------------------- /src/net/stack/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.net.stack` 2 | 3 | The namespace `PoC.net.stack` offers pre-configure common network stack implementation. 4 | 5 | ## Package 6 | 7 | *No files published, yet.* 8 | 9 | 10 | ## Entities 11 | 12 | *No files published, yet.* 13 | -------------------------------------------------------------------------------- /src/net/udp/README.md: -------------------------------------------------------------------------------- 1 | # Namespace `PoC.net.udp` 2 | 3 | The namespace `PoC.net.udp` offers an "User Datagram Protocol" (UDP) implementation. UDP can be used on top of IPv4 and IPv6. 4 | 5 | 6 | ## Entities 7 | 8 | - [`PoC.net.udp.TX`][net_udp_TX] 9 | - [`PoC.net.udp.RX`][net_udp_RX] 10 | - [`PoC.net.udp.FrameLoopback`][net_udp_FrameLoopback] 11 | - [`PoC.net.udp.Wrapper`][net_udp_Wrapper] 12 | 13 | 14 | [net_udp_TX]: udp_TX.vhdl 15 | [net_udp_RX]: udp_RX.vhdl 16 | [net_udp_FrameLoopback]: udp_FrameLoopback.vhdl 17 | [net_udp_Wrapper]: udp_Wrapper.vhdl 18 | 19 | -------------------------------------------------------------------------------- /src/sort/sort_lru_cache.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | include "src/arith/arith_prefix_and.files" 12 | 13 | # PoC.sort 14 | vhdl poc "src/sort/sort_lru_cache.vhdl" # Top-Level 15 | -------------------------------------------------------------------------------- /src/sort/sort_lru_list.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.arith 11 | include "src/arith/arith_prefix_and.files" 12 | 13 | # PoC.sort 14 | vhdl poc "src/sort/sort_lru_list.vhdl" # Top-Level 15 | -------------------------------------------------------------------------------- /src/sort/sortnet/sortnet_BitonicSort.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.sort.sortnet 11 | vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # 12 | vhdl poc "src/sort/sortnet/sortnet_BitonicSort.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/sort/sortnet/sortnet_MergeSort_Streamed.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.sort.sortnet 11 | vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # 12 | vhdl poc "src/sort/sortnet/sortnet_MergeSort_Streamed.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/sort/sortnet/sortnet_OddEvenMergeSort.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.sort.sortnet 11 | vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # 12 | vhdl poc "src/sort/sortnet/sortnet_OddEvenMergeSort.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/sort/sortnet/sortnet_OddEvenSort.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.sort.sortnet 11 | vhdl poc "src/sort/sortnet/sortnet.pkg.vhdl" # 12 | vhdl poc "src/sort/sortnet/sortnet_OddEvenSort.vhdl" # Top-Level 13 | -------------------------------------------------------------------------------- /src/xil/xil_ICAP.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # PoC.xil 11 | if (Vendor = "Xilinx") then 12 | vhdl PoC "src/xil/xil_ICAP.vhdl" # Top-Level 13 | else 14 | report "These modules are for Xilinx only." 15 | end if 16 | -------------------------------------------------------------------------------- /tb/arith/arith_addw_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_addw.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | if (Tool in ["Xilinx_iSim", "Xilinx_xSim"]) then 12 | vhdl test "tb/arith/arith_addw_tb.iSim.vhdl" # Testbench 13 | else 14 | vhdl test "tb/arith/arith_addw_tb.vhdl" # Testbench 15 | end if 16 | -------------------------------------------------------------------------------- /tb/arith/arith_convert_bin2bcd_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_convert_bin2bcd.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/arith/arith_convert_bin2bcd_tb.vhdl" # Testbench 12 | 13 | -------------------------------------------------------------------------------- /tb/arith/arith_counter_bcd_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_counter_bcd.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/arith/arith_counter_bcd_tb.vhdl" # Testbench 12 | 13 | -------------------------------------------------------------------------------- /tb/arith/arith_div_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_div.files" # Unit Under Test 9 | 10 | if (VHDLVersion < 2002) then 11 | report "VHDL version not supported." 12 | end if 13 | 14 | # Testbench file(s) 15 | vhdl test "tb/arith/arith_div_tb.vhdl" # Testbench 16 | -------------------------------------------------------------------------------- /tb/arith/arith_firstone_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_firstone.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/arith/arith_firstone_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/arith/arith_prefix_and_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_prefix_and.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | if (Tool = "Xilinx_iSim") then 12 | vhdl test "tb/arith/arith_prefix_and_tb.iSim.vhdl" # Testbench 13 | else 14 | vhdl test "tb/arith/arith_prefix_and_tb.vhdl" # Testbench 15 | end if 16 | -------------------------------------------------------------------------------- /tb/arith/arith_prefix_or_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_prefix_or.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/arith/arith_prefix_or_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/arith/arith_prng_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_prng.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | if ((Tool in ["Xilinx_iSim", "Xilinx_xSim"]) and (VHDLVersion < 2008)) then 12 | vhdl test "tb/arith/arith_prng_tb.isim.vhdl" # Testbench 13 | else 14 | vhdl test "tb/arith/arith_prng_tb.vhdl" # Testbench 15 | end if 16 | -------------------------------------------------------------------------------- /tb/arith/arith_scaler_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.arith 8 | include "src/arith/arith_scaler.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/arith/arith_scaler_tb.vhdl" # Testbench 12 | 13 | -------------------------------------------------------------------------------- /tb/cache/cache_cpu_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.cache 8 | include "src/cache/cache_cpu.files" # UUT (Unit Under Test) 9 | 10 | # PoC.arith 11 | include "src/arith/arith_prng.files" 12 | 13 | # Testbench files 14 | vhdl test "tb/mem/mem_model.vhdl" # Memory Model 15 | vhdl test "tb/cache/cache_cpu_tb.vhdl" # Testbench 16 | -------------------------------------------------------------------------------- /tb/cache/cache_mem_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.cache 8 | include "src/cache/cache_mem.files" # UUT (Unit Under Test) 9 | 10 | # PoC.arith 11 | include "src/arith/arith_prng.files" 12 | 13 | # Testbench files 14 | vhdl test "tb/mem/mem_model.vhdl" # Memory Model 15 | vhdl test "tb/cache/cache_mem_tb.vhdl" # Testbench 16 | -------------------------------------------------------------------------------- /tb/cache/cache_par2_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.cache 8 | include "src/cache/cache_par2.files" # UUT (Unit Under Test) 9 | 10 | # Testbench file(s) 11 | if (ToolChain = "Cocotb") then 12 | cocotb "tb/common/utils.py" 13 | cocotb "tb/common/lru_dict.py" 14 | cocotb "tb/cache/cache_par2_cocotb.py" # Cocotb Testbench 15 | else 16 | report "Only Cocotb testbench available." 17 | end if 18 | -------------------------------------------------------------------------------- /tb/cache/cache_par_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.cache 8 | include "src/cache/cache_par.files" # UUT (Unit Under Test) 9 | 10 | # Testbench file(s) 11 | if (ToolChain = "Cocotb") then 12 | cocotb "tb/common/utils.py" 13 | cocotb "tb/common/lru_dict.py" 14 | cocotb "tb/cache/cache_par_cocotb.py" # Cocotb Testbench 15 | else 16 | report "Only Cocotb testbench available." 17 | end if 18 | -------------------------------------------------------------------------------- /tb/common/config_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Testbench file(s) 8 | include "src/common/common.files" 9 | 10 | vhdl test "tb/common/config_tb.vhdl" # Testbench 11 | -------------------------------------------------------------------------------- /tb/common/physical_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Testbench file(s) 8 | include "src/common/common.files" 9 | 10 | vhdl test "tb/common/physical_tb.vhdl" 11 | -------------------------------------------------------------------------------- /tb/common/strings_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Testbench file(s) 8 | include "src/common/common.files" 9 | 10 | vhdl test "tb/common/strings_tb.vhdl" # Testbench 11 | -------------------------------------------------------------------------------- /tb/dstruct/dstruct_deque_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.dstruct 8 | include "src/dstruct/dstruct_deque.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/dstruct/dstruct_deque_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/dstruct/dstruct_stack_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.dstruct 8 | include "src/dstruct/dstruct_stack.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/dstruct/dstruct_stack_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/fifo/fifo_cc_got_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.fifo 8 | include "src/fifo/fifo_cc_got.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/fifo/fifo_cc_got_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/fifo/fifo_cc_got_tempput_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.comm 8 | include "src/comm/comm_scramble.files" # Scrambler 9 | 10 | # PoC.fifo 11 | include "src/fifo/fifo_cc_got_tempput.files" # Unit Under Test 12 | 13 | # Testbench file(s) 14 | vhdl test "tb/fifo/fifo_cc_got_tempput_tb.vhdl" # Testbench 15 | -------------------------------------------------------------------------------- /tb/fifo/fifo_ic_assembly_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.fifo 8 | include "src/fifo/fifo_ic_assembly.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/fifo/fifo_ic_assembly_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/fifo/fifo_ic_got_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.comm 8 | include "src/comm/comm_scramble.files" # Scrambler 9 | 10 | # PoC.fifo 11 | include "src/fifo/fifo_ic_got.files" # Unit Under Test 12 | 13 | # PoC.comm 14 | include "src/comm/comm_scramble.files" 15 | 16 | # Testbench file(s) 17 | vhdl test "tb/fifo/fifo_ic_got_tb.vhdl" # Testbench 18 | -------------------------------------------------------------------------------- /tb/io/ddrio/ddrio_in_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.io 8 | include "src/io/ddrio/ddrio_in.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/io/ddrio/ddrio_in_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/io/ddrio/ddrio_inout_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.io 8 | include "src/io/ddrio/ddrio_inout.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/io/ddrio/ddrio_inout_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/io/ddrio/ddrio_out_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.io 8 | include "src/io/ddrio/ddrio_out.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/io/ddrio/ddrio_out_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/io/io_Debounce_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.io 8 | include "src/io/io_Debounce.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/io/io_Debounce_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/lut/lut_Sine_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.lut 8 | include "src/mem/lut/lut_Sine.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/mem/lut/lut_Sine_tb.vhdl" # Testbench 12 | 13 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_esdp_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_esdp.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_esdp_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_sdp_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_sdp.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_sdp_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_sdp_wf_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_sdp_wf.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_sdp_wf_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_sp_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_sp.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_sp_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_tdp_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_tdp.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_tdp_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/mem/ocram/ocram_tdp_wf_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.mem.ocram 8 | include "src/mem/ocram/ocram_tdp_wf.files" # Unit Under Test 9 | 10 | # Testbench files 11 | vhdl test "tb/mem/ocram/ocram_tdp_wf_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/gearbox/gearbox_down_cc_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Load external vendor libraries 8 | include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) 9 | 10 | # PoC.misc.gearbox 11 | include "src/misc/gearbox/gearbox_down_cc.files" # UUT (Unit Under Test) 12 | 13 | # Testbench file(s) 14 | vhdl test "tb/misc/gearbox/gearbox_down_cc_tb.vhdl" # Testbench 15 | -------------------------------------------------------------------------------- /tb/misc/gearbox/gearbox_down_dc_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Load external vendor libraries 8 | include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) 9 | 10 | # PoC.misc.gearbox 11 | include "src/misc/gearbox/gearbox_down_dc.files" # UUT (Unit Under Test) 12 | 13 | # Testbench file(s) 14 | vhdl test "tb/misc/gearbox/gearbox_down_dc_tb.vhdl" # Testbench 15 | -------------------------------------------------------------------------------- /tb/misc/gearbox/gearbox_up_cc_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Load external vendor libraries 8 | include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) 9 | 10 | # PoC.misc.gearbox 11 | include "src/misc/gearbox/gearbox_up_cc.files" # UUT (Unit Under Test) 12 | 13 | # Testbench file(s) 14 | vhdl test "tb/misc/gearbox/gearbox_up_cc_tb.vhdl" # Testbench 15 | -------------------------------------------------------------------------------- /tb/misc/gearbox/gearbox_up_dc_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Load external vendor libraries 8 | include "lib/OSVVM.files" # Open Source VHDL Verification Methodology (OS-VVM) 9 | 10 | # PoC.misc.gearbox 11 | include "src/misc/gearbox/gearbox_up_dc.files" # UUT (Unit Under Test) 12 | 13 | # Testbench file(s) 14 | vhdl test "tb/misc/gearbox/gearbox_up_dc_tb.vhdl" # Testbench 15 | -------------------------------------------------------------------------------- /tb/misc/stat/stat_Average_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.stat 8 | include "src/misc/stat/stat_Average.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/stat/stat_Average_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/stat/stat_Histogram_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.stat 8 | include "src/misc/stat/stat_Histogram.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/stat/stat_Histogram_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/stat/stat_Maximum_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.stat 8 | include "src/misc/stat/stat_Maximum.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/stat/stat_Maximum_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/stat/stat_Minimum_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.stat 8 | include "src/misc/stat/stat_Minimum.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/stat/stat_Minimum_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/sync/sync_Bits_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.sync 8 | include "src/misc/sync/sync_Bits.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/sync/sync_Bits_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/sync/sync_Command_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.sync 8 | include "src/misc/sync/sync_Command.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/sync/sync_Command_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/sync/sync_Reset_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.sync 8 | include "src/misc/sync/sync_Reset.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/sync/sync_Reset_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/sync/sync_Strobe_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.sync 8 | include "src/misc/sync/sync_Strobe.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/sync/sync_Strobe_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/misc/sync/sync_Vector_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.misc.sync 8 | include "src/misc/sync/sync_Vector.files" # Unit Under Test 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/misc/sync/sync_Vector_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/sim/sim_VCDParser_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # Load common packages 9 | vhdl PoC "src/sim/sim_VCDParser.vhdl" # VCD parser 10 | 11 | # Testbench file(s) 12 | vhdl test "tb/sim/sim_VCDParser_tb.vhdl" # Testbench 13 | -------------------------------------------------------------------------------- /tb/sim/sim_Waveform_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # Common PoC packages for configuration, synthesis and simulation 8 | include "src/common/common.files" # load common packages 9 | 10 | # Testbench file(s) 11 | vhdl test "tb/sim/sim_Waveform_tb.vhdl" # Testbench 12 | -------------------------------------------------------------------------------- /tb/sort/sort_lru_list_tb.files: -------------------------------------------------------------------------------- 1 | # EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- 2 | # vim: tabstop=2:shiftwidth=2:noexpandtab 3 | # kate: tab-width 2; replace-tabs off; indent-width 2; 4 | # ============================================================================== 5 | # Note: all files are relative to PoC root directory 6 | # 7 | # PoC.sort 8 | include "src/sort/sort_lru_list.files" # UUT (Unit Under Test) 9 | 10 | # Testbench file(s) 11 | if (ToolChain = "Cocotb") then 12 | cocotb "tb/common/lru_dict.py" 13 | cocotb "tb/sort/sort_lru_list_cocotb.py" # Cocotb Testbench 14 | else 15 | report "Only Cocotb testbench available." 16 | end if 17 | -------------------------------------------------------------------------------- /tcl/README.md: -------------------------------------------------------------------------------- 1 | # Tcl Procedures and Scripts 2 | 3 | This directory provides a collection of code snippets to support the workflow 4 | on Tcl-controlled tools. The tasks of Tcl scripts are quite versatile and 5 | can be distinguished, at least, into: 6 | 7 | * tool control, and 8 | * constraint specification. 9 | 10 | Both of these tasks typically demand inherently tool- or device-dependent 11 | code. So, please, classify scripts into an appropriate subdirectory that 12 | identifies: 13 | 14 | * the targeted tool, or 15 | * the target hardware platform. 16 | -------------------------------------------------------------------------------- /temp/.gitempty: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/temp/.gitempty -------------------------------------------------------------------------------- /temp/README.md: -------------------------------------------------------------------------------- 1 | # Temporary directory 2 | 3 | This folder and its sub-folders are used by several external tools as working 4 | directories. All sub-folders can be removed to cleanup intermediat steps or to 5 | free disk space. 6 | -------------------------------------------------------------------------------- /temp/precompiled/.gitempty: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/temp/precompiled/.gitempty -------------------------------------------------------------------------------- /tools/AppVeyor/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | others = $MODEL_TECH/../modelsim.ini 3 | -------------------------------------------------------------------------------- /tools/AppVeyor/requirements.txt: -------------------------------------------------------------------------------- 1 | -r ../../requirements.txt 2 | -------------------------------------------------------------------------------- /tools/GitLab-CI/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | others = $MODEL_TECH/../modelsim.ini 3 | -------------------------------------------------------------------------------- /tools/GitLab-CI/requirements.txt: -------------------------------------------------------------------------------- 1 | -r ../../requirements.txt 2 | -------------------------------------------------------------------------------- /tools/ReadTheDocs/requirements.txt: -------------------------------------------------------------------------------- 1 | -r ../../requirements.txt 2 | sphinx>=1.5.3 3 | sphinxcontrib-autoprogram>=0.1.3 4 | #sphinxcontrib-actdiag>=0.8.5 5 | #sphinxcontrib-seqdiag>=0.8.5 6 | sphinxcontrib-wavedrom>=1.3.0 7 | # sphinxcontrib-textstyle>=0.2.1 8 | # sphinxcontrib-spelling>=2.2.0 9 | autoapi 10 | # changelog>=0.3.5 11 | -------------------------------------------------------------------------------- /tools/Travis-CI/modelsim.ini: -------------------------------------------------------------------------------- 1 | [Library] 2 | others = $MODEL_TECH/../modelsim.ini 3 | -------------------------------------------------------------------------------- /tools/Travis-CI/requirements.txt: -------------------------------------------------------------------------------- 1 | -r ../../requirements.txt 2 | -------------------------------------------------------------------------------- /tools/precompile/ghdl.grcrules: -------------------------------------------------------------------------------- 1 | # color warnings 2 | regexp=^.*?:\d+:\d+:warning: .* 3 | colours=yellow 4 | count=stop 5 | ========= 6 | 7 | # color errors 8 | regexp=^.*?:\d+:\d+: .* 9 | colours=red 10 | count=stop 11 | ========= 12 | 13 | # skip additional message line on Linux 14 | regexp=^ghdl: compilation error 15 | skip=yes 16 | -------------------------------------------------------------------------------- /tools/precompile/ghdl.skipwarning.grcrules: -------------------------------------------------------------------------------- 1 | # skip warnings 2 | regexp=^.*?:\d+:\d+:warning: .* 3 | skip=yes 4 | ========= 5 | 6 | # color errors 7 | regexp=^.*?:\d+:\d+: .* 8 | colours=red 9 | count=stop 10 | ========= 11 | 12 | # skip additional message line on Linux 13 | regexp=^ghdl: compilation error 14 | skip=yes 15 | -------------------------------------------------------------------------------- /ucf/Atlys/Bus.IIC.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## I²C-Bus 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 0 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: JA (PMODA) 7 | ## ----------------------------------------------------------------------------- 8 | NET "Atlys_JA_SerialClock" LOC = "C13" | IOSTANDARD = LVCMOS33; ## {INOUT} JA - Pin 17 - SerialClock 9 | NET "Atlys_JA_SerialData" LOC = "A13" | IOSTANDARD = LVCMOS33; ## {INOUT} JA - Pin 18 - SerialData 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "Atlys_JA_Serial*" TIG; 13 | -------------------------------------------------------------------------------- /ucf/Atlys/USB_UART.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## USB UART 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 0 5 | ## VCCO: 3.3V (VCC3V3) 6 | ## Location: IC7 7 | ## Vendor: EXAR 8 | ## Device: XR21V1410L16 9 | ## Baud-Rate: 300 Bd - 12 MBd 10 | ## Note: FPGA is the master, USB-UART is the slave => so TX is an output and RX an input 11 | NET "Atlys_USB_UART_TX" LOC = "A16" ; ## {IN} IC7.9 {OUT} 12 | NET "Atlys_USB_UART_RX" LOC = "B16" ; ## {OUT} IC7.10 {IN} 13 | NET "Atlys_USB_UART_?X" IOSTANDARD = LVCMOS33; 14 | 15 | ## Ignore timings on async I/O pins 16 | NET "Atlys_USB_UART_?X" TIG; 17 | -------------------------------------------------------------------------------- /ucf/DE4/FanControl.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## Fan Control 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: J48, Q1 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_FanControl] 13 | } 14 | -------------------------------------------------------------------------------- /ucf/DE4/GPIO.LED.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_GPIO_LED_n*] 13 | } 14 | -------------------------------------------------------------------------------- /ucf/DE4/GPIO.Seg7.sdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 5 | ## VCCO: 6 | ## Location: 7 | ## ----------------------------------------------------------------------------- 8 | if {$TimingConstraints == 0} then { 9 | # is it possible to define pin and I/O standard constraints here? 10 | } else { 11 | # Ignore timings on async I/O pins 12 | set_false_path -to [get_ports DE4_GPIO_Seg7_Digit0_n*] 13 | set_false_path -to [get_ports DE4_GPIO_Seg7_Digit1_n*] 14 | } 15 | -------------------------------------------------------------------------------- /ucf/KC705/Bus.PMBus.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PowerManagementBus (PMBus) 3 | ## ----------------------------------------------------------------------------- 4 | #$ ## Bank: 15 5 | #$ ## VCCO: 1,8V (VCC1V8_FPGA) 6 | #$ ## Location: 7 | #$ ## Vendor: 8 | #$ ## Device: 9 | #$ ##NET "KC705_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## 10 | #$ ##NET "KC705_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## 11 | #$ ##NET "KC705_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## 12 | 13 | ## Ignore timings on async I/O pins 14 | #$ NET "KC705_LCD_*" TIG; 15 | -------------------------------------------------------------------------------- /ucf/ML505/Bus.IIC.Monitor.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## I2C-MonitorBus 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | ## Devices: ?? 8 | ## Location: 9 | ## Vendor: 10 | ## Device: 11 | ## I²C-Address: 12 | NET "ML505_IIC_Monitor_SerialClock" LOC = "U27"; ## 13 | NET "ML505_IIC_Monitor_SerialData" LOC = "T29"; ## 14 | NET "ML505_IIC_Monitor_*" PULLUP; 15 | NET "ML505_IIC_Monitor_*" IOSTANDARD = LVCMOS18; 16 | 17 | ## Ignore timings on async I/O pins 18 | NET "ML505_IIC_Monitor_*" TIG; 19 | -------------------------------------------------------------------------------- /ucf/ML505/Bus.PS2.Keyboard.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PS2-Bus - Keyboard 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | NET "ML505_PS2_Keyboard_SerialClock" LOC = "T26"; ## external 4k7 pullup resistor 8 | NET "ML505_PS2_Keyboard_SerialData" LOC = "T25"; ## external 4k7 pullup resistor 9 | NET "ML505_PS2_Keyboard_*" IOSTANDARD = LVCMOS18; 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "ML505_PS2_Keyboard_*" TIG; 13 | -------------------------------------------------------------------------------- /ucf/ML505/Bus.PS2.Mouse.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## PS2-Bus - Mouse 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1.8V (VCC1V8) 6 | ## ----------------------------------------------------------------------------- 7 | NET "ML505_PS2_Mouse_SerialClock" LOC = "R27"; ## external 4k7 pullup resistor 8 | NET "ML505_PS2_Mouse_SerialData" LOC = "U26"; ## external 4k7 pullup resistor 9 | NET "ML505_PS2_Mouse_*" IOSTANDARD = LVCMOS18; 10 | 11 | ## Ignore timings on async I/O pins 12 | NET "ML505_PS2_Mouse_*" TIG; 13 | -------------------------------------------------------------------------------- /ucf/ML505/Clock.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## SMA Clock 2 | ## ============================================================================= 3 | ## Bank: 14 4 | ## VCCO: 2.5V (VCC2V5_FPGA) 5 | ## Location: J10, J11 6 | NET "ML505_SMAClock_in_p" LOC = "H14" | IOSTANDARD = LVCMOS25; ## {INOUT} J10 7 | NET "ML505_SMAClock_in_n" LOC = "H15" | IOSTANDARD = LVCMOS25; ## {INOUT} J11 8 | -------------------------------------------------------------------------------- /ucf/ML505/Clock.UserClock.ucf: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ============================================================================= 3 | ## Bank: 4 4 | ## VCCO: 3.3V (VCC3V3) 5 | ## Location: X1; single-ended clock socket 6 | ## Oscillator: 100 MHz 7 | ## Vendor: 8 | ## Device: 9 | ## Frequency: 100.0 MHz 10 | NET "ML505_UserClock" LOC = "AH15"; ## {IN} X1.Out 11 | NET "ML505_UserClock" IOSTANDARD = LVCMOS33; 12 | ## 13 | NET "ML505_UserClock" TNM_NET = "TGRP_UserClock"; 14 | TIMESPEC "TS_UserClock" = PERIOD "TGRP_UserClock" 100 MHz HIGH 40 %; 15 | -------------------------------------------------------------------------------- /ucf/ML505/GPIO.Button.Special.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Special Buttons 3 | ## ============================================================================= 4 | ## Bank: 20 5 | ## VCCO: 3.3V (VCC3V3_FPGA) 6 | ## Location: SW7 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_Button_CPU_Reset_n" LOC = "E9" | IOSTANDARD = LVCMOS33; ## {IN} low-active; external 4k7 pullup resistor 9 | 10 | ## Ignore timings on async I/O pins 11 | NET "ML505_GPIO_Button_CPU_Reset_n" TIG; 12 | -------------------------------------------------------------------------------- /ucf/ML505/GPIO.LED.Error.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## LEDs 3 | ## ============================================================================= 4 | ## Bank: 12 5 | ## VCCO: 3.3V (VCC1V8_FPGA) 6 | ## Location: DS5, DS6 7 | ## ----------------------------------------------------------------------------- 8 | NET "ML505_GPIO_LED_Error<0>" LOC = "F6"; ## DS6 9 | NET "ML505_GPIO_LED_Error<1>" LOC = "T10"; ## DS5 10 | NET "ML505_GPIO_LED_Error" IOSTANDARD = LVCMOS33; 11 | NET "ML505_GPIO_LED_Error" SLEW = SLOW; 12 | 13 | ## Ignore timings on async I/O pins 14 | NET "ML505_GPIO_LED_Error" TIG; 15 | -------------------------------------------------------------------------------- /ucf/ML505/Transceiver.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 3 4 | ## ReferenceClock (see Transceiver.SMA_RefClock.ucf) 5 | 6 | ## SMA LVDS signal-pairs 7 | ## -------------------------- 8 | ## Bank: 116 9 | ## LOC X0Y4 - GTP_DUAL port 1 10 | ## Location: P27, J28, J29, J30 11 | NET "ML505_SMA_TX_p" LOC = "L2"; ## J29 12 | NET "ML505_SMA_TX_n" LOC = "K2"; ## J30 13 | NET "ML505_SMA_RX_p" LOC = "K1"; ## J27 14 | NET "ML505_SMA_RX_n" LOC = "J1"; ## J28 15 | -------------------------------------------------------------------------------- /ucf/ML505/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 3 4 | ## ReferenceClock 5 | ## Location: J25, J26 6 | NET "ML505_SMA_RefClock_p" LOC = "H14"; ## J25 7 | NET "ML505_SMA_RefClock_n" LOC = "H15"; ## J26 8 | 9 | -------------------------------------------------------------------------------- /ucf/ML506/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ========================================================================== 2 | ## Xilinx User Constraint File (UCF) 3 | ## ========================================================================== 4 | ## Board: Xilinx - Virtex 5 ML506 5 | ## FPGA: Xilinx Virtex 5 6 | ## Device: XC5VSX50T 7 | ## Package: FF1136 8 | ## Speedgrade: -1 9 | ## ========================================================================== 10 | CONFIG PART = XC5VSX50T-FF1136-1; 11 | CONFIG STEPPING = "ES"; 12 | -------------------------------------------------------------------------------- /ucf/ML506/README.md: -------------------------------------------------------------------------------- 1 | The ML506 platform corresponds to the ML505 platform for all but the FPGA 2 | device. Refer to [ML505](../ML505/) for pinout information. 3 | -------------------------------------------------------------------------------- /ucf/MetaStability.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## MetaStability timing settings 3 | ## ============================================================================= 4 | NET "*_async" TIG; 5 | INST "*_meta*" TNM = "METASTABILITY_FFS"; 6 | TIMESPEC "TS_MetaStability" = FROM FFS TO "METASTABILITY_FFS" TIG; 7 | -------------------------------------------------------------------------------- /ucf/S3SK/buttons.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - user buttons (without reset): BTN2 - BTN0 7 | # 8 | NET "btn<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "btn<2>" LOC = "L13" ; 10 | NET "btn<1>" LOC = "M14" ; 11 | NET "btn<0>" LOC = "M13" ; 12 | -------------------------------------------------------------------------------- /ucf/S3SK/default.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - default board clock (100 MHz) 7 | # - user reset (BTN3) 8 | # 9 | NET "clk" TNM_NET = "clk"; 10 | TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %; 11 | 12 | NET "clk" LOC = "T9" | IOSTANDARD = LVCMOS33 ; 13 | NET "rst" LOC = "L14" | IOSTANDARD = LVCMOS33 ; 14 | -------------------------------------------------------------------------------- /ucf/S3SK/leds.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - LEDs 7 | # 8 | NET "leds<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "leds<0>" LOC = "K12" ; 10 | NET "leds<1>" LOC = "P14" ; 11 | NET "leds<2>" LOC = "L12" ; 12 | NET "leds<3>" LOC = "N14" ; 13 | NET "leds<4>" LOC = "P13" ; 14 | NET "leds<5>" LOC = "N12" ; 15 | NET "leds<6>" LOC = "P12" ; 16 | NET "leds<7>" LOC = "P11" ; 17 | -------------------------------------------------------------------------------- /ucf/S3SK/switches.ucf: -------------------------------------------------------------------------------- 1 | # 2 | # Xilinx User Constraint File (UCF) 3 | # 4 | # Board: Spartan-3 Starter Kit 5 | # 6 | # Contents: - slide switched 7 | # 8 | NET "sw<*>" IOSTANDARD = LVCMOS33 ; 9 | NET "sw<0>" LOC = "F12" ; 10 | NET "sw<1>" LOC = "G12" ; 11 | NET "sw<2>" LOC = "H14" ; 12 | NET "sw<3>" LOC = "H13" ; 13 | NET "sw<4>" LOC = "J14" ; 14 | NET "sw<5>" LOC = "J13" ; 15 | NET "sw<6>" LOC = "K14" ; 16 | NET "sw<7>" LOC = "K13" ; 17 | -------------------------------------------------------------------------------- /ucf/S3SK/uart.ucf: -------------------------------------------------------------------------------- 1 | NET "rx" LOC = "T13" | IOSTANDARD = LVCMOS33 ; 2 | NET "tx" LOC = "R13" | IOSTANDARD = LVCMOS33 ; 3 | -------------------------------------------------------------------------------- /ucf/S3SK/vga.ucf: -------------------------------------------------------------------------------- 1 | NET "VGA_HSync" LOC = "R9"; 2 | NET "VGA_VSync" LOC = "T10"; 3 | NET "VGA_R" LOC = "R12"; 4 | NET "VGA_G" LOC = "T12"; 5 | NET "VGA_B" LOC = "R11"; 6 | -------------------------------------------------------------------------------- /ucf/VC707/Bus.PMBus.ucf: -------------------------------------------------------------------------------- 1 | ## PowerManagementBus (PMBus) 2 | ## ============================================================================= 3 | ## Bank: 15 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: 6 | ## Vendor: 7 | ## Device: 8 | ##NET "VC707_PMBus_Clock" LOC = "AW37" | IOSTANDARD = LVCMOS18; ## 9 | ##NET "VC707_PMBus_Data" LOC = "AY39" | IOSTANDARD = LVCMOS18; ## 10 | ##NET "VC707_PMBus_Alert" LOC = "AV38" | IOSTANDARD = LVCMOS18; ## 11 | -------------------------------------------------------------------------------- /ucf/VC707/Clock.ProgUserClock.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## User Clock 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14 5 | ## VCCO: 1.8V (VCC1V8_FPGA) 6 | ## Location: U34 (SI570) 7 | ## Vendor: Silicon Labs 8 | ## Device: SI570BAB0000544DG 9 | ## Frequency: 10 - 810 MHz, 50ppm 10 | ## Default Freq: 156.250 MHz 11 | ## I²C-Address: 0x5D #$ (0111 010xb) 12 | NET "VC707_ProgUserClock_p" LOC = "AK34" | IOSTANDARD = LVDS; ## {IN} U34.4 13 | NET "VC707_ProgUserClock_n" LOC = "AL34" | IOSTANDARD = LVDS; ## {IN} U34.5 14 | NET "VC707_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; 15 | -------------------------------------------------------------------------------- /ucf/VC707/Clock.ProgUserClock.xdc: -------------------------------------------------------------------------------- 1 | ## 2 | ## User Clock 3 | ## ----------------------------------------------------------------------------- 4 | ## Bank: 14 5 | ## VCCO: 1.8V (VCC1V8_FPGA) 6 | ## Location: U34 (SI570) 7 | ## Vendor: Silicon Labs 8 | ## Device: SI570BAB0000544DG 9 | ## Frequency: 10 - 810 MHz, 50ppm 10 | ## Default Freq: 156.250 MHz 11 | ## I²C-Address: 0x5D #$ (0111 010xb) 12 | set_property PACKAGE_PIN AK34 [get_ports VC707_ProgUserClock_p] 13 | set_property PACKAGE_PIN AL34 [get_ports VC707_ProgUserClock_n] 14 | # set I/O standard 15 | set_property IOSTANDARD LVDS [get_ports -regexp {VC707_ProgUserClock_[p|n]}] 16 | -------------------------------------------------------------------------------- /ucf/VC707/FanControl.ucf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Fan Control 3 | ## ============================================================================= 4 | ## Bank: 15 5 | ## VCCO: 1,8V (VCC1V8_FPGA) 6 | ## Location: J48, Q1 7 | ## ----------------------------------------------------------------------------- 8 | NET "VC707_FanControl_PWM" LOC = "BA37"; ## Q1.Gate; external 1k pullup resistor 9 | NET "VC707_FanControl_Tacho" LOC = "BB37"; ## J48 - Pin 3; voltage limited by D2 (DDZ9678 - 1.8V zener-diode) 10 | NET "VC707_FanControl_*" IOSTANDARD = LVCMOS18; 11 | 12 | ## Ignore timings on async I/O pins 13 | NET "VC707_FanControl_*" TIG; 14 | -------------------------------------------------------------------------------- /ucf/VC707/Transceiver.SMA.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 113 4 | ## ReferenceClock (see Transceiver.SMA_RefClock.ucf) 5 | 6 | ## SMA LVDS signal-pairs 7 | ## -------------------------- 8 | ## Bank: 113 9 | ## Location: P27, J28, J29, J30 10 | NET "VC707_SMA_TX_p" LOC = "AP4"; ## J29 11 | NET "VC707_SMA_TX_n" LOC = "AP3"; ## J30 12 | NET "VC707_SMA_RX_p" LOC = "AN6"; ## J27 13 | NET "VC707_SMA_RX_n" LOC = "AN5"; ## J28 14 | -------------------------------------------------------------------------------- /ucf/VC707/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 113 4 | ## ReferenceClock 5 | ## Location: J25, J26 6 | NET "VC707_SMA_RefClock_p" LOC = "AK8"; ## J25 7 | NET "VC707_SMA_RefClock_n" LOC = "AK7"; ## J26 8 | 9 | -------------------------------------------------------------------------------- /ucf/VC707/USB_UART.ucf: -------------------------------------------------------------------------------- 1 | ## USB UART 2 | ## ============================================================================= 3 | ## Bank: 13 4 | ## VCCO: 1,8V (VCC1V8_FPGA) 5 | ## Location: U44 6 | ## Vendor: 7 | ## Device: 8 | NET "VC707_USB_UART_RX" LOC = "AU36"; ## 9 | NET "VC707_USB_UART_RTS_n" LOC = "AT32"; ## 10 | NET "VC707_USB_UART_TX" LOC = "AU33"; ## 11 | NET "VC707_USB_UART_CTS_n" LOC = "AR34"; ## 12 | NET "VC707_USB_UART_*" IOSTANDARD = LVCMOS18; 13 | 14 | ## Ignore timings on async I/O pins 15 | NET "VC707_USB_UART_*" TIG; 16 | -------------------------------------------------------------------------------- /ucf/XUPV5/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ========================================================================== 2 | ## Xilinx User Constraint File (UCF) 3 | ## ========================================================================== 4 | ## Board: Xilinx - Virtex 5 XUPV5 5 | ## FPGA: Xilinx Virtex 5 6 | ## Device: XC5VLX110T 7 | ## Package: FF1136 8 | ## Speedgrade: -1 9 | ## ========================================================================== 10 | CONFIG PART = XC5VLX110T-FFG1136-1; 11 | -------------------------------------------------------------------------------- /ucf/XUPV5/README.md: -------------------------------------------------------------------------------- 1 | The XUPV5 platform corresponds to the ML505 platform for all but the FPGA 2 | device. Refer to [ML505](../ML505/) for pinout information. 3 | -------------------------------------------------------------------------------- /ucf/Xilinx/Disable_DRC_Rules_GTHE3_Common.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTHE3_COMMON.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-1751} ] 3 | -------------------------------------------------------------------------------- /ucf/Xilinx/Disable_DRC_Rules_GTPE2_Channel.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTPE2_CHANNEL.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-49} ] 3 | -------------------------------------------------------------------------------- /ucf/Xilinx/Disable_DRC_Rules_GTXE2_Channel.xdc: -------------------------------------------------------------------------------- 1 | #Allow to drive GTXE2_CHANNEL.GTGREFCLK by global clock BUFG 2 | set_property IS_ENABLED 0 [ get_drc_checks {REQP-52} ] 3 | -------------------------------------------------------------------------------- /ucf/ZC706/Clock.ProgUserClock.ucf: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 10 4 | ## VCCO: 2.5V (VADJ_FPGA) 5 | ## Location: U37 (SI570) 6 | ## Vendor: Silicon Labs 7 | ## Device: SI570BAB0000544DG 8 | ## Frequency: 10 - 810 MHz, 50ppm 9 | ## Default Freq: 156.250 MHz 10 | ## I²C-Address: 11 | NET "ZC706_ProgUserClock_p" LOC = "AF14" | IOSTANDARD = LVDS_25; ## {IN} U37.4 12 | NET "ZC706_ProgUserClock_n" LOC = "AG14" | IOSTANDARD = LVDS_25; ## {IN} U37.5 13 | NET "ZC706_ProgUserClock_p" TNM_NET = "PIN_ProgUserClock"; 14 | -------------------------------------------------------------------------------- /ucf/ZC706/Clock.ProgUserClock.xdc: -------------------------------------------------------------------------------- 1 | ## User Clock 2 | ## ----------------------------------------------------------------------------- 3 | ## Bank: 10 4 | ## VCCO: 2.5V (VADJ_FPGA) 5 | ## Location: U37 (SI570) 6 | ## Vendor: Silicon Labs 7 | ## Device: SI570BAB0000544DG 8 | ## Frequency: 10 - 810 MHz, 50ppm 9 | ## Default Freq: 156.250 MHz 10 | ## I²C-Address: 11 | set_property PACKAGE_PIN AF14 [get_ports ZC706_ProgUserClock_p] 12 | set_property PACKAGE_PIN AG14 [get_ports ZC706_ProgUserClock_n] 13 | # set I/O standard 14 | set_property IOSTANDARD LVDS_25 [get_ports -regexp {ZC706_ProgUserClock_[p|n]}] 15 | -------------------------------------------------------------------------------- /ucf/ZC706/Clock.SMAClock.xdc: -------------------------------------------------------------------------------- 1 | ## Bank: 9 2 | ## VCCO: 2.5V (VADJ_FPGA) 3 | ## Location: J67, J68 4 | set_property PACKAGE_PIN AD18 [get_ports ZC706_SMAClock_p] 5 | set_property PACKAGE_PIN AD19 [get_ports ZC706_SMAClock_n] 6 | # set I/O standard 7 | set_property IOSTANDARD LVDS_25 [get_ports -regexp {ZC706_SMAClock_.}] 8 | -------------------------------------------------------------------------------- /ucf/ZC706/Transceiver.SMA_RefClock.ucf: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 111 4 | ## ReferenceClock MGT_REFCLK1 5 | ## Location: J36, J31 6 | NET "ZC706_SMA_RefClock_p" LOC = "W8"; ## J25 7 | NET "ZC706_SMA_RefClock_n" LOC = "W7"; ## J26 8 | -------------------------------------------------------------------------------- /ucf/ZC706/Transceiver.SMA_RefClock.xdc: -------------------------------------------------------------------------------- 1 | ## Transceiver - SMA interface 2 | ## ============================================================================= 3 | ## Bank: 111 4 | ## ReferenceClock MGT_REFCLK1 5 | ## Location: J36, J31 6 | set_property PACKAGE_PIN W8 [get_ports ZC706_SMA_RefClock_p] 7 | set_property PACKAGE_PIN W7 [get_ports ZC706_SMA_RefClock_n] 8 | -------------------------------------------------------------------------------- /ucf/ZedBoard/Default.ucf: -------------------------------------------------------------------------------- 1 | ## ============================================================================= 2 | ## Xilinx User Constraint File (UCF) 3 | ## ============================================================================= 4 | ## Board: Xilinx - Zynq 7020 ZedBoard 5 | ## FPGA: Xilinx Zynq 7000 6 | ## Device: XC7Z020 7 | ## Package: CLG484 8 | ## Speedgrade: -1 9 | ## 10 | ## ============================================================================= 11 | ## Miscellaneous 12 | ## ============================================================================= 13 | CONFIG PART = XC7Z020-CLG484-1; 14 | -------------------------------------------------------------------------------- /ucf/arith/arith_trng.xdc: -------------------------------------------------------------------------------- 1 | set_property -quiet ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical *osc*] 2 | -------------------------------------------------------------------------------- /ucf/misc/sync/sync_Bits_Xilinx.ucf: -------------------------------------------------------------------------------- 1 | # 2 | INST "*FF1_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; 3 | -------------------------------------------------------------------------------- /ucf/misc/sync/sync_Bits_Xilinx.xdc: -------------------------------------------------------------------------------- 1 | # This XDC file must be directly applied to all instances of sync_Bits_Xilinx. 2 | # To achieve this, set property SCOPED_TO_REF to sync_Bits_Xilinx within the Vivado project. 3 | # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. 4 | set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF2}] 5 | set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS}] 6 | set_false_path -from [all_clocks] -to [get_pins -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS/D}] 7 | -------------------------------------------------------------------------------- /ucf/misc/sync/sync_Reset_Xilinx.ucf: -------------------------------------------------------------------------------- 1 | # 2 | INST "*FF2_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; 3 | INST "*FF3_METASTABILITY_FFS" TNM = "METASTABILITY_FFS"; 4 | -------------------------------------------------------------------------------- /ucf/misc/sync/sync_Reset_Xilinx.xdc: -------------------------------------------------------------------------------- 1 | # This XDC file must be directly applied to all instances of sync_Reset_Xilinx. 2 | # To achieve this, set property SCOPED_TO_REF to sync_Reset_Xilinx within the Vivado project. 3 | # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. 4 | set_property ASYNC_REG true [get_cells {FF2_METASTABILITY_FFS FF3_METASTABILITY_FFS}] 5 | set_false_path -from [all_clocks] -to [get_pins FF2_METASTABILITY_FFS/PRE] 6 | set_false_path -from [all_clocks] -to [get_pins FF3_METASTABILITY_FFS/PRE] 7 | -------------------------------------------------------------------------------- /ucf/misc/sync/sync_Vector.xdc: -------------------------------------------------------------------------------- 1 | # This XDC file must be directly applied to all instances of sync_Vector. 2 | # To achieve this, set property SCOPED_TO_REF to sync_Vector within the Vivado project. 3 | # Load XDC file defining the clocks before this XDC file by using the property PROCESSING_ORDER. 4 | # Also load sync_Bits_Xilinx.xdc as described within that file. 5 | 6 | # set max delay between data register D0 and D4 to lower clock period 7 | set_max_delay -from [get_cells -regexp {D0_reg\[\d+\]}] -to [get_cells -regexp {D4_reg\[\d+\]}] -datapath_only [expr "min([get_property period [get_clocks -of_objects [get_pins {D0_reg[0]/C}]]], [get_property period [get_clocks -of_objects [get_pins {D4_reg[0]/C}]]])"] 8 | -------------------------------------------------------------------------------- /xst/README.md: -------------------------------------------------------------------------------- 1 | # Files required by Xilinx XST 2 | 3 | *No documentation available.* -------------------------------------------------------------------------------- /xst/default.filter: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/xst/default.filter -------------------------------------------------------------------------------- /xst/empty.xcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSI-EDA/PoC/894d3cd03c81f5b01121c4f878d1f9c91ff70105/xst/empty.xcf -------------------------------------------------------------------------------- /xst/xil/mig/mig_Atlys_1x128.xcf: -------------------------------------------------------------------------------- 1 | 2 | NET "c3_sys_clk" TNM_NET = "NET_mig_Atlys_1x128_c3_sys_clk"; 3 | TIMESPEC "TS_mig_Atlys_1x128_c3_sys_clk" = PERIOD "NET_mig_Atlys_1x128_c3_sys_clk" 100 MHz HIGH 50 %; ## 100 MHz board clock (50%/50% duty-cycle) 4 | --------------------------------------------------------------------------------