├── .coveragerc ├── .gitattributes ├── .github ├── ISSUE_TEMPLATE │ └── bug_report.md └── workflows │ ├── README.md │ ├── deploy.yml │ ├── regress.yml │ ├── sync.yml │ ├── sync_tag.yml │ └── version.yml ├── .gitignore ├── CNAME ├── CONTRIBUTING.md ├── LICENSE ├── MANIFEST.in ├── Makefile ├── OpenRAM_ICCAD_2016_paper.pdf ├── PORTING.md ├── README.md ├── VERSION ├── __init__.py ├── _config.yml ├── common.py ├── compiler ├── Makefile ├── base │ ├── __init__.py │ ├── channel_route.py │ ├── contact.py │ ├── delay_data.py │ ├── design.py │ ├── errors.py │ ├── geometry.py │ ├── hierarchy_design.py │ ├── hierarchy_layout.py │ ├── hierarchy_spice.py │ ├── lef.py │ ├── logical_effort.py │ ├── pin_layout.py │ ├── power_data.py │ ├── rom_verilog.py │ ├── route.py │ ├── timing_graph.py │ ├── utils.py │ ├── vector.py │ ├── vector3d.py │ ├── verilog.py │ ├── wire.py │ ├── wire_path.py │ └── wire_spice_model.py ├── characterizer │ ├── __init__.py │ ├── analytical_util.py │ ├── cacti.py │ ├── charutils.py │ ├── delay.py │ ├── elmore.py │ ├── fake_sram.py │ ├── functional.py │ ├── lib.py │ ├── linear_regression.py │ ├── measurements.py │ ├── model_check.py │ ├── neural_network.py │ ├── regression_model.py │ ├── setup_hold.py │ ├── simulation.py │ ├── stimuli.py │ └── trim_spice.py ├── datasheet │ ├── __init__.py │ ├── add_db.py │ ├── assets │ │ ├── OpenRAM_logo.png │ │ ├── datasheet.css │ │ └── vlsi_logo.png │ ├── datasheet.py │ ├── datasheet_gen.py │ └── table_gen.py ├── debug.py ├── drc │ ├── __init__.py │ ├── custom_cell_properties.py │ ├── custom_layer_properties.py │ ├── design_rules.py │ ├── drc_lut.py │ ├── drc_value.py │ └── module_type.py ├── gdsMill │ ├── README │ ├── exampleUserDir │ │ ├── arrayDemo.py │ │ ├── fillerDemo.py │ │ ├── gdsFiles │ │ │ └── testLayoutA.gds │ │ ├── gdsMill.cshrc │ │ └── quickStart.py │ ├── gdsMill.sh │ ├── gdsMill │ │ ├── __init__.py │ │ ├── gds2reader.py │ │ ├── gds2writer.py │ │ ├── gdsPrimitives.py │ │ ├── gdsStreamer.py │ │ ├── pdfLayout.py │ │ └── vlsiLayout.py │ ├── pyx │ │ ├── __init__.py │ │ ├── attr.py │ │ ├── bbox.py │ │ ├── bitmap.py │ │ ├── box.py │ │ ├── canvas.py │ │ ├── color.py │ │ ├── config.py │ │ ├── connector.py │ │ ├── deco.py │ │ ├── deformer.py │ │ ├── document.py │ │ ├── dvifile.py │ │ ├── epsfile.py │ │ ├── font │ │ │ ├── __init__.py │ │ │ ├── _t1code.c │ │ │ ├── afm.py │ │ │ ├── encoding.py │ │ │ ├── t1code.py │ │ │ └── t1font.py │ │ ├── graph │ │ │ ├── __init__.py │ │ │ ├── axis │ │ │ │ ├── __init__.py │ │ │ │ ├── axis.py │ │ │ │ ├── painter.py │ │ │ │ ├── parter.py │ │ │ │ ├── positioner.py │ │ │ │ ├── rater.py │ │ │ │ ├── texter.py │ │ │ │ ├── tick.py │ │ │ │ └── timeaxis.py │ │ │ ├── data.py │ │ │ ├── graph.py │ │ │ ├── key.py │ │ │ └── style.py │ │ ├── lfs │ │ │ ├── 10pt.lfs │ │ │ ├── 10ptex.lfs │ │ │ ├── 11pt.lfs │ │ │ ├── 11ptex.lfs │ │ │ ├── 12pt.lfs │ │ │ ├── 12ptex.lfs │ │ │ ├── createlfs.py │ │ │ ├── createlfs.tex │ │ │ ├── foils17pt.lfs │ │ │ ├── foils20pt.lfs │ │ │ ├── foils25pt.lfs │ │ │ └── foils30pt.lfs │ │ ├── mathutils.py │ │ ├── mesh.py │ │ ├── normpath.py │ │ ├── path.py │ │ ├── pattern.py │ │ ├── pdfwriter.py │ │ ├── pswriter.py │ │ ├── pykpathsea │ │ │ ├── __init__.py │ │ │ └── pykpathsea.c │ │ ├── siteconfig.py │ │ ├── style.py │ │ ├── text.py │ │ ├── trafo.py │ │ ├── type1font.py │ │ ├── unit.py │ │ └── version.py │ └── sram_examples │ │ ├── cell6tDemo.py │ │ ├── fillerDemo.py │ │ ├── gdsMill.sh │ │ ├── layoutB.gds │ │ ├── newcell.gds │ │ ├── newcell.py │ │ ├── printGDS.py │ │ ├── quickStart.py │ │ ├── sram_lib16.gds │ │ ├── sram_lib2.gds │ │ └── sys ├── gen_stimulus.py ├── globals.py ├── model_configs │ ├── shared_config.py │ ├── sram_10b_64w_4wpr_21las_1rw.py │ ├── sram_128b_1024_1rw.py │ ├── sram_12b_128w_4wpr_38las_1rw.py │ ├── sram_12b_16w_1wpr_1las_1rw.py │ ├── sram_12b_256w_16wpr_186las_1rw.py │ ├── sram_12b_256w_8wpr_17las_1rw.py │ ├── sram_14b_32w_2wpr_23las_1rw.py │ ├── sram_15b_512w_8wpr_85las_1rw.py │ ├── sram_16b_1024w_16wpr_40las_1rw.py │ ├── sram_17b_1024w_16wpr_86las_1rw.py │ ├── sram_17b_256w_16wpr_49las_1rw.py │ ├── sram_18b_128w_2wpr_7las_1rw.py │ ├── sram_18b_32w_1wpr_18las_1rw.py │ ├── sram_21b_1024w_4wpr_54las_1rw.py │ ├── sram_22b_512w_16wpr_249las_1rw.py │ ├── sram_23b_1024w_16wpr_118las_1rw.py │ ├── sram_26b_64w_4wpr_23las_1rw.py │ ├── sram_27b_1024w_4wpr_89las_1rw.py │ ├── sram_27b_256w_8wpr_191las_1rw.py │ ├── sram_27b_512w_4wpr_60las_1rw.py │ ├── sram_32b_1024_1rw.py │ ├── sram_32b_2048_1rw.py │ ├── sram_32b_256_1rw.py │ ├── sram_32b_32w_1wpr_31las_1rw.py │ ├── sram_32b_512_1rw.py │ ├── sram_4b_16w_1wpr_4las_1rw.py │ ├── sram_4b_32w_2wpr_5las_1rw.py │ ├── sram_4b_64w_4wpr_14las_1rw.py │ ├── sram_5b_256w_16wpr_75las_1rw.py │ ├── sram_64b_1024_1rw.py │ ├── sram_64b_512_1rw.py │ ├── sram_6b_16w_1wpr_1las_1rw.py │ ├── sram_7b_256w_4wpr_25las_1rw.py │ ├── sram_7b_64w_2wpr_10las_1rw.py │ ├── sram_8b_1024_1rw.py │ ├── sram_8b_256_1rw.py │ ├── sram_8b_256w_1wpr_1las_1rw.py │ ├── sram_8b_512_1rw.py │ ├── sram_9b_1024w_4wpr_3las_1rw.py │ ├── sram_9b_128w_1wpr_4las_1rw.py │ └── sram_9b_256w_4wpr_15las_1rw.py ├── model_data_util.py ├── modules │ ├── __init__.py │ ├── and2_dec.py │ ├── and3_dec.py │ ├── and4_dec.py │ ├── bank.py │ ├── bitcell_1port.py │ ├── bitcell_2port.py │ ├── bitcell_array.py │ ├── bitcell_base.py │ ├── bitcell_base_array.py │ ├── capped_replica_bitcell_array.py │ ├── col_cap_array.py │ ├── col_cap_bitcell_1port.py │ ├── col_cap_bitcell_2port.py │ ├── column_decoder.py │ ├── column_mux.py │ ├── column_mux_array.py │ ├── control_logic.py │ ├── control_logic_base.py │ ├── control_logic_delay.py │ ├── delay_chain.py │ ├── dff.py │ ├── dff_array.py │ ├── dff_buf.py │ ├── dff_buf_array.py │ ├── dff_inv.py │ ├── dff_inv_array.py │ ├── dummy_array.py │ ├── dummy_bitcell_1port.py │ ├── dummy_bitcell_2port.py │ ├── dummy_pbitcell.py │ ├── global_bitcell_array.py │ ├── hierarchical_decoder.py │ ├── hierarchical_predecode.py │ ├── hierarchical_predecode2x4.py │ ├── hierarchical_predecode3x8.py │ ├── hierarchical_predecode4x16.py │ ├── internal_base.py │ ├── inv_dec.py │ ├── local_bitcell_array.py │ ├── multi_delay_chain.py │ ├── multibank.py │ ├── nand2_dec.py │ ├── nand3_dec.py │ ├── nand4_dec.py │ ├── orig_bitcell_array.py │ ├── pand2.py │ ├── pand3.py │ ├── pand4.py │ ├── pbitcell.py │ ├── pbuf.py │ ├── pbuf_dec.py │ ├── pdriver.py │ ├── pgate.py │ ├── pinv.py │ ├── pinv_dec.py │ ├── pinvbuf.py │ ├── pnand2.py │ ├── pnand3.py │ ├── pnand4.py │ ├── pnor2.py │ ├── port_address.py │ ├── port_data.py │ ├── precharge.py │ ├── precharge_array.py │ ├── ptristate_inv.py │ ├── ptx.py │ ├── pwrite_driver.py │ ├── replica_bitcell_1port.py │ ├── replica_bitcell_2port.py │ ├── replica_bitcell_array.py │ ├── replica_column.py │ ├── replica_pbitcell.py │ ├── rom_address_control_array.py │ ├── rom_address_control_buf.py │ ├── rom_bank.py │ ├── rom_base_array.py │ ├── rom_base_cell.py │ ├── rom_column_mux.py │ ├── rom_column_mux_array.py │ ├── rom_control_logic.py │ ├── rom_decoder.py │ ├── rom_poly_tap.py │ ├── rom_precharge_array.py │ ├── rom_precharge_cell.py │ ├── rom_wordline_driver_array.py │ ├── row_cap_array.py │ ├── row_cap_bitcell_1port.py │ ├── row_cap_bitcell_2port.py │ ├── sense_amp.py │ ├── sense_amp_array.py │ ├── sram_1bank.py │ ├── sram_multibank.py │ ├── sram_multibank_template.v │ ├── template.py │ ├── tri_gate.py │ ├── tri_gate_array.py │ ├── wordline_buffer_array.py │ ├── wordline_driver.py │ ├── wordline_driver_array.py │ ├── write_driver.py │ ├── write_driver_array.py │ └── write_mask_and_array.py ├── options.py ├── rom.py ├── rom_config.py ├── router │ ├── __init__.py │ ├── bbox.py │ ├── bbox_node.py │ ├── graph.py │ ├── graph_node.py │ ├── graph_probe.py │ ├── graph_shape.py │ ├── graph_utils.py │ ├── router.py │ ├── router_tech.py │ ├── signal_escape_router.py │ └── supply_router.py ├── run_profile.sh ├── sram.py ├── sram_config.py ├── sram_factory.py ├── tests │ ├── 00_code_format_check_test.py │ ├── 01_library_test.py │ ├── 03_contact_test.py │ ├── 03_path_test.py │ ├── 03_ptx_1finger_nmos_test.py │ ├── 03_ptx_1finger_pmos_test.py │ ├── 03_ptx_3finger_nmos_test.py │ ├── 03_ptx_3finger_pmos_test.py │ ├── 03_ptx_4finger_nmos_test.py │ ├── 03_ptx_4finger_pmos_test.py │ ├── 03_ptx_no_contacts_test.py │ ├── 03_wire_test.py │ ├── 04_and2_dec_test.py │ ├── 04_and3_dec_test.py │ ├── 04_and4_dec_test.py │ ├── 04_column_mux_1rw_1r_test.py │ ├── 04_column_mux_pbitcell_test.py │ ├── 04_column_mux_test.py │ ├── 04_dff_buf_test.py │ ├── 04_dummy_pbitcell_1rw1r1w_test.py │ ├── 04_dummy_pbitcell_1rw_test.py │ ├── 04_pand2_test.py │ ├── 04_pand3_test.py │ ├── 04_pand4_test.py │ ├── 04_pbitcell_test.py │ ├── 04_pbuf_dec_8x_test.py │ ├── 04_pbuf_test.py │ ├── 04_pdriver_test.py │ ├── 04_pinv_100x_test.py │ ├── 04_pinv_10x_test.py │ ├── 04_pinv_1x_beta_test.py │ ├── 04_pinv_1x_test.py │ ├── 04_pinv_2x_test.py │ ├── 04_pinv_dec_1x_test.py │ ├── 04_pinvbuf_test.py │ ├── 04_pnand2_test.py │ ├── 04_pnand3_test.py │ ├── 04_pnand4_test.py │ ├── 04_pnor2_test.py │ ├── 04_precharge_1rw_1r_test.py │ ├── 04_precharge_pbitcell_test.py │ ├── 04_precharge_test.py │ ├── 04_pwrite_driver_test.py │ ├── 04_replica_pbitcell_1rw1r1w_test.py │ ├── 04_replica_pbitcell_1rw_test.py │ ├── 04_rom_address_control_buf_test.py │ ├── 04_rom_precharge_test.py │ ├── 04_wordline_driver_test.py │ ├── 05_bitcell_array_1rw_1r_test.py │ ├── 05_bitcell_array_test.py │ ├── 05_dummy_array_test.py │ ├── 05_pbitcell_array_test.py │ ├── 05_rom_array_test.py │ ├── 06_column_decoder_16row_test.py │ ├── 06_hierarchical_decoder_132row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_132row_test.py │ ├── 06_hierarchical_decoder_16row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_16row_test.py │ ├── 06_hierarchical_decoder_17row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_17row_test.py │ ├── 06_hierarchical_decoder_32row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_32row_test.py │ ├── 06_hierarchical_decoder_4096row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_4096row_test.py │ ├── 06_hierarchical_decoder_512row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_512row_test.py │ ├── 06_hierarchical_decoder_64row_1rw_1r_test.py │ ├── 06_hierarchical_decoder_64row_test.py │ ├── 06_hierarchical_decoder_pbitcell_test.py │ ├── 06_hierarchical_predecode2x4_1rw_1r_test.py │ ├── 06_hierarchical_predecode2x4_pbitcell_test.py │ ├── 06_hierarchical_predecode2x4_test.py │ ├── 06_hierarchical_predecode3x8_1rw_1r_test.py │ ├── 06_hierarchical_predecode3x8_pbitcell_test.py │ ├── 06_hierarchical_predecode3x8_test.py │ ├── 06_hierarchical_predecode4x16_test.py │ ├── 06_rom_decoder_test.py │ ├── 07_column_mux_array_16mux_1rw_1r_test.py │ ├── 07_column_mux_array_16mux_test.py │ ├── 07_column_mux_array_2mux_1rw_1r_test.py │ ├── 07_column_mux_array_2mux_test.py │ ├── 07_column_mux_array_4mux_1rw_1r_test.py │ ├── 07_column_mux_array_4mux_test.py │ ├── 07_column_mux_array_8mux_1rw_1r_test.py │ ├── 07_column_mux_array_8mux_test.py │ ├── 07_column_mux_array_pbitcell_test.py │ ├── 07_rom_column_mux_array_test.py │ ├── 08_precharge_array_1rw_1r_test.py │ ├── 08_precharge_array_test.py │ ├── 08_rom_decoder_buffer_array_test.py │ ├── 08_rom_precharge_array_test.py │ ├── 08_wordline_buffer_array_test.py │ ├── 08_wordline_driver_array_1rw_1r_test.py │ ├── 08_wordline_driver_array_pbitcell_test.py │ ├── 08_wordline_driver_array_test.py │ ├── 09_sense_amp_array_1rw_1r_test.py │ ├── 09_sense_amp_array_pbitcell_test.py │ ├── 09_sense_amp_array_spare_cols_test.py │ ├── 09_sense_amp_array_test.py │ ├── 10_rom_wordline_driver_array_test.py │ ├── 10_write_driver_array_1rw_1r_test.py │ ├── 10_write_driver_array_pbitcell_test.py │ ├── 10_write_driver_array_spare_cols_test.py │ ├── 10_write_driver_array_test.py │ ├── 10_write_driver_array_wmask_pbitcell_test.py │ ├── 10_write_driver_array_wmask_spare_cols_test.py │ ├── 10_write_driver_array_wmask_test.py │ ├── 10_write_mask_and_array_1rw_1r_test.py │ ├── 10_write_mask_and_array_pbitcell_test.py │ ├── 10_write_mask_and_array_test.py │ ├── 11_dff_array_test.py │ ├── 11_dff_buf_array_test.py │ ├── 12_tri_gate_array_test.py │ ├── 13_delay_chain_test.py │ ├── 14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py │ ├── 14_capped_replica_bitcell_array_dummies_1rw_1r_test.py │ ├── 14_capped_replica_bitcell_array_dummies_1rw_test.py │ ├── 14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py │ ├── 14_capped_replica_bitcell_array_leftrbl_1rw_test.py │ ├── 14_capped_replica_bitcell_array_norbl_1rw_1r_test.py │ ├── 14_capped_replica_bitcell_array_norbl_1rw_test.py │ ├── 14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py │ ├── 14_replica_bitcell_array_bothrbl_1rw_1r_test.py │ ├── 14_replica_bitcell_array_dummies_1rw_1r_test.py │ ├── 14_replica_bitcell_array_dummies_1rw_test.py │ ├── 14_replica_bitcell_array_leftrbl_1rw_1r_test.py │ ├── 14_replica_bitcell_array_leftrbl_1rw_test.py │ ├── 14_replica_bitcell_array_norbl_1rw_1r_test.py │ ├── 14_replica_bitcell_array_norbl_1rw_test.py │ ├── 14_replica_bitcell_array_rightrbl_1rw_1r_test.py │ ├── 14_replica_column_1rw_1r_test.py │ ├── 14_replica_column_1rw_test.py │ ├── 14_replica_pbitcell_1rw1r_array_test.py │ ├── 14_replica_pbitcell_1rw_array_test.py │ ├── 15_global_bitcell_array_norbl_1rw_1r_test.py │ ├── 15_global_bitcell_array_norbl_1rw_test.py │ ├── 15_global_bitcell_array_rbl_1rw_1r_test.py │ ├── 15_global_bitcell_array_rbl_1rw_test.py │ ├── 15_local_bitcell_array_bothrbl_1rw_1r_test.py │ ├── 15_local_bitcell_array_dummies_1rw_1r_test.py │ ├── 15_local_bitcell_array_dummies_1rw_test.py │ ├── 15_local_bitcell_array_leftrbl_1rw_1r_test.py │ ├── 15_local_bitcell_array_leftrbl_1rw_test.py │ ├── 15_local_bitcell_array_norbl_1rw_1r_test.py │ ├── 15_local_bitcell_array_norbl_1rw_test.py │ ├── 15_local_bitcell_array_rightrbl_1rw_1r_test.py │ ├── 16_control_logic_delay_multiport_test.py │ ├── 16_control_logic_delay_r_test.py │ ├── 16_control_logic_delay_rw_test.py │ ├── 16_control_logic_delay_w_test.py │ ├── 16_control_logic_multiport_test.py │ ├── 16_control_logic_r_test.py │ ├── 16_control_logic_rw_test.py │ ├── 16_control_logic_w_test.py │ ├── 16_rom_control_logic_test.py │ ├── 18_port_address_16rows_1rw_1r_test.py │ ├── 18_port_address_16rows_test.py │ ├── 18_port_address_256rows_1rw_1r_test.py │ ├── 18_port_address_512rows_test.py │ ├── 18_port_data_16mux_1rw_1r_test.py │ ├── 18_port_data_16mux_test.py │ ├── 18_port_data_2mux_1rw_1r_test.py │ ├── 18_port_data_2mux_test.py │ ├── 18_port_data_4mux_1rw_1r_test.py │ ├── 18_port_data_4mux_test.py │ ├── 18_port_data_8mux_1rw_1r_test.py │ ├── 18_port_data_8mux_test.py │ ├── 18_port_data_nomux_1rw_1r_test.py │ ├── 18_port_data_nomux_test.py │ ├── 18_port_data_spare_cols_test.py │ ├── 18_port_data_wmask_1rw_1r_test.py │ ├── 18_port_data_wmask_test.py │ ├── 19_multi_bank_test.py │ ├── 19_pmulti_bank_test.py │ ├── 19_psingle_bank_test.py │ ├── 19_rom_bank_test.py │ ├── 19_single_bank_16mux_1rw_1r_test.py │ ├── 19_single_bank_16mux_test.py │ ├── 19_single_bank_1w_1r_test.py │ ├── 19_single_bank_2mux_1rw_1r_test.py │ ├── 19_single_bank_2mux_test.py │ ├── 19_single_bank_4mux_1rw_1r_test.py │ ├── 19_single_bank_4mux_test.py │ ├── 19_single_bank_8mux_1rw_1r_test.py │ ├── 19_single_bank_8mux_test.py │ ├── 19_single_bank_global_bitline_test.py │ ├── 19_single_bank_nomux_1rw_1r_test.py │ ├── 19_single_bank_nomux_norbl_1rw_1r_test.py │ ├── 19_single_bank_nomux_norbl_test.py │ ├── 19_single_bank_nomux_test.py │ ├── 19_single_bank_spare_cols_test.py │ ├── 19_single_bank_wmask_1rw_1r_test.py │ ├── 19_single_bank_wmask_test.py │ ├── 20_psram_1bank_2mux_1rw_1w_test.py │ ├── 20_psram_1bank_2mux_1rw_1w_wmask_test.py │ ├── 20_psram_1bank_2mux_1w_1r_test.py │ ├── 20_psram_1bank_2mux_test.py │ ├── 20_psram_1bank_4mux_1rw_1r_test.py │ ├── 20_sram_1bank_16mux_1rw_1r_test.py │ ├── 20_sram_1bank_16mux_test.py │ ├── 20_sram_1bank_2mux_1rw_1r_spare_cols_test.py │ ├── 20_sram_1bank_2mux_1rw_1r_test.py │ ├── 20_sram_1bank_2mux_1w_1r_spare_cols_test.py │ ├── 20_sram_1bank_2mux_1w_1r_test.py │ ├── 20_sram_1bank_2mux_global_test.py │ ├── 20_sram_1bank_2mux_test.py │ ├── 20_sram_1bank_2mux_wmask_spare_cols_test.py │ ├── 20_sram_1bank_2mux_wmask_test.py │ ├── 20_sram_1bank_32b_1024_wmask_test.py │ ├── 20_sram_1bank_4mux_1rw_1r_test.py │ ├── 20_sram_1bank_4mux_test.py │ ├── 20_sram_1bank_8mux_1rw_1r_test.py │ ├── 20_sram_1bank_8mux_test.py │ ├── 20_sram_1bank_nomux_1rw_1r_spare_cols_test.py │ ├── 20_sram_1bank_nomux_1rw_1r_test.py │ ├── 20_sram_1bank_nomux_norbl_1rw_1r_test.py │ ├── 20_sram_1bank_nomux_norbl_test.py │ ├── 20_sram_1bank_nomux_spare_cols_test.py │ ├── 20_sram_1bank_nomux_test.py │ ├── 20_sram_1bank_nomux_wmask_sparecols_test.py │ ├── 20_sram_1bank_nomux_wmask_test.py │ ├── 20_sram_1bank_ring_test.py │ ├── 20_sram_2bank_test.py │ ├── 21_hspice_delay_test.py │ ├── 21_hspice_setuphold_test.py │ ├── 21_model_delay_test.py │ ├── 21_ngspice_delay_extra_rows_test.py │ ├── 21_ngspice_delay_global_test.py │ ├── 21_ngspice_delay_test.py │ ├── 21_ngspice_setuphold_test.py │ ├── 21_regression_delay_test.py │ ├── 21_xyce_delay_test.py │ ├── 21_xyce_setuphold_test.py │ ├── 22_psram_1bank_2mux_func_test.py │ ├── 22_psram_1bank_4mux_func_test.py │ ├── 22_psram_1bank_8mux_func_test.py │ ├── 22_psram_1bank_nomux_func_test.py │ ├── 22_sram_1bank_2mux_func_test.py │ ├── 22_sram_1bank_2mux_global_func_test.py │ ├── 22_sram_1bank_2mux_sparecols_func_test.py │ ├── 22_sram_1bank_4mux_func_test.py │ ├── 22_sram_1bank_8mux_func_test.py │ ├── 22_sram_1bank_nomux_1rw_1r_func_test.py │ ├── 22_sram_1bank_nomux_func_test.py │ ├── 22_sram_1bank_nomux_sparecols_func_test.py │ ├── 22_sram_1bank_wmask_1rw_1r_func_test.py │ ├── 22_sram_wmask_func_test.py │ ├── 23_lib_sram_linear_regression_test.py │ ├── 23_lib_sram_model_corners_test.py │ ├── 23_lib_sram_model_test.py │ ├── 23_lib_sram_prune_test.py │ ├── 23_lib_sram_test.py │ ├── 24_lef_sram_test.py │ ├── 25_verilog_multibank_test.py │ ├── 25_verilog_sram_test.py │ ├── 26_hspice_pex_pinv_test.py │ ├── 26_ngspice_pex_pinv_test.py │ ├── 26_sram_pex_test.py │ ├── 30_openram_back_end_library_test.py │ ├── 30_openram_back_end_test.py │ ├── 30_openram_front_end_library_test.py │ ├── 30_openram_front_end_test.py │ ├── 30_openram_sram_char_test.py │ ├── 30_openram_sram_func_test.py │ ├── 50_riscv_1k_1rw1r_func_test.py │ ├── 50_riscv_1k_1rw_func_test.py │ ├── 50_riscv_1rw1r_func_test.py │ ├── 50_riscv_1rw1r_phys_test.py │ ├── 50_riscv_1rw_func_test.py │ ├── 50_riscv_1rw_phys_test.py │ ├── 50_riscv_2k_1rw1r_func_test.py │ ├── 50_riscv_2k_1rw_func_test.py │ ├── 50_riscv_4k_1rw1r_func_test.py │ ├── 50_riscv_4k_1rw_func_test.py │ ├── 50_riscv_512b_1rw1r_func_test.py │ ├── 50_riscv_512b_1rw_func_test.py │ ├── 50_riscv_8k_1rw1r_func_test.py │ ├── 50_riscv_8k_1rw_func_test.py │ ├── Makefile │ ├── configs │ │ ├── config.py │ │ ├── config_back_end.py │ │ ├── config_front_end.py │ │ ├── config_mem_char_func.py │ │ └── rom_data_64B │ ├── golden │ │ ├── sram_2_16_1_freepdk45.lef │ │ ├── sram_2_16_1_freepdk45.sp │ │ ├── sram_2_16_1_freepdk45.v │ │ ├── sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib │ │ ├── sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib │ │ ├── sram_2_16_1_freepdk45_TT_1p0V_25C.lib │ │ ├── sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib │ │ ├── sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib │ │ ├── sram_2_16_1_scn4m_subm.lef │ │ ├── sram_2_16_1_scn4m_subm.sp │ │ ├── sram_2_16_1_scn4m_subm.v │ │ ├── sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib │ │ ├── sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib │ │ ├── sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib │ │ ├── sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib │ │ ├── sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib │ │ ├── sram_2_16_1_sky130.sp │ │ ├── sram_2_16_2_freepdk45.v │ │ ├── sram_2_16_2_freepdk45_top.v │ │ ├── sram_2_16_2_scn4m_subm.v │ │ └── sram_2_16_2_scn4m_subm_top.v │ ├── sp_files │ │ ├── sram_2_16_1_freepdk45.sp │ │ ├── sram_2_16_1_scn4m_subm.sp │ │ └── sram_2_16_1_sky130.sp │ ├── sram_1rw_1r_tb.v │ ├── sram_1rw_tb.v │ ├── sram_1rw_wmask_tb.v │ └── testutils.py ├── verify │ ├── __init__.py │ ├── assura.py │ ├── calibre.py │ ├── klayout.py │ ├── magic.py │ ├── none.py │ └── run_script.py └── view_profile.py ├── docker ├── Dockerfile ├── Makefile ├── README.md ├── mrg.patch └── set-paths.sh ├── docs ├── assets │ └── images │ │ ├── architecture │ │ └── sram_architecture.png │ │ ├── base_data_structures │ │ ├── layout_1.png │ │ ├── layout_2.png │ │ ├── parameterized_cell.png │ │ └── transistor.png │ │ ├── basic_usage │ │ ├── datasheet_1.png │ │ ├── datasheet_2.png │ │ └── datasheet_3.png │ │ ├── bitcells │ │ ├── 10t.png │ │ ├── 6t.png │ │ ├── dff.png │ │ ├── dff_reference.png │ │ ├── multiport_bitcells.png │ │ ├── parameterized_1.png │ │ ├── parameterized_2.png │ │ ├── thin_dual.png │ │ ├── thin_dual_straps.png │ │ ├── thin_single.png │ │ └── thin_single_straps.png │ │ ├── characterization │ │ ├── buffer_1.png │ │ ├── buffer_2.png │ │ ├── buffer_3.png │ │ ├── exclusion.png │ │ ├── graph_with_exclusion.png │ │ └── graph_without_exclusion.png │ │ ├── control_logic │ │ ├── internal_signals_read.png │ │ ├── internal_signals_write.png │ │ ├── read_simulation.png │ │ ├── read_timing.png │ │ ├── replica_array.png │ │ ├── write_simulation.png │ │ └── write_timing.png │ │ ├── design_modules │ │ ├── 1d_array.png │ │ ├── 2d_array_horizontal.png │ │ ├── 2d_array_vertical.png │ │ ├── address_decoder.png │ │ ├── bank.png │ │ ├── bitcell_array.png │ │ ├── delay_line.png │ │ └── replica_bitcell_array.png │ │ ├── logos │ │ ├── okstate.png │ │ └── vlsida.png │ │ ├── results │ │ ├── generated_layout.jpg │ │ ├── small_layouts_1.png │ │ ├── small_layouts_2.png │ │ ├── sram_area.png │ │ └── timing_and_density_results.png │ │ └── routing │ │ ├── channel_router_book.png │ │ ├── channel_router_connection.png │ │ └── power_routing.png └── source │ ├── FAQ.md │ ├── OpenRAM.ipynb │ ├── architecture.md │ ├── base_data_structures.md │ ├── basic_rom_usage.md │ ├── basic_setup.md │ ├── basic_usage.md │ ├── bitcells.md │ ├── characterization.md │ ├── control_logic.md │ ├── debug.md │ ├── design_modules.md │ ├── index.md │ ├── library_cells.md │ ├── openram_dev_notes.md │ ├── python_library.md │ ├── results.md │ ├── routing.md │ ├── technology_setup.md │ └── tutorials.md ├── images ├── OpenRAM_logo_yellow_transparent.png ├── OpenRAM_logo_yellow_transparent.svg ├── Python-3.5-green.svg ├── SCMOS_16kb_sram.jpg └── license_badge.svg ├── install_conda.sh ├── macros ├── Makefile ├── rom_configs │ ├── example_1kbyte.bin │ ├── example_1kbyte.hex │ ├── gf180mcu_rom_1kbyte.py │ ├── gf180mcu_rom_common.py │ ├── sky130_rom_1kbyte.py │ └── sky130_rom_common.py └── sram_configs │ ├── example_config_1rw_1r_scn4m_subm.py │ ├── example_config_1rw_1w_scn4m_subm.py │ ├── example_config_1rw_2mux_scn4m_subm.py │ ├── example_config_1w_1r_scn4m_subm.py │ ├── example_config_2rw_scn4m_subm.py │ ├── example_config_big_scn4m_subm.py │ ├── example_config_freepdk45.py │ ├── example_config_giant_scn4m_subm.py │ ├── example_config_medium_scn4m_subm.py │ ├── example_config_scn4m_subm.py │ ├── freepdk45_sram_1rw1r_32x2048_8.py │ ├── scn4m_subm_sram_16kbyte_1rw1r_32x4096_8.py │ ├── scn4m_subm_sram_1kbyte_1rw1r_32x256_8.py │ ├── scn4m_subm_sram_2kbyte_1rw1r_32x512_8.py │ ├── scn4m_subm_sram_32kbyte_1rw1r_2x32x4096_8.py │ ├── scn4m_subm_sram_4kbyte_1rw1r_32x1024_8.py │ ├── scn4m_subm_sram_8kbyte_1rw1r_32x2048_8.py │ ├── sky130_sram_1kbyte_1r1w_8x1024_8.py │ ├── sky130_sram_1kbyte_1rw1r_32x256_8.py │ ├── sky130_sram_1kbyte_1rw1r_8x1024_8.py │ ├── sky130_sram_1kbyte_1rw_32x256_8.py │ ├── sky130_sram_1rw1r_tiny.py │ ├── sky130_sram_1rw_tiny.py │ ├── sky130_sram_2kbyte_1rw1r_32x512_8.py │ ├── sky130_sram_2kbyte_1rw_32x512_8.py │ ├── sky130_sram_4kbyte_1rw1r_32x1024_8.py │ ├── sky130_sram_4kbyte_1rw_32x1024_8.py │ ├── sky130_sram_4kbyte_1rw_64x512_8.py │ └── sky130_sram_common.py ├── openram.mk ├── pyproject.toml ├── requirements.txt ├── rom_compiler.py ├── setpaths.sh ├── setup.py ├── sram_char.py ├── sram_compiler.py ├── sram_func.py └── technology ├── freepdk45 ├── __init__.py ├── gds_lib │ ├── cell_1rw.gds │ ├── cell_2rw.gds │ ├── dff.gds │ ├── dummy_cell_1rw.gds │ ├── dummy_cell_2rw.gds │ ├── replica_cell_1rw.gds │ ├── replica_cell_2rw.gds │ ├── sense_amp.gds │ ├── tri_gate.gds │ └── write_driver.gds ├── layers.map ├── models │ ├── APACHE-LICENSE-2.0.txt │ ├── hspice_ff.include │ ├── hspice_nom.include │ ├── hspice_ss.include │ └── tran_models │ │ ├── models_ff │ │ ├── NMOS_THKOX.inc │ │ ├── NMOS_VTG.inc │ │ ├── NMOS_VTH.inc │ │ ├── NMOS_VTL.inc │ │ ├── PMOS_THKOX.inc │ │ ├── PMOS_VTG.inc │ │ ├── PMOS_VTH.inc │ │ └── PMOS_VTL.inc │ │ ├── models_nom │ │ ├── NMOS_THKOX.inc │ │ ├── NMOS_VTG.inc │ │ ├── NMOS_VTH.inc │ │ ├── NMOS_VTL.inc │ │ ├── PMOS_THKOX.inc │ │ ├── PMOS_VTG.inc │ │ ├── PMOS_VTH.inc │ │ └── PMOS_VTL.inc │ │ └── models_ss │ │ ├── NMOS_THKOX.inc │ │ ├── NMOS_VTG.inc │ │ ├── NMOS_VTH.inc │ │ ├── NMOS_VTL.inc │ │ ├── PMOS_THKOX.inc │ │ ├── PMOS_VTG.inc │ │ ├── PMOS_VTH.inc │ │ └── PMOS_VTL.inc ├── sim_data │ ├── leakage_data.csv │ └── sim_data.csv ├── sp_lib │ ├── cell_1rw.sp │ ├── cell_2rw.sp │ ├── dff.sp │ ├── dummy_cell_1rw.sp │ ├── dummy_cell_2rw.sp │ ├── replica_cell_1rw.sp │ ├── replica_cell_2rw.sp │ ├── sense_amp.sp │ ├── tri_gate.sp │ └── write_driver.sp ├── tech │ ├── __init__.py │ ├── freepdk45.lydrc │ ├── freepdk45.lylvs │ ├── freepdk45.lyp │ ├── freepdk45.lyt │ ├── scn4m_subm.lyp │ ├── scn4m_subm.lyt │ └── tech.py └── tf │ ├── APACHE-LICENSE-2.0.txt │ ├── FreePDK45.tf │ ├── README.txt │ ├── SVRF_EULA_06Feb09.txt │ ├── display.drf │ └── layers.map ├── gf180mcu ├── __init__.py ├── custom │ └── gf180_bitcell.py ├── gds_lib │ ├── cell1rw.gds │ └── gf180mcu_3v3__nand2_1_dec.gds ├── mag_lib │ ├── .magicrc │ └── gf180mcu_3v3__nand2_1_dec.mag ├── sp_lib │ ├── cell1rw.sp │ └── gf180mcu_3v3__nand2_1_dec.sp └── tech │ ├── .magicrc │ ├── __init__.py │ ├── gf180mcu.lym │ ├── gf180mcu.lyp │ ├── gf180mcu.lyt │ └── tech.py ├── scn3me_subm ├── __init__.py ├── gds_lib │ ├── cell_1rw_1r.gds │ ├── cell_1w_1r.gds │ ├── cell_6t.gds │ ├── dff.gds │ ├── ms_flop.gds │ ├── replica_cell_1rw_1r.gds │ ├── replica_cell_1w_1r.gds │ ├── replica_cell_6t.gds │ ├── sense_amp.gds │ ├── tri_gate.gds │ └── write_driver.gds ├── mag_lib │ ├── cell_1rw_1r.mag │ ├── cell_1w_1r.mag │ ├── cell_6t.mag │ ├── convertall.sh │ ├── dff.mag │ ├── ms_flop.mag │ ├── replica_cell_1rw_1r.mag │ ├── replica_cell_1w_1r.mag │ ├── replica_cell_6t.mag │ ├── sense_amp.mag │ ├── tri_gate.mag │ └── write_driver.mag ├── models │ ├── ff │ │ ├── nmos.sp │ │ └── pmos.sp │ ├── nom │ │ ├── nmos.sp │ │ └── pmos.sp │ └── ss │ │ ├── nmos.sp │ │ └── pmos.sp ├── sp_lib │ ├── cell_1rw_1r.sp │ ├── cell_1w_1r.sp │ ├── cell_6t.sp │ ├── dff.sp │ ├── incorrect │ │ ├── cell_1rw_1r.sp │ │ ├── cell_1w_1r.sp │ │ ├── replica_cell_1rw_1r.sp │ │ └── replica_cell_1w_1r.sp │ ├── ms_flop.sp │ ├── replica_cell_1rw_1r.sp │ ├── replica_cell_1w_1r.sp │ ├── replica_cell_6t.sp │ ├── sense_amp.sp │ ├── tri_gate.sp │ └── write_driver.sp ├── sue_lib │ ├── cell_6t.sue │ ├── ms_flop.sue │ ├── replica_cell_6t.sue │ ├── sense_amp.sue │ ├── tri_gate.sue │ └── write_driver.sue ├── tech │ ├── .magicrc │ ├── README │ ├── SCN3ME_SUBM.30.tech │ ├── __init__.py │ ├── calibreDRC_scn3me_subm.rul │ ├── calibreLVS_scn3me_subm.rul │ ├── setup.tcl │ └── tech.py └── tf │ ├── README │ ├── display.drf │ ├── glade_scn3me_subm.py │ ├── layers.map │ └── mosis.tf ├── scn4m_subm ├── __init__.py ├── gds_lib │ ├── cell_1rw.gds │ ├── cell_2rw.gds │ ├── dff.gds │ ├── dummy_cell_1rw.gds │ ├── dummy_cell_2rw.gds │ ├── replica_cell_1rw.gds │ ├── replica_cell_2rw.gds │ ├── sense_amp.gds │ ├── tri_gate.gds │ └── write_driver.gds ├── mag_lib │ ├── cell_1rw.mag │ ├── cell_2rw.mag │ ├── convertall.sh │ ├── dff.mag │ ├── dummy_cell_1rw.mag │ ├── dummy_cell_2rw.mag │ ├── replica_cell_1rw.mag │ ├── replica_cell_2rw.mag │ ├── sense_amp.mag │ ├── tri_gate.mag │ └── write_driver.mag ├── models │ ├── ff │ │ ├── nmos.sp │ │ └── pmos.sp │ ├── nom │ │ ├── nmos.sp │ │ └── pmos.sp │ └── ss │ │ ├── nmos.sp │ │ └── pmos.sp ├── sim_data │ └── sim_data.csv ├── sp_lib │ ├── cell_1rw.sp │ ├── cell_2rw.sp │ ├── cell_6t.st0 │ ├── dff.sp │ ├── dummy_cell_1rw.sp │ ├── dummy_cell_2rw.sp │ ├── replica_cell_1rw.sp │ ├── replica_cell_2rw.sp │ ├── sense_amp.sp │ ├── tri_gate.sp │ └── write_driver.sp ├── tech │ ├── .magicrc │ ├── README │ ├── SCN4M_SUBM.20.tech │ ├── __init__.py │ ├── scn4m_subm.lydrc │ ├── scn4m_subm.lylvs │ ├── setup.tcl │ └── tech.py └── tf │ ├── README.txt │ ├── display.drf │ ├── glade_scn4m_subm.py │ ├── layers.map │ ├── mosis.lyp │ ├── mosis.lyt │ └── mosis.tf ├── setup_scripts └── gen_analytical_model.py └── sky130 ├── __init__.py ├── custom ├── __init__.py ├── replica_bitcell_array.py ├── sky130_bitcell.py ├── sky130_bitcell_array.py ├── sky130_bitcell_base_array.py ├── sky130_capped_replica_bitcell_array.py ├── sky130_col_cap.py ├── sky130_col_cap_array.py ├── sky130_corner.py ├── sky130_dummy_array.py ├── sky130_dummy_bitcell.py ├── sky130_internal.py ├── sky130_replica_bitcell.py ├── sky130_replica_bitcell_array.py ├── sky130_replica_column.py ├── sky130_row_cap.py └── sky130_row_cap_array.py └── tech ├── __init__.py ├── sky130.lydrc ├── sky130.lylvs └── tech.py /.coveragerc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSIDA/OpenRAM/HEAD/.coveragerc -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VLSIDA/OpenRAM/HEAD/.gitattributes -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug_report.md: 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