├── .gitattributes ├── FFT ├── DC │ ├── outputs │ │ ├── fft_chip.ddc │ │ ├── fft_chip.sdc │ │ └── fft_chip.v │ ├── reports │ │ ├── area_report.rpt │ │ ├── design_physical_report.rpt │ │ ├── power_report.rpt │ │ ├── qor_report.rpt │ │ ├── timing_report.rpt │ │ └── violation_report.rpt │ ├── rtl │ │ └── fft │ │ │ ├── butterfly.v │ │ │ ├── ctrl.v │ │ │ ├── fft.v │ │ │ ├── fft.v~ │ │ │ ├── fft_chip.v │ │ │ ├── fft_chip.v~ │ │ │ ├── multi16.v │ │ │ ├── mux.v │ │ │ ├── mux.v~ │ │ │ ├── p_s.v │ │ │ ├── p_s.v~ │ │ │ ├── reg1.v │ │ │ ├── reg1.v~ │ │ │ ├── s_p.v │ │ │ └── s_p.v~ │ └── scripts │ │ ├── dc.tcl │ │ ├── fft.con │ │ └── read.tcl └── ICC │ ├── design │ ├── fft_chip.ddc │ ├── fft_chip.sdc │ └── fft_chip.v │ ├── fft_chip.mw │ ├── .lock │ ├── CEL │ │ ├── 1_datasetup │ │ ├── 2_1_floorplan_init │ │ ├── 2_2_floorplan_pns │ │ ├── 2_3_floorplan_complete │ │ ├── 3_1_place_setup │ │ ├── 3_2_place_complete │ │ ├── 4_1_clock_cts │ │ ├── 4_2_clock_psyn │ │ ├── 4_3_clock_route │ │ ├── 5_route_final │ │ ├── 6_1_chip_finish_critical_area │ │ ├── 6_2_chip_finish_final │ │ └── fft_chip │ ├── lib │ ├── lib_1 │ └── lib_bck │ ├── outputs │ ├── fft_chip.def │ ├── fft_chip.gdsii │ └── fft_chip.v │ ├── reports │ ├── cts_only_cts.rpt │ ├── cts_only_psyn.rpt │ ├── data_setup.rpt │ ├── data_setup_zic.rpt │ ├── final_design.rpt │ ├── final_power.rpt │ ├── final_qor.rpt │ ├── floorplan.rpt │ ├── placement.rpt │ ├── route_final.rpt │ └── route_initial.rpt │ └── scripts │ ├── cb13_6m_antenna.tcl │ ├── common_optimization_settings_icc.tcl │ ├── common_placement_settings.tcl │ ├── common_post_cts_timing_settings.tcl │ ├── common_route_si_settings_zrt_icc.tcl │ ├── derive_pg.tcl │ ├── icc.tcl │ ├── insert_pad_filler.tcl │ ├── ndr.tcl │ ├── opt_ctrl.tcl │ ├── pad_cell_cons.tcl │ ├── pns.tcl │ ├── run_cts.tcl │ ├── run_data_setup.tcl │ ├── run_design_planning.tcl │ ├── run_finishing.tcl │ ├── run_placement.tcl │ ├── run_route.tcl │ └── zic_timing.tcl ├── LICENSE ├── README.md ├── doc ├── 0-SPEC.pdf ├── 1-方案讨论_V3.5.pdf ├── 2-signals_list_V2.0.md ├── 3-Design_Structure_V1.1.mht ├── 4-Verilog_Template_V1.3.v ├── 5-test_vectors_V2.0.md ├── 6-项目报告_V1.0.pdf ├── 7-结题答辩_V1.4.pdf ├── extra │ ├── fft.m │ ├── numI.txt │ ├── numR.txt │ └── 补充说明.pdf ├── history_versions │ ├── 1-方案讨论 │ │ ├── 1-方案讨论V1.0.pdf │ │ ├── 1-方案讨论V1.1.pdf │ │ ├── 1-方案讨论V2.0.pdf │ │ ├── 1-方案讨论V2.1.pdf │ │ ├── 1-方案讨论V3.0.pdf │ │ ├── 1-方案讨论V3.1.pdf │ │ ├── 1-方案讨论V3.2.pdf │ │ ├── 1-方案讨论V3.3.pdf │ │ └── 1-方案讨论V3.4.pdf │ ├── 2-signals_list │ │ └── 2-signals_list_V1.0.md │ ├── 3-Design_Structure │ │ └── 3-Design_Structure_V1.0.mht │ ├── 4-Verilog_Template │ │ ├── 4-Verilog_Template_V1.0.v │ │ ├── 4-Verilog_Template_V1.1.v │ │ └── 4-Verilog_Template_V1.2.v │ └── 7-结题答辩 │ │ ├── 7-结题答辩_V1.0.pdf │ │ ├── 7-结题答辩_V1.1.pdf │ │ ├── 7-结题答辩_V1.2.pdf │ │ └── 7-结题答辩_V1.3.pdf └── ref │ ├── 16点基4_FFT芯片设计技术研究.pdf │ ├── Design_of_16-point_Radix-4_Fast_Fourier_Transform_in_0.18μm_CMOS_Technology.pdf │ └── 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