├── .bazelrc ├── .bazelversion ├── .clang-format ├── .github └── workflows │ ├── 0001-TensorFlow-V280-Enable-External-Delegate.patch │ ├── bazel_x86_vsim_unit_test.yml │ ├── cmake_x86_vsim.yml │ └── self-hosted.yml ├── .gitignore ├── Android.mk ├── BUILD ├── CMakeLists.txt ├── LICENSE ├── README.md ├── VERSION ├── WORKSPACE ├── cmake ├── A311D.cmake ├── S905D3.cmake ├── X86_64_linux.cmake ├── YOCTO.cmake ├── gRPC.cmake ├── local_sdk.cmake ├── openssl.cmake ├── openssl.patch └── vim3_android.cmake ├── docs ├── Operators.md ├── Operators.md.template ├── Programming_Guide.md ├── customized_op.md ├── extend_tim-vx-operators.uxf ├── gen_docs.py ├── image │ ├── architecture.png │ ├── extend.tim-vx.operators.png │ ├── graph_lifecycle.png │ ├── timvx_overview.drawio │ └── timvx_overview.svg └── openssl_build.md ├── gen_vsi_feat_ops_def.sh ├── include └── tim │ ├── experimental │ └── trace │ │ ├── README.md │ │ ├── replayer.h │ │ ├── trace_tvx.h │ │ ├── tracer.h │ │ └── tvx │ │ ├── context.h │ │ ├── graph.h │ │ ├── ops.h │ │ ├── tensor.h │ │ └── types.h │ ├── lite │ ├── execution.h │ └── handle.h │ ├── transform │ ├── layout_inference.h │ └── mean_stddev_normalize_fusion.h │ ├── utils │ └── nbg_parser │ │ ├── gc_vip_nbg_format.h │ │ ├── nbg_parser.h │ │ ├── nbg_parser_impl.h │ │ └── nbg_parser_version.h │ └── vx │ ├── builtin_op.h │ ├── compile_option.h │ ├── context.h │ ├── graph.h │ ├── operation.h │ ├── ops.h │ ├── ops │ ├── BidirectionalSequenceLstm.json │ ├── BidirectionalSequenceRNN.json │ ├── HashtableLookup.json │ ├── L2Normalization.json │ ├── LayerNormalization.json │ ├── MaxpoolWithArgmax.json │ ├── MaxpoolWithArgmax2.json │ ├── abs.json │ ├── activations.h │ ├── add.json │ ├── addn.h │ ├── addn.json │ ├── and.json │ ├── arg.h │ ├── argmax.json │ ├── argmin.json │ ├── batch2space.h │ ├── batch2space.json │ ├── batchnorm.h │ ├── batchnorm.json │ ├── bidirectional_sequence_lstm.h │ ├── bidirectional_sequence_rnn.h │ ├── bidirectional_sequence_rnn_ext.h │ ├── broadcast.h │ ├── broadcast.json │ ├── cast.json │ ├── ceil.json │ ├── celu.json │ ├── clip.h │ ├── clip.json │ ├── concat.h │ ├── concat.json │ ├── conv1d.h │ ├── conv1d.json │ ├── conv2d.h │ ├── conv2d.json │ ├── conv3d.h │ ├── conv3d.json │ ├── cumsum.h │ ├── cumsum.json │ ├── custom_base.h │ ├── dataconvert.json │ ├── deconv.h │ ├── deconv1d.h │ ├── deconv1d.json │ ├── deconv2d.json │ ├── depth2space.h │ ├── depth2space.json │ ├── div.json │ ├── dropout.h │ ├── dropout.json │ ├── elementwise.h │ ├── elu.json │ ├── embedding_lookup.h │ ├── embeddinglookup.json │ ├── equal.json │ ├── erf.h │ ├── erf.json │ ├── exp.json │ ├── floor.json │ ├── floordiv.json │ ├── fullyconnected.h │ ├── fullyconnected.json │ ├── gather.h │ ├── gather.json │ ├── gather_elements.h │ ├── gatherelements.json │ ├── gathernd.h │ ├── gathernd.json │ ├── gelu.json │ ├── greater.json │ ├── greaterOrEqual.json │ ├── groupedConv1d.json │ ├── groupedConv2d.json │ ├── groupedconv1d.h │ ├── groupedconv2d.h │ ├── grucell.h │ ├── grucell.json │ ├── hardsigmoid.json │ ├── hardswish.json │ ├── hashtable_lookup.h │ ├── instanceNormalization.json │ ├── instancenormalization.h │ ├── l2normalization.h │ ├── layernormalization.h │ ├── leakyrelu.json │ ├── less.json │ ├── lessOrEqual.json │ ├── linear.json │ ├── localresponseNormalization.json │ ├── localresponsenormalization.h │ ├── log.json │ ├── logical.h │ ├── logicalnot.json │ ├── logicalor.json │ ├── logsoftmax.h │ ├── logsoftmax.json │ ├── matmul.h │ ├── matmul.json │ ├── max_pool3d.h │ ├── maximum.json │ ├── maxpool3d.json │ ├── maxpoolgrad.h │ ├── maxpoolwithargmax.h │ ├── maxpoolwithargmax2.h │ ├── maxunpool2d.h │ ├── maxunpool2d.json │ ├── minimum.json │ ├── mish.json │ ├── mod.h │ ├── mod.json │ ├── moments.h │ ├── moments.json │ ├── mul.json │ ├── nbg.h │ ├── nbg.json │ ├── neg.json │ ├── notEqual.json │ ├── onehot.h │ ├── onehot.json │ ├── pad.h │ ├── pad.json │ ├── pad_v2.h │ ├── padv2.json │ ├── pool1d.h │ ├── pool1d.json │ ├── pool2d.h │ ├── pool2d.json │ ├── pow.json │ ├── prelu.json │ ├── rcp.json │ ├── reduce.h │ ├── reduceall.json │ ├── reduceany.json │ ├── reducemax.json │ ├── reducemean.json │ ├── reducemin.json │ ├── reduceprod.json │ ├── reducesum.json │ ├── relational_operations.h │ ├── relu.json │ ├── relu1.json │ ├── relu6.json │ ├── reorg.h │ ├── reorg.json │ ├── reshape.h │ ├── reshape.json │ ├── resize.h │ ├── resize.json │ ├── resize1d.h │ ├── resize1d.json │ ├── reverse.h │ ├── reverse.json │ ├── rnn_cell.h │ ├── rnncell.json │ ├── roi_align.h │ ├── roi_pool.h │ ├── roialign.json │ ├── roipool.json │ ├── round.json │ ├── rsqrt.json │ ├── scatternd.h │ ├── scatternd.json │ ├── scatternd_onnx_v16.h │ ├── scatternd_onnx_v16.json │ ├── select.h │ ├── select.json │ ├── selu.json │ ├── shuffle_channel.h │ ├── shufflechannel.json │ ├── sigmoid.json │ ├── sign.json │ ├── signal_frame.h │ ├── signal_frame.json │ ├── simple_operations.h │ ├── sin.json │ ├── slice.h │ ├── slice.json │ ├── softmax.h │ ├── softmax.json │ ├── softrelu.json │ ├── softsign.json │ ├── space2batch.h │ ├── space2batch.json │ ├── space2depth.h │ ├── space2depth.json │ ├── spatial_transformer.h │ ├── spatialtransformer.json │ ├── split.h │ ├── split.json │ ├── sqrt.json │ ├── square.json │ ├── squeeze.h │ ├── squeeze.json │ ├── stack.h │ ├── stack.json │ ├── stridedslice.h │ ├── stridedslice.json │ ├── sub.json │ ├── svdf.h │ ├── svdf.json │ ├── swish.json │ ├── tanh.json │ ├── tile.h │ ├── tile.json │ ├── tiny_yolov4_postprocess.h │ ├── topk.h │ ├── topk.json │ ├── transpose.h │ ├── transpose.json │ ├── unidirectional_sequence_gru.h │ ├── unidirectional_sequence_lstm.h │ ├── unidirectional_sequence_rnn.h │ ├── unidirectional_sequence_rnn_ext.h │ ├── unidirectionalsequenceGRU.json │ ├── unidirectionalsequenceLstm.json │ ├── unidirectionalsequenceRNN.json │ ├── unstack.h │ └── unstack.json │ ├── platform │ ├── grpc │ │ └── grpc_remote.h │ ├── lite │ │ └── lite_native.h │ ├── native.h │ └── platform.h │ ├── tensor.h │ └── types.h ├── prebuilt-sdk ├── BUILD ├── VIPLite │ └── BUILD └── x86_64_linux │ ├── BUILD │ ├── VERSION │ ├── include │ ├── CL │ │ └── cl_viv_vx_ext.h │ └── VX │ │ ├── viv_nn_compatibility.h │ │ ├── vx.h │ │ ├── vx_api.h │ │ ├── vx_compatibility.h │ │ ├── vx_ext_program.h │ │ ├── vx_ext_target.h │ │ ├── vx_helper.h │ │ ├── vx_import.h │ │ ├── vx_kernels.h │ │ ├── vx_khr_cnn.h │ │ ├── vx_khr_compatible.h │ │ ├── vx_khr_dot.h │ │ ├── vx_khr_icd.h │ │ ├── vx_khr_import_kernel.h │ │ ├── vx_khr_interp.h │ │ ├── vx_khr_ix.h │ │ ├── vx_khr_nn.h │ │ ├── vx_khr_nn_internal.h │ │ ├── vx_khr_node_memory.h │ │ ├── vx_khr_opencl.h │ │ ├── vx_khr_tiling.h │ │ ├── vx_khr_variants.h │ │ ├── vx_khr_xml.h │ │ ├── vx_lib_debug.h │ │ ├── vx_lib_extras.h │ │ ├── vx_lib_xyz.h │ │ ├── vx_nodes.h │ │ ├── vx_spinst.h │ │ ├── vx_types.h │ │ ├── vx_vendors.h │ │ ├── vx_viv_sys.h │ │ └── vxu.h │ └── lib │ ├── libArchModelSw.so │ ├── libCLC.so │ ├── libEmulator.so │ ├── libGAL.1.7.4.so │ ├── libGAL.so │ ├── libNNArchPerf.so │ ├── libOpenVX.so │ ├── libOpenVX.so.1 │ ├── libOpenVX.so.1.3.0 │ ├── libOpenVXC.so │ ├── libOpenVXU.so │ ├── libVSC.so │ └── libvdtproxy.so ├── samples ├── CMakeLists.txt ├── benchmark_test │ ├── BUILD │ ├── CMakeLists.txt │ └── benchmark_test.cc ├── custom_lenet │ ├── BUILD │ ├── CMakeLists.txt │ ├── custom_softmax.cc │ ├── custom_softmax.h │ ├── lenet_asymu8.cc │ └── lenet_asymu8_weights.h ├── custom_op_test │ ├── CMakeLists.txt │ ├── custom_gemm.cc │ ├── custom_gemm.h │ └── custom_op_test.cc ├── grpc │ ├── CMakeLists.txt │ ├── README.txt │ └── grpc_multi_device.cc ├── lenet │ ├── BUILD │ ├── CMakeLists.txt │ ├── lenet_asymu8.cc │ └── lenet_asymu8_weights.h ├── lenet_lite │ ├── BUILD │ ├── CMakeLists.txt │ ├── lenet_lite_asymu8.cc │ └── lenet_lite_asymu8_executable.h ├── lenet_multi_device │ ├── BUILD │ ├── CMakeLists.txt │ ├── lenet.h │ └── lenet_multi_device.cc ├── multi_device │ ├── CMakeLists.txt │ ├── README │ ├── lenet │ │ ├── lenet.export.data │ │ └── lenet_input_1_1_28_28_uint8.bin │ ├── mobilenet │ │ ├── mobilenet.export.data │ │ └── mobilenet_1_224_224_3_uint8.bin │ ├── multi_device.cc │ ├── multi_device_demo.cc │ ├── resnet50 │ │ ├── resnet50.export.data │ │ └── resnet50_1_3_224_224_uint8.bin │ ├── vx_lenet.cc │ ├── vx_lenet.h │ ├── vx_mobilenet.cc │ ├── vx_mobilenet.h │ ├── vx_resnet50.cc │ └── vx_resnet50.h ├── multi_thread_test │ ├── BUILD │ ├── CMakeLists.txt │ ├── lenet_asymu8_weights.h │ └── multi_thread_test.cc ├── nbg_runner │ ├── BUILD │ ├── CMakeLists.txt │ └── nbg_runner_main.cc ├── nbg_runner_pybind │ ├── .clang-format │ ├── .clang-tidy │ ├── .gitignore │ ├── CMakeLists.txt │ ├── README.md │ ├── cmake │ │ └── modules │ │ │ ├── FindPyBind11.cmake │ │ │ └── FindVivanteSDK.cmake │ ├── examples │ │ ├── data │ │ │ ├── bird.jpg │ │ │ ├── cat.jpg │ │ │ └── imagenet1k_labels.txt │ │ ├── demo.py │ │ ├── imagenet1k.py │ │ └── models │ │ │ └── conv2d_relu_maxpool2d_fp32.nbg │ ├── python │ │ └── nbg_runner │ │ │ ├── __init__.py │ │ │ ├── _binding │ │ │ └── __init__.py │ │ │ └── vx │ │ │ ├── __init__.py │ │ │ └── ovx_executor.py │ └── src │ │ ├── CMakeLists.txt │ │ ├── nbg_runner_pybind.cpp │ │ └── vx │ │ ├── CMakeLists.txt │ │ ├── ovx_executor.cpp │ │ ├── ovx_executor.hpp │ │ └── utils.hpp └── platform_sample │ ├── CMakeLists.txt │ ├── README │ └── platform_sample.cc ├── src └── tim │ ├── CMakeLists.txt │ ├── lite │ ├── execution.cc │ ├── execution_private.h │ ├── handle.cc │ └── handle_private.h │ ├── transform │ ├── average_pool_layout_infer_test.cc │ ├── layout_infer_context.h │ ├── layout_inference.cc │ ├── layout_inference_test.cc │ ├── mean_stddev_normalize_fusion.cc │ ├── ops │ │ ├── activation_layout_inference.h │ │ ├── addn_layout_inference.h │ │ ├── arg_layout_inference.h │ │ ├── batch2space_layout_inference.h │ │ ├── batchnorm_layout_inference.h │ │ ├── bidirectional_rnn_layout_inference.h │ │ ├── broadcast_layout_inference.h │ │ ├── concat_layout_inferene.h │ │ ├── conv2d_layout_inference.h │ │ ├── conv3d_layout_inference.h │ │ ├── deconv2d_layout_inference.h │ │ ├── default_layout_inference.h │ │ ├── depth2space_layout_inference.h │ │ ├── elementwise_layout_inference.h │ │ ├── fullyconnected_layout_inference.h │ │ ├── gather_layout_inference.h │ │ ├── gather_nd_layout_inference.h │ │ ├── grouped_conv2d_layout_inference.h │ │ ├── instance_norm_layout_inference.h │ │ ├── l2normalization_layout_inference.h │ │ ├── logical_layout_inference.h │ │ ├── lrn_layout_inference.h │ │ ├── op_layout_inference.cc │ │ ├── op_layout_inference.h │ │ ├── pad_layout_inference.h │ │ ├── pad_v2_layout_inference.h │ │ ├── pool2d_layout_inference.h │ │ ├── reduce_layout_inference.h │ │ ├── resize_layout_inference.h │ │ ├── reverse_layout_inference.h │ │ ├── roi_align_layout_inference.h │ │ ├── roi_pool_layout_inference.h │ │ ├── select_layout_inference.h │ │ ├── simple_ops_layout_inference.h │ │ ├── slice_layout_inference.h │ │ ├── softmax_layout_inference.h │ │ ├── space2batch_layout_inference.h │ │ ├── space2depth_layout_inference.h │ │ ├── split_layout_inference.h │ │ ├── squeeze_layout_inference.h │ │ ├── stack_layout_inference.h │ │ ├── stridedslice_layout_inference.h │ │ ├── transpose_layout_inference.h │ │ ├── unidirectional_lstm_layout_inference.h │ │ ├── unidirectional_rnn_layout_inference.h │ │ └── yolov4_layout_inference.h │ ├── pad_layout_inference_test.cc │ ├── permute_vector.h │ ├── prelu_layout_inference_test.cc │ ├── reduce_layout_inference_test.cc │ ├── rnncell_layout_inference_test.cc │ ├── stack_layout_inference_test.cc │ └── stridedslice_layout_inference_test.cc │ ├── utils │ ├── CMakeLists.txt │ └── nbg_parser │ │ ├── CMakeLists.txt │ │ └── nbg_parser.c │ └── vx │ ├── builtin_op.cc │ ├── builtin_op_impl.cc │ ├── builtin_op_impl.h │ ├── compile_option.cc │ ├── compile_option_test.cc │ ├── context.cc │ ├── context_private.h │ ├── context_test.cc │ ├── graph.cc │ ├── graph_private.h │ ├── graph_test.cc │ ├── internal │ ├── .clang-format │ ├── .gitignore │ ├── BUILD │ ├── ConvertPGMToH.py │ ├── include │ │ ├── custom │ │ │ ├── custom_node_type.def │ │ │ ├── custom_ops.def │ │ │ ├── ops │ │ │ │ ├── vsi_nn_op_custom_ainr_denoise_postprocess.h │ │ │ │ ├── vsi_nn_op_custom_letterbox.h │ │ │ │ ├── vsi_nn_op_custom_sample.h │ │ │ │ ├── vsi_nn_op_custom_softmax.h │ │ │ │ ├── vsi_nn_op_custom_tiny_yolov4_postprocess.h │ │ │ │ ├── vsi_nn_op_custom_tiny_yolov4_postprocess_box.h │ │ │ │ ├── vsi_nn_op_custom_tiny_yolov4_postprocess_confidence.h │ │ │ │ ├── vsi_nn_op_custom_warp_affine.h │ │ │ │ └── vsi_nn_op_custom_warp_perspective.h │ │ │ └── vsi_nn_custom_node_type.h │ │ ├── interface │ │ │ └── ops.def │ │ ├── internal │ │ │ └── internal_ops.def │ │ ├── kernel │ │ │ ├── vsi_nn_gpu.h │ │ │ ├── vsi_nn_gpu_config.h │ │ │ ├── vsi_nn_kernel.h │ │ │ ├── vsi_nn_kernel_eltwise.h │ │ │ ├── vsi_nn_kernel_gpu_shape_optimize.h │ │ │ ├── vsi_nn_kernel_lut.h │ │ │ └── vsi_nn_kernel_node.h │ │ ├── libnnext │ │ │ ├── vsi_nn_libnnext_resource.h │ │ │ ├── vsi_nn_vxkernel.h │ │ │ ├── vx_bin │ │ │ │ └── vxc_binaries.h │ │ │ └── vx_lib_nnext.h │ │ ├── ops │ │ │ ├── vsi_nn_op_activations.h │ │ │ ├── vsi_nn_op_addn.h │ │ │ ├── vsi_nn_op_argmax.h │ │ │ ├── vsi_nn_op_argmin.h │ │ │ ├── vsi_nn_op_avg_pool3d.h │ │ │ ├── vsi_nn_op_axis_aligned_bbox_transform.h │ │ │ ├── vsi_nn_op_batch2space.h │ │ │ ├── vsi_nn_op_batch_norm.h │ │ │ ├── vsi_nn_op_batchnorm_single.h │ │ │ ├── vsi_nn_op_bidirectional_sequence_lstm.h │ │ │ ├── vsi_nn_op_bidirectional_sequence_rnn.h │ │ │ ├── vsi_nn_op_bitcast.h │ │ │ ├── vsi_nn_op_box_with_nms_limit.h │ │ │ ├── vsi_nn_op_bucketize.h │ │ │ ├── vsi_nn_op_cast.h │ │ │ ├── vsi_nn_op_celu.h │ │ │ ├── vsi_nn_op_clip.h │ │ │ ├── vsi_nn_op_col2im.h │ │ │ ├── vsi_nn_op_concat.h │ │ │ ├── vsi_nn_op_concatshift.h │ │ │ ├── vsi_nn_op_conv1d.h │ │ │ ├── vsi_nn_op_conv2d.h │ │ │ ├── vsi_nn_op_conv2d_lstm.h │ │ │ ├── vsi_nn_op_conv2d_lstm_cell.h │ │ │ ├── vsi_nn_op_conv3d.h │ │ │ ├── vsi_nn_op_conv_relu.h │ │ │ ├── vsi_nn_op_crop.h │ │ │ ├── vsi_nn_op_crop_and_resize.h │ │ │ ├── vsi_nn_op_cumsum.h │ │ │ ├── vsi_nn_op_dataconvert.h │ │ │ ├── vsi_nn_op_deconv3d.h │ │ │ ├── vsi_nn_op_deconvolution.h │ │ │ ├── vsi_nn_op_deconvolution1d.h │ │ │ ├── vsi_nn_op_depth2space.h │ │ │ ├── vsi_nn_op_depth2space_internal.h │ │ │ ├── vsi_nn_op_depthwise_conv1d.h │ │ │ ├── vsi_nn_op_detection_postprocess.h │ │ │ ├── vsi_nn_op_divide.h │ │ │ ├── vsi_nn_op_dropout.h │ │ │ ├── vsi_nn_op_elu.h │ │ │ ├── vsi_nn_op_embedding_lookup.h │ │ │ ├── vsi_nn_op_exp.h │ │ │ ├── vsi_nn_op_expand_broadcast.h │ │ │ ├── vsi_nn_op_extra_ending.h │ │ │ ├── vsi_nn_op_floor.h │ │ │ ├── vsi_nn_op_floordiv.h │ │ │ ├── vsi_nn_op_fullconnect.h │ │ │ ├── vsi_nn_op_gather.h │ │ │ ├── vsi_nn_op_gather_elements.h │ │ │ ├── vsi_nn_op_gather_nd.h │ │ │ ├── vsi_nn_op_gelu.h │ │ │ ├── vsi_nn_op_generate_proposals.h │ │ │ ├── vsi_nn_op_globallppool.h │ │ │ ├── vsi_nn_op_grid_sample.h │ │ │ ├── vsi_nn_op_grouped_conv1d.h │ │ │ ├── vsi_nn_op_grouped_conv2d.h │ │ │ ├── vsi_nn_op_grouped_conv3d.h │ │ │ ├── vsi_nn_op_groupnormalize.h │ │ │ ├── vsi_nn_op_gru.h │ │ │ ├── vsi_nn_op_gru_ovxlib.h │ │ │ ├── vsi_nn_op_grucell.h │ │ │ ├── vsi_nn_op_grucell_activation.h │ │ │ ├── vsi_nn_op_grucell_activation_internal.h │ │ │ ├── vsi_nn_op_grucell_activation_internal_sma.h │ │ │ ├── vsi_nn_op_grucell_activation_z_h.h │ │ │ ├── vsi_nn_op_grucell_h_times_activation_r.h │ │ │ ├── vsi_nn_op_grucell_ovxlib.h │ │ │ ├── vsi_nn_op_hard_sigmoid.h │ │ │ ├── vsi_nn_op_heatmap_max_keypoint.h │ │ │ ├── vsi_nn_op_imageprocess.h │ │ │ ├── vsi_nn_op_instancenormalize.h │ │ │ ├── vsi_nn_op_interp.h │ │ │ ├── vsi_nn_op_inverse_sigmoid.h │ │ │ ├── vsi_nn_op_l1_layer_norm.h │ │ │ ├── vsi_nn_op_l2_normalize.h │ │ │ ├── vsi_nn_op_l2normalizescale.h │ │ │ ├── vsi_nn_op_layernormalize.h │ │ │ ├── vsi_nn_op_linear.h │ │ │ ├── vsi_nn_op_log.h │ │ │ ├── vsi_nn_op_log_softmax.h │ │ │ ├── vsi_nn_op_logical_not.h │ │ │ ├── vsi_nn_op_logical_ops.h │ │ │ ├── vsi_nn_op_lpnorm.h │ │ │ ├── vsi_nn_op_lppool.h │ │ │ ├── vsi_nn_op_lrn.h │ │ │ ├── vsi_nn_op_lsh_projection.h │ │ │ ├── vsi_nn_op_lstm.h │ │ │ ├── vsi_nn_op_lstm_ovxlib.h │ │ │ ├── vsi_nn_op_lstmunit.h │ │ │ ├── vsi_nn_op_lstmunit_activation.h │ │ │ ├── vsi_nn_op_lstmunit_ovxlib.h │ │ │ ├── vsi_nn_op_matrixmul.h │ │ │ ├── vsi_nn_op_max_pool3d.h │ │ │ ├── vsi_nn_op_maximum.h │ │ │ ├── vsi_nn_op_maxunpool.h │ │ │ ├── vsi_nn_op_mod.h │ │ │ ├── vsi_nn_op_moments.h │ │ │ ├── vsi_nn_op_multiply.h │ │ │ ├── vsi_nn_op_nbg.h │ │ │ ├── vsi_nn_op_neg.h │ │ │ ├── vsi_nn_op_nms.h │ │ │ ├── vsi_nn_op_one_hot.h │ │ │ ├── vsi_nn_op_pad.h │ │ │ ├── vsi_nn_op_pad2.h │ │ │ ├── vsi_nn_op_permute.h │ │ │ ├── vsi_nn_op_pool.h │ │ │ ├── vsi_nn_op_post_process.h │ │ │ ├── vsi_nn_op_pow.h │ │ │ ├── vsi_nn_op_pre_process.h │ │ │ ├── vsi_nn_op_pre_process_bgra.h │ │ │ ├── vsi_nn_op_pre_process_gray.h │ │ │ ├── vsi_nn_op_pre_process_nv12.h │ │ │ ├── vsi_nn_op_pre_process_rgb.h │ │ │ ├── vsi_nn_op_pre_process_rgb888_planar.h │ │ │ ├── vsi_nn_op_pre_process_tensor.h │ │ │ ├── vsi_nn_op_pre_process_yuv420.h │ │ │ ├── vsi_nn_op_pre_process_yuv422.h │ │ │ ├── vsi_nn_op_pre_process_yuv444.h │ │ │ ├── vsi_nn_op_prelu.h │ │ │ ├── vsi_nn_op_proposal.h │ │ │ ├── vsi_nn_op_quantized_16bit_lstm.h │ │ │ ├── vsi_nn_op_random_multinomial.h │ │ │ ├── vsi_nn_op_rcp.h │ │ │ ├── vsi_nn_op_reduce.h │ │ │ ├── vsi_nn_op_reduce_mean_internal.h │ │ │ ├── vsi_nn_op_reduceall_internal.h │ │ │ ├── vsi_nn_op_reduceany_internal.h │ │ │ ├── vsi_nn_op_reducel2.h │ │ │ ├── vsi_nn_op_reducemax_internal.h │ │ │ ├── vsi_nn_op_reducemin_internal.h │ │ │ ├── vsi_nn_op_reduceprod_internal.h │ │ │ ├── vsi_nn_op_reducesum_internal.h │ │ │ ├── vsi_nn_op_relational_ops.h │ │ │ ├── vsi_nn_op_relu_keras.h │ │ │ ├── vsi_nn_op_relu_keras_internal.h │ │ │ ├── vsi_nn_op_relun.h │ │ │ ├── vsi_nn_op_reorg.h │ │ │ ├── vsi_nn_op_repeat.h │ │ │ ├── vsi_nn_op_reshape.h │ │ │ ├── vsi_nn_op_reshape2.h │ │ │ ├── vsi_nn_op_resize.h │ │ │ ├── vsi_nn_op_resize_1d.h │ │ │ ├── vsi_nn_op_resize_1d_bilinear_internal.h │ │ │ ├── vsi_nn_op_resize_1d_nearest_internal.h │ │ │ ├── vsi_nn_op_resize_3d.h │ │ │ ├── vsi_nn_op_resize_internal.h │ │ │ ├── vsi_nn_op_resize_nearest_internal.h │ │ │ ├── vsi_nn_op_reverse.h │ │ │ ├── vsi_nn_op_reversesequence.h │ │ │ ├── vsi_nn_op_rmsnorm.h │ │ │ ├── vsi_nn_op_rnn.h │ │ │ ├── vsi_nn_op_rnncell_ovxlib.h │ │ │ ├── vsi_nn_op_roi_align.h │ │ │ ├── vsi_nn_op_roi_pool.h │ │ │ ├── vsi_nn_op_rope.h │ │ │ ├── vsi_nn_op_scale.h │ │ │ ├── vsi_nn_op_scatter_elements.h │ │ │ ├── vsi_nn_op_scatter_nd.h │ │ │ ├── vsi_nn_op_scatter_nd_update.h │ │ │ ├── vsi_nn_op_select.h │ │ │ ├── vsi_nn_op_selu.h │ │ │ ├── vsi_nn_op_sequence_mask.h │ │ │ ├── vsi_nn_op_shape.h │ │ │ ├── vsi_nn_op_shufflechannel.h │ │ │ ├── vsi_nn_op_sign.h │ │ │ ├── vsi_nn_op_signalframe.h │ │ │ ├── vsi_nn_op_sin.h │ │ │ ├── vsi_nn_op_slice.h │ │ │ ├── vsi_nn_op_softmax.h │ │ │ ├── vsi_nn_op_softmax_internal.h │ │ │ ├── vsi_nn_op_softsign.h │ │ │ ├── vsi_nn_op_space2batch.h │ │ │ ├── vsi_nn_op_space2depth.h │ │ │ ├── vsi_nn_op_space2depth_internal.h │ │ │ ├── vsi_nn_op_spatial_transformer.h │ │ │ ├── vsi_nn_op_split.h │ │ │ ├── vsi_nn_op_squeeze.h │ │ │ ├── vsi_nn_op_stack.h │ │ │ ├── vsi_nn_op_strided_slice.h │ │ │ ├── vsi_nn_op_svdf.h │ │ │ ├── vsi_nn_op_swish.h │ │ │ ├── vsi_nn_op_tanh.h │ │ │ ├── vsi_nn_op_tensor_add_mean_stddev_norm.h │ │ │ ├── vsi_nn_op_tensorstackconcat.h │ │ │ ├── vsi_nn_op_tile.h │ │ │ ├── vsi_nn_op_topk.h │ │ │ ├── vsi_nn_op_unidirectional_sequence_rnn.h │ │ │ ├── vsi_nn_op_unstack.h │ │ │ ├── vsi_nn_op_upsample.h │ │ │ ├── vsi_nn_op_upsamplescale.h │ │ │ └── vsi_nn_op_variable.h │ │ ├── post │ │ │ ├── vsi_nn_post_cmupose.h │ │ │ └── vsi_nn_post_fasterrcnn.h │ │ ├── quantization │ │ │ ├── vsi_nn_asymmetric_affine.h │ │ │ ├── vsi_nn_dynamic_fixed_point.h │ │ │ └── vsi_nn_perchannel_symmetric_affine.h │ │ ├── utils │ │ │ ├── vsi_nn_binary_tree.h │ │ │ ├── vsi_nn_code_generator.h │ │ │ ├── vsi_nn_constraint_check.h │ │ │ ├── vsi_nn_dlfcn.h │ │ │ ├── vsi_nn_dtype_util.h │ │ │ ├── vsi_nn_dtype_util_prv.h │ │ │ ├── vsi_nn_hashmap.h │ │ │ ├── vsi_nn_limits.h │ │ │ ├── vsi_nn_link_list.h │ │ │ ├── vsi_nn_map.h │ │ │ ├── vsi_nn_math.h │ │ │ ├── vsi_nn_shape_util.h │ │ │ ├── vsi_nn_tensor_op.h │ │ │ └── vsi_nn_util.h │ │ ├── vip │ │ │ └── virtual_device.h │ │ ├── vsi_nn_assert.h │ │ ├── vsi_nn_client_op.h │ │ ├── vsi_nn_compatibility.h │ │ ├── vsi_nn_context.h │ │ ├── vsi_nn_daemon.h │ │ ├── vsi_nn_error.h │ │ ├── vsi_nn_feature.h │ │ ├── vsi_nn_feature_config.h │ │ ├── vsi_nn_graph.h │ │ ├── vsi_nn_graph_optimization.h │ │ ├── vsi_nn_internal_node.h │ │ ├── vsi_nn_log.h │ │ ├── vsi_nn_node.h │ │ ├── vsi_nn_node_attr_template.h │ │ ├── vsi_nn_node_type.h │ │ ├── vsi_nn_ops.h │ │ ├── vsi_nn_platform.h │ │ ├── vsi_nn_post.h │ │ ├── vsi_nn_pre_post_process.h │ │ ├── vsi_nn_prv.h │ │ ├── vsi_nn_pub.h │ │ ├── vsi_nn_rnn.h │ │ ├── vsi_nn_rnn_helper.h │ │ ├── vsi_nn_rnn_prv.h │ │ ├── vsi_nn_tensor.h │ │ ├── vsi_nn_tensor_util.h │ │ ├── vsi_nn_test.h │ │ ├── vsi_nn_types.h │ │ └── vsi_nn_version.h │ ├── ovxlib_bin_build.md │ ├── ovxlib_bin_build.sh │ ├── src │ │ ├── Android.mk │ │ ├── custom │ │ │ └── ops │ │ │ │ ├── custom_tiny_yolov4_postprocess.c │ │ │ │ ├── custom_tiny_yolov4_postprocess_box.c │ │ │ │ ├── custom_tiny_yolov4_postprocess_confidence.c │ │ │ │ ├── kernel │ │ │ │ ├── cl │ │ │ │ │ └── custom_softmax.cl │ │ │ │ ├── cpu │ │ │ │ │ ├── custom_sample_cpu.c │ │ │ │ │ ├── custom_softmax_cpu.c │ │ │ │ │ ├── custom_warp_affine_cpu.c │ │ │ │ │ └── custom_warp_perspective_cpu.c │ │ │ │ └── evis │ │ │ │ │ ├── custom_letterbox_evis.c │ │ │ │ │ ├── custom_softmax_evis.c │ │ │ │ │ ├── custom_tiny_yolov4_postprocess_box_evis.c │ │ │ │ │ ├── custom_tiny_yolov4_postprocess_confidence_evis.c │ │ │ │ │ ├── custom_warp_affine_evis.c │ │ │ │ │ └── custom_warp_perspective_evis.c │ │ │ │ ├── op_custom_ainr_denoise_postprocess.c │ │ │ │ ├── op_custom_sample.c │ │ │ │ ├── op_custom_softmax.c │ │ │ │ ├── vsi_nn_op_custom_letterbox.c │ │ │ │ ├── vsi_nn_op_custom_warp_affine.c │ │ │ │ └── vsi_nn_op_custom_warp_perspective.c │ │ ├── kernel │ │ │ ├── cl │ │ │ │ ├── add_mean_std_norm_cl.c │ │ │ │ ├── argmax_cl.c │ │ │ │ ├── argmin_cl.c │ │ │ │ ├── avg_pool3d_cl.c │ │ │ │ ├── batchnorm_single_cl.c │ │ │ │ ├── bilinear_grid_sample_cl.c │ │ │ │ ├── bucketize_cl.c │ │ │ │ ├── cast_cl.c │ │ │ │ ├── clip_cl.c │ │ │ │ ├── col2im_cl.c │ │ │ │ ├── comparisons_cl.c │ │ │ │ ├── crop_and_resize_cl.c │ │ │ │ ├── cumsum_cl.c │ │ │ │ ├── depth2space_internal_cl.c │ │ │ │ ├── eltwise_unary_cl.c │ │ │ │ ├── erf_cl.c │ │ │ │ ├── floordiv_cl.c │ │ │ │ ├── gather_cl.c │ │ │ │ ├── gather_elements_cl.c │ │ │ │ ├── gather_nd_cl.c │ │ │ │ ├── globallppool_cl.c │ │ │ │ ├── group_normalization_cl.c │ │ │ │ ├── grucell_activation_cl.c │ │ │ │ ├── grucell_activation_sma_cl.c │ │ │ │ ├── grucell_activation_z_h_cl.c │ │ │ │ ├── grucell_h_times_activation_r_cl.c │ │ │ │ ├── grucell_reset_after_activation_cl.c │ │ │ │ ├── instance_normalization_cl.c │ │ │ │ ├── l1norm_cl.c │ │ │ │ ├── l2normalizescale_cl.c │ │ │ │ ├── layer_normalization_cl.c │ │ │ │ ├── log_softmax_cl.c │ │ │ │ ├── logical_not_cl.c │ │ │ │ ├── logical_ops_cl.c │ │ │ │ ├── lppool_cl.c │ │ │ │ ├── lstmunit_activation_cl.c │ │ │ │ ├── matrixmul_cl.c │ │ │ │ ├── maximum_cl.c │ │ │ │ ├── maxpoolwithargmax_cl.c │ │ │ │ ├── maxunpool_cl.c │ │ │ │ ├── minimum_cl.c │ │ │ │ ├── mod_cl.c │ │ │ │ ├── moments_cl.c │ │ │ │ ├── nearest_grid_sample_cl.c │ │ │ │ ├── one_hot_cl.c │ │ │ │ ├── pool_cl.c │ │ │ │ ├── poolwithargmax_cl.c │ │ │ │ ├── pow_cl.c │ │ │ │ ├── prelu_cl.c │ │ │ │ ├── random_multinomial_cl.c │ │ │ │ ├── reduceall_internal_cl.c │ │ │ │ ├── reduceany_internal_cl.c │ │ │ │ ├── reducemax_internal_cl.c │ │ │ │ ├── reducemin_internal_cl.c │ │ │ │ ├── reduceprod_internal_cl.c │ │ │ │ ├── relu_keras_cl.c │ │ │ │ ├── repeat_cl.c │ │ │ │ ├── resize_1d_bilinear_cl.c │ │ │ │ ├── resize_1d_nearest_cl.c │ │ │ │ ├── resize_3d_bilinear_cl.c │ │ │ │ ├── resize_3d_nearest_cl.c │ │ │ │ ├── resize_bilinear_cl.c │ │ │ │ ├── resize_cubic_cl.c │ │ │ │ ├── resize_nearest_cl.c │ │ │ │ ├── reversesequence_cl.c │ │ │ │ ├── roi_align_cl.c │ │ │ │ ├── rope_cl.c │ │ │ │ ├── scatter_elements_cl.c │ │ │ │ ├── scatter_nd_cl.c │ │ │ │ ├── scatter_nd_update_cl.c │ │ │ │ ├── scatter_nd_update_reduction_cl.c │ │ │ │ ├── select_cl.c │ │ │ │ ├── sequence_mask_cl.c │ │ │ │ ├── signal_frame_cl.c │ │ │ │ ├── slice_cl.c │ │ │ │ ├── space2depth_internal_cl.c │ │ │ │ ├── swish_cl.c │ │ │ │ ├── tile_cl.c │ │ │ │ ├── topk_cl.c │ │ │ │ └── upsample_cl.c │ │ │ ├── evis │ │ │ │ ├── a_times_b_plus_c_evis.c │ │ │ │ ├── add_mean_std_norm_evis.c │ │ │ │ ├── argmax_evis.c │ │ │ │ ├── argmin_evis.c │ │ │ │ ├── batchnorm_single_evis.c │ │ │ │ ├── bilinear_grid_sample_evis.c │ │ │ │ ├── bucketize_evis.c │ │ │ │ ├── cast_evis.c │ │ │ │ ├── clip_evis.c │ │ │ │ ├── comparisons_evis.c │ │ │ │ ├── conv1d_ovxlib_evis.c │ │ │ │ ├── crop_and_resize_evis.c │ │ │ │ ├── cumsum_evis.c │ │ │ │ ├── depth2space_internal_evis.c │ │ │ │ ├── depthwise_conv1d_evis.c │ │ │ │ ├── detect_post_box_evis.c │ │ │ │ ├── detect_post_nms_evis.c │ │ │ │ ├── eltwise_unary_evis.c │ │ │ │ ├── erf_evis.c │ │ │ │ ├── extra_ending_evis.c │ │ │ │ ├── floordiv_evis.c │ │ │ │ ├── gather_elements_evis.c │ │ │ │ ├── gather_evis.c │ │ │ │ ├── gather_nd_evis.c │ │ │ │ ├── group_normalization_evis.c │ │ │ │ ├── grucell_activation_evis.c │ │ │ │ ├── grucell_activation_sma_evis.c │ │ │ │ ├── grucell_activation_z_h_evis.c │ │ │ │ ├── grucell_h_times_activation_r_evis.c │ │ │ │ ├── grucell_reset_after_activation_evis.c │ │ │ │ ├── instance_normalization_evis.c │ │ │ │ ├── l1norm_evis.c │ │ │ │ ├── l2normalizescale_evis.c │ │ │ │ ├── layer_normalization_evis.c │ │ │ │ ├── log_softmax_evis.c │ │ │ │ ├── logical_not_evis.c │ │ │ │ ├── logical_ops_evis.c │ │ │ │ ├── lstmunit_activation_evis.c │ │ │ │ ├── matrixmul_evis.c │ │ │ │ ├── maximum_evis.c │ │ │ │ ├── minimum_evis.c │ │ │ │ ├── mod_evis.c │ │ │ │ ├── moments_evis.c │ │ │ │ ├── nearest_grid_sample_evis.c │ │ │ │ ├── one_hot_evis.c │ │ │ │ ├── pool_evis.c │ │ │ │ ├── poolwithargmax_evis.c │ │ │ │ ├── pow_evis.c │ │ │ │ ├── pre_process_bgra_evis.c │ │ │ │ ├── pre_process_gray_evis.c │ │ │ │ ├── pre_process_nv12_evis.c │ │ │ │ ├── pre_process_nv12_rggb_evis.c │ │ │ │ ├── pre_process_rgb888_planar_evis.c │ │ │ │ ├── pre_process_rgb888_planar_nhwc_evis.c │ │ │ │ ├── pre_process_rgb_evis.c │ │ │ │ ├── pre_process_yuv420_evis.c │ │ │ │ ├── pre_process_yuv422_evis.c │ │ │ │ ├── pre_process_yuv444_evis.c │ │ │ │ ├── prelu_evis.c │ │ │ │ ├── random_multinomial_evis.c │ │ │ │ ├── reduceall_internal_evis.c │ │ │ │ ├── reduceany_internal_evis.c │ │ │ │ ├── reducemax_internal_evis.c │ │ │ │ ├── reducemin_internal_evis.c │ │ │ │ ├── reduceprod_internal_evis.c │ │ │ │ ├── relu_keras_evis.c │ │ │ │ ├── repeat_evis.c │ │ │ │ ├── resize_1d_bilinear_evis.c │ │ │ │ ├── resize_1d_nearest_evis.c │ │ │ │ ├── resize_bilinear_evis.c │ │ │ │ ├── resize_bilinear_nhwc_evis.c │ │ │ │ ├── resize_cubic_evis.c │ │ │ │ ├── resize_nearest_evis.c │ │ │ │ ├── rope_evis.c │ │ │ │ ├── scatter_nd_evis.c │ │ │ │ ├── scatter_nd_update_evis.c │ │ │ │ ├── scatter_nd_update_reduction_evis.c │ │ │ │ ├── select_evis.c │ │ │ │ ├── sequence_mask_evis.c │ │ │ │ ├── signal_frame_evis.c │ │ │ │ ├── slice_evis.c │ │ │ │ ├── space2depth_internal_evis.c │ │ │ │ ├── spatial_transformer_evis.c │ │ │ │ ├── swish_evis.c │ │ │ │ ├── tensorstackconcat_evis.c │ │ │ │ ├── tile_evis.c │ │ │ │ ├── upsample_evis.c │ │ │ │ └── upsamplescale_evis.c │ │ │ ├── vsi_nn_gpu.c │ │ │ ├── vsi_nn_kernel.c │ │ │ ├── vsi_nn_kernel_backend.c │ │ │ ├── vsi_nn_kernel_eltwise.c │ │ │ ├── vsi_nn_kernel_gpu_shape_optimize.c │ │ │ ├── vsi_nn_kernel_lut.c │ │ │ ├── vsi_nn_kernel_node.c │ │ │ ├── vsi_nn_kernel_param.c │ │ │ ├── vsi_nn_kernel_selector.c │ │ │ ├── vsi_nn_kernel_util.c │ │ │ └── vx │ │ │ │ ├── a_times_b_plus_c_vx.c │ │ │ │ ├── argmax_vx.c │ │ │ │ ├── batch_norm_vx.c │ │ │ │ ├── bitcast_vx.c │ │ │ │ ├── convolutional.c │ │ │ │ ├── eltwise_unary_vx.c │ │ │ │ ├── eltwise_vx.c │ │ │ │ ├── gather_vx.c │ │ │ │ ├── grid_sample_vx.c │ │ │ │ ├── group_norm_vx.c │ │ │ │ ├── instance_norm_vx.c │ │ │ │ ├── l1_layer_norm_vx.c │ │ │ │ ├── l2_normalize_vx.c │ │ │ │ ├── layer_norm_vx.c │ │ │ │ ├── log_softmax_vx.c │ │ │ │ ├── matrixmul_vx.c │ │ │ │ ├── pad2_vx.c │ │ │ │ ├── pow_vx.c │ │ │ │ ├── prelu_vx.c │ │ │ │ ├── relationalops_vx.c │ │ │ │ ├── resize_vx.c │ │ │ │ ├── rms_norm_vx.c │ │ │ │ ├── select_vx.c │ │ │ │ ├── softmax_vx.c │ │ │ │ ├── square_vx.c │ │ │ │ ├── swish_vx.c │ │ │ │ └── tile_vx.c │ │ ├── libnnext │ │ │ ├── ops │ │ │ │ ├── cl │ │ │ │ │ ├── add_mean_std_norm.cl │ │ │ │ │ ├── argmax_axis0.cl │ │ │ │ │ ├── argmax_axis1.cl │ │ │ │ │ ├── argmax_axis2.cl │ │ │ │ │ ├── argmin_axis0.cl │ │ │ │ │ ├── argmin_axis1.cl │ │ │ │ │ ├── argmin_axis2.cl │ │ │ │ │ ├── avg_pool3d.cl │ │ │ │ │ ├── batchnorm_single.cl │ │ │ │ │ ├── bilinear_grid_sample.cl │ │ │ │ │ ├── bilinear_grid_sample_reflect.cl │ │ │ │ │ ├── bucketize.cl │ │ │ │ │ ├── cast.cl │ │ │ │ │ ├── clip_BF16.cl │ │ │ │ │ ├── clip_F32.cl │ │ │ │ │ ├── clip_I32.cl │ │ │ │ │ ├── clip_U8.cl │ │ │ │ │ ├── col2im.cl │ │ │ │ │ ├── crop_and_resize_bilinear.cl │ │ │ │ │ ├── crop_and_resize_nearest_neighbor.cl │ │ │ │ │ ├── cumsum.cl │ │ │ │ │ ├── cumsum_2d.cl │ │ │ │ │ ├── cumsum_array_2d_axis0.cl │ │ │ │ │ ├── cumsum_array_2d_axis1.cl │ │ │ │ │ ├── cumsum_array_axis0.cl │ │ │ │ │ ├── cumsum_array_axis1.cl │ │ │ │ │ ├── cumsum_array_axis2.cl │ │ │ │ │ ├── depth2space_crd.cl │ │ │ │ │ ├── eltwise_ops_helper.cl │ │ │ │ │ ├── eltwise_unary_0.cl │ │ │ │ │ ├── eltwise_unary_1.cl │ │ │ │ │ ├── erf.cl │ │ │ │ │ ├── floordiv.cl │ │ │ │ │ ├── gather.cl │ │ │ │ │ ├── gather_array.cl │ │ │ │ │ ├── gather_batch.cl │ │ │ │ │ ├── gather_elements.cl │ │ │ │ │ ├── gather_nd.cl │ │ │ │ │ ├── gather_nd_3d.cl │ │ │ │ │ ├── gather_nd_batch.cl │ │ │ │ │ ├── globallppool.cl │ │ │ │ │ ├── group_normalization_f32.cl │ │ │ │ │ ├── group_normalization_i32.cl │ │ │ │ │ ├── group_normalization_u8.cl │ │ │ │ │ ├── grucell_activation.cl │ │ │ │ │ ├── grucell_activation_sma.cl │ │ │ │ │ ├── grucell_activation_z_h.cl │ │ │ │ │ ├── grucell_h_times_activation_r.cl │ │ │ │ │ ├── grucell_reset_after_activation.cl │ │ │ │ │ ├── hswish.cl │ │ │ │ │ ├── instance_normalization_f32.cl │ │ │ │ │ ├── instance_normalization_i32.cl │ │ │ │ │ ├── instance_normalization_u8.cl │ │ │ │ │ ├── l1norm.cl │ │ │ │ │ ├── l2normalizescale_axis0.cl │ │ │ │ │ ├── l2normalizescale_axis1.cl │ │ │ │ │ ├── layer_normalization.cl │ │ │ │ │ ├── log_softmax_axis0.cl │ │ │ │ │ ├── log_softmax_axis1.cl │ │ │ │ │ ├── log_softmax_axis2.cl │ │ │ │ │ ├── log_softmax_exceed_axis0.cl │ │ │ │ │ ├── log_softmax_exceed_axis1.cl │ │ │ │ │ ├── logical_not.cl │ │ │ │ │ ├── logical_ops.cl │ │ │ │ │ ├── lppool.cl │ │ │ │ │ ├── lstmunit_activation_BP_F32.cl │ │ │ │ │ ├── lstmunit_activation_BP_U8.cl │ │ │ │ │ ├── lstmunit_activation_B_F32.cl │ │ │ │ │ ├── lstmunit_activation_B_U8.cl │ │ │ │ │ ├── lstmunit_activation_CBP_F32.cl │ │ │ │ │ ├── lstmunit_activation_CBP_U8.cl │ │ │ │ │ ├── lstmunit_activation_CB_F32.cl │ │ │ │ │ ├── lstmunit_activation_CB_U8.cl │ │ │ │ │ ├── lstmunit_activation_CLP_F32.cl │ │ │ │ │ ├── lstmunit_activation_CLP_U8.cl │ │ │ │ │ ├── lstmunit_activation_CL_F32.cl │ │ │ │ │ ├── lstmunit_activation_CL_U8.cl │ │ │ │ │ ├── lstmunit_activation_CSP_F32.cl │ │ │ │ │ ├── lstmunit_activation_CSP_U8.cl │ │ │ │ │ ├── lstmunit_activation_CS_F32.cl │ │ │ │ │ ├── lstmunit_activation_CS_U8.cl │ │ │ │ │ ├── lstmunit_activation_LP_F32.cl │ │ │ │ │ ├── lstmunit_activation_L_F32.cl │ │ │ │ │ ├── lstmunit_activation_SP_F32.cl │ │ │ │ │ ├── lstmunit_activation_SP_U8.cl │ │ │ │ │ ├── lstmunit_activation_S_F32.cl │ │ │ │ │ ├── lstmunit_activation_S_U8.cl │ │ │ │ │ ├── matrixmul.cl │ │ │ │ │ ├── matrixmul_4x.cl │ │ │ │ │ ├── matrixmul_cross.cl │ │ │ │ │ ├── matrixmul_transA.cl │ │ │ │ │ ├── maximum.cl │ │ │ │ │ ├── maxpool.cl │ │ │ │ │ ├── maxpoolwithargmax.cl │ │ │ │ │ ├── maxpoolwithargmax_2d.cl │ │ │ │ │ ├── maxunpool.cl │ │ │ │ │ ├── minimum.cl │ │ │ │ │ ├── mod.cl │ │ │ │ │ ├── moments_axis0.cl │ │ │ │ │ ├── moments_axis01.cl │ │ │ │ │ ├── moments_axis012.cl │ │ │ │ │ ├── moments_axis1.cl │ │ │ │ │ ├── moments_axis2.cl │ │ │ │ │ ├── nearest_grid_sample.cl │ │ │ │ │ ├── one_hot.cl │ │ │ │ │ ├── poolwithargmax.cl │ │ │ │ │ ├── pow.cl │ │ │ │ │ ├── prelu.cl │ │ │ │ │ ├── random_multinomial.cl │ │ │ │ │ ├── reduceall_internal_axis0.cl │ │ │ │ │ ├── reduceall_internal_axis1.cl │ │ │ │ │ ├── reduceall_internal_axis2.cl │ │ │ │ │ ├── reduceany_internal_axis0.cl │ │ │ │ │ ├── reduceany_internal_axis1.cl │ │ │ │ │ ├── reduceany_internal_axis2.cl │ │ │ │ │ ├── reducemax_internal_axis0.cl │ │ │ │ │ ├── reducemax_internal_axis1.cl │ │ │ │ │ ├── reducemax_internal_axis2.cl │ │ │ │ │ ├── reducemin_internal_axis0.cl │ │ │ │ │ ├── reducemin_internal_axis1.cl │ │ │ │ │ ├── reducemin_internal_axis2.cl │ │ │ │ │ ├── reduceprod_internal_axis0.cl │ │ │ │ │ ├── reduceprod_internal_axis1.cl │ │ │ │ │ ├── reduceprod_internal_axis2.cl │ │ │ │ │ ├── relational_ops.cl │ │ │ │ │ ├── relu_keras.cl │ │ │ │ │ ├── repeat.cl │ │ │ │ │ ├── resize_1d_bilinear.cl │ │ │ │ │ ├── resize_1d_nearest.cl │ │ │ │ │ ├── resize_3d_bilinear.cl │ │ │ │ │ ├── resize_3d_nearest.cl │ │ │ │ │ ├── resize_bilinear.cl │ │ │ │ │ ├── resize_cubic.cl │ │ │ │ │ ├── resize_nearest.cl │ │ │ │ │ ├── reversesequence.cl │ │ │ │ │ ├── roi_align.cl │ │ │ │ │ ├── rope_0.cl │ │ │ │ │ ├── scatter_elements.cl │ │ │ │ │ ├── scatter_elements_add.cl │ │ │ │ │ ├── scatter_elements_mul.cl │ │ │ │ │ ├── scatter_nd.cl │ │ │ │ │ ├── scatter_nd_update.cl │ │ │ │ │ ├── scatter_nd_update_reduction.cl │ │ │ │ │ ├── scatter_nd_update_reduction_conv.cl │ │ │ │ │ ├── select.cl │ │ │ │ │ ├── sequence_mask.cl │ │ │ │ │ ├── signal_frame.cl │ │ │ │ │ ├── slice.cl │ │ │ │ │ ├── space2depth_internal.cl │ │ │ │ │ ├── swish.cl │ │ │ │ │ ├── tile.cl │ │ │ │ │ ├── topk.cl │ │ │ │ │ ├── topk2.cl │ │ │ │ │ ├── topk_odd_even_sort.cl │ │ │ │ │ ├── topk_odd_even_sort2.cl │ │ │ │ │ └── upsample.cl │ │ │ │ └── vx │ │ │ │ │ ├── a_times_b_plus_c.vx │ │ │ │ │ ├── add_mean_std_norm.vx │ │ │ │ │ ├── argmax_axis0.vx │ │ │ │ │ ├── argmax_axis1.vx │ │ │ │ │ ├── argmax_axis2.vx │ │ │ │ │ ├── argmin_axis0.vx │ │ │ │ │ ├── argmin_axis1.vx │ │ │ │ │ ├── argmin_axis2.vx │ │ │ │ │ ├── batchnorm_single.vx │ │ │ │ │ ├── batchnorm_single_f32.vx │ │ │ │ │ ├── bilinear_grid_sample_BF16_to_BF16.vx │ │ │ │ │ ├── bilinear_grid_sample_F16_to_F16.vx │ │ │ │ │ ├── bilinear_grid_sample_F16_to_U8.vx │ │ │ │ │ ├── bilinear_grid_sample_I16_to_I16.vx │ │ │ │ │ ├── bilinear_grid_sample_I8_to_I8.vx │ │ │ │ │ ├── bilinear_grid_sample_U8_to_U8.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_BF16_to_BF16.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_F16_to_F16.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_F16_to_U8.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_I16_to_I16.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_I8_to_I8.vx │ │ │ │ │ ├── bilinear_grid_sample_reflect_U8_to_U8.vx │ │ │ │ │ ├── bucketize.vx │ │ │ │ │ ├── cast.vx │ │ │ │ │ ├── clip_F16.vx │ │ │ │ │ ├── clip_I16.vx │ │ │ │ │ ├── clip_I8.vx │ │ │ │ │ ├── clip_U8.vx │ │ │ │ │ ├── conv1d_ovxlib.vx │ │ │ │ │ ├── conv1d_ovxlib_k1024.vx │ │ │ │ │ ├── crop_and_resize_bilinear.vx │ │ │ │ │ ├── crop_and_resize_nearest_neighbor.vx │ │ │ │ │ ├── cumsum.vx │ │ │ │ │ ├── cumsum_2d.vx │ │ │ │ │ ├── cumsum_array.vx │ │ │ │ │ ├── cumsum_array_2d.vx │ │ │ │ │ ├── cumsum_array_bf16.vx │ │ │ │ │ ├── cumsum_array_ex_rev_axis0.vx │ │ │ │ │ ├── cumsum_array_ex_rev_axis1.vx │ │ │ │ │ ├── cumsum_array_ex_rev_axis2.vx │ │ │ │ │ ├── cumsum_array_f16_u8.vx │ │ │ │ │ ├── cumsum_array_f16_u8_2d.vx │ │ │ │ │ ├── cumsum_bf16.vx │ │ │ │ │ ├── cumsum_ex_rev_axis0.vx │ │ │ │ │ ├── cumsum_ex_rev_axis1.vx │ │ │ │ │ ├── cumsum_ex_rev_axis2.vx │ │ │ │ │ ├── cumsum_f16_u8.vx │ │ │ │ │ ├── custom_letterbox.vx │ │ │ │ │ ├── custom_softmax.vx │ │ │ │ │ ├── custom_warp_affine.vx │ │ │ │ │ ├── custom_warp_affine_2d.vx │ │ │ │ │ ├── custom_warp_affine_optional.vx │ │ │ │ │ ├── custom_warp_affine_rgb.vx │ │ │ │ │ ├── custom_warp_affine_rgb_optional.vx │ │ │ │ │ ├── custom_warp_perspective.vx │ │ │ │ │ ├── depth2space_crd.vx │ │ │ │ │ ├── depthwise_conv1d_src0.vx │ │ │ │ │ ├── depthwise_conv1d_src1.vx │ │ │ │ │ ├── depthwise_conv1d_src2.vx │ │ │ │ │ ├── depthwise_conv1d_src3.vx │ │ │ │ │ ├── detect_post_box.vx │ │ │ │ │ ├── eltwise_unary_2d_0.vx │ │ │ │ │ ├── eltwise_unary_2d_1.vx │ │ │ │ │ ├── eltwise_unary_3d_0.vx │ │ │ │ │ ├── eltwise_unary_3d_1.vx │ │ │ │ │ ├── erf.vx │ │ │ │ │ ├── extra_ending.vx │ │ │ │ │ ├── floordiv.vx │ │ │ │ │ ├── gather.vx │ │ │ │ │ ├── gather_array.vx │ │ │ │ │ ├── gather_batch.vx │ │ │ │ │ ├── gather_elements.vx │ │ │ │ │ ├── gather_mix.vx │ │ │ │ │ ├── gather_mix_batch.vx │ │ │ │ │ ├── gather_nd.vx │ │ │ │ │ ├── gather_nd_2d.vx │ │ │ │ │ ├── gather_nd_2d_mix.vx │ │ │ │ │ ├── gather_nd_3d.vx │ │ │ │ │ ├── gather_nd_3d_mix.vx │ │ │ │ │ ├── gather_nd_batch.vx │ │ │ │ │ ├── gather_nd_batch_2d.vx │ │ │ │ │ ├── gather_nd_mix.vx │ │ │ │ │ ├── get_matrix.vx │ │ │ │ │ ├── group_normalization_0.vx │ │ │ │ │ ├── group_normalization_1.vx │ │ │ │ │ ├── group_normalization_2.vx │ │ │ │ │ ├── grucell_activation.vx │ │ │ │ │ ├── grucell_activation_sma.vx │ │ │ │ │ ├── grucell_activation_z_h.vx │ │ │ │ │ ├── grucell_cdnn_activation.vx │ │ │ │ │ ├── grucell_cdnn_activation_bf16.vx │ │ │ │ │ ├── grucell_cdnn_activation_u8.vx │ │ │ │ │ ├── grucell_h_times_activation_r.vx │ │ │ │ │ ├── grucell_reset_after_activation.vx │ │ │ │ │ ├── hswish.vx │ │ │ │ │ ├── instance_normalization_0.vx │ │ │ │ │ ├── instance_normalization_1.vx │ │ │ │ │ ├── instance_normalization_2.vx │ │ │ │ │ ├── instance_normalization_3.vx │ │ │ │ │ ├── l1norm_axis0.vx │ │ │ │ │ ├── l1norm_axis1.vx │ │ │ │ │ ├── l1norm_axis2.vx │ │ │ │ │ ├── l2normalizescale_axis0.vx │ │ │ │ │ ├── l2normalizescale_axis0_2d.vx │ │ │ │ │ ├── l2normalizescale_axis1.vx │ │ │ │ │ ├── layer_normalization_0.vx │ │ │ │ │ ├── layer_normalization_1.vx │ │ │ │ │ ├── layer_normalization_2.vx │ │ │ │ │ ├── layer_normalization_3.vx │ │ │ │ │ ├── layer_normalization_axis01_0.vx │ │ │ │ │ ├── layer_normalization_axis01_1.vx │ │ │ │ │ ├── layer_normalization_axis01_2.vx │ │ │ │ │ ├── layer_normalization_axis01_3.vx │ │ │ │ │ ├── layer_normalization_axis01_sum.vx │ │ │ │ │ ├── log_softmax_axis0.vx │ │ │ │ │ ├── log_softmax_axis0_BF16.vx │ │ │ │ │ ├── log_softmax_axis1.vx │ │ │ │ │ ├── log_softmax_axis1_BF16.vx │ │ │ │ │ ├── log_softmax_axis2.vx │ │ │ │ │ ├── log_softmax_exceed_axis0.vx │ │ │ │ │ ├── log_softmax_exceed_axis0_BF16.vx │ │ │ │ │ ├── log_softmax_exceed_axis1.vx │ │ │ │ │ ├── log_softmax_exceed_axis1_BF16.vx │ │ │ │ │ ├── logical_not.vx │ │ │ │ │ ├── logical_ops.vx │ │ │ │ │ ├── lstmunit_activation_BP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_BP_F16.vx │ │ │ │ │ ├── lstmunit_activation_BP_U8.vx │ │ │ │ │ ├── lstmunit_activation_B_BF16.vx │ │ │ │ │ ├── lstmunit_activation_B_F16.vx │ │ │ │ │ ├── lstmunit_activation_B_U8.vx │ │ │ │ │ ├── lstmunit_activation_CBP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CBP_F16.vx │ │ │ │ │ ├── lstmunit_activation_CBP_U8.vx │ │ │ │ │ ├── lstmunit_activation_CB_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CB_F16.vx │ │ │ │ │ ├── lstmunit_activation_CB_U8.vx │ │ │ │ │ ├── lstmunit_activation_CLP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CLP_F16.vx │ │ │ │ │ ├── lstmunit_activation_CL_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CL_F16.vx │ │ │ │ │ ├── lstmunit_activation_CSP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CSP_F16.vx │ │ │ │ │ ├── lstmunit_activation_CSP_U8.vx │ │ │ │ │ ├── lstmunit_activation_CS_BF16.vx │ │ │ │ │ ├── lstmunit_activation_CS_F16.vx │ │ │ │ │ ├── lstmunit_activation_CS_U8.vx │ │ │ │ │ ├── lstmunit_activation_LP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_LP_F16.vx │ │ │ │ │ ├── lstmunit_activation_L_BF16.vx │ │ │ │ │ ├── lstmunit_activation_L_F16.vx │ │ │ │ │ ├── lstmunit_activation_SP_BF16.vx │ │ │ │ │ ├── lstmunit_activation_SP_F16.vx │ │ │ │ │ ├── lstmunit_activation_SP_U8.vx │ │ │ │ │ ├── lstmunit_activation_S_BF16.vx │ │ │ │ │ ├── lstmunit_activation_S_F16.vx │ │ │ │ │ ├── lstmunit_activation_S_U8.vx │ │ │ │ │ ├── matrixmul_bf16.vx │ │ │ │ │ ├── matrixmul_cross.vx │ │ │ │ │ ├── matrixmul_cross_i16.vx │ │ │ │ │ ├── matrixmul_f16.vx │ │ │ │ │ ├── matrixmul_f16f16_u8.vx │ │ │ │ │ ├── matrixmul_f16i16_i16.vx │ │ │ │ │ ├── matrixmul_f16u8_f16.vx │ │ │ │ │ ├── matrixmul_f16u8_u8.vx │ │ │ │ │ ├── matrixmul_i16.vx │ │ │ │ │ ├── matrixmul_merge.vx │ │ │ │ │ ├── matrixmul_transA.vx │ │ │ │ │ ├── matrixmul_transB_f16.vx │ │ │ │ │ ├── matrixmul_transB_f16_mix.vx │ │ │ │ │ ├── matrixmul_transB_u8_mix.vx │ │ │ │ │ ├── matrixmul_u8.vx │ │ │ │ │ ├── matrixmul_u8f16_f16.vx │ │ │ │ │ ├── matrixmul_u8f16_u8.vx │ │ │ │ │ ├── matrixmul_u8i16_i16.vx │ │ │ │ │ ├── matrixmul_u8u8_f16.vx │ │ │ │ │ ├── maximum_0.vx │ │ │ │ │ ├── maximum_1.vx │ │ │ │ │ ├── maxpool.vx │ │ │ │ │ ├── minimum_0.vx │ │ │ │ │ ├── minimum_1.vx │ │ │ │ │ ├── mod.vx │ │ │ │ │ ├── moments_axis0.vx │ │ │ │ │ ├── moments_axis01.vx │ │ │ │ │ ├── moments_axis012.vx │ │ │ │ │ ├── moments_axis1.vx │ │ │ │ │ ├── moments_axis2.vx │ │ │ │ │ ├── moments_u8.vx │ │ │ │ │ ├── moments_u8_axis012.vx │ │ │ │ │ ├── nearest_grid_sample_BF16_to_BF16.vx │ │ │ │ │ ├── nearest_grid_sample_F16_to_F16.vx │ │ │ │ │ ├── nearest_grid_sample_F16_to_U8.vx │ │ │ │ │ ├── nearest_grid_sample_I16_to_I16.vx │ │ │ │ │ ├── nearest_grid_sample_I8_to_I8.vx │ │ │ │ │ ├── nearest_grid_sample_U8_to_U8.vx │ │ │ │ │ ├── one_hot.vx │ │ │ │ │ ├── poolwithargmax_F16.vx │ │ │ │ │ ├── poolwithargmax_I16.vx │ │ │ │ │ ├── poolwithargmax_I8.vx │ │ │ │ │ ├── poolwithargmax_U8.vx │ │ │ │ │ ├── pow.vx │ │ │ │ │ ├── pre_process_bgra.vx │ │ │ │ │ ├── pre_process_gray.vx │ │ │ │ │ ├── pre_process_gray_2.vx │ │ │ │ │ ├── pre_process_gray_copy.vx │ │ │ │ │ ├── pre_process_nv12_copy.vx │ │ │ │ │ ├── pre_process_nv12_rggb_copy.vx │ │ │ │ │ ├── pre_process_nv12_rggb_scale.vx │ │ │ │ │ ├── pre_process_nv12_scale.vx │ │ │ │ │ ├── pre_process_rgb.vx │ │ │ │ │ ├── pre_process_rgb888_planar_0.vx │ │ │ │ │ ├── pre_process_rgb888_planar_1.vx │ │ │ │ │ ├── pre_process_rgb888_planar_2.vx │ │ │ │ │ ├── pre_process_rgb888_planar_nhwc_0.vx │ │ │ │ │ ├── pre_process_rgb888_planar_nhwc_1.vx │ │ │ │ │ ├── pre_process_rgb888_planar_nhwc_2.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_0.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_1.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_2.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_nhwc_0.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_nhwc_1.vx │ │ │ │ │ ├── pre_process_rgb888_planar_sep_nhwc_2.vx │ │ │ │ │ ├── pre_process_rgb_copy.vx │ │ │ │ │ ├── pre_process_yuv420_copy.vx │ │ │ │ │ ├── pre_process_yuv420_scale_0.vx │ │ │ │ │ ├── pre_process_yuv420_scale_1.vx │ │ │ │ │ ├── pre_process_yuv422_copy.vx │ │ │ │ │ ├── pre_process_yuv422_scale.vx │ │ │ │ │ ├── pre_process_yuv444_copy_u8.vx │ │ │ │ │ ├── pre_process_yuv444_scale.vx │ │ │ │ │ ├── pre_process_yuv444_scale_fp16.vx │ │ │ │ │ ├── prelu.vx │ │ │ │ │ ├── prelu_BF16.vx │ │ │ │ │ ├── random_multinomial.vx │ │ │ │ │ ├── reduceall_internal_axis0.vx │ │ │ │ │ ├── reduceall_internal_axis1.vx │ │ │ │ │ ├── reduceall_internal_axis2.vx │ │ │ │ │ ├── reduceany_internal_axis0.vx │ │ │ │ │ ├── reduceany_internal_axis1.vx │ │ │ │ │ ├── reduceany_internal_axis2.vx │ │ │ │ │ ├── reducemax_internal_axis0.vx │ │ │ │ │ ├── reducemax_internal_axis1.vx │ │ │ │ │ ├── reducemax_internal_axis2.vx │ │ │ │ │ ├── reducemin_internal_axis0.vx │ │ │ │ │ ├── reducemin_internal_axis1.vx │ │ │ │ │ ├── reducemin_internal_axis2.vx │ │ │ │ │ ├── reduceprod_internal_axis0.vx │ │ │ │ │ ├── reduceprod_internal_axis1.vx │ │ │ │ │ ├── reduceprod_internal_axis2.vx │ │ │ │ │ ├── relational_ops_2d.vx │ │ │ │ │ ├── relational_ops_3d.vx │ │ │ │ │ ├── relu_keras.vx │ │ │ │ │ ├── repeat.vx │ │ │ │ │ ├── repeat_axis1.vx │ │ │ │ │ ├── resize_1d_bilinear_BF16.vx │ │ │ │ │ ├── resize_1d_bilinear_DOWN_NX.vx │ │ │ │ │ ├── resize_1d_bilinear_F16.vx │ │ │ │ │ ├── resize_1d_bilinear_I16.vx │ │ │ │ │ ├── resize_1d_bilinear_I8.vx │ │ │ │ │ ├── resize_1d_bilinear_U8.vx │ │ │ │ │ ├── resize_1d_bilinear_U8_opt.vx │ │ │ │ │ ├── resize_1d_bilinear_UP_NX.vx │ │ │ │ │ ├── resize_1d_nearest.vx │ │ │ │ │ ├── resize_bilinear_BF16.vx │ │ │ │ │ ├── resize_bilinear_F16.vx │ │ │ │ │ ├── resize_bilinear_I16.vx │ │ │ │ │ ├── resize_bilinear_I8.vx │ │ │ │ │ ├── resize_bilinear_U16.vx │ │ │ │ │ ├── resize_bilinear_U8.vx │ │ │ │ │ ├── resize_bilinear_U8_half_pixel_centers_1.vx │ │ │ │ │ ├── resize_bilinear_U8_half_pixel_centers_2.vx │ │ │ │ │ ├── resize_bilinear_U8_half_pixel_centers_3.vx │ │ │ │ │ ├── resize_bilinear_U8_half_pixel_centers_4.vx │ │ │ │ │ ├── resize_bilinear_U8_half_pixel_centers_5.vx │ │ │ │ │ ├── resize_bilinear_U8_opt.vx │ │ │ │ │ ├── resize_bilinear_align_corners.vx │ │ │ │ │ ├── resize_bilinear_nhwc.vx │ │ │ │ │ ├── resize_bilinear_nhwc_bound.vx │ │ │ │ │ ├── resize_cubic.vx │ │ │ │ │ ├── resize_nearest.vx │ │ │ │ │ ├── rope_0.vx │ │ │ │ │ ├── rope_1.vx │ │ │ │ │ ├── rope_2.vx │ │ │ │ │ ├── rope_3.vx │ │ │ │ │ ├── scatter_nd.vx │ │ │ │ │ ├── scatter_nd_big.vx │ │ │ │ │ ├── scatter_nd_update.vx │ │ │ │ │ ├── scatter_nd_update_atom.vx │ │ │ │ │ ├── scatter_nd_update_big.vx │ │ │ │ │ ├── scatter_nd_update_fp.vx │ │ │ │ │ ├── scatter_nd_update_qint.vx │ │ │ │ │ ├── scatter_nd_update_reduction.vx │ │ │ │ │ ├── scatter_nd_update_reduction_conv.vx │ │ │ │ │ ├── scatter_nd_update_special.vx │ │ │ │ │ ├── select.vx │ │ │ │ │ ├── sequence_mask.vx │ │ │ │ │ ├── signal_frame.vx │ │ │ │ │ ├── slice.vx │ │ │ │ │ ├── space2depth_internal.vx │ │ │ │ │ ├── swish.vx │ │ │ │ │ ├── tensorstackconcat.vx │ │ │ │ │ ├── tile.vx │ │ │ │ │ ├── tile_mix.vx │ │ │ │ │ ├── tiny_yolov4_postprocess_box.vx │ │ │ │ │ ├── tiny_yolov4_postprocess_confidence.vx │ │ │ │ │ ├── upsample_F16.vx │ │ │ │ │ ├── upsample_I16.vx │ │ │ │ │ ├── upsample_I8.vx │ │ │ │ │ ├── upsample_U8.vx │ │ │ │ │ ├── upsamplescale.vx │ │ │ │ │ ├── upsamplescale_k2.vx │ │ │ │ │ ├── vsi_nn_kernel_header.vx │ │ │ │ │ └── warp_affine.vx │ │ │ ├── vsi_nn_libnnext_resource.c │ │ │ └── vsi_nn_vxkernel.c │ │ ├── ops │ │ │ ├── vsi_nn_op_a_times_b_plus_c.c │ │ │ ├── vsi_nn_op_abs.c │ │ │ ├── vsi_nn_op_addn.c │ │ │ ├── vsi_nn_op_argmaxmin.c │ │ │ ├── vsi_nn_op_avg_pool3d.c │ │ │ ├── vsi_nn_op_axis_aligned_bbox_transform.c │ │ │ ├── vsi_nn_op_batch2space.c │ │ │ ├── vsi_nn_op_batch_norm.c │ │ │ ├── vsi_nn_op_batchnorm_single.c │ │ │ ├── vsi_nn_op_bidirectional_sequence_lstm.c │ │ │ ├── vsi_nn_op_bidirectional_sequence_rnn.c │ │ │ ├── vsi_nn_op_bitcast.c │ │ │ ├── vsi_nn_op_box_with_nms_limit.c │ │ │ ├── vsi_nn_op_bucketize.c │ │ │ ├── vsi_nn_op_cast.c │ │ │ ├── vsi_nn_op_ceil.c │ │ │ ├── vsi_nn_op_clip.c │ │ │ ├── vsi_nn_op_col2im.c │ │ │ ├── vsi_nn_op_common.c │ │ │ ├── vsi_nn_op_concat.c │ │ │ ├── vsi_nn_op_concatshift.c │ │ │ ├── vsi_nn_op_conv1d.c │ │ │ ├── vsi_nn_op_conv2d.c │ │ │ ├── vsi_nn_op_conv2d_lstm.c │ │ │ ├── vsi_nn_op_conv2d_lstm_cell.c │ │ │ ├── vsi_nn_op_conv3d.c │ │ │ ├── vsi_nn_op_conv_relu.c │ │ │ ├── vsi_nn_op_conv_relu_pool.c │ │ │ ├── vsi_nn_op_crop.c │ │ │ ├── vsi_nn_op_crop_and_resize.c │ │ │ ├── vsi_nn_op_cumsum.c │ │ │ ├── vsi_nn_op_dataconvert.c │ │ │ ├── vsi_nn_op_deconv3d.c │ │ │ ├── vsi_nn_op_deconvolution.c │ │ │ ├── vsi_nn_op_deconvolution1d.c │ │ │ ├── vsi_nn_op_depth2space.c │ │ │ ├── vsi_nn_op_depth2space_internal.c │ │ │ ├── vsi_nn_op_depthwise_conv1d.c │ │ │ ├── vsi_nn_op_detection_postprocess.c │ │ │ ├── vsi_nn_op_dropout.c │ │ │ ├── vsi_nn_op_eltwise.c │ │ │ ├── vsi_nn_op_eltwise_unary.c │ │ │ ├── vsi_nn_op_embedding_lookup.c │ │ │ ├── vsi_nn_op_erf.c │ │ │ ├── vsi_nn_op_expand_broadcast.c │ │ │ ├── vsi_nn_op_extra_ending.c │ │ │ ├── vsi_nn_op_floor.c │ │ │ ├── vsi_nn_op_floordiv.c │ │ │ ├── vsi_nn_op_fullconnect.c │ │ │ ├── vsi_nn_op_fullconnect2.c │ │ │ ├── vsi_nn_op_fullconnect_relu.c │ │ │ ├── vsi_nn_op_gather.c │ │ │ ├── vsi_nn_op_gather_elements.c │ │ │ ├── vsi_nn_op_gather_nd.c │ │ │ ├── vsi_nn_op_generate_proposals.c │ │ │ ├── vsi_nn_op_globallppool.c │ │ │ ├── vsi_nn_op_grid_sample.c │ │ │ ├── vsi_nn_op_grouped_conv1d.c │ │ │ ├── vsi_nn_op_grouped_conv2d.c │ │ │ ├── vsi_nn_op_grouped_conv3d.c │ │ │ ├── vsi_nn_op_groupnormalize.c │ │ │ ├── vsi_nn_op_gru.c │ │ │ ├── vsi_nn_op_gru_ovxlib.c │ │ │ ├── vsi_nn_op_grucell.c │ │ │ ├── vsi_nn_op_grucell_activation.c │ │ │ ├── vsi_nn_op_grucell_activation_internal.c │ │ │ ├── vsi_nn_op_grucell_activation_internal_sma.c │ │ │ ├── vsi_nn_op_grucell_activation_z_h.c │ │ │ ├── vsi_nn_op_grucell_h_times_activation_r.c │ │ │ ├── vsi_nn_op_grucell_ovxlib.c │ │ │ ├── vsi_nn_op_hashtable_lookup.c │ │ │ ├── vsi_nn_op_heatmap_max_keypoint.c │ │ │ ├── vsi_nn_op_imageprocess.c │ │ │ ├── vsi_nn_op_instancenormalize.c │ │ │ ├── vsi_nn_op_interp.c │ │ │ ├── vsi_nn_op_l1_layer_norm.c │ │ │ ├── vsi_nn_op_l2_normalize.c │ │ │ ├── vsi_nn_op_l2normalizescale.c │ │ │ ├── vsi_nn_op_layernormalize.c │ │ │ ├── vsi_nn_op_leaky_relu.c │ │ │ ├── vsi_nn_op_linear.c │ │ │ ├── vsi_nn_op_log_softmax.c │ │ │ ├── vsi_nn_op_logical_not.c │ │ │ ├── vsi_nn_op_logical_ops.c │ │ │ ├── vsi_nn_op_lpnorm.c │ │ │ ├── vsi_nn_op_lppool.c │ │ │ ├── vsi_nn_op_lrn.c │ │ │ ├── vsi_nn_op_lrn2.c │ │ │ ├── vsi_nn_op_lsh_projection.c │ │ │ ├── vsi_nn_op_lstm.c │ │ │ ├── vsi_nn_op_lstm_ovxlib.c │ │ │ ├── vsi_nn_op_lstmunit.c │ │ │ ├── vsi_nn_op_lstmunit_activation.c │ │ │ ├── vsi_nn_op_lstmunit_ovxlib.c │ │ │ ├── vsi_nn_op_matrixmul.c │ │ │ ├── vsi_nn_op_max_pool3d.c │ │ │ ├── vsi_nn_op_maxpoolwithargmax.c │ │ │ ├── vsi_nn_op_maxunpool.c │ │ │ ├── vsi_nn_op_mod.c │ │ │ ├── vsi_nn_op_moments.c │ │ │ ├── vsi_nn_op_nbg.c │ │ │ ├── vsi_nn_op_nms.c │ │ │ ├── vsi_nn_op_noop.c │ │ │ ├── vsi_nn_op_one_hot.c │ │ │ ├── vsi_nn_op_pad.c │ │ │ ├── vsi_nn_op_pad2.c │ │ │ ├── vsi_nn_op_permute.c │ │ │ ├── vsi_nn_op_pool.c │ │ │ ├── vsi_nn_op_poolwithargmax.c │ │ │ ├── vsi_nn_op_post_process.c │ │ │ ├── vsi_nn_op_pre_process.c │ │ │ ├── vsi_nn_op_pre_process_bgra.c │ │ │ ├── vsi_nn_op_pre_process_gray.c │ │ │ ├── vsi_nn_op_pre_process_nv12.c │ │ │ ├── vsi_nn_op_pre_process_rgb.c │ │ │ ├── vsi_nn_op_pre_process_rgb888_planar.c │ │ │ ├── vsi_nn_op_pre_process_tensor.c │ │ │ ├── vsi_nn_op_pre_process_yuv420.c │ │ │ ├── vsi_nn_op_pre_process_yuv422.c │ │ │ ├── vsi_nn_op_pre_process_yuv444.c │ │ │ ├── vsi_nn_op_prelu.c │ │ │ ├── vsi_nn_op_proposal.c │ │ │ ├── vsi_nn_op_quantized_16bit_lstm.c │ │ │ ├── vsi_nn_op_random_multinomial.c │ │ │ ├── vsi_nn_op_reduce.c │ │ │ ├── vsi_nn_op_reduce_internal.c │ │ │ ├── vsi_nn_op_reduce_mean_internal.c │ │ │ ├── vsi_nn_op_reducel2.c │ │ │ ├── vsi_nn_op_reducesum_internal.c │ │ │ ├── vsi_nn_op_relational_ops.c │ │ │ ├── vsi_nn_op_relu.c │ │ │ ├── vsi_nn_op_relu1.c │ │ │ ├── vsi_nn_op_relu6.c │ │ │ ├── vsi_nn_op_relu_keras.c │ │ │ ├── vsi_nn_op_relu_keras_internal.c │ │ │ ├── vsi_nn_op_relun.c │ │ │ ├── vsi_nn_op_reorg.c │ │ │ ├── vsi_nn_op_repeat.c │ │ │ ├── vsi_nn_op_reshape.c │ │ │ ├── vsi_nn_op_reshape2.c │ │ │ ├── vsi_nn_op_resize.c │ │ │ ├── vsi_nn_op_resize_1d.c │ │ │ ├── vsi_nn_op_resize_1d_bilinear_internal.c │ │ │ ├── vsi_nn_op_resize_1d_nearest_internal.c │ │ │ ├── vsi_nn_op_resize_3d.c │ │ │ ├── vsi_nn_op_resize_internal.c │ │ │ ├── vsi_nn_op_resize_nearest_internal.c │ │ │ ├── vsi_nn_op_reverse.c │ │ │ ├── vsi_nn_op_reversesequence.c │ │ │ ├── vsi_nn_op_rmsnorm.c │ │ │ ├── vsi_nn_op_rnn.c │ │ │ ├── vsi_nn_op_rnncell_ovxlib.c │ │ │ ├── vsi_nn_op_roi_align.c │ │ │ ├── vsi_nn_op_roi_pool.c │ │ │ ├── vsi_nn_op_rope.c │ │ │ ├── vsi_nn_op_rsqrt.c │ │ │ ├── vsi_nn_op_scale.c │ │ │ ├── vsi_nn_op_scatter_elements.c │ │ │ ├── vsi_nn_op_scatter_nd.c │ │ │ ├── vsi_nn_op_scatter_nd_update.c │ │ │ ├── vsi_nn_op_select.c │ │ │ ├── vsi_nn_op_sequence_mask.c │ │ │ ├── vsi_nn_op_shape.c │ │ │ ├── vsi_nn_op_shufflechannel.c │ │ │ ├── vsi_nn_op_sigmoid.c │ │ │ ├── vsi_nn_op_signal_frame.c │ │ │ ├── vsi_nn_op_slice.c │ │ │ ├── vsi_nn_op_softmax.c │ │ │ ├── vsi_nn_op_softmax_internal.c │ │ │ ├── vsi_nn_op_softrelu.c │ │ │ ├── vsi_nn_op_space2batch.c │ │ │ ├── vsi_nn_op_space2depth.c │ │ │ ├── vsi_nn_op_space2depth_internal.c │ │ │ ├── vsi_nn_op_spatial_transformer.c │ │ │ ├── vsi_nn_op_split.c │ │ │ ├── vsi_nn_op_sqrt.c │ │ │ ├── vsi_nn_op_square.c │ │ │ ├── vsi_nn_op_squeeze.c │ │ │ ├── vsi_nn_op_stack.c │ │ │ ├── vsi_nn_op_strided_slice.c │ │ │ ├── vsi_nn_op_svdf.c │ │ │ ├── vsi_nn_op_swish.c │ │ │ ├── vsi_nn_op_sync_host.c │ │ │ ├── vsi_nn_op_tanh.c │ │ │ ├── vsi_nn_op_tensor_add_mean_stddev_norm.c │ │ │ ├── vsi_nn_op_tensorstackconcat.c │ │ │ ├── vsi_nn_op_tile.c │ │ │ ├── vsi_nn_op_topk.c │ │ │ ├── vsi_nn_op_unidirectional_sequence_rnn.c │ │ │ ├── vsi_nn_op_unstack.c │ │ │ ├── vsi_nn_op_upsample.c │ │ │ ├── vsi_nn_op_upsamplescale.c │ │ │ └── vsi_nn_op_variable.c │ │ ├── post │ │ │ ├── vsi_nn_post_cmupose.c │ │ │ └── vsi_nn_post_fasterrcnn.c │ │ ├── quantization │ │ │ ├── vsi_nn_asymmetric_affine.c │ │ │ ├── vsi_nn_dynamic_fixed_point.c │ │ │ └── vsi_nn_perchannel_symmetric_affine.c │ │ ├── utils │ │ │ ├── vsi_nn_binary_tree.c │ │ │ ├── vsi_nn_code_generator.c │ │ │ ├── vsi_nn_constraint_check.c │ │ │ ├── vsi_nn_dlfcn.c │ │ │ ├── vsi_nn_dtype.c │ │ │ ├── vsi_nn_dtype_util.c │ │ │ ├── vsi_nn_hashmap.c │ │ │ ├── vsi_nn_limits.c │ │ │ ├── vsi_nn_link_list.c │ │ │ ├── vsi_nn_map.c │ │ │ ├── vsi_nn_math.c │ │ │ ├── vsi_nn_shape_util.c │ │ │ ├── vsi_nn_tensor_op.c │ │ │ └── vsi_nn_util.c │ │ ├── vip │ │ │ ├── virtual_device.cpp │ │ │ └── virtual_device_private.h │ │ ├── vsi_nn_client_op.c │ │ ├── vsi_nn_context.c │ │ ├── vsi_nn_daemon.c │ │ ├── vsi_nn_graph.c │ │ ├── vsi_nn_graph_optimization.c │ │ ├── vsi_nn_internal_node.c │ │ ├── vsi_nn_kernel_prv.h │ │ ├── vsi_nn_log.c │ │ ├── vsi_nn_node.c │ │ ├── vsi_nn_node_attr_template.c │ │ ├── vsi_nn_ops.c │ │ ├── vsi_nn_pre_post_process.c │ │ ├── vsi_nn_rnn.c │ │ ├── vsi_nn_rnn_helper.c │ │ ├── vsi_nn_tensor.c │ │ ├── vsi_nn_tensor_util_prv.h │ │ ├── vsi_nn_types_prv.h │ │ └── vsi_nn_version.c │ └── tim_internal.cmake │ ├── op_impl.cc │ ├── op_impl.h │ ├── operation.cc │ ├── ops │ ├── README.md │ ├── activations.cc │ ├── activations_test.cc │ ├── addn.cc │ ├── addn_test.cc │ ├── arg.cc │ ├── arg_test.cc │ ├── avg_pool_test.cc │ ├── batch2space.cc │ ├── batch2space_test.cc │ ├── batchnorm.cc │ ├── batchnorm_test.cc │ ├── bidirectional_sequence_lstm.cc │ ├── bidirectional_sequence_lstm_test.cc │ ├── bidirectional_sequence_rnn.cc │ ├── bidirectional_sequence_rnn_ext.cc │ ├── bidirectional_sequence_rnn_ext_test.cc │ ├── bidirectional_sequence_rnn_test.cc │ ├── broadcast.cc │ ├── broadcast_test.cc │ ├── clip.cc │ ├── concat.cc │ ├── conv1d.cc │ ├── conv1d_test.cc │ ├── conv2d.cc │ ├── conv2d_test.cc │ ├── conv3d.cc │ ├── conv3d_test.cc │ ├── cumsum.cc │ ├── cumsum_test.cc │ ├── custom_base.cc │ ├── deconv.cc │ ├── deconv1d.cc │ ├── deconv1d_test.cc │ ├── deconv2d_test.cc │ ├── depth2space.cc │ ├── depth2space_test.cc │ ├── depthwiseConv_test.cc │ ├── dropout.cc │ ├── elementwise.cc │ ├── elementwise_test.cc │ ├── embedding_lookup.cc │ ├── embedding_lookup_test.cc │ ├── erf.cc │ ├── erf_test.cc │ ├── fullyconnected.cc │ ├── fullyconnected_test.cc │ ├── gather.cc │ ├── gather_elements.cc │ ├── gather_elements_test.cc │ ├── gather_test.cc │ ├── gathernd.cc │ ├── groupedconv1d.cc │ ├── groupedconv1d_test.cc │ ├── groupedconv2d.cc │ ├── groupedconv2d_test.cc │ ├── grucell.cc │ ├── grucell_test.cc │ ├── hashtable_lookup.cc │ ├── hashtable_lookup_test.cc │ ├── instancenormalization.cc │ ├── instancenormalization_test.cc │ ├── l2normalization.cc │ ├── l2normalization_test.cc │ ├── layernormalization.cc │ ├── layernormalization_test.cc │ ├── localresponsenormalization.cc │ ├── localresponsenormalization_test.cc │ ├── logical.cc │ ├── logsoftmax.cc │ ├── logsoftmax_test.cc │ ├── matmul.cc │ ├── matmul_test.cc │ ├── max_pool3d.cc │ ├── max_pool3d_test.cc │ ├── max_pool_test.cc │ ├── maxpoolgrad.cc │ ├── maxpoolgrad_test.cc │ ├── maxpoolwithargmax.cc │ ├── maxpoolwithargmax2.cc │ ├── maxpoolwithargmax2_test.cc │ ├── maxpoolwithargmax_test.cc │ ├── maxunpool2d.cc │ ├── maxunpool2d_test.cc │ ├── mod.cc │ ├── mod_test.cc │ ├── moments.cc │ ├── moments_test.cc │ ├── nbg.cc │ ├── onehot.cc │ ├── onehot_test.cc │ ├── pad.cc │ ├── pad_test.cc │ ├── pad_v2.cc │ ├── pool1d.cc │ ├── pool2d.cc │ ├── reduce.cc │ ├── reduce_test.cc │ ├── relational_operations.cc │ ├── relational_operations_test.cc │ ├── reorg.cc │ ├── reorg_test.cc │ ├── reshape.cc │ ├── reshape_test.cc │ ├── resize.cc │ ├── resize1d.cc │ ├── resize1d_test.cc │ ├── resize_bilinear_test.cc │ ├── reverse.cc │ ├── rnn_cell.cc │ ├── rnn_cell_test.cc │ ├── roi_align.cc │ ├── roi_align_test.cc │ ├── roi_pool.cc │ ├── roi_pool_test.cc │ ├── scatternd.cc │ ├── scatternd_onnx_v16.cc │ ├── scatternd_onnx_v16_test.cc │ ├── scatternd_test.cc │ ├── select.cc │ ├── shuffle_channel.cc │ ├── shuffle_channel_test.cc │ ├── signal_frame.cc │ ├── signal_frame_test.cc │ ├── simple_operations.cc │ ├── simple_operations_test.cc │ ├── slice.cc │ ├── slice_test.cc │ ├── softmax.cc │ ├── softmax_test.cc │ ├── space2batch.cc │ ├── space2batch_test.cc │ ├── space2depth.cc │ ├── spatial_transformer.cc │ ├── spatial_transformer_test.cc │ ├── split.cc │ ├── squeeze.cc │ ├── stack.cc │ ├── stack_test.cc │ ├── stridedslice.cc │ ├── stridedslice_test.cc │ ├── svdf.cc │ ├── svdf_test.cc │ ├── tile.cc │ ├── tile_test.cc │ ├── tiny_yolov4_postprocess.cc │ ├── topk.cc │ ├── topk_test.cc │ ├── transpose.cc │ ├── transposeConv_test.cc │ ├── transpose_test.cc │ ├── unidirectional_sequence_gru.cc │ ├── unidirectional_sequence_gru_test.cc │ ├── unidirectional_sequence_lstm.cc │ ├── unidirectional_sequence_lstm_test.cc │ ├── unidirectional_sequence_rnn.cc │ ├── unidirectional_sequence_rnn_ext.cc │ ├── unidirectional_sequence_rnn_ext_test.cc │ ├── unidirectional_sequence_rnn_test.cc │ ├── unstack.cc │ └── unstack_test.cc │ ├── platform │ ├── grpc │ │ ├── README.md │ │ ├── grpc_platform.proto │ │ ├── grpc_platform_client.cc │ │ ├── grpc_platform_client.h │ │ ├── grpc_platform_server.cc │ │ └── grpc_remote.cc │ ├── lite │ │ ├── lite_native.cc │ │ └── lite_native_private.h │ ├── native.cc │ └── native_private.h │ ├── tensor.cc │ ├── tensor_private.h │ ├── test_utils.h │ ├── type_utils.cc │ └── type_utils.h ├── third_party └── half │ ├── ChangeLog.txt │ ├── ChangeLog.txt.license │ ├── LICENSE.spdx │ ├── LICENSE.txt │ ├── README.txt │ ├── README.txt.license │ └── half.hpp └── toolchains ├── BUILD.bazel ├── WORKSPACE ├── cc_toolchain_base.bzl ├── gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu ├── BUILD.bazel ├── bin │ ├── BUILD.bazel │ ├── wrapper-ar │ ├── wrapper-as │ ├── wrapper-cpp │ ├── wrapper-gcc │ ├── wrapper-gcov │ ├── wrapper-ld │ ├── wrapper-nm │ ├── wrapper-objcopy │ ├── wrapper-objdump │ └── wrapper-strip ├── cc_toolchain_config.bzl └── toolchain.BUILD └── toolchains.bzl /.bazelrc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.bazelrc -------------------------------------------------------------------------------- /.bazelversion: -------------------------------------------------------------------------------- 1 | 3.1.0 2 | -------------------------------------------------------------------------------- /.clang-format: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.clang-format -------------------------------------------------------------------------------- /.github/workflows/bazel_x86_vsim_unit_test.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.github/workflows/bazel_x86_vsim_unit_test.yml -------------------------------------------------------------------------------- /.github/workflows/cmake_x86_vsim.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.github/workflows/cmake_x86_vsim.yml -------------------------------------------------------------------------------- /.github/workflows/self-hosted.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.github/workflows/self-hosted.yml -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/.gitignore -------------------------------------------------------------------------------- /Android.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/Android.mk -------------------------------------------------------------------------------- /BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/BUILD -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/CMakeLists.txt -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/README.md -------------------------------------------------------------------------------- /VERSION: -------------------------------------------------------------------------------- 1 | 1.2.22 2 | -------------------------------------------------------------------------------- /WORKSPACE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/WORKSPACE -------------------------------------------------------------------------------- /cmake/A311D.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/A311D.cmake -------------------------------------------------------------------------------- /cmake/S905D3.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/S905D3.cmake -------------------------------------------------------------------------------- /cmake/X86_64_linux.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/X86_64_linux.cmake -------------------------------------------------------------------------------- /cmake/YOCTO.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/YOCTO.cmake -------------------------------------------------------------------------------- /cmake/gRPC.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/gRPC.cmake -------------------------------------------------------------------------------- /cmake/local_sdk.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/local_sdk.cmake -------------------------------------------------------------------------------- /cmake/openssl.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/openssl.cmake -------------------------------------------------------------------------------- /cmake/openssl.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/openssl.patch -------------------------------------------------------------------------------- /cmake/vim3_android.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/cmake/vim3_android.cmake -------------------------------------------------------------------------------- /docs/Operators.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/Operators.md -------------------------------------------------------------------------------- /docs/Operators.md.template: -------------------------------------------------------------------------------- 1 | # Operators 2 | 3 | {DOCS} 4 | -------------------------------------------------------------------------------- /docs/Programming_Guide.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/Programming_Guide.md -------------------------------------------------------------------------------- /docs/customized_op.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/customized_op.md -------------------------------------------------------------------------------- /docs/extend_tim-vx-operators.uxf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/extend_tim-vx-operators.uxf -------------------------------------------------------------------------------- /docs/gen_docs.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/gen_docs.py -------------------------------------------------------------------------------- /docs/image/architecture.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/image/architecture.png -------------------------------------------------------------------------------- /docs/image/extend.tim-vx.operators.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/image/extend.tim-vx.operators.png -------------------------------------------------------------------------------- /docs/image/graph_lifecycle.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/image/graph_lifecycle.png -------------------------------------------------------------------------------- /docs/image/timvx_overview.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/image/timvx_overview.drawio -------------------------------------------------------------------------------- /docs/image/timvx_overview.svg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/image/timvx_overview.svg -------------------------------------------------------------------------------- /docs/openssl_build.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/docs/openssl_build.md -------------------------------------------------------------------------------- /gen_vsi_feat_ops_def.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/gen_vsi_feat_ops_def.sh -------------------------------------------------------------------------------- /include/tim/experimental/trace/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/README.md -------------------------------------------------------------------------------- /include/tim/experimental/trace/replayer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/replayer.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/trace_tvx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/trace_tvx.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tracer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tracer.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tvx/context.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tvx/context.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tvx/graph.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tvx/graph.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tvx/ops.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tvx/ops.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tvx/tensor.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tvx/tensor.h -------------------------------------------------------------------------------- /include/tim/experimental/trace/tvx/types.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/experimental/trace/tvx/types.h -------------------------------------------------------------------------------- /include/tim/lite/execution.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/lite/execution.h -------------------------------------------------------------------------------- /include/tim/lite/handle.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/lite/handle.h -------------------------------------------------------------------------------- /include/tim/transform/layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/transform/layout_inference.h -------------------------------------------------------------------------------- /include/tim/utils/nbg_parser/gc_vip_nbg_format.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/utils/nbg_parser/gc_vip_nbg_format.h -------------------------------------------------------------------------------- /include/tim/utils/nbg_parser/nbg_parser.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/utils/nbg_parser/nbg_parser.h -------------------------------------------------------------------------------- /include/tim/utils/nbg_parser/nbg_parser_impl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/utils/nbg_parser/nbg_parser_impl.h -------------------------------------------------------------------------------- /include/tim/utils/nbg_parser/nbg_parser_version.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/utils/nbg_parser/nbg_parser_version.h -------------------------------------------------------------------------------- /include/tim/vx/builtin_op.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/builtin_op.h -------------------------------------------------------------------------------- /include/tim/vx/compile_option.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/compile_option.h -------------------------------------------------------------------------------- /include/tim/vx/context.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/context.h -------------------------------------------------------------------------------- /include/tim/vx/graph.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/graph.h -------------------------------------------------------------------------------- /include/tim/vx/operation.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/operation.h -------------------------------------------------------------------------------- /include/tim/vx/ops.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops.h -------------------------------------------------------------------------------- /include/tim/vx/ops/BidirectionalSequenceLstm.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/BidirectionalSequenceLstm.json -------------------------------------------------------------------------------- /include/tim/vx/ops/BidirectionalSequenceRNN.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/BidirectionalSequenceRNN.json -------------------------------------------------------------------------------- /include/tim/vx/ops/HashtableLookup.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/HashtableLookup.json -------------------------------------------------------------------------------- /include/tim/vx/ops/L2Normalization.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/L2Normalization.json -------------------------------------------------------------------------------- /include/tim/vx/ops/LayerNormalization.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/LayerNormalization.json -------------------------------------------------------------------------------- /include/tim/vx/ops/MaxpoolWithArgmax.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/MaxpoolWithArgmax.json -------------------------------------------------------------------------------- /include/tim/vx/ops/MaxpoolWithArgmax2.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/MaxpoolWithArgmax2.json -------------------------------------------------------------------------------- /include/tim/vx/ops/abs.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/abs.json -------------------------------------------------------------------------------- /include/tim/vx/ops/activations.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/activations.h -------------------------------------------------------------------------------- /include/tim/vx/ops/add.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/add.json -------------------------------------------------------------------------------- /include/tim/vx/ops/addn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/addn.h -------------------------------------------------------------------------------- /include/tim/vx/ops/addn.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/addn.json -------------------------------------------------------------------------------- /include/tim/vx/ops/and.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/and.json -------------------------------------------------------------------------------- /include/tim/vx/ops/arg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/arg.h -------------------------------------------------------------------------------- /include/tim/vx/ops/argmax.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/argmax.json -------------------------------------------------------------------------------- /include/tim/vx/ops/argmin.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/argmin.json -------------------------------------------------------------------------------- /include/tim/vx/ops/batch2space.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/batch2space.h -------------------------------------------------------------------------------- /include/tim/vx/ops/batch2space.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/batch2space.json -------------------------------------------------------------------------------- /include/tim/vx/ops/batchnorm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/batchnorm.h -------------------------------------------------------------------------------- /include/tim/vx/ops/batchnorm.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/batchnorm.json -------------------------------------------------------------------------------- /include/tim/vx/ops/bidirectional_sequence_lstm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/bidirectional_sequence_lstm.h -------------------------------------------------------------------------------- /include/tim/vx/ops/bidirectional_sequence_rnn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/bidirectional_sequence_rnn.h -------------------------------------------------------------------------------- /include/tim/vx/ops/broadcast.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/broadcast.h -------------------------------------------------------------------------------- /include/tim/vx/ops/broadcast.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/broadcast.json -------------------------------------------------------------------------------- /include/tim/vx/ops/cast.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/cast.json -------------------------------------------------------------------------------- /include/tim/vx/ops/ceil.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/ceil.json -------------------------------------------------------------------------------- /include/tim/vx/ops/celu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/celu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/clip.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/clip.h -------------------------------------------------------------------------------- /include/tim/vx/ops/clip.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/clip.json -------------------------------------------------------------------------------- /include/tim/vx/ops/concat.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/concat.h -------------------------------------------------------------------------------- /include/tim/vx/ops/concat.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/concat.json -------------------------------------------------------------------------------- /include/tim/vx/ops/conv1d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv1d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/conv1d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv1d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/conv2d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv2d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/conv2d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv2d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/conv3d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv3d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/conv3d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/conv3d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/cumsum.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/cumsum.h -------------------------------------------------------------------------------- /include/tim/vx/ops/cumsum.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/cumsum.json -------------------------------------------------------------------------------- /include/tim/vx/ops/custom_base.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/custom_base.h -------------------------------------------------------------------------------- /include/tim/vx/ops/dataconvert.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/dataconvert.json -------------------------------------------------------------------------------- /include/tim/vx/ops/deconv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/deconv.h -------------------------------------------------------------------------------- /include/tim/vx/ops/deconv1d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/deconv1d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/deconv1d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/deconv1d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/deconv2d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/deconv2d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/depth2space.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/depth2space.h -------------------------------------------------------------------------------- /include/tim/vx/ops/depth2space.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/depth2space.json -------------------------------------------------------------------------------- /include/tim/vx/ops/div.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/div.json -------------------------------------------------------------------------------- /include/tim/vx/ops/dropout.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/dropout.h -------------------------------------------------------------------------------- /include/tim/vx/ops/dropout.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/dropout.json -------------------------------------------------------------------------------- /include/tim/vx/ops/elementwise.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/elementwise.h -------------------------------------------------------------------------------- /include/tim/vx/ops/elu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/elu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/embedding_lookup.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/embedding_lookup.h -------------------------------------------------------------------------------- /include/tim/vx/ops/embeddinglookup.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/embeddinglookup.json -------------------------------------------------------------------------------- /include/tim/vx/ops/equal.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/equal.json -------------------------------------------------------------------------------- /include/tim/vx/ops/erf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/erf.h -------------------------------------------------------------------------------- /include/tim/vx/ops/erf.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/erf.json -------------------------------------------------------------------------------- /include/tim/vx/ops/exp.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/exp.json -------------------------------------------------------------------------------- /include/tim/vx/ops/floor.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/floor.json -------------------------------------------------------------------------------- /include/tim/vx/ops/floordiv.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/floordiv.json -------------------------------------------------------------------------------- /include/tim/vx/ops/fullyconnected.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/fullyconnected.h -------------------------------------------------------------------------------- /include/tim/vx/ops/fullyconnected.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/fullyconnected.json -------------------------------------------------------------------------------- /include/tim/vx/ops/gather.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gather.h -------------------------------------------------------------------------------- /include/tim/vx/ops/gather.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gather.json -------------------------------------------------------------------------------- /include/tim/vx/ops/gather_elements.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gather_elements.h -------------------------------------------------------------------------------- /include/tim/vx/ops/gatherelements.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gatherelements.json -------------------------------------------------------------------------------- /include/tim/vx/ops/gathernd.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gathernd.h -------------------------------------------------------------------------------- /include/tim/vx/ops/gathernd.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gathernd.json -------------------------------------------------------------------------------- /include/tim/vx/ops/gelu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/gelu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/greater.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/greater.json -------------------------------------------------------------------------------- /include/tim/vx/ops/greaterOrEqual.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/greaterOrEqual.json -------------------------------------------------------------------------------- /include/tim/vx/ops/groupedConv1d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/groupedConv1d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/groupedConv2d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/groupedConv2d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/groupedconv1d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/groupedconv1d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/groupedconv2d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/groupedconv2d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/grucell.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/grucell.h -------------------------------------------------------------------------------- /include/tim/vx/ops/grucell.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/grucell.json -------------------------------------------------------------------------------- /include/tim/vx/ops/hardsigmoid.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/hardsigmoid.json -------------------------------------------------------------------------------- /include/tim/vx/ops/hardswish.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/hardswish.json -------------------------------------------------------------------------------- /include/tim/vx/ops/hashtable_lookup.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/hashtable_lookup.h -------------------------------------------------------------------------------- /include/tim/vx/ops/instanceNormalization.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/instanceNormalization.json -------------------------------------------------------------------------------- /include/tim/vx/ops/instancenormalization.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/instancenormalization.h -------------------------------------------------------------------------------- /include/tim/vx/ops/l2normalization.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/l2normalization.h -------------------------------------------------------------------------------- /include/tim/vx/ops/layernormalization.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/layernormalization.h -------------------------------------------------------------------------------- /include/tim/vx/ops/leakyrelu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/leakyrelu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/less.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/less.json -------------------------------------------------------------------------------- /include/tim/vx/ops/lessOrEqual.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/lessOrEqual.json -------------------------------------------------------------------------------- /include/tim/vx/ops/linear.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/linear.json -------------------------------------------------------------------------------- /include/tim/vx/ops/localresponsenormalization.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/localresponsenormalization.h -------------------------------------------------------------------------------- /include/tim/vx/ops/log.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/log.json -------------------------------------------------------------------------------- /include/tim/vx/ops/logical.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/logical.h -------------------------------------------------------------------------------- /include/tim/vx/ops/logicalnot.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/logicalnot.json -------------------------------------------------------------------------------- /include/tim/vx/ops/logicalor.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/logicalor.json -------------------------------------------------------------------------------- /include/tim/vx/ops/logsoftmax.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/logsoftmax.h -------------------------------------------------------------------------------- /include/tim/vx/ops/logsoftmax.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/logsoftmax.json -------------------------------------------------------------------------------- /include/tim/vx/ops/matmul.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/matmul.h -------------------------------------------------------------------------------- /include/tim/vx/ops/matmul.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/matmul.json -------------------------------------------------------------------------------- /include/tim/vx/ops/max_pool3d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/max_pool3d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/maximum.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maximum.json -------------------------------------------------------------------------------- /include/tim/vx/ops/maxpool3d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxpool3d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/maxpoolgrad.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxpoolgrad.h -------------------------------------------------------------------------------- /include/tim/vx/ops/maxpoolwithargmax.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxpoolwithargmax.h -------------------------------------------------------------------------------- /include/tim/vx/ops/maxpoolwithargmax2.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxpoolwithargmax2.h -------------------------------------------------------------------------------- /include/tim/vx/ops/maxunpool2d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxunpool2d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/maxunpool2d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/maxunpool2d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/minimum.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/minimum.json -------------------------------------------------------------------------------- /include/tim/vx/ops/mish.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/mish.json -------------------------------------------------------------------------------- /include/tim/vx/ops/mod.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/mod.h -------------------------------------------------------------------------------- /include/tim/vx/ops/mod.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/mod.json -------------------------------------------------------------------------------- /include/tim/vx/ops/moments.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/moments.h -------------------------------------------------------------------------------- /include/tim/vx/ops/moments.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/moments.json -------------------------------------------------------------------------------- /include/tim/vx/ops/mul.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/mul.json -------------------------------------------------------------------------------- /include/tim/vx/ops/nbg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/nbg.h -------------------------------------------------------------------------------- /include/tim/vx/ops/nbg.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/nbg.json -------------------------------------------------------------------------------- /include/tim/vx/ops/neg.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/neg.json -------------------------------------------------------------------------------- /include/tim/vx/ops/notEqual.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/notEqual.json -------------------------------------------------------------------------------- /include/tim/vx/ops/onehot.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/onehot.h -------------------------------------------------------------------------------- /include/tim/vx/ops/onehot.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/onehot.json -------------------------------------------------------------------------------- /include/tim/vx/ops/pad.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pad.h -------------------------------------------------------------------------------- /include/tim/vx/ops/pad.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pad.json -------------------------------------------------------------------------------- /include/tim/vx/ops/pad_v2.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pad_v2.h -------------------------------------------------------------------------------- /include/tim/vx/ops/padv2.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/padv2.json -------------------------------------------------------------------------------- /include/tim/vx/ops/pool1d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pool1d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/pool1d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pool1d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/pool2d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pool2d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/pool2d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pool2d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/pow.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/pow.json -------------------------------------------------------------------------------- /include/tim/vx/ops/prelu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/prelu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/rcp.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/rcp.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reduce.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reduce.h -------------------------------------------------------------------------------- /include/tim/vx/ops/reduceall.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reduceall.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reduceany.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reduceany.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reducemax.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reducemax.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reducemean.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reducemean.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reducemin.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reducemin.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reduceprod.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reduceprod.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reducesum.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reducesum.json -------------------------------------------------------------------------------- /include/tim/vx/ops/relational_operations.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/relational_operations.h -------------------------------------------------------------------------------- /include/tim/vx/ops/relu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/relu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/relu1.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/relu1.json -------------------------------------------------------------------------------- /include/tim/vx/ops/relu6.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/relu6.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reorg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reorg.h -------------------------------------------------------------------------------- /include/tim/vx/ops/reorg.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reorg.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reshape.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reshape.h -------------------------------------------------------------------------------- /include/tim/vx/ops/reshape.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reshape.json -------------------------------------------------------------------------------- /include/tim/vx/ops/resize.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/resize.h -------------------------------------------------------------------------------- /include/tim/vx/ops/resize.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/resize.json -------------------------------------------------------------------------------- /include/tim/vx/ops/resize1d.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/resize1d.h -------------------------------------------------------------------------------- /include/tim/vx/ops/resize1d.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/resize1d.json -------------------------------------------------------------------------------- /include/tim/vx/ops/reverse.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reverse.h -------------------------------------------------------------------------------- /include/tim/vx/ops/reverse.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/reverse.json -------------------------------------------------------------------------------- /include/tim/vx/ops/rnn_cell.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/rnn_cell.h -------------------------------------------------------------------------------- /include/tim/vx/ops/rnncell.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/rnncell.json -------------------------------------------------------------------------------- /include/tim/vx/ops/roi_align.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/roi_align.h -------------------------------------------------------------------------------- /include/tim/vx/ops/roi_pool.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/roi_pool.h -------------------------------------------------------------------------------- /include/tim/vx/ops/roialign.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/roialign.json -------------------------------------------------------------------------------- /include/tim/vx/ops/roipool.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/roipool.json -------------------------------------------------------------------------------- /include/tim/vx/ops/round.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/round.json -------------------------------------------------------------------------------- /include/tim/vx/ops/rsqrt.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/rsqrt.json -------------------------------------------------------------------------------- /include/tim/vx/ops/scatternd.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/scatternd.h -------------------------------------------------------------------------------- /include/tim/vx/ops/scatternd.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/scatternd.json -------------------------------------------------------------------------------- /include/tim/vx/ops/scatternd_onnx_v16.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/scatternd_onnx_v16.h -------------------------------------------------------------------------------- /include/tim/vx/ops/scatternd_onnx_v16.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/scatternd_onnx_v16.json -------------------------------------------------------------------------------- /include/tim/vx/ops/select.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/select.h -------------------------------------------------------------------------------- /include/tim/vx/ops/select.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/select.json -------------------------------------------------------------------------------- /include/tim/vx/ops/selu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/selu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/shuffle_channel.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/shuffle_channel.h -------------------------------------------------------------------------------- /include/tim/vx/ops/shufflechannel.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/shufflechannel.json -------------------------------------------------------------------------------- /include/tim/vx/ops/sigmoid.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/sigmoid.json -------------------------------------------------------------------------------- /include/tim/vx/ops/sign.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/sign.json -------------------------------------------------------------------------------- /include/tim/vx/ops/signal_frame.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/signal_frame.h -------------------------------------------------------------------------------- /include/tim/vx/ops/signal_frame.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/signal_frame.json -------------------------------------------------------------------------------- /include/tim/vx/ops/simple_operations.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/simple_operations.h -------------------------------------------------------------------------------- /include/tim/vx/ops/sin.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/sin.json -------------------------------------------------------------------------------- /include/tim/vx/ops/slice.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/slice.h -------------------------------------------------------------------------------- /include/tim/vx/ops/slice.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/slice.json -------------------------------------------------------------------------------- /include/tim/vx/ops/softmax.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/softmax.h -------------------------------------------------------------------------------- /include/tim/vx/ops/softmax.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/softmax.json -------------------------------------------------------------------------------- /include/tim/vx/ops/softrelu.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/softrelu.json -------------------------------------------------------------------------------- /include/tim/vx/ops/softsign.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/softsign.json -------------------------------------------------------------------------------- /include/tim/vx/ops/space2batch.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/space2batch.h -------------------------------------------------------------------------------- /include/tim/vx/ops/space2batch.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/space2batch.json -------------------------------------------------------------------------------- /include/tim/vx/ops/space2depth.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/space2depth.h -------------------------------------------------------------------------------- /include/tim/vx/ops/space2depth.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/space2depth.json -------------------------------------------------------------------------------- /include/tim/vx/ops/spatial_transformer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/spatial_transformer.h -------------------------------------------------------------------------------- /include/tim/vx/ops/spatialtransformer.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/spatialtransformer.json -------------------------------------------------------------------------------- /include/tim/vx/ops/split.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/split.h -------------------------------------------------------------------------------- /include/tim/vx/ops/split.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/split.json -------------------------------------------------------------------------------- /include/tim/vx/ops/sqrt.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/sqrt.json -------------------------------------------------------------------------------- /include/tim/vx/ops/square.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/square.json -------------------------------------------------------------------------------- /include/tim/vx/ops/squeeze.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/squeeze.h -------------------------------------------------------------------------------- /include/tim/vx/ops/squeeze.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/squeeze.json -------------------------------------------------------------------------------- /include/tim/vx/ops/stack.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/stack.h -------------------------------------------------------------------------------- /include/tim/vx/ops/stack.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/stack.json -------------------------------------------------------------------------------- /include/tim/vx/ops/stridedslice.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/stridedslice.h -------------------------------------------------------------------------------- /include/tim/vx/ops/stridedslice.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/stridedslice.json -------------------------------------------------------------------------------- /include/tim/vx/ops/sub.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/sub.json -------------------------------------------------------------------------------- /include/tim/vx/ops/svdf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/svdf.h -------------------------------------------------------------------------------- /include/tim/vx/ops/svdf.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/svdf.json -------------------------------------------------------------------------------- /include/tim/vx/ops/swish.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/swish.json -------------------------------------------------------------------------------- /include/tim/vx/ops/tanh.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/tanh.json -------------------------------------------------------------------------------- /include/tim/vx/ops/tile.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/tile.h -------------------------------------------------------------------------------- /include/tim/vx/ops/tile.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/tile.json -------------------------------------------------------------------------------- /include/tim/vx/ops/tiny_yolov4_postprocess.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/tiny_yolov4_postprocess.h -------------------------------------------------------------------------------- /include/tim/vx/ops/topk.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/topk.h -------------------------------------------------------------------------------- /include/tim/vx/ops/topk.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/topk.json -------------------------------------------------------------------------------- /include/tim/vx/ops/transpose.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/transpose.h -------------------------------------------------------------------------------- /include/tim/vx/ops/transpose.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/transpose.json -------------------------------------------------------------------------------- /include/tim/vx/ops/unidirectional_sequence_gru.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unidirectional_sequence_gru.h -------------------------------------------------------------------------------- /include/tim/vx/ops/unidirectional_sequence_lstm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unidirectional_sequence_lstm.h -------------------------------------------------------------------------------- /include/tim/vx/ops/unidirectional_sequence_rnn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unidirectional_sequence_rnn.h -------------------------------------------------------------------------------- /include/tim/vx/ops/unidirectionalsequenceGRU.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unidirectionalsequenceGRU.json -------------------------------------------------------------------------------- /include/tim/vx/ops/unidirectionalsequenceRNN.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unidirectionalsequenceRNN.json -------------------------------------------------------------------------------- /include/tim/vx/ops/unstack.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unstack.h -------------------------------------------------------------------------------- /include/tim/vx/ops/unstack.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/ops/unstack.json -------------------------------------------------------------------------------- /include/tim/vx/platform/grpc/grpc_remote.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/platform/grpc/grpc_remote.h -------------------------------------------------------------------------------- /include/tim/vx/platform/lite/lite_native.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/platform/lite/lite_native.h -------------------------------------------------------------------------------- /include/tim/vx/platform/native.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/platform/native.h -------------------------------------------------------------------------------- /include/tim/vx/platform/platform.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/platform/platform.h -------------------------------------------------------------------------------- /include/tim/vx/tensor.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/tensor.h -------------------------------------------------------------------------------- /include/tim/vx/types.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/include/tim/vx/types.h -------------------------------------------------------------------------------- /prebuilt-sdk/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/BUILD -------------------------------------------------------------------------------- /prebuilt-sdk/VIPLite/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/VIPLite/BUILD -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/BUILD -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/VERSION: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/VERSION -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_api.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_api.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_helper.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_helper.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_import.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_import.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_kernels.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_kernels.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_cnn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_cnn.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_dot.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_dot.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_icd.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_icd.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_ix.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_ix.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_nn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_nn.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_khr_xml.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_khr_xml.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_lib_xyz.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_lib_xyz.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_nodes.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_nodes.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_spinst.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_spinst.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_types.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_types.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_vendors.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_vendors.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vx_viv_sys.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vx_viv_sys.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/include/VX/vxu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/include/VX/vxu.h -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libArchModelSw.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libArchModelSw.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libCLC.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libCLC.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libEmulator.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libEmulator.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libGAL.1.7.4.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libGAL.1.7.4.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libGAL.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libGAL.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libNNArchPerf.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libNNArchPerf.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libOpenVX.so: -------------------------------------------------------------------------------- 1 | libOpenVX.so.1.3.0 -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libOpenVX.so.1: -------------------------------------------------------------------------------- 1 | libOpenVX.so.1.3.0 -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libOpenVX.so.1.3.0: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libOpenVX.so.1.3.0 -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libOpenVXC.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libOpenVXC.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libOpenVXU.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libOpenVXU.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libVSC.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libVSC.so -------------------------------------------------------------------------------- /prebuilt-sdk/x86_64_linux/lib/libvdtproxy.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/prebuilt-sdk/x86_64_linux/lib/libvdtproxy.so -------------------------------------------------------------------------------- /samples/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/CMakeLists.txt -------------------------------------------------------------------------------- /samples/benchmark_test/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/benchmark_test/BUILD -------------------------------------------------------------------------------- /samples/benchmark_test/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/benchmark_test/CMakeLists.txt -------------------------------------------------------------------------------- /samples/benchmark_test/benchmark_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/benchmark_test/benchmark_test.cc -------------------------------------------------------------------------------- /samples/custom_lenet/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/BUILD -------------------------------------------------------------------------------- /samples/custom_lenet/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/CMakeLists.txt -------------------------------------------------------------------------------- /samples/custom_lenet/custom_softmax.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/custom_softmax.cc -------------------------------------------------------------------------------- /samples/custom_lenet/custom_softmax.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/custom_softmax.h -------------------------------------------------------------------------------- /samples/custom_lenet/lenet_asymu8.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/lenet_asymu8.cc -------------------------------------------------------------------------------- /samples/custom_lenet/lenet_asymu8_weights.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_lenet/lenet_asymu8_weights.h -------------------------------------------------------------------------------- /samples/custom_op_test/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_op_test/CMakeLists.txt -------------------------------------------------------------------------------- /samples/custom_op_test/custom_gemm.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_op_test/custom_gemm.cc -------------------------------------------------------------------------------- /samples/custom_op_test/custom_gemm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_op_test/custom_gemm.h -------------------------------------------------------------------------------- /samples/custom_op_test/custom_op_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/custom_op_test/custom_op_test.cc -------------------------------------------------------------------------------- /samples/grpc/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/grpc/CMakeLists.txt -------------------------------------------------------------------------------- /samples/grpc/README.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/grpc/README.txt -------------------------------------------------------------------------------- /samples/grpc/grpc_multi_device.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/grpc/grpc_multi_device.cc -------------------------------------------------------------------------------- /samples/lenet/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet/BUILD -------------------------------------------------------------------------------- /samples/lenet/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet/CMakeLists.txt -------------------------------------------------------------------------------- /samples/lenet/lenet_asymu8.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet/lenet_asymu8.cc -------------------------------------------------------------------------------- /samples/lenet/lenet_asymu8_weights.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet/lenet_asymu8_weights.h -------------------------------------------------------------------------------- /samples/lenet_lite/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_lite/BUILD -------------------------------------------------------------------------------- /samples/lenet_lite/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_lite/CMakeLists.txt -------------------------------------------------------------------------------- /samples/lenet_lite/lenet_lite_asymu8.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_lite/lenet_lite_asymu8.cc -------------------------------------------------------------------------------- /samples/lenet_lite/lenet_lite_asymu8_executable.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_lite/lenet_lite_asymu8_executable.h -------------------------------------------------------------------------------- /samples/lenet_multi_device/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_multi_device/BUILD -------------------------------------------------------------------------------- /samples/lenet_multi_device/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_multi_device/CMakeLists.txt -------------------------------------------------------------------------------- /samples/lenet_multi_device/lenet.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_multi_device/lenet.h -------------------------------------------------------------------------------- /samples/lenet_multi_device/lenet_multi_device.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/lenet_multi_device/lenet_multi_device.cc -------------------------------------------------------------------------------- /samples/multi_device/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/CMakeLists.txt -------------------------------------------------------------------------------- /samples/multi_device/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/README -------------------------------------------------------------------------------- /samples/multi_device/lenet/lenet.export.data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/lenet/lenet.export.data -------------------------------------------------------------------------------- /samples/multi_device/multi_device.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/multi_device.cc -------------------------------------------------------------------------------- /samples/multi_device/multi_device_demo.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/multi_device_demo.cc -------------------------------------------------------------------------------- /samples/multi_device/vx_lenet.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_lenet.cc -------------------------------------------------------------------------------- /samples/multi_device/vx_lenet.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_lenet.h -------------------------------------------------------------------------------- /samples/multi_device/vx_mobilenet.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_mobilenet.cc -------------------------------------------------------------------------------- /samples/multi_device/vx_mobilenet.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_mobilenet.h -------------------------------------------------------------------------------- /samples/multi_device/vx_resnet50.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_resnet50.cc -------------------------------------------------------------------------------- /samples/multi_device/vx_resnet50.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_device/vx_resnet50.h -------------------------------------------------------------------------------- /samples/multi_thread_test/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_thread_test/BUILD -------------------------------------------------------------------------------- /samples/multi_thread_test/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_thread_test/CMakeLists.txt -------------------------------------------------------------------------------- /samples/multi_thread_test/lenet_asymu8_weights.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_thread_test/lenet_asymu8_weights.h -------------------------------------------------------------------------------- /samples/multi_thread_test/multi_thread_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/multi_thread_test/multi_thread_test.cc -------------------------------------------------------------------------------- /samples/nbg_runner/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner/BUILD -------------------------------------------------------------------------------- /samples/nbg_runner/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner/CMakeLists.txt -------------------------------------------------------------------------------- /samples/nbg_runner/nbg_runner_main.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner/nbg_runner_main.cc -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/.clang-format: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/.clang-format -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/.clang-tidy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/.clang-tidy -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/.gitignore -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/CMakeLists.txt -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/README.md -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/examples/data/bird.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/examples/data/bird.jpg -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/examples/data/cat.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/examples/data/cat.jpg -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/examples/demo.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/examples/demo.py -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/examples/imagenet1k.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/examples/imagenet1k.py -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/python/nbg_runner/vx/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/src/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/src/CMakeLists.txt -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/src/vx/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/src/vx/CMakeLists.txt -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/src/vx/ovx_executor.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/src/vx/ovx_executor.cpp -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/src/vx/ovx_executor.hpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/src/vx/ovx_executor.hpp -------------------------------------------------------------------------------- /samples/nbg_runner_pybind/src/vx/utils.hpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/nbg_runner_pybind/src/vx/utils.hpp -------------------------------------------------------------------------------- /samples/platform_sample/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/platform_sample/CMakeLists.txt -------------------------------------------------------------------------------- /samples/platform_sample/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/platform_sample/README -------------------------------------------------------------------------------- /samples/platform_sample/platform_sample.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/samples/platform_sample/platform_sample.cc -------------------------------------------------------------------------------- /src/tim/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/CMakeLists.txt -------------------------------------------------------------------------------- /src/tim/lite/execution.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/lite/execution.cc -------------------------------------------------------------------------------- /src/tim/lite/execution_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/lite/execution_private.h -------------------------------------------------------------------------------- /src/tim/lite/handle.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/lite/handle.cc -------------------------------------------------------------------------------- /src/tim/lite/handle_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/lite/handle_private.h -------------------------------------------------------------------------------- /src/tim/transform/layout_infer_context.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/layout_infer_context.h -------------------------------------------------------------------------------- /src/tim/transform/layout_inference.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/layout_inference.cc -------------------------------------------------------------------------------- /src/tim/transform/layout_inference_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/layout_inference_test.cc -------------------------------------------------------------------------------- /src/tim/transform/mean_stddev_normalize_fusion.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/mean_stddev_normalize_fusion.cc -------------------------------------------------------------------------------- /src/tim/transform/ops/addn_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/addn_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/arg_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/arg_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/concat_layout_inferene.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/concat_layout_inferene.h -------------------------------------------------------------------------------- /src/tim/transform/ops/conv2d_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/conv2d_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/conv3d_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/conv3d_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/deconv2d_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/deconv2d_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/default_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/default_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/gather_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/gather_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/logical_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/logical_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/lrn_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/lrn_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/op_layout_inference.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/op_layout_inference.cc -------------------------------------------------------------------------------- /src/tim/transform/ops/op_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/op_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/pad_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/pad_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/pad_v2_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/pad_v2_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/pool2d_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/pool2d_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/reduce_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/reduce_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/resize_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/resize_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/reverse_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/reverse_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/roi_pool_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/roi_pool_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/select_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/select_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/slice_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/slice_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/softmax_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/softmax_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/split_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/split_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/squeeze_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/squeeze_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/stack_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/stack_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/ops/yolov4_layout_inference.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/ops/yolov4_layout_inference.h -------------------------------------------------------------------------------- /src/tim/transform/pad_layout_inference_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/pad_layout_inference_test.cc -------------------------------------------------------------------------------- /src/tim/transform/permute_vector.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/permute_vector.h -------------------------------------------------------------------------------- /src/tim/transform/prelu_layout_inference_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/prelu_layout_inference_test.cc -------------------------------------------------------------------------------- /src/tim/transform/reduce_layout_inference_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/reduce_layout_inference_test.cc -------------------------------------------------------------------------------- /src/tim/transform/stack_layout_inference_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/transform/stack_layout_inference_test.cc -------------------------------------------------------------------------------- /src/tim/utils/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if(TIM_VX_ENABLE_NBG_PARSER) 2 | add_subdirectory("nbg_parser") 3 | endif() -------------------------------------------------------------------------------- /src/tim/utils/nbg_parser/CMakeLists.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/utils/nbg_parser/CMakeLists.txt -------------------------------------------------------------------------------- /src/tim/utils/nbg_parser/nbg_parser.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/utils/nbg_parser/nbg_parser.c -------------------------------------------------------------------------------- /src/tim/vx/builtin_op.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/builtin_op.cc -------------------------------------------------------------------------------- /src/tim/vx/builtin_op_impl.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/builtin_op_impl.cc -------------------------------------------------------------------------------- /src/tim/vx/builtin_op_impl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/builtin_op_impl.h -------------------------------------------------------------------------------- /src/tim/vx/compile_option.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/compile_option.cc -------------------------------------------------------------------------------- /src/tim/vx/compile_option_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/compile_option_test.cc -------------------------------------------------------------------------------- /src/tim/vx/context.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/context.cc -------------------------------------------------------------------------------- /src/tim/vx/context_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/context_private.h -------------------------------------------------------------------------------- /src/tim/vx/context_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/context_test.cc -------------------------------------------------------------------------------- /src/tim/vx/graph.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/graph.cc -------------------------------------------------------------------------------- /src/tim/vx/graph_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/graph_private.h -------------------------------------------------------------------------------- /src/tim/vx/graph_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/graph_test.cc -------------------------------------------------------------------------------- /src/tim/vx/internal/.clang-format: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/.clang-format -------------------------------------------------------------------------------- /src/tim/vx/internal/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/.gitignore -------------------------------------------------------------------------------- /src/tim/vx/internal/BUILD: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/BUILD -------------------------------------------------------------------------------- /src/tim/vx/internal/ConvertPGMToH.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/ConvertPGMToH.py -------------------------------------------------------------------------------- /src/tim/vx/internal/include/custom/custom_ops.def: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/custom/custom_ops.def -------------------------------------------------------------------------------- /src/tim/vx/internal/include/interface/ops.def: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/interface/ops.def -------------------------------------------------------------------------------- /src/tim/vx/internal/include/kernel/vsi_nn_gpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/kernel/vsi_nn_gpu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_addn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_addn.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_cast.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_cast.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_celu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_celu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_clip.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_clip.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_crop.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_crop.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_elu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_elu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_exp.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_exp.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_floor.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_floor.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_gelu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_gelu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_gru.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_gru.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_log.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_log.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_lrn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_lrn.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_lstm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_lstm.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_mod.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_mod.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_nbg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_nbg.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_neg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_neg.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_nms.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_nms.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_pad.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_pad.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_pad2.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_pad2.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_pool.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_pool.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_pow.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_pow.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_prelu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_prelu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_rcp.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_rcp.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_relun.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_relun.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_reorg.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_reorg.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_rnn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_rnn.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_rope.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_rope.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_scale.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_scale.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_selu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_selu.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_shape.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_shape.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_sign.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_sign.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_sin.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_sin.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_slice.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_slice.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/ops/vsi_nn_op_split.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/ops/vsi_nn_op_split.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/utils/vsi_nn_map.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/utils/vsi_nn_map.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/utils/vsi_nn_math.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/utils/vsi_nn_math.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/utils/vsi_nn_util.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/utils/vsi_nn_util.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_assert.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_assert.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_client_op.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_client_op.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_context.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_context.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_daemon.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_daemon.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_error.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_error.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_feature.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_feature.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_graph.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_graph.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_log.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_log.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_node.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_node.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_node_type.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_node_type.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_ops.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_ops.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_platform.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_platform.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_post.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_post.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_prv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_prv.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_pub.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_pub.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_rnn.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_rnn.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_rnn_helper.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_rnn_helper.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_rnn_prv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_rnn_prv.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_tensor.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_tensor.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_test.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_types.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_types.h -------------------------------------------------------------------------------- /src/tim/vx/internal/include/vsi_nn_version.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/include/vsi_nn_version.h -------------------------------------------------------------------------------- /src/tim/vx/internal/ovxlib_bin_build.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/ovxlib_bin_build.md -------------------------------------------------------------------------------- /src/tim/vx/internal/ovxlib_bin_build.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/ovxlib_bin_build.sh -------------------------------------------------------------------------------- /src/tim/vx/internal/src/Android.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/Android.mk -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/argmax_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/argmax_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/argmin_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/argmin_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/cast_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/cast_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/clip_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/clip_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/col2im_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/col2im_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/cumsum_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/cumsum_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/erf_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/erf_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/floordiv_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/floordiv_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/gather_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/gather_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/l1norm_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/l1norm_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/lppool_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/lppool_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/maximum_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/maximum_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/minimum_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/minimum_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/mod_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/mod_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/moments_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/moments_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/one_hot_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/one_hot_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/pool_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/pool_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/pow_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/pow_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/prelu_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/prelu_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/repeat_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/repeat_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/rope_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/rope_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/select_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/select_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/slice_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/slice_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/swish_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/swish_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/tile_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/tile_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/topk_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/topk_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/cl/upsample_cl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/cl/upsample_cl.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/cast_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/cast_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/clip_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/clip_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/erf_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/erf_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/mod_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/mod_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/pool_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/pool_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/pow_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/pow_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/rope_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/rope_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/evis/tile_evis.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/evis/tile_evis.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vsi_nn_gpu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vsi_nn_gpu.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vsi_nn_kernel.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vsi_nn_kernel.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/argmax_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/argmax_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/bitcast_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/bitcast_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/eltwise_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/eltwise_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/gather_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/gather_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/pad2_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/pad2_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/pow_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/pow_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/prelu_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/prelu_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/resize_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/resize_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/rms_norm_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/rms_norm_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/select_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/select_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/softmax_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/softmax_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/square_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/square_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/swish_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/swish_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/kernel/vx/tile_vx.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/kernel/vx/tile_vx.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/cast.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/cast.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/erf.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/erf.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/mod.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/mod.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/pow.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/pow.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/tile.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/tile.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/cl/topk.cl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/cl/topk.cl -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/vx/cast.vx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/vx/cast.vx -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/vx/erf.vx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/vx/erf.vx -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/vx/mod.vx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/vx/mod.vx -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/vx/pow.vx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/vx/pow.vx -------------------------------------------------------------------------------- /src/tim/vx/internal/src/libnnext/ops/vx/tile.vx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/libnnext/ops/vx/tile.vx -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_abs.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_abs.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_addn.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_addn.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_bitcast.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_bitcast.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_cast.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_cast.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_ceil.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_ceil.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_clip.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_clip.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_col2im.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_col2im.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_common.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_common.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_concat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_concat.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_conv1d.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_conv1d.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_conv2d.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_conv2d.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_conv3d.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_conv3d.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_crop.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_crop.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_cumsum.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_cumsum.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_dropout.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_dropout.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_eltwise.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_eltwise.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_erf.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_erf.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_floor.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_floor.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_gather.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_gather.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_gru.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_gru.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_grucell.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_grucell.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_interp.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_interp.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_linear.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_linear.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_lpnorm.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_lpnorm.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_lppool.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_lppool.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_lrn.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_lrn.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_lrn2.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_lrn2.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_lstm.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_lstm.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_mod.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_mod.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_moments.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_moments.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_nbg.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_nbg.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_nms.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_nms.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_noop.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_noop.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_one_hot.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_one_hot.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_pad.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_pad.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_pad2.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_pad2.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_permute.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_permute.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_pool.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_pool.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_prelu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_prelu.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_reduce.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_reduce.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_relu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_relu.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_relu1.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_relu1.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_relu6.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_relu6.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_relun.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_relun.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_reorg.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_reorg.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_repeat.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_repeat.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_reshape.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_reshape.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_resize.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_resize.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_reverse.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_reverse.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_rmsnorm.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_rmsnorm.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_rnn.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_rnn.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_rope.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_rope.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_rsqrt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_rsqrt.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_scale.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_scale.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_select.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_select.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_shape.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_shape.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_sigmoid.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_sigmoid.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_slice.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_slice.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_softmax.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_softmax.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_split.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_split.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_sqrt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_sqrt.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_square.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_square.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_squeeze.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_squeeze.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_stack.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_stack.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_svdf.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_svdf.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_swish.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_swish.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_tanh.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_tanh.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_tile.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_tile.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_topk.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_topk.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/ops/vsi_nn_op_unstack.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/ops/vsi_nn_op_unstack.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_dlfcn.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_dlfcn.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_dtype.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_dtype.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_hashmap.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_hashmap.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_limits.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_limits.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_map.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_map.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_math.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_math.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/utils/vsi_nn_util.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/utils/vsi_nn_util.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vip/virtual_device.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vip/virtual_device.cpp -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_client_op.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_client_op.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_context.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_context.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_daemon.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_daemon.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_graph.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_graph.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_internal_node.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_internal_node.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_kernel_prv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_kernel_prv.h -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_log.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_log.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_node.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_node.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_ops.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_ops.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_rnn.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_rnn.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_rnn_helper.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_rnn_helper.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_tensor.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_tensor.c -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_types_prv.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_types_prv.h -------------------------------------------------------------------------------- /src/tim/vx/internal/src/vsi_nn_version.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/src/vsi_nn_version.c -------------------------------------------------------------------------------- /src/tim/vx/internal/tim_internal.cmake: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/internal/tim_internal.cmake -------------------------------------------------------------------------------- /src/tim/vx/op_impl.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/op_impl.cc -------------------------------------------------------------------------------- /src/tim/vx/op_impl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/op_impl.h -------------------------------------------------------------------------------- /src/tim/vx/operation.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/operation.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/README.md -------------------------------------------------------------------------------- /src/tim/vx/ops/activations.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/activations.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/activations_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/activations_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/addn.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/addn.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/addn_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/addn_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/arg.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/arg.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/arg_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/arg_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/avg_pool_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/avg_pool_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/batch2space.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/batch2space.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/batch2space_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/batch2space_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/batchnorm.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/batchnorm.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/batchnorm_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/batchnorm_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/bidirectional_sequence_lstm.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/bidirectional_sequence_lstm.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/bidirectional_sequence_rnn.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/bidirectional_sequence_rnn.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/broadcast.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/broadcast.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/broadcast_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/broadcast_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/clip.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/clip.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/concat.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/concat.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv1d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv1d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv1d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv1d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv2d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv2d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv2d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv2d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv3d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv3d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/conv3d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/conv3d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/cumsum.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/cumsum.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/cumsum_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/cumsum_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/custom_base.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/custom_base.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/deconv.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/deconv.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/deconv1d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/deconv1d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/deconv1d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/deconv1d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/deconv2d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/deconv2d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/depth2space.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/depth2space.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/depth2space_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/depth2space_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/depthwiseConv_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/depthwiseConv_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/dropout.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/dropout.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/elementwise.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/elementwise.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/elementwise_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/elementwise_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/embedding_lookup.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/embedding_lookup.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/embedding_lookup_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/embedding_lookup_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/erf.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/erf.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/erf_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/erf_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/fullyconnected.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/fullyconnected.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/fullyconnected_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/fullyconnected_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/gather.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/gather.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/gather_elements.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/gather_elements.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/gather_elements_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/gather_elements_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/gather_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/gather_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/gathernd.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/gathernd.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/groupedconv1d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/groupedconv1d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/groupedconv1d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/groupedconv1d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/groupedconv2d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/groupedconv2d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/groupedconv2d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/groupedconv2d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/grucell.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/grucell.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/grucell_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/grucell_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/hashtable_lookup.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/hashtable_lookup.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/hashtable_lookup_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/hashtable_lookup_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/instancenormalization.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/instancenormalization.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/instancenormalization_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/instancenormalization_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/l2normalization.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/l2normalization.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/l2normalization_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/l2normalization_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/layernormalization.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/layernormalization.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/layernormalization_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/layernormalization_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/localresponsenormalization.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/localresponsenormalization.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/logical.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/logical.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/logsoftmax.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/logsoftmax.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/logsoftmax_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/logsoftmax_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/matmul.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/matmul.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/matmul_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/matmul_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/max_pool3d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/max_pool3d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/max_pool3d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/max_pool3d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/max_pool_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/max_pool_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolgrad.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolgrad.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolgrad_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolgrad_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolwithargmax.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolwithargmax.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolwithargmax2.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolwithargmax2.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolwithargmax2_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolwithargmax2_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxpoolwithargmax_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxpoolwithargmax_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxunpool2d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxunpool2d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/maxunpool2d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/maxunpool2d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/mod.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/mod.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/mod_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/mod_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/moments.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/moments.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/moments_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/moments_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/nbg.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/nbg.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/onehot.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/onehot.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/onehot_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/onehot_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/pad.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/pad.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/pad_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/pad_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/pad_v2.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/pad_v2.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/pool1d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/pool1d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/pool2d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/pool2d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reduce.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reduce.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reduce_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reduce_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/relational_operations.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/relational_operations.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/relational_operations_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/relational_operations_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reorg.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reorg.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reorg_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reorg_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reshape.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reshape.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reshape_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reshape_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/resize.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/resize.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/resize1d.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/resize1d.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/resize1d_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/resize1d_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/resize_bilinear_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/resize_bilinear_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/reverse.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/reverse.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/rnn_cell.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/rnn_cell.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/rnn_cell_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/rnn_cell_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/roi_align.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/roi_align.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/roi_align_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/roi_align_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/roi_pool.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/roi_pool.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/roi_pool_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/roi_pool_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/scatternd.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/scatternd.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/scatternd_onnx_v16.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/scatternd_onnx_v16.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/scatternd_onnx_v16_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/scatternd_onnx_v16_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/scatternd_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/scatternd_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/select.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/select.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/shuffle_channel.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/shuffle_channel.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/shuffle_channel_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/shuffle_channel_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/signal_frame.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/signal_frame.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/signal_frame_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/signal_frame_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/simple_operations.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/simple_operations.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/simple_operations_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/simple_operations_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/slice.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/slice.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/slice_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/slice_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/softmax.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/softmax.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/softmax_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/softmax_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/space2batch.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/space2batch.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/space2batch_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/space2batch_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/space2depth.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/space2depth.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/spatial_transformer.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/spatial_transformer.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/spatial_transformer_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/spatial_transformer_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/split.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/split.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/squeeze.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/squeeze.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/stack.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/stack.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/stack_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/stack_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/stridedslice.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/stridedslice.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/stridedslice_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/stridedslice_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/svdf.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/svdf.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/svdf_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/svdf_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/tile.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/tile.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/tile_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/tile_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/tiny_yolov4_postprocess.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/tiny_yolov4_postprocess.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/topk.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/topk.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/topk_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/topk_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/transpose.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/transpose.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/transposeConv_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/transposeConv_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/transpose_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/transpose_test.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/unidirectional_sequence_gru.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/unidirectional_sequence_gru.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/unidirectional_sequence_lstm.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/unidirectional_sequence_lstm.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/unidirectional_sequence_rnn.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/unidirectional_sequence_rnn.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/unstack.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/unstack.cc -------------------------------------------------------------------------------- /src/tim/vx/ops/unstack_test.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/ops/unstack_test.cc -------------------------------------------------------------------------------- /src/tim/vx/platform/grpc/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/grpc/README.md -------------------------------------------------------------------------------- /src/tim/vx/platform/grpc/grpc_platform.proto: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/grpc/grpc_platform.proto -------------------------------------------------------------------------------- /src/tim/vx/platform/grpc/grpc_platform_client.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/grpc/grpc_platform_client.h -------------------------------------------------------------------------------- /src/tim/vx/platform/grpc/grpc_remote.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/grpc/grpc_remote.cc -------------------------------------------------------------------------------- /src/tim/vx/platform/lite/lite_native.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/lite/lite_native.cc -------------------------------------------------------------------------------- /src/tim/vx/platform/lite/lite_native_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/lite/lite_native_private.h -------------------------------------------------------------------------------- /src/tim/vx/platform/native.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/native.cc -------------------------------------------------------------------------------- /src/tim/vx/platform/native_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/platform/native_private.h -------------------------------------------------------------------------------- /src/tim/vx/tensor.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/tensor.cc -------------------------------------------------------------------------------- /src/tim/vx/tensor_private.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/tensor_private.h -------------------------------------------------------------------------------- /src/tim/vx/test_utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/test_utils.h -------------------------------------------------------------------------------- /src/tim/vx/type_utils.cc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/type_utils.cc -------------------------------------------------------------------------------- /src/tim/vx/type_utils.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/src/tim/vx/type_utils.h -------------------------------------------------------------------------------- /third_party/half/ChangeLog.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/ChangeLog.txt -------------------------------------------------------------------------------- /third_party/half/ChangeLog.txt.license: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/ChangeLog.txt.license -------------------------------------------------------------------------------- /third_party/half/LICENSE.spdx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/LICENSE.spdx -------------------------------------------------------------------------------- /third_party/half/LICENSE.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/LICENSE.txt -------------------------------------------------------------------------------- /third_party/half/README.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/README.txt -------------------------------------------------------------------------------- /third_party/half/README.txt.license: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/README.txt.license -------------------------------------------------------------------------------- /third_party/half/half.hpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/third_party/half/half.hpp -------------------------------------------------------------------------------- /toolchains/BUILD.bazel: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/toolchains/BUILD.bazel -------------------------------------------------------------------------------- /toolchains/WORKSPACE: -------------------------------------------------------------------------------- 1 | workspace(name = "TOOLCHAINS") -------------------------------------------------------------------------------- /toolchains/cc_toolchain_base.bzl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/toolchains/cc_toolchain_base.bzl -------------------------------------------------------------------------------- /toolchains/toolchains.bzl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VeriSilicon/TIM-VX/HEAD/toolchains/toolchains.bzl --------------------------------------------------------------------------------