├── .gitignore ├── COPYING ├── README ├── scripts ├── veriperl.pl └── xilinx │ ├── axi_slave_interconnect_external_ports_creation.tcl │ ├── axi_slave_v1_0.v │ ├── axi_slave_v1_0_S00_AXI.v │ └── base_microblaze_design_wrapper.vhd └── src ├── sw ├── common │ └── trace_parser.pl ├── miaow_unit_tests │ ├── common │ │ ├── benchmark.ini │ │ ├── ut │ │ ├── ut.cpp │ │ ├── ut.hpp │ │ ├── ut_Kernels.bin │ │ └── ut_Kernels.cl │ ├── run │ ├── test_000_branch │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_000_branch_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_000_branch_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_000_mov_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_000_mov_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_000_mov_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_001_cbranch_scc0 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_001_cbranch_scc0_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_001_cbranch_scc0_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_001_mov_b64 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_001_mov_b64_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_001_mov_b64_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_002_cbranch_scc1 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_002_cbranch_scc1_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_002_cbranch_scc1_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_002_not_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_002_not_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_002_not_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_003_and_saveexec_b64 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_003_and_saveexec_b64_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_003_and_saveexec_b64_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_003_cbranch_vccz │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_003_cbranch_vccz_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_003_cbranch_vccz_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_004_add_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_004_add_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_004_add_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_004_cbranch_execz │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_004_cbranch_execz_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_004_cbranch_execz_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_005_add_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_005_add_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_005_add_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_005_barrier │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_005_barrier_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_005_barrier_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_006_sub_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_006_sub_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_006_sub_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_006_waitcnt │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_006_waitcnt_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_006_waitcnt_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_007_min_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_007_min_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_007_min_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_008_max_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_008_max_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_008_max_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_009_and_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_009_and_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_009_and_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_010_and_b64 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_010_and_b64_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_010_and_b64_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_011_or_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_011_or_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_011_or_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_012_andn2_b64 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_012_andn2_b64_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_012_andn2_b64_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_013_lshl_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_013_lshl_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_013_lshl_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_014_lshr_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_014_lshr_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_014_lshr_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_015_ashr_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_015_ashr_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_015_ashr_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_016_mul_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_016_mul_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_016_mul_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_017_movk_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_017_movk_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_017_movk_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_018_addk_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_018_addk_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_018_addk_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_019_mulk_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_019_mulk_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_019_mulk_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_020_cmp_eq_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_020_cmp_eq_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_020_cmp_eq_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_021_cmp_le_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_021_cmp_le_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_021_cmp_le_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_022_cmp_ge_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_022_cmp_ge_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_022_cmp_ge_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_023_cmp_le_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_023_cmp_le_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_023_cmp_le_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_100_mov_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_100_mov_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_100_mov_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_105_cndmask_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_105_cndmask_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_105_cndmask_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_106_add_f32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_106_add_f32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_106_add_f32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_107_sub_f32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_107_sub_f32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_107_sub_f32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_108_subrev_f32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_108_subrev_f32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_108_subrev_f32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_109_mul_f32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_109_mul_f32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_109_mul_f32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_110_mul_i32_i24 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_110_mul_i32_i24_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_110_mul_i32_i24_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_111_lshrrev_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_111_lshrrev_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_111_lshrrev_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_112_lshlrev_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_112_lshlrev_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_112_lshlrev_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_113_and_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_113_and_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_113_and_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_114_or_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_114_or_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_114_or_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_116_add_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_116_add_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_116_add_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_117_sub_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_117_sub_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_117_sub_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_118_cmp_gt_f32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_118_cmp_gt_f32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_118_cmp_gt_f32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_119_cmp_eq_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_119_cmp_eq_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_119_cmp_eq_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_120_cmp_gt_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_120_cmp_gt_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_120_cmp_gt_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_121_cmp_ne_i32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_121_cmp_ne_i32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_121_cmp_ne_i32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_122_cmp_le_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_122_cmp_le_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_122_cmp_le_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_123_cmp_gt_u32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_123_cmp_gt_u32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_123_cmp_gt_u32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_124_cmp_gt_f32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_124_cmp_gt_f32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_124_cmp_gt_f32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_125_cmp_eq_i32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_125_cmp_eq_i32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_125_cmp_eq_i32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_126_cmp_gt_i32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_126_cmp_gt_i32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_126_cmp_gt_i32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_127_cmp_ne_i32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_127_cmp_ne_i32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_127_cmp_ne_i32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_128_cmp_le_u32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_128_cmp_le_u32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_128_cmp_le_u32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_129_cmp_gt_u32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_129_cmp_gt_u32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_129_cmp_gt_u32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_130_cmp_ge_u32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_130_cmp_ge_u32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_130_cmp_ge_u32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_131_mul_lo_u32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_131_mul_lo_u32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_131_mul_lo_u32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_132_mul_hi_u32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_132_mul_hi_u32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_132_mul_hi_u32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_133_mul_lo_i32_3a │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_133_mul_lo_i32_3a_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_133_mul_lo_i32_3a_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_200_ld_dwx4 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_200_ld_dwx4_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_200_ld_dwx4_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_201_buff_ld_dw │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_201_buff_ld_dw_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_201_buff_ld_dw_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_202_buff_ld_dwx2 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_202_buff_ld_dwx2_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_202_buff_ld_dwx2_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_300_tbuff_ld_fmt_x │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_300_tbuff_ld_fmt_x_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_300_tbuff_ld_fmt_x_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_301_tbuff_ld_fmt_xyzw │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_301_tbuff_ld_fmt_xyzw_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_301_tbuff_ld_fmt_xyzw_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_302_tbuff_st_fmt_x │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_302_tbuff_st_fmt_x_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_302_tbuff_st_fmt_x_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_303_tbuff_st_fmt_xyzw │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_303_tbuff_st_fmt_xyzw_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_303_tbuff_st_fmt_xyzw_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ ├── test_304_ds_wr_b32 │ │ ├── kernel_0 │ │ │ ├── config_0.txt │ │ │ ├── data_0.mem │ │ │ ├── instr_0.mem │ │ │ └── test_304_ds_wr_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_304_ds_wr_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem │ └── test_305_ds_rd_b32 │ │ ├── kernel_0 │ │ ├── config_0.txt │ │ ├── data_0.mem │ │ ├── instr_0.mem │ │ └── test_305_ds_rd_b32_trace_0_0_0 │ │ ├── stage_cu.c │ │ ├── test_305_ds_rd_b32_trace │ │ ├── unit_test_config.txt │ │ ├── unit_test_data.mem │ │ └── unit_test_instr.mem ├── siagen │ ├── Makefile │ ├── asm.cpp │ ├── asm.h │ ├── helper.cpp │ ├── helper.h │ ├── main.cpp │ ├── siagen.cpp │ └── siagen.h └── xilinx_sdk │ └── main.c └── verilog ├── .gitignore ├── make ├── rtl.mk ├── tb.mk ├── test.mk └── veriperl.mk ├── rtl ├── Makefile ├── alu │ ├── Makefile │ ├── PS_flops_EX_WB_alu.v │ ├── PS_flops_issue_alu.v │ ├── alu.v │ ├── alu_controller.v │ ├── alu_definitions.v │ ├── alu_fsm.v │ ├── alu_wb_queue.v │ ├── dest_shift_reg.v │ ├── mux_2_to_1.v │ ├── shift_in.v │ ├── shift_out.v │ ├── src_mux.v │ ├── src_shift_reg.v │ └── valu.v ├── common │ ├── .gitignore │ ├── Makefile │ ├── adder1bit.v │ ├── adder_param.v │ ├── circular_barrel_shift.v │ ├── decoder_10_to_1024.vp │ ├── decoder_6_to_40.vp │ ├── decoder_6b_40b_en.v │ ├── decoder_9_to_512.vp │ ├── decoder_param.v │ ├── decoder_param_en.v │ ├── dff.v │ ├── dff_en.v │ ├── dff_set.v │ ├── dff_set_en.v │ ├── dff_set_en_rst.v │ ├── encoder.v │ ├── encoder_5b_3b.v │ ├── flop.v │ ├── flop_32b.v │ ├── flop_en.v │ ├── global_definitions.v │ ├── issue_definitions.v │ ├── mux2_1.v │ ├── mux_40x64b_to_1x64b.vp │ ├── mux_40xX_to_1xX.vp │ ├── mux_param.v │ ├── nand2.v │ ├── not1.v │ ├── priority_encoder_40to6.v │ ├── queue_param_1r_1w.v │ ├── reg_32b.v │ ├── reg_40b.v │ ├── reg_40b_set.v │ ├── reg_40xX_1r_1w.v │ ├── reg_40xX_2r_1w.v │ ├── reg_64b.v │ ├── reg_param.v │ ├── regfile.v │ └── register.v ├── compute_unit │ ├── Makefile │ ├── compute_unit.interface │ └── compute_unit.vp ├── decode │ ├── Makefile │ ├── PS_flops_wavepool_decode.v │ ├── decode.interface │ ├── decode.v │ ├── decode_core.v │ ├── decode_definitions.v │ ├── flag_generator.v │ ├── instr_collate.v │ └── reg_field_encoder.v ├── dispatcher │ ├── .gitignore │ ├── Makefile │ ├── allocator.v │ ├── cam_allocator.v │ ├── cu_handler.v │ ├── dis_controller.v │ ├── dispatcher.v │ ├── gds_resource_table.v │ ├── global_resource_table.v │ ├── gpu_interface.v │ ├── inflight_wg_buffer.v │ ├── ram_2_port.v │ ├── resource_table.v │ ├── resource_update_buffer.v │ ├── sim │ │ ├── allocator.do │ │ ├── allocator │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── allocator_tb.v │ │ │ └── wave.do │ │ ├── dis_controller │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── dis_controller_tb.v │ │ │ └── wave.do │ │ ├── dispatcher │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── dispatcher_tb.v │ │ │ └── wave.do │ │ ├── filelists │ │ │ ├── allocator │ │ │ └── resource_table │ │ ├── global_resource_table │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── global_resource_table_tb.v │ │ │ └── wave.do │ │ ├── gpu_interface │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── gpu_interface_tb.v │ │ │ └── wave.do │ │ ├── inflight_wg_buffer │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── inflight_wg_buffer_tb.v │ │ │ ├── wave.do │ │ │ └── work │ │ │ │ ├── compile.do │ │ │ │ ├── sim.do │ │ │ │ └── wave.do │ │ ├── resource_table.do │ │ ├── resource_table │ │ │ ├── compile.do │ │ │ ├── sim.do │ │ │ ├── src │ │ │ │ └── resource_table_tb.v │ │ │ └── wave.do │ │ └── src │ │ │ ├── cu_simulator.v │ │ │ ├── dispatcher_checker.v │ │ │ ├── host_test.v │ │ │ └── resource_table_tb.v │ └── wg_resource_table.v ├── exec │ ├── Makefile │ ├── exec.interface │ ├── exec.v │ ├── rd_port_9_to_1.v │ ├── reg_40xX_1r_2w.vp │ ├── reg_40xX_2r_2w.vp │ ├── reg_40xX_2r_3w.vp │ └── wr_port_40x64b_8_to_1.v ├── fetch │ ├── Makefile │ ├── add_wraparound_after40.v │ ├── adder.v │ ├── adder6bit.v │ ├── adder7bit.v │ ├── decoder.v │ ├── dff_clr.v │ ├── dff_en_fixed_reset_value.v │ ├── fetch.interface │ ├── fetch.v │ ├── fetch.v.bk │ ├── fetch_controller.v │ ├── incr_wraparound_at40.v │ ├── mask_gen.v │ ├── mux4to1_6bit.v │ ├── pc_block.v │ ├── regblock.v │ ├── regfile_clr.v │ ├── round_robin.v │ ├── special_decode.vp.bk │ ├── vacant_mask_gen.v │ ├── wavegrp_info.v │ └── wfid_generator.v ├── fpga │ ├── compute_unit_fpga.v │ ├── fpga_memory.v │ ├── reg_128x32b_3r_2w_fpga.v │ └── reg_256x32b_3r_1w_fpga.v ├── fpga_make.sh ├── instr_buffer │ ├── Makefile │ ├── instr_buffer.interface │ └── instr_buffer.v ├── issue │ ├── Makefile │ ├── alu_issue_logic.v │ ├── arbiter.v │ ├── barrier_wait.v │ ├── branch_wait.v │ ├── busy_gpr_table.v │ ├── circular_barrel_shift_5b.v │ ├── finished_wf.v │ ├── functional_unit_reg.v │ ├── functional_unit_reg_bank.v │ ├── gpr_dependency_table.vp │ ├── inflight_instr_counter.v │ ├── instr_info_table.v │ ├── instruction_arbiter.v │ ├── issue.interface │ ├── issue.v │ ├── issue_flow_control.v │ ├── issue_scoreboard_v │ ├── mem_wait.v │ ├── mux_40xPARAMb_to_1xPARAMb.v │ ├── ready_bits_demux.vp │ ├── scoreboard.v │ ├── sgpr_busy_table_decoder.v │ ├── sgpr_busy_table_decoder.vp │ ├── sgpr_busy_table_mux.v │ ├── sgpr_busy_table_mux.vp │ ├── sgpr_comparator.v │ ├── spr_dependency_table.v │ ├── valid_entry.v │ ├── vgpr_busy_table_decoder.v │ ├── vgpr_busy_table_decoder.vp │ ├── vgpr_busy_table_mux.v │ ├── vgpr_busy_table_mux.vp │ └── vgpr_comparator.v ├── lsu │ ├── Makefile │ ├── ds_addr_calc.v │ ├── lsu.interface │ ├── lsu.v │ ├── lsu_addr_calculator.v │ ├── lsu_definitions.v │ ├── lsu_op_manager.v │ ├── lsu_opcode_decoder.v │ └── mtbuf_addr_calc.v ├── memory │ ├── Makefile │ ├── cachesim.c │ ├── memory.interface │ └── memory.v ├── rfa │ ├── Makefile │ ├── circular_shift.v │ ├── priority_encoder_16_to_4.v │ ├── rfa.interface │ └── rfa.v ├── salu │ ├── Makefile │ ├── salu.interface │ ├── salu.vp │ ├── salu_controller.v │ └── scalar_alu.v ├── sgpr │ ├── Makefile │ ├── mux_128x32b_to_1x32b.vp │ ├── reg_128x32b_3r_2w.vp │ ├── reg_128x32b_3r_3w.vp │ ├── reg_512x32b_3r_2w.v │ ├── reg_512x32b_3r_3w.v │ ├── sgpr.interface │ ├── sgpr.v │ ├── sgpr_3to1_rd_port_mux.v │ ├── sgpr_simx_rd_port_mux.v │ ├── sgpr_simx_wr_port_mux.v │ └── sgpr_simxlsu_wr_port_mux.v ├── simd │ ├── Makefile │ ├── amultp2_32x32.v │ ├── simd.interface │ ├── simd.v │ ├── simd_alu.v │ └── simd_instr_decoder.v ├── simf │ ├── Makefile │ ├── README │ ├── ToDosRag │ ├── fpu_addsub.v │ ├── fpu_arith.v │ ├── fpu_div.v │ ├── fpu_intfloat_conv.v │ ├── fpu_intfloat_conv_except.v │ ├── fpu_mul.v │ ├── fpu_post_norm_addsub.v │ ├── fpu_post_norm_div.v │ ├── fpu_post_norm_intfloat_conv.v │ ├── fpu_post_norm_mul.v │ ├── fpu_pre_norm_addsub.v │ ├── fpu_pre_norm_div.v │ ├── fpu_pre_norm_mul.v │ ├── simf.interface │ ├── simf.v │ ├── simf_alu.v │ └── simf_instr_decoder.v ├── tracemon │ ├── .gitignore │ ├── Makefile │ ├── tracemon.c │ ├── tracemon.h │ ├── tracemon.vp │ └── vgpr_contention_tracker.v ├── vgpr │ ├── Makefile │ ├── mux_256x32b_to_1x32b.vp │ ├── rd_port_mux_8to1.v │ ├── reg_1024x32b_3r_1w.v │ ├── reg_1024x32b_3r_2w.vp │ ├── reg_1024x32b_3r_2w_banked.vp │ ├── reg_256x32b_3r_1w.v │ ├── reg_256x32b_3r_2w.vp │ ├── reg_64page_1024x32b_3r_1w.vp │ ├── reg_64page_1024x32b_3r_2w.vp │ ├── vgpr.interface │ ├── vgpr.v │ ├── vgpr_2to1_rd_port_mux.v │ ├── wfid_mux_8to1.v │ ├── wfid_mux_9to1.v │ ├── wr_port_mux_8to1.v │ └── wr_port_mux_9to1.v └── wavepool │ ├── Makefile │ ├── PS_flops_fetch_wavepool.v │ ├── adder3bit.v │ ├── decoder_3_to_8.vp │ ├── mux_40x35b_to_1x35b.vp │ ├── mux_8x64b_to_1x64b.vp │ ├── queue_controller.v │ ├── reg_35b.v │ ├── reg_3b.v │ ├── reg_40x35b_1r_1w.v │ ├── reg_8x64b_1r_1w.v │ ├── scbd_feeder.v │ ├── wave_queue.v │ ├── wavepool.interface │ ├── wavepool.vp │ ├── wavepool_controller.v │ └── wq_pool.v └── tb ├── .gitignore ├── Makefile ├── decode ├── Makefile ├── decode_tb.v └── session.vcdplus.vpd.tcl ├── dispatcher_wrapper ├── dispatcher_hard.v ├── dispatcher_hard_host.v ├── dispatcher_soft.v └── dispatcher_wrapper.v ├── exec ├── Makefile └── exec_tb.v ├── fetch ├── Makefile ├── fetch_tb.v └── test_round_robin.v ├── fpu ├── Makefile └── fpu_tb.v ├── gpu_tb.v ├── instr_buffer ├── Makefile └── instr_buffer_tb.v ├── issue ├── Makefile ├── debug_alu_issue.tcl ├── debug_spr.tcl ├── debug_wave_configurations │ ├── gpu_test_issue_alu.tcl │ └── gpu_test_issue_alu_sb_info.tcl ├── input.trace ├── issue_tb.v ├── output.trace ├── salu_input.trace ├── salu_output.trace ├── session.vcdplus.vpd.tcl ├── tester.v ├── valu_input.trace └── valu_output.trace ├── lsu ├── Makefile ├── addr_calc_test.v └── lsu_tb.v ├── memory ├── Makefile └── memory_tb.v ├── rfa ├── Makefile └── rfa_tb.v ├── run.pl ├── salu ├── Makefile └── salu_tb.v ├── sgpr ├── Makefile └── sgpr_tb.v ├── simd ├── Makefile ├── session.vcdplus.vpd.tcl ├── session1.vcdplus.vpd.tcl ├── simd_tb.v └── vector_alu_tb.verilog ├── simf ├── Makefile ├── session.vcdplus.vpd.tcl └── simf_tb.v ├── tracefile_cmp.pl ├── tracemon ├── .gitignore ├── Makefile └── tracemon_tb.v ├── vgpr ├── Makefile └── vgpr_tb.v ├── wave.c ├── wave.h └── wavepool ├── Makefile ├── session.vcdplus.vpd.tcl └── wavepool_tb.v /.gitignore: -------------------------------------------------------------------------------- 1 | .project 2 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VerticalResearchGroup/miaow/HEAD/COPYING -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/VerticalResearchGroup/miaow/HEAD/README -------------------------------------------------------------------------------- /scripts/veriperl.pl: -------------------------------------------------------------------------------- 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