├── FPGA Design and Implementation of Electric Guitar Audio Effects - Project Report.pdf ├── LICENSE ├── Meffects_constants_testing_3.srcs.rar ├── Meffects_constants_testing_3_all_except_srcs.rar ├── README └── ip_repo ├── VL_user_Distortion_1.0 ├── VL_user_Distortion_1.0.zip ├── component.xml ├── sim_1 │ └── new │ │ └── Distortion_tb.vhd ├── sources_1 │ └── new │ │ └── Distortion.vhd └── xgui │ └── Distortion_v1_0.tcl ├── VL_user_MCLK_gen_1.0 ├── MCLK_gen.vhd ├── VL_user_MCLK_gen_1.0.zip ├── component.xml └── xgui │ └── MCLK_gen_v1_0.tcl ├── VL_user_PL_to_PS_1.0 ├── VL_user_PL_to_PS_1.0.zip ├── bd │ └── bd.tcl ├── component.xml ├── drivers │ └── PL_to_PS_v1_0 │ │ ├── data │ │ ├── PL_to_PS.mdd │ │ └── PL_to_PS.tcl │ │ └── src │ │ ├── Makefile │ │ ├── PL_to_PS.c │ │ ├── PL_to_PS.h │ │ └── PL_to_PS_selftest.c ├── hdl │ ├── PL_to_PS_v1_0.vhd │ └── PL_to_PS_v1_0_S00_AXI.vhd └── xgui │ └── PL_to_PS_v1_0.tcl ├── VL_user_PS_to_PL_1.0 ├── VL_user_PS_to_PL_1.0.zip ├── bd │ └── bd.tcl ├── component.xml ├── drivers │ └── PS_to_PL_v1_0 │ │ ├── data │ │ ├── PS_to_PL.mdd │ │ └── PS_to_PL.tcl │ │ └── src │ │ ├── Makefile │ │ ├── PS_to_PL.c │ │ ├── PS_to_PL.h │ │ └── PS_to_PL_selftest.c ├── hdl │ ├── PS_to_PL_v1_0.vhd │ └── PS_to_PL_v1_0_S00_AXI.vhd └── xgui │ └── PS_to_PL_v1_0.tcl ├── VL_user_clk_slow_1.0 ├── VL_user_clk_slow_1.0.zip ├── component.xml ├── sim_1 │ └── new │ │ └── clk_slow_tb.vhd ├── sources_1 │ └── new │ │ └── clk_slow.vhd └── xgui │ └── clk_slow_v1_0.tcl ├── VL_user_control_1.0 ├── VL_user_control_1.0.zip ├── component.xml ├── control.vhd ├── control_tb.vhd └── xgui │ └── control_v1_0.tcl ├── VL_user_delay_1.0 ├── VL_user_delay_1.0.zip ├── component.xml ├── sim_1 │ └── new │ │ └── delay_tb.vhd ├── sources_1 │ └── new │ │ ├── bram.vhd │ │ └── delay.vhd └── xgui │ └── delay_v1_0.tcl ├── VL_user_octaver_1.0 ├── VL_user_octaver_1.0.zip ├── component.xml ├── sim_1 │ └── new │ │ └── octaver_tb.vhd ├── sources_1 │ └── new │ │ ├── bram_oct.vhd │ │ └── octaver.vhd └── xgui │ └── octaver_v1_0.tcl ├── VL_user_trem_1.0 ├── VL_user_trem_1.0.zip ├── component.xml ├── sim_1 │ └── new │ │ └── trem_tb.vhd ├── sources_1 │ └── new │ │ └── trem.vhd └── xgui │ └── trem_v1_0.tcl └── zed_audio_ctrl ├── component.xml ├── xgui └── i2s_ctrl_v1_0.tcl ├── zed_audio_ctrl.srcs └── sources_1 │ └── imports │ └── i2s_audio │ ├── address_decoder.vhd │ ├── axi_lite_ipif.vhd │ ├── common_types.vhd │ ├── family_support.vhd │ ├── i2s_ctrl.vhd │ ├── iis_deser.vhd │ ├── iis_ser.vhd │ ├── pselect_f.vhd │ ├── slave_attachment.vhd │ └── user_logic.vhd └── zed_audio_ctrl.zip /FPGA Design and Implementation of Electric Guitar Audio Effects - Project Report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/FPGA Design and Implementation of Electric Guitar Audio Effects - Project Report.pdf -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/LICENSE -------------------------------------------------------------------------------- /Meffects_constants_testing_3.srcs.rar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/Meffects_constants_testing_3.srcs.rar -------------------------------------------------------------------------------- /Meffects_constants_testing_3_all_except_srcs.rar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/Meffects_constants_testing_3_all_except_srcs.rar -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/README -------------------------------------------------------------------------------- /ip_repo/VL_user_Distortion_1.0/VL_user_Distortion_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_Distortion_1.0/VL_user_Distortion_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_Distortion_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_Distortion_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_Distortion_1.0/sim_1/new/Distortion_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_Distortion_1.0/sim_1/new/Distortion_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_Distortion_1.0/sources_1/new/Distortion.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_Distortion_1.0/sources_1/new/Distortion.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_Distortion_1.0/xgui/Distortion_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_Distortion_1.0/xgui/Distortion_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_MCLK_gen_1.0/MCLK_gen.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_MCLK_gen_1.0/MCLK_gen.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_MCLK_gen_1.0/VL_user_MCLK_gen_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_MCLK_gen_1.0/VL_user_MCLK_gen_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_MCLK_gen_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_MCLK_gen_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_MCLK_gen_1.0/xgui/MCLK_gen_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_MCLK_gen_1.0/xgui/MCLK_gen_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/VL_user_PL_to_PS_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/VL_user_PL_to_PS_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/bd/bd.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/data/PL_to_PS.mdd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/data/PL_to_PS.mdd -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/data/PL_to_PS.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/data/PL_to_PS.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/Makefile -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS.c -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS.h -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS_selftest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/drivers/PL_to_PS_v1_0/src/PL_to_PS_selftest.c -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0_S00_AXI.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/hdl/PL_to_PS_v1_0_S00_AXI.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_PL_to_PS_1.0/xgui/PL_to_PS_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PL_to_PS_1.0/xgui/PL_to_PS_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/VL_user_PS_to_PL_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/VL_user_PS_to_PL_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/bd/bd.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/bd/bd.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/data/PS_to_PL.mdd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/data/PS_to_PL.mdd -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/data/PS_to_PL.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/data/PS_to_PL.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/Makefile -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL.c -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL.h -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL_selftest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/drivers/PS_to_PL_v1_0/src/PS_to_PL_selftest.c -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0_S00_AXI.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/hdl/PS_to_PL_v1_0_S00_AXI.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_PS_to_PL_1.0/xgui/PS_to_PL_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_PS_to_PL_1.0/xgui/PS_to_PL_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_clk_slow_1.0/VL_user_clk_slow_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_clk_slow_1.0/VL_user_clk_slow_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_clk_slow_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_clk_slow_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_clk_slow_1.0/sim_1/new/clk_slow_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_clk_slow_1.0/sim_1/new/clk_slow_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_clk_slow_1.0/sources_1/new/clk_slow.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_clk_slow_1.0/sources_1/new/clk_slow.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_clk_slow_1.0/xgui/clk_slow_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_clk_slow_1.0/xgui/clk_slow_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_control_1.0/VL_user_control_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_control_1.0/VL_user_control_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_control_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_control_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_control_1.0/control.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_control_1.0/control.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_control_1.0/control_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_control_1.0/control_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_control_1.0/xgui/control_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_control_1.0/xgui/control_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/VL_user_delay_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/VL_user_delay_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/sim_1/new/delay_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/sim_1/new/delay_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/sources_1/new/bram.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/sources_1/new/bram.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/sources_1/new/delay.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/sources_1/new/delay.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_delay_1.0/xgui/delay_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_delay_1.0/xgui/delay_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/VL_user_octaver_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/VL_user_octaver_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/sim_1/new/octaver_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/sim_1/new/octaver_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/sources_1/new/bram_oct.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/sources_1/new/bram_oct.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/sources_1/new/octaver.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/sources_1/new/octaver.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_octaver_1.0/xgui/octaver_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_octaver_1.0/xgui/octaver_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/VL_user_trem_1.0/VL_user_trem_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_trem_1.0/VL_user_trem_1.0.zip -------------------------------------------------------------------------------- /ip_repo/VL_user_trem_1.0/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_trem_1.0/component.xml -------------------------------------------------------------------------------- /ip_repo/VL_user_trem_1.0/sim_1/new/trem_tb.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_trem_1.0/sim_1/new/trem_tb.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_trem_1.0/sources_1/new/trem.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_trem_1.0/sources_1/new/trem.vhd -------------------------------------------------------------------------------- /ip_repo/VL_user_trem_1.0/xgui/trem_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/VL_user_trem_1.0/xgui/trem_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/component.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/component.xml -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/xgui/i2s_ctrl_v1_0.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/xgui/i2s_ctrl_v1_0.tcl -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/address_decoder.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/address_decoder.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/axi_lite_ipif.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/axi_lite_ipif.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/common_types.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/common_types.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/family_support.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/family_support.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/i2s_ctrl.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/i2s_ctrl.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_deser.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_deser.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_ser.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/iis_ser.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/pselect_f.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/pselect_f.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/user_logic.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/user_logic.vhd -------------------------------------------------------------------------------- /ip_repo/zed_audio_ctrl/zed_audio_ctrl.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Vladilit/fpga-multi-effect/HEAD/ip_repo/zed_audio_ctrl/zed_audio_ctrl.zip --------------------------------------------------------------------------------