├── TrueStudio
└── W5x00-HTTPClient
│ ├── .gitignore
│ ├── Src
│ ├── syscalls.c
│ ├── wizchip_init.c
│ ├── stm32f4xx_it.c
│ ├── stm32f4xx_hal_msp.c
│ └── httpClient.c
│ ├── .settings
│ ├── org.eclipse.cdt.ui.prefs
│ ├── com.atollic.truestudio.tsp.prefs
│ ├── com.atollic.truestudio.debug.hardware_device.prefs
│ ├── org.eclipse.cdt.managedbuilder.core.prefs
│ ├── language.settings.xml
│ ├── org.eclipse.cdt.codan.core.prefs
│ └── org.eclipse.cdt.core.prefs
│ ├── Drivers
│ ├── CMSIS
│ │ ├── Device
│ │ │ └── ST
│ │ │ │ └── STM32F4xx
│ │ │ │ └── Include
│ │ │ │ ├── stm32f4xx.h
│ │ │ │ └── system_stm32f4xx.h
│ │ └── Include
│ │ │ ├── cmsis_version.h
│ │ │ ├── tz_context.h
│ │ │ ├── cmsis_compiler.h
│ │ │ ├── mpu_armv8.h
│ │ │ └── mpu_armv7.h
│ └── STM32F4xx_HAL_Driver
│ │ ├── Inc
│ │ ├── stm32f4xx_hal_flash_ramfunc.h
│ │ ├── stm32f4xx_hal_dma_ex.h
│ │ ├── stm32f4xx_hal_def.h
│ │ ├── stm32f4xx_hal_gpio.h
│ │ └── stm32f4xx_hal.h
│ │ └── Src
│ │ ├── stm32f4xx_hal_flash_ramfunc.c
│ │ └── stm32f4xx_hal_dma_ex.c
│ ├── Inc
│ ├── wizchip_init.h
│ ├── stm32f4xx_it.h
│ ├── main.h
│ ├── httpClient.h
│ └── webpage.h
│ ├── .project
│ ├── .code_review_properties
│ ├── W5x00-HTTPClient.ioc
│ ├── W5x00-HTTPClient.elf.launch
│ ├── W5x00-HTTPServer.elf.launch
│ ├── Debug_STM32F401RE_FLASH.ld
│ └── .mxproject
├── .gitmodules
└── README.md
/TrueStudio/W5x00-HTTPClient/.gitignore:
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1 | /Debug/
2 |
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/.gitmodules:
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1 | [submodule "ioLibrary_Driver"]
2 | path = ioLibrary_Driver
3 | url = https://github.com/Wiznet/ioLibrary_Driver
4 |
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/TrueStudio/W5x00-HTTPClient/Src/syscalls.c:
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https://raw.githubusercontent.com/WIZnet-ioLibrary/W5x00-HTTPClient/HEAD/TrueStudio/W5x00-HTTPClient/Src/syscalls.c
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/TrueStudio/W5x00-HTTPClient/.settings/org.eclipse.cdt.ui.prefs:
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1 | eclipse.preferences.version=1
2 | formatter_profile=_becky_profile
3 | formatter_settings_version=1
4 |
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/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
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https://raw.githubusercontent.com/WIZnet-ioLibrary/W5x00-HTTPClient/HEAD/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
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/TrueStudio/W5x00-HTTPClient/.settings/com.atollic.truestudio.tsp.prefs:
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1 | eclipse.preferences.version=1
2 | svd_custom_file_path=
3 | svd_file_path=C\:\\Program Files (x86)\\Atollic\\TrueSTUDIO for STM32 9.2.0\\ide\\plugins\\com.atollic.truestudio.tsp.stm32_1.0.0.20181203-0921\\tsp\\sfr\\STM32F411.svd
4 |
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/TrueStudio/W5x00-HTTPClient/.settings/com.atollic.truestudio.debug.hardware_device.prefs:
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1 | BOARD=None
2 | CODE_LOCATION=FLASH
3 | ENDIAN=Little-endian
4 | MCU=default
5 | MCU_VENDOR=STMicroelectronics
6 | MODEL=Lite
7 | PROBE=ST-LINK
8 | PROJECT_FORMAT_VERSION=2
9 | TARGET=ARM\u00AE
10 | VERSION=4.1.0
11 | eclipse.preferences.version=1
12 |
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/TrueStudio/W5x00-HTTPClient/Inc/wizchip_init.h:
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1 | #ifndef __WIZCHIP_INIT_H__
2 | #define __WIZCHIP_INIT_H__
3 |
4 |
5 | #include "main.h"
6 | #include "wizchip_conf.h"
7 |
8 |
9 |
10 |
11 |
12 |
13 | /* CS */
14 | extern SPI_HandleTypeDef hspi1;
15 | #define WIZCHIP_SPI hspi1
16 | #define WIZCHIP_CS_PIN GPIO_PIN_6
17 | #define WIZCHIP_CS_PORT GPIOB
18 |
19 |
20 | void WIZCHIPInitialize();
21 |
22 | #define W5x00_RESET_PIN W5x00_RESET_Pin
23 | #define W5x00_RESET_PORT W5x00_RESET_GPIO_Port
24 |
25 | void csEnable(void);
26 | void csDisable(void);
27 | void spiWriteByte(uint8_t tx);
28 | uint8_t spiReadByte(void);
29 |
30 | #endif
31 |
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/TrueStudio/W5x00-HTTPClient/.settings/org.eclipse.cdt.managedbuilder.core.prefs:
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1 | eclipse.preferences.version=1
2 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/delimiter=;
3 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/operation=remove
4 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/delimiter=;
5 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/operation=remove
6 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/append=true
7 | environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true
8 | environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/delimiter=;
9 | environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/operation=remove
10 | environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/append=true
11 | environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true
12 |
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/TrueStudio/W5x00-HTTPClient/.settings/language.settings.xml:
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
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/README.md:
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1 | # W5x00-HTTPClient
2 | The HTTPCleint Example for W5x00 using ioLibrary
3 |
4 | # Hardware Configuration
5 |
6 | | | | | |
7 | | ------------------------- | :----------------------------------------------------------: | :----------------------------------------------------------: | :----------------------------------------------------------: |
8 | | **BaseBoard for Example** | | NUCLEO-F401RE | |
9 | | **io module** | WIZ810Sio(W5100S) | WIZ850io(W5500) | W820io(W5200) |
10 | | **mj module** | WIZ812MJ(W5100) | | |
11 |
12 |
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/TrueStudio/W5x00-HTTPClient/Src/wizchip_init.c:
--------------------------------------------------------------------------------
1 | /*
2 | * wizchip_init.c
3 | *
4 | * Created on: Nov 28, 2019
5 | * Author: becky
6 | */
7 |
8 | #include "wizchip_init.h"
9 |
10 |
11 | void WIZCHIPInitialize(){
12 |
13 | csDisable();
14 | reg_wizchip_spi_cbfunc(spiReadByte, spiWriteByte);
15 | reg_wizchip_cs_cbfunc(csEnable, csDisable);
16 |
17 |
18 | uint8_t tmp;
19 | //w5500, w5200
20 | #if _WIZCHIP_ >= W5200
21 | uint8_t memsize[2][8] = { {2,2,2,2,2,2,2,2},{2,2,2,2,2,2,2,2}};
22 | #else
23 | uint8_t memsize[2][4] = { {2,2,2,2},{2,2,2,2}};
24 | #endif
25 | if(ctlwizchip(CW_INIT_WIZCHIP,(void*)memsize) == -1)
26 | {
27 | //myprintf("WIZCHIP Initialized fail.\r\n");
28 | printf("WIZCHIP Initialized fail.\r\n", 1, 10);
29 | return;
30 | }
31 | /* PHY link status check */
32 | do {
33 | if(ctlwizchip(CW_GET_PHYLINK, (void*)&tmp) == -1)
34 | {
35 | printf("Unknown PHY Link status.\r\n", 1, 10);
36 | return;
37 | }
38 | } while (tmp == PHY_LINK_OFF);
39 |
40 |
41 |
42 | }
43 |
44 |
45 | void resetAssert(void)
46 | {
47 | HAL_GPIO_WritePin(W5x00_RESET_PORT, W5x00_RESET_PIN, GPIO_PIN_RESET);
48 | }
49 |
50 | void resetDeassert(void)
51 | {
52 | HAL_GPIO_WritePin(W5x00_RESET_PORT, W5x00_RESET_PIN, GPIO_PIN_SET);
53 | }
54 |
55 | void csEnable(void)
56 | {
57 | HAL_GPIO_WritePin(WIZCHIP_CS_PORT, WIZCHIP_CS_PIN, GPIO_PIN_RESET);
58 | }
59 |
60 | void csDisable(void)
61 | {
62 | HAL_GPIO_WritePin(WIZCHIP_CS_PORT, WIZCHIP_CS_PIN, GPIO_PIN_SET);
63 | }
64 |
65 | void spiWriteByte(uint8_t tx)
66 | {
67 | uint8_t rx;
68 | HAL_SPI_TransmitReceive(&WIZCHIP_SPI, &tx, &rx, 1, 10);
69 | }
70 |
71 | uint8_t spiReadByte(void)
72 | {
73 | uint8_t rx = 0, tx = 0xFF;
74 | HAL_SPI_TransmitReceive(&WIZCHIP_SPI, &tx, &rx, 1, 10);
75 | return rx;
76 | }
77 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
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/TrueStudio/W5x00-HTTPClient/Inc/stm32f4xx_it.h:
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1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | *
© Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_IT_H
23 | #define __STM32F4xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void SVC_Handler(void);
56 | void DebugMon_Handler(void);
57 | void PendSV_Handler(void);
58 | void SysTick_Handler(void);
59 | /* USER CODE BEGIN EFP */
60 |
61 | /* USER CODE END EFP */
62 |
63 | #ifdef __cplusplus
64 | }
65 | #endif
66 |
67 | #endif /* __STM32F4xx_IT_H */
68 |
69 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
70 |
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/TrueStudio/W5x00-HTTPClient/Inc/main.h:
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1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2019 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 | /* USER CODE END ET */
41 |
42 | /* Exported constants --------------------------------------------------------*/
43 | /* USER CODE BEGIN EC */
44 |
45 | /* USER CODE END EC */
46 |
47 | /* Exported macro ------------------------------------------------------------*/
48 | /* USER CODE BEGIN EM */
49 |
50 | /* USER CODE END EM */
51 |
52 | /* Exported functions prototypes ---------------------------------------------*/
53 | void Error_Handler(void);
54 |
55 | /* USER CODE BEGIN EFP */
56 |
57 | /* USER CODE END EFP */
58 |
59 | /* Private defines -----------------------------------------------------------*/
60 | #define W5x00_RESET_Pin GPIO_PIN_7
61 | #define W5x00_RESET_GPIO_Port GPIOC
62 | /* USER CODE BEGIN Private defines */
63 |
64 | /* USER CODE END Private defines */
65 |
66 | #ifdef __cplusplus
67 | }
68 | #endif
69 |
70 | #endif /* __MAIN_H */
71 |
72 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
73 |
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/TrueStudio/W5x00-HTTPClient/.project:
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1 |
2 |
3 | W5x00-HTTPClient
4 |
5 |
6 |
7 |
8 |
9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder
10 | clean,full,incremental,
11 |
12 |
13 | ?children?
14 | ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||
15 |
16 |
17 | ?name?
18 |
19 |
20 |
21 | org.eclipse.cdt.make.core.append_environment
22 | true
23 |
24 |
25 | org.eclipse.cdt.make.core.buildArguments
26 |
27 |
28 |
29 | org.eclipse.cdt.make.core.buildCommand
30 | make
31 |
32 |
33 | org.eclipse.cdt.make.core.buildLocation
34 | ${workspace_loc:/STM32100B-EVAL/Debug}
35 |
36 |
37 | org.eclipse.cdt.make.core.contents
38 | org.eclipse.cdt.make.core.activeConfigSettings
39 |
40 |
41 | org.eclipse.cdt.make.core.enableAutoBuild
42 | false
43 |
44 |
45 | org.eclipse.cdt.make.core.enableCleanBuild
46 | true
47 |
48 |
49 | org.eclipse.cdt.make.core.enableFullBuild
50 | true
51 |
52 |
53 | org.eclipse.cdt.make.core.stopOnError
54 | true
55 |
56 |
57 | org.eclipse.cdt.make.core.useDefaultBuildCmd
58 | true
59 |
60 |
61 |
62 |
63 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
64 |
65 |
66 |
67 |
68 |
69 | org.eclipse.cdt.core.cnature
70 | org.eclipse.cdt.managedbuilder.core.managedBuildNature
71 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
72 |
73 |
74 |
75 | ioLibrary_Driver
76 | 2
77 | PARENT-2-PROJECT_LOC/ioLibrary_Driver
78 |
79 |
80 |
81 |
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/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH RAMFUNC driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H
22 | #define __STM32F4xx_FLASH_RAMFUNC_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
28 | defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_hal_def.h"
32 |
33 | /** @addtogroup STM32F4xx_HAL_Driver
34 | * @{
35 | */
36 |
37 | /** @addtogroup FLASH_RAMFUNC
38 | * @{
39 | */
40 |
41 | /* Exported types ------------------------------------------------------------*/
42 | /* Exported macro ------------------------------------------------------------*/
43 | /* Exported functions --------------------------------------------------------*/
44 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions
45 | * @{
46 | */
47 |
48 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
49 | * @{
50 | */
51 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
52 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
54 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
55 | /**
56 | * @}
57 | */
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
72 | #ifdef __cplusplus
73 | }
74 | #endif
75 |
76 |
77 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
78 |
79 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
80 |
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/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Include/tz_context.h:
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1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
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/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of DMA HAL extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_DMA_EX_H
22 | #define __STM32F4xx_HAL_DMA_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup DMAEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
41 | * @brief DMAEx Exported types
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief HAL DMA Memory definition
47 | */
48 | typedef enum
49 | {
50 | MEMORY0 = 0x00U, /*!< Memory 0 */
51 | MEMORY1 = 0x01U /*!< Memory 1 */
52 | }HAL_DMA_MemoryTypeDef;
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /* Exported functions --------------------------------------------------------*/
59 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
60 | * @brief DMAEx Exported functions
61 | * @{
62 | */
63 |
64 | /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
65 | * @brief Extended features functions
66 | * @{
67 | */
68 |
69 | /* IO operation functions *******************************************************/
70 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
71 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
72 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
73 |
74 | /**
75 | * @}
76 | */
77 | /**
78 | * @}
79 | */
80 |
81 | /* Private functions ---------------------------------------------------------*/
82 | /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
83 | * @brief DMAEx Private functions
84 | * @{
85 | */
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #ifdef __cplusplus
99 | }
100 | #endif
101 |
102 | #endif /*__STM32F4xx_HAL_DMA_EX_H*/
103 |
104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
105 |
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/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
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1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f4xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2017 STMicroelectronics
10 | *
11 | * Redistribution and use in source and binary forms, with or without modification,
12 | * are permitted provided that the following conditions are met:
13 | * 1. Redistributions of source code must retain the above copyright notice,
14 | * this list of conditions and the following disclaimer.
15 | * 2. Redistributions in binary form must reproduce the above copyright notice,
16 | * this list of conditions and the following disclaimer in the documentation
17 | * and/or other materials provided with the distribution.
18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 | * may be used to endorse or promote products derived from this software
20 | * without specific prior written permission.
21 | *
22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 | *
33 | ******************************************************************************
34 | */
35 |
36 | /** @addtogroup CMSIS
37 | * @{
38 | */
39 |
40 | /** @addtogroup stm32f4xx_system
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief Define to prevent recursive inclusion
46 | */
47 | #ifndef __SYSTEM_STM32F4XX_H
48 | #define __SYSTEM_STM32F4XX_H
49 |
50 | #ifdef __cplusplus
51 | extern "C" {
52 | #endif
53 |
54 | /** @addtogroup STM32F4xx_System_Includes
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 |
63 | /** @addtogroup STM32F4xx_System_Exported_types
64 | * @{
65 | */
66 | /* This variable is updated in three ways:
67 | 1) by calling CMSIS function SystemCoreClockUpdate()
68 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
69 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
70 | Note: If you use this function to configure the system clock; then there
71 | is no need to call the 2 first functions listed above, since SystemCoreClock
72 | variable is updated automatically.
73 | */
74 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
75 |
76 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
77 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /** @addtogroup STM32F4xx_System_Exported_Constants
84 | * @{
85 | */
86 |
87 | /**
88 | * @}
89 | */
90 |
91 | /** @addtogroup STM32F4xx_System_Exported_Macros
92 | * @{
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | /** @addtogroup STM32F4xx_System_Exported_Functions
100 | * @{
101 | */
102 |
103 | extern void SystemInit(void);
104 | extern void SystemCoreClockUpdate(void);
105 | /**
106 | * @}
107 | */
108 |
109 | #ifdef __cplusplus
110 | }
111 | #endif
112 |
113 | #endif /*__SYSTEM_STM32F4XX_H */
114 |
115 | /**
116 | * @}
117 | */
118 |
119 | /**
120 | * @}
121 | */
122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
123 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/W5x00-HTTPClient.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | KeepUserPlacement=false
4 | Mcu.Family=STM32F4
5 | Mcu.IP0=NVIC
6 | Mcu.IP1=RCC
7 | Mcu.IP2=SPI1
8 | Mcu.IP3=SYS
9 | Mcu.IP4=USART2
10 | Mcu.IPNb=5
11 | Mcu.Name=STM32F401R(D-E)Tx
12 | Mcu.Package=LQFP64
13 | Mcu.Pin0=PA2
14 | Mcu.Pin1=PA3
15 | Mcu.Pin2=PA5
16 | Mcu.Pin3=PA6
17 | Mcu.Pin4=PA7
18 | Mcu.Pin5=PC7
19 | Mcu.Pin6=PB6
20 | Mcu.Pin7=VP_SYS_VS_Systick
21 | Mcu.PinsNb=8
22 | Mcu.ThirdPartyNb=0
23 | Mcu.UserConstants=
24 | Mcu.UserName=STM32F401RETx
25 | MxCube.Version=5.4.0
26 | MxDb.Version=DB.5.0.40
27 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
28 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
29 | NVIC.ForceEnableDMAVector=true
30 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
31 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
32 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
33 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
34 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
35 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
36 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
37 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
38 | PA2.Mode=Asynchronous
39 | PA2.Signal=USART2_TX
40 | PA3.Mode=Asynchronous
41 | PA3.Signal=USART2_RX
42 | PA5.Mode=Full_Duplex_Master
43 | PA5.Signal=SPI1_SCK
44 | PA6.Mode=Full_Duplex_Master
45 | PA6.Signal=SPI1_MISO
46 | PA7.Mode=Full_Duplex_Master
47 | PA7.Signal=SPI1_MOSI
48 | PB6.Locked=true
49 | PB6.Signal=GPIO_Output
50 | PC7.GPIOParameters=GPIO_Label
51 | PC7.GPIO_Label=W5x00_RESET
52 | PC7.Locked=true
53 | PC7.Signal=GPIO_Output
54 | PCC.Checker=false
55 | PCC.Line=STM32F401
56 | PCC.MCU=STM32F401R(D-E)Tx
57 | PCC.PartNumber=STM32F401RETx
58 | PCC.Seq0=0
59 | PCC.Series=STM32F4
60 | PCC.Temperature=25
61 | PCC.Vdd=3.3
62 | PinOutPanel.RotationAngle=0
63 | ProjectManager.AskForMigrate=true
64 | ProjectManager.BackupPrevious=false
65 | ProjectManager.CompilerOptimize=6
66 | ProjectManager.ComputerToolchain=false
67 | ProjectManager.CoupleFile=false
68 | ProjectManager.CustomerFirmwarePackage=
69 | ProjectManager.DefaultFWLocation=true
70 | ProjectManager.DeletePrevious=true
71 | ProjectManager.DeviceId=STM32F401RETx
72 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2
73 | ProjectManager.FreePins=false
74 | ProjectManager.HalAssertFull=false
75 | ProjectManager.HeapSize=0x200
76 | ProjectManager.KeepUserCode=true
77 | ProjectManager.LastFirmware=true
78 | ProjectManager.LibraryCopy=1
79 | ProjectManager.MainLocation=Src
80 | ProjectManager.NoMain=false
81 | ProjectManager.PreviousToolchain=TrueSTUDIO
82 | ProjectManager.ProjectBuild=false
83 | ProjectManager.ProjectFileName=W5x00-HTTPClient.ioc
84 | ProjectManager.ProjectName=W5x00-HTTPClient
85 | ProjectManager.StackSize=0x400
86 | ProjectManager.TargetToolchain=TrueSTUDIO
87 | ProjectManager.ToolChainLocation=
88 | ProjectManager.UnderRoot=true
89 | ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,1-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_SPI1_Init-SPI1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true
90 | RCC.AHBFreq_Value=16000000
91 | RCC.APB1Freq_Value=16000000
92 | RCC.APB2Freq_Value=16000000
93 | RCC.CortexFreq_Value=16000000
94 | RCC.HSE_VALUE=25000000
95 | RCC.HSI_VALUE=16000000
96 | RCC.I2SClocksFreq_Value=96000000
97 | RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,CortexFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
98 | RCC.LSE_VALUE=32768
99 | RCC.LSI_VALUE=32000
100 | RCC.PLLCLKFreq_Value=96000000
101 | RCC.PLLQCLKFreq_Value=48000000
102 | RCC.RTCFreq_Value=32000
103 | RCC.RTCHSEDivFreq_Value=12500000
104 | RCC.SYSCLKFreq_VALUE=16000000
105 | RCC.VCOI2SOutputFreq_Value=192000000
106 | RCC.VCOInputFreq_Value=1000000
107 | RCC.VCOOutputFreq_Value=192000000
108 | RCC.VcooutputI2S=96000000
109 | SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
110 | SPI1.Direction=SPI_DIRECTION_2LINES
111 | SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler
112 | SPI1.Mode=SPI_MODE_MASTER
113 | SPI1.VirtualType=VM_MASTER
114 | USART2.IPParameters=VirtualMode
115 | USART2.VirtualMode=VM_ASYNC
116 | VP_SYS_VS_Systick.Mode=SysTick
117 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
118 | board=custom
119 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Inc/httpClient.h:
--------------------------------------------------------------------------------
1 | /*
2 | * httpClient.h
3 | *
4 | * Created on: Feb 21, 2020
5 | * Author: becky
6 | */
7 |
8 | #ifndef HTTPCLIENT_H_
9 | #define HTTPCLIENT_H_
10 |
11 | #include
12 |
13 |
14 | // HTTP client debug message enable
15 | #define _HTTPCLIENT_DEBUG_
16 |
17 | // Data buffer size
18 | #ifndef DATA_BUF_SIZE
19 | #define DATA_BUF_SIZE 2048
20 | #endif
21 |
22 | #define HTTP_CLIENT_PORT_MIN 0xB000 // 45056
23 | #define HTTP_CLIENT_PORT_MAX 0xFFFF // 65535
24 |
25 | /*********************************************
26 | * HTTP Method String
27 | *********************************************/
28 | #define HTTP_GET "GET"
29 | #define HTTP_HEAD "HEAD"
30 | #define HTTP_POST "POST"
31 | #define HTTP_PUT "PUT"
32 | #define HTTP_DELETE "DELETE"
33 |
34 |
35 | /*********************************************
36 | * HTTP Content-Type String
37 | *********************************************/
38 | #define HTTP_CTYPE_MULTIPART_FORM "multipart/form-data"
39 | #define HTTP_CTYPE_APP_HTTP_FORM "Application/x-www-form-urlencoded"
40 | #define HTTP_CTYPE_APP_JS "Application/javascript"
41 | #define HTTP_CTYPE_APP_JSON "Application/json"
42 | #define HTTP_CTYPE_APP_XML "Application/xml"
43 | #define HTTP_CTYPE_TEXT_PLAIN "text/plain"
44 | #define HTTP_CTYPE_TEXT_HTML "text/html"
45 | #define HTTP_CTYPE_TEXT_CSS "text/css"
46 | #define HTTP_CTYPE_TEXT_JS "text/javascript"
47 | #define HTTP_CTYPE_TEXT_XML "text/xml"
48 |
49 |
50 | /*********************************************
51 | * HTTP Simple Return Value
52 | *********************************************/
53 | // Return value
54 | #define HTTPC_FAILED 0
55 | #define HTTPC_SUCCESS 1
56 | #define HTTPC_CONNECTED 2
57 | // Return value: boolean type
58 | #define HTTPC_FALSE 0
59 | #define HTTPC_TRUE 1
60 |
61 |
62 | /*********************************************
63 | * HTTP Requset Structure Initializer
64 | *********************************************/
65 | #define HttpRequest_multipart_post_initializer {(uint8_t *)HTTP_POST, NULL, NULL, (uint8_t *)HTTP_CTYPE_MULTIPART_FORM, (uint8_t *)"keep-alive", 0}
66 | #define HttpRequest_get_initializer {(uint8_t *)HTTP_GET, NULL, NULL, NULL, (uint8_t *)"keep-alive", 0}
67 |
68 |
69 | /*********************************************
70 | * HTTP Boundary String for Multipart/form data
71 | *********************************************/
72 | #define formDataBoundary "----WebKitFormBoundaryE8pT6qqUHgRhSDDC" // example boundary string for multipart form data
73 |
74 |
75 | // HTTP client structure
76 | typedef struct __HttpRequest {
77 | uint8_t * method;
78 | uint8_t * uri;
79 | uint8_t * host;
80 | uint8_t * content_type;
81 | uint8_t * connection;
82 | uint32_t content_length;
83 | } __attribute__((packed)) HttpRequest;
84 |
85 | // HTTP client status flags
86 | extern uint8_t httpc_isSockOpen;
87 | extern uint8_t httpc_isConnected;
88 | extern uint16_t httpc_isReceived;
89 |
90 | // extern: HTTP request structure
91 | extern HttpRequest request;
92 |
93 | /*********************************************
94 | * HTTP Client Functions
95 | *********************************************/
96 | uint8_t httpc_connection_handler(); // HTTP client socket handler - for main loop, implemented in polling
97 |
98 | uint8_t httpc_init(uint8_t sock, uint8_t * ip, uint16_t port, uint8_t * sbuf, uint8_t * rbuf); // HTTP client initialize
99 | uint8_t httpc_connect(); // HTTP client connect (after HTTP socket opened)
100 | uint8_t httpc_disconnect(void);
101 |
102 | uint16_t httpc_add_customHeader_field(uint8_t * customHeader_buf, const char * name, const char * value); // Function for adding custom header fields (httpc_send_header() function only)
103 | uint16_t httpc_send_header(HttpRequest * req, uint8_t * buf, uint8_t * customHeader_buf, uint16_t content_len); // Send the HTTP header only
104 | uint16_t httpc_send_body(uint8_t * buf, uint16_t len); // Send the HTTP body only (have to send http request body after header sent)
105 | uint16_t httpc_send(HttpRequest * req, uint8_t * buf, uint8_t * body, uint16_t content_len); // Send the HTTP header and body
106 |
107 | uint16_t httpc_recv(uint8_t * buf, uint16_t len); // Receive the HTTP response header and body, User have to parse the received messages depending on needs
108 |
109 |
110 | #endif /* HTTPCLIENT_H_ */
111 |
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/TrueStudio/W5x00-HTTPClient/W5x00-HTTPClient.elf.launch:
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/TrueStudio/W5x00-HTTPClient/W5x00-HTTPServer.elf.launch:
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/TrueStudio/W5x00-HTTPClient/Src/stm32f4xx_it.c:
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1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32f4xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32f4xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 |
60 | /* USER CODE BEGIN EV */
61 |
62 | /* USER CODE END EV */
63 |
64 | /******************************************************************************/
65 | /* Cortex-M4 Processor Interruption and Exception Handlers */
66 | /******************************************************************************/
67 | /**
68 | * @brief This function handles Non maskable interrupt.
69 | */
70 | void NMI_Handler(void)
71 | {
72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73 |
74 | /* USER CODE END NonMaskableInt_IRQn 0 */
75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76 |
77 | /* USER CODE END NonMaskableInt_IRQn 1 */
78 | }
79 |
80 | /**
81 | * @brief This function handles Hard fault interrupt.
82 | */
83 | void HardFault_Handler(void)
84 | {
85 | /* USER CODE BEGIN HardFault_IRQn 0 */
86 |
87 | /* USER CODE END HardFault_IRQn 0 */
88 | while (1)
89 | {
90 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
91 | /* USER CODE END W1_HardFault_IRQn 0 */
92 | }
93 | }
94 |
95 | /**
96 | * @brief This function handles Memory management fault.
97 | */
98 | void MemManage_Handler(void)
99 | {
100 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
101 |
102 | /* USER CODE END MemoryManagement_IRQn 0 */
103 | while (1)
104 | {
105 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
106 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
107 | }
108 | }
109 |
110 | /**
111 | * @brief This function handles Pre-fetch fault, memory access fault.
112 | */
113 | void BusFault_Handler(void)
114 | {
115 | /* USER CODE BEGIN BusFault_IRQn 0 */
116 |
117 | /* USER CODE END BusFault_IRQn 0 */
118 | while (1)
119 | {
120 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
121 | /* USER CODE END W1_BusFault_IRQn 0 */
122 | }
123 | }
124 |
125 | /**
126 | * @brief This function handles Undefined instruction or illegal state.
127 | */
128 | void UsageFault_Handler(void)
129 | {
130 | /* USER CODE BEGIN UsageFault_IRQn 0 */
131 |
132 | /* USER CODE END UsageFault_IRQn 0 */
133 | while (1)
134 | {
135 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
136 | /* USER CODE END W1_UsageFault_IRQn 0 */
137 | }
138 | }
139 |
140 | /**
141 | * @brief This function handles System service call via SWI instruction.
142 | */
143 | void SVC_Handler(void)
144 | {
145 | /* USER CODE BEGIN SVCall_IRQn 0 */
146 |
147 | /* USER CODE END SVCall_IRQn 0 */
148 | /* USER CODE BEGIN SVCall_IRQn 1 */
149 |
150 | /* USER CODE END SVCall_IRQn 1 */
151 | }
152 |
153 | /**
154 | * @brief This function handles Debug monitor.
155 | */
156 | void DebugMon_Handler(void)
157 | {
158 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159 |
160 | /* USER CODE END DebugMonitor_IRQn 0 */
161 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162 |
163 | /* USER CODE END DebugMonitor_IRQn 1 */
164 | }
165 |
166 | /**
167 | * @brief This function handles Pendable request for system service.
168 | */
169 | void PendSV_Handler(void)
170 | {
171 | /* USER CODE BEGIN PendSV_IRQn 0 */
172 |
173 | /* USER CODE END PendSV_IRQn 0 */
174 | /* USER CODE BEGIN PendSV_IRQn 1 */
175 |
176 | /* USER CODE END PendSV_IRQn 1 */
177 | }
178 |
179 | /**
180 | * @brief This function handles System tick timer.
181 | */
182 | void SysTick_Handler(void)
183 | {
184 | /* USER CODE BEGIN SysTick_IRQn 0 */
185 |
186 | /* USER CODE END SysTick_IRQn 0 */
187 | HAL_IncTick();
188 | /* USER CODE BEGIN SysTick_IRQn 1 */
189 |
190 | /* USER CODE END SysTick_IRQn 1 */
191 | }
192 |
193 | /******************************************************************************/
194 | /* STM32F4xx Peripheral Interrupt Handlers */
195 | /* Add here the Interrupt Handlers for the used peripherals. */
196 | /* For the available peripheral interrupt handler names, */
197 | /* please refer to the startup file (startup_stm32f4xx.s). */
198 | /******************************************************************************/
199 |
200 | /* USER CODE BEGIN 1 */
201 |
202 | /* USER CODE END 1 */
203 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
204 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Src/stm32f4xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * File Name : stm32f4xx_hal_msp.c
5 | * Description : This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2019 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /* USER CODE BEGIN MspInit 1 */
76 |
77 | /* USER CODE END MspInit 1 */
78 | }
79 |
80 | /**
81 | * @brief SPI MSP Initialization
82 | * This function configures the hardware resources used in this example
83 | * @param hspi: SPI handle pointer
84 | * @retval None
85 | */
86 | void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
87 | {
88 | GPIO_InitTypeDef GPIO_InitStruct = {0};
89 | if(hspi->Instance==SPI1)
90 | {
91 | /* USER CODE BEGIN SPI1_MspInit 0 */
92 |
93 | /* USER CODE END SPI1_MspInit 0 */
94 | /* Peripheral clock enable */
95 | __HAL_RCC_SPI1_CLK_ENABLE();
96 |
97 | __HAL_RCC_GPIOA_CLK_ENABLE();
98 | /**SPI1 GPIO Configuration
99 | PA5 ------> SPI1_SCK
100 | PA6 ------> SPI1_MISO
101 | PA7 ------> SPI1_MOSI
102 | */
103 | GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
104 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
105 | GPIO_InitStruct.Pull = GPIO_NOPULL;
106 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
107 | GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
108 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
109 |
110 | /* USER CODE BEGIN SPI1_MspInit 1 */
111 |
112 | /* USER CODE END SPI1_MspInit 1 */
113 | }
114 |
115 | }
116 |
117 | /**
118 | * @brief SPI MSP De-Initialization
119 | * This function freeze the hardware resources used in this example
120 | * @param hspi: SPI handle pointer
121 | * @retval None
122 | */
123 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
124 | {
125 | if(hspi->Instance==SPI1)
126 | {
127 | /* USER CODE BEGIN SPI1_MspDeInit 0 */
128 |
129 | /* USER CODE END SPI1_MspDeInit 0 */
130 | /* Peripheral clock disable */
131 | __HAL_RCC_SPI1_CLK_DISABLE();
132 |
133 | /**SPI1 GPIO Configuration
134 | PA5 ------> SPI1_SCK
135 | PA6 ------> SPI1_MISO
136 | PA7 ------> SPI1_MOSI
137 | */
138 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
139 |
140 | /* USER CODE BEGIN SPI1_MspDeInit 1 */
141 |
142 | /* USER CODE END SPI1_MspDeInit 1 */
143 | }
144 |
145 | }
146 |
147 | /**
148 | * @brief UART MSP Initialization
149 | * This function configures the hardware resources used in this example
150 | * @param huart: UART handle pointer
151 | * @retval None
152 | */
153 | void HAL_UART_MspInit(UART_HandleTypeDef* huart)
154 | {
155 | GPIO_InitTypeDef GPIO_InitStruct = {0};
156 | if(huart->Instance==USART2)
157 | {
158 | /* USER CODE BEGIN USART2_MspInit 0 */
159 |
160 | /* USER CODE END USART2_MspInit 0 */
161 | /* Peripheral clock enable */
162 | __HAL_RCC_USART2_CLK_ENABLE();
163 |
164 | __HAL_RCC_GPIOA_CLK_ENABLE();
165 | /**USART2 GPIO Configuration
166 | PA2 ------> USART2_TX
167 | PA3 ------> USART2_RX
168 | */
169 | GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
170 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
171 | GPIO_InitStruct.Pull = GPIO_PULLUP;
172 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
173 | GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
174 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
175 |
176 | /* USER CODE BEGIN USART2_MspInit 1 */
177 |
178 | /* USER CODE END USART2_MspInit 1 */
179 | }
180 |
181 | }
182 |
183 | /**
184 | * @brief UART MSP De-Initialization
185 | * This function freeze the hardware resources used in this example
186 | * @param huart: UART handle pointer
187 | * @retval None
188 | */
189 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
190 | {
191 | if(huart->Instance==USART2)
192 | {
193 | /* USER CODE BEGIN USART2_MspDeInit 0 */
194 |
195 | /* USER CODE END USART2_MspDeInit 0 */
196 | /* Peripheral clock disable */
197 | __HAL_RCC_USART2_CLK_DISABLE();
198 |
199 | /**USART2 GPIO Configuration
200 | PA2 ------> USART2_TX
201 | PA3 ------> USART2_RX
202 | */
203 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
204 |
205 | /* USER CODE BEGIN USART2_MspDeInit 1 */
206 |
207 | /* USER CODE END USART2_MspDeInit 1 */
208 | }
209 |
210 | }
211 |
212 | /* USER CODE BEGIN 1 */
213 |
214 | /* USER CODE END 1 */
215 |
216 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
217 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Debug_STM32F401RE_FLASH.ld:
--------------------------------------------------------------------------------
1 | /*
2 | ******************************************************************************
3 | File: Debug_STM32F401RE_FLASH.ld
4 | Info: Generated by Atollic TrueSTUDIO(R) 9.3.0 2019-12-17
5 |
6 | Abstract: Linker script for STM32F401RE device
7 | Set heap size, stack size, stack location, memory areas and
8 | sections according to application requirements.
9 |
10 | The MIT License (MIT)
11 | Copyright (c) 2019 STMicroelectronics
12 |
13 | Permission is hereby granted, free of charge, to any person obtaining a copy
14 | of this software and associated documentation files (the "Software"), to deal
15 | in the Software without restriction, including without limitation the rights
16 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17 | copies of the Software, and to permit persons to whom the Software is
18 | furnished to do so, subject to the following conditions:
19 |
20 | The above copyright notice and this permission notice shall be included in all
21 | copies or substantial portions of the Software.
22 |
23 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
26 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 | SOFTWARE.
30 |
31 | ******************************************************************************
32 | */
33 |
34 | /* Entry Point */
35 | ENTRY(Reset_Handler)
36 |
37 | /* Highest address of the user mode stack */
38 | _estack = 0x20018000; /* end of 96K RAM */
39 |
40 | /* Generate a link error if heap and stack don't fit into RAM */
41 | _Min_Heap_Size = 0; /* required amount of heap */
42 | _Min_Stack_Size = 0x400; /* required amount of stack */
43 |
44 | /* Specify the memory areas */
45 | MEMORY
46 | {
47 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
48 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
49 | MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
50 | CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
51 | }
52 |
53 | /* Define output sections */
54 | SECTIONS
55 | {
56 | /* The startup code goes first into FLASH */
57 | .isr_vector :
58 | {
59 | . = ALIGN(4);
60 | KEEP(*(.isr_vector)) /* Startup code */
61 | . = ALIGN(4);
62 | } >FLASH
63 |
64 | /* The program code and other data goes into FLASH */
65 | .text :
66 | {
67 | . = ALIGN(4);
68 | *(.text) /* .text sections (code) */
69 | *(.text*) /* .text* sections (code) */
70 | *(.glue_7) /* glue arm to thumb code */
71 | *(.glue_7t) /* glue thumb to arm code */
72 | *(.eh_frame)
73 |
74 | KEEP (*(.init))
75 | KEEP (*(.fini))
76 |
77 | . = ALIGN(4);
78 | _etext = .; /* define a global symbols at end of code */
79 | } >FLASH
80 |
81 | /* Constant data goes into FLASH */
82 | .rodata :
83 | {
84 | . = ALIGN(4);
85 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
86 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
87 | . = ALIGN(4);
88 | } >FLASH
89 |
90 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
91 | .ARM : {
92 | __exidx_start = .;
93 | *(.ARM.exidx*)
94 | __exidx_end = .;
95 | } >FLASH
96 |
97 | .preinit_array :
98 | {
99 | PROVIDE_HIDDEN (__preinit_array_start = .);
100 | KEEP (*(.preinit_array*))
101 | PROVIDE_HIDDEN (__preinit_array_end = .);
102 | } >FLASH
103 | .init_array :
104 | {
105 | PROVIDE_HIDDEN (__init_array_start = .);
106 | KEEP (*(SORT(.init_array.*)))
107 | KEEP (*(.init_array*))
108 | PROVIDE_HIDDEN (__init_array_end = .);
109 | } >FLASH
110 | .fini_array :
111 | {
112 | PROVIDE_HIDDEN (__fini_array_start = .);
113 | KEEP (*(SORT(.fini_array.*)))
114 | KEEP (*(.fini_array*))
115 | PROVIDE_HIDDEN (__fini_array_end = .);
116 | } >FLASH
117 |
118 | /* used by the startup to initialize data */
119 | _sidata = LOADADDR(.data);
120 |
121 | /* Initialized data sections goes into RAM, load LMA copy after code */
122 | .data :
123 | {
124 | . = ALIGN(4);
125 | _sdata = .; /* create a global symbol at data start */
126 | *(.data) /* .data sections */
127 | *(.data*) /* .data* sections */
128 |
129 | . = ALIGN(4);
130 | _edata = .; /* define a global symbol at data end */
131 | } >RAM AT> FLASH
132 |
133 | _siccmram = LOADADDR(.ccmram);
134 |
135 | /* CCM-RAM section
136 | *
137 | * IMPORTANT NOTE!
138 | * If initialized variables will be placed in this section,
139 | * the startup code needs to be modified to copy the init-values.
140 | */
141 | .ccmram :
142 | {
143 | . = ALIGN(4);
144 | _sccmram = .; /* create a global symbol at ccmram start */
145 | *(.ccmram)
146 | *(.ccmram*)
147 |
148 | . = ALIGN(4);
149 | _eccmram = .; /* create a global symbol at ccmram end */
150 | } >CCMRAM AT> FLASH
151 |
152 | /* Uninitialized data section */
153 | . = ALIGN(4);
154 | .bss :
155 | {
156 | /* This is used by the startup in order to initialize the .bss secion */
157 | _sbss = .; /* define a global symbol at bss start */
158 | __bss_start__ = _sbss;
159 | *(.bss)
160 | *(.bss*)
161 | *(COMMON)
162 |
163 | . = ALIGN(4);
164 | _ebss = .; /* define a global symbol at bss end */
165 | __bss_end__ = _ebss;
166 | } >RAM
167 |
168 | /* User_heap_stack section, used to check that there is enough RAM left */
169 | ._user_heap_stack :
170 | {
171 | . = ALIGN(4);
172 | PROVIDE ( end = . );
173 | PROVIDE ( _end = . );
174 | . = . + _Min_Heap_Size;
175 | . = . + _Min_Stack_Size;
176 | . = ALIGN(4);
177 | } >RAM
178 |
179 | /* MEMORY_bank1 section, code must be located here explicitly */
180 | /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
181 | .memory_b1_text :
182 | {
183 | *(.mb1text) /* .mb1text sections (code) */
184 | *(.mb1text*) /* .mb1text* sections (code) */
185 | *(.mb1rodata) /* read-only data (constants) */
186 | *(.mb1rodata*)
187 | } >MEMORY_B1
188 |
189 | /* Remove information from the standard libraries */
190 | /DISCARD/ :
191 | {
192 | libc.a ( * )
193 | libm.a ( * )
194 | libgcc.a ( * )
195 | }
196 |
197 | .ARM.attributes 0 : { *(.ARM.attributes) }
198 | }
199 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/.mxproject:
--------------------------------------------------------------------------------
1 | [PreviousGenFiles]
2 | HeaderPath=D:/___WORK/__iEthernet/__W5X00/W5x00-HTTPClient/TrueStudio/W5x00-HTTPClient/Inc
3 | HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h;
4 | SourcePath=D:/___WORK/__iEthernet/__W5X00/W5x00-HTTPClient/TrueStudio/W5x00-HTTPClient/Src
5 | SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
6 |
7 | [PreviousLibFiles]
8 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
9 |
10 | [PreviousUsedTStudioFiles]
11 | SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
12 | HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
13 | CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__));USE_HAL_DRIVER;STM32F401xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
14 |
15 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_flash_ramfunc.c
4 | * @author MCD Application Team
5 | * @brief FLASH RAMFUNC module driver.
6 | * This file provides a FLASH firmware functions which should be
7 | * executed from internal SRAM
8 | * + Stop/Start the flash interface while System Run
9 | * + Enable/Disable the flash sleep while System Run
10 | @verbatim
11 | ==============================================================================
12 | ##### APIs executed from Internal RAM #####
13 | ==============================================================================
14 | [..]
15 | *** ARM Compiler ***
16 | --------------------
17 | [..] RAM functions are defined using the toolchain options.
18 | Functions that are be executed in RAM should reside in a separate
19 | source module. Using the 'Options for File' dialog you can simply change
20 | the 'Code / Const' area of a module to a memory space in physical RAM.
21 | Available memory areas are declared in the 'Target' tab of the
22 | Options for Target' dialog.
23 |
24 | *** ICCARM Compiler ***
25 | -----------------------
26 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
27 |
28 | *** GNU Compiler ***
29 | --------------------
30 | [..] RAM functions are defined using a specific toolchain attribute
31 | "__attribute__((section(".RamFunc")))".
32 |
33 | @endverbatim
34 | ******************************************************************************
35 | * @attention
36 | *
37 | * © Copyright (c) 2017 STMicroelectronics.
38 | * All rights reserved.
39 | *
40 | * This software component is licensed by ST under BSD 3-Clause license,
41 | * the "License"; You may not use this file except in compliance with the
42 | * License. You may obtain a copy of the License at:
43 | * opensource.org/licenses/BSD-3-Clause
44 | *
45 | ******************************************************************************
46 | */
47 |
48 | /* Includes ------------------------------------------------------------------*/
49 | #include "stm32f4xx_hal.h"
50 |
51 | /** @addtogroup STM32F4xx_HAL_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
56 | * @brief FLASH functions executed from RAM
57 | * @{
58 | */
59 | #ifdef HAL_FLASH_MODULE_ENABLED
60 | #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
61 | defined(STM32F412Rx) || defined(STM32F412Cx)
62 |
63 | /* Private typedef -----------------------------------------------------------*/
64 | /* Private define ------------------------------------------------------------*/
65 | /* Private macro -------------------------------------------------------------*/
66 | /* Private variables ---------------------------------------------------------*/
67 | /* Private function prototypes -----------------------------------------------*/
68 | /* Exported functions --------------------------------------------------------*/
69 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
70 | * @{
71 | */
72 |
73 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM
74 | * @brief Peripheral Extended features functions
75 | *
76 | @verbatim
77 |
78 | ===============================================================================
79 | ##### ramfunc functions #####
80 | ===============================================================================
81 | [..]
82 | This subsection provides a set of functions that should be executed from RAM
83 | transfers.
84 |
85 | @endverbatim
86 | * @{
87 | */
88 |
89 | /**
90 | * @brief Stop the flash interface while System Run
91 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
92 | * @note This mode couldn't be set while executing with the flash itself.
93 | * It should be done with specific routine executed from RAM.
94 | * @retval HAL status
95 | */
96 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
97 | {
98 | /* Enable Power ctrl clock */
99 | __HAL_RCC_PWR_CLK_ENABLE();
100 | /* Stop the flash interface while System Run */
101 | SET_BIT(PWR->CR, PWR_CR_FISSR);
102 |
103 | return HAL_OK;
104 | }
105 |
106 | /**
107 | * @brief Start the flash interface while System Run
108 | * @note This mode is only available for STM32F411xx/STM32F446xx devices.
109 | * @note This mode couldn't be set while executing with the flash itself.
110 | * It should be done with specific routine executed from RAM.
111 | * @retval HAL status
112 | */
113 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
114 | {
115 | /* Enable Power ctrl clock */
116 | __HAL_RCC_PWR_CLK_ENABLE();
117 | /* Start the flash interface while System Run */
118 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
119 |
120 | return HAL_OK;
121 | }
122 |
123 | /**
124 | * @brief Enable the flash sleep while System Run
125 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
126 | * @note This mode could n't be set while executing with the flash itself.
127 | * It should be done with specific routine executed from RAM.
128 | * @retval HAL status
129 | */
130 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
131 | {
132 | /* Enable Power ctrl clock */
133 | __HAL_RCC_PWR_CLK_ENABLE();
134 | /* Enable the flash sleep while System Run */
135 | SET_BIT(PWR->CR, PWR_CR_FMSSR);
136 |
137 | return HAL_OK;
138 | }
139 |
140 | /**
141 | * @brief Disable the flash sleep while System Run
142 | * @note This mode is only available for STM32F41xxx/STM32F446xx devices.
143 | * @note This mode couldn't be set while executing with the flash itself.
144 | * It should be done with specific routine executed from RAM.
145 | * @retval HAL status
146 | */
147 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
148 | {
149 | /* Enable Power ctrl clock */
150 | __HAL_RCC_PWR_CLK_ENABLE();
151 | /* Disable the flash sleep while System Run */
152 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
153 |
154 | return HAL_OK;
155 | }
156 |
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
166 | #endif /* HAL_FLASH_MODULE_ENABLED */
167 | /**
168 | * @}
169 | */
170 |
171 | /**
172 | * @}
173 | */
174 |
175 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
176 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2017 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32F4xx_HAL_DEF
23 | #define __STM32F4xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32f4xx.h"
31 | #include "Legacy/stm32_hal_legacy.h"
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 |
58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
59 |
60 | #define HAL_MAX_DELAY 0xFFFFFFFFU
61 |
62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
64 |
65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
66 | do{ \
67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
69 | } while(0U)
70 |
71 | /** @brief Reset the Handle's State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handle's "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error "USE_RTOS should be 0 in the current HAL release"
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif /* __weak */
114 | #ifndef __packed
115 | #define __packed __attribute__((__packed__))
116 | #endif /* __packed */
117 | #endif /* __GNUC__ */
118 |
119 |
120 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
121 | #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
122 | #ifndef __ALIGN_END
123 | #define __ALIGN_END __attribute__ ((aligned (4)))
124 | #endif /* __ALIGN_END */
125 | #ifndef __ALIGN_BEGIN
126 | #define __ALIGN_BEGIN
127 | #endif /* __ALIGN_BEGIN */
128 | #else
129 | #ifndef __ALIGN_END
130 | #define __ALIGN_END
131 | #endif /* __ALIGN_END */
132 | #ifndef __ALIGN_BEGIN
133 | #if defined (__CC_ARM) /* ARM Compiler */
134 | #define __ALIGN_BEGIN __align(4)
135 | #elif defined (__ICCARM__) /* IAR Compiler */
136 | #define __ALIGN_BEGIN
137 | #endif /* __CC_ARM */
138 | #endif /* __ALIGN_BEGIN */
139 | #endif /* __GNUC__ */
140 |
141 |
142 | /**
143 | * @brief __RAM_FUNC definition
144 | */
145 | #if defined ( __CC_ARM )
146 | /* ARM Compiler
147 | ------------
148 | RAM functions are defined using the toolchain options.
149 | Functions that are executed in RAM should reside in a separate source module.
150 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
151 | area of a module to a memory space in physical RAM.
152 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
153 | dialog.
154 | */
155 | #define __RAM_FUNC
156 |
157 | #elif defined ( __ICCARM__ )
158 | /* ICCARM Compiler
159 | ---------------
160 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
161 | */
162 | #define __RAM_FUNC __ramfunc
163 |
164 | #elif defined ( __GNUC__ )
165 | /* GNU Compiler
166 | ------------
167 | RAM functions are defined using a specific toolchain attribute
168 | "__attribute__((section(".RamFunc")))".
169 | */
170 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
171 |
172 | #endif
173 |
174 | /**
175 | * @brief __NOINLINE definition
176 | */
177 | #if defined ( __CC_ARM ) || defined ( __GNUC__ )
178 | /* ARM & GNUCompiler
179 | ----------------
180 | */
181 | #define __NOINLINE __attribute__ ( (noinline) )
182 |
183 | #elif defined ( __ICCARM__ )
184 | /* ICCARM Compiler
185 | ---------------
186 | */
187 | #define __NOINLINE _Pragma("optimize = no_inline")
188 |
189 | #endif
190 |
191 | #ifdef __cplusplus
192 | }
193 | #endif
194 |
195 | #endif /* ___STM32F4xx_HAL_DEF */
196 |
197 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
198 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Src/httpClient.c:
--------------------------------------------------------------------------------
1 | /*
2 | * httpClient.c
3 | *
4 | * Created on: Feb 21, 2020
5 | * Author: becky
6 | */
7 |
8 |
9 | #include
10 | #include
11 |
12 | #include "wizchip_conf.h"
13 | #include "socket.h"
14 | #include "httpClient.h"
15 |
16 | /* Private define ------------------------------------------------------------*/
17 |
18 | /* Private variables ---------------------------------------------------------*/
19 | uint8_t * httpc_send_buf;
20 | uint8_t * httpc_recv_buf;
21 | //HttpRequest request = HttpRequest_multipart_post_initializer;
22 | HttpRequest request = HttpRequest_get_initializer;
23 |
24 | static int8_t httpsock = 0;
25 | static uint8_t dest_ip[4] = {0, };
26 | static uint16_t dest_port = 0;
27 | static uint16_t httpc_any_port = 0;
28 |
29 | uint8_t httpc_isSockOpen = HTTPC_FALSE;
30 | uint8_t httpc_isConnected = HTTPC_FALSE;
31 | uint16_t httpc_isReceived = HTTPC_FALSE;
32 |
33 | /* Private functions prototypes ----------------------------------------------*/
34 | uint16_t get_httpc_any_port(void);
35 |
36 | /* Public & Private functions ------------------------------------------------*/
37 |
38 | uint8_t httpc_init(uint8_t sock, uint8_t * ip, uint16_t port, uint8_t * sbuf, uint8_t * rbuf)
39 | {
40 | uint8_t ret = HTTPC_FALSE;
41 |
42 | if(sock <= _WIZCHIP_SOCK_NUM_)
43 | {
44 | // Hardware socket number for HTTP client (0 ~ 7)
45 | httpsock = sock;
46 |
47 | // Shared buffers: HTTP Send / Recevice
48 | httpc_send_buf = sbuf;
49 | httpc_recv_buf = rbuf;
50 |
51 | // Destination IP address and Port number
52 | // (Destination = HTTP server)
53 | dest_ip[0] = ip[0];
54 | dest_ip[1] = ip[1];
55 | dest_ip[2] = ip[2];
56 | dest_ip[3] = ip[3];
57 | dest_port = port;
58 |
59 | ret = HTTPC_TRUE;
60 | }
61 |
62 | return ret;
63 | }
64 |
65 |
66 | // return: true / false
67 | uint8_t httpc_connection_handler()
68 | {
69 | uint8_t ret = HTTPC_FALSE;
70 |
71 | uint16_t source_port;
72 |
73 | #ifdef _HTTPCLIENT_DEBUG_
74 | uint8_t destip[4] = {0, };
75 | uint16_t destport = 0;
76 | #endif
77 |
78 | uint8_t state = getSn_SR(httpsock);
79 | switch(state)
80 | {
81 | case SOCK_INIT:
82 | // state: connect
83 | ret = HTTPC_TRUE;
84 | break;
85 |
86 | case SOCK_ESTABLISHED:
87 | if(getSn_IR(httpsock) & Sn_IR_CON)
88 | {
89 | #ifdef _HTTPCLIENT_DEBUG_
90 | // Serial debug message printout
91 | getsockopt(httpsock, SO_DESTIP, &destip);
92 | getsockopt(httpsock, SO_DESTPORT, &destport);
93 | printf(" > HTTP CLIENT: CONNECTED TO - %d.%d.%d.%d : %d\r\n",destip[0], destip[1], destip[2], destip[3], destport);
94 | #endif
95 | httpc_isConnected = HTTPC_TRUE;
96 |
97 | setSn_IR(httpsock, Sn_IR_CON);
98 | }
99 |
100 | httpc_isReceived = getSn_RX_RSR(httpsock);
101 | ret = HTTPC_CONNECTED;
102 | break;
103 |
104 | case SOCK_CLOSE_WAIT:
105 | disconnect(httpsock);
106 | break;
107 |
108 | case SOCK_FIN_WAIT:
109 | case SOCK_CLOSED:
110 | httpc_isSockOpen = HTTPC_FALSE;
111 | httpc_isConnected = HTTPC_FALSE;
112 |
113 | source_port = get_httpc_any_port();
114 | #ifdef _HTTPCLIENT_DEBUG_
115 | printf(" > HTTP CLIENT: source_port = %d\r\n", source_port);
116 | #endif
117 |
118 | if(socket(httpsock, Sn_MR_TCP, source_port, Sn_MR_ND) == httpsock)
119 | {
120 | if(httpc_isSockOpen == HTTPC_FALSE)
121 | {
122 | #ifdef _HTTPCLIENT_DEBUG_
123 | printf(" > HTTP CLIENT: SOCKOPEN\r\n");
124 | #endif
125 | httpc_isSockOpen = HTTPC_TRUE;
126 | }
127 | }
128 |
129 |
130 | break;
131 |
132 | default:
133 | break;
134 | }
135 |
136 | return ret;
137 | }
138 |
139 |
140 | // return: socket status
141 | uint8_t httpc_connect()
142 | {
143 | uint8_t ret = HTTPC_FALSE;
144 |
145 | if(httpsock >= 0)
146 | {
147 | if(httpc_isSockOpen == HTTPC_TRUE)
148 | {
149 | // TCP connect
150 | ret = connect(httpsock, dest_ip, dest_port);
151 | if(ret == SOCK_OK) ret = HTTPC_TRUE;
152 | }
153 | }
154 |
155 | return ret;
156 | }
157 |
158 | uint16_t httpc_add_customHeader_field(uint8_t * customHeader_buf, const char * name, const char * value)
159 | {
160 | uint16_t len = 0;
161 |
162 | if((strlen((char *)name) + strlen((char *)value)) > DATA_BUF_SIZE) return 0;
163 |
164 | if(strlen((char *)customHeader_buf) == 0)
165 | {
166 | len = sprintf((char *)customHeader_buf, "%s: %s\r\n", name, value);
167 | }
168 | else
169 | {
170 | len = sprintf((char *)customHeader_buf, "%s%s: %s\r\n", customHeader_buf, name, value);
171 | }
172 |
173 | return len;
174 | }
175 |
176 | // return: sent header length
177 | uint16_t httpc_send_header(HttpRequest * req, uint8_t * buf, uint8_t * customHeader_buf, uint16_t content_len)
178 | {
179 | uint16_t len;
180 |
181 | if(httpc_isConnected == HTTPC_TRUE)
182 | {
183 | memset(buf, 0x00, DATA_BUF_SIZE);
184 |
185 | len = sprintf((char *)buf, "%s %s HTTP/1.1\r\n", req->method, req->uri);
186 | len += sprintf((char *)buf+len, "Host: %s\r\n", req->host);
187 | len += sprintf((char *)buf+len, "Connection: %s\r\n", req->connection);
188 |
189 | // HTTP content type: POST / PUT
190 | if(content_len > 0)
191 | {
192 | len += sprintf((char *)buf+len, "Content-Length: %d\r\n", content_len);
193 |
194 | if(strcmp((char *)req->content_type, HTTP_CTYPE_MULTIPART_FORM) == 0)
195 | {
196 | // HTTP content type: multipart/form-data
197 | len += sprintf((char *)buf+len, "Content-Type: %s; boundary=%s\r\n", req->content_type, formDataBoundary);
198 | }
199 | else
200 | {
201 | // HTTP content type: others
202 | len += sprintf((char *)buf+len, "Content-Type: %s\r\n", req->content_type); // HTTP content type: others
203 | }
204 | }
205 |
206 | // for adding custom header fields
207 | if(customHeader_buf != NULL)
208 | {
209 | if((strlen((char *)customHeader_buf) + len + 2) <= DATA_BUF_SIZE)
210 | {
211 | len += sprintf((char *)buf+len, "%s", customHeader_buf);
212 | }
213 | }
214 |
215 | len += sprintf((char *)buf+len, "\r\n");
216 |
217 | #ifdef _HTTPCLIENT_DEBUG_
218 | printf(" >> HTTP Request header - Method: %s, URI: %s, Content-Length: %d\r\n", req->method, req->uri, content_len);
219 | printf("%s", buf);
220 | #endif
221 | send(httpsock, buf, len);
222 | }
223 | else
224 | {
225 | len = HTTPC_FAILED;
226 | }
227 |
228 | return len;
229 | }
230 |
231 |
232 | // return: sent body length
233 | uint16_t httpc_send_body(uint8_t * buf, uint16_t len)
234 | {
235 | uint16_t sentlen = 0;
236 |
237 | #ifdef _HTTPCLIENT_DEBUG_
238 | uint16_t i;
239 | #endif
240 |
241 | if(httpc_isConnected == HTTPC_TRUE)
242 | {
243 | do{
244 | sentlen += send(httpsock, buf, len);
245 | } while(sentlen < len);
246 |
247 | #ifdef _HTTPCLIENT_DEBUG_
248 | if(sentlen > 0)
249 | {
250 | printf(" >> HTTP Request Body\r\n");
251 | for(i = 0; i < sentlen; i++) printf("%c", buf[i]);
252 | printf("\r\n");
253 | }
254 | #endif
255 | }
256 | else
257 | {
258 | sentlen = HTTPC_FAILED;
259 | }
260 |
261 | return sentlen;
262 | }
263 |
264 |
265 | // return: sent data length
266 | uint16_t httpc_send(HttpRequest * req, uint8_t * buf, uint8_t * body, uint16_t content_len)
267 | {
268 | uint16_t i;
269 | uint16_t len;
270 | uint8_t http_header_generated = HTTPC_FAILED;
271 |
272 | if(httpc_isConnected == HTTPC_TRUE)
273 | {
274 | do
275 | {
276 | memset(buf, 0x00, DATA_BUF_SIZE);
277 |
278 | /* HTTP request header */
279 | len = sprintf((char *)buf, "%s %s HTTP/1.1\r\n", req->method, req->uri);
280 | len += sprintf((char *)buf+len, "Host: %s\r\n", req->host);
281 | len += sprintf((char *)buf+len, "Connection: %s\r\n", req->connection);
282 |
283 | // HTTP content type: POST / PUT only
284 | if(content_len > 0)
285 | {
286 | len += sprintf((char *)buf+len, "Content-Length: %d\r\n", content_len);
287 |
288 | if(strcmp((char *)req->content_type, HTTP_CTYPE_MULTIPART_FORM) == 0)
289 | {
290 | // HTTP content type: multipart/form-data
291 | len += sprintf((char *)buf+len, "Content-Type: %s; boundary=%s\r\n", req->content_type, formDataBoundary);
292 | }
293 | else
294 | {
295 | // HTTP content type: others
296 | len += sprintf((char *)buf+len, "Content-Type: %s\r\n", req->content_type); // HTTP content type: others
297 | }
298 | }
299 | len += sprintf((char *)buf+len, "\r\n");
300 |
301 | // Avoiding buffer overflow
302 | if((len + content_len) > DATA_BUF_SIZE) {
303 | content_len = DATA_BUF_SIZE - len; // HTTP request header re-generation (do-while)
304 | //http_header_generated = FAILED;
305 | } else {
306 | http_header_generated = HTTPC_SUCCESS;
307 | }
308 | } while(http_header_generated != HTTPC_SUCCESS);
309 |
310 | /* HTTP request body */
311 | for(i = 0; i < content_len; i++)
312 | {
313 | buf[len++] = body[i];
314 | }
315 |
316 | //#ifdef _HTTPCLIENT_DEBUG_
317 | printf(" >> HTTP Request - Method: %s, URI: %s, Content-Length: %d\r\n", req->method, req->uri, content_len);
318 | for(i = 0; i < len; i++) printf("%c", buf[i]);
319 | printf("\r\n");
320 | //#endif
321 | send(httpsock, buf, len);
322 | }
323 | else
324 | {
325 | len = HTTPC_FAILED;
326 | }
327 |
328 | return len;
329 | }
330 |
331 |
332 | // return: received data length
333 | uint16_t httpc_recv(uint8_t * buf, uint16_t len)
334 | {
335 | uint16_t recvlen;
336 |
337 | if(httpc_isConnected == HTTPC_TRUE)
338 | {
339 | if(len > DATA_BUF_SIZE) len = DATA_BUF_SIZE;
340 | recvlen = recv(httpsock, buf, len);
341 | }
342 | else
343 | {
344 | recvlen = HTTPC_FAILED;
345 | }
346 |
347 | return recvlen;
348 | }
349 |
350 |
351 | // return: true / false
352 | uint8_t httpc_disconnect(void)
353 | {
354 | uint8_t ret = HTTPC_FALSE;
355 |
356 | if(httpc_isConnected == HTTPC_TRUE)
357 | {
358 | #ifdef _HTTPCLIENT_DEBUG_
359 | printf(" > HTTP CLIENT: Try to disconnect\r\n");
360 | #endif
361 | ret = disconnect(httpsock);
362 | if(ret == SOCK_OK)
363 | {
364 | ret = HTTPC_TRUE;
365 | #ifdef _HTTPCLIENT_DEBUG_
366 | printf(" > HTTP CLIENT: Disconnected\r\n");
367 | #endif
368 | }
369 | }
370 |
371 | return ret;
372 | }
373 |
374 |
375 | // return: source port number for tcp client
376 | uint16_t get_httpc_any_port(void)
377 | {
378 | if(httpc_any_port)
379 | {
380 | if((httpc_any_port >= HTTP_CLIENT_PORT_MIN) && (httpc_any_port < HTTP_CLIENT_PORT_MAX)) {
381 | httpc_any_port++;
382 | } else {
383 | httpc_any_port = 0;
384 | }
385 | }
386 |
387 | if(httpc_any_port < HTTP_CLIENT_PORT_MIN)
388 | {
389 | // todo: get random seed value
390 | httpc_any_port = (rand() % 10000) + 46000; // 46000 ~ 55999
391 | }
392 |
393 | return httpc_any_port;
394 | }
395 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_dma_ex.c
4 | * @author MCD Application Team
5 | * @brief DMA Extension HAL module driver
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the DMA Extension peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### How to use this driver #####
13 | ==============================================================================
14 | [..]
15 | The DMA Extension HAL driver can be used as follows:
16 | (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
17 | for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
18 |
19 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
20 | -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
21 | -@- In Multi (Double) buffer mode, it is possible to update the base address for
22 | the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
23 |
24 | @endverbatim
25 | ******************************************************************************
26 | * @attention
27 | *
28 | * © Copyright (c) 2017 STMicroelectronics.
29 | * All rights reserved.
30 | *
31 | * This software component is licensed by ST under BSD 3-Clause license,
32 | * the "License"; You may not use this file except in compliance with the
33 | * License. You may obtain a copy of the License at:
34 | * opensource.org/licenses/BSD-3-Clause
35 | *
36 | ******************************************************************************
37 | */
38 |
39 | /* Includes ------------------------------------------------------------------*/
40 | #include "stm32f4xx_hal.h"
41 |
42 | /** @addtogroup STM32F4xx_HAL_Driver
43 | * @{
44 | */
45 |
46 | /** @defgroup DMAEx DMAEx
47 | * @brief DMA Extended HAL module driver
48 | * @{
49 | */
50 |
51 | #ifdef HAL_DMA_MODULE_ENABLED
52 |
53 | /* Private types -------------------------------------------------------------*/
54 | /* Private variables ---------------------------------------------------------*/
55 | /* Private Constants ---------------------------------------------------------*/
56 | /* Private macros ------------------------------------------------------------*/
57 | /* Private functions ---------------------------------------------------------*/
58 | /** @addtogroup DMAEx_Private_Functions
59 | * @{
60 | */
61 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
62 | /**
63 | * @}
64 | */
65 |
66 | /* Exported functions ---------------------------------------------------------*/
67 |
68 | /** @addtogroup DMAEx_Exported_Functions
69 | * @{
70 | */
71 |
72 |
73 | /** @addtogroup DMAEx_Exported_Functions_Group1
74 | *
75 | @verbatim
76 | ===============================================================================
77 | ##### Extended features functions #####
78 | ===============================================================================
79 | [..] This section provides functions allowing to:
80 | (+) Configure the source, destination address and data length and
81 | Start MultiBuffer DMA transfer
82 | (+) Configure the source, destination address and data length and
83 | Start MultiBuffer DMA transfer with interrupt
84 | (+) Change on the fly the memory0 or memory1 address.
85 |
86 | @endverbatim
87 | * @{
88 | */
89 |
90 |
91 | /**
92 | * @brief Starts the multi_buffer DMA Transfer.
93 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
94 | * the configuration information for the specified DMA Stream.
95 | * @param SrcAddress The source memory Buffer address
96 | * @param DstAddress The destination memory Buffer address
97 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
98 | * @param DataLength The length of data to be transferred from source to destination
99 | * @retval HAL status
100 | */
101 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
102 | {
103 | HAL_StatusTypeDef status = HAL_OK;
104 |
105 | /* Check the parameters */
106 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
107 |
108 | /* Memory-to-memory transfer not supported in double buffering mode */
109 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
110 | {
111 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
112 | status = HAL_ERROR;
113 | }
114 | else
115 | {
116 | /* Process Locked */
117 | __HAL_LOCK(hdma);
118 |
119 | if(HAL_DMA_STATE_READY == hdma->State)
120 | {
121 | /* Change DMA peripheral state */
122 | hdma->State = HAL_DMA_STATE_BUSY;
123 |
124 | /* Enable the double buffer mode */
125 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
126 |
127 | /* Configure DMA Stream destination address */
128 | hdma->Instance->M1AR = SecondMemAddress;
129 |
130 | /* Configure the source, destination address and the data length */
131 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
132 |
133 | /* Enable the peripheral */
134 | __HAL_DMA_ENABLE(hdma);
135 | }
136 | else
137 | {
138 | /* Return error status */
139 | status = HAL_BUSY;
140 | }
141 | }
142 | return status;
143 | }
144 |
145 | /**
146 | * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
147 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
148 | * the configuration information for the specified DMA Stream.
149 | * @param SrcAddress The source memory Buffer address
150 | * @param DstAddress The destination memory Buffer address
151 | * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
152 | * @param DataLength The length of data to be transferred from source to destination
153 | * @retval HAL status
154 | */
155 | HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
156 | {
157 | HAL_StatusTypeDef status = HAL_OK;
158 |
159 | /* Check the parameters */
160 | assert_param(IS_DMA_BUFFER_SIZE(DataLength));
161 |
162 | /* Memory-to-memory transfer not supported in double buffering mode */
163 | if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
164 | {
165 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
166 | return HAL_ERROR;
167 | }
168 |
169 | /* Check callback functions */
170 | if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
171 | {
172 | hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
173 | return HAL_ERROR;
174 | }
175 |
176 | /* Process locked */
177 | __HAL_LOCK(hdma);
178 |
179 | if(HAL_DMA_STATE_READY == hdma->State)
180 | {
181 | /* Change DMA peripheral state */
182 | hdma->State = HAL_DMA_STATE_BUSY;
183 |
184 | /* Initialize the error code */
185 | hdma->ErrorCode = HAL_DMA_ERROR_NONE;
186 |
187 | /* Enable the Double buffer mode */
188 | hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
189 |
190 | /* Configure DMA Stream destination address */
191 | hdma->Instance->M1AR = SecondMemAddress;
192 |
193 | /* Configure the source, destination address and the data length */
194 | DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
195 |
196 | /* Clear all flags */
197 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
198 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
199 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
200 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
201 | __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
202 |
203 | /* Enable Common interrupts*/
204 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
205 | hdma->Instance->FCR |= DMA_IT_FE;
206 |
207 | if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
208 | {
209 | hdma->Instance->CR |= DMA_IT_HT;
210 | }
211 |
212 | /* Enable the peripheral */
213 | __HAL_DMA_ENABLE(hdma);
214 | }
215 | else
216 | {
217 | /* Process unlocked */
218 | __HAL_UNLOCK(hdma);
219 |
220 | /* Return error status */
221 | status = HAL_BUSY;
222 | }
223 | return status;
224 | }
225 |
226 | /**
227 | * @brief Change the memory0 or memory1 address on the fly.
228 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
229 | * the configuration information for the specified DMA Stream.
230 | * @param Address The new address
231 | * @param memory the memory to be changed, This parameter can be one of
232 | * the following values:
233 | * MEMORY0 /
234 | * MEMORY1
235 | * @note The MEMORY0 address can be changed only when the current transfer use
236 | * MEMORY1 and the MEMORY1 address can be changed only when the current
237 | * transfer use MEMORY0.
238 | * @retval HAL status
239 | */
240 | HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
241 | {
242 | if(memory == MEMORY0)
243 | {
244 | /* change the memory0 address */
245 | hdma->Instance->M0AR = Address;
246 | }
247 | else
248 | {
249 | /* change the memory1 address */
250 | hdma->Instance->M1AR = Address;
251 | }
252 |
253 | return HAL_OK;
254 | }
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /** @addtogroup DMAEx_Private_Functions
265 | * @{
266 | */
267 |
268 | /**
269 | * @brief Set the DMA Transfer parameter.
270 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains
271 | * the configuration information for the specified DMA Stream.
272 | * @param SrcAddress The source memory Buffer address
273 | * @param DstAddress The destination memory Buffer address
274 | * @param DataLength The length of data to be transferred from source to destination
275 | * @retval HAL status
276 | */
277 | static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
278 | {
279 | /* Configure DMA Stream data length */
280 | hdma->Instance->NDTR = DataLength;
281 |
282 | /* Peripheral to Memory */
283 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
284 | {
285 | /* Configure DMA Stream destination address */
286 | hdma->Instance->PAR = DstAddress;
287 |
288 | /* Configure DMA Stream source address */
289 | hdma->Instance->M0AR = SrcAddress;
290 | }
291 | /* Memory to Peripheral */
292 | else
293 | {
294 | /* Configure DMA Stream source address */
295 | hdma->Instance->PAR = SrcAddress;
296 |
297 | /* Configure DMA Stream destination address */
298 | hdma->Instance->M0AR = DstAddress;
299 | }
300 | }
301 |
302 | /**
303 | * @}
304 | */
305 |
306 | #endif /* HAL_DMA_MODULE_ENABLED */
307 | /**
308 | * @}
309 | */
310 |
311 | /**
312 | * @}
313 | */
314 |
315 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
316 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/.settings/org.eclipse.cdt.codan.core.prefs:
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hal_gpio.h
4 | * @author MCD Application Team
5 | * @brief Header file of GPIO HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2017 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __STM32F4xx_HAL_GPIO_H
22 | #define __STM32F4xx_HAL_GPIO_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32F4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup GPIO
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup GPIO_Exported_Types GPIO Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief GPIO Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
50 | This parameter can be any value of @ref GPIO_pins_define */
51 |
52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
53 | This parameter can be a value of @ref GPIO_mode_define */
54 |
55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
56 | This parameter can be a value of @ref GPIO_pull_define */
57 |
58 | uint32_t Speed; /*!< Specifies the speed for the selected pins.
59 | This parameter can be a value of @ref GPIO_speed_define */
60 |
61 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
62 | This parameter can be a value of @ref GPIO_Alternate_function_selection */
63 | }GPIO_InitTypeDef;
64 |
65 | /**
66 | * @brief GPIO Bit SET and Bit RESET enumeration
67 | */
68 | typedef enum
69 | {
70 | GPIO_PIN_RESET = 0,
71 | GPIO_PIN_SET
72 | }GPIO_PinState;
73 | /**
74 | * @}
75 | */
76 |
77 | /* Exported constants --------------------------------------------------------*/
78 |
79 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
80 | * @{
81 | */
82 |
83 | /** @defgroup GPIO_pins_define GPIO pins define
84 | * @{
85 | */
86 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
87 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
88 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
89 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
90 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
91 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
92 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
93 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
94 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
95 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
96 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
97 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
98 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
99 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
100 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
101 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
102 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
103 |
104 | #define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
105 | /**
106 | * @}
107 | */
108 |
109 | /** @defgroup GPIO_mode_define GPIO mode define
110 | * @brief GPIO Configuration Mode
111 | * Elements values convention: 0xX0yz00YZ
112 | * - X : GPIO mode or EXTI Mode
113 | * - y : External IT or Event trigger detection
114 | * - z : IO configuration on External IT or Event
115 | * - Y : Output type (Push Pull or Open Drain)
116 | * - Z : IO Direction mode (Input, Output, Alternate or Analog)
117 | * @{
118 | */
119 | #define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
120 | #define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
121 | #define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
122 | #define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
123 | #define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
124 |
125 | #define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
126 |
127 | #define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
128 | #define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
129 | #define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
130 |
131 | #define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
132 | #define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
133 | #define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
134 | /**
135 | * @}
136 | */
137 |
138 | /** @defgroup GPIO_speed_define GPIO speed define
139 | * @brief GPIO Output Maximum frequency
140 | * @{
141 | */
142 | #define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
143 | #define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
144 | #define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
145 | #define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup GPIO_pull_define GPIO pull define
151 | * @brief GPIO Pull-Up or Pull-Down Activation
152 | * @{
153 | */
154 | #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
155 | #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
156 | #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
157 | /**
158 | * @}
159 | */
160 |
161 | /**
162 | * @}
163 | */
164 |
165 | /* Exported macro ------------------------------------------------------------*/
166 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
167 | * @{
168 | */
169 |
170 | /**
171 | * @brief Checks whether the specified EXTI line flag is set or not.
172 | * @param __EXTI_LINE__ specifies the EXTI line flag to check.
173 | * This parameter can be GPIO_PIN_x where x can be(0..15)
174 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
175 | */
176 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
177 |
178 | /**
179 | * @brief Clears the EXTI's line pending flags.
180 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
181 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
182 | * @retval None
183 | */
184 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
185 |
186 | /**
187 | * @brief Checks whether the specified EXTI line is asserted or not.
188 | * @param __EXTI_LINE__ specifies the EXTI line to check.
189 | * This parameter can be GPIO_PIN_x where x can be(0..15)
190 | * @retval The new state of __EXTI_LINE__ (SET or RESET).
191 | */
192 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
193 |
194 | /**
195 | * @brief Clears the EXTI's line pending bits.
196 | * @param __EXTI_LINE__ specifies the EXTI lines to clear.
197 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
198 | * @retval None
199 | */
200 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
201 |
202 | /**
203 | * @brief Generates a Software interrupt on selected EXTI line.
204 | * @param __EXTI_LINE__ specifies the EXTI line to check.
205 | * This parameter can be GPIO_PIN_x where x can be(0..15)
206 | * @retval None
207 | */
208 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
209 | /**
210 | * @}
211 | */
212 |
213 | /* Include GPIO HAL Extension module */
214 | #include "stm32f4xx_hal_gpio_ex.h"
215 |
216 | /* Exported functions --------------------------------------------------------*/
217 | /** @addtogroup GPIO_Exported_Functions
218 | * @{
219 | */
220 |
221 | /** @addtogroup GPIO_Exported_Functions_Group1
222 | * @{
223 | */
224 | /* Initialization and de-initialization functions *****************************/
225 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
226 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
227 | /**
228 | * @}
229 | */
230 |
231 | /** @addtogroup GPIO_Exported_Functions_Group2
232 | * @{
233 | */
234 | /* IO operation functions *****************************************************/
235 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
236 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
237 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
238 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
239 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
240 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
241 |
242 | /**
243 | * @}
244 | */
245 |
246 | /**
247 | * @}
248 | */
249 | /* Private types -------------------------------------------------------------*/
250 | /* Private variables ---------------------------------------------------------*/
251 | /* Private constants ---------------------------------------------------------*/
252 | /** @defgroup GPIO_Private_Constants GPIO Private Constants
253 | * @{
254 | */
255 |
256 | /**
257 | * @}
258 | */
259 |
260 | /* Private macros ------------------------------------------------------------*/
261 | /** @defgroup GPIO_Private_Macros GPIO Private Macros
262 | * @{
263 | */
264 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
265 | #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
266 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
267 | ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
268 | ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
269 | ((MODE) == GPIO_MODE_AF_PP) ||\
270 | ((MODE) == GPIO_MODE_AF_OD) ||\
271 | ((MODE) == GPIO_MODE_IT_RISING) ||\
272 | ((MODE) == GPIO_MODE_IT_FALLING) ||\
273 | ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
274 | ((MODE) == GPIO_MODE_EVT_RISING) ||\
275 | ((MODE) == GPIO_MODE_EVT_FALLING) ||\
276 | ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
277 | ((MODE) == GPIO_MODE_ANALOG))
278 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
279 | ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
280 | #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
281 | ((PULL) == GPIO_PULLDOWN))
282 | /**
283 | * @}
284 | */
285 |
286 | /* Private functions ---------------------------------------------------------*/
287 | /** @defgroup GPIO_Private_Functions GPIO Private Functions
288 | * @{
289 | */
290 |
291 | /**
292 | * @}
293 | */
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | #ifdef __cplusplus
304 | }
305 | #endif
306 |
307 | #endif /* __STM32F4xx_HAL_GPIO_H */
308 |
309 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
310 |
--------------------------------------------------------------------------------
/TrueStudio/W5x00-HTTPClient/Inc/webpage.h:
--------------------------------------------------------------------------------
1 | #ifndef _WEBPAGE_H_
2 | #define _WEBPAGE_H_
3 |
4 | /*************************************************************************************
5 | * JavaScript Functions
6 | *************************************************************************************/
7 |
8 | #define w5x00web_ajax_js "function AJAX(a,e){var c=d();c.onreadystatechange=b;function d(){if(window.XMLHttpRequest){return new XMLHttpRequest()}else{if(window.ActiveXObject){return new ActiveXObject(\"Microsoft.XMLHTTP\")}}}function b(){if(c.readyState==4){if(c.status==200){if(e){e(c.responseText)}}}}this.doGet=function(){c.open(\"GET\",a,true);c.send(null)};this.doPost=function(f){c.open(\"POST\",a,true);c.setRequestHeader(\"Content-Type\",\"application/x-www-form-urlencoded\");c.setRequestHeader(\"ISAJAX\",\"yes\");c.send(f)}}function $(a){return document.getElementById(a)}function $$(a){return document.getElementsByName(a)}function $$_ie(a,c){if(!a){a=\"*\"}var b=document.getElementsByTagName(a);var e=[];for(var d=0;d"\
72 | ""\
73 | "w5x00 Web Server"\
74 | ""\
75 | ""\
76 | ""\
77 | ""\
78 | "w5x00 Web Server Demopage"\
79 | "
"\
80 | "
"\
81 | "Network Information"\
82 | "
"\
83 | "Base64 Image Data"\
84 | "
"\
85 | " Digital I/O RGB LED"\
86 | ""\
87 | "