├── 8bit CPU clock board.pdf ├── Arithmatic logic unit.pdf ├── Arithmatic unit.pdf ├── Backplane.zip ├── Fib10 ASM.txt ├── Fibonacci workout 1 - 13 ASM.txt ├── Fibonacci workout 1 - 255 ASM.txt ├── IO+ROM board.pdf ├── IOROM board.zip ├── IOport.png ├── IR and control.zip ├── IR&control.pdf ├── LCD test.txt ├── LED disp test.txt ├── Memory board.pdf ├── Memory board.zip ├── PC+dispDecoder.pdf ├── PCdisp decode.zip ├── README.md ├── ROMCARTgerber.zip ├── Register board.pdf ├── Sound board.pdf ├── Sound_Board.zip ├── arithmatic unit.zip ├── aritmatic logic unit.zip ├── bootload.txt ├── clock board.zip ├── dispDecode HEX OCT.bin ├── dispDecodeDEC.bin ├── division.txt ├── instruction converter cheat sheet.txt ├── instruction set.doc ├── microcode high.BIN ├── microcode low.BIN ├── microcode mid.BIN ├── mutliply.txt ├── oldromdump.bin └── register board.zip /8bit CPU clock board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/8bit CPU clock board.pdf -------------------------------------------------------------------------------- /Arithmatic logic unit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Arithmatic logic unit.pdf -------------------------------------------------------------------------------- /Arithmatic unit.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Arithmatic unit.pdf -------------------------------------------------------------------------------- /Backplane.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Backplane.zip -------------------------------------------------------------------------------- /Fib10 ASM.txt: -------------------------------------------------------------------------------- 1 | 00: 74 01 2E MOV 1, 2E 'init some locations in memory 2 | 03: 74 00 2D MOV 0, 2D 3 | 06: 74 0A 31 MOV 10, 31 'set to iteration of fibonacci to calculate (max 13) 4 | 09: 71 31 DEC 1, 31 'decrement iteration count 5 | 0B: 28 1F JPZ 1F 'when iteration count is zero jump to 1Fh 6 | 7 | 0D: 04 2D LDA 2D 8 | 0F: 08 2E ADD 2E 9 | 11: 18 2F STA 2F 10 | 13: 04 2E LDA 2E 11 | 15: 18 2D STA 2D 12 | 17: 04 2F LDA 2F 13 | 19: 18 2E STA 2E 14 | 1B: 04 2D LDA 2D 15 | 1D: 10 09 JMP 09 'loop 16 | 1F: 24 2E OPM 2E 'output result from 2E 17 | 21: 1C 99 LDI 99h 'load tone value to A 18 | 23 80 MOV A, E 'load into sound register 19 | 24 1C 00 LDI 00 'load value to A register which 20 | 26 80 MOV A, E 'turns off the sound 21 | 27 FC HLT 'stop 22 | 23 | 74 01 2E 74 00 2D 74 0A 31 71 31 28 1F 04 2D 08 2E 18 2F 04 2E 18 2D 04 2F 18 2E 04 2D 10 09 24 2E 1C 99 80 1C 00 80 FC -------------------------------------------------------------------------------- /Fibonacci workout 1 - 13 ASM.txt: -------------------------------------------------------------------------------- 1 | 00: 74 01 2E MOV 1, 2E 'init some locations in memory 2 | 03: 74 00 2D MOV 0, 2D 3 | 06: 74 01 31 MOV 1, 31 'set to iteration of fibonacci to calculate (max 13) 4 | 09: 71 31 DEC 1, 31 'decrement iteration count 5 | 0B: 28 1F JPZ 1F 'when iteration count is zero jump to 1Fh 6 | 7 | 0D: 04 2D LDA 2D 8 | 0F: 08 2E ADD 2E 9 | 11: 18 2F STA 2F 10 | 13: 04 2E LDA 2E 11 | 15: 18 2D STA 2D 12 | 17: 04 2F LDA 2F 13 | 19: 18 2E STA 2E 14 | 1B: 04 2D LDA 2D 15 | 1D: 10 09 JMP 09 'loop 16 | 1F: 24 2E OPM 2E 'output result from 2E 17 | 21: 6D 07 INC 07, 1 18 | 23 7C MOV A, D 'Display iteration num on D register 19 | 24 40 0D(13dec) SUI 13(dec) 'check if iteration count is 13 20 | 26 28 29 JPZ 29 'jump if result is 0 21 | 28 A4 RET 'shortcut to reset PC to 0 22 | 'C register should be 0 23 | 29 74 01 07 MOV 1, 7 'reset location 7 back to 1 24 | 2C FC HLT 'stop 25 | 26 | -------------------------------------------------------------------------------- /Fibonacci workout 1 - 255 ASM.txt: -------------------------------------------------------------------------------- 1 | 00: 74 01 2E MOV 1, 2E 'init some locations in memory 2 | 03: 74 00 2D MOV 0, 2D 3 | 06: 74 01 31 MOV 10, 31 'set to iteration of fibonacci to calculate (max 13) 4 | 09: 71 31 DEC 1, 31 'decrement iteration count 5 | 0B: 28 1F JPZ 1F 'when iteration count is zero jump to 1Fh 6 | 7 | 0D: 04 2D LDA 2D 8 | 0F: 08 2E ADD 2E 9 | 11: 18 2F STA 2F 10 | 13: 04 2E LDA 2E 11 | 15: 18 2D STA 2D 12 | 17: 04 2F LDA 2F 13 | 19: 18 2E STA 2E 14 | 1B: 04 2D LDA 2D 15 | 1D: 10 09 JMP 09 'loop 16 | 1F: 24 2E OPM 2E 'output result from 2E 17 | 21: 6D 07 INC 07, 1 18 | 23 30 27 JPC 27 19 | 25 A4 RET 20 | 21 | 27 FC HLT 'stop 22 | 23 | 74 01 2E 74 00 2D 74 0A 31 71 31 28 1F 04 2D 08 2E 18 2F 04 2E 18 2D 04 2F 18 2E 04 2D 10 09 24 2E 1C 99 80 1C 00 80 FC -------------------------------------------------------------------------------- /IO+ROM board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/IO+ROM board.pdf -------------------------------------------------------------------------------- /IOROM board.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/IOROM board.zip -------------------------------------------------------------------------------- /IOport.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/IOport.png -------------------------------------------------------------------------------- /IR and control.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/IR and control.zip -------------------------------------------------------------------------------- /IR&control.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/IR&control.pdf -------------------------------------------------------------------------------- /LCD test.txt: -------------------------------------------------------------------------------- 1 | 00: 74 24 FA MOV 24 FA 2 | 03: 74 2A FB MOV 2A FB 3 | 06: 68 FA IOP FA 4 | 08: 44 00 OPI 00 5 | 0A: 6D FA INC 1 FA 6 | 0C: 0C FB SUB FB 7 | 0E: 28 12 JPZ 12 8 | 10: 10 06 JMP 06 9 | 12: 74 2B F8 MOV 2B F8 10 | 15: 74 E4 F9 MOV E4 F9 11 | 18: 68 F8 IOP F8 12 | 1A: 44 00 OPI 00 13 | 1C: 6D F8 INC 1, F8 14 | 1E: 0C F9 SUB F9 15 | 20: 28 12 JPZ 12 16 | 22: 10 18 JMP 18 17 | 18 | 19 | LCD DATA 24- E4 20 | 21 21 81 01 E1 01 61 33 83 23 03 63 23 63 93 73 43 23 03 43 43 63 93 73 33 63 33 73 23 63 53 73 43 63 53 23 03 23 03 23 03 C1 01 43 C3 63 F3 63 73 63 93 63 33 23 03 43 33 53 03 53 53 23 03 23 03 23 03 01 11 01 21 33 23 33 53 33 63 23 03 43 23 73 93 73 43 63 53 73 33 23 03 43 D3 63 53 63 D3 63 F3 73 23 73 93 C1 01 33 33 33 63 23 03 43 93 63 E3 73 33 73 43 73 23 73 53 63 33 73 43 63 93 63 F3 63 E3 73 33 23 03 23 03 23 03 01 11 01 21 33 83 23 03 63 23 63 93 73 43 23 03 43 93 23 F3 43 F3 C1 01 33 83 23 03 63 23 63 93 73 43 23 03 43 13 43 C3 53 53 23 03 23 03 23 03 01 11 01 21 21 | 22 | 23 | 24 | 25 | 26 | 74 24 FA 74 2A FB 68 FA 0C FB 28 12 10 06 74 2B F8 74 E4 F9 68 F8 44 00 6D F8 0C F9 28 12 10 18 21 21 81 01 E1 01 61 33 83 23 03 63 23 63 93 73 43 23 03 43 43 63 93 73 33 63 33 73 23 63 53 73 43 63 53 23 03 23 03 23 03 C1 01 43 C3 63 F3 63 73 63 93 63 33 23 03 43 33 53 03 53 53 23 03 23 03 23 03 01 11 01 21 33 23 33 53 33 63 23 03 43 23 73 93 73 43 63 53 73 33 23 03 43 D3 63 53 63 D3 63 F3 73 23 73 93 C1 01 33 33 33 63 23 03 43 93 63 E3 73 33 73 43 73 23 73 53 63 33 73 43 63 93 63 F3 63 E3 73 33 23 03 23 03 23 03 01 11 01 21 33 83 23 03 63 23 63 93 73 43 23 03 43 93 23 F3 43 F3 C1 01 33 83 23 03 63 23 63 93 73 43 23 03 43 13 43 C3 53 53 23 03 23 03 23 03 01 11 01 21 -------------------------------------------------------------------------------- /LED disp test.txt: -------------------------------------------------------------------------------- 1 | 00: 74 10 F6 MOV 10 F6 'Start location in memory 2 | 03: 74 72 F5 MOV 72 F5 'End location in memory 3 | 06: 68 F6 IOP F6 4 | 08: 6D F6 INC 1, F6 5 | 0A: 0C F5 SUB F5 6 | 0C: 28 00 JPZ 00 7 | 0E: 10 06 JMP 06 8 | DATA: 10h - 72h 9 | F7 00 37 84 33 00 97 84 76 63 E1 73 33 73 00 23 17 67 84 63 00 63 F1 A7 08 00 08 00 08 00 D3 76 77 00 37 B6 33 73 76 00 F1 E1 17 67 00 76 F1 F5 63 73 00 D6 E7 00 84 E5 76 33 E1 A7 63 33 84 17 E5 76 00 F7 00 37 84 33 00 84 E5 F1 A7 33 00 17 A7 33 F1 A7 33 00 F7 00 37 84 33 00 F5 23 A7 00 00 00 00 10 | 11 | 12 | 13 | RAW DUMP 14 | 74 10 F6 74 72 F5 68 F6 6D F6 0C F5 28 00 10 06 F7 00 37 84 33 00 97 84 76 63 E1 73 33 73 00 23 17 67 84 63 00 63 F1 A7 08 00 08 00 08 00 D3 76 77 00 37 B6 33 73 76 00 F1 E1 17 67 00 76 F1 F5 63 73 00 D6 E7 00 84 E5 76 33 E1 A7 63 33 84 17 E5 76 00 F7 00 37 84 33 00 84 E5 F1 A7 33 00 17 A7 33 F1 A7 33 00 F7 00 37 84 33 00 F5 23 A7 00 00 00 00 -------------------------------------------------------------------------------- /Memory board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Memory board.pdf -------------------------------------------------------------------------------- /Memory board.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Memory board.zip -------------------------------------------------------------------------------- /PC+dispDecoder.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/PC+dispDecoder.pdf -------------------------------------------------------------------------------- /PCdisp decode.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/PCdisp decode.zip -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DiscreteLogicCPU 2 | ROM dumps and other information for my version of the 8 bit computer 3 | all ROM's are 28c16's 4 | 5 | I have included the instruction set, and copies of the ROM's used in my machine, I have made schematics and PCB layouts, keep an eye out for the changes as there are some mistakes on those, I need to update the github with the new schematics with corrections 6 | -------------------------------------------------------------------------------- /ROMCARTgerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/ROMCARTgerber.zip -------------------------------------------------------------------------------- /Register board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Register board.pdf -------------------------------------------------------------------------------- /Sound board.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Sound board.pdf -------------------------------------------------------------------------------- /Sound_Board.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/Sound_Board.zip -------------------------------------------------------------------------------- /arithmatic unit.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/arithmatic unit.zip -------------------------------------------------------------------------------- /aritmatic logic unit.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/aritmatic logic unit.zip -------------------------------------------------------------------------------- /bootload.txt: -------------------------------------------------------------------------------- 1 | ROM bootstrap 2 | Loads in 248 bytes from ROM 3 | attached to IO port 4 | 5 | Newer bootstrap, uses A register, uses less space and has potential to be in a ROM 6 | 7 | 00 10, F8 8 | 9 | F7: 00 NOP 'set to 00, will be set to A4 (return) when finished 10 | F8: 38 OUT A 'output value in A 11 | F9: A0 AIN 'use value in A as memory address then read inputs into there 12 | FA: AD INC A, 1 'increment A 13 | FB: 10 F7 JMP F7 'loop 14 | 15 | 16 | Old bootstrap 17 | 00: 10, F8 JMP F8 18 | . 19 | . 20 | . 21 | F7: 00 22 | F8: 44, 00 OPI 00 23 | FA: 60, F8 INI F8 24 | FC: 6D, F8 INC 1, F8 25 | FE: 10, F7 JMP F7 26 | -------------------------------------------------------------------------------- /clock board.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/clock board.zip -------------------------------------------------------------------------------- /dispDecode HEX OCT.bin: -------------------------------------------------------------------------------- 1 | 7777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~0my3[_p{wN=OG~~~~~~~~~~~~~~~~0000000000000000mmmmmmmmmmmmmmmmyyyyyyyyyyyyyyyy3333333333333333[[[[[[[[[[[[[[[[________________pppppppppppppppp{{{{{{{{{{{{{{{{wwwwwwwwwwwwwwwwNNNNNNNNNNNNNNNN================OOOOOOOOOOOOOOOOGGGGGGGGGGGGGGGG~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~0my3[_p~~~~~~~~00000000mmmmmmmmyyyyyyyy33333333[[[[[[[[________pppppppp~~~~~~~~00000000mmmmmmmmyyyyyyyy33333333[[[[[[[[________pppppppp~~~~~~~~00000000mmmmmmmmyyyyyyyy33333333[[[[[[[[________pppppppp~~~~~~~~00000000mmmmmmmmyyyyyyyy33333333[[[[[[[[________pppppppp~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0000000000000000000000000000000000000000000000000000000000000000mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy -------------------------------------------------------------------------------- /dispDecodeDEC.bin: -------------------------------------------------------------------------------- 1 | ~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[~~~~~~~~~~0000000000mmmmmmmmmmyyyyyyyyyy3333333333[[[[[[[[[[__________pppppppppp{{{{{{{{{{~~~~~~~~~~0000000000mmmmmmmmmmyyyyyyyyyy3333333333[[[[[[[[[[__________pppppppppp{{{{{{{{{{~~~~~~~~~~0000000000mmmmmmmmmmyyyyyyyyyy3333333333[[[[[[~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_p{~0my3[_pp_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~{p_[3ym0~~~~~~~~~~0000000000mmmmmmmmmmyyyyyyyyyy3333333333[[[[[[[[[[__________pppppppppp{{{{{{{{{{~~~~~~~~~~0000000000mmmmmmmmmmmmmmmmm0000000000~~~~~~~~~~{{{{{{{{{{pppppppppp__________[[[[[[[[[[3333333333yyyyyyyyyymmmmmmmmmm0000000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000000000000000000000000000000000000000000000000000000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------- /division.txt: -------------------------------------------------------------------------------- 1 | 00: 74 0F 24 MOV 0F 24 2 | 03: 74 03 25 MOV 03 25 3 | 06: 74 00 26 MOV 00 26 4 | 09: 6D 26 INC 1, 26 5 | 0B: 04 24 LDA 24 6 | 0D: 0C 25 SUB 25 7 | 0F: 18 24 STA 24 8 | 11: 28 17 JPZ 16 9 | 13: 10 09 JMP 09 10 | 11 | 17: 24 26 OPM 26 12 | 19: FC HLT 13 | 14 | 74 0F 24 74 03 25 74 00 26 6D 26 04 24 0C 25 18 24 28 17 10 09 24 26 FC -------------------------------------------------------------------------------- /instruction converter cheat sheet.txt: -------------------------------------------------------------------------------- 1 | instruction old new 2 | 3 | LDA 10 04 4 | ADD 20 08 5 | SUB 30 0C 6 | JMP 40 10 7 | STA 60 18 8 | INM 80 20 9 | OPM 90 24 10 | JPZ A0 28 11 | JNZ B0 2C 12 | JPC C0 30 13 | JNC D0 34 14 | OUT E0 38 15 | OPI 14 44 16 | INI 84 60 17 | INM 80 20 18 | INC B4 6C 19 | DEC C4 70 20 | INC A B8 AC 21 | DEC A C8 B0 22 | SUI 04 40 23 | MOV XX YY D4 74 24 | IOP A4 68 25 | 26 | INI 84 60 27 | -------------------------------------------------------------------------------- /instruction set.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/instruction set.doc -------------------------------------------------------------------------------- /microcode high.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/microcode high.BIN -------------------------------------------------------------------------------- /microcode low.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/microcode low.BIN -------------------------------------------------------------------------------- /microcode mid.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/microcode mid.BIN -------------------------------------------------------------------------------- /mutliply.txt: -------------------------------------------------------------------------------- 1 | 00: 74 03 20 MOV 03, 20 2 | 03: 74 05 21 MOV 05, 21 3 | 06: 74 00 22 MOV 00, 22 4 | 09: 04 20 LDA 20 5 | 0B: 08 22 ADD 22 6 | 0D: 18 22 STA 22 7 | 0F: 71 21 DEC 21 8 | 11: 28 15 JPZ 15 9 | 13: 10 09 JMP 09 10 | 15: 24 22 OPM 22 11 | 17: FC HLT 12 | 13 | 14 | 15 | 74 03 20 74 05 21 74 00 22 04 20 08 22 18 22 71 21 28 15 10 08 24 22 FC -------------------------------------------------------------------------------- /oldromdump.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/oldromdump.bin -------------------------------------------------------------------------------- /register board.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WRFleete/DiscreteLogicCPU/144daef4337bedb8e1265c4dda6cbd8b480dff8b/register board.zip --------------------------------------------------------------------------------