├── Tutorial ├── Tutorial.runs │ ├── impl_1 │ │ ├── .vivado.end.rst │ │ ├── .init_design.end.rst │ │ ├── .opt_design.end.rst │ │ ├── .place_design.end.rst │ │ ├── .route_design.end.rst │ │ ├── .phys_opt_design.end.rst │ │ ├── .write_bitstream.end.rst │ │ ├── .Vivado_Implementation.queue.rst │ │ ├── vivado.pb │ │ ├── Add_half.bit │ │ ├── init_design.pb │ │ ├── opt_design.pb │ │ ├── Add_half_opt.dcp │ │ ├── place_design.pb │ │ ├── route_design.pb │ │ ├── Add_half_placed.dcp │ │ ├── Add_half_routed.dcp │ │ ├── phys_opt_design.pb │ │ ├── write_bitstream.pb │ │ ├── Add_half_drc_opted.pb │ │ ├── Add_half_physopt.dcp │ │ ├── Add_half_drc_opted.rpx │ │ ├── Add_half_drc_routed.pb │ │ ├── Add_half_drc_routed.rpx │ │ ├── Add_half_route_status.pb │ │ ├── Add_half_power_routed.rpx │ │ ├── Add_half_bus_skew_routed.pb │ │ ├── Add_half_bus_skew_routed.rpx │ │ ├── Add_half_utilization_placed.pb │ │ ├── Add_half_methodology_drc_routed.pb │ │ ├── Add_half_power_summary_routed.pb │ │ ├── Add_half_timing_summary_routed.pb │ │ ├── Add_half_timing_summary_routed.rpx │ │ ├── Add_half_methodology_drc_routed.rpx │ │ ├── .init_design.begin.rst │ │ ├── .opt_design.begin.rst │ │ ├── .place_design.begin.rst │ │ ├── .route_design.begin.rst │ │ ├── .phys_opt_design.begin.rst │ │ ├── .write_bitstream.begin.rst │ │ ├── runme.bat │ │ ├── htr.txt │ │ ├── .vivado.begin.rst │ │ ├── Add_half_route_status.rpt │ │ ├── vivado.jou │ │ ├── vivado_26744.backup.jou │ │ ├── Add_half_bus_skew_routed.rpt │ │ ├── runme.sh │ │ ├── rundef.js │ │ ├── Add_half_methodology_drc_routed.rpt │ │ ├── Add_half_drc_opted.rpt │ │ ├── Add_half_drc_routed.rpt │ │ ├── ISEWrap.sh │ │ ├── project.wdf │ │ ├── Add_half_control_sets_placed.rpt │ │ ├── Add_half.tcl │ │ ├── Add_half_clock_utilization_routed.rpt │ │ ├── gen_run.xml │ │ ├── Add_half_power_routed.rpt │ │ ├── ISEWrap.js │ │ ├── Add_half_utilization_placed.rpt │ │ └── Add_half_timing_summary_routed.rpt │ ├── synth_1 │ │ ├── .vivado.end.rst │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── __synthesis_is_complete__ │ │ ├── vivado.pb │ │ ├── Add_half.dcp │ │ ├── incr_synth_reason.pb │ │ ├── Add_half_utilization_synth.pb │ │ ├── .vivado.begin.rst │ │ ├── runme.bat │ │ ├── htr.txt │ │ ├── vivado.jou │ │ ├── .Xil │ │ │ └── Add_half_propImpl.xdc │ │ ├── runme.sh │ │ ├── rundef.js │ │ ├── ISEWrap.sh │ │ ├── gen_run.xml │ │ ├── project.wdf │ │ ├── Add_half.tcl │ │ ├── Add_half_utilization_synth.rpt │ │ └── ISEWrap.js │ └── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ ├── vrs_config_3.xml │ │ ├── vrs_config_4.xml │ │ └── vrs_config_5.xml ├── Tutorial.cache │ └── wt │ │ ├── synthesis_details.wdf │ │ ├── project.wpc │ │ ├── webtalk_pa.xml │ │ └── synthesis.wdf ├── Tutorial.srcs │ ├── utils_1 │ │ └── imports │ │ │ └── synth_1 │ │ │ └── Add_half.dcp │ └── sources_1 │ │ ├── new │ │ └── half_adder.v │ │ └── bd │ │ └── half_adder │ │ ├── ui │ │ └── bd_8ef7dec2.ui │ │ ├── half_adder.bd │ │ ├── ip │ │ └── half_adder_Add_half_0_0 │ │ │ └── half_adder_Add_half_0_0.xci │ │ └── half_adder.bda ├── Tutorial.gen │ └── sources_1 │ │ └── bd │ │ ├── mref │ │ └── Add_half │ │ │ ├── xgui │ │ │ └── Add_half_v1_0.tcl │ │ │ └── component.xml │ │ └── half_adder │ │ ├── half_adder.bxml │ │ ├── half_adder.bda │ │ └── ip │ │ └── half_adder_Add_half_0_0 │ │ └── half_adder_Add_half_0_0.xml ├── Tutorial.hw │ ├── Tutorial.lpr │ └── hw_1 │ │ └── hw.xml └── Tutorial.xpr ├── .gitattributes ├── Resource ├── 1.jpg ├── 2.jpg ├── 3.jpg ├── 4.jpg ├── 5.jpg ├── 6.jpg ├── 7.jpg ├── 8.jpg ├── 9.jpg ├── 10.jpg ├── 11.jpg ├── 12.jpg ├── 13.jpg ├── 14.jpg ├── 15.jpg ├── 16.jpg ├── 17.jpg ├── 18.jpg ├── 19.jpg ├── 20.jpg ├── 21.jpg ├── 22.jpg ├── 23.jpg ├── 24.jpg ├── 25.jpg ├── 26.jpg ├── 27.jpg ├── 28.jpg ├── 29.jpg ├── 30.jpg ├── 31.jpg ├── 32.jpg ├── 33.jpg ├── 34.jpg └── 35.jpg ├── pynqz2_user_manual_v1_0.pdf ├── Document ├── PYNQ-Z2电路图 │ └── PYNQ电路图.pdf ├── PYNQ-Z2参考实验 │ ├── PYNQ-Z2 基础开发实验资料.pdf │ └── PYNQ-Z2 Python开发实验资料.pdf ├── PYNQ-Z2用户手册 │ └── pynqz2_user_manual_v1_0.pdf └── PYNQ-Z2板卡文件 │ └── PYNQ-Z2 board file v1.0 │ └── A.0 │ ├── pynq_z2.jpg │ └── part0_pins.xml └── README.md /Tutorial/Tutorial.runs/impl_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/.init_design.end.rst: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/.opt_design.end.rst: -------------------------------------------------------------------------------- 1 | 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-------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/.write_bitstream.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.srcs/sources_1/new/half_adder.v: -------------------------------------------------------------------------------- 1 | module Add_half (sum, c_out, a, b); 2 | input a, b; 3 | output sum, c_out; 4 | wire c_out_bar; 5 | xor (sum, a, b); 6 | nand (c_out_bar, a, b); 7 | not (c_out, c_out_bar); 8 | endmodule 9 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.gen/sources_1/bd/mref/Add_half/xgui/Add_half_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.hw/Tutorial.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/.jobs/vrs_config_4.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log Add_half.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Add_half.tcl 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/.jobs/vrs_config_5.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log Add_half.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Add_half.tcl -notrace 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_route_status.rpt: -------------------------------------------------------------------------------- 1 | Design Route Status 2 | : # nets : 3 | ------------------------------------------- : ----------- : 4 | # of logical nets.......................... : 8 : 5 | # of nets not needing routing.......... : 4 : 6 | # of internally routed nets........ : 4 : 7 | # of routable nets..................... : 4 : 8 | # of fully routed nets............. : 4 : 9 | # of nets with routing errors.......... : 0 : 10 | ------------------------------------------- : ----------- : 11 | 12 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.gen/sources_1/bd/half_adder/half_adder.bxml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | Composite Fileset 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2022.2 (64-bit) 3 | # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 4 | # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 5 | # Start of session at: Sat Feb 18 00:28:15 2023 6 | # Process ID: 26420 7 | # Current directory: E:/Projects/Tutorial/Tutorial.runs/synth_1 8 | # Command line: vivado.exe -log Add_half.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Add_half.tcl 9 | # Log file: E:/Projects/Tutorial/Tutorial.runs/synth_1/Add_half.vds 10 | # Journal file: E:/Projects/Tutorial/Tutorial.runs/synth_1\vivado.jou 11 | # Running On: Albert-G14, OS: Windows, CPU Frequency: 2895 MHz, CPU Physical cores: 16, Host memory: 16556 MB 12 | #----------------------------------------------------------- 13 | source Add_half.tcl -notrace 14 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2022.2 (64-bit) 3 | # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 4 | # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 5 | # Start of session at: Sat Feb 18 00:31:53 2023 6 | # Process ID: 25432 7 | # Current directory: E:/Projects/Tutorial/Tutorial.runs/impl_1 8 | # Command line: vivado.exe -log Add_half.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Add_half.tcl -notrace 9 | # Log file: E:/Projects/Tutorial/Tutorial.runs/impl_1/Add_half.vdi 10 | # Journal file: E:/Projects/Tutorial/Tutorial.runs/impl_1\vivado.jou 11 | # Running On: Albert-G14, OS: Windows, CPU Frequency: 2895 MHz, CPU Physical cores: 16, Host memory: 16556 MB 12 | #----------------------------------------------------------- 13 | source Add_half.tcl -notrace 14 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/vivado_26744.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2022.2 (64-bit) 3 | # SW Build 3671981 on Fri Oct 14 05:00:03 MDT 2022 4 | # IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 5 | # Start of session at: Sat Feb 18 00:29:21 2023 6 | # Process ID: 26744 7 | # Current directory: E:/Projects/Tutorial/Tutorial.runs/impl_1 8 | # Command line: vivado.exe -log Add_half.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Add_half.tcl -notrace 9 | # Log file: E:/Projects/Tutorial/Tutorial.runs/impl_1/Add_half.vdi 10 | # Journal file: E:/Projects/Tutorial/Tutorial.runs/impl_1\vivado.jou 11 | # Running On: Albert-G14, OS: Windows, CPU Frequency: 2895 MHz, CPU Physical cores: 16, Host memory: 16556 MB 12 | #----------------------------------------------------------- 13 | source Add_half.tcl -notrace 14 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/.Xil/Add_half_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:{E:/Projects/Tutorial/Tutorial.srcs/constrs_1/imports/pynq-z2_v1.0.xdc/PYNQ-Z2 v1.0.xdc} rfile:{../../../Tutorial.srcs/constrs_1/imports/pynq-z2_v1.0.xdc/PYNQ-Z2 v1.0.xdc} id:1} [current_design] 2 | set_property src_info {type:XDC file:1 line:195 export:INPUT save:INPUT read:READ} [current_design] 3 | set_property PACKAGE_PIN M19 [get_ports a] 4 | set_property src_info {type:XDC file:1 line:196 export:INPUT save:INPUT read:READ} [current_design] 5 | set_property PACKAGE_PIN M20 [get_ports b] 6 | set_property src_info {type:XDC file:1 line:197 export:INPUT save:INPUT read:READ} [current_design] 7 | set_property PACKAGE_PIN P14 [get_ports c_out] 8 | set_property src_info {type:XDC file:1 line:198 export:INPUT save:INPUT read:READ} [current_design] 9 | set_property PACKAGE_PIN R14 [get_ports sum] 10 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_bus_skew_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:19 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_bus_skew -warn_on_violation -file Add_half_bus_skew_routed.rpt -pb Add_half_bus_skew_routed.pb -rpx Add_half_bus_skew_routed.rpx 7 | | Design : Add_half 8 | | Device : 7z020-clg400 9 | | Speed File : -1 PRODUCTION 1.12 2019-11-22 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Bus Skew Report 13 | 14 | No bus skew constraints 15 | 16 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.srcs/sources_1/bd/half_adder/ui/bd_8ef7dec2.ui: -------------------------------------------------------------------------------- 1 | { 2 | "ActiveEmotionalView":"Default View", 3 | "Default View_ScaleFactor":"1.0", 4 | "Default View_TopLeft":"-505,-259", 5 | "ExpandedHierarchyInLayout":"", 6 | "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS 7 | # -string -flagsOSRD 8 | preplace port port-id_LED0 -pg 1 -lvl 2 -x 220 -y 0 -defaultsOSRD 9 | preplace port port-id_LED1 -pg 1 -lvl 2 -x 220 -y 20 -defaultsOSRD 10 | preplace port port-id_SW0 -pg 1 -lvl 0 -x -10 -y 0 -defaultsOSRD 11 | preplace port port-id_SW1 -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD 12 | preplace inst Add_half_0 -pg 1 -lvl 1 -x 100 -y 10 -defaultsOSRD 13 | preplace netloc Add_half_0_sum 1 1 1 N 0 14 | preplace netloc Add_half_0_c_out 1 1 1 N 20 15 | preplace netloc SW0_1 1 0 1 N 0 16 | preplace netloc SW1_1 1 0 1 N 20 17 | levelinfo -pg 1 -10 100 220 18 | pagesize -pg 1 -db -bbox -sgen -90 -110 310 140 19 | " 20 | } 21 | 22 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 |
20 | 21 | 22 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64:E:/Vivado/2022.2/bin 15 | else 16 | PATH=E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64:E:/Vivado/2022.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='E:/Projects/Tutorial/Tutorial.runs/synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log Add_half.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Add_half.tcl 44 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64:E:/Vivado/2022.2/bin 15 | else 16 | PATH=E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64:E:/Vivado/2022.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='E:/Projects/Tutorial/Tutorial.runs/impl_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | # pre-commands: 44 | /bin/touch .write_bitstream.begin.rst 45 | EAStep vivado -log Add_half.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Add_half.tcl -notrace 46 | 47 | 48 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64;E:/Vivado/2022.2/bin;"; 12 | } else { 13 | PathVal = "E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64;E:/Vivado/2022.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log Add_half.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Add_half.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64;E:/Vivado/2022.2/bin;"; 12 | } else { 13 | PathVal = "E:/Vivado/2022.2/ids_lite/ISE/bin/nt64;E:/Vivado/2022.2/ids_lite/ISE/lib/nt64;E:/Vivado/2022.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | // pre-commands: 26 | ISETouchFile( "write_bitstream", "begin" ); 27 | ISEStep( "vivado", 28 | "-log Add_half.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Add_half.tcl -notrace" ); 29 | 30 | 31 | 32 | 33 | 34 | function EAInclude( EAInclFilename ) { 35 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 36 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 37 | var EAIFContents = EAInclFile.ReadAll(); 38 | EAInclFile.Close(); 39 | return EAIFContents; 40 | } 41 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_methodology_drc_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:18 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_methodology -file Add_half_methodology_drc_routed.rpt -pb Add_half_methodology_drc_routed.pb -rpx Add_half_methodology_drc_routed.rpx 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Speed File : -1 10 | | Design State : Fully Routed 11 | -------------------------------------------------------------------------------------------------------------------------------------------------------------- 12 | 13 | Report Methodology 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. REPORT SUMMARY 18 | 2. REPORT DETAILS 19 | 20 | 1. REPORT SUMMARY 21 | ----------------- 22 | Netlist: netlist 23 | Floorplan: design_1 24 | Design limits: 25 | Max violations: 26 | Violations found: 0 27 | +------+----------+-------------+------------+ 28 | | Rule | Severity | Description | Violations | 29 | +------+----------+-------------+------------+ 30 | +------+----------+-------------+------------+ 31 | 32 | 2. REPORT DETAILS 33 | ----------------- 34 | 35 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_drc_opted.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:29:48 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_drc -file Add_half_drc_opted.rpt -pb Add_half_drc_opted.pb -rpx Add_half_drc_opted.rpx 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Speed File : -1 10 | | Design State : Synthesized 11 | --------------------------------------------------------------------------------------------------------------- 12 | 13 | Report DRC 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. REPORT SUMMARY 18 | 2. REPORT DETAILS 19 | 20 | 1. REPORT SUMMARY 21 | ----------------- 22 | Netlist: netlist 23 | Floorplan: design_1 24 | Design limits: 25 | Ruledeck: default 26 | Max violations: 27 | Violations found: 1 28 | +--------+----------+--------------------+------------+ 29 | | Rule | Severity | Description | Violations | 30 | +--------+----------+--------------------+------------+ 31 | | ZPS7-1 | Warning | PS7 block required | 1 | 32 | +--------+----------+--------------------+------------+ 33 | 34 | 2. REPORT DETAILS 35 | ----------------- 36 | ZPS7-1#1 Warning 37 | PS7 block required 38 | The PS7 cell must be used in this Zynq design in order to enable correct default configuration. 39 | Related violations: 40 | 41 | 42 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_drc_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------------------------------------ 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:18 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_drc -file Add_half_drc_routed.rpt -pb Add_half_drc_routed.pb -rpx Add_half_drc_routed.rpx 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Speed File : -1 10 | | Design State : Fully Routed 11 | ------------------------------------------------------------------------------------------------------------------ 12 | 13 | Report DRC 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. REPORT SUMMARY 18 | 2. REPORT DETAILS 19 | 20 | 1. REPORT SUMMARY 21 | ----------------- 22 | Netlist: netlist 23 | Floorplan: design_1 24 | Design limits: 25 | Ruledeck: default 26 | Max violations: 27 | Violations found: 1 28 | +--------+----------+--------------------+------------+ 29 | | Rule | Severity | Description | Violations | 30 | +--------+----------+--------------------+------------+ 31 | | ZPS7-1 | Warning | PS7 block required | 1 | 32 | +--------+----------+--------------------+------------+ 33 | 34 | 2. REPORT DETAILS 35 | ----------------- 36 | ZPS7-1#1 Warning 37 | PS7 block required 38 | The PS7 cell must be used in this Zynq design in order to enable correct default configuration. 39 | Related violations: 40 | 41 | 42 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.srcs/sources_1/bd/half_adder/half_adder.bd: -------------------------------------------------------------------------------- 1 | { 2 | "design": { 3 | "design_info": { 4 | "boundary_crc": "0x0", 5 | "device": "xc7z020clg400-1", 6 | "gen_directory": "../../../../Tutorial.gen/sources_1/bd/half_adder", 7 | "name": "half_adder", 8 | "rev_ctrl_bd_flag": "RevCtrlBdOff", 9 | "synth_flow_mode": "Hierarchical", 10 | "tool_version": "2022.2" 11 | }, 12 | "design_tree": { 13 | "Add_half_0": "" 14 | }, 15 | "ports": { 16 | "LED0": { 17 | "direction": "O" 18 | }, 19 | "LED1": { 20 | "direction": "O" 21 | }, 22 | "SW0": { 23 | "direction": "I" 24 | }, 25 | "SW1": { 26 | "direction": "I" 27 | } 28 | }, 29 | "components": { 30 | "Add_half_0": { 31 | "vlnv": "xilinx.com:module_ref:Add_half:1.0", 32 | "xci_name": "half_adder_Add_half_0_0", 33 | "xci_path": "ip\\half_adder_Add_half_0_0\\half_adder_Add_half_0_0.xci", 34 | "inst_hier_path": "Add_half_0", 35 | "reference_info": { 36 | "ref_type": "hdl", 37 | "ref_name": "Add_half", 38 | "boundary_crc": "0x0" 39 | }, 40 | "ports": { 41 | "sum": { 42 | "direction": "O" 43 | }, 44 | "c_out": { 45 | "direction": "O" 46 | }, 47 | "a": { 48 | "direction": "I" 49 | }, 50 | "b": { 51 | "direction": "I" 52 | } 53 | } 54 | } 55 | }, 56 | "nets": { 57 | "Add_half_0_c_out": { 58 | "ports": [ 59 | "Add_half_0/c_out", 60 | "LED1" 61 | ] 62 | }, 63 | "Add_half_0_sum": { 64 | "ports": [ 65 | "Add_half_0/sum", 66 | "LED0" 67 | ] 68 | }, 69 | "SW0_1": { 70 | "ports": [ 71 | "SW0", 72 | "Add_half_0/a" 73 | ] 74 | }, 75 | "SW1_1": { 76 | "ports": [ 77 | "SW1", 78 | "Add_half_0/b" 79 | ] 80 | } 81 | } 82 | } 83 | } -------------------------------------------------------------------------------- /Tutorial/Tutorial.srcs/sources_1/bd/half_adder/ip/half_adder_Add_half_0_0/half_adder_Add_half_0_0.xci: -------------------------------------------------------------------------------- 1 | { 2 | "schema": "xilinx.com:schema:json_instance:1.0", 3 | "ip_inst": { 4 | "xci_name": "half_adder_Add_half_0_0", 5 | "cell_name": "Add_half_0", 6 | "component_reference": "xilinx.com:module_ref:Add_half:1.0", 7 | "ip_revision": "1", 8 | "gen_directory": "../../../../../../Tutorial.gen/sources_1/bd/half_adder/ip/half_adder_Add_half_0_0", 9 | "parameters": { 10 | "component_parameters": { 11 | "Component_Name": [ { "value": "half_adder_Add_half_0_0", "resolve_type": "user", "usage": "all" } ] 12 | }, 13 | "project_parameters": { 14 | "ARCHITECTURE": [ { "value": "zynq" } ], 15 | "BASE_BOARD_PART": [ { "value": "tul.com.tw:pynq-z2:part0:1.0" } ], 16 | "BOARD_CONNECTIONS": [ { "value": "" } ], 17 | "DEVICE": [ { "value": "xc7z020" } ], 18 | "PACKAGE": [ { "value": "clg400" } ], 19 | "PREFHDL": [ { "value": "VERILOG" } ], 20 | "SILICON_REVISION": [ { "value": "" } ], 21 | "SIMULATOR_LANGUAGE": [ { "value": "VERILOG" } ], 22 | "SPEEDGRADE": [ { "value": "-1" } ], 23 | "STATIC_POWER": [ { "value": "" } ], 24 | "TEMPERATURE_GRADE": [ { "value": "" } ], 25 | "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], 26 | "USE_RDI_GENERATION": [ { "value": "TRUE" } ] 27 | }, 28 | "runtime_parameters": { 29 | "IPCONTEXT": [ { "value": "IP_Integrator" } ], 30 | "IPREVISION": [ { "value": "1" } ], 31 | "MANAGED": [ { "value": "TRUE" } ], 32 | "OUTPUTDIR": [ { "value": "../../../../../../Tutorial.gen/sources_1/bd/half_adder/ip/half_adder_Add_half_0_0" } ], 33 | "SELECTEDSIMMODEL": [ { "value": "" } ], 34 | "SHAREDDIR": [ { "value": "../../ipshared" } ], 35 | "SWVERSION": [ { "value": "2022.2" } ], 36 | "SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ] 37 | } 38 | }, 39 | "boundary": { 40 | "ports": { 41 | "sum": [ { "direction": "out" } ], 42 | "c_out": [ { "direction": "out" } ], 43 | "a": [ { "direction": "in" } ], 44 | "b": [ { "direction": "in" } ] 45 | } 46 | } 47 | } 48 | } -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | cmd_exists() 10 | { 11 | command -v "$1" >/dev/null 2>&1 12 | } 13 | 14 | HD_LOG=$1 15 | shift 16 | 17 | # CHECK for a STOP FILE 18 | if [ -f .stop.rst ] 19 | then 20 | echo "" >> $HD_LOG 21 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 22 | echo "" >> $HD_LOG 23 | exit 1 24 | fi 25 | 26 | ISE_STEP=$1 27 | shift 28 | 29 | # WRITE STEP HEADER to LOG 30 | echo "" >> $HD_LOG 31 | echo "*** Running $ISE_STEP" >> $HD_LOG 32 | echo " with args $@" >> $HD_LOG 33 | echo "" >> $HD_LOG 34 | 35 | # LAUNCH! 36 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 37 | 38 | # BEGIN file creation 39 | ISE_PID=$! 40 | 41 | HostNameFile=/proc/sys/kernel/hostname 42 | if cmd_exists hostname 43 | then 44 | ISE_HOST=$(hostname) 45 | elif cmd_exists uname 46 | then 47 | ISE_HOST=$(uname -n) 48 | elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 49 | then 50 | ISE_HOST=$(cat $HostNameFile) 51 | elif [ X != X$HOSTNAME ] 52 | then 53 | ISE_HOST=$HOSTNAME #bash 54 | else 55 | ISE_HOST=$HOST #csh 56 | fi 57 | 58 | ISE_USER=$USER 59 | 60 | ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) 61 | ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) 62 | 63 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 64 | /bin/touch $ISE_BEGINFILE 65 | echo "" >> $ISE_BEGINFILE 66 | echo "" >> $ISE_BEGINFILE 67 | echo " " >> $ISE_BEGINFILE 68 | echo " " >> $ISE_BEGINFILE 69 | echo "" >> $ISE_BEGINFILE 70 | 71 | # WAIT for ISEStep to finish 72 | wait $ISE_PID 73 | 74 | # END/ERROR file creation 75 | RETVAL=$? 76 | if [ $RETVAL -eq 0 ] 77 | then 78 | /bin/touch .$ISE_STEP.end.rst 79 | else 80 | /bin/touch .$ISE_STEP.error.rst 81 | fi 82 | 83 | exit $RETVAL 84 | 85 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | cmd_exists() 10 | { 11 | command -v "$1" >/dev/null 2>&1 12 | } 13 | 14 | HD_LOG=$1 15 | shift 16 | 17 | # CHECK for a STOP FILE 18 | if [ -f .stop.rst ] 19 | then 20 | echo "" >> $HD_LOG 21 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 22 | echo "" >> $HD_LOG 23 | exit 1 24 | fi 25 | 26 | ISE_STEP=$1 27 | shift 28 | 29 | # WRITE STEP HEADER to LOG 30 | echo "" >> $HD_LOG 31 | echo "*** Running $ISE_STEP" >> $HD_LOG 32 | echo " with args $@" >> $HD_LOG 33 | echo "" >> $HD_LOG 34 | 35 | # LAUNCH! 36 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 37 | 38 | # BEGIN file creation 39 | ISE_PID=$! 40 | 41 | HostNameFile=/proc/sys/kernel/hostname 42 | if cmd_exists hostname 43 | then 44 | ISE_HOST=$(hostname) 45 | elif cmd_exists uname 46 | then 47 | ISE_HOST=$(uname -n) 48 | elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 49 | then 50 | ISE_HOST=$(cat $HostNameFile) 51 | elif [ X != X$HOSTNAME ] 52 | then 53 | ISE_HOST=$HOSTNAME #bash 54 | else 55 | ISE_HOST=$HOST #csh 56 | fi 57 | 58 | ISE_USER=$USER 59 | 60 | ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) 61 | ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) 62 | 63 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 64 | /bin/touch $ISE_BEGINFILE 65 | echo "" >> $ISE_BEGINFILE 66 | echo "" >> $ISE_BEGINFILE 67 | echo " " >> $ISE_BEGINFILE 68 | echo " " >> $ISE_BEGINFILE 69 | echo "" >> $ISE_BEGINFILE 70 | 71 | # WAIT for ISEStep to finish 72 | wait $ISE_PID 73 | 74 | # END/ERROR file creation 75 | RETVAL=$? 76 | if [ $RETVAL -eq 0 ] 77 | then 78 | /bin/touch .$ISE_STEP.end.rst 79 | else 80 | /bin/touch .$ISE_STEP.error.rst 81 | fi 82 | 83 | exit $RETVAL 84 | 85 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.gen/sources_1/bd/half_adder/half_adder.bda: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 2 27 | half_adder 28 | VR 29 | 30 | 31 | half_adder 32 | BC 33 | 34 | 35 | active 36 | 2 37 | PM 38 | 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.srcs/sources_1/bd/half_adder/half_adder.bda: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 2 27 | half_adder 28 | VR 29 | 30 | 31 | half_adder 32 | BC 33 | 34 | 35 | active 36 | 2 37 | PM 38 | 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.gen/sources_1/bd/half_adder/ip/half_adder_Add_half_0_0/half_adder_Add_half_0_0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | customized_ip 5 | half_adder_Add_half_0_0 6 | 1.0 7 | 8 | 9 | 10 | sum 11 | 12 | out 13 | 14 | 15 | std_logic 16 | dummy_view 17 | 18 | 19 | 20 | 21 | 22 | c_out 23 | 24 | out 25 | 26 | 27 | std_logic 28 | dummy_view 29 | 30 | 31 | 32 | 33 | 34 | a 35 | 36 | in 37 | 38 | 39 | std_logic 40 | dummy_view 41 | 42 | 43 | 44 | 45 | 46 | b 47 | 48 | in 49 | 50 | 51 | std_logic 52 | dummy_view 53 | 54 | 55 | 56 | 57 | 58 | 59 | xilinx.com:module_ref:Add_half:1.0 60 | 61 | 62 | Component_Name 63 | half_adder_Add_half_0_0 64 | 65 | 66 | 67 | 68 | Add_half_v1_0 69 | module_ref 70 | 1 71 | 72 | 73 | 2022.2 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:566572696c6f67:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 17 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 18 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 19 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 20 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 21 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 22 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 23 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 24 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 25 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 26 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 27 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 28 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 29 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 30 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3837623333616430663030373461646262666231336536393763616334656663:506172656e742050412070726f6a656374204944:00 31 | eof:680842915 32 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:566572696c6f67:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 17 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 18 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 19 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 20 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 21 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 22 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 23 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 24 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 25 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 26 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 27 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 28 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 29 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 30 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3837623333616430663030373461646262666231336536393763616334656663:506172656e742050412070726f6a656374204944:00 31 | eof:680842915 32 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_control_sets_placed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:29:50 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_control_sets -verbose -file Add_half_control_sets_placed.rpt 7 | | Design : Add_half 8 | | Device : xc7z020 9 | ------------------------------------------------------------------------------------- 10 | 11 | Control Set Information 12 | 13 | Table of Contents 14 | ----------------- 15 | 1. Summary 16 | 2. Histogram 17 | 3. Flip-Flop Distribution 18 | 4. Detailed Control Set Information 19 | 20 | 1. Summary 21 | ---------- 22 | 23 | +----------------------------------------------------------+-------+ 24 | | Status | Count | 25 | +----------------------------------------------------------+-------+ 26 | | Total control sets | 0 | 27 | | Minimum number of control sets | 0 | 28 | | Addition due to synthesis replication | 0 | 29 | | Addition due to physical synthesis replication | 0 | 30 | | Unused register locations in slices containing registers | 0 | 31 | +----------------------------------------------------------+-------+ 32 | * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers 33 | ** Run report_qor_suggestions for automated merging and remapping suggestions 34 | 35 | 36 | 2. Histogram 37 | ------------ 38 | 39 | +--------------------+-------+ 40 | | Fanout | Count | 41 | +--------------------+-------+ 42 | | Total control sets | 0 | 43 | | >= 0 to < 4 | 0 | 44 | | >= 4 to < 6 | 0 | 45 | | >= 6 to < 8 | 0 | 46 | | >= 8 to < 10 | 0 | 47 | | >= 10 to < 12 | 0 | 48 | | >= 12 to < 14 | 0 | 49 | | >= 14 to < 16 | 0 | 50 | | >= 16 | 0 | 51 | +--------------------+-------+ 52 | * Control sets can be remapped at either synth_design or opt_design 53 | 54 | 55 | 3. Flip-Flop Distribution 56 | ------------------------- 57 | 58 | +--------------+-----------------------+------------------------+-----------------+--------------+ 59 | | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | 60 | +--------------+-----------------------+------------------------+-----------------+--------------+ 61 | | No | No | No | 0 | 0 | 62 | | No | No | Yes | 0 | 0 | 63 | | No | Yes | No | 0 | 0 | 64 | | Yes | No | No | 0 | 0 | 65 | | Yes | No | Yes | 0 | 0 | 66 | | Yes | Yes | No | 0 | 0 | 67 | +--------------+-----------------------+------------------------+-----------------+--------------+ 68 | 69 | 70 | 4. Detailed Control Set Information 71 | ----------------------------------- 72 | 73 | +--------------+---------------+------------------+------------------+----------------+--------------+ 74 | | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | 75 | +--------------+---------------+------------------+------------------+----------------+--------------+ 76 | 77 | 78 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Report generation script generated by Vivado 3 | # 4 | 5 | proc create_report { reportName command } { 6 | set status "." 7 | append status $reportName ".fail" 8 | if { [file exists $status] } { 9 | eval file delete [glob $status] 10 | } 11 | send_msg_id runtcl-4 info "Executing : $command" 12 | set retval [eval catch { $command } msg] 13 | if { $retval != 0 } { 14 | set fp [open $status w] 15 | close $fp 16 | send_msg_id runtcl-5 warning "$msg" 17 | } 18 | } 19 | namespace eval ::optrace { 20 | variable script "E:/Projects/Tutorial/Tutorial.runs/impl_1/Add_half.tcl" 21 | variable category "vivado_impl" 22 | } 23 | 24 | # Try to connect to running dispatch if we haven't done so already. 25 | # This code assumes that the Tcl interpreter is not using threads, 26 | # since the ::dispatch::connected variable isn't mutex protected. 27 | if {![info exists ::dispatch::connected]} { 28 | namespace eval ::dispatch { 29 | variable connected false 30 | if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { 31 | set result "true" 32 | if {[catch { 33 | if {[lsearch -exact [package names] DispatchTcl] < 0} { 34 | set result [load librdi_cd_clienttcl[info sharedlibextension]] 35 | } 36 | if {$result eq "false"} { 37 | puts "WARNING: Could not load dispatch client library" 38 | } 39 | set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] 40 | if { $connect_id eq "" } { 41 | puts "WARNING: Could not initialize dispatch client" 42 | } else { 43 | puts "INFO: Dispatch client connection id - $connect_id" 44 | set connected true 45 | } 46 | } catch_res]} { 47 | puts "WARNING: failed to connect to dispatch server - $catch_res" 48 | } 49 | } 50 | } 51 | } 52 | if {$::dispatch::connected} { 53 | # Remove the dummy proc if it exists. 54 | if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { 55 | rename ::OPTRACE "" 56 | } 57 | proc ::OPTRACE { task action {tags {} } } { 58 | ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category 59 | } 60 | # dispatch is generic. We specifically want to attach logging. 61 | ::vitis_log::connect_client 62 | } else { 63 | # Add dummy proc if it doesn't exist. 64 | if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { 65 | proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { 66 | # Do nothing 67 | } 68 | } 69 | } 70 | 71 | proc start_step { step } { 72 | set stopFile ".stop.rst" 73 | if {[file isfile .stop.rst]} { 74 | puts "" 75 | puts "*** Halting run - EA reset detected ***" 76 | puts "" 77 | puts "" 78 | return -code error 79 | } 80 | set beginFile ".$step.begin.rst" 81 | set platform "$::tcl_platform(platform)" 82 | set user "$::tcl_platform(user)" 83 | set pid [pid] 84 | set host "" 85 | if { [string equal $platform unix] } { 86 | if { [info exist ::env(HOSTNAME)] } { 87 | set host $::env(HOSTNAME) 88 | } elseif { [info exist ::env(HOST)] } { 89 | set host $::env(HOST) 90 | } 91 | } else { 92 | if { [info exist ::env(COMPUTERNAME)] } { 93 | set host $::env(COMPUTERNAME) 94 | } 95 | } 96 | set ch [open $beginFile w] 97 | puts $ch "" 98 | puts $ch "" 99 | puts $ch " " 100 | puts $ch " " 101 | puts $ch "" 102 | close $ch 103 | } 104 | 105 | proc end_step { step } { 106 | set endFile ".$step.end.rst" 107 | set ch [open $endFile w] 108 | close $ch 109 | } 110 | 111 | proc step_failed { step } { 112 | set endFile ".$step.error.rst" 113 | set ch [open $endFile w] 114 | close $ch 115 | OPTRACE "impl_1" END { } 116 | } 117 | 118 | 119 | OPTRACE "impl_1" START { ROLLUP_1 } 120 | OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO } 121 | OPTRACE "write_bitstream setup" START { } 122 | start_step write_bitstream 123 | set ACTIVE_STEP write_bitstream 124 | set rc [catch { 125 | create_msg_db write_bitstream.pb 126 | set_param chipscope.maxJobs 4 127 | open_checkpoint Add_half_routed.dcp 128 | set_property webtalk.parent_dir E:/Projects/Tutorial/Tutorial.cache/wt [current_project] 129 | set_property TOP Add_half [current_fileset] 130 | OPTRACE "read constraints: write_bitstream" START { } 131 | OPTRACE "read constraints: write_bitstream" END { } 132 | catch { write_mem_info -force -no_partial_mmi Add_half.mmi } 133 | OPTRACE "write_bitstream setup" END { } 134 | OPTRACE "write_bitstream" START { } 135 | write_bitstream -force Add_half.bit 136 | OPTRACE "write_bitstream" END { } 137 | OPTRACE "write_bitstream misc" START { } 138 | OPTRACE "read constraints: write_bitstream_post" START { } 139 | OPTRACE "read constraints: write_bitstream_post" END { } 140 | catch {write_debug_probes -quiet -force Add_half} 141 | catch {file copy -force Add_half.ltx debug_nets.ltx} 142 | close_msg_db -file write_bitstream.pb 143 | } RESULT] 144 | if {$rc} { 145 | step_failed write_bitstream 146 | return -code error $RESULT 147 | } else { 148 | end_step write_bitstream 149 | unset ACTIVE_STEP 150 | } 151 | 152 | OPTRACE "write_bitstream misc" END { } 153 | OPTRACE "Phase: Write Bitstream" END { } 154 | OPTRACE "impl_1" END { } 155 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/Add_half.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Synthesis run script generated by Vivado 3 | # 4 | 5 | set TIME_start [clock seconds] 6 | namespace eval ::optrace { 7 | variable script "E:/Projects/Tutorial/Tutorial.runs/synth_1/Add_half.tcl" 8 | variable category "vivado_synth" 9 | } 10 | 11 | # Try to connect to running dispatch if we haven't done so already. 12 | # This code assumes that the Tcl interpreter is not using threads, 13 | # since the ::dispatch::connected variable isn't mutex protected. 14 | if {![info exists ::dispatch::connected]} { 15 | namespace eval ::dispatch { 16 | variable connected false 17 | if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { 18 | set result "true" 19 | if {[catch { 20 | if {[lsearch -exact [package names] DispatchTcl] < 0} { 21 | set result [load librdi_cd_clienttcl[info sharedlibextension]] 22 | } 23 | if {$result eq "false"} { 24 | puts "WARNING: Could not load dispatch client library" 25 | } 26 | set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] 27 | if { $connect_id eq "" } { 28 | puts "WARNING: Could not initialize dispatch client" 29 | } else { 30 | puts "INFO: Dispatch client connection id - $connect_id" 31 | set connected true 32 | } 33 | } catch_res]} { 34 | puts "WARNING: failed to connect to dispatch server - $catch_res" 35 | } 36 | } 37 | } 38 | } 39 | if {$::dispatch::connected} { 40 | # Remove the dummy proc if it exists. 41 | if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { 42 | rename ::OPTRACE "" 43 | } 44 | proc ::OPTRACE { task action {tags {} } } { 45 | ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category 46 | } 47 | # dispatch is generic. We specifically want to attach logging. 48 | ::vitis_log::connect_client 49 | } else { 50 | # Add dummy proc if it doesn't exist. 51 | if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { 52 | proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { 53 | # Do nothing 54 | } 55 | } 56 | } 57 | 58 | proc create_report { reportName command } { 59 | set status "." 60 | append status $reportName ".fail" 61 | if { [file exists $status] } { 62 | eval file delete [glob $status] 63 | } 64 | send_msg_id runtcl-4 info "Executing : $command" 65 | set retval [eval catch { $command } msg] 66 | if { $retval != 0 } { 67 | set fp [open $status w] 68 | close $fp 69 | send_msg_id runtcl-5 warning "$msg" 70 | } 71 | } 72 | OPTRACE "synth_1" START { ROLLUP_AUTO } 73 | OPTRACE "Creating in-memory project" START { } 74 | create_project -in_memory -part xc7z020clg400-1 75 | 76 | set_param project.singleFileAddWarning.threshold 0 77 | set_param project.compositeFile.enableAutoGeneration 0 78 | set_param synth.vivado.isSynthRun true 79 | set_property webtalk.parent_dir E:/Projects/Tutorial/Tutorial.cache/wt [current_project] 80 | set_property parent.project_path E:/Projects/Tutorial/Tutorial.xpr [current_project] 81 | set_property default_lib xil_defaultlib [current_project] 82 | set_property target_language Verilog [current_project] 83 | set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project] 84 | set_property ip_output_repo e:/Projects/Tutorial/Tutorial.cache/ip [current_project] 85 | set_property ip_cache_permissions {read write} [current_project] 86 | OPTRACE "Creating in-memory project" END { } 87 | OPTRACE "Adding files" START { } 88 | read_verilog -library xil_defaultlib E:/Projects/Tutorial/Tutorial.srcs/sources_1/new/half_adder.v 89 | OPTRACE "Adding files" END { } 90 | # Mark all dcp files as not used in implementation to prevent them from being 91 | # stitched into the results of this synthesis run. Any black boxes in the 92 | # design are intentionally left as such for best results. Dcp files will be 93 | # stitched into the design at a later time, either when this synthesis run is 94 | # opened, or when it is stitched into a dependent implementation run. 95 | foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { 96 | set_property used_in_implementation false $dcp 97 | } 98 | read_xdc {{E:/Projects/Tutorial/Tutorial.srcs/constrs_1/imports/pynq-z2_v1.0.xdc/PYNQ-Z2 v1.0.xdc}} 99 | set_property used_in_implementation false [get_files {{E:/Projects/Tutorial/Tutorial.srcs/constrs_1/imports/pynq-z2_v1.0.xdc/PYNQ-Z2 v1.0.xdc}}] 100 | 101 | set_param ips.enableIPCacheLiteLoad 1 102 | 103 | read_checkpoint -auto_incremental -incremental E:/Projects/Tutorial/Tutorial.srcs/utils_1/imports/synth_1/Add_half.dcp 104 | close [open __synthesis_is_running__ w] 105 | 106 | OPTRACE "synth_design" START { } 107 | synth_design -top Add_half -part xc7z020clg400-1 108 | OPTRACE "synth_design" END { } 109 | if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { 110 | send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" 111 | } 112 | 113 | 114 | OPTRACE "write_checkpoint" START { CHECKPOINT } 115 | # disable binary constraint mode for synth run checkpoints 116 | set_param constraints.enableBinaryConstraints false 117 | write_checkpoint -force -noxdef Add_half.dcp 118 | OPTRACE "write_checkpoint" END { } 119 | OPTRACE "synth reports" START { REPORT } 120 | create_report "synth_1_synth_report_utilization_0" "report_utilization -file Add_half_utilization_synth.rpt -pb Add_half_utilization_synth.pb" 121 | OPTRACE "synth reports" END { } 122 | file delete __synthesis_is_running__ 123 | close [open __synthesis_is_complete__ w] 124 | OPTRACE "synth_1" END { } 125 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.gen/sources_1/bd/mref/Add_half/component.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | module_ref 5 | Add_half 6 | 1.0 7 | 8 | 9 | 10 | xilinx_anylanguagesynthesis 11 | Synthesis 12 | :vivado.xilinx.com:synthesis 13 | Verilog 14 | Add_half 15 | 16 | 17 | viewChecksum 18 | fc555e18 19 | 20 | 21 | 22 | 23 | xilinx_anylanguagebehavioralsimulation 24 | Simulation 25 | :vivado.xilinx.com:simulation 26 | Verilog 27 | Add_half 28 | 29 | 30 | viewChecksum 31 | fc555e18 32 | 33 | 34 | 35 | 36 | xilinx_xpgui 37 | UI Layout 38 | :vivado.xilinx.com:xgui.ui 39 | 40 | xilinx_xpgui_view_fileset 41 | 42 | 43 | 44 | 45 | 46 | sum 47 | 48 | out 49 | 50 | 51 | std_logic 52 | xilinx_anylanguagesynthesis 53 | xilinx_anylanguagebehavioralsimulation 54 | 55 | 56 | 57 | 58 | 59 | c_out 60 | 61 | out 62 | 63 | 64 | std_logic 65 | xilinx_anylanguagesynthesis 66 | xilinx_anylanguagebehavioralsimulation 67 | 68 | 69 | 70 | 71 | 72 | a 73 | 74 | in 75 | 76 | 77 | std_logic 78 | xilinx_anylanguagesynthesis 79 | xilinx_anylanguagebehavioralsimulation 80 | 81 | 82 | 83 | 84 | 85 | b 86 | 87 | in 88 | 89 | 90 | std_logic 91 | xilinx_anylanguagesynthesis 92 | xilinx_anylanguagebehavioralsimulation 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | xilinx_xpgui_view_fileset 102 | 103 | xgui/Add_half_v1_0.tcl 104 | tclSource 105 | CHECKSUM_f64a5dae 106 | XGUI_VERSION_2 107 | 108 | 109 | 110 | xilinx.com:module_ref:Add_half:1.0 111 | 112 | 113 | Component_Name 114 | Add_half_v1_0 115 | 116 | 117 | 118 | 119 | 120 | zynq 121 | 122 | 123 | /UserIP 124 | 125 | Add_half_v1_0 126 | level_1 127 | module_ref 128 | 129 | IPI 130 | 131 | 1 132 | 2023-02-17T15:48:50Z 133 | 134 | 135 | 2022.2 136 | 137 | 138 | 139 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.cache/wt/synthesis.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303230636c673430302d31:00:00 3 | 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-------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_clock_utilization_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | -------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:19 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_clock_utilization -file Add_half_clock_utilization_routed.rpt 7 | | Design : Add_half 8 | | Device : 7z020-clg400 9 | | Speed File : -1 PRODUCTION 1.12 2019-11-22 10 | | Design State : Routed 11 | -------------------------------------------------------------------------------------- 12 | 13 | Clock Utilization Report 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. Clock Primitive Utilization 18 | 2. Global Clock Resources 19 | 3. Global Clock Source Details 20 | 4. Clock Regions: Key Resource Utilization 21 | 5. Clock Regions : Global Clock Summary 22 | 23 | 1. Clock Primitive Utilization 24 | ------------------------------ 25 | 26 | +----------+------+-----------+-----+--------------+--------+ 27 | | Type | Used | Available | LOC | Clock Region | Pblock | 28 | +----------+------+-----------+-----+--------------+--------+ 29 | | BUFGCTRL | 0 | 32 | 0 | 0 | 0 | 30 | | BUFH | 0 | 72 | 0 | 0 | 0 | 31 | | BUFIO | 0 | 16 | 0 | 0 | 0 | 32 | | BUFMR | 0 | 8 | 0 | 0 | 0 | 33 | | BUFR | 0 | 16 | 0 | 0 | 0 | 34 | | MMCM | 0 | 4 | 0 | 0 | 0 | 35 | | PLL | 0 | 4 | 0 | 0 | 0 | 36 | +----------+------+-----------+-----+--------------+--------+ 37 | 38 | 39 | 2. Global Clock Resources 40 | ------------------------- 41 | 42 | +-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ 43 | | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | 44 | +-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ 45 | * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered 46 | ** Non-Clock Loads column represents cell count of non-clock pin loads 47 | 48 | 49 | 3. Global Clock Source Details 50 | ------------------------------ 51 | 52 | +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ 53 | | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | 54 | +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ 55 | * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered 56 | ** Non-Clock Loads column represents cell count of non-clock pin loads 57 | 58 | 59 | 4. Clock Regions: Key Resource Utilization 60 | ------------------------------------------ 61 | 62 | +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ 63 | | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | 64 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 65 | | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | 66 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 67 | | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | 68 | | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | 69 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | 70 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | 71 | | X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | 72 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | 73 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ 74 | * Global Clock column represents track count; while other columns represents cell counts 75 | 76 | 77 | 5. Clock Regions : Global Clock Summary 78 | --------------------------------------- 79 | 80 | All Modules 81 | +----+----+----+ 82 | | | X0 | X1 | 83 | +----+----+----+ 84 | | Y2 | 0 | 0 | 85 | | Y1 | 0 | 0 | 86 | | Y0 | 0 | 0 | 87 | +----+----+----+ 88 | 89 | 90 | 91 | # Location of IO Primitives which is load of clock spine 92 | 93 | # Location of clock ports 94 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 基于PYNQ Z2开发板与Vivado 2022.2的FPGA开发板使用教程 2 | 3 | ## 0. PYNQ Z2配置 4 | 5 | 见官方文档: https://pynq.readthedocs.io/en/latest/getting_started/pynq_z2_setup.html 6 | SD卡系统镜像文件在http://www.pynq.io/board.html下载, 使用Win32DiskImager烧录即可. 7 | 8 | ## 1. Vivado下载与安装 9 | 10 | **下载** 11 | 12 | 前往XILINX下载中心: https://www.xilinx.com/support/download.html 13 | 首先进行账户注册, 注册完成后选择"Xilinx Unified Installer 2022.2: Windows Self Extracting Web Installer (EXE - 209.61 MB)"下载. 14 | 下载时提示"U.S. Government Export Approval", 可以按照以下信息填写: 15 | Company Name: Massachusetts Institute of Technology 16 | Address 1: Massachusetts Institute of Technology 17 | Location: United States 18 | State/Province: Massachusetts 19 | City: Cambridge 20 | Postal Code: 02139 21 | 22 | 点击Download下载. 23 | 24 | **安装** 25 | 26 | 安装时按照默认配置即可. 在安装路径处选择安装文件夹. 注意安装时所需的磁盘空间至少120GB, 安装完毕后将占用磁盘100GB以上空间. 下载文件时会出现警告, 多次重试即可. 27 | 28 | ## 2. 配置开发板文件 29 | 30 | **配置文件** 31 | 前往PYNQ官网: https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html 32 | 选择PYNQ-Z2 Board File下载. 解压压缩包, 复制第二层pynq-z2文件夹. 33 | 打开Vivado所在路径, 进入Vivado\2022.2\data\boards文件夹. 新建board_files文件夹, 并将pynq-z2文件夹粘贴进去. 如图. 34 | 35 | ![1.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/1.jpg) 36 | 37 | **约束文件** 38 | 前往PYNQ教程网站: https://pynq.readthedocs.io/en/latest/overlay_design_methodology/board_settings.html 39 | 选择Download the Pynq-Z2 Master XDC constraints下载约束文件, 解压备用. 40 | 41 | ## 3. 新建项目 42 | 打开Vivado, 选择"Create Project", 输入项目名称与路径. 选中Create project subdirectory, 点击Next. 43 | 44 | ![2.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/2.jpg) 45 | 46 | 选择RTL Project, 点击Next. 47 | 48 | ![3.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/3.jpg) 49 | 50 | Target language与Simulator language均为Verilog, 点击Next. 51 | 52 | ![4.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/4.jpg) 53 | 54 | Add Constriants中选择左上角蓝色+, 点击Add files. 选择上一步下载的约束文件(后缀名为.xdc). 选中Copy constraints files into project, 点击Next. 55 | 56 | ![5.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/5.jpg) 57 | 58 | 选择Boards, 选择pynq-z2(如果上一步配置文件配置正确的话应该会出现), 点击Next. 59 | 60 | ![6.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/6.jpg) 61 | 62 | 点击Finish. 项目新建完成. 63 | 64 | ![7.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/7.jpg) 65 | 66 | ## 4. 新建IP(Intellectual Property) 67 | 68 | 点击左边栏IP INTEGRATOR-Create Block Design, 命名完毕后点击OK 69 | 70 | ![8.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/8.jpg) 71 | ![9.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/9.jpg) 72 | 73 | 进入Sources菜单, 右键Design Sources, 点击Add Sources. 74 | 75 | ![10.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/10.jpg) 76 | 77 | 选择Add or create design sources, 点击Next. 78 | 79 | ![11.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/11.jpg) 80 | 81 | 点击Create File, File type选择Verilog, 命名后点击OK. 82 | 83 | ![12.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/12.jpg) 84 | 85 | 点击Finish. 86 | 87 | ![13.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/13.jpg) 88 | 89 | 自动弹出引脚定义页面. 以半加法器为例, 拥有两个input(a, b)与两个output(sum, c_out). 点击OK. 90 | 91 | ![14.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/14.jpg) 92 | 93 | 进入half_adder.v, 粘贴以下代码并保存(Ctrl+S): 94 | 95 | ```Verilog 96 | module Add_half (sum, c_out, a, b); 97 | input a, b; 98 | output sum, c_out; 99 | wire c_out_bar; 100 | xor (sum, a, b); 101 | nand (c_out_bar, a, b); 102 | not (c_out, c_out_bar); 103 | endmodule 104 | ``` 105 | 106 | ![15.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/15.jpg) 107 | 108 | ## 5. 准备运行 109 | 110 | 进入Diagram菜单(或点击half_adder.bd), 将half_adder.v拖入框中. 111 | 112 | ![16.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/16.jpg) 113 | 114 | 右键一个引脚, 选择Create Port, 命名(建议命名为对应的外设名称)后点击OK. Ctrl+S保存. 115 | 116 | ![17.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/17.jpg) 117 | ![18.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/18.jpg) 118 | ![19.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/19.jpg) 119 | 120 | 点击左边栏Run Synthesis, 以默认配置运行. 121 | 122 | ![20.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/20.jpg) 123 | ![21.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/21.jpg) 124 | 125 | 可在Design Run中监测进度. 等待一段时间. 126 | 127 | ![22.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/22.jpg) 128 | 129 | 完成后弹出如下菜单, 选择Open Synthesis Design. 130 | 131 | ![23.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/23.jpg) 132 | 133 | 进入I/O Ports菜单, 根据User Manual第20页所示的引脚定义配置. 此处以input为两个开关, output为单色LED为例. 134 | I/O Std参考约束文件13,14,27,28行 135 | 136 | ```Verilog 137 | #set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=sw[0] 138 | #set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=sw[1] 139 | ... 140 | #set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=led[0] 141 | #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=led[1] 142 | ``` 143 | 144 | 修改为LVCMOS33. 145 | 146 | ![24.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/24.jpg) 147 | ![25.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/25.jpg) 148 | 149 | Ctrl+S保存, 弹出警告页面, 选择OK即可. 保存约束文件页面选择保存到之前的约束文件, 点击OK. 150 | 151 | ![26.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/26.jpg) 152 | 153 | 再次Run Synthesis, 完成后在弹出的页面选择Run Implementation, 默认配置, 点击OK. 完成后在弹出的页面选择Generate Bitstream, 默认配置. 完成后在弹出的页面选择Cancel. 154 | 155 | ![27.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/27.jpg) 156 | 157 | ## 6. 运行 158 | 将PYNQ-Z2通过Micro-USB连接到电脑并开启电源. 开机后在Vivado左侧边栏选择Open Hardware Manager. 点击Open Target-Auto Connect, 连接开发板. 159 | 160 | ![28.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/28.jpg) 161 | 162 | 点击左侧边栏Program Device, 选择XILINX芯片进行烧录. 默认配置. 点击Program. 163 | 164 | ![29.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/29.jpg) 165 | 166 | 烧录完成后程序自动运行. 167 | 168 | ## 7. 保存至SD卡并运行 169 | 170 | 上一步中通过Vivado进行烧录的方法并不能在开发板中永久保存你的代码. 下面的方法可以永久保存代码并运行代码. 171 | 172 | **连接网络** 173 | 174 | 将网线插入开发板与电脑(可以使用USB转RJ45转接线连接)并开机. 开机后在电脑控制面板-网络和 Internet-网络连接, 右键网口所在的网络适配器, 选择属性. 175 | 176 | ![30.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/30.jpg) 177 | 178 | 在IPv4中配置IP地址为192.168.2.x(x表示任选), 子网掩码为255.255.255.0, 点击确定. 179 | 180 | ![31.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/31.jpg) 181 | 182 | 打开电脑浏览器, 地址栏输入192.168.2.99:9090, 进入jupyter notebooks. 默认密码为xilinx 183 | 184 | ![32.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/32.jpg) 185 | 186 | 打开电脑文件资源管理器, 地址栏输入\\\pynq, 密码与用户名均为xilinx. 进入\xilinx\jupyter_notebooks并新建文件夹, 名称任意. 187 | 188 | ![33.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/33.jpg) 189 | 190 | **导入Bitstream** 191 | 192 | 进入Tutorial.runs\impl_1, 将.bit文件拷贝至上一步新建的文件夹中. 193 | 194 | ![34.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/34.jpg) 195 | 196 | 返回浏览器, 进入上一步新建的文件夹, 点击New-Python3, 复制下面的代码: 197 | 198 | ```Python 199 | from pynq import Bitstream 200 | 201 | bit = Bitstream("Add_half.bit") # No overlay Tcl file required 202 | 203 | bit.download() 204 | 205 | bit.bitfile_name 206 | ``` 207 | 208 | ![35.jpg](https://github.com/WangHaoZhe/PYNQ-Tutorial/blob/main/Resource/35.jpg) 209 | 210 | 其中Add_half.bit为你的Bitstream文件名. 保存, 点击运行, 等待开发板载入代码. 载入代码后jupyter notebooks进入不可用状态, 无法再进行控制. 若想停止代码运行并恢复jupyter notebooks, 点按开发板上的SRST并等待重启即可. 211 | 之后每次重新上电, 运行该notebook即可, 无需重新烧录代码. 212 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/Add_half_utilization_synth.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | ----------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:28:58 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_utilization -file Add_half_utilization_synth.rpt -pb Add_half_utilization_synth.pb 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Speed File : -1 10 | | Design State : Synthesized 11 | ----------------------------------------------------------------------------------------------------------- 12 | 13 | Utilization Design Information 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. Slice Logic 18 | 1.1 Summary of Registers by Type 19 | 2. Memory 20 | 3. DSP 21 | 4. IO and GT Specific 22 | 5. Clocking 23 | 6. Specific Feature 24 | 7. Primitives 25 | 8. Black Boxes 26 | 9. Instantiated Netlists 27 | 28 | 1. Slice Logic 29 | -------------- 30 | 31 | +-------------------------+------+-------+------------+-----------+-------+ 32 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 33 | +-------------------------+------+-------+------------+-----------+-------+ 34 | | Slice LUTs* | 1 | 0 | 0 | 53200 | <0.01 | 35 | | LUT as Logic | 1 | 0 | 0 | 53200 | <0.01 | 36 | | LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 | 37 | | Slice Registers | 0 | 0 | 0 | 106400 | 0.00 | 38 | | Register as Flip Flop | 0 | 0 | 0 | 106400 | 0.00 | 39 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | 40 | | F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 | 41 | | F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 | 42 | +-------------------------+------+-------+------------+-----------+-------+ 43 | * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 44 | Warning! LUT value is adjusted to account for LUT combining. 45 | 46 | 47 | 1.1 Summary of Registers by Type 48 | -------------------------------- 49 | 50 | +-------+--------------+-------------+--------------+ 51 | | Total | Clock Enable | Synchronous | Asynchronous | 52 | +-------+--------------+-------------+--------------+ 53 | | 0 | _ | - | - | 54 | | 0 | _ | - | Set | 55 | | 0 | _ | - | Reset | 56 | | 0 | _ | Set | - | 57 | | 0 | _ | Reset | - | 58 | | 0 | Yes | - | - | 59 | | 0 | Yes | - | Set | 60 | | 0 | Yes | - | Reset | 61 | | 0 | Yes | Set | - | 62 | | 0 | Yes | Reset | - | 63 | +-------+--------------+-------------+--------------+ 64 | 65 | 66 | 2. Memory 67 | --------- 68 | 69 | +----------------+------+-------+------------+-----------+-------+ 70 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 71 | +----------------+------+-------+------------+-----------+-------+ 72 | | Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 | 73 | | RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 | 74 | | RAMB18 | 0 | 0 | 0 | 280 | 0.00 | 75 | +----------------+------+-------+------------+-----------+-------+ 76 | * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 77 | 78 | 79 | 3. DSP 80 | ------ 81 | 82 | +-----------+------+-------+------------+-----------+-------+ 83 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 84 | +-----------+------+-------+------------+-----------+-------+ 85 | | DSPs | 0 | 0 | 0 | 220 | 0.00 | 86 | +-----------+------+-------+------------+-----------+-------+ 87 | 88 | 89 | 4. IO and GT Specific 90 | --------------------- 91 | 92 | +-----------------------------+------+-------+------------+-----------+-------+ 93 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 94 | +-----------------------------+------+-------+------------+-----------+-------+ 95 | | Bonded IOB | 4 | 0 | 0 | 125 | 3.20 | 96 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | 97 | | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | 98 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 | 99 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 | 100 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 | 101 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 | 102 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 | 103 | | IBUFDS | 0 | 0 | 0 | 121 | 0.00 | 104 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 | 105 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 | 106 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 | 107 | | ILOGIC | 0 | 0 | 0 | 125 | 0.00 | 108 | | OLOGIC | 0 | 0 | 0 | 125 | 0.00 | 109 | +-----------------------------+------+-------+------------+-----------+-------+ 110 | 111 | 112 | 5. Clocking 113 | ----------- 114 | 115 | +------------+------+-------+------------+-----------+-------+ 116 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 117 | +------------+------+-------+------------+-----------+-------+ 118 | | BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | 119 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 | 120 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 | 121 | | PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 | 122 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 | 123 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 | 124 | | BUFR | 0 | 0 | 0 | 16 | 0.00 | 125 | +------------+------+-------+------------+-----------+-------+ 126 | 127 | 128 | 6. Specific Feature 129 | ------------------- 130 | 131 | +-------------+------+-------+------------+-----------+-------+ 132 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 133 | +-------------+------+-------+------------+-----------+-------+ 134 | | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | 135 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | 136 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | 137 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | 138 | | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | 139 | | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | 140 | | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | 141 | | XADC | 0 | 0 | 0 | 1 | 0.00 | 142 | +-------------+------+-------+------------+-----------+-------+ 143 | 144 | 145 | 7. Primitives 146 | ------------- 147 | 148 | +----------+------+---------------------+ 149 | | Ref Name | Used | Functional Category | 150 | +----------+------+---------------------+ 151 | | OBUF | 2 | IO | 152 | | LUT2 | 2 | LUT | 153 | | IBUF | 2 | IO | 154 | +----------+------+---------------------+ 155 | 156 | 157 | 8. Black Boxes 158 | -------------- 159 | 160 | +----------+------+ 161 | | Ref Name | Used | 162 | +----------+------+ 163 | 164 | 165 | 9. Instantiated Netlists 166 | ------------------------ 167 | 168 | +----------+------+ 169 | | Ref Name | Used | 170 | +----------+------+ 171 | 172 | 173 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_power_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:19 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_power -file Add_half_power_routed.rpt -pb Add_half_power_summary_routed.pb -rpx Add_half_power_routed.rpx 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Design State : routed 10 | | Grade : commercial 11 | | Process : typical 12 | | Characterization : Production 13 | ---------------------------------------------------------------------------------------------------------------------------------------------- 14 | 15 | Power Report 16 | 17 | Table of Contents 18 | ----------------- 19 | 1. Summary 20 | 1.1 On-Chip Components 21 | 1.2 Power Supply Summary 22 | 1.3 Confidence Level 23 | 2. Settings 24 | 2.1 Environment 25 | 2.2 Clock Constraints 26 | 3. Detailed Reports 27 | 3.1 By Hierarchy 28 | 29 | 1. Summary 30 | ---------- 31 | 32 | +--------------------------+--------------+ 33 | | Total On-Chip Power (W) | 2.150 | 34 | | Design Power Budget (W) | Unspecified* | 35 | | Power Budget Margin (W) | NA | 36 | | Dynamic (W) | 2.000 | 37 | | Device Static (W) | 0.150 | 38 | | Effective TJA (C/W) | 11.5 | 39 | | Max Ambient (C) | 60.2 | 40 | | Junction Temperature (C) | 49.8 | 41 | | Confidence Level | Low | 42 | | Setting File | --- | 43 | | Simulation Activity File | --- | 44 | | Design Nets Matched | NA | 45 | +--------------------------+--------------+ 46 | * Specify Design Power Budget using, set_operating_conditions -design_power_budget 47 | 48 | 49 | 1.1 On-Chip Components 50 | ---------------------- 51 | 52 | +----------------+-----------+----------+-----------+-----------------+ 53 | | On-Chip | Power (W) | Used | Available | Utilization (%) | 54 | +----------------+-----------+----------+-----------+-----------------+ 55 | | Slice Logic | 0.005 | 2 | --- | --- | 56 | | LUT as Logic | 0.005 | 1 | 53200 | <0.01 | 57 | | Signals | 0.028 | 4 | --- | --- | 58 | | I/O | 1.966 | 4 | 125 | 3.20 | 59 | | Static Power | 0.150 | | | | 60 | | Total | 2.150 | | | | 61 | +----------------+-----------+----------+-----------+-----------------+ 62 | 63 | 64 | 1.2 Power Supply Summary 65 | ------------------------ 66 | 67 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 68 | | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | 69 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 70 | | Vccint | 1.000 | 0.060 | 0.041 | 0.018 | NA | Unspecified | NA | 71 | | Vccaux | 1.800 | 0.089 | 0.072 | 0.017 | NA | Unspecified | NA | 72 | | Vcco33 | 3.300 | 0.555 | 0.554 | 0.001 | NA | Unspecified | NA | 73 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 74 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 75 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 76 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 77 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 78 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 79 | | Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | 80 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 81 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 82 | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 83 | | Vccpint | 1.000 | 0.036 | 0.000 | 0.036 | NA | Unspecified | NA | 84 | | Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA | 85 | | Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA | 86 | | Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 87 | | Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 88 | | Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | 89 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | 90 | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ 91 | 92 | 93 | 1.3 Confidence Level 94 | -------------------- 95 | 96 | +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ 97 | | User Input Data | Confidence | Details | Action | 98 | +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ 99 | | Design implementation state | High | Design is routed | | 100 | | Clock nodes activity | High | User specified more than 95% of clocks | | 101 | | I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | 102 | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | 103 | | Device models | High | Device models are Production | | 104 | | | | | | 105 | | Overall confidence level | Low | | | 106 | +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ 107 | 108 | 109 | 2. Settings 110 | ----------- 111 | 112 | 2.1 Environment 113 | --------------- 114 | 115 | +-----------------------+------------------------+ 116 | | Ambient Temp (C) | 25.0 | 117 | | ThetaJA (C/W) | 11.5 | 118 | | Airflow (LFM) | 250 | 119 | | Heat Sink | none | 120 | | ThetaSA (C/W) | 0.0 | 121 | | Board Selection | medium (10"x10") | 122 | | # of Board Layers | 8to11 (8 to 11 Layers) | 123 | | Board Temperature (C) | 25.0 | 124 | +-----------------------+------------------------+ 125 | 126 | 127 | 2.2 Clock Constraints 128 | --------------------- 129 | 130 | +-------+--------+-----------------+ 131 | | Clock | Domain | Constraint (ns) | 132 | +-------+--------+-----------------+ 133 | 134 | 135 | 3. Detailed Reports 136 | ------------------- 137 | 138 | 3.1 By Hierarchy 139 | ---------------- 140 | 141 | +----------+-----------+ 142 | | Name | Power (W) | 143 | +----------+-----------+ 144 | | Add_half | 2.000 | 145 | +----------+-----------+ 146 | 147 | 148 | -------------------------------------------------------------------------------- /Document/PYNQ-Z2板卡文件/PYNQ-Z2 board file v1.0/A.0/part0_pins.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/ISEWrap.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | // GLOBAL VARIABLES 8 | var ISEShell = new ActiveXObject( "WScript.Shell" ); 9 | var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); 10 | var ISERunDir = ""; 11 | var ISELogFile = "runme.log"; 12 | var ISELogFileStr = null; 13 | var ISELogEcho = true; 14 | var ISEOldVersionWSH = false; 15 | 16 | 17 | 18 | // BOOTSTRAP 19 | ISEInit(); 20 | 21 | 22 | 23 | // 24 | // ISE FUNCTIONS 25 | // 26 | function ISEInit() { 27 | 28 | // 1. RUN DIR setup 29 | var ISEScrFP = WScript.ScriptFullName; 30 | var ISEScrN = WScript.ScriptName; 31 | ISERunDir = 32 | ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); 33 | 34 | // 2. LOG file setup 35 | ISELogFileStr = ISEOpenFile( ISELogFile ); 36 | 37 | // 3. LOG echo? 38 | var ISEScriptArgs = WScript.Arguments; 39 | for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; 106 | ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); 107 | ISELogFileStr = ISEOpenFile( ISELogFile ); 108 | 109 | } else { // WSH 5.6 110 | 111 | // LAUNCH! 112 | ISEShell.CurrentDirectory = ISERunDir; 113 | 114 | // Redirect STDERR to STDOUT 115 | ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; 116 | var ISEProcess = ISEShell.Exec( ISECmdLine ); 117 | 118 | // BEGIN file creation 119 | var wbemFlagReturnImmediately = 0x10; 120 | var wbemFlagForwardOnly = 0x20; 121 | var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); 122 | var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); 123 | var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); 124 | var NOC = 0; 125 | var NOLP = 0; 126 | var TPM = 0; 127 | var cpuInfos = new Enumerator(processor); 128 | for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { 129 | var cpuInfo = cpuInfos.item(); 130 | NOC += cpuInfo.NumberOfCores; 131 | NOLP += cpuInfo.NumberOfLogicalProcessors; 132 | } 133 | var csInfos = new Enumerator(computerSystem); 134 | for(;!csInfos.atEnd(); csInfos.moveNext()) { 135 | var csInfo = csInfos.item(); 136 | TPM += csInfo.TotalPhysicalMemory; 137 | } 138 | 139 | var ISEHOSTCORE = NOLP 140 | var ISEMEMTOTAL = TPM 141 | 142 | var ISENetwork = WScript.CreateObject( "WScript.Network" ); 143 | var ISEHost = ISENetwork.ComputerName; 144 | var ISEUser = ISENetwork.UserName; 145 | var ISEPid = ISEProcess.ProcessID; 146 | var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); 147 | ISEBeginFile.WriteLine( "" ); 148 | ISEBeginFile.WriteLine( "" ); 149 | ISEBeginFile.WriteLine( " " ); 156 | ISEBeginFile.WriteLine( " " ); 157 | ISEBeginFile.WriteLine( "" ); 158 | ISEBeginFile.Close(); 159 | 160 | var ISEOutStr = ISEProcess.StdOut; 161 | var ISEErrStr = ISEProcess.StdErr; 162 | 163 | // WAIT for ISEStep to finish 164 | while ( ISEProcess.Status == 0 ) { 165 | 166 | // dump stdout then stderr - feels a little arbitrary 167 | while ( !ISEOutStr.AtEndOfStream ) { 168 | ISEStdOut( ISEOutStr.ReadLine() ); 169 | } 170 | 171 | WScript.Sleep( 100 ); 172 | } 173 | 174 | ISEExitCode = ISEProcess.ExitCode; 175 | } 176 | 177 | ISELogFileStr.Close(); 178 | 179 | // END/ERROR file creation 180 | if ( ISEExitCode != 0 ) { 181 | ISETouchFile( ISEStep, "error" ); 182 | 183 | } else { 184 | ISETouchFile( ISEStep, "end" ); 185 | } 186 | 187 | return ISEExitCode; 188 | } 189 | 190 | 191 | // 192 | // UTILITIES 193 | // 194 | function ISEStdOut( ISELine ) { 195 | 196 | ISELogFileStr.WriteLine( ISELine ); 197 | 198 | if ( ISELogEcho ) { 199 | WScript.StdOut.WriteLine( ISELine ); 200 | } 201 | } 202 | 203 | function ISEStdErr( ISELine ) { 204 | 205 | ISELogFileStr.WriteLine( ISELine ); 206 | 207 | if ( ISELogEcho ) { 208 | WScript.StdErr.WriteLine( ISELine ); 209 | } 210 | } 211 | 212 | function ISETouchFile( ISERoot, ISEStatus ) { 213 | 214 | var ISETFile = 215 | ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); 216 | ISETFile.Close(); 217 | } 218 | 219 | function ISEOpenFile( ISEFilename ) { 220 | 221 | // This function has been updated to deal with a problem seen in CR #870871. 222 | // In that case the user runs a script that runs impl_1, and then turns around 223 | // and runs impl_1 -to_step write_bitstream. That second run takes place in 224 | // the same directory, which means we may hit some of the same files, and in 225 | // particular, we will open the runme.log file. Even though this script closes 226 | // the file (now), we see cases where a subsequent attempt to open the file 227 | // fails. Perhaps the OS is slow to release the lock, or the disk comes into 228 | // play? In any case, we try to work around this by first waiting if the file 229 | // is already there for an arbitrary 5 seconds. Then we use a try-catch block 230 | // and try to open the file 10 times with a one second delay after each attempt. 231 | // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. 232 | // If there is an unrecognized exception when trying to open the file, we output 233 | // an error message and write details to an exception.log file. 234 | var ISEFullPath = ISERunDir + "/" + ISEFilename; 235 | if (ISEFileSys.FileExists(ISEFullPath)) { 236 | // File is already there. This could be a problem. Wait in case it is still in use. 237 | WScript.Sleep(5000); 238 | } 239 | var i; 240 | for (i = 0; i < 10; ++i) { 241 | try { 242 | return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); 243 | } catch (exception) { 244 | var error_code = exception.number & 0xFFFF; // The other bits are a facility code. 245 | if (error_code == 52) { // 52 is bad file name or number. 246 | // Wait a second and try again. 247 | WScript.Sleep(1000); 248 | continue; 249 | } else { 250 | WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 251 | var exceptionFilePath = ISERunDir + "/exception.log"; 252 | if (!ISEFileSys.FileExists(exceptionFilePath)) { 253 | WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); 254 | var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); 255 | exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 256 | exceptionFile.WriteLine("\tException name: " + exception.name); 257 | exceptionFile.WriteLine("\tException error code: " + error_code); 258 | exceptionFile.WriteLine("\tException message: " + exception.message); 259 | exceptionFile.Close(); 260 | } 261 | throw exception; 262 | } 263 | } 264 | } 265 | // If we reached this point, we failed to open the file after 10 attempts. 266 | // We need to error out. 267 | WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); 268 | WScript.Quit(1); 269 | } 270 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/synth_1/ISEWrap.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | // GLOBAL VARIABLES 8 | var ISEShell = new ActiveXObject( "WScript.Shell" ); 9 | var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); 10 | var ISERunDir = ""; 11 | var ISELogFile = "runme.log"; 12 | var ISELogFileStr = null; 13 | var ISELogEcho = true; 14 | var ISEOldVersionWSH = false; 15 | 16 | 17 | 18 | // BOOTSTRAP 19 | ISEInit(); 20 | 21 | 22 | 23 | // 24 | // ISE FUNCTIONS 25 | // 26 | function ISEInit() { 27 | 28 | // 1. RUN DIR setup 29 | var ISEScrFP = WScript.ScriptFullName; 30 | var ISEScrN = WScript.ScriptName; 31 | ISERunDir = 32 | ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); 33 | 34 | // 2. LOG file setup 35 | ISELogFileStr = ISEOpenFile( ISELogFile ); 36 | 37 | // 3. LOG echo? 38 | var ISEScriptArgs = WScript.Arguments; 39 | for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; 106 | ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); 107 | ISELogFileStr = ISEOpenFile( ISELogFile ); 108 | 109 | } else { // WSH 5.6 110 | 111 | // LAUNCH! 112 | ISEShell.CurrentDirectory = ISERunDir; 113 | 114 | // Redirect STDERR to STDOUT 115 | ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; 116 | var ISEProcess = ISEShell.Exec( ISECmdLine ); 117 | 118 | // BEGIN file creation 119 | var wbemFlagReturnImmediately = 0x10; 120 | var wbemFlagForwardOnly = 0x20; 121 | var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); 122 | var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); 123 | var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); 124 | var NOC = 0; 125 | var NOLP = 0; 126 | var TPM = 0; 127 | var cpuInfos = new Enumerator(processor); 128 | for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { 129 | var cpuInfo = cpuInfos.item(); 130 | NOC += cpuInfo.NumberOfCores; 131 | NOLP += cpuInfo.NumberOfLogicalProcessors; 132 | } 133 | var csInfos = new Enumerator(computerSystem); 134 | for(;!csInfos.atEnd(); csInfos.moveNext()) { 135 | var csInfo = csInfos.item(); 136 | TPM += csInfo.TotalPhysicalMemory; 137 | } 138 | 139 | var ISEHOSTCORE = NOLP 140 | var ISEMEMTOTAL = TPM 141 | 142 | var ISENetwork = WScript.CreateObject( "WScript.Network" ); 143 | var ISEHost = ISENetwork.ComputerName; 144 | var ISEUser = ISENetwork.UserName; 145 | var ISEPid = ISEProcess.ProcessID; 146 | var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); 147 | ISEBeginFile.WriteLine( "" ); 148 | ISEBeginFile.WriteLine( "" ); 149 | ISEBeginFile.WriteLine( " " ); 156 | ISEBeginFile.WriteLine( " " ); 157 | ISEBeginFile.WriteLine( "" ); 158 | ISEBeginFile.Close(); 159 | 160 | var ISEOutStr = ISEProcess.StdOut; 161 | var ISEErrStr = ISEProcess.StdErr; 162 | 163 | // WAIT for ISEStep to finish 164 | while ( ISEProcess.Status == 0 ) { 165 | 166 | // dump stdout then stderr - feels a little arbitrary 167 | while ( !ISEOutStr.AtEndOfStream ) { 168 | ISEStdOut( ISEOutStr.ReadLine() ); 169 | } 170 | 171 | WScript.Sleep( 100 ); 172 | } 173 | 174 | ISEExitCode = ISEProcess.ExitCode; 175 | } 176 | 177 | ISELogFileStr.Close(); 178 | 179 | // END/ERROR file creation 180 | if ( ISEExitCode != 0 ) { 181 | ISETouchFile( ISEStep, "error" ); 182 | 183 | } else { 184 | ISETouchFile( ISEStep, "end" ); 185 | } 186 | 187 | return ISEExitCode; 188 | } 189 | 190 | 191 | // 192 | // UTILITIES 193 | // 194 | function ISEStdOut( ISELine ) { 195 | 196 | ISELogFileStr.WriteLine( ISELine ); 197 | 198 | if ( ISELogEcho ) { 199 | WScript.StdOut.WriteLine( ISELine ); 200 | } 201 | } 202 | 203 | function ISEStdErr( ISELine ) { 204 | 205 | ISELogFileStr.WriteLine( ISELine ); 206 | 207 | if ( ISELogEcho ) { 208 | WScript.StdErr.WriteLine( ISELine ); 209 | } 210 | } 211 | 212 | function ISETouchFile( ISERoot, ISEStatus ) { 213 | 214 | var ISETFile = 215 | ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); 216 | ISETFile.Close(); 217 | } 218 | 219 | function ISEOpenFile( ISEFilename ) { 220 | 221 | // This function has been updated to deal with a problem seen in CR #870871. 222 | // In that case the user runs a script that runs impl_1, and then turns around 223 | // and runs impl_1 -to_step write_bitstream. That second run takes place in 224 | // the same directory, which means we may hit some of the same files, and in 225 | // particular, we will open the runme.log file. Even though this script closes 226 | // the file (now), we see cases where a subsequent attempt to open the file 227 | // fails. Perhaps the OS is slow to release the lock, or the disk comes into 228 | // play? In any case, we try to work around this by first waiting if the file 229 | // is already there for an arbitrary 5 seconds. Then we use a try-catch block 230 | // and try to open the file 10 times with a one second delay after each attempt. 231 | // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. 232 | // If there is an unrecognized exception when trying to open the file, we output 233 | // an error message and write details to an exception.log file. 234 | var ISEFullPath = ISERunDir + "/" + ISEFilename; 235 | if (ISEFileSys.FileExists(ISEFullPath)) { 236 | // File is already there. This could be a problem. Wait in case it is still in use. 237 | WScript.Sleep(5000); 238 | } 239 | var i; 240 | for (i = 0; i < 10; ++i) { 241 | try { 242 | return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); 243 | } catch (exception) { 244 | var error_code = exception.number & 0xFFFF; // The other bits are a facility code. 245 | if (error_code == 52) { // 52 is bad file name or number. 246 | // Wait a second and try again. 247 | WScript.Sleep(1000); 248 | continue; 249 | } else { 250 | WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 251 | var exceptionFilePath = ISERunDir + "/exception.log"; 252 | if (!ISEFileSys.FileExists(exceptionFilePath)) { 253 | WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); 254 | var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); 255 | exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 256 | exceptionFile.WriteLine("\tException name: " + exception.name); 257 | exceptionFile.WriteLine("\tException error code: " + error_code); 258 | exceptionFile.WriteLine("\tException message: " + exception.message); 259 | exceptionFile.Close(); 260 | } 261 | throw exception; 262 | } 263 | } 264 | } 265 | // If we reached this point, we failed to open the file after 10 attempts. 266 | // We need to error out. 267 | WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); 268 | WScript.Quit(1); 269 | } 270 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_utilization_placed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:29:50 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_utilization -file Add_half_utilization_placed.rpt -pb Add_half_utilization_placed.pb 7 | | Design : Add_half 8 | | Device : xc7z020clg400-1 9 | | Speed File : -1 10 | | Design State : Fully Placed 11 | ------------------------------------------------------------------------------------------------------------- 12 | 13 | Utilization Design Information 14 | 15 | Table of Contents 16 | ----------------- 17 | 1. Slice Logic 18 | 1.1 Summary of Registers by Type 19 | 2. Slice Logic Distribution 20 | 3. Memory 21 | 4. DSP 22 | 5. IO and GT Specific 23 | 6. Clocking 24 | 7. Specific Feature 25 | 8. Primitives 26 | 9. Black Boxes 27 | 10. Instantiated Netlists 28 | 29 | 1. Slice Logic 30 | -------------- 31 | 32 | +-------------------------+------+-------+------------+-----------+-------+ 33 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 34 | +-------------------------+------+-------+------------+-----------+-------+ 35 | | Slice LUTs | 1 | 0 | 0 | 53200 | <0.01 | 36 | | LUT as Logic | 1 | 0 | 0 | 53200 | <0.01 | 37 | | LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 | 38 | | Slice Registers | 0 | 0 | 0 | 106400 | 0.00 | 39 | | Register as Flip Flop | 0 | 0 | 0 | 106400 | 0.00 | 40 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | 41 | | F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 | 42 | | F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 | 43 | +-------------------------+------+-------+------------+-----------+-------+ 44 | * Warning! LUT value is adjusted to account for LUT combining. 45 | 46 | 47 | 1.1 Summary of Registers by Type 48 | -------------------------------- 49 | 50 | +-------+--------------+-------------+--------------+ 51 | | Total | Clock Enable | Synchronous | Asynchronous | 52 | +-------+--------------+-------------+--------------+ 53 | | 0 | _ | - | - | 54 | | 0 | _ | - | Set | 55 | | 0 | _ | - | Reset | 56 | | 0 | _ | Set | - | 57 | | 0 | _ | Reset | - | 58 | | 0 | Yes | - | - | 59 | | 0 | Yes | - | Set | 60 | | 0 | Yes | - | Reset | 61 | | 0 | Yes | Set | - | 62 | | 0 | Yes | Reset | - | 63 | +-------+--------------+-------------+--------------+ 64 | 65 | 66 | 2. Slice Logic Distribution 67 | --------------------------- 68 | 69 | +------------------------------------------+------+-------+------------+-----------+-------+ 70 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 71 | +------------------------------------------+------+-------+------------+-----------+-------+ 72 | | Slice | 1 | 0 | 0 | 13300 | <0.01 | 73 | | SLICEL | 1 | 0 | | | | 74 | | SLICEM | 0 | 0 | | | | 75 | | LUT as Logic | 1 | 0 | 0 | 53200 | <0.01 | 76 | | using O5 output only | 0 | | | | | 77 | | using O6 output only | 0 | | | | | 78 | | using O5 and O6 | 1 | | | | | 79 | | LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 | 80 | | LUT as Distributed RAM | 0 | 0 | | | | 81 | | LUT as Shift Register | 0 | 0 | | | | 82 | | Slice Registers | 0 | 0 | 0 | 106400 | 0.00 | 83 | | Register driven from within the Slice | 0 | | | | | 84 | | Register driven from outside the Slice | 0 | | | | | 85 | | Unique Control Sets | 0 | | 0 | 13300 | 0.00 | 86 | +------------------------------------------+------+-------+------------+-----------+-------+ 87 | * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. 88 | 89 | 90 | 3. Memory 91 | --------- 92 | 93 | +----------------+------+-------+------------+-----------+-------+ 94 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 95 | +----------------+------+-------+------------+-----------+-------+ 96 | | Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 | 97 | | RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 | 98 | | RAMB18 | 0 | 0 | 0 | 280 | 0.00 | 99 | +----------------+------+-------+------------+-----------+-------+ 100 | * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 101 | 102 | 103 | 4. DSP 104 | ------ 105 | 106 | +-----------+------+-------+------------+-----------+-------+ 107 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 108 | +-----------+------+-------+------------+-----------+-------+ 109 | | DSPs | 0 | 0 | 0 | 220 | 0.00 | 110 | +-----------+------+-------+------------+-----------+-------+ 111 | 112 | 113 | 5. IO and GT Specific 114 | --------------------- 115 | 116 | +-----------------------------+------+-------+------------+-----------+-------+ 117 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 118 | +-----------------------------+------+-------+------------+-----------+-------+ 119 | | Bonded IOB | 4 | 4 | 0 | 125 | 3.20 | 120 | | IOB Master Pads | 2 | | | | | 121 | | IOB Slave Pads | 2 | | | | | 122 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | 123 | | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | 124 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 | 125 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 | 126 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 | 127 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 | 128 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 | 129 | | IBUFDS | 0 | 0 | 0 | 121 | 0.00 | 130 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 | 131 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 | 132 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 | 133 | | ILOGIC | 0 | 0 | 0 | 125 | 0.00 | 134 | | OLOGIC | 0 | 0 | 0 | 125 | 0.00 | 135 | +-----------------------------+------+-------+------------+-----------+-------+ 136 | 137 | 138 | 6. Clocking 139 | ----------- 140 | 141 | +------------+------+-------+------------+-----------+-------+ 142 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 143 | +------------+------+-------+------------+-----------+-------+ 144 | | BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | 145 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 | 146 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 | 147 | | PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 | 148 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 | 149 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 | 150 | | BUFR | 0 | 0 | 0 | 16 | 0.00 | 151 | +------------+------+-------+------------+-----------+-------+ 152 | 153 | 154 | 7. Specific Feature 155 | ------------------- 156 | 157 | +-------------+------+-------+------------+-----------+-------+ 158 | | Site Type | Used | Fixed | Prohibited | Available | Util% | 159 | +-------------+------+-------+------------+-----------+-------+ 160 | | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | 161 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | 162 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | 163 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | 164 | | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | 165 | | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | 166 | | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | 167 | | XADC | 0 | 0 | 0 | 1 | 0.00 | 168 | +-------------+------+-------+------------+-----------+-------+ 169 | 170 | 171 | 8. Primitives 172 | ------------- 173 | 174 | +----------+------+---------------------+ 175 | | Ref Name | Used | Functional Category | 176 | +----------+------+---------------------+ 177 | | OBUF | 2 | IO | 178 | | LUT2 | 2 | LUT | 179 | | IBUF | 2 | IO | 180 | +----------+------+---------------------+ 181 | 182 | 183 | 9. Black Boxes 184 | -------------- 185 | 186 | +----------+------+ 187 | | Ref Name | Used | 188 | +----------+------+ 189 | 190 | 191 | 10. Instantiated Netlists 192 | ------------------------- 193 | 194 | +----------+------+ 195 | | Ref Name | Used | 196 | +----------+------+ 197 | 198 | 199 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 130 | 131 | 132 | 133 | 134 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 162 | 163 | 164 | 165 | 166 | 169 | 170 | 172 | 173 | 175 | 176 | 178 | 179 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | default_dashboard 242 | 243 | 244 | 245 | -------------------------------------------------------------------------------- /Tutorial/Tutorial.runs/impl_1/Add_half_timing_summary_routed.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 2 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022 4 | | Date : Sat Feb 18 00:30:19 2023 5 | | Host : Albert-G14 running 64-bit major release (build 9200) 6 | | Command : report_timing_summary -max_paths 10 -report_unconstrained -file Add_half_timing_summary_routed.rpt -pb Add_half_timing_summary_routed.pb -rpx Add_half_timing_summary_routed.rpx -warn_on_violation 7 | | Design : Add_half 8 | | Device : 7z020-clg400 9 | | Speed File : -1 PRODUCTION 1.12 2019-11-22 10 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Timing Summary Report 13 | 14 | ------------------------------------------------------------------------------------------------ 15 | | Timer Settings 16 | | -------------- 17 | ------------------------------------------------------------------------------------------------ 18 | 19 | Enable Multi Corner Analysis : Yes 20 | Enable Pessimism Removal : Yes 21 | Pessimism Removal Resolution : Nearest Common Node 22 | Enable Input Delay Default Clock : No 23 | Enable Preset / Clear Arcs : No 24 | Disable Flight Delays : No 25 | Ignore I/O Paths : No 26 | Timing Early Launch at Borrowing Latches : No 27 | Borrow Time for Max Delay Exceptions : Yes 28 | Merge Timing Exceptions : Yes 29 | 30 | Corner Analyze Analyze 31 | Name Max Paths Min Paths 32 | ------ --------- --------- 33 | Slow Yes Yes 34 | Fast Yes Yes 35 | 36 | 37 | ------------------------------------------------------------------------------------------------ 38 | | Report Methodology 39 | | ------------------ 40 | ------------------------------------------------------------------------------------------------ 41 | 42 | No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. 43 | 44 | 45 | 46 | check_timing report 47 | 48 | Table of Contents 49 | ----------------- 50 | 1. checking no_clock (0) 51 | 2. checking constant_clock (0) 52 | 3. checking pulse_width_clock (0) 53 | 4. checking unconstrained_internal_endpoints (0) 54 | 5. checking no_input_delay (0) 55 | 6. checking no_output_delay (0) 56 | 7. checking multiple_clock (0) 57 | 8. checking generated_clocks (0) 58 | 9. checking loops (0) 59 | 10. checking partial_input_delay (0) 60 | 11. checking partial_output_delay (0) 61 | 12. checking latch_loops (0) 62 | 63 | 1. checking no_clock (0) 64 | ------------------------ 65 | There are 0 register/latch pins with no clock. 66 | 67 | 68 | 2. checking constant_clock (0) 69 | ------------------------------ 70 | There are 0 register/latch pins with constant_clock. 71 | 72 | 73 | 3. checking pulse_width_clock (0) 74 | --------------------------------- 75 | There are 0 register/latch pins which need pulse_width check 76 | 77 | 78 | 4. checking unconstrained_internal_endpoints (0) 79 | ------------------------------------------------ 80 | There are 0 pins that are not constrained for maximum delay. 81 | 82 | There are 0 pins that are not constrained for maximum delay due to constant clock. 83 | 84 | 85 | 5. checking no_input_delay (0) 86 | ------------------------------ 87 | There are 0 input ports with no input delay specified. 88 | 89 | There are 0 input ports with no input delay but user has a false path constraint. 90 | 91 | 92 | 6. checking no_output_delay (0) 93 | ------------------------------- 94 | There are 0 ports with no output delay specified. 95 | 96 | There are 0 ports with no output delay but user has a false path constraint 97 | 98 | There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 99 | 100 | 101 | 7. checking multiple_clock (0) 102 | ------------------------------ 103 | There are 0 register/latch pins with multiple clocks. 104 | 105 | 106 | 8. checking generated_clocks (0) 107 | -------------------------------- 108 | There are 0 generated clocks that are not connected to a clock source. 109 | 110 | 111 | 9. checking loops (0) 112 | --------------------- 113 | There are 0 combinational loops in the design. 114 | 115 | 116 | 10. checking partial_input_delay (0) 117 | ------------------------------------ 118 | There are 0 input ports with partial input delay specified. 119 | 120 | 121 | 11. checking partial_output_delay (0) 122 | ------------------------------------- 123 | There are 0 ports with partial output delay specified. 124 | 125 | 126 | 12. checking latch_loops (0) 127 | ---------------------------- 128 | There are 0 combinational latch loops in the design through latch input 129 | 130 | 131 | 132 | ------------------------------------------------------------------------------------------------ 133 | | Design Timing Summary 134 | | --------------------- 135 | ------------------------------------------------------------------------------------------------ 136 | 137 | WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints 138 | ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 139 | inf 0.000 0 2 inf 0.000 0 2 NA NA NA NA 140 | 141 | 142 | There are no user specified timing constraints. 143 | 144 | 145 | ------------------------------------------------------------------------------------------------ 146 | | Clock Summary 147 | | ------------- 148 | ------------------------------------------------------------------------------------------------ 149 | 150 | 151 | ------------------------------------------------------------------------------------------------ 152 | | Intra Clock Table 153 | | ----------------- 154 | ------------------------------------------------------------------------------------------------ 155 | 156 | Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints 157 | ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 158 | 159 | 160 | ------------------------------------------------------------------------------------------------ 161 | | Inter Clock Table 162 | | ----------------- 163 | ------------------------------------------------------------------------------------------------ 164 | 165 | From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints 166 | ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- 167 | 168 | 169 | ------------------------------------------------------------------------------------------------ 170 | | Other Path Groups Table 171 | | ----------------------- 172 | ------------------------------------------------------------------------------------------------ 173 | 174 | Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints 175 | ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- 176 | 177 | 178 | ------------------------------------------------------------------------------------------------ 179 | | User Ignored Path Table 180 | | ----------------------- 181 | ------------------------------------------------------------------------------------------------ 182 | 183 | Path Group From Clock To Clock 184 | ---------- ---------- -------- 185 | 186 | 187 | ------------------------------------------------------------------------------------------------ 188 | | Unconstrained Path Table 189 | | ------------------------ 190 | ------------------------------------------------------------------------------------------------ 191 | 192 | Path Group From Clock To Clock 193 | ---------- ---------- -------- 194 | (none) 195 | 196 | 197 | ------------------------------------------------------------------------------------------------ 198 | | Timing Details 199 | | -------------- 200 | ------------------------------------------------------------------------------------------------ 201 | 202 | 203 | -------------------------------------------------------------------------------------- 204 | Path Group: (none) 205 | From Clock: 206 | To Clock: 207 | 208 | Max Delay 2 Endpoints 209 | Min Delay 2 Endpoints 210 | -------------------------------------------------------------------------------------- 211 | 212 | 213 | Max Delay Paths 214 | -------------------------------------------------------------------------------------- 215 | Slack: inf 216 | Source: a 217 | (input port) 218 | Destination: c_out 219 | (output port) 220 | Path Group: (none) 221 | Path Type: Max at Slow Process Corner 222 | Data Path Delay: 10.146ns (logic 5.444ns (53.656%) route 4.702ns (46.344%)) 223 | Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1) 224 | 225 | Location Delay type Incr(ns) Path(ns) Netlist Resource(s) 226 | ------------------------------------------------------------------- ------------------- 227 | M19 0.000 0.000 r a (IN) 228 | net (fo=0) 0.000 0.000 a 229 | M19 IBUF (Prop_ibuf_I_O) 1.533 1.533 r a_IBUF_inst/O 230 | net (fo=2, routed) 1.366 2.898 a_IBUF 231 | SLICE_X113Y135 LUT2 (Prop_lut2_I0_O) 0.152 3.050 r c_out_OBUF_inst_i_1/O 232 | net (fo=1, routed) 3.336 6.387 c_out_OBUF 233 | P14 OBUF (Prop_obuf_I_O) 3.759 10.146 r c_out_OBUF_inst/O 234 | net (fo=0) 0.000 10.146 c_out 235 | P14 r c_out (OUT) 236 | ------------------------------------------------------------------- ------------------- 237 | 238 | Slack: inf 239 | Source: a 240 | (input port) 241 | Destination: sum 242 | (output port) 243 | Path Group: (none) 244 | Path Type: Max at Slow Process Corner 245 | Data Path Delay: 9.886ns (logic 5.186ns (52.462%) route 4.700ns (47.538%)) 246 | Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1) 247 | 248 | Location Delay type Incr(ns) Path(ns) Netlist Resource(s) 249 | ------------------------------------------------------------------- ------------------- 250 | M19 0.000 0.000 r a (IN) 251 | net (fo=0) 0.000 0.000 a 252 | M19 IBUF (Prop_ibuf_I_O) 1.533 1.533 r a_IBUF_inst/O 253 | net (fo=2, routed) 1.366 2.898 a_IBUF 254 | SLICE_X113Y135 LUT2 (Prop_lut2_I1_O) 0.124 3.022 r sum_OBUF_inst_i_1/O 255 | net (fo=1, routed) 3.334 6.356 sum_OBUF 256 | R14 OBUF (Prop_obuf_I_O) 3.530 9.886 r sum_OBUF_inst/O 257 | net (fo=0) 0.000 9.886 sum 258 | R14 r sum (OUT) 259 | ------------------------------------------------------------------- ------------------- 260 | 261 | 262 | 263 | 264 | 265 | Min Delay Paths 266 | -------------------------------------------------------------------------------------- 267 | Slack: inf 268 | Source: b 269 | (input port) 270 | Destination: sum 271 | (output port) 272 | Path Group: (none) 273 | Path Type: Min at Fast Process Corner 274 | Data Path Delay: 3.009ns (logic 1.585ns (52.679%) route 1.424ns (47.321%)) 275 | Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1) 276 | 277 | Location Delay type Incr(ns) Path(ns) Netlist Resource(s) 278 | ------------------------------------------------------------------- ------------------- 279 | M20 0.000 0.000 r b (IN) 280 | net (fo=0) 0.000 0.000 b 281 | M20 IBUF (Prop_ibuf_I_O) 0.309 0.309 r b_IBUF_inst/O 282 | net (fo=2, routed) 0.375 0.684 b_IBUF 283 | SLICE_X113Y135 LUT2 (Prop_lut2_I0_O) 0.045 0.729 r sum_OBUF_inst_i_1/O 284 | net (fo=1, routed) 1.049 1.778 sum_OBUF 285 | R14 OBUF (Prop_obuf_I_O) 1.231 3.009 r sum_OBUF_inst/O 286 | net (fo=0) 0.000 3.009 sum 287 | R14 r sum (OUT) 288 | ------------------------------------------------------------------- ------------------- 289 | 290 | Slack: inf 291 | Source: b 292 | (input port) 293 | Destination: c_out 294 | (output port) 295 | Path Group: (none) 296 | Path Type: Min at Fast Process Corner 297 | Data Path Delay: 3.111ns (logic 1.675ns (53.858%) route 1.435ns (46.142%)) 298 | Logic Levels: 3 (IBUF=1 LUT2=1 OBUF=1) 299 | 300 | Location Delay type Incr(ns) Path(ns) Netlist Resource(s) 301 | ------------------------------------------------------------------- ------------------- 302 | M20 0.000 0.000 r b (IN) 303 | net (fo=0) 0.000 0.000 b 304 | M20 IBUF (Prop_ibuf_I_O) 0.309 0.309 r b_IBUF_inst/O 305 | net (fo=2, routed) 0.375 0.684 b_IBUF 306 | SLICE_X113Y135 LUT2 (Prop_lut2_I1_O) 0.046 0.730 r c_out_OBUF_inst_i_1/O 307 | net (fo=1, routed) 1.060 1.791 c_out_OBUF 308 | P14 OBUF (Prop_obuf_I_O) 1.320 3.111 r c_out_OBUF_inst/O 309 | net (fo=0) 0.000 3.111 c_out 310 | P14 r c_out (OUT) 311 | ------------------------------------------------------------------- ------------------- 312 | 313 | 314 | 315 | 316 | 317 | --------------------------------------------------------------------------------