├── .gitattributes ├── .gitignore ├── AHB2BRAM └── AHB2BRAM.v ├── AHB_GPIO ├── cmsdk_ahb_gpio.v ├── cmsdk_ahb_to_iop.v └── cmsdk_iop_gpio.v ├── AHB_UART ├── AHBUART.v ├── baudgen.v ├── fifo.v ├── uart_rx.v └── uart_tx.v ├── AXI_DMA_RD_1.0 ├── bd │ └── bd.tcl ├── component.xml ├── example_designs │ ├── bfm_design │ │ ├── AXI_DMA_RD_v1_0_tb.v │ │ └── design.tcl │ └── debug_hw_design │ │ ├── AXI_DMA_RD_v1_0_hw_test.tcl │ │ └── design.tcl ├── hdl │ ├── AXI_DMA_RD_v1_0.v │ ├── AXI_DMA_RD_v1_0_M00_AXI.v │ └── VGA_TIMING.v ├── src │ └── frame_fifo_64x4096 │ │ ├── blk_mem_gen_v8_3_1 │ │ └── hdl │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── doc │ │ └── fifo_generator_v13_0_changelog.txt │ │ ├── fifo_generator_v13_0_1 │ │ ├── hdl │ │ │ ├── fifo_generator_v13_0.vhd │ │ │ ├── fifo_generator_v13_0_rfs.vhd │ │ │ └── fifo_generator_v13_0_vhsyn_rfs.vhd │ │ └── simulation │ │ │ └── fifo_generator_vhdl_beh.vhd │ │ ├── frame_fifo_64x4096.veo │ │ ├── frame_fifo_64x4096.vho │ │ ├── frame_fifo_64x4096.xci │ │ ├── frame_fifo_64x4096.xml │ │ ├── frame_fifo_64x4096 │ │ ├── frame_fifo_64x4096.xdc │ │ └── frame_fifo_64x4096_clocks.xdc │ │ ├── sim │ │ └── frame_fifo_64x4096.vhd │ │ └── synth │ │ └── frame_fifo_64x4096.vhd ├── xgui │ └── AXI_DMA_RD_v1_0.tcl └── xilinx.com_user_AXI_DMA_RD_1.0.zip ├── AXI_DMA_WR_1.0 ├── bd │ └── bd.tcl ├── component.xml ├── example_designs │ ├── bfm_design │ │ ├── AXI_DMA_WR_v1_0_tb.v │ │ └── design.tcl │ └── debug_hw_design │ │ ├── AXI_DMA_WR_v1_0_hw_test.tcl │ │ └── design.tcl ├── hdl │ ├── AXI_DMA_WR_v1_0.v │ └── AXI_DMA_WR_v1_0_M00_AXI.v ├── src │ ├── fifo_generator_0 │ │ ├── blk_mem_gen_v8_3_1 │ │ │ └── hdl │ │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── doc │ │ │ └── fifo_generator_v13_0_changelog.txt │ │ ├── fifo_generator_0.veo │ │ ├── fifo_generator_0.vho │ │ ├── fifo_generator_0.xci │ │ ├── fifo_generator_0.xml │ │ ├── fifo_generator_0 │ │ │ ├── fifo_generator_0.xdc │ │ │ └── fifo_generator_0_clocks.xdc │ │ ├── fifo_generator_v13_0_1 │ │ │ ├── hdl │ │ │ │ ├── fifo_generator_v13_0.vhd │ │ │ │ ├── fifo_generator_v13_0_rfs.vhd │ │ │ │ └── fifo_generator_v13_0_vhsyn_rfs.vhd │ │ │ └── simulation │ │ │ │ └── fifo_generator_vhdl_beh.vhd │ │ ├── sim │ │ │ └── fifo_generator_0.vhd │ │ └── synth │ │ │ └── fifo_generator_0.vhd │ └── frame_buf_32x8192 │ │ ├── blk_mem_gen_v8_3_1 │ │ └── hdl │ │ │ ├── blk_mem_gen_v8_3.vhd │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd │ │ ├── doc │ │ └── fifo_generator_v13_0_changelog.txt │ │ ├── fifo_generator_v13_0_1 │ │ ├── hdl │ │ │ ├── fifo_generator_v13_0.vhd │ │ │ ├── fifo_generator_v13_0_rfs.vhd │ │ │ └── fifo_generator_v13_0_vhsyn_rfs.vhd │ │ └── simulation │ │ │ └── fifo_generator_vhdl_beh.vhd │ │ ├── frame_buf_32x8192.veo │ │ ├── frame_buf_32x8192.vho │ │ ├── frame_buf_32x8192.xci │ │ ├── frame_buf_32x8192.xml │ │ ├── frame_buf_32x8192 │ │ ├── frame_buf_32x8192.xdc │ │ └── frame_buf_32x8192_clocks.xdc │ │ ├── sim │ │ └── frame_buf_32x8192.vhd │ │ └── synth │ │ └── frame_buf_32x8192.vhd ├── xgui │ └── AXI_DMA_WR_v1_0.tcl └── xilinx.com_user_AXI_DMA_WR_1.0.zip ├── AXI_lite_test_hdl ├── AXI_Test_M.v ├── AXI_Test_M_v1_0_M00_AXI.v ├── AXI_Test_S.v ├── AXI_Test_S_v1_0_S00_AXI.v ├── AXI_Test_top.v └── AXI_Test_top_testbench.v ├── BMP_FAT ├── bmp_img.c └── bmp_img.h ├── BRAM ├── BRAM.v ├── BRAM_inst.v └── initial_data.hex ├── DE1_SOC_SEG_HEX ├── DE1_SOC.sdc ├── DE1_SOC_HEX.qpf ├── DE1_SOC_HEX.qsf ├── DE1_SOC_HEX.tcl ├── README.md ├── hdl │ ├── DE1_SOC_HEX.v │ └── SEG_HEX.v ├── output_files │ └── DE1_SOC_HEX.sof └── 文件列表.txt ├── Edge_Detect ├── Edge_Detect.vt └── sim │ └── Edge_Detect.v ├── Fudan_uart ├── uart_rx.v ├── uart_top.v ├── uart_top_inst.v └── uart_tx.v ├── Key_Module ├── Key_Module.v ├── key_Module_inst.v └── 说明.txt ├── README.md ├── RGB_Gary_Binary └── RGB_Gary_Binary.v ├── SEG_display ├── seg_display.v ├── seg_test.v ├── 数码管原理图.bmp └── 说明.txt ├── UART_Module ├── UART_TOP.v ├── baudgen.v ├── fifo.v ├── uart_rx.v └── uart_tx.v ├── aq_axi_master ├── .gitignore ├── aq_axi_master.v ├── axi_slave_v1_0_S00_AXI.v ├── mem_test.v └── top.v ├── async_fifo-master ├── .gitignore ├── LICENSE ├── README.md ├── async_fifo.core ├── doc │ ├── architecture.rst │ ├── release.rst │ ├── specification.rst │ └── testplan.rst ├── sim │ └── test │ │ ├── Makefile │ │ ├── async_fifo_unit_test.sv │ │ ├── files.f │ │ └── wave.gtkw └── src │ ├── .gitignore │ ├── async_fifo.qpf │ ├── async_fifo.qsf │ └── vlog │ ├── async_bidir_fifo.v │ ├── async_bidir_ramif_fifo.v │ ├── async_fifo.v │ ├── fifo_2mem.v │ ├── fifomem_dp.v │ ├── rptr_empty.v │ ├── sync_ptr.v │ ├── sync_r2w.v │ ├── sync_w2r.v │ └── wptr_full.v ├── axi_full_sim ├── .gitignore ├── axi_full_top.v ├── axi_master_1.0 │ ├── bd │ │ └── bd.tcl │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── design.tcl │ │ │ └── myip_v1_0_tb.sv │ │ └── debug_hw_design │ │ │ ├── design.tcl │ │ │ └── myip_v1_0_hw_test.tcl │ ├── hdl │ │ ├── axi_master_v1_0.v │ │ └── axi_master_v1_0_M00_AXI.v │ └── xgui │ │ └── myip_v1_0.tcl ├── axi_master_v1_0_M00_AXI.v ├── axi_slave_1.0 │ ├── bd │ │ └── bd.tcl │ ├── drivers │ │ └── axi_slave_v1_0 │ │ │ ├── data │ │ │ ├── axi_slave.mdd │ │ │ └── axi_slave.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── axi_slave.c │ │ │ ├── axi_slave.h │ │ │ └── axi_slave_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── axi_slave_v1_0_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── axi_slave_v1_0_hw_test.tcl │ │ │ └── design.tcl │ ├── hdl │ │ ├── axi_slave_v1_0.v │ │ └── axi_slave_v1_0_S00_AXI.v │ └── xgui │ │ └── axi_slave_v1_0.tcl ├── axi_slave_v1_0_S00_AXI.v └── tb_axi_full_top.v ├── fifo └── fifo.v ├── hdmi_tx_1.0 ├── hdl │ ├── DVITransmitter.vhd │ ├── SerializerN_1.vhd │ ├── TMDSEncoder.vhd │ └── hdmi_tx.vhd ├── hdmi_tx_0 │ └── hdmi_tx_0.xci └── xgui │ ├── AXI_DisplayController_v1_0_v1_0.tcl │ └── hdmi_tx_v1_0.tcl ├── i2c_master ├── .gitignore ├── i2c_config.v ├── i2c_master │ ├── i2c_master_bit_ctrl.v │ ├── i2c_master_byte_ctrl.v │ ├── i2c_master_defines.v │ ├── i2c_master_top.v │ └── timescale.v ├── lut_ov5640_rgb565_480_272.v ├── ov5640_config_top.qpf ├── ov5640_config_top.qsf └── ov5640_config_top.v ├── pwm └── PWM_ip.v ├── pwm_motor ├── PWM_ip.v ├── Segled_Module.v ├── pwm_control.v ├── sim │ └── top.vt ├── speed_display.v ├── top.v └── 工程说明.docx ├── ram_2p └── ram_2p.v ├── sdram_core └── sdram_core.v ├── uart_module ├── uart_inst.v └── urat_test │ ├── data_16bit_to_8bit.v │ ├── data_to_8bit.v │ ├── top.v │ ├── uart_test_data.v │ └── 说明.txt ├── vivado-library-master.zip ├── wave_data ├── sin_1024_14bit_signd.hex ├── sin_16bit_1024_signed.hex ├── sin_16bit_32768_signed.hex └── sin_8bit_1024_unsigne.hex └── white_balance └── white_balance.v /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WayneGong/Verilog_Module/HEAD/.gitattributes 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