├── Change_History ├── HDLGen.bin ├── HDLGen.pl ├── README.md ├── doc ├── AutoDef_Sample.PNG ├── AutoInstSig_Sample.PNG ├── AutoWarning_Sample.PNG ├── Design_Template_Sample.PNG ├── HDLGen_Intro_En.pdf ├── IPXACT_Sample.PNG ├── Instance_Sample.PNG ├── JSON_Sample.PNG └── WorkingFlow.PNG ├── plugins ├── AsyncIntfGen.pm ├── ClkGen.pm ├── Design_Template │ ├── AsyncFifo.tmpl.v │ ├── AsyncIntf.tmpl.v │ ├── Clk.tmpl.v │ ├── Fuse.tmpl.v │ ├── Mem.tmpl.v │ ├── Pmu.tmpl.v │ ├── Rst.tmpl.v │ └── SyncFifo.tmpl.v ├── FifoGen.pm ├── FuseGen.pm ├── HDLGen.pm ├── HDLGenIpxIntf.pm ├── MemGen.pm ├── PmuGen.pm ├── RstGen.pm ├── eFunc.pm └── eFuncPrint.pm ├── setenv.sh └── test ├── NV_NVDLA_CMAC_CORE_mac.v.Ref ├── NV_NVDLA_CMAC_CORE_mac.vp ├── cfg ├── AFifo_Cfg.json ├── APB.xml ├── AsyncIntf_Cfg.json ├── Clk_Cfg.json ├── Fuse_Cfg.json ├── Mem_Cfg.json ├── MyIntf.json ├── Pmu_Cfg.json ├── Regs.json ├── Rst_Cfg.json ├── SFifo_Cfg.json ├── my_test_design.JSON └── simple_spi.xml ├── incr ├── NV_NVDLA_CMAC_CORE_MAC_exp.v ├── NV_NVDLA_CMAC_CORE_MAC_mul.v ├── NV_NVDLA_CMAC_CORE_MAC_nan.v ├── apb_test.v └── test_sys_ctrl_apb_regs.v ├── src.list └── test_DAC.v /Change_History: -------------------------------------------------------------------------------- 1 | 2 | 2023/10/31 V1.18 Wilson Chen fix a bug for IPXACT interface port parser 3 | 4 | 2023/05/05 V1.17 Wilson Chen add interface signals filter for &Connect from a new issue 5 | 6 | 2023/03/12 V1.16 Wilson Chen add floating port support as a new issue 7 | 8 | 2023/03/10 V1.15 Wilson Chen change source file to be ".vp" 9 | change temp file to $mod_name.vpp 10 | add `ifdef support on port connection from a new issue 11 | 12 | 2023/02/10 V1.13 Wilson Chen fix bug of `define handler & print 13 | 14 | 2023/02/08 V1.12 Wilson Chen fix Instance Connect 'bxx 'hxx bug 15 | add missed test_DAC.v 16 | 17 | 2023/02/07 V1.11 Wilson Chen fix Verilog ports parser, support & test more strange style 18 | fix instance ports printing bugs for specail cases 19 | 20 | 2023/02/05 V1.10 Wilson Chen Decide to use JSON file as Hierarchy Integration solution, but NOT IPXACT! 21 | Add TransIPX to translate IPXACT to JSON for easy understanding 22 | Add GenModJson to export Modules' name & interfaces & ports to JSON file 23 | Update Instance function to instance from JSON file with interfaces & ports 24 | Change HDLGenIpxIntf.pm to real package 25 | 26 | 2023/01/26 V1.05 Wilson Chen Add functions to export Interfaces & Ports for Hierarchy Integration 27 | need to update: export Interfaces & Ports to IPXACT file 28 | 29 | 2023/01/08 V1.02 Wilson Chen fix an auto signal width-learning bug 30 | add missed AsyncIntfGen.pm 31 | update license date 32 | 33 | 2022/12/25 V1.01 Wilson Chen Add AddParam function from an open request 34 | 35 | 2022/12/12 V1.00 Wilson Chen fix some typo & format 36 | Beta release 37 | 38 | 2022/11/30 V0.99 Wilson Chen support inhouse function module generation: 39 | use JSON file for paramaters 40 | use ePerl Template file for custom design 41 | 42 | 2022/11/26 V0.94 Wilson Chen fix AutoWarning function 43 | support PARAMETER & DEFINE on auto signal declare 44 | sig declare will change to final value but not PARAM/DEFINE name 45 | 46 | 2022/11/18 V0.93 Wilson Chen fix LHS multi-signal: handle {wire0,wire1...} = {sig0[...], sig1[...] ...} 47 | 48 | 2022/11/14 V0.92 Wilson Chen update AutoInstSigs to do width-learning from all Instance & Assignments 49 | need to update: handle assign LHS multi-signal (FIXME) 50 | 51 | 2022/11/12 V0.91 Wilson Chen add AutoWarning feature, but not perfect yet (FIXME) 52 | 53 | 2022/11/10 V0.90 Wilson Chen add Instance inputs & outputs no connection warnings 54 | 55 | 2022/11/08 V0.86 Wilson Chen use Verilog::Netlist to handle Assignments 56 | change "AutoInstWire" to "AutoInstSig" as "reg" is possible for Instance's port connection 57 | "reg" is not perfect but should work in most case 58 | 59 | 2022/10/14 V0.85 Wilson Chen add ShowIntf & ShowIPX function 60 | 61 | 2022/10/11 V0.84 Wilson Chen fix Instance bug(return) 62 | update colorful information print 63 | 64 | 2022/10/10 V0.83 Wilson Chen update Instance to support IPXACT 65 | update Instance for multi-parameter support 66 | fix Instance function bug($C_done)£» 67 | 68 | 2022/10/08 V0.82 Wilson Chen change ExptIPX function name (remove IPX) 69 | add RmIntfPort function & usage 70 | add CallCmd function & usage 71 | add 3 DTI(Data Transfer Interface) function & usage 72 | fix Connect bug($n) 73 | 74 | 2022/9/30 V0.81 Wilson Chen fix a few bugs 75 | change from temp file to mem array for internal database 76 | 77 | 2022/6/01 V0.8 Wilson Chen bugs & typo cleaning 78 | Alpha release 79 | 80 | 2022/5/20 V0.7 Wilson Chen support SV/RTL/HASH interface customize 81 | 82 | 2022/4/30 V0.6 Wilson Chen support IPXACT & XML interface & port 83 | 84 | 2022/4/22 V0.5 Wilson Chen support Interface Connect 85 | 86 | 2022/4/18 V0.4 Wilson Chen support AMBA Interface 87 | 88 | 2022/4/16 V0.3 Wilson Chen initial function done(SRC & Instance & Connect) 89 | 90 | 2022/4/10 V0.2 Wilson Chen enable embedded Perl & Python 91 | 92 | 2022/4/05 V0.1 Wilson Chen project initial 93 | -------------------------------------------------------------------------------- /HDLGen.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/HDLGen.bin -------------------------------------------------------------------------------- /HDLGen.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | #============================================================================================================# 4 | #============================================================================================================# 5 | #========================================= Public Packages ==================================================# 6 | #============================================================================================================# 7 | #============================================================================================================# 8 | use strict; 9 | use File::Basename; 10 | use Getopt::Long qw(GetOptions); 11 | use Cwd qw/abs_path/; 12 | use Term::ANSIColor qw(:constants); 13 | $Term::ANSIColor::AUTORESET = 1; 14 | #============================================================================================================# 15 | #========================================= End of Public Packages ===========================================# 16 | #============================================================================================================# 17 | 18 | ### Add Script Dir as include paths, most for all PlugIn APIs ### 19 | use lib abs_path(dirname(__FILE__)) . '/plugins'; 20 | 21 | our $HDLGEN_ROOT = $ENV{"HDLGEN_ROOT"}; 22 | if ($HDLGEN_ROOT eq "") { 23 | print STDOUT BOLD RED " !!! ERROR !!! : HDLGEN_ROOT is not defined!\n\n"; 24 | exit(1); 25 | } 26 | 27 | #============================================================================================================# 28 | #========================= Inhouse Packages for internal developed functions ================================# 29 | #============================================================================================================# 30 | #require "HDLGen.pm"; 31 | use HDLGen; 32 | #============================================================================================================# 33 | #================================ End of Inhouse Packages ===================================================# 34 | #============================================================================================================# 35 | 36 | our($input_src, $output_vlg, $input_flist,$verbose, $debug, $clean, $usage) = ("", "", "", "", "", "", ""); 37 | GetOptions( 38 | 'verbose' => \$verbose, 39 | 'input=s' => \$input_src, 40 | 'output=s' => \$output_vlg, 41 | 'f=s' => \$input_flist, 42 | 'debug' => \$debug, 43 | 'clean' => \$clean, 44 | 'usage' => \$usage, 45 | ); 46 | 47 | if ($verbose ) { 48 | print("--- Verbose Debug Infomation is turned on ---\n"); 49 | } 50 | 51 | our $HDLGEN_DEBUG_MODE = 0; 52 | $HDLGEN_DEBUG_MODE = "1" if ($verbose && $debug); 53 | 54 | 55 | if ($debug ne "") { 56 | system("rm -r .eperl.pl") if (-e ".eperl.pl"); 57 | system("rm -r .epython.py") if (-e ".epython.py"); 58 | } 59 | 60 | #============================================================================================================# 61 | #============================================================================================================# 62 | #============================================================================================================# 63 | #=========================================== Main Function ==================================================# 64 | #============================================================================================================# 65 | #============================================================================================================# 66 | #============================================================================================================# 67 | # 68 | 69 | if ($usage) { 70 | &Usage(); 71 | } elsif ($input_flist eq "") { 72 | if ( $input_src eq "" ) { 73 | &Usage(); 74 | } else { 75 | &HDLGen::ProcessOneFile($input_src, $output_vlg); 76 | } 77 | } else { 78 | open(LIST_IN, "<$input_flist") or die "!!! Error: can't find input list file of ($input_flist) \n\n"; 79 | while () { 80 | chomp(); 81 | &HDLGen::ProcessOneFile($input_src, ""); 82 | } 83 | } 84 | 85 | 86 | sub Version { 87 | print BOLD BLUE < $0 -i HDL_Design.src 109 | --> $0 -i HDL_Design.src -o HDL_Design_NewName.v ( default is HDL_Design.v ) 110 | --> $0 -i HDL_Design.src -d ( run with debug option ) 111 | EOF 112 | 113 | RESET; 114 | print < 126 | EOF 127 | 128 | RESET; 129 | print YELLOW < <= dd'h/b... 134 | or: reg_sig <= dd{1'x... 135 | or: reg_sig <= left_sig[q:p] 136 | EOF 137 | RESET; 138 | print < 5 |   It supports all syntax and data structure of Perl or Python, and has a few predefined functions for signal define, module instance, port connection etc.
6 |   This tool also supports extended API functions in Perl style, for any function or module that you want or have from previous knowledge or project.
7 |   HDL and script mixed design file can be any name, while final generated RTL file will be Verilog only( as .v).
8 |   This tool can achieve all functions of EMACS veirlog-mode，while support more as emdedded regular-express, IPXACT/XML,Interface,JSON,Hash，and the working mode is very similiar or even idential to HDL design, but not DSL or HLS.
9 | 10 |   **From function or working mode, this tool is much more efficient than commercial integration tools, with zero learning curve.**
11 | 12 | ## License 13 | Copyright 2022~2023 Wilson Chen 14 | Licensed under the Apache License, Version 2.0 (the "License"); 15 | You may not use this file except in compliance with the License. 16 | You may obtain a copy of the License at 17 | http://www.apache.org/licenses/LICENSE-2.0 18 | Unless required by applicable law or agreed to in writing, software 19 | distributed under the License is distributed on an "AS IS" BASIS, 20 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | See the License for the specific language governing permissions and 22 | limitations under the License. 23 | 24 | **************************************************************************************** 25 | ***any feedback, suggestion, requirement, solution, contribution, is always welcome*** 26 | **************************************************************************************** 27 | 28 | ## Working Flow 29 | Different level design can use this tool with different functions a/o inputs/outputs, the main working flow is as below
30 | ![Working Flow](https://github.com/WilsonChen003/HDLGen/blob/master/doc/WorkingFlow.PNG) 31 | 32 | ## What you can do with HDLGen 33 | RTL stitch 34 | * Instance module from RTL or IPXACT or JSON file as what Verilog does 35 | * Connect module's port to wires with native regular express 36 | * Automatically generate instance's wires definitions 37 | * Automatically generate reg or wire definictions(not perfect but really helpful) 38 | * Warning out any Instance signals which has no connection 39 | * Use embedded native Perl or Python to generate(print) whatever code you want (replace structure/for/generate) 40 | 41 | Interface manipulate 42 | * Add interface from IPXACT, JSON, RTL, SV code, or hash array 43 | * Add port to interface by name 44 | * Remove port from interface by name 45 | * Print or show interface signals for design or debug 46 | 47 | IPXACT manipulate 48 | * Read in IPXACT or JSON and import all interfaces & ports 49 | * Show all interfaces defined in IPXACT ( for debug ) 50 | * Translate IPXACT into JSON file ( for debug & integration) 51 | * Export Interface to JSON with name changing 52 | * Export port or remove port to/from JSON file 53 | * Generator module JSON with name,interface,port for up-level integration 54 | * Export interface to IPXACT by name ( **abolished** ) 55 | * Export port to IPXACT by name ( **abolished** ) 56 | * Export standard IPXACT for current top module ( **abolished** ) 57 | 58 | Function generation 59 | * Use embedded functions to generate differnt module or loigc you want 60 | * Clk, Reset, Fuse, Pmu, Fifo, Async-interface, Memories etc ( flow done, can custom design by anyone) 61 | * Extend your own module/logic by standard config ( in development ) 62 | * config can be in Verilog, JSON, YAML, EXCEL etc. 63 | * then generate these logic with parameters by just a simple function call 64 | 65 | **Based on above functions, this tool can generate a SOC in an easy and flexible way** 66 | 67 | ## What you cannot do with HDLGen 68 | * Detail logic design: you still need to write RTL to implement your ideas 69 | * Synthesis or simulation or verification: you need to use other EDA tools to handle 70 | 71 | 72 | 73 | ## Directory Structure 74 | ├── HDLGen.bin # Tool binary for easy adopt 75 | ├── HDLGen.pl # Tool source code 76 | ├── plugins # Tool plugin funcitons in Perl module 77 | ├── Design_Template # custom module design template files 78 | ├── test # Source design code for testing 79 | ├── cfg # JSON and XML for config 80 | ├── incr # necessary design files 81 | ├── doc # usage introduction 82 | 83 | ## Usage 84 | first you need to set shell ENV of ***HDLGEN_ROOT***, otherwise tool will report error.
85 | plese refer to `setenv.sh`
86 | then run command as simple as:
87 | `cd test`
88 | `../HDLGen.pl -i NV_NVDLA_CMAC_CORE_mac.src` or `../HDLGen.bin -i NV_NVDLA_CMAC_CORE_mac.src`
89 | or `../HDLGen.pl -f ./src.list`
90 | for help message you can run:
91 | `HDLGen.pl -usage` 92 | 93 | ### NOTE: 94 | * Verilog-mode for EMACS or VIM is very powerful to do AUTO Port,Reg/Wire, and Instance, but it has some limitations or inconvenient things:
95 | --- mostly used in GUI mode but no batch mode -- ***seems NOT TURE***
96 | --- Instance port/wire name change is manual hard mapping but no Regular Express --- ***NOT TRUE, RE is supproted but need 3rd file***
97 | --- No Warning for unconnected instance signals
98 | --- No Interface a/o IPXACT support
99 | --- No embedded Perl/Python support
100 | --- no function generation for inhouse/customer design 101 | * this tool only test on Ubuntu 18.04.05 & 20.04.5 with Perl-5.34, but should work on any system have Perl5 installed 102 | * Python script only support python3 but no python2.x (one more reason for why not Python ;-) ) 103 | * several Perl Modules are required, can refer to the package head in source code, here listed:
104 | Getopt
105 | JSON
106 | Text::Template
107 | File::Basename
108 | File::Find
109 | Verilog::Netlist
110 | XML::Simple
111 | XML::SAX::Expat; *#this is strange as not used at all, but pp need it*
112 | Dumper
113 | Text::ParseWords
114 | Term::ANSIColor
115 | 116 | 117 | **Suggestion:**
118 | You can first run HDLGen.pl, then install any package according to the error message,
119 | or just run HDLGen.bin for results 120 | 121 | 122 | ### Samples 123 | **AutoDef Sample:**
124 |
125 | 126 | 127 | **AutoInstSig Sample:**
128 |
129 | 130 | **AutoWarning Sample:**
131 |
132 | 133 | 134 | **Verilog Instance Sample:**
135 |
136 | 137 | **IPXACT Instance Sample:**
138 |
139 | 140 | 141 | **JSON Instance Sample:**
142 |
143 | 144 | 145 | **Design Template File Sample:**
146 |
147 | 148 | 149 | 150 | ### ***Why need this tool?***
151 |   For any ASIC or SOC engineer with over 10 years experience, we may hate Verilog sometime, as Verilog HDL's syntax is TOO simple or TOO basic, it's Register Transfer Level description, we're not writing code, we're indeed designing circuit, it's very cool, but sometime we will be bored, especially when instancing module, do wire connections.
152 |   We're very excited when seeing System Verilog for design, because some new syntax like structure,for,generator can impove coding efficiency dramatically,but unfortuantely these syntax will really cause pain when debugging, because ability of EDA tools. Evenmore, some time engineer may need to manually change code to workaround EDA tool on RTL or netlist, this really cause risk to projects.
153 |    Then, in order to reduce manual work and improve efficiency, we'll try to use script to generate bulk of structural code, or for module/chip integration, the script we tried includes Perl,Python,Shell, or Vim/Emacs language. But, these ways often need manual run a/o copy in flow, it will cause big risk if any version is not aligned or any manual step is missed. 154 |   So we will try new different ways, we may study and learn Chisel, SpinalHDL, MyHDL PyHDL, or PyGear recently. But, when we learned, tried, finally we gave up, because they're DSL, they're not HDL! DSL is totally new language, DSL is more like a high level software language, we have to write code in a new style, no Verilog or HDL at all.
155 |   We'll ask: is it safe for a project to abandon Verilog HDL? Is it safe for an experienced engineer to abandon previous skills and design logic with non-HDL code? Is it easy or friendly to learn a new language? Is that language widely used or accepted and will evolve in long term? Is that language suitable and safe for IP/SOC/ASIC development? Is there any different way to help us?
156 |   Yes, we have a different way! And it is easy to use, smoothly to move, seamlessly to adopt.
157 |   The tool is going to support you keep writing HDL while give the ability to improve your efficiency, and with ZERO learning curve, is here, named as "HDLGen".
158 |   The way you're going to work is writing Verilog or VHDL code, the tool helps you on most boring tasks: signal define for wire a/o reg, instance modules by connections with auto wire signals defined and easy name change, connect signals with regular expression, instance JSON and IPXACT xml file as simple as HDL code natively. If any task/logic/design which is not friendly written in HDL, then you can use high level script language like Perl or Python for any code or task you want, wherever and whenever in the HDL source file, as long as you know Perl or Python script, or even shell script.
159 |   This tool supports standard AMBA bus interfaces natively. This tool also support you to manually define an interface, through SystemVerilog, Verilog, IPXACT or XML, JSON, or Hash array.
160 |   If there is any inhouse developed or accumulated design which is common for your designs, you can put as a template in this tool, then instance with any parameters you want by just as simple as one function call in HDL.
161 | 162 | 163 | __*** The most intuitive and effective design is "what you see is what you coding" ***__
164 | __*** In most cases, Verilog is the most secure design ***__
165 | __*** At the system level, the use of parameters requires extreme caution ***__
166 | 167 | 168 | __*** DSL is really cool ***__
169 | __*** But Verilog is still the King ***__
170 | __*** Connection is what you need ***__
171 | __*** And Fexibility is really helpful ***__
172 | 173 | 174 | ## Thanks 175 | ***Thanks NVIDIA for giving me the chance to know how Perl is powerful to run big ASIC factory,***
176 | ***Thanks NVIDIA's VIVA to let me know how Perl makes Verilog intersting and amazing.***
177 | ***Thanks NVIDIA's open sourced NVDLA as a test source.***
178 | 179 | ### ***Note:*** 180 | This tool was developed from scratch during the special spring time in Shanghai in 2022
181 | The things related to NVIDIA are:
182 | * 2 functions' name（Instance,Connect) are identical;
183 | * several HDL files of open sourced NVDLA are used to be test source
184 | 185 | *************************************************************** 186 | ***Please kindly let me know if there is any license issue*** 187 | *************************************************************** 188 | 189 | -------------------------------------------------------------------------------- /doc/AutoDef_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/AutoDef_Sample.PNG -------------------------------------------------------------------------------- /doc/AutoInstSig_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/AutoInstSig_Sample.PNG -------------------------------------------------------------------------------- /doc/AutoWarning_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/AutoWarning_Sample.PNG -------------------------------------------------------------------------------- /doc/Design_Template_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/Design_Template_Sample.PNG -------------------------------------------------------------------------------- /doc/HDLGen_Intro_En.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/HDLGen_Intro_En.pdf -------------------------------------------------------------------------------- /doc/IPXACT_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/IPXACT_Sample.PNG -------------------------------------------------------------------------------- /doc/Instance_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/Instance_Sample.PNG -------------------------------------------------------------------------------- /doc/JSON_Sample.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/JSON_Sample.PNG -------------------------------------------------------------------------------- /doc/WorkingFlow.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/doc/WorkingFlow.PNG -------------------------------------------------------------------------------- /plugins/AsyncIntfGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | # 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | 19 | package AsyncIntfGen; 20 | use strict; 21 | use warnings FATAL => qw(all); 22 | 23 | use Text::Template; 24 | use JSON; 25 | 26 | #use Getopt::Long qw(GetOptions); 27 | #use JSON; 28 | #use eFuncPrint; 29 | 30 | =head1 AsyncIntfGen 31 | 32 | &eFunc::AsyncIntfGen("mod_name", "json_file"); 33 | 34 | Required Inputs: 35 | mod_name : generated RTL & Module name 36 | json_file : containt all parameters template design file needs 37 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 38 | all Perl syntax is supported 39 | 40 | =cut 41 | 42 | use base ("Exporter"); 43 | our @EXPORT = qw(AsyncIntfGen); 44 | 45 | sub AsyncIntfGen { 46 | my $mod_name = shift; ### module name, as file name too 47 | my $cfg_file = shift; ### cfg json file for parameters 48 | 49 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 50 | #================================ 51 | # OPTIONS 52 | #================================ 53 | our $clk = "clk"; 54 | 55 | my $reset = ""; 56 | my $test = 0; 57 | 58 | my $left = "<:"; 59 | my $right = ":>"; 60 | #================================ 61 | 62 | my $cfg_json = &HDLGen::FindFile($cfg_file); 63 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 64 | my $json_text = do { local $/; }; 65 | close(JSON); 66 | my $cfg_hash = decode_json($json_text); 67 | $cfg_hash->{"mod_name"} = "$mod_name"; 68 | 69 | 70 | #================================ 71 | my $result = ""; 72 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/AsyncIntf.tmpl.v"; 73 | if (!(-e $tmpl_file)) { 74 | die " !!!ERROR!!!: your ClkGen design template does NOT existe!\n"; 75 | } 76 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 77 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 78 | 79 | close(MOD_OUT); 80 | 81 | } 82 | 83 | 1; 84 | -------------------------------------------------------------------------------- /plugins/ClkGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | package ClkGen; 22 | use strict; 23 | use warnings FATAL => qw(all); 24 | 25 | use Text::Template; 26 | use JSON; 27 | 28 | 29 | =head1 ClkGen 30 | 31 | &eFunc::ClkGen("mod_name", "json_file"); 32 | 33 | Required Inputs: 34 | mod_name : generated RTL & Module name 35 | json_file : containt all parameters template design file needs 36 | 37 | template_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 38 | all Perl syntax is supported 39 | 40 | =cut 41 | 42 | use base ("Exporter"); 43 | our @EXPORT = qw(ClkGen); 44 | 45 | sub ClkGen { 46 | my $mod_name = shift; 47 | my $cfg_file = shift; 48 | 49 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 50 | #================================ 51 | #================================ 52 | our $clk = "clk"; 53 | 54 | my $reset = ""; 55 | my $test = 0; 56 | 57 | my $left = "<:"; 58 | my $right = ":>"; 59 | #================================ 60 | 61 | 62 | my $cfg_json = &HDLGen::FindFile($cfg_file); 63 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 64 | my $json_text = do { local $/; }; 65 | close(JSON); 66 | my $cfg_hash = decode_json($json_text); 67 | $cfg_hash->{"mod_name"} = "$mod_name"; 68 | 69 | my $async = $cfg_hash->{"async"}; 70 | 71 | #================================ 72 | my $result = ""; 73 | 74 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/Clk.tmpl.v"; 75 | if (!(-e $tmpl_file)) { 76 | die " !!!ERROR!!!: your ClkGen design template does NOT existe!\n"; 77 | } 78 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 79 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 80 | 81 | close(MOD_OUT); 82 | 83 | 84 | 85 | } 86 | 87 | 1; 88 | -------------------------------------------------------------------------------- /plugins/Design_Template/AsyncFifo.tmpl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/plugins/Design_Template/AsyncFifo.tmpl.v -------------------------------------------------------------------------------- /plugins/Design_Template/AsyncIntf.tmpl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/f216b256e5b882fa6f305b79c21b377d26feeb93/plugins/Design_Template/AsyncIntf.tmpl.v -------------------------------------------------------------------------------- /plugins/Design_Template/Clk.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | 18 | //================================================================================================ 19 | //======= this is internal design for Clk =============== 20 | //================================================================================================ 21 | //// default module name is : Clk_Gen 22 | 23 | module <:$mod_name:> 24 | ( 25 | input wire <:$clk:>, 26 | input wire rstn, 27 | 28 | // You need to change ports to your specific design 29 | input wire <:$en:>, 30 | 31 | input wire [2:0] <:$clk_sel:>, 32 | input wire [5:0] <:$divn:>, 33 | 34 | input wire <:$src0:>, 35 | input wire <:$src1:>, 36 | input wire <:$src2:>, 37 | input wire <:$src3:>, 38 | input wire <:$src4:>, 39 | input wire <:$src5:>, 40 | input wire <:$src6:>, 41 | input wire <:$src7:>, 42 | 43 | <: 44 | if ($test ==1) { 45 | $VOUT .= " 46 | input wire $occ_clk, 47 | input wire TEST_EN, 48 | input wire SCAN_EN, 49 | "; 50 | } 51 | :> 52 | 53 | output wire <:$oclk:>, 54 | ); 55 | 56 | <: 57 | if ($test ) { 58 | $OUT .= " // Please add Test OCC_CLK Control logic here"; 59 | } 60 | :> 61 | 62 | 63 | //======================================================================================================================= 64 | // Please add your implement logic below , 65 | // Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var} 66 | //======================================================================================================================= 67 | 68 | 69 | 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /plugins/Design_Template/Fuse.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | // 18 | //================================================================================================ 19 | //======= this is internal design for Fuse =============== 20 | //================================================================================================ 21 | //// default module name is : Fuse 22 | 23 | module <:$mod_name:> 24 | ( 25 | input wire <:$clk:>, 26 | input wire rstn, 27 | 28 | // You need to change ports to your specific design 29 | output wire fuse_bit0, 30 | output wire fuse_bit1, 31 | output wire fuse_bit2, 32 | output wire fuse_bit3, 33 | output wire fuse_bit4, 34 | output wire fuse_bit5, 35 | output wire fuse_bit6, 36 | output wire fuse_bit7 37 | 38 | ); 39 | 40 | <: 41 | if ($en ) { 42 | $OUT .= " // Please add Enable Control logic here"; 43 | } 44 | 45 | if ($test ) { 46 | $OUT .= " // Please add Test OCC_CLK Control logic here"; 47 | } 48 | :> 49 | 50 | 51 | //======================================================================================================================= 52 | // Please add your implement logic below , 53 | // Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var} 54 | //======================================================================================================================= 55 | 56 | 57 | 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /plugins/Design_Template/Mem.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | 18 | //================================================================================================ 19 | //======= this is internal design for Mem module =============== 20 | //================================================================================================ 21 | //// default module name is : Mem 22 | 23 | module <:$mod_name:> 24 | parameter DATA_WIDTH = <:$dwd:>; 25 | parameter DATA_DEPTH = <:$depth:>; 26 | parameter ADDR_WIDTH = <:$awd:>; 27 | ( 28 | input wire <:$clk:>, 29 | input wire rstn, 30 | 31 | // You need to change ports to your specific design 32 | input wire wr_en, 33 | input wire [ADD_WIDTH-1:0] wr_addr, 34 | input wire rd_en, 35 | input wire [ADD_WIDTH-1:0] rd_addr, 36 | 37 | output wire [DATA_WIDTH-1:0] rd_out 38 | ); 39 | 40 | <: 41 | if ($en ) { 42 | $OUT .= " // Please add Enable Control logic here"; 43 | } 44 | 45 | if ($test ) { 46 | $OUT .= " // Please add Test OCC_CLK Control logic here"; 47 | } 48 | :> 49 | 50 | 51 | 52 | //======================================================================================================================= 53 | // Please add your implement logic below , 54 | // Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var} 55 | //======================================================================================================================= 56 | 57 | 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /plugins/Design_Template/Pmu.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | 18 | //================================================================================================ 19 | //======= this is internal design for Pmu =============== 20 | //================================================================================================ 21 | //// default module name is : Pmu 22 | 23 | module <:$mod_name:> 24 | ( 25 | input wire <:$clk:>, 26 | input wire rstn, 27 | 28 | // You need to change ports to your specific design 29 | output wire <:$rst_out:> 30 | ); 31 | 32 | <: 33 | if ($en ) { 34 | $OUT .= " // Please add Enable Control logic here"; 35 | } 36 | 37 | if ($test ) { 38 | $OUT .= " // Please add Test OCC_CLK Control logic here"; 39 | } 40 | :> 41 | 42 | //======================================================================================================================= 43 | // Please add your implement logic below , 44 | // Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var} 45 | //======================================================================================================================= 46 | 47 | 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /plugins/Design_Template/Rst.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | 18 | //================================================================================================ 19 | //======= this is internal design for Rst =============== 20 | //================================================================================================ 21 | //// default module name is : Rst_Gen 22 | 23 | module <:$mod_name:> 24 | ( 25 | input wire <:$clk:>, 26 | input wire <:$rst_in:>, 27 | 28 | // You need to change ports to your specific design 29 | input wire <:$en:>, 30 | 31 | output wire <:$rst_out:> 32 | ); 33 | 34 | <: 35 | if ($en ) { 36 | $OUT .= " // Please add Enable Control logic here"; 37 | } 38 | 39 | if ($test ) { 40 | $OUT .= " // Please add Test OCC_CLK Control logic here"; 41 | } 42 | :> 43 | 44 | 45 | 46 | //======================================================================================================================= 47 | // Please add your implement logic below , 48 | // Please add any cfg parameter in _Cfg.json, and used in code as a variabe of {$var} 49 | //======================================================================================================================= 50 | 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /plugins/Design_Template/SyncFifo.tmpl.v: -------------------------------------------------------------------------------- 1 | //############################################################################################################## 2 | //############################################################################################################## 3 | //############################################################################################################## 4 | //### Copyright 2022~2023 Wilson Chen ### 5 | //### Licensed under the Apache License, Version 2.0 (the "License"); ### 6 | //### You may not use this file except in compliance with the License. ### 7 | //### You may obtain a copy of the License at ### 8 | //### http://www.apache.org/licenses/LICENSE-2.0 ### 9 | //### Unless required by applicable law or agreed to in writing, software ### 10 | //### distributed under the License is distributed on an "AS IS" BASIS, ### 11 | //### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 12 | //### See the License for the specific language governing permissions and ### 13 | //### limitations under the License. ### 14 | //############################################################################################################## 15 | //############################################################################################################## 16 | //############################################################################################################## 17 | 18 | //================================================================================================ 19 | //======= this is internal design for Sync Fifo =============== 20 | //================================================================================================ 21 | //// default module name is : sync_fifo 22 | 23 | module <:$mod_name:> 24 | parameter DATA_WIDTH = <:$dwd:>; 25 | parameter DATA_DEPTH = <:$depth:>; 26 | parameter PTR_WIDTH = <:$awd:>; 27 | //parameter PTR_WIDTH = $clog2(DATA_DEPTH) 28 | ( 29 | input wire <:$clk:>, 30 | input wire rstn , 31 | 32 | //write interface 33 | input wire wr_en , 34 | input wire [DATA_WIDTH-1:0] wr_din, 35 | 36 | //read interface 37 | input wire rd_en , 38 | output reg [DATA_WIDTH-1:0] rd_dout, 39 | 40 | //Flags_o 41 | output reg full , 42 | output reg empty 43 | ); 44 | 45 | <: 46 | if ($noram == 1) { 47 | $OUT .= " reg [DATA_WIDTH-1:0] FIFO_DFF_ARRAY [DATA_DEPTH-1:0];"; 48 | } 49 | :> 50 | 51 | reg [PTR_WIDTH-1 :0] wr_ptr ; 52 | reg [PTR_WIDTH-1 :0] rd_ptr ; 53 | reg [PTR_WIDTH :0] elem_cnt ; 54 | reg [PTR_WIDTH :0] elem_cnt_nxt ; 55 | //Flags 56 | wire full_comb ; 57 | wire empty_comb ; 58 | 59 | /*---------------------------------------------------\ 60 | --------------- write poiter addr ---------------- 61 | \---------------------------------------------------*/ 62 | always @ (posedge clk_i or negedge rst_n_i) begin 63 | if (!rst_n_i) begin 64 | wr_ptr <= 3'b0; 65 | end 66 | else if (wr_en_i && !full_o) begin 67 | wr_ptr <= wr_ptr + 3'b1; 68 | end 69 | end 70 | 71 | /*---------------------------------------------------\ 72 | -------------- read poiter addr ------------------ 73 | \---------------------------------------------------*/ 74 | always @ (posedge clk_i or negedge rst_n_i) begin 75 | if (!rst_n_i) begin 76 | rd_ptr <= 3'b0; 77 | end 78 | else if (rd_en_i && !empty_o) begin 79 | rd_ptr <= rd_ptr + 3'b1; 80 | end 81 | end 82 | 83 | /*---------------------------------------------------\ 84 | --------------- element counter ------------------ 85 | \---------------------------------------------------*/ 86 | 87 | always @ (posedge clk_i or negedge rst_n_i) begin 88 | if (!rst_n_i) begin 89 | elem_cnt <= 4'b0; 90 | end 91 | else if (wr_en_i && rd_en_i && !full_o && !empty_o) begin 92 | elem_cnt <= elem_cnt; 93 | end 94 | else if(wr_en_i && !full_o) begin 95 | elem_cnt <= elem_cnt + 1'b1; 96 | end 97 | else if(rd_en_i && !empty_o) begin 98 | elem_cnt <= elem_cnt - 1'b1; 99 | end 100 | end 101 | 102 | /*---------------------------------------------------\ 103 | ------------- generate the flags ----------------- 104 | \---------------------------------------------------*/ 105 | always @(*) begin 106 | if(!rst_n_i) begin 107 | elem_cnt_nxt = 1'b0; 108 | end 109 | else if(elem_cnt != 4'd0 && rd_en_i && !empty_o) begin 110 | elem_cnt_nxt = elem_cnt - 1'b1; 111 | end 112 | else if(elem_cnt != 4'd8 && wr_en_i && !full_o) begin 113 | elem_cnt_nxt = elem_cnt + 1'b1; 114 | end 115 | else begin 116 | elem_cnt_nxt = elem_cnt; 117 | end 118 | end 119 | 120 | assign full_comb = (elem_cnt_nxt == 4'd8); 121 | assign empty_comb = (elem_cnt_nxt == 4'd0); 122 | 123 | always @ (posedge clk_i or negedge rst_n_i) begin 124 | if (!rst_n_i) begin 125 | full <= 1'b0; 126 | end 127 | else begin 128 | full <= full_comb; 129 | end 130 | end 131 | 132 | always @ (posedge clk_i or negedge rst_n_i) begin 133 | if (!rst_n_i) begin 134 | empty <= 1'b1; 135 | end 136 | else begin 137 | empty <= empty_comb; 138 | end 139 | end 140 | 141 | 142 | <: 143 | if ($noram) { 144 | $OUT .= " 145 | /*---------------------------------------------------\ 146 | -------------------- read data ------------------- 147 | \---------------------------------------------------*/ 148 | always @ (posedge clk_i or negedge rst_n_i) begin 149 | if (!rst_n_i) begin 150 | rd_data_o <= 32'b0; 151 | end 152 | else if(rd_en_i && !empty_o) begin 153 | rd_data_o <= FIFO_DFF_ARRAY[rd_ptr]; 154 | end 155 | end 156 | 157 | /*---------------------------------------------------\ 158 | ------------------- write data ------------------- 159 | \---------------------------------------------------*/ 160 | reg [PTR_WIDTH:0] i; 161 | 162 | always @ (posedge clk_i or negedge rst_n_i) begin 163 | if (!rst_n_i) begin 164 | for(i=0;i 192 | 193 | -------------------------------------------------------------------------------- /plugins/FifoGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | package FifoGen; 22 | use strict; 23 | use warnings FATAL => qw(all); 24 | 25 | use Text::Template; 26 | use JSON; 27 | 28 | 29 | =head1 FifoGen 30 | 31 | &eFunc::FifoGen("mod_name", "json_file"); 32 | 33 | Required Inputs: 34 | mod_name : generated RTL & Module name 35 | json_file : containt all parameters template design file needs 36 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 37 | all Perl syntax is supported 38 | 39 | =cut 40 | 41 | use base ("Exporter"); 42 | our @EXPORT = qw(FifoGen); 43 | 44 | sub FifoGen { 45 | my $mod_name = shift; 46 | my $cfg_file = shift; 47 | 48 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 49 | #================================ 50 | #================================ 51 | our $clk = "clk"; 52 | 53 | my $reset = ""; 54 | my $test = 0; 55 | 56 | my $left = "<:"; 57 | my $right = ":>"; 58 | #================================ 59 | 60 | my $cfg_json = &HDLGen::FindFile($cfg_file); 61 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 62 | my $json_text = do { local $/; }; 63 | close(JSON); 64 | my $cfg_hash = decode_json($json_text); 65 | $cfg_hash->{"mod_name"} = "$mod_name"; 66 | 67 | my $async = $cfg_hash->{"async"}; 68 | 69 | #================================ 70 | my $result = ""; 71 | if ($async == 1) { 72 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/AsyncFifo.tmpl.v"; 73 | if (!(-e $tmpl_file)) { 74 | die " !!!ERROR!!!: your Async-FIFO design template does NOT existe!\n"; 75 | } 76 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 77 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 78 | } else { 79 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/SyncFifo.tmpl.v"; 80 | if (!(-e $tmpl_file)) { 81 | die " !!!ERROR!!!: your Sync-FIFO design template does NOT existe!\n"; 82 | } 83 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 84 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 85 | } 86 | 87 | close(MOD_OUT); 88 | 89 | } 90 | 91 | 1; 92 | -------------------------------------------------------------------------------- /plugins/FuseGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | package FuseGen; 22 | use strict; 23 | use warnings FATAL => qw(all); 24 | 25 | use Text::Template; 26 | use JSON; 27 | 28 | 29 | =head1 FuseGen 30 | 31 | &eFunc::FuseGen("json_file", "template_file"); 32 | 33 | Required Inputs: 34 | mod_name : generated RTL & Module name 35 | json_file : containt all parameters template design file needs 36 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 37 | all Perl syntax is supported 38 | 39 | =cut 40 | 41 | use base ("Exporter"); 42 | our @EXPORT = qw(FuseGen); 43 | 44 | sub FuseGen { 45 | my $mod_name = shift; 46 | my $cfg_file = shift; 47 | 48 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 49 | #================================ 50 | #================================ 51 | our $clk = "clk"; 52 | 53 | my $reset = ""; 54 | my $test = 0; 55 | 56 | my $left = "<:"; 57 | my $right = ":>"; 58 | #================================ 59 | 60 | my $cfg_json = &HDLGen::FindFile($cfg_file); 61 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 62 | my $json_text = do { local $/; }; 63 | close(JSON); 64 | my $cfg_hash = decode_json($json_text); 65 | $cfg_hash->{"mod_name"} = "$mod_name"; 66 | 67 | #================================ 68 | my $result = ""; 69 | 70 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/Fuse.tmpl.v"; 71 | if (!(-e $tmpl_file)) { 72 | die " !!!ERROR!!!: your FuseGen design template does NOT existe!\n"; 73 | } 74 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 75 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 76 | 77 | close(MOD_OUT); 78 | 79 | 80 | } 81 | 82 | 1; 83 | -------------------------------------------------------------------------------- /plugins/MemGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | package MemGen; 22 | use strict; 23 | use warnings FATAL => qw(all); 24 | 25 | use Text::Template; 26 | use JSON; 27 | 28 | 29 | =head1 MemGen 30 | 31 | &eFunc::MemGen("json_file", "template_file"); 32 | 33 | Required Inputs: 34 | mod_name : generated RTL & Module name 35 | json_file : containt all parameters template design file needs 36 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 37 | all Perl syntax is supported 38 | 39 | =cut 40 | 41 | use base ("Exporter"); 42 | our @EXPORT = qw(MemGen); 43 | 44 | sub MemGen { 45 | my $mod_name = shift; 46 | my $cfg_file = shift; 47 | 48 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 49 | #================================ 50 | #================================ 51 | our $clk = "clk"; 52 | 53 | my $reset = ""; 54 | my $test = 0; 55 | 56 | my $left = "<:"; 57 | my $right = ":>"; 58 | #================================ 59 | 60 | my $cfg_json = &HDLGen::FindFile($cfg_file); 61 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 62 | my $json_text = do { local $/; }; 63 | close(JSON); 64 | my $cfg_hash = decode_json($json_text); 65 | $cfg_hash->{"mod_name"} = "$mod_name"; 66 | 67 | #================================ 68 | my $result = ""; 69 | 70 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/Mem.tmpl.v"; 71 | if (!(-e $tmpl_file)) { 72 | die " !!!ERROR!!!: your MemGen design template does NOT existe!\n"; 73 | } 74 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 75 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 76 | 77 | close(MOD_OUT); 78 | 79 | 80 | } 81 | 82 | 1; 83 | -------------------------------------------------------------------------------- /plugins/PmuGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | 22 | package PmuGen; 23 | use strict; 24 | use warnings FATAL => qw(all); 25 | 26 | use Text::Template; 27 | use JSON; 28 | 29 | 30 | =head1 PmuGen 31 | 32 | &eFunc::PmuGen("json_file", "template_file"); 33 | 34 | Required Inputs: 35 | mod_name : generated RTL & Module name 36 | json_file : containt all parameters template design file needs 37 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 38 | all Perl syntax is supported 39 | 40 | =cut 41 | 42 | use base ("Exporter"); 43 | our @EXPORT = qw(PmuGen); 44 | 45 | sub PmuGen { 46 | my $mod_name = shift; 47 | my $cfg_file = shift; 48 | 49 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 50 | #================================ 51 | #================================ 52 | our $clk = "clk"; 53 | 54 | my $reset = ""; 55 | my $test = 0; 56 | 57 | my $left = "<:"; 58 | my $right = ":>"; 59 | #================================ 60 | 61 | my $cfg_json = &HDLGen::FindFile($cfg_file); 62 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 63 | my $json_text = do { local $/; }; 64 | close(JSON); 65 | my $cfg_hash = decode_json($json_text); 66 | $cfg_hash->{"mod_name"} = "$mod_name"; 67 | 68 | #================================ 69 | my $result = ""; 70 | 71 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/Pmu.tmpl.v"; 72 | if (!(-e $tmpl_file)) { 73 | die " !!!ERROR!!!: your Pmu design template does NOT existe!\n"; 74 | } 75 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 76 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 77 | 78 | close(MOD_OUT); 79 | 80 | 81 | } 82 | 83 | 1; 84 | -------------------------------------------------------------------------------- /plugins/RstGen.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | 21 | package RstGen; 22 | use strict; 23 | use warnings FATAL => qw(all); 24 | 25 | use Text::Template; 26 | use JSON; 27 | 28 | 29 | =head1 RstGen 30 | 31 | &eFunc::RstGen("json_file", "template_file"); 32 | 33 | Required Inputs: 34 | mod_name : generated RTL & Module name 35 | json_file : containt all parameters template design file needs 36 | tmplate_file : design template file as verilog HDL, any parameter can be replaced by $vars in above json file 37 | all Perl syntax is supported 38 | 39 | =cut 40 | 41 | use base ("Exporter"); 42 | our @EXPORT = qw(RstGen); 43 | 44 | sub RstGen { 45 | my $mod_name = shift; 46 | my $cfg_file = shift; 47 | 48 | open(MOD_OUT, ">${mod_name}.v") or die "!!! Error: can't find output module file of (${mod_name}.v) \n\n"; 49 | #================================ 50 | #================================ 51 | our $clk = "clk"; 52 | 53 | my $reset = ""; 54 | my $test = 0; 55 | 56 | my $left = "<:"; 57 | my $right = ":>"; 58 | #================================ 59 | 60 | my $cfg_json = &HDLGen::FindFile($cfg_file); 61 | open(JSON, "<$cfg_json") or die "!!! Error: can't find input cfg JSON file of ($cfg_json) \n\n"; 62 | my $json_text = do { local $/; }; 63 | close(JSON); 64 | my $cfg_hash = decode_json($json_text); 65 | $cfg_hash->{"mod_name"} = "$mod_name"; 66 | 67 | my $async = $cfg_hash->{"async"}; 68 | 69 | #================================ 70 | my $result = ""; 71 | 72 | my $tmpl_file = "$main::HDLGEN_ROOT/plugins/Design_Template/Rst.tmpl.v"; 73 | if (!(-e $tmpl_file)) { 74 | die " !!!ERROR!!!: your ClkGen design template does NOT existe!\n"; 75 | } 76 | my $template = Text::Template->new(DELIMITERS => [$left, $right], TYPE => "FILE", SOURCE => "$tmpl_file"); 77 | $result = $template->fill_in(HASH => \%$cfg_hash, OUTPUT => \*MOD_OUT); 78 | 79 | close(MOD_OUT); 80 | 81 | 82 | } 83 | 84 | 1; 85 | -------------------------------------------------------------------------------- /plugins/eFunc.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ############################################################################################################## 6 | ### Copyright 2022~2023 Wilson Chen ### 7 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 8 | ### You may not use this file except in compliance with the License. ### 9 | ### You may obtain a copy of the License at ### 10 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 11 | ### Unless required by applicable law or agreed to in writing, software ### 12 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 13 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 14 | ### See the License for the specific language governing permissions and ### 15 | ### limitations under the License. ### 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | ############################################################################################################## 19 | 20 | package eFunc; 21 | use strict; 22 | use base qw(Exporter); 23 | use warnings FATAL => qw(all); 24 | 25 | # add plugin below, and check the usege in each package in the directory 26 | use ClkGen; 27 | use RstGen; 28 | use PmuGen; 29 | use FuseGen; 30 | use MemGen; 31 | use AsyncIntfGen; 32 | use FifoGen; 33 | 34 | 1; 35 | -------------------------------------------------------------------------------- /plugins/eFuncPrint.pm: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env perl 2 | ############################################################################################################## 3 | ############################################################################################################## 4 | ############################################################################################################## 5 | ### Copyright 2022~2023 Wilson Chen ### 6 | ### Licensed under the Apache License, Version 2.0 (the "License"); ### 7 | ### You may not use this file except in compliance with the License. ### 8 | ### You may obtain a copy of the License at ### 9 | ### http://www.apache.org/licenses/LICENSE-2.0 ### 10 | ### Unless required by applicable law or agreed to in writing, software ### 11 | ### distributed under the License is distributed on an "AS IS" BASIS, ### 12 | ### WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ### 13 | ### See the License for the specific language governing permissions and ### 14 | ### limitations under the License. ### 15 | ############################################################################################################## 16 | ############################################################################################################## 17 | ############################################################################################################## 18 | 19 | 20 | package eFuncPrint; 21 | use strict; 22 | use warnings FATAL => qw(all); 23 | 24 | use base ("Exporter"); 25 | our @EXPORT = qw( 26 | vprintl 27 | ); 28 | 29 | sub vprintl { 30 | my @list = @_; 31 | foreach my $item (@list) { 32 | &HDLGen::vprintl("$item"); 33 | } 34 | } 35 | 36 | 37 | 1; 38 | -------------------------------------------------------------------------------- /setenv.sh: -------------------------------------------------------------------------------- 1 | export HDLGEN_ROOT=`pwd` 2 | -------------------------------------------------------------------------------- /test/NV_NVDLA_CMAC_CORE_mac.vp: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: NV_NVDLA_CMAC_CORE_mac.v 10 | 11 | `define INT_NUM_PLIC 240 12 | 13 | module NV_NVDLA_CMAC_CORE_mac ( 14 | nvdla_core_clk //|< i 15 | ,nvdla_wg_clk //|< i 16 | ,nvdla_core_rstn //|< i 17 | ,cfg_is_fp16 //|< i 18 | ,cfg_is_int16 //|< i 19 | ,cfg_is_int8 //|< i 20 | ,cfg_is_wg //|< i 21 | ,cfg_reg_en //|< i 22 | ,dat_actv_data //|< i 23 | ,dat_actv_nan //|< i 24 | ,dat_actv_nz //|< i 25 | //,dat_actv_pvld //|< i 26 | ,dat_pre_exp //|< i 27 | ,dat_pre_mask //|< / 28 | ,dat_pre_pvld //|< i 29 | ,dat_pre_stripe_end //|< i 30 | ,dat_pre_stripe_st //|< i 31 | ,wt_actv_data //|< i 32 | ,wt_actv_nan //|< i 33 | ,wt_actv_nz //|< i 34 | ,wt_actv_pvld //|< i 35 | //,wt_sd_exp //|< i 36 | ,wt_sd_mask //|< i 37 | ,wt_sd_pvld //|< i 38 | ,mac_out_data //|> o 39 | ,mac_out_nan //|> o 40 | ,mac_out_pvld, //|> o 41 | ); 42 | 43 | parameter NUM_INT = 24; 44 | parameter NUM_TEST = 8; 45 | parameter NUM_TOTAL = NUM_INT * NUM_TEST; 46 | 47 | //: our $NUM_INT_VAR = 240; 48 | 49 | // ======================================================================================== 50 | // ======================================================================================== 51 | input nvdla_core_clk; 52 | input nvdla_wg_clk; 53 | input nvdla_core_rstn; 54 | input cfg_is_fp16; 55 | input cfg_is_int16; 56 | input cfg_is_int8; 57 | input cfg_is_wg; 58 | input cfg_reg_en; 59 | input [1023:0] dat_actv_data; 60 | input [63:0] dat_actv_nan; 61 | input [127:0] dat_actv_nz; 62 | //input [103:0] dat_actv_pvld; 63 | input [191:0] dat_pre_exp; 64 | input [63:0] dat_pre_mask; 65 | input dat_pre_pvld; 66 | input dat_pre_stripe_end; 67 | input dat_pre_stripe_st; 68 | input [1023:0] wt_actv_data; 69 | input [63:0] wt_actv_nan; 70 | input [127:0] wt_actv_nz; 71 | input [103:0] wt_actv_pvld; 72 | //input [191:0] wt_sd_exp; 73 | input [63:0] wt_sd_mask; 74 | input wt_sd_pvld; 75 | output [175:0] mac_out_data; 76 | output mac_out_nan; 77 | output mac_out_pvld; 78 | 79 | // ****** these 2 Auto function must be before all wire or reg define ! ****** 80 | // ======================================================================================== 81 | //:AutoDef; 82 | //:AutoInstSig; 83 | // ======================================================================================== 84 | 85 | wire [63:0] test_PRE_PDAT_SUF; 86 | reg [65:0] dbg_sign; 87 | reg [3:0] exp_max; 88 | reg exp_pvld; 89 | 90 | // ======================================================================================== 91 | //// Sample to update search path for config & design files 92 | //: SRC ./incr 93 | //: &SRC ./cfg 94 | // ======================================================================================== 95 | 96 | // ======================================================================================== 97 | // Sample for single line script 98 | // ======================================================================================== 99 | // wire [3:0] exp_sft_00; 100 | // .. 101 | //: for my $i (0..63) { 102 | //: print("wire [7:0] exp_test_$i;\n"); 103 | //: } 104 | // wire [3:0] exp_sft_63; 105 | // 106 | 107 | // ======================================================================================== 108 | // Sample for multi-line script 109 | // ======================================================================================== 110 | //:Begin 111 | for my $i (0..3) { 112 | print("wire [15:0] test_data$i;\n"); 113 | print "wire [15:0] test_DATA$i;"; 114 | } 115 | //:End 116 | 117 | 118 | // ======================================================================================== 119 | // Sample for multi-line script 120 | // ======================================================================================== 121 | //:Begin 122 | for my $i (0..5) { 123 | for my $j (0..9) { 124 | print("reg [35:0] pp_in_l0_a_${i}${j};\n"); 125 | print("reg [35:0] pp_in_l0_b_${i}${j};\n"); 126 | } 127 | } 128 | //:End 129 | 130 | // ======================================================================================== 131 | // Sample for DTI interface generation 132 | // ======================================================================================== 133 | //:&DTIWire("top2dp", 512); 134 | 135 | 136 | //wire [63:0] res_tag_b0; 137 | wire [63:0] res_tag_b1; 138 | wire [63:0] res_tag_b2; 139 | wire [63:0] res_tag_b3; 140 | wire [63:0] res_tag_b4; 141 | wire [63:0] res_tag_b5; 142 | wire [63:0] res_tag_b6; 143 | wire [63:0] res_tag_b7; 144 | 145 | 146 | 147 | // ======================================================================================== 148 | // Sample for Python script 149 | // ======================================================================================== 150 | //#Begin 151 | for i in [0,1,2,3,4,5,6,7]: 152 | print("wire [63:0] test_PY_data%d;" % i ) 153 | //#End 154 | // ======================================================================================== 155 | 156 | 157 | 158 | //============================================================================== 159 | // MAC support Winograd post addition (POA). 160 | // It's a 2-level matrix muliplication implemented by adders. 161 | // Fomular of POA are: 162 | // 163 | // | pp_out_00, pp_out_01, pp_out_02, pp_out_03 | | 1 0 | 164 | // | 1, 1, 1, 0 | | pp_out_04, pp_out_05, pp_out_06, pp_out_07 | | 1, 1 | 165 | // | 0, 1, -1, -1 | | pp_out_08, pp_out_09, pp_out_10, pp_out_11 | | 1, -1 | 166 | // | pp_out_12, pp_out_13, pp_out_14, pp_out_15 | | 0, -1 | 167 | // 168 | //============================================================================== 169 | 170 | 171 | // ======================================================================================== 172 | // Sample for Instance function 173 | //========================================================== 174 | // Sub unit to handle fp16 NaN 175 | //========================================================== 176 | &Instance NV_NVDLA_CMAC_CORE_MAC_nan u_nan; 177 | 178 | 179 | // ======================================================================================== 180 | // Sample for Instance function 181 | //========================================================== 182 | // Fp16 exponent pre-calculaiton instant 183 | //========================================================== 184 | &Instance NV_NVDLA_CMAC_CORE_MAC_exp u_exp; 185 | 186 | 187 | //========================================================== 188 | // Single multiplication instances 189 | //========================================================== 190 | 191 | 192 | always @( 193 | wt_actv_data 194 | ) begin 195 | {wt_actv_data63, wt_actv_data62, wt_actv_data61, wt_actv_data60, wt_actv_data59, wt_actv_data58, wt_actv_data57, wt_actv_data56, wt_actv_data55, wt_actv_data54, wt_actv_data53, wt_actv_data52, wt_actv_data51, wt_actv_data50, wt_actv_data49, wt_actv_data48, wt_actv_data47, wt_actv_data46, wt_actv_data45, wt_actv_data44, wt_actv_data43, wt_actv_data42, wt_actv_data41, wt_actv_data40, wt_actv_data39, wt_actv_data38, wt_actv_data37, wt_actv_data36, wt_actv_data35, wt_actv_data34, wt_actv_data33, wt_actv_data32, wt_actv_data31, wt_actv_data30, wt_actv_data29, wt_actv_data28, wt_actv_data27, wt_actv_data26, wt_actv_data25, wt_actv_data24, wt_actv_data23, wt_actv_data22, wt_actv_data21, wt_actv_data20, wt_actv_data19, wt_actv_data18, wt_actv_data17, wt_actv_data16, wt_actv_data15, wt_actv_data14, wt_actv_data13, wt_actv_data12, wt_actv_data11, wt_actv_data10, wt_actv_data9, wt_actv_data8, wt_actv_data7, wt_actv_data6, wt_actv_data5, wt_actv_data4, wt_actv_data3, wt_actv_data2, wt_actv_data1, wt_actv_data0} = wt_actv_data; 196 | end 197 | 198 | // ======================================================================================== 199 | // Sample for script with for loop and structural connections 200 | // ======================================================================================== 201 | //:Begin 202 | for my $i (0..63) { 203 | my $ii = sprintf("%02d",$i); 204 | &Instance NV_NVDLA_CMAC_CORE_MAC_mul u_mul_$i; 205 | &Connect exp_sft exp_sft_$ii; 206 | Connect op_a_dat wt_actv_data${i}; 207 | Connect op_a_nz wt_actv_nz${ii}; 208 | Connect op_a_pvld wt_actv_pvld[${i}]; 209 | &Connect op_b_dat dat_actv_data${i}; 210 | &Connect op_b_nz dat_actv_nz${i}; 211 | &Connect op_b_pvld dat_actv_pvld[${i}]; 212 | Connect /(res_.*)/ \${1}_$ii; 213 | Connect -final (res_tag) \${1}_$i; ### override above line 214 | 215 | } 216 | //:End 217 | 218 | 219 | //========================================================== 220 | // MAC cell CSA tree level 0 221 | // 64(128) -> 16(32) 222 | //========================================================== 223 | 224 | /////////////////////////////////////////////////////////////////// 225 | //////////////// input select for CSA tree level 0 //////////////// 226 | /////////////////////////////////////////////////////////////////// 227 | 228 | always @( 229 | cfg_is_int8_d0 230 | or res_a_00 231 | or res_b_00 232 | ) begin 233 | pp_in_l0_a_00 = cfg_is_int8_d0[0] ? {2'b0, res_a_00[31:16], 2'b0, res_a_00[15:0]} : 234 | {4'b0, res_a_00[31:0]}; 235 | pp_in_l0_b_00 = cfg_is_int8_d0[0] ? {2'b0, res_b_00[31:16], 2'b0, res_b_00[15:0]} : 236 | {4'b0, res_b_00[31:0]}; 237 | end 238 | 239 | 240 | ////////////////////////////////////////////////////////// 241 | //////////////// CSA tree level 0: 64->16 //////////////// 242 | ////////////////////////////////////////////////////////// 243 | 244 | // ======================================================================================== 245 | // Sample for script with bulk lines printing 246 | // ======================================================================================== 247 | //:Begin 248 | for my $i (0..9) { 249 | ### for bulk print 250 | print < w 255 | ,.OUT1 (pp_out_l0n0${i}_1[35:0]) //|> w 256 | ); 257 | `else 258 | DW02_tree #(8, 36) u_tree_l0n00 ( 259 | .INPUT (pp_in_l0n0${i}[287:0]) //|< r 260 | ,.OUT0 (pp_out_l0n0${i}_0[35:0]) //|> w 261 | ,.OUT1 (pp_out_l0n0${i}_1[35:0]) //|> w 262 | ); 263 | `endif 264 | EOF 265 | } 266 | //:End 267 | 268 | 269 | //========================================================== 270 | //// Sample for strange port defines 271 | /// Sample for empty port connection 272 | //========================================================== 273 | &Instance test_DAC; 274 | `ifdef FPGA 275 | .iSrc_Select ( src_selct_FPGA), 276 | .iCLK_18_4 ( clk_FPGA), 277 | `endif 278 | &Connect iSrc_Select null; 279 | &Connect oFLASH_ADDR ''; 280 | 281 | /////////////////////////////////////////////////////////////////////// 282 | //////////////// assemble output from CSA tree level 0 //////////////// 283 | /////////////////////////////////////////////////////////////////////// 284 | 285 | always @( 286 | pp_out_l0n00_0 287 | or pp_out_l0n00_1 288 | ) begin 289 | pp_out_l0n00_0_d1_w[35:0] = pp_out_l0n00_0; 290 | pp_out_l0n00_1_d1_w[35:0] = pp_out_l0n00_1; 291 | end 292 | 293 | //========================================================== 294 | // Gather FP16 sign tag 295 | //========================================================== 296 | 297 | assign res_tag_b0 = {res_tag_63[0], res_tag_62[0], res_tag_61[0], res_tag_60[0], res_tag_59[0], res_tag_58[0], res_tag_57[0], res_tag_56[0], res_tag_55[0], res_tag_54[0], res_tag_53[0], res_tag_52[0], res_tag_51[0], res_tag_50[0], res_tag_49[0], res_tag_48[0], res_tag_47[0], res_tag_46[0], res_tag_45[0], res_tag_44[0], res_tag_43[0], res_tag_42[0], res_tag_41[0], res_tag_40[0], res_tag_39[0], res_tag_38[0], res_tag_37[0], res_tag_36[0], res_tag_35[0], res_tag_34[0], res_tag_33[0], res_tag_32[0], res_tag_31[0], res_tag_30[0], res_tag_29[0], res_tag_28[0], res_tag_27[0], res_tag_26[0], res_tag_25[0], res_tag_24[0], res_tag_23[0], res_tag_22[0], res_tag_21[0], res_tag_20[0], res_tag_19[0], res_tag_18[0], res_tag_17[0], res_tag_16[0], res_tag_15[0], res_tag_14[0], res_tag_13[0], res_tag_12[0], res_tag_11[0], res_tag_10[0], res_tag_9[0], res_tag_8[0], res_tag_7[0], res_tag_6[0], res_tag_5[0], res_tag_4[0], res_tag_3[0], res_tag_2[0], res_tag_1[0], res_tag_0[0]}; 298 | assign res_tag_b1 = {res_tag_63[1], res_tag_62[1], res_tag_61[1], res_tag_60[1], res_tag_59[1], res_tag_58[1], res_tag_57[1], res_tag_56[1], res_tag_55[1], res_tag_54[1], res_tag_53[1], res_tag_52[1], res_tag_51[1], res_tag_50[1], res_tag_49[1], res_tag_48[1], res_tag_47[1], res_tag_46[1], res_tag_45[1], res_tag_44[1], res_tag_43[1], res_tag_42[1], res_tag_41[1], res_tag_40[1], res_tag_39[1], res_tag_38[1], res_tag_37[1], res_tag_36[1], res_tag_35[1], res_tag_34[1], res_tag_33[1], res_tag_32[1], res_tag_31[1], res_tag_30[1], res_tag_29[1], res_tag_28[1], res_tag_27[1], res_tag_26[1], res_tag_25[1], res_tag_24[1], res_tag_23[1], res_tag_22[1], res_tag_21[1], res_tag_20[1], res_tag_19[1], res_tag_18[1], res_tag_17[1], res_tag_16[1], res_tag_15[1], res_tag_14[1], res_tag_13[1], res_tag_12[1], res_tag_11[1], res_tag_10[1], res_tag_9[1], res_tag_8[1], res_tag_7[1], res_tag_6[1], res_tag_5[1], res_tag_4[1], res_tag_3[1], res_tag_2[1], res_tag_1[1], res_tag_0[1]}; 299 | assign res_tag_b2 = {res_tag_63[2], res_tag_62[2], res_tag_61[2], res_tag_60[2], res_tag_59[2], res_tag_58[2], res_tag_57[2], res_tag_56[2], res_tag_55[2], res_tag_54[2], res_tag_53[2], res_tag_52[2], res_tag_51[2], res_tag_50[2], res_tag_49[2], res_tag_48[2], res_tag_47[2], res_tag_46[2], res_tag_45[2], res_tag_44[2], res_tag_43[2], res_tag_42[2], res_tag_41[2], res_tag_40[2], res_tag_39[2], res_tag_38[2], res_tag_37[2], res_tag_36[2], res_tag_35[2], res_tag_34[2], res_tag_33[2], res_tag_32[2], res_tag_31[2], res_tag_30[2], res_tag_29[2], res_tag_28[2], res_tag_27[2], res_tag_26[2], res_tag_25[2], res_tag_24[2], res_tag_23[2], res_tag_22[2], res_tag_21[2], res_tag_20[2], res_tag_19[2], res_tag_18[2], res_tag_17[2], res_tag_16[2], res_tag_15[2], res_tag_14[2], res_tag_13[2], res_tag_12[2], res_tag_11[2], res_tag_10[2], res_tag_9[2], res_tag_8[2], res_tag_7[2], res_tag_6[2], res_tag_5[2], res_tag_4[2], res_tag_3[2], res_tag_2[2], res_tag_1[2], res_tag_0[2]}; 300 | assign res_tag_b3 = {res_tag_63[3], res_tag_62[3], res_tag_61[3], res_tag_60[3], res_tag_59[3], res_tag_58[3], res_tag_57[3], res_tag_56[3], res_tag_55[3], res_tag_54[3], res_tag_53[3], res_tag_52[3], res_tag_51[3], res_tag_50[3], res_tag_49[3], res_tag_48[3], res_tag_47[3], res_tag_46[3], res_tag_45[3], res_tag_44[3], res_tag_43[3], res_tag_42[3], res_tag_41[3], res_tag_40[3], res_tag_39[3], res_tag_38[3], res_tag_37[3], res_tag_36[3], res_tag_35[3], res_tag_34[3], res_tag_33[3], res_tag_32[3], res_tag_31[3], res_tag_30[3], res_tag_29[3], res_tag_28[3], res_tag_27[3], res_tag_26[3], res_tag_25[3], res_tag_24[3], res_tag_23[3], res_tag_22[3], res_tag_21[3], res_tag_20[3], res_tag_19[3], res_tag_18[3], res_tag_17[3], res_tag_16[3], res_tag_15[3], res_tag_14[3], res_tag_13[3], res_tag_12[3], res_tag_11[3], res_tag_10[3], res_tag_9[3], res_tag_8[3], res_tag_7[3], res_tag_6[3], res_tag_5[3], res_tag_4[3], res_tag_3[3], res_tag_2[3], res_tag_1[3], res_tag_0[3]}; 301 | assign res_tag_b4 = {res_tag_63[4], res_tag_62[4], res_tag_61[4], res_tag_60[4], res_tag_59[4], res_tag_58[4], res_tag_57[4], res_tag_56[4], res_tag_55[4], res_tag_54[4], res_tag_53[4], res_tag_52[4], res_tag_51[4], res_tag_50[4], res_tag_49[4], res_tag_48[4], res_tag_47[4], res_tag_46[4], res_tag_45[4], res_tag_44[4], res_tag_43[4], res_tag_42[4], res_tag_41[4], res_tag_40[4], res_tag_39[4], res_tag_38[4], res_tag_37[4], res_tag_36[4], res_tag_35[4], res_tag_34[4], res_tag_33[4], res_tag_32[4], res_tag_31[4], res_tag_30[4], res_tag_29[4], res_tag_28[4], res_tag_27[4], res_tag_26[4], res_tag_25[4], res_tag_24[4], res_tag_23[4], res_tag_22[4], res_tag_21[4], res_tag_20[4], res_tag_19[4], res_tag_18[4], res_tag_17[4], res_tag_16[4], res_tag_15[4], res_tag_14[4], res_tag_13[4], res_tag_12[4], res_tag_11[4], res_tag_10[4], res_tag_9[4], res_tag_8[4], res_tag_7[4], res_tag_6[4], res_tag_5[4], res_tag_4[4], res_tag_3[4], res_tag_2[4], res_tag_1[4], res_tag_0[4]}; 302 | assign res_tag_b5 = {res_tag_63[5], res_tag_62[5], res_tag_61[5], res_tag_60[5], res_tag_59[5], res_tag_58[5], res_tag_57[5], res_tag_56[5], res_tag_55[5], res_tag_54[5], res_tag_53[5], res_tag_52[5], res_tag_51[5], res_tag_50[5], res_tag_49[5], res_tag_48[5], res_tag_47[5], res_tag_46[5], res_tag_45[5], res_tag_44[5], res_tag_43[5], res_tag_42[5], res_tag_41[5], res_tag_40[5], res_tag_39[5], res_tag_38[5], res_tag_37[5], res_tag_36[5], res_tag_35[5], res_tag_34[5], res_tag_33[5], res_tag_32[5], res_tag_31[5], res_tag_30[5], res_tag_29[5], res_tag_28[5], res_tag_27[5], res_tag_26[5], res_tag_25[5], res_tag_24[5], res_tag_23[5], res_tag_22[5], res_tag_21[5], res_tag_20[5], res_tag_19[5], res_tag_18[5], res_tag_17[5], res_tag_16[5], res_tag_15[5], res_tag_14[5], res_tag_13[5], res_tag_12[5], res_tag_11[5], res_tag_10[5], res_tag_9[5], res_tag_8[5], res_tag_7[5], res_tag_6[5], res_tag_5[5], res_tag_4[5], res_tag_3[5], res_tag_2[5], res_tag_1[5], res_tag_0[5]}; 303 | assign res_tag_b6 = {res_tag_63[6], res_tag_62[6], res_tag_61[6], res_tag_60[6], res_tag_59[6], res_tag_58[6], res_tag_57[6], res_tag_56[6], res_tag_55[6], res_tag_54[6], res_tag_53[6], res_tag_52[6], res_tag_51[6], res_tag_50[6], res_tag_49[6], res_tag_48[6], res_tag_47[6], res_tag_46[6], res_tag_45[6], res_tag_44[6], res_tag_43[6], res_tag_42[6], res_tag_41[6], res_tag_40[6], res_tag_39[6], res_tag_38[6], res_tag_37[6], res_tag_36[6], res_tag_35[6], res_tag_34[6], res_tag_33[6], res_tag_32[6], res_tag_31[6], res_tag_30[6], res_tag_29[6], res_tag_28[6], res_tag_27[6], res_tag_26[6], res_tag_25[6], res_tag_24[6], res_tag_23[6], res_tag_22[6], res_tag_21[6], res_tag_20[6], res_tag_19[6], res_tag_18[6], res_tag_17[6], res_tag_16[6], res_tag_15[6], res_tag_14[6], res_tag_13[6], res_tag_12[6], res_tag_11[6], res_tag_10[6], res_tag_9[6], res_tag_8[6], res_tag_7[6], res_tag_6[6], res_tag_5[6], res_tag_4[6], res_tag_3[6], res_tag_2[6], res_tag_1[6], res_tag_0[6]}; 304 | assign res_tag_b7 = {res_tag_63[7], res_tag_62[7], res_tag_61[7], res_tag_60[7], res_tag_59[7], res_tag_58[7], res_tag_57[7], res_tag_56[7], res_tag_55[7], res_tag_54[7], res_tag_53[7], res_tag_52[7], res_tag_51[7], res_tag_50[7], res_tag_49[7], res_tag_48[7], res_tag_47[7], res_tag_46[7], res_tag_45[7], res_tag_44[7], res_tag_43[7], res_tag_42[7], res_tag_41[7], res_tag_40[7], res_tag_39[7], res_tag_38[7], res_tag_37[7], res_tag_36[7], res_tag_35[7], res_tag_34[7], res_tag_33[7], res_tag_32[7], res_tag_31[7], res_tag_30[7], res_tag_29[7], res_tag_28[7], res_tag_27[7], res_tag_26[7], res_tag_25[7], res_tag_24[7], res_tag_23[7], res_tag_22[7], res_tag_21[7], res_tag_20[7], res_tag_19[7], res_tag_18[7], res_tag_17[7], res_tag_16[7], res_tag_15[7], res_tag_14[7], res_tag_13[7], res_tag_12[7], res_tag_11[7], res_tag_10[7], res_tag_9[7], res_tag_8[7], res_tag_7[7], res_tag_6[7], res_tag_5[7], res_tag_4[7], res_tag_3[7], res_tag_2[7], res_tag_1[7], res_tag_0[7]}; 305 | 306 | 307 | 308 | // ========================================================================================================================================= 309 | // =============== Below for more testing ============== 310 | // ========================================================================================================================================= 311 | 312 | 313 | 314 | //========================================================== 315 | // Config logic 316 | //========================================================== 317 | 318 | always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin 319 | if (!nvdla_core_rstn) begin 320 | cfg_reg_en_d0 <= 1'b0; 321 | end else begin 322 | cfg_reg_en_d0 <= cfg_reg_en; 323 | end 324 | end 325 | always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin 326 | if (!nvdla_core_rstn) begin 327 | cfg_is_int8_d0 <= {65{1'b0}}; 328 | end else begin 329 | if ((cfg_reg_en) == 1'b1) begin 330 | cfg_is_int8_d0 <= {65{cfg_is_int8}}; 331 | // VCS coverage off 332 | end else if ((cfg_reg_en) == 1'b0) begin 333 | end else begin 334 | cfg_is_int8_d0 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) 335 | // VCS coverage on 336 | end 337 | end 338 | end 339 | 340 | 341 | 342 | 343 | 344 | always @(*) 345 | begin 346 | MISO_I_IPX = my_msio; 347 | MOSI_O_IPX = my_mosi; 348 | end 349 | 350 | //========================================================== 351 | //// Sample for IPXACT instance with AddParam function 352 | //========================================================== 353 | //:Begin 354 | &Instance simple_spi.xml my_spi_Param; 355 | AddParam PARM0 A0; 356 | AddParam PARM1 A1; 357 | Connect -final -interface spi -up \${1}_IPX ; 358 | Connect /(clk.*)/ IPX_\${1}; 359 | Connect /(rst.*)/ IPX_\${1}; 360 | //:End 361 | 362 | //============= Sample to Print(show) interface to a file ======== 363 | //: &ShowIntf("spi"); 364 | 365 | 366 | //============= Sample to Translate(show) IPXACT to JSON file ======== 367 | //: &TransIPX("simple_spi.xml"); 368 | 369 | 370 | //========================================================== 371 | //// Sample for IPXACT instance with multi-paramaters 372 | //========================================================== 373 | &Instance simple_spi.xml 374 | #( .parm0(0), 375 | .param1(1), 376 | .param2(2) 377 | ) 378 | my_spi; 379 | Connect -final -interface spi -up \${1}_IPX ; 380 | Connect /(clk.*)/ IPX_\${1}; 381 | Connect /(rst.*)/ IPX_\${1}; 382 | 383 | 384 | //========================================================== 385 | //// Sample for JSON instance 386 | //========================================================== 387 | &Instance my_test_design.JSON; 388 | Connect -final /(PRE_PDAT_SUF)/ {test_\${1}[63:34],2'b00}; 389 | Connect -final -interface my_spi My_\${1} ; 390 | Connect /(clk.*)/ My_\${1}; 391 | Connect /(reset.*)/ My_\${1}; 392 | 393 | //========================================================== 394 | // Final register for MAC output 395 | //========================================================== 396 | 397 | always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin 398 | if (!nvdla_core_rstn) begin 399 | mac_out_pvld <= 1'b0; 400 | end else begin 401 | mac_out_pvld <= pp_pvld_d3[0]; 402 | end 403 | end 404 | 405 | 406 | //========================================================== 407 | //// Sample for Interface add & print 408 | //========================================================== 409 | //: &AddIntfByIPX("./cfg/simple_spi.xml"); 410 | //: &AddIntfByJson("./cfg/MyIntf.json"); 411 | //: &PrintIntfPort("-intf spi"); 412 | 413 | 414 | //========================================================== 415 | //// Sample of normal Perl script with hash 416 | //========================================================== 417 | //:Begin 418 | my %test_hash = ( 419 | 'sys_ctrl'=> "&", 420 | 'sys_en' => "&", 421 | 'sys_off' => "|", 422 | 'sys_on' => "" 423 | ); 424 | for my $i (0..3) { 425 | my $sig = "test_input$i & ( "; 426 | foreach my $test_sig (sort(keys(%test_hash))) { 427 | $sig .= " $test_sig"." $test_hash{$test_sig} "; 428 | } 429 | print "assign test_wire$i = $sig );\n"; 430 | } 431 | //:End 432 | 433 | 434 | always @(*) begin 435 | dat_pre_exp <= my_data_pre_exp ; 436 | dat_pre_mask<= my_data_pre_max ; 437 | end 438 | 439 | 440 | //========================================================== 441 | //// Sample of Connect with standard AMBA interface 442 | //========================================================== 443 | &Instance test_sys_ctrl_apb_regs; 444 | Connect -final -interface APB3 -up \${1}_suffix ; 445 | 446 | //: &PrintAmbaBus("-type APB3 -awd 18 -d 32 -pre Test_ -u "); 447 | 448 | 449 | //========================================================== 450 | //// Sample of interface keyword 451 | //========================================================== 452 | &Instance apb_test; 453 | Connect -interface APB3 -key sys_ctrl_*_test KEY_\$1; 454 | 455 | //========================================================== 456 | //// Sample of adding interface from Perl Hash Array 457 | //========================================================== 458 | //:Begin 459 | my %APB3 = ( 460 | 'pSELx' => "input: 1", 461 | 'pADDR' => "input: 32", 462 | 'pENABL' => "input: 1", 463 | 'pRDATA' => "output: 32", 464 | 'pREADY' => "output: 1", 465 | 'pSLVERR' => "output: 1", 466 | 'pDAT' => "input: 32" 467 | ); 468 | &AddIntfByHash(\%APB3,"test_APB3"); 469 | &PrintIntfPort("-intf test_APB3 -awd 12 -d 32 -pre my_ -port -end ;"); 470 | //:End 471 | 472 | //========================================================== 473 | //// Sample of embeded variable 474 | //========================================================== 475 | //: our $reset= " or negedge resetn"; 476 | 477 | //========================================================== 478 | //// Sample of adding interface by SystemVerilog interface code 479 | //========================================================== 480 | //:Begin 481 | my $sv = " 482 | interface test_if(input clk); 483 | logic rst_n, 484 | wire [1:0] port_a_0 ; 485 | logic [12:0] port_a_1 ; 486 | wire port_b_0 ; 487 | logic port_b_1 ; 488 | endinterface 489 | "; 490 | &AddIntfBySV($sv); 491 | &PrintIntfPort("-intf test_if -up"); 492 | 493 | //:End 494 | 495 | //========================================================== 496 | //// Sample of auto signal declare 497 | //========================================================== 498 | assign test_wires = test_input[3:0]; 499 | 500 | always @(posedge clk ${reset}) 501 | begin 502 | q <= d; 503 | $display("%t:%m: this is a test string\n"); 504 | end 505 | 506 | 507 | assign plic_int_vld[`INT_NUM_PLIC+15:0] = {pad_plic_int_vld[`INT_NUM_PLIC-1:0],14'b0,l2c_plic_ecc_int_vld,1'b0}; 508 | assign plic_int_cfg[`INT_NUM_PLIC+15:0] = {pad_plic_int_cfg[`INT_NUM_PLIC-1:0],16'b0}; 509 | //assign plic_int_cfg = {pad_plic_int_cfg[`INT_NUM_PLIC-1:0],16'b0}; 510 | assign plic_int_cfg_test_0 = {pad_plic_int_cfg[`INT_NUM_PLIC-1:0],16'b0}; 511 | assign plic_int_cfg_test_1 = {pad_plic_int_cfg[239:0],16'b0}; 512 | assign plic_int_cfg_test_2 = {pad_plic_int_cfg[240-1:0],16'b0}; 513 | 514 | assign plic_int_cfg_test_3 = pad_plic_int_cfg[239:0]; 515 | 516 | assign plic_int_cfg_test_4 = {pad_plic_int_cfg[240+2:0],16'b0}; 517 | 518 | assign plic_int_cfg_test_5 = pad_plic_int_cfg[NUM_INT-1:0]; 519 | assign plic_int_cfg_test_6 = {pad_plic_int_cfg[${NUM_INT_VAR}-1:0],16'b0}; 520 | 521 | assign plic_int_cfg_test_7 = {pad_plic_int_cfg[NUM_TOTAL-1:0],16'b0}; 522 | 523 | assign plic_core0_me_int = plic_hartx_mint_req[0]; 524 | assign plic_core0_se_int = plic_hartx_sint_req[0]; 525 | 526 | //========================================================== 527 | //========================================================== 528 | //========================================================== 529 | //// Sample of various inhouse design generation & instance 530 | //========================================================== 531 | //========================================================== 532 | //========================================================== 533 | //: &eFunc::ClkGen("Test_Clk", "./cfg/Clk_Cfg.json"); 534 | 535 | //: &eFunc::RstGen("Test_Rst", "./cfg/Rst_Cfg.json"); 536 | 537 | //: &eFunc::FuseGen("Test_Fuse", "./cfg/Fuse_Cfg.json"); 538 | 539 | //: &eFunc::PmuGen("Test_Pmu", "./cfg/Pmu_Cfg.json"); 540 | 541 | //: &eFunc::MemGen("Test_Mem", "./cfg/Mem_Cfg.json"); 542 | 543 | //: &eFunc::AsyncIntfGen("Test_AsyncIntf", "./cfg/AsyncIntf_Cfg.json"); 544 | 545 | //: &eFunc::FifoGen("Test_SFifo", "./cfg/SFifo_Cfg.json"); 546 | 547 | &Instance Test_SFifo; 548 | 549 | //: &eFunc::FifoGen("Test_AFifo", "./cfg/AFifo_Cfg.json"); 550 | 551 | &Instance Test_AFifo; 552 | 553 | 554 | ////&Instance CORTEXM7INTEGRATIONCS_1.xml u_xml; 555 | //// &Connect -interface Authentication_slave \${1}_Slave; 556 | 557 | endmodule // NV_NVDLA_CMAC_CORE_mac 558 | 559 | 560 | //========================================================== 561 | //========================================================== 562 | //========================================================== 563 | //// Sample of exporting interface & port, 564 | //// generate module JSON file for integration 565 | //// NOTE: GenModJson must be AFTER "endmodule", 566 | //// otherwisse cause syntax error, fix later 567 | //// Othter functions can be anywhere 568 | //========================================================== 569 | //========================================================== 570 | //========================================================== 571 | //: &ExptIntf("-intf_name test_APB3 -name my_APB3 -upcase -prefix Pre_ -suffix _Suf -master"); 572 | //: &ExptIntf("-intf spi -name my_spi"); 573 | //: &ExptPort("clk", "input", "1"); 574 | //: &ExptPort("reset", "input", "1"); 575 | 576 | //manual defined name, may not be same as current module, not recommended 577 | //: &GenModJson("test_design" ); # manual name may not be same as current module, not recommended 578 | 579 | //default usage for current Top Module 580 | //: &GenModJson(); # default usage for current Top Module 581 | 582 | -------------------------------------------------------------------------------- /test/cfg/AFifo_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "awd" : "4", 3 | "dwd" : "64", 4 | "depth" : "16", 5 | "clk" : "clka", 6 | "async" : "1", 7 | "noram" : "1", 8 | "ilatch" : "0", 9 | "olatch" : "0" 10 | } 11 | 12 | -------------------------------------------------------------------------------- /test/cfg/APB.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | MY_CORP.com 4 | MY_CORP_lib 5 | APB 6 | 1.0_mm 7 | 8 | 9 | pENABL 10 | 11 | 12 | 13 | false 14 | 15 | 16 | 8 17 | little 18 | 19 | pAT 20 | 21 | 22 | 23 | false 24 | 25 | 26 | 8 27 | little 28 | 29 | pSELx 30 | 31 | 32 | 33 | false 34 | 35 | 36 | 8 37 | little 38 | 39 | pRDATA 40 | 41 | 42 | 43 | false 44 | 45 | 46 | 8 47 | little 48 | 49 | pADDR 50 | 51 | 52 | 53 | false 54 | 55 | 56 | 8 57 | little 58 | 59 | pREADY 60 | 61 | 62 | 63 | false 64 | 65 | 66 | 8 67 | little 68 | 69 | pSLVERR 70 | 71 | 72 | 73 | false 74 | 75 | 76 | 8 77 | little 78 | 79 | -------------------------------------------------------------------------------- /test/cfg/AsyncIntf_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "awd" : "4", 3 | "dwd" : "64", 4 | "depth" : "16", 5 | "noram" : "1", 6 | "ilatch" : "0", 7 | "olatch" : "0" 8 | } 9 | 10 | -------------------------------------------------------------------------------- /test/cfg/Clk_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "clk" : "clk", 3 | "oclk" : "clk_out", 4 | "divn" : "1", 5 | "clk_sel" : "clk_sel0", 6 | "src0" : "xtal_clk", 7 | "src1" : "clk_32khz", 8 | "src2" : "pll0", 9 | "src3" : "pll1", 10 | "src4" : "pll2", 11 | "src5" : "1'b0", 12 | "src6" : "1'b0", 13 | "src7" : "1'b0", 14 | "en" : "clk_en0", 15 | "occ_clk" : "test_clk", 16 | "test" : "1" 17 | } 18 | -------------------------------------------------------------------------------- /test/cfg/Fuse_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "clk" : "clk", 3 | "en" : "1", 4 | "test" : "1" 5 | } 6 | -------------------------------------------------------------------------------- /test/cfg/Mem_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "dwd" : "32", 3 | "awd" : "8", 4 | "depth" : "256", 5 | "clk" : "clk", 6 | "en" : "1", 7 | "test" : "1" 8 | } 9 | -------------------------------------------------------------------------------- /test/cfg/MyIntf.json: -------------------------------------------------------------------------------- 1 | { 2 | "MyIntf" : { 3 | "intf_sig0" : "reg:1" , 4 | "intf_sig1" : "wire:1" , 5 | "intf_sig2" : "reg:32" 6 | } 7 | } 8 | 9 | -------------------------------------------------------------------------------- /test/cfg/Pmu_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "clk" : "clk", 3 | "rst_out": "rstn_o", 4 | "en" : "1", 5 | "test" : "1" 6 | } 7 | -------------------------------------------------------------------------------- /test/cfg/Regs.json: -------------------------------------------------------------------------------- 1 | { 2 | "#mod_name" : "Optional", 3 | #"mod_name" : "Optional", 4 | "mod_name" : "test_sys_ctrl", 5 | "#base_addr" : "Optional to add base offset on all registers", 6 | "base_addr" : "0x00000010", 7 | "sys_ctrl0" : { 8 | "#field_name" : "width, RW/RO/WO, Reset_Value, 'Comments' ", 9 | "pdc_use_ctrl" : "1, RW, init=0, 'Control if use arm ctrl-seq, HIGH enable' " , 10 | : "NO=0", 11 | : "YES = 1", 12 | "l2c_strip_mode" : "3, RW, init=0, 'Control L2 cache stripping mode, HIGH enable' " , 13 | : "md0=0", 14 | : "md1=1", 15 | : "md2=2", 16 | : "md5=5", 17 | "smmu_mmusid" : "5, RW, init=3" , 18 | "mem_repair_en" : "1, RW, init=5" , 19 | : "NO =0", 20 | : "YES= 1", 21 | "mem_repair_done" : "7, RO, init=7" 22 | }, 23 | "test_reg" : { 24 | "#offset" : "Optional to change per-reg offset, default is incr4(0x4), can be any of aligned hex addr" , 25 | "offset" : "0xc" , 26 | "test_field0" : "4, RW, init=0 , 'This test comments'", 27 | "test_filed1" : "2, WO, init=3" 28 | } 29 | } 30 | 31 | 32 | -------------------------------------------------------------------------------- /test/cfg/Rst_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "clk" : "clk", 3 | "rst_in" : "rstn_i", 4 | "rst_out": "rstn_o", 5 | "en" : "en", 6 | "test" : "1" 7 | } 8 | -------------------------------------------------------------------------------- /test/cfg/SFifo_Cfg.json: -------------------------------------------------------------------------------- 1 | { 2 | "awd" : "4", 3 | "dwd" : "64", 4 | "depth" : "16", 5 | "clk" : "clks", 6 | "async" : "0", 7 | "noram" : "0", 8 | "ilatch" : "0", 9 | "olatch" : "0" 10 | } 11 | -------------------------------------------------------------------------------- /test/cfg/my_test_design.JSON: -------------------------------------------------------------------------------- 1 | { 2 | "module" : "my_test_design", 3 | 4 | "busInterfaces" : { 5 | "my_APB3" : { 6 | "PRE_PSLVERR_SUF" : "input:1" , 7 | "PRE_PSELX_SUF" : "input:1" , 8 | "PRE_PRDATA_SUF" : "input:32" , 9 | "PRE_PREADY_SUF" : "output:1" , 10 | "PRE_PADDR_SUF" : "input:32" , 11 | "PRE_PENABL_SUF" : "input:1" , 12 | "PRE_PDAT_SUF" : "input:32" 13 | }, 14 | "my_spi" : { 15 | "ss_o" : "input: 1" , 16 | "miso_i" : "output: 1" , 17 | "sck_o" : "input: 1" , 18 | "mosi_o" : "input: 1" 19 | } 20 | }, 21 | 22 | "ports" : { 23 | "PRE_PSLVERR_SUF" : "input:1" , 24 | "PRE_PSELX_SUF" : "input:1" , 25 | "PRE_PRDATA_SUF" : "input:32" , 26 | "PRE_PREADY_SUF" : "output:1" , 27 | "PRE_PADDR_SUF" : "input:32" , 28 | "PRE_PENABL_SUF" : "input:1" , 29 | "PRE_PDAT_SUF" : "input:32" , 30 | 31 | "ss_o" : "input: 1" , 32 | "miso_i" : "output: 1" , 33 | "sck_o" : "input: 1" , 34 | "mosi_o" : "input: 1" , 35 | "reset" : "input : 1" , 36 | "clk" : "input : 1" 37 | 38 | } 39 | 40 | } 41 | -------------------------------------------------------------------------------- /test/cfg/simple_spi.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | librecores.org 4 | ip 5 | simple_spi 6 | 1.0 7 | 8 | 9 | wb 10 | 11 | 12 | 13 | false 14 | 15 | 16 | 17 | adr_o 18 | 19 | 2 20 | 0 21 | 22 | 23 | 24 | adr_i 25 | 26 | 2 27 | 0 28 | 29 | 30 | 31 | 32 | 33 | we_o 34 | 35 | 0 36 | 0 37 | 38 | 39 | 40 | we_i 41 | 42 | 0 43 | 0 44 | 45 | 46 | 47 | 48 | 49 | cyc_o 50 | 51 | 0 52 | 0 53 | 54 | 55 | 56 | cyc_i 57 | 58 | 0 59 | 0 60 | 61 | 62 | 63 | 64 | 65 | stb_o 66 | 67 | 0 68 | 0 69 | 70 | 71 | 72 | stb_i 73 | 74 | 0 75 | 0 76 | 77 | 78 | 79 | 80 | 81 | dat_i 82 | 83 | 7 84 | 0 85 | 86 | 87 | 88 | dat_o 89 | 90 | 7 91 | 0 92 | 93 | 94 | 95 | 96 | 97 | ack_i 98 | 99 | 0 100 | 0 101 | 102 | 103 | 104 | ack_o 105 | 106 | 0 107 | 0 108 | 109 | 110 | 111 | 112 | 113 | dat_o 114 | 115 | 7 116 | 0 117 | 118 | 119 | 120 | dat_i 121 | 122 | 7 123 | 0 124 | 125 | 126 | 127 | 128 | 8 129 | little 130 | 131 | 132 | spi 133 | 134 | 135 | 136 | false 137 | 138 | 139 | 140 | sck 141 | 142 | 0 143 | 0 144 | 145 | 146 | 147 | sck_o 148 | 149 | 0 150 | 0 151 | 152 | 153 | 154 | 155 | 156 | miso 157 | 158 | 0 159 | 0 160 | 161 | 162 | 163 | miso_i 164 | 165 | 0 166 | 0 167 | 168 | 169 | 170 | 171 | 172 | mosi 173 | 174 | 0 175 | 0 176 | 177 | 178 | 179 | mosi_o 180 | 181 | 0 182 | 0 183 | 184 | 185 | 186 | 187 | 188 | cs 189 | 190 | 0 191 | 0 192 | 193 | 194 | 195 | ss_o 196 | 197 | 0 198 | 0 199 | 200 | 201 | 202 | 203 | 8 204 | little 205 | 206 | 207 | wb_sys 208 | 209 | 210 | 211 | false 212 | 213 | 214 | 215 | clk 216 | 217 | 0 218 | 0 219 | 220 | 221 | 222 | clk_i 223 | 224 | 0 225 | 0 226 | 227 | 228 | 229 | 230 | 231 | rst 232 | 233 | 0 234 | 0 235 | 236 | 237 | 238 | rst_i 239 | 240 | 0 241 | 0 242 | 243 | 244 | 245 | 246 | 8 247 | little 248 | 249 | 250 | 251 | 252 | 253 | flat 254 | verilog:Kactus2: 255 | verilog 256 | simple_spi_top 257 | 258 | 259 | flat 260 | 261 | 262 | 263 | 264 | 265 | 266 | clk_i 267 | clock 268 | 269 | in 270 | 271 | 0 272 | 0 273 | 274 | 275 | 276 | wire 277 | 278 | flat 279 | 280 | 281 | 282 | 283 | 284 | rst_i 285 | reset (asynchronous active low) 286 | 287 | in 288 | 289 | 0 290 | 0 291 | 292 | 293 | 294 | wire 295 | 296 | flat 297 | 298 | 299 | 300 | 301 | 302 | cyc_i 303 | cycle 304 | 305 | in 306 | 307 | 0 308 | 0 309 | 310 | 311 | 312 | wire 313 | 314 | flat 315 | 316 | 317 | 318 | 319 | 320 | stb_i 321 | strobe 322 | 323 | in 324 | 325 | 0 326 | 0 327 | 328 | 329 | 330 | wire 331 | 332 | flat 333 | 334 | 335 | 336 | 337 | 338 | adr_i 339 | address 340 | 341 | in 342 | 343 | 2 344 | 0 345 | 346 | 347 | 348 | wire 349 | 350 | flat 351 | 352 | 353 | 354 | 355 | 356 | we_i 357 | write enable 358 | 359 | in 360 | 361 | 0 362 | 0 363 | 364 | 365 | 366 | wire 367 | 368 | flat 369 | 370 | 371 | 372 | 373 | 374 | dat_i 375 | data input 376 | 377 | in 378 | 379 | 7 380 | 0 381 | 382 | 383 | 384 | wire 385 | 386 | flat 387 | 388 | 389 | 390 | 391 | 392 | dat_o 393 | data output 394 | 395 | out 396 | 397 | 7 398 | 0 399 | 400 | 401 | 402 | reg 403 | 404 | flat 405 | 406 | 407 | 408 | 409 | 410 | ack_o 411 | normal bus termination 412 | 413 | out 414 | 415 | 0 416 | 0 417 | 418 | 419 | 420 | reg 421 | 422 | flat 423 | 424 | 425 | 426 | 427 | 428 | inta_o 429 | interrupt output 430 | 431 | out 432 | 433 | 0 434 | 0 435 | 436 | 437 | 438 | reg 439 | 440 | flat 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | sck_o 450 | serial clock output 451 | 452 | out 453 | 454 | 0 455 | 0 456 | 457 | 458 | 459 | reg 460 | 461 | flat 462 | 463 | 464 | 465 | 466 | 467 | mosi_o 468 | MasterOut SlaveIN 469 | 470 | out 471 | 472 | 0 473 | 0 474 | 475 | 476 | 477 | wire 478 | 479 | flat 480 | 481 | 482 | 483 | 484 | 485 | miso_i 486 | MasterIn SlaveOut 487 | 488 | in 489 | 490 | 0 491 | 0 492 | 493 | 494 | 495 | wire 496 | 497 | flat 498 | 499 | 500 | 501 | 502 | 503 | ss_o 504 | 505 | out 506 | 507 | 508 | 509 | 510 | 511 | 512 | 513 | Global 514 | HW 515 | Mutable 516 | 517 | olof.kindgren 518 | 519 | 520 | 521 | -------------------------------------------------------------------------------- /test/incr/NV_NVDLA_CMAC_CORE_MAC_mul.v: -------------------------------------------------------------------------------- 1 | // ================================================================ 2 | // NVDLA Open Source Project 3 | // 4 | // Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the 5 | // NVDLA Open Hardware License; Check "LICENSE" which comes with 6 | // this distribution for more information. 7 | // ================================================================ 8 | 9 | // File Name: NV_NVDLA_CMAC_CORE_MAC_mul.v 10 | 11 | module NV_NVDLA_CMAC_CORE_MAC_mul ( 12 | nvdla_core_clk //|< i 13 | ,nvdla_core_rstn //|< i 14 | ,cfg_is_fp16 //|< i 15 | ,cfg_is_int8 //|< i 16 | ,cfg_reg_en //|< i 17 | ,exp_sft //|< i 18 | ,op_a_dat //|< i 19 | ,op_a_nz //|< i 20 | ,op_a_pvld //|< i 21 | ,op_b_dat //|< i 22 | ,op_b_nz //|< i 23 | ,op_b_pvld //|< i 24 | ,res_a //|> o 25 | ,res_b //|> o 26 | ,res_tag //|> o 27 | ); 28 | 29 | input nvdla_core_clk; 30 | input nvdla_core_rstn; 31 | input cfg_is_fp16; 32 | input cfg_is_int8; 33 | input cfg_reg_en; 34 | input [3:0] exp_sft; 35 | input [15:0] op_a_dat; 36 | input [1:0] op_a_nz; 37 | input op_a_pvld; 38 | input [15:0] op_b_dat; 39 | input [1:0] op_b_nz; 40 | input op_b_pvld; 41 | output [31:0] res_a; 42 | output [31:0] res_b; 43 | output [7:0] res_tag; 44 | wire [23:0] pp_out_l0n0_0; 45 | wire [23:0] pp_out_l0n0_1; 46 | wire [23:0] pp_out_l0n1_0; 47 | wire [23:0] pp_out_l0n1_1; 48 | wire [31:0] pp_out_l1n0_0; 49 | wire [31:0] pp_out_l1n0_1; 50 | wire [16:0] sel_data_0; 51 | wire [16:0] sel_data_1; 52 | wire [16:0] sel_data_2; 53 | wire [16:0] sel_data_3; 54 | wire [16:0] sel_data_4; 55 | wire [16:0] sel_data_5; 56 | wire [16:0] sel_data_6; 57 | wire [16:0] sel_data_7; 58 | wire sel_inv_0; 59 | wire sel_inv_1; 60 | wire sel_inv_2; 61 | wire sel_inv_3; 62 | wire sel_inv_4; 63 | wire sel_inv_5; 64 | wire sel_inv_6; 65 | wire sel_inv_7; 66 | reg [3:0] cfg_is_fp16_d1; 67 | reg cfg_is_int8_d1; 68 | reg [2:0] code_0; 69 | reg [2:0] code_1; 70 | reg [2:0] code_2; 71 | reg [2:0] code_3; 72 | reg [2:0] code_4; 73 | reg [2:0] code_5; 74 | reg [2:0] code_6; 75 | reg [2:0] code_7; 76 | reg [8:0] code_hi; 77 | reg [8:0] code_lo; 78 | reg fp16_sign; 79 | reg [15:0] op_a_cur_dat; 80 | reg [15:0] op_b_cur_dat; 81 | reg [1:0] op_out_pvld; 82 | reg [31:0] pp_fp16_0_sft; 83 | reg [31:0] pp_fp16_1_sft; 84 | reg [119:0] pp_in_l0n0; 85 | reg [119:0] pp_in_l0n1; 86 | reg [127:0] pp_in_l1n0; 87 | reg [7:0] pp_sign_tag; 88 | reg [23:0] ppre_0; 89 | reg [23:0] ppre_1; 90 | reg [23:0] ppre_2; 91 | reg [23:0] ppre_3; 92 | reg [23:0] ppre_4; 93 | reg [23:0] ppre_5; 94 | reg [23:0] ppre_6; 95 | reg [23:0] ppre_7; 96 | reg [23:0] ppre_8; 97 | reg [23:0] ppre_9; 98 | reg [31:0] res_a; 99 | reg [31:0] res_a_gate; 100 | reg [31:0] res_a_ori; 101 | reg [31:0] res_b; 102 | reg [31:0] res_b_gate; 103 | reg [31:0] res_b_ori; 104 | reg [15:0] src_data_0; 105 | reg [15:0] src_data_1; 106 | 107 | // synoff nets 108 | 109 | // monitor nets 110 | 111 | // debug nets 112 | 113 | // tie high nets 114 | 115 | // tie low nets 116 | 117 | // no connect nets 118 | 119 | // not all bits used nets 120 | 121 | // todo nets 122 | 123 | 124 | //========================================================== 125 | // Config logic 126 | //========================================================== 127 | 128 | always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin 129 | if (!nvdla_core_rstn) begin 130 | cfg_is_int8_d1 <= 1'b0; 131 | end else begin 132 | if ((cfg_reg_en) == 1'b1) begin 133 | cfg_is_int8_d1 <= cfg_is_int8; 134 | // VCS coverage off 135 | end else if ((cfg_reg_en) == 1'b0) begin 136 | end else begin 137 | cfg_is_int8_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) 138 | // VCS coverage on 139 | end 140 | end 141 | end 142 | `ifdef SPYGLASS_ASSERT_ON 143 | `else 144 | // spyglass disable_block NoWidthInBasedNum-ML 145 | // spyglass disable_block STARC-2.10.3.2a 146 | // spyglass disable_block STARC05-2.1.3.1 147 | // spyglass disable_block STARC-2.1.4.6 148 | // spyglass disable_block W116 149 | // spyglass disable_block W154 150 | // spyglass disable_block W239 151 | // spyglass disable_block W362 152 | // spyglass disable_block WRN_58 153 | // spyglass disable_block WRN_61 154 | `endif // SPYGLASS_ASSERT_ON 155 | `ifdef ASSERT_ON 156 | `ifdef FV_ASSERT_ON 157 | `define ASSERT_RESET nvdla_core_rstn 158 | `else 159 | `ifdef SYNTHESIS 160 | `define ASSERT_RESET nvdla_core_rstn 161 | `else 162 | `ifdef ASSERT_OFF_RESET_IS_X 163 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) 164 | `else 165 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) 166 | `endif // ASSERT_OFF_RESET_IS_X 167 | `endif // SYNTHESIS 168 | `endif // FV_ASSERT_ON 169 | `ifndef SYNTHESIS 170 | // VCS coverage off 171 | nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML 172 | // VCS coverage on 173 | `endif 174 | `undef ASSERT_RESET 175 | `endif // ASSERT_ON 176 | `ifdef SPYGLASS_ASSERT_ON 177 | `else 178 | // spyglass enable_block NoWidthInBasedNum-ML 179 | // spyglass enable_block STARC-2.10.3.2a 180 | // spyglass enable_block STARC05-2.1.3.1 181 | // spyglass enable_block STARC-2.1.4.6 182 | // spyglass enable_block W116 183 | // spyglass enable_block W154 184 | // spyglass enable_block W239 185 | // spyglass enable_block W362 186 | // spyglass enable_block WRN_58 187 | // spyglass enable_block WRN_61 188 | `endif // SPYGLASS_ASSERT_ON 189 | always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin 190 | if (!nvdla_core_rstn) begin 191 | cfg_is_fp16_d1 <= {4{1'b0}}; 192 | end else begin 193 | if ((cfg_reg_en) == 1'b1) begin 194 | cfg_is_fp16_d1 <= {4{cfg_is_fp16}}; 195 | // VCS coverage off 196 | end else if ((cfg_reg_en) == 1'b0) begin 197 | end else begin 198 | cfg_is_fp16_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) 199 | // VCS coverage on 200 | end 201 | end 202 | end 203 | `ifdef SPYGLASS_ASSERT_ON 204 | `else 205 | // spyglass disable_block NoWidthInBasedNum-ML 206 | // spyglass disable_block STARC-2.10.3.2a 207 | // spyglass disable_block STARC05-2.1.3.1 208 | // spyglass disable_block STARC-2.1.4.6 209 | // spyglass disable_block W116 210 | // spyglass disable_block W154 211 | // spyglass disable_block W239 212 | // spyglass disable_block W362 213 | // spyglass disable_block WRN_58 214 | // spyglass disable_block WRN_61 215 | `endif // SPYGLASS_ASSERT_ON 216 | `ifdef ASSERT_ON 217 | `ifdef FV_ASSERT_ON 218 | `define ASSERT_RESET nvdla_core_rstn 219 | `else 220 | `ifdef SYNTHESIS 221 | `define ASSERT_RESET nvdla_core_rstn 222 | `else 223 | `ifdef ASSERT_OFF_RESET_IS_X 224 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) 225 | `else 226 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) 227 | `endif // ASSERT_OFF_RESET_IS_X 228 | `endif // SYNTHESIS 229 | `endif // FV_ASSERT_ON 230 | `ifndef SYNTHESIS 231 | // VCS coverage off 232 | nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML 233 | // VCS coverage on 234 | `endif 235 | `undef ASSERT_RESET 236 | `endif // ASSERT_ON 237 | `ifdef SPYGLASS_ASSERT_ON 238 | `else 239 | // spyglass enable_block NoWidthInBasedNum-ML 240 | // spyglass enable_block STARC-2.10.3.2a 241 | // spyglass enable_block STARC05-2.1.3.1 242 | // spyglass enable_block STARC-2.1.4.6 243 | // spyglass enable_block W116 244 | // spyglass enable_block W154 245 | // spyglass enable_block W239 246 | // spyglass enable_block W362 247 | // spyglass enable_block WRN_58 248 | // spyglass enable_block WRN_61 249 | `endif // SPYGLASS_ASSERT_ON 250 | 251 | //========================================================== 252 | // Control logic 253 | //========================================================== 254 | 255 | always @( 256 | op_a_pvld 257 | or op_b_pvld 258 | or op_a_nz 259 | or op_b_nz 260 | ) begin 261 | op_out_pvld[1] = op_a_pvld & op_b_pvld & op_a_nz[1] & op_b_nz[1]; 262 | op_out_pvld[0] = op_a_pvld & op_b_pvld & op_a_nz[0] & op_b_nz[0]; 263 | end 264 | 265 | always @( 266 | cfg_is_fp16_d1 267 | or op_a_dat 268 | or op_b_dat 269 | ) begin 270 | op_a_cur_dat = {(~cfg_is_fp16_d1[0] & op_a_dat[15]), op_a_dat[14:0]}; 271 | op_b_cur_dat = {(~cfg_is_fp16_d1[0] & op_b_dat[15]), op_b_dat[14:0]}; 272 | end 273 | 274 | `ifdef SPYGLASS_ASSERT_ON 275 | `else 276 | // spyglass disable_block NoWidthInBasedNum-ML 277 | // spyglass disable_block STARC-2.10.3.2a 278 | // spyglass disable_block STARC05-2.1.3.1 279 | // spyglass disable_block STARC-2.1.4.6 280 | // spyglass disable_block W116 281 | // spyglass disable_block W154 282 | // spyglass disable_block W239 283 | // spyglass disable_block W362 284 | // spyglass disable_block WRN_58 285 | // spyglass disable_block WRN_61 286 | `endif // SPYGLASS_ASSERT_ON 287 | `ifdef ASSERT_ON 288 | `ifdef FV_ASSERT_ON 289 | `define ASSERT_RESET nvdla_core_rstn 290 | `else 291 | `ifdef SYNTHESIS 292 | `define ASSERT_RESET nvdla_core_rstn 293 | `else 294 | `ifdef ASSERT_OFF_RESET_IS_X 295 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) 296 | `else 297 | `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) 298 | `endif // ASSERT_OFF_RESET_IS_X 299 | `endif // SYNTHESIS 300 | `endif // FV_ASSERT_ON 301 | `ifndef SYNTHESIS 302 | // VCS coverage off 303 | nv_assert_never #(0,0,"Error! op_out_pvld not match!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (~cfg_is_int8_d1 & (op_out_pvld[0] ^ op_out_pvld[1]))); // spyglass disable W504 SelfDeterminedExpr-ML 304 | // VCS coverage on 305 | `endif 306 | `undef ASSERT_RESET 307 | `endif // ASSERT_ON 308 | `ifdef SPYGLASS_ASSERT_ON 309 | `else 310 | // spyglass enable_block NoWidthInBasedNum-ML 311 | // spyglass enable_block STARC-2.10.3.2a 312 | // spyglass enable_block STARC05-2.1.3.1 313 | // spyglass enable_block STARC-2.1.4.6 314 | // spyglass enable_block W116 315 | // spyglass enable_block W154 316 | // spyglass enable_block W239 317 | // spyglass enable_block W362 318 | // spyglass enable_block WRN_58 319 | // spyglass enable_block WRN_61 320 | `endif // SPYGLASS_ASSERT_ON 321 | 322 | //========================================================== 323 | // Booth recoding and selection, radix-4 324 | //========================================================== 325 | 326 | always @( 327 | op_a_cur_dat 328 | ) begin 329 | code_lo = {op_a_cur_dat[7:0], 1'b0}; 330 | end 331 | 332 | always @( 333 | cfg_is_int8_d1 334 | or op_a_cur_dat 335 | ) begin 336 | code_hi = cfg_is_int8_d1 ? {op_a_cur_dat[15:8], 1'b0} : 337 | op_a_cur_dat[15:7]; 338 | end 339 | 340 | always @( 341 | code_lo 342 | ) begin 343 | code_0 = code_lo[2:0]; 344 | code_1 = code_lo[4:2]; 345 | code_2 = code_lo[6:4]; 346 | code_3 = code_lo[8:6]; 347 | end 348 | 349 | always @( 350 | code_hi 351 | ) begin 352 | code_4 = code_hi[2:0]; 353 | code_5 = code_hi[4:2]; 354 | code_6 = code_hi[6:4]; 355 | code_7 = code_hi[8:6]; 356 | end 357 | 358 | always @( 359 | cfg_is_int8_d1 360 | or op_b_cur_dat 361 | ) begin 362 | src_data_0 = cfg_is_int8_d1 ? {8'b0, op_b_cur_dat[7:0]} : op_b_cur_dat; 363 | src_data_1 = cfg_is_int8_d1 ? {8'b0, op_b_cur_dat[15:8]} : op_b_cur_dat; 364 | end 365 | 366 | always @( 367 | cfg_is_fp16_d1 368 | or op_a_dat 369 | or op_b_dat 370 | ) begin 371 | fp16_sign = (cfg_is_fp16_d1[1] & (op_a_dat[15] ^ op_b_dat[15])); 372 | end 373 | 374 | 375 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_0 ( 376 | .code (code_0[2:0]) //|< r 377 | ,.is_8bit (cfg_is_int8_d1) //|< r 378 | ,.sign (fp16_sign) //|< r 379 | ,.src_data (src_data_0[15:0]) //|< r 380 | ,.out_data (sel_data_0[16:0]) //|> w 381 | ,.out_inv (sel_inv_0) //|> w 382 | ); 383 | 384 | 385 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_1 ( 386 | .code (code_1[2:0]) //|< r 387 | ,.is_8bit (cfg_is_int8_d1) //|< r 388 | ,.sign (fp16_sign) //|< r 389 | ,.src_data (src_data_0[15:0]) //|< r 390 | ,.out_data (sel_data_1[16:0]) //|> w 391 | ,.out_inv (sel_inv_1) //|> w 392 | ); 393 | 394 | 395 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_2 ( 396 | .code (code_2[2:0]) //|< r 397 | ,.is_8bit (cfg_is_int8_d1) //|< r 398 | ,.sign (fp16_sign) //|< r 399 | ,.src_data (src_data_0[15:0]) //|< r 400 | ,.out_data (sel_data_2[16:0]) //|> w 401 | ,.out_inv (sel_inv_2) //|> w 402 | ); 403 | 404 | 405 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_3 ( 406 | .code (code_3[2:0]) //|< r 407 | ,.is_8bit (cfg_is_int8_d1) //|< r 408 | ,.sign (fp16_sign) //|< r 409 | ,.src_data (src_data_0[15:0]) //|< r 410 | ,.out_data (sel_data_3[16:0]) //|> w 411 | ,.out_inv (sel_inv_3) //|> w 412 | ); 413 | 414 | 415 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_4 ( 416 | .code (code_4[2:0]) //|< r 417 | ,.is_8bit (cfg_is_int8_d1) //|< r 418 | ,.sign (fp16_sign) //|< r 419 | ,.src_data (src_data_1[15:0]) //|< r 420 | ,.out_data (sel_data_4[16:0]) //|> w 421 | ,.out_inv (sel_inv_4) //|> w 422 | ); 423 | 424 | 425 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_5 ( 426 | .code (code_5[2:0]) //|< r 427 | ,.is_8bit (cfg_is_int8_d1) //|< r 428 | ,.sign (fp16_sign) //|< r 429 | ,.src_data (src_data_1[15:0]) //|< r 430 | ,.out_data (sel_data_5[16:0]) //|> w 431 | ,.out_inv (sel_inv_5) //|> w 432 | ); 433 | 434 | 435 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_6 ( 436 | .code (code_6[2:0]) //|< r 437 | ,.is_8bit (cfg_is_int8_d1) //|< r 438 | ,.sign (fp16_sign) //|< r 439 | ,.src_data (src_data_1[15:0]) //|< r 440 | ,.out_data (sel_data_6[16:0]) //|> w 441 | ,.out_inv (sel_inv_6) //|> w 442 | ); 443 | 444 | 445 | NV_NVDLA_CMAC_CORE_MAC_booth u_booth_7 ( 446 | .code (code_7[2:0]) //|< r 447 | ,.is_8bit (cfg_is_int8_d1) //|< r 448 | ,.sign (fp16_sign) //|< r 449 | ,.src_data (src_data_1[15:0]) //|< r 450 | ,.out_data (sel_data_7[16:0]) //|> w 451 | ,.out_inv (sel_inv_7) //|> w 452 | ); 453 | 454 | 455 | //========================================================== 456 | // CSA tree input 457 | //========================================================== 458 | 459 | always @( 460 | sel_data_0 461 | or sel_data_1 462 | or sel_inv_0 463 | or sel_data_2 464 | or sel_inv_1 465 | or sel_data_3 466 | or sel_inv_2 467 | or sel_inv_3 468 | ) begin 469 | ppre_0 = {7'b0, sel_data_0}; 470 | ppre_1 = {5'b0, sel_data_1, 1'b0, sel_inv_0}; 471 | ppre_2 = {3'b0, sel_data_2, 1'b0, sel_inv_1, 2'b0}; 472 | ppre_3 = {1'b0, sel_data_3, 1'b0, sel_inv_2, 4'b0}; 473 | ppre_4 = {17'b0, sel_inv_3, 6'b0}; 474 | end 475 | 476 | always @( 477 | sel_data_4 478 | or sel_data_5 479 | or sel_inv_4 480 | or sel_data_6 481 | or sel_inv_5 482 | or sel_data_7 483 | or sel_inv_6 484 | or sel_inv_7 485 | ) begin 486 | ppre_5 = {7'b0, sel_data_4}; 487 | ppre_6 = {5'b0, sel_data_5, 1'b0, sel_inv_4}; 488 | ppre_7 = {3'b0, sel_data_6, 1'b0, sel_inv_5, 2'b0}; 489 | ppre_8 = {1'b0, sel_data_7, 1'b0, sel_inv_6, 4'b0}; 490 | ppre_9 = {17'b0, sel_inv_7, 6'b0}; 491 | end 492 | 493 | //========================================================== 494 | // CSA tree level 1 495 | //========================================================== 496 | 497 | always @( 498 | ppre_4 499 | or ppre_3 500 | or ppre_2 501 | or ppre_1 502 | or ppre_0 503 | ) begin 504 | pp_in_l0n0 = {ppre_4, ppre_3, ppre_2, ppre_1, ppre_0}; 505 | end 506 | 507 | always @( 508 | ppre_9 509 | or ppre_8 510 | or ppre_7 511 | or ppre_6 512 | or ppre_5 513 | ) begin 514 | pp_in_l0n1 = {ppre_9, ppre_8, ppre_7, ppre_6, ppre_5}; 515 | end 516 | 517 | 518 | `ifdef DESIGNWARE_NOEXIST 519 | NV_DW02_tree #(5, 24) u_tree_l0n0 ( 520 | .INPUT (pp_in_l0n0[119:0]) //|< r 521 | ,.OUT0 (pp_out_l0n0_0[23:0]) //|> w 522 | ,.OUT1 (pp_out_l0n0_1[23:0]) //|> w 523 | ); 524 | `else 525 | DW02_tree #(5, 24) u_tree_l0n0 ( 526 | .INPUT (pp_in_l0n0[119:0]) //|< r 527 | ,.OUT0 (pp_out_l0n0_0[23:0]) //|> w 528 | ,.OUT1 (pp_out_l0n0_1[23:0]) //|> w 529 | ); 530 | `endif 531 | 532 | 533 | `ifdef DESIGNWARE_NOEXIST 534 | NV_DW02_tree #(5, 24) u_tree_l0n1 ( 535 | .INPUT (pp_in_l0n1[119:0]) //|< r 536 | ,.OUT0 (pp_out_l0n1_0[23:0]) //|> w 537 | ,.OUT1 (pp_out_l0n1_1[23:0]) //|> w 538 | ); 539 | `else 540 | DW02_tree #(5, 24) u_tree_l0n1 ( 541 | .INPUT (pp_in_l0n1[119:0]) //|< r 542 | ,.OUT0 (pp_out_l0n1_0[23:0]) //|> w 543 | ,.OUT1 (pp_out_l0n1_1[23:0]) //|> w 544 | ); 545 | `endif 546 | 547 | 548 | //========================================================== 549 | // CSA tree level 2 550 | //========================================================== 551 | always @( 552 | cfg_is_int8_d1 553 | or pp_out_l0n1_1 554 | or pp_out_l0n1_0 555 | or pp_out_l0n0_1 556 | or pp_out_l0n0_0 557 | ) begin 558 | pp_in_l1n0 = cfg_is_int8_d1 ? 128'b0 : 559 | {{pp_out_l0n1_1, 8'b0}, 560 | {pp_out_l0n1_0, 8'b0}, 561 | {8'b0, pp_out_l0n0_1}, 562 | {8'b0, pp_out_l0n0_0}}; 563 | end 564 | 565 | `ifdef DESIGNWARE_NOEXIST 566 | NV_DW02_tree #(4, 32) u_tree_l1n0 ( 567 | .INPUT (pp_in_l1n0[127:0]) //|< r 568 | ,.OUT0 (pp_out_l1n0_0[31:0]) //|> w 569 | ,.OUT1 (pp_out_l1n0_1[31:0]) //|> w 570 | ); 571 | `else 572 | DW02_tree #(4, 32) u_tree_l1n0 ( 573 | .INPUT (pp_in_l1n0[127:0]) //|< r 574 | ,.OUT0 (pp_out_l1n0_0[31:0]) //|> w 575 | ,.OUT1 (pp_out_l1n0_1[31:0]) //|> w 576 | ); 577 | `endif 578 | 579 | //========================================================== 580 | // Shift logic for float-point 581 | //========================================================== 582 | 583 | always @( 584 | cfg_is_fp16_d1 585 | or exp_sft 586 | or pp_out_l1n0_0 587 | ) begin 588 | pp_fp16_0_sft[31:0] = (~cfg_is_fp16_d1[2] | exp_sft[3]) ? 32'b0 : 589 | (pp_out_l1n0_0 >> {exp_sft[2:0], 2'b0}); 590 | end 591 | 592 | always @( 593 | cfg_is_fp16_d1 594 | or exp_sft 595 | or pp_out_l1n0_1 596 | ) begin 597 | pp_fp16_1_sft[31:0] = (~cfg_is_fp16_d1[2] | exp_sft[3]) ? 32'b0 : 598 | (pp_out_l1n0_1 >> {exp_sft[2:0], 2'b0}); 599 | end 600 | 601 | //sign compensation 602 | always @( 603 | op_out_pvld 604 | or exp_sft 605 | ) begin 606 | pp_sign_tag = (~op_out_pvld[1] | exp_sft[3]) ? 8'h0 : 607 | (8'hf0 >> exp_sft[2:0]); 608 | end 609 | 610 | //========================================================== 611 | // Output select 612 | //========================================================== 613 | 614 | 615 | always @( 616 | cfg_is_int8_d1 617 | or cfg_is_fp16_d1 618 | ) begin 619 | res_a_gate = cfg_is_int8_d1 ? 32'h55005500 : 620 | ~cfg_is_fp16_d1[3] ? 32'h55550000 : 621 | 32'h0; 622 | res_b_gate = 32'h0; 623 | end 624 | 625 | always @( 626 | cfg_is_fp16_d1 627 | or pp_fp16_0_sft 628 | or cfg_is_int8_d1 629 | or pp_out_l0n1_0 630 | or pp_out_l0n0_0 631 | or pp_out_l1n0_0 632 | ) begin 633 | res_a_ori = cfg_is_fp16_d1[2] ? pp_fp16_0_sft : 634 | cfg_is_int8_d1 ? {pp_out_l0n1_0[15:0], pp_out_l0n0_0[15:0]} : 635 | pp_out_l1n0_0; 636 | end 637 | 638 | always @( 639 | cfg_is_fp16_d1 640 | or pp_fp16_1_sft 641 | or cfg_is_int8_d1 642 | or pp_out_l0n1_1 643 | or pp_out_l0n0_1 644 | or pp_out_l1n0_1 645 | ) begin 646 | res_b_ori = cfg_is_fp16_d1[2] ? pp_fp16_1_sft : 647 | cfg_is_int8_d1 ? {pp_out_l0n1_1[15:0], pp_out_l0n0_1[15:0]} : 648 | pp_out_l1n0_1; 649 | end 650 | 651 | always @( 652 | op_out_pvld 653 | or res_a_ori 654 | or res_a_gate 655 | ) begin 656 | res_a[31:16] = op_out_pvld[1] ? res_a_ori[31:16] : res_a_gate[31:16]; 657 | res_a[15:0] = op_out_pvld[0] ? res_a_ori[15:0] : res_a_gate[15:0]; 658 | end 659 | 660 | always @( 661 | op_out_pvld 662 | or res_b_ori 663 | or res_b_gate 664 | ) begin 665 | res_b[31:16] = op_out_pvld[1] ? res_b_ori[31:16] : res_b_gate[31:16]; 666 | res_b[15:0] = op_out_pvld[0] ? res_b_ori[15:0] : res_b_gate[15:0]; 667 | end 668 | 669 | assign res_tag = pp_sign_tag; 670 | 671 | endmodule // NV_NVDLA_CMAC_CORE_MAC_mul 672 | 673 | //========================================================== 674 | // 675 | // Sub unit for NV_NVDLA_CMAC_CORE_MAC_mul 676 | // Booth's recoder and Booth's selector with inversed sign flag 677 | // 678 | //========================================================== 679 | 680 | module NV_NVDLA_CMAC_CORE_MAC_booth ( 681 | code 682 | ,is_8bit 683 | ,sign 684 | ,src_data 685 | ,out_data 686 | ,out_inv 687 | ); 688 | 689 | input [2:0] code; 690 | input is_8bit; 691 | input sign; 692 | input [15:0] src_data; 693 | output [16:0] out_data; 694 | output out_inv; 695 | reg [2:0] in_code; 696 | reg [16:0] out_data; 697 | reg out_inv; 698 | 699 | 700 | always @( 701 | sign 702 | or code 703 | ) begin 704 | in_code = {3{sign}} ^ code; 705 | end 706 | 707 | always @( 708 | is_8bit 709 | or in_code 710 | or src_data 711 | ) begin 712 | case({is_8bit, in_code}) 713 | ///////// for 16bit ///////// 714 | // +/- 0*src_data 715 | 4'b0000, 716 | 4'b0111: 717 | begin 718 | out_data = 17'h10000; 719 | out_inv = 1'b0; 720 | end 721 | 722 | // + 1*src_data 723 | 4'b0001, 724 | 4'b0010: 725 | begin 726 | out_data = {~src_data[15], src_data}; 727 | out_inv = 1'b0; 728 | end 729 | 730 | // - 1*src_data 731 | 4'b0101, 732 | 4'b0110: 733 | begin 734 | out_data = {src_data[15], ~src_data}; 735 | out_inv = 1'b1; 736 | end 737 | 738 | // + 2*src_data 739 | 4'b0011: 740 | begin 741 | out_data = {~src_data[15], src_data[14:0], 1'b0}; 742 | out_inv = 1'b0; 743 | end 744 | 745 | // - 2*src_data 746 | 4'b0100: 747 | begin 748 | out_data = {src_data[15], ~src_data[14:0], 1'b1}; 749 | out_inv = 1'b1; 750 | end 751 | 752 | ///////// for 8bit ///////// 753 | // +/- 0*src_data 754 | 4'b1000, 755 | 4'b1111: 756 | begin 757 | out_data = 17'h100; 758 | out_inv = 1'b0; 759 | end 760 | 761 | // + 1*src_data 762 | 4'b1001, 763 | 4'b1010: 764 | begin 765 | out_data = {8'b0, ~src_data[7], src_data[7:0]}; 766 | out_inv = 1'b0; 767 | end 768 | 769 | // - 1*src_data 770 | 4'b1101, 771 | 4'b1110: 772 | begin 773 | out_data = {8'b0, src_data[7], ~src_data[7:0]}; 774 | out_inv = 1'b1; 775 | end 776 | 777 | // + 2*src_data 778 | 4'b1011: 779 | begin 780 | out_data = {8'b0, ~src_data[7], src_data[6:0], 1'b0}; 781 | out_inv = 1'b0; 782 | end 783 | 784 | // - 2*src_data 785 | 4'b1100: 786 | begin 787 | out_data = {8'b0, src_data[7], ~src_data[6:0], 1'b1}; 788 | out_inv = 1'b1; 789 | end 790 | default: 791 | begin 792 | out_data = 17'h10000; 793 | out_inv = 1'b0; 794 | end 795 | endcase 796 | end 797 | 798 | endmodule // NV_NVDLA_CMAC_CORE_MAC_booth 799 | 800 | -------------------------------------------------------------------------------- /test/incr/apb_test.v: -------------------------------------------------------------------------------- 1 | // ===================================================== 2 | // === APB register module generated by RegGen === 3 | // === Please do NOT change manually === 4 | // ===================================================== 5 | 6 | module test_sys_ctrl ( 7 | input sys_ctrl_pclk_test, 8 | input sys_ctrl_presetn_test, 9 | input sys_ctrl_psel_test, 10 | input sys_ctrl_penable_test, 11 | input sys_ctrl_pwrite_test, 12 | input [31:0] paddr_test, 13 | input [31:0] pwdata_test, 14 | output reg [31:0] prdata_test, 15 | output reg pready_test, 16 | output reg pslverr_test 17 | 18 | // field "pdc_use_arm_ctrl" of reg_sys_ctrl0 : 19 | ,output reg[0:0] sys_ctrl0_pdc_use_arm_ctrl 20 | // field "l2c_strip_mode" of reg_sys_ctrl0 : 21 | ,output reg[2:0] sys_ctrl0_l2c_strip_mode 22 | // field "smmu_mmusid" of reg_sys_ctrl0 : 23 | ,output reg[4:0] sys_ctrl0_smmu_mmusid 24 | // field "mem_repair_en" of reg_sys_ctrl0 : 25 | ,output reg[0:0] sys_ctrl0_mem_repair_en 26 | // field "mem_repair_done" of reg_sys_ctrl0 : 27 | ,output reg[6:0] sys_ctrl0_mem_repair_done 28 | // field "test_field0" of reg_test_reg : 29 | ,output reg[3:0] test_reg_test_field0 30 | // field "test_filed1" of reg_test_reg : 31 | ,output reg[1:0] test_reg_test_filed1 32 | ); 33 | 34 | localparam NULLRESP = 1'b0; 35 | localparam DVA = 1'b0; 36 | localparam FAIL = 1'b1; 37 | localparam ERR = 1'b1: 38 | 39 | //Protocol management 40 | reg ready, error; 41 | reg [1:0] state, nstate; 42 | reg [31:0] rdata_sel: 43 | 44 | localparam RESET = 2'b00, IDLE = 2'b01, TRANSACTION = 2'b10, NOTREADY = 2'b11; 45 | 46 | always @(*) begin 47 | nstate = state; 48 | case (state) 49 | //transition when reset is no more active 50 | RESET : nstate = IDLE; 51 | //when an access starts 52 | IDLE : if psel !penable)nstate TRANSACTION: 53 | //if ready then the APB access completes in 2 cycles 54 | TRANSACTION : begin if (pready | error | !psel |!penable) nstate =IDLE; else nstate = NOTREADY; end 55 | //data is not ready,APB access is extended 56 | NOTREADY:if (pready !psel !penable) nstate = IDLE; 57 | endcase 58 | end 59 | 60 | always @(negedge presetn or posedge pclk) begin 61 | if (!presetn) 62 | state <= RESET; 63 | else 64 | state <=nstate; 65 | end 66 | 67 | // 68 | // Protocol specific assignment to inside signals do not do something internally if the cmd is not valid 69 | // 70 | wire [31:0] addr, paddr[31:0]; 71 | wire [31:0] pwdata[31:0]; 72 | wire wen = pwrite & (state =TRANSACTION) & psel & penable; 73 | 74 | // write byte enable for each reg 75 | wire [5-1:0] wen_sys_ctrl0 = wen & (addr[31:0] == 00000010) ? {5{1'b1}} : {5{1'b0}}; 76 | wire [2-1:0] wen_test_reg = wen & (addr[31:0] == 0000001c) ? {2{1'b1}} : {2{1'b0}}; 77 | 78 | // Reg: sys_ctrl0 79 | // Field: pdc_use_arm_ctrl 80 | // Type: RW 81 | // Reset: 0 82 | always @(negedge preset or posedge pclk) begin 83 | if (!preset) begin 84 | sys_ctrl0_pdc_use_arm_ctrl <= 1'h0; 85 | end begin 86 | if ( wen_sys_ctrl0[0] ) begin 87 | sys_ctrl0_pdc_use_arm_ctrl[1-1:0] <= pwdata[0:0]; 88 | end 89 | end 90 | end 91 | 92 | 93 | // Reg: sys_ctrl0 94 | // Field: l2c_strip_mode 95 | // Type: RW 96 | // Reset: 0 97 | always @(negedge preset or posedge pclk) begin 98 | if (!preset) begin 99 | sys_ctrl0_l2c_strip_mode <= 3'h0; 100 | end begin 101 | if ( wen_sys_ctrl0[1] ) begin 102 | sys_ctrl0_l2c_strip_mode[3-1:0] <= pwdata[3:1]; 103 | end 104 | end 105 | end 106 | 107 | 108 | // Reg: sys_ctrl0 109 | // Field: smmu_mmusid 110 | // Type: RW 111 | // Reset: 3 112 | always @(negedge preset or posedge pclk) begin 113 | if (!preset) begin 114 | sys_ctrl0_smmu_mmusid <= 5'h3; 115 | end begin 116 | if ( wen_sys_ctrl0[2] ) begin 117 | sys_ctrl0_smmu_mmusid[5-1:0] <= pwdata[8:4]; 118 | end 119 | end 120 | end 121 | 122 | 123 | // Reg: sys_ctrl0 124 | // Field: mem_repair_en 125 | // Type: RW 126 | // Reset: 5 127 | always @(negedge preset or posedge pclk) begin 128 | if (!preset) begin 129 | sys_ctrl0_mem_repair_en <= 1'h5; 130 | end begin 131 | if ( wen_sys_ctrl0[3] ) begin 132 | sys_ctrl0_mem_repair_en[1-1:0] <= pwdata[9:9]; 133 | end 134 | end 135 | end 136 | 137 | 138 | // Reg: sys_ctrl0 139 | // Field: mem_repair_done 140 | // Type: RO 141 | // Reset: 7 142 | always @(negedge preset or posedge pclk) begin 143 | if (!preset) begin 144 | sys_ctrl0_mem_repair_done <= 7'h7; 145 | end begin 146 | if ( wen_sys_ctrl0[4] ) begin 147 | sys_ctrl0_mem_repair_done <= sys_ctrl0_mem_repair_done; 148 | $display("%m @%t: Error writing Read-Only field of sys_ctrl0_mem_repair_done !"); 149 | end 150 | end 151 | end 152 | 153 | 154 | // Reg: test_reg 155 | // Field: test_field0 156 | // Type: RW 157 | // Reset: 0 158 | always @(negedge preset or posedge pclk) begin 159 | if (!preset) begin 160 | test_reg_test_field0 <= 4'h0; 161 | end begin 162 | if ( wen_test_reg[0] ) begin 163 | test_reg_test_field0[4-1:0] <= pwdata[3:0]; 164 | end 165 | end 166 | end 167 | 168 | 169 | // Reg: test_reg 170 | // Field: test_filed1 171 | // Type: WO 172 | // Reset: 3 173 | always @(negedge preset or posedge pclk) begin 174 | if (!preset) begin 175 | test_reg_test_filed1 <= 2'h3; 176 | end begin 177 | if ( wen_test_reg[1] ) begin 178 | test_reg_test_filed1[2-1:0] <= pwdata[5:4]; 179 | end 180 | end 181 | end 182 | 183 | always @(*) begin 184 | rdata_sel = 32'h00000000; 185 | if (!pwrite & psel ) begin 186 | case (addr) 187 | 32'h00000010: begin 188 | rdata_sel[0:0] = sys_ctrl0_pdc_use_arm_ctrl[0:0]; //Control if use arm ctrl-seq HIGH enable 189 | rdata_sel[3:1] = sys_ctrl0_l2c_strip_mode[2:0]; //Control L2 cache stripping mode HIGH enable 190 | rdata_sel[8:4] = sys_ctrl0_smmu_mmusid[4:0]; // 191 | rdata_sel[9:9] = sys_ctrl0_mem_repair_en[0:0]; // 192 | rdata_sel[16:10] = sys_ctrl0_mem_repair_done[6:0]; // 193 | end 194 | 32'h0000001c: begin 195 | rdata_sel[3:0] = test_reg_test_field0[3:0]; //This test comments 196 | rdata_sel[5:4] = 1'hxxxxxxxx; //X out for WriteOnly field: test_reg_test_filed1[1:0]; // 197 | end 198 | default: begin 199 | rdata_sel = 32'h00000000; 200 | end 201 | endcase 202 | end 203 | end 204 | 205 | endmodule 206 | -------------------------------------------------------------------------------- /test/incr/test_sys_ctrl_apb_regs.v: -------------------------------------------------------------------------------- 1 | // ===================================================== 2 | // === APB register module generated by RegGen === 3 | // === Please do NOT change manually === 4 | // ===================================================== 5 | 6 | module test_sys_ctrl ( 7 | input pclk, 8 | input presetn, 9 | input psel, 10 | input penable, 11 | input pwrite, 12 | input [31:0] paddr, 13 | input [31:0] pwdata, 14 | output reg [31:0] prdata, 15 | output reg pready, 16 | output reg pslverr 17 | 18 | // field "pdc_use_arm_ctrl" of reg_sys_ctrl0 : 19 | ,output reg[0:0] sys_ctrl0_pdc_use_arm_ctrl 20 | // field "l2c_strip_mode" of reg_sys_ctrl0 : 21 | ,output reg[2:0] sys_ctrl0_l2c_strip_mode 22 | // field "smmu_mmusid" of reg_sys_ctrl0 : 23 | ,output reg[4:0] sys_ctrl0_smmu_mmusid 24 | // field "mem_repair_en" of reg_sys_ctrl0 : 25 | ,output reg[0:0] sys_ctrl0_mem_repair_en 26 | // field "mem_repair_done" of reg_sys_ctrl0 : 27 | ,output reg[6:0] sys_ctrl0_mem_repair_done 28 | // field "test_field0" of reg_test_reg : 29 | ,output reg[3:0] test_reg_test_field0 30 | // field "test_filed1" of reg_test_reg : 31 | ,output reg[1:0] test_reg_test_filed1 32 | ); 33 | 34 | localparam NULLRESP = 1'b0; 35 | localparam DVA = 1'b0; 36 | localparam FAIL = 1'b1; 37 | localparam ERR = 1'b1: 38 | 39 | //Protocol management 40 | reg ready, error; 41 | reg [1:0] state, nstate; 42 | reg [31:0] rdata_sel: 43 | 44 | localparam RESET = 2'b00, IDLE = 2'b01, TRANSACTION = 2'b10, NOTREADY = 2'b11; 45 | 46 | always @(*) begin 47 | nstate = state; 48 | case (state) 49 | //transition when reset is no more active 50 | RESET : nstate = IDLE; 51 | //when an access starts 52 | IDLE : if psel !penable)nstate TRANSACTION: 53 | //if ready then the APB access completes in 2 cycles 54 | TRANSACTION : begin if (pready | error | !psel |!penable) nstate =IDLE; else nstate = NOTREADY; end 55 | //data is not ready,APB access is extended 56 | NOTREADY:if (pready !psel !penable) nstate = IDLE; 57 | endcase 58 | end 59 | 60 | always @(negedge presetn or posedge pclk) begin 61 | if (!presetn) 62 | state <= RESET; 63 | else 64 | state <=nstate; 65 | end 66 | 67 | // 68 | // Protocol specific assignment to inside signals do not do something internally if the cmd is not valid 69 | // 70 | wire [31:0] addr, paddr[31:0]; 71 | wire [31:0] pwdata[31:0]; 72 | wire wen = pwrite & (state =TRANSACTION) & psel & penable; 73 | 74 | // write byte enable for each reg 75 | wire [5-1:0] wen_sys_ctrl0 = wen & (addr[31:0] == 00000010) ? {5{1'b1}} : {5{1'b0}}; 76 | wire [2-1:0] wen_test_reg = wen & (addr[31:0] == 0000001c) ? {2{1'b1}} : {2{1'b0}}; 77 | 78 | // Reg: sys_ctrl0 79 | // Field: pdc_use_arm_ctrl 80 | // Type: RW 81 | // Reset: 0 82 | always @(negedge preset or posedge pclk) begin 83 | if (!preset) begin 84 | sys_ctrl0_pdc_use_arm_ctrl <= 1'h0; 85 | end begin 86 | if ( wen_sys_ctrl0[0] ) begin 87 | sys_ctrl0_pdc_use_arm_ctrl[1-1:0] <= pwdata[0:0]; 88 | end 89 | end 90 | end 91 | 92 | 93 | // Reg: sys_ctrl0 94 | // Field: l2c_strip_mode 95 | // Type: RW 96 | // Reset: 0 97 | always @(negedge preset or posedge pclk) begin 98 | if (!preset) begin 99 | sys_ctrl0_l2c_strip_mode <= 3'h0; 100 | end begin 101 | if ( wen_sys_ctrl0[1] ) begin 102 | sys_ctrl0_l2c_strip_mode[3-1:0] <= pwdata[3:1]; 103 | end 104 | end 105 | end 106 | 107 | 108 | // Reg: sys_ctrl0 109 | // Field: smmu_mmusid 110 | // Type: RW 111 | // Reset: 3 112 | always @(negedge preset or posedge pclk) begin 113 | if (!preset) begin 114 | sys_ctrl0_smmu_mmusid <= 5'h3; 115 | end begin 116 | if ( wen_sys_ctrl0[2] ) begin 117 | sys_ctrl0_smmu_mmusid[5-1:0] <= pwdata[8:4]; 118 | end 119 | end 120 | end 121 | 122 | 123 | // Reg: sys_ctrl0 124 | // Field: mem_repair_en 125 | // Type: RW 126 | // Reset: 5 127 | always @(negedge preset or posedge pclk) begin 128 | if (!preset) begin 129 | sys_ctrl0_mem_repair_en <= 1'h5; 130 | end begin 131 | if ( wen_sys_ctrl0[3] ) begin 132 | sys_ctrl0_mem_repair_en[1-1:0] <= pwdata[9:9]; 133 | end 134 | end 135 | end 136 | 137 | 138 | // Reg: sys_ctrl0 139 | // Field: mem_repair_done 140 | // Type: RO 141 | // Reset: 7 142 | always @(negedge preset or posedge pclk) begin 143 | if (!preset) begin 144 | sys_ctrl0_mem_repair_done <= 7'h7; 145 | end begin 146 | if ( wen_sys_ctrl0[4] ) begin 147 | sys_ctrl0_mem_repair_done <= sys_ctrl0_mem_repair_done; 148 | $display("%m @%t: Error writing Read-Only field of sys_ctrl0_mem_repair_done !"); 149 | end 150 | end 151 | end 152 | 153 | 154 | // Reg: test_reg 155 | // Field: test_field0 156 | // Type: RW 157 | // Reset: 0 158 | always @(negedge preset or posedge pclk) begin 159 | if (!preset) begin 160 | test_reg_test_field0 <= 4'h0; 161 | end begin 162 | if ( wen_test_reg[0] ) begin 163 | test_reg_test_field0[4-1:0] <= pwdata[3:0]; 164 | end 165 | end 166 | end 167 | 168 | 169 | // Reg: test_reg 170 | // Field: test_filed1 171 | // Type: WO 172 | // Reset: 3 173 | always @(negedge preset or posedge pclk) begin 174 | if (!preset) begin 175 | test_reg_test_filed1 <= 2'h3; 176 | end begin 177 | if ( wen_test_reg[1] ) begin 178 | test_reg_test_filed1[2-1:0] <= pwdata[5:4]; 179 | end 180 | end 181 | end 182 | 183 | always @(*) begin 184 | rdata_sel = 32'h00000000; 185 | if (!pwrite & psel ) begin 186 | case (addr) 187 | 32'h00000010: begin 188 | rdata_sel[0:0] = sys_ctrl0_pdc_use_arm_ctrl[0:0]; //Control if use arm ctrl-seq HIGH enable 189 | rdata_sel[3:1] = sys_ctrl0_l2c_strip_mode[2:0]; //Control L2 cache stripping mode HIGH enable 190 | rdata_sel[8:4] = sys_ctrl0_smmu_mmusid[4:0]; // 191 | rdata_sel[9:9] = sys_ctrl0_mem_repair_en[0:0]; // 192 | rdata_sel[16:10] = sys_ctrl0_mem_repair_done[6:0]; // 193 | end 194 | 32'h0000001c: begin 195 | rdata_sel[3:0] = test_reg_test_field0[3:0]; //This test comments 196 | rdata_sel[5:4] = 1'hxxxxxxxx; //X out for WriteOnly field: test_reg_test_filed1[1:0]; // 197 | end 198 | default: begin 199 | rdata_sel = 32'h00000000; 200 | end 201 | endcase 202 | end 203 | end 204 | 205 | endmodule 206 | -------------------------------------------------------------------------------- /test/src.list: -------------------------------------------------------------------------------- 1 | ./NV_NVDLA_CMAC_CORE_mac.src 2 | -------------------------------------------------------------------------------- /test/test_DAC.v: -------------------------------------------------------------------------------- 1 | module test_DAC( 2 | oFLASH_ADDR 3 | ,iFLASH_DATA 4 | ,oSDRAM_ADDR 5 | ,iSDRAM_DATA 6 | ,oSRAM_ADDR, 7 | SRAM_DATA 8 | ,oAUD_BCK 9 | ,oAUD_DATA 10 | ,oAUD_LRCK 11 | ,iSrc_Select 12 | ,iCLK_18_4 13 | ,iRST_N 14 | ); 15 | 16 | `define TEST_BIT 3 17 | 18 | parameter REF_CLK = 18562000; // 18.432 MHz 19 | parameter SAMPLE_RATE = 48000; // 48 KHz 20 | parameter DATA_WIDTH = 16; // 16 Bits 21 | parameter CHANNEL_NUM = 2; // Dual Channel 22 | 23 | parameter SIN_SAMPLE_DATA = 48; 24 | parameter FLASH_DATA_NUM = 1048576; // 1 MWords 25 | parameter SDRAM_DATA_NUM = 4194304; // 4 MWords 26 | parameter SRAM_DATA_NUM = 262144; // 256 KWords 27 | 28 | parameter FLASH_ADDR_WIDTH= 20; // 20 Address Line 29 | parameter SDRAM_ADDR_WIDTH= 22; // 22 Address Line 30 | parameter SRAM_ADDR_WIDTH= 18; // 18 Address Line 31 | 32 | parameter FLASH_DATA_WIDTH= 8; // 8 Bits 33 | parameter SDRAM_DATA_WIDTH= 16; // 16 Bits 34 | parameter SRAM_DATA_WIDTH= 16; // 16 Bits 35 | 36 | //////////// Input Source Number ////////////// 37 | parameter SIN_SANPLE = 0; 38 | parameter FLASH_DATA = 1; 39 | parameter SDRAM_DATA = 2; 40 | parameter SRAM_DATA = 3; 41 | ////////////////////////////////////////////////// 42 | // Memory Side 43 | output reg [FLASH_ADDR_WIDTH-1:0] oFLASH_ADDR; 44 | input [FLASH_DATA_WIDTH-1:0] iFLASH_DATA; 45 | output bit [SDRAM_ADDR_WIDTH:0] oSDRAM_ADDR; 46 | input logic [SDRAM_DATA_WIDTH-1:0] iSDRAM_DATA; 47 | output wire [SRAM_ADDR_WIDTH:0] oSRAM_ADDR; 48 | input [SRAM_DATA_WIDTH-1:0] iSRAM_DATA; 49 | // Audio Side 50 | output [`TEST_BIT:0] oAUD_DATA; 51 | output oAUD_LRCK; 52 | output reg oAUD_BCK; 53 | // Control Signals 54 | input [1:0] iSrc_Select; 55 | input iCLK_18_4, iRST_N; // clk & reset port 56 | // Internal Registers and Wires 57 | reg [3:0] BCK_DIV; 58 | reg [8:0] LRCK_1X_DIV; 59 | reg [7:0] LRCK_2X_DIV; 60 | reg [6:0] LRCK_4X_DIV; 61 | reg [3:0] SEL_Cont; 62 | //////// DATA Counter //////// 63 | reg [5:0] SIN_Cont; 64 | reg [FLASH_ADDR_WIDTH-1:0] FLASH_Cont; 65 | reg [SDRAM_ADDR_WIDTH-1:0] SDRAM_Cont; 66 | reg [SRAM_ADDR_WIDTH-1:0] SRAM_Cont; 67 | //////////////////////////////////// 68 | reg [DATA_WIDTH-1:0] Sin_Out; 69 | reg [DATA_WIDTH-1:0] FLASH_Out; 70 | reg [DATA_WIDTH-1:0] SDRAM_Out; 71 | reg [DATA_WIDTH-1:0] SRAM_Out; 72 | reg [DATA_WIDTH-1:0] FLASH_Out_Tmp; 73 | reg [DATA_WIDTH-1:0] SDRAM_Out_Tmp; 74 | reg [DATA_WIDTH-1:0] SRAM_Out_Tmp; 75 | reg LRCK_1X; 76 | reg LRCK_2X; 77 | reg LRCK_4X; 78 | 79 | //////////// AUD_BCK Generator ////////////// 80 | always@(posedge iCLK_18_4 or negedge iRST_N) 81 | begin 82 | if(!iRST_N) 83 | begin 84 | BCK_DIV <= 0; 85 | oAUD_BCK <= 0; 86 | end 87 | else 88 | begin 89 | if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 ) 90 | begin 91 | BCK_DIV <= 0; 92 | oAUD_BCK <= ~oAUD_BCK; 93 | end 94 | else 95 | BCK_DIV <= BCK_DIV+1; 96 | end 97 | end 98 | ////////////////////////////////////////////////// 99 | //////////// AUD_LRCK Generator ////////////// 100 | always@(posedge iCLK_18_4 or negedge iRST_N) 101 | begin 102 | if(!iRST_N) 103 | begin 104 | LRCK_1X_DIV <= 0; 105 | LRCK_2X_DIV <= 0; 106 | LRCK_4X_DIV <= 0; 107 | LRCK_1X <= 0; 108 | LRCK_2X <= 0; 109 | LRCK_4X <= 0; 110 | end 111 | else 112 | begin 113 | // LRCK 1X 114 | if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 ) 115 | begin 116 | LRCK_1X_DIV <= 0; 117 | LRCK_1X <= ~LRCK_1X; 118 | end 119 | else 120 | LRCK_1X_DIV <= LRCK_1X_DIV+1; 121 | // LRCK 2X 122 | if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 ) 123 | begin 124 | LRCK_2X_DIV <= 0; 125 | LRCK_2X <= ~LRCK_2X; 126 | end 127 | else 128 | LRCK_2X_DIV <= LRCK_2X_DIV+1; 129 | // LRCK 4X 130 | if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 ) 131 | begin 132 | LRCK_4X_DIV <= 0; 133 | LRCK_4X <= ~LRCK_4X; 134 | end 135 | else 136 | LRCK_4X_DIV <= LRCK_4X_DIV+1; 137 | end 138 | end 139 | assign oAUD_LRCK = LRCK_1X; 140 | ////////////////////////////////////////////////// 141 | ////////// Sin LUT ADDR Generator ////////////// 142 | always@(negedge LRCK_1X or negedge iRST_N) 143 | begin 144 | if(!iRST_N) 145 | SIN_Cont <= 0; 146 | else 147 | begin 148 | if(SIN_Cont < SIN_SAMPLE_DATA-1 ) 149 | SIN_Cont <= SIN_Cont+1; 150 | else 151 | SIN_Cont <= 0; 152 | end 153 | end 154 | ////////////////////////////////////////////////// 155 | ////////// FLASH ADDR Generator ////////////// 156 | always@(negedge LRCK_4X or negedge iRST_N) 157 | begin 158 | if(!iRST_N) 159 | FLASH_Cont <= 0; 160 | else 161 | begin 162 | if(FLASH_Cont < FLASH_DATA_NUM-1 ) 163 | FLASH_Cont <= FLASH_Cont+1; 164 | else 165 | FLASH_Cont <= 0; 166 | end 167 | end 168 | assign oFLASH_ADDR = FLASH_Cont; 169 | ////////////////////////////////////////////////// 170 | ////////// FLASH DATA Reorder ////////////// 171 | always@(posedge LRCK_4X or negedge iRST_N) 172 | begin 173 | if(!iRST_N) 174 | FLASH_Out_Tmp <= 0; 175 | else 176 | begin 177 | if(FLASH_Cont[0]) 178 | FLASH_Out_Tmp[15:8] <= iFLASH_DATA; 179 | else 180 | FLASH_Out_Tmp[7:0] <= iFLASH_DATA; 181 | end 182 | end 183 | always@(negedge LRCK_2X or negedge iRST_N) 184 | begin 185 | if(!iRST_N) 186 | FLASH_Out <= 0; 187 | else 188 | FLASH_Out <= FLASH_Out_Tmp; 189 | end 190 | ////////////////////////////////////////////////// 191 | ////////// SDRAM ADDR Generator ////////////// 192 | always@(negedge LRCK_2X or negedge iRST_N) 193 | begin 194 | if(!iRST_N) 195 | SDRAM_Cont <= 0; 196 | else 197 | begin 198 | if(SDRAM_Cont < SDRAM_DATA_NUM-1 ) 199 | SDRAM_Cont <= SDRAM_Cont+1; 200 | else 201 | SDRAM_Cont <= 0; 202 | end 203 | end 204 | assign oSDRAM_ADDR = SDRAM_Cont; 205 | ////////////////////////////////////////////////// 206 | ////////// SDRAM DATA Latch ////////////// 207 | always@(posedge LRCK_2X or negedge iRST_N) 208 | begin 209 | if(!iRST_N) 210 | SDRAM_Out_Tmp <= 0; 211 | else 212 | SDRAM_Out_Tmp <= iSDRAM_DATA; 213 | end 214 | always@(negedge LRCK_2X or negedge iRST_N) 215 | begin 216 | if(!iRST_N) 217 | SDRAM_Out <= 0; 218 | else 219 | SDRAM_Out <= SDRAM_Out_Tmp; 220 | end 221 | ////////////////////////////////////////////////// 222 | //////////// SRAM ADDR Generator //////////// 223 | always@(negedge LRCK_2X or negedge iRST_N) 224 | begin 225 | if(!iRST_N) 226 | SRAM_Cont <= 0; 227 | else 228 | begin 229 | if(SRAM_Cont < SRAM_DATA_NUM-1 ) 230 | SRAM_Cont <= SRAM_Cont+1; 231 | else 232 | SRAM_Cont <= 0; 233 | end 234 | end 235 | assign oSRAM_ADDR = SRAM_Cont; 236 | ////////////////////////////////////////////////// 237 | ////////// SRAM DATA Latch ////////////// 238 | always@(posedge LRCK_2X or negedge iRST_N) 239 | begin 240 | if(!iRST_N) 241 | SRAM_Out_Tmp <= 0; 242 | else 243 | SRAM_Out_Tmp <= iSRAM_DATA; 244 | end 245 | always@(negedge LRCK_2X or negedge iRST_N) 246 | begin 247 | if(!iRST_N) 248 | SRAM_Out <= 0; 249 | else 250 | SRAM_Out <= SRAM_Out_Tmp; 251 | end 252 | ////////////////////////////////////////////////// 253 | ////////// 16 Bits PISO MSB First ////////////// 254 | always@(negedge oAUD_BCK or negedge iRST_N) 255 | begin 256 | if(!iRST_N) 257 | SEL_Cont <= 0; 258 | else 259 | SEL_Cont <= SEL_Cont+1; 260 | end 261 | assign oAUD_DATA = (iSrc_Select==SIN_SANPLE) ? Sin_Out[~SEL_Cont] : 262 | (iSrc_Select==FLASH_DATA) ? FLASH_Out[~SEL_Cont]: 263 | (iSrc_Select==SDRAM_DATA) ? SDRAM_Out[~SEL_Cont]: 264 | SRAM_Out[~SEL_Cont] ; 265 | ////////////////////////////////////////////////// 266 | //////////// Sin Wave ROM Table ////////////// 267 | always@(SIN_Cont) 268 | begin 269 | case(SIN_Cont) 270 | 0 : Sin_Out <= 0 ; 271 | 1 : Sin_Out <= 4276 ; 272 | 2 : Sin_Out <= 8480 ; 273 | 3 : Sin_Out <= 12539 ; 274 | 4 : Sin_Out <= 16383 ; 275 | 5 : Sin_Out <= 19947 ; 276 | 6 : Sin_Out <= 23169 ; 277 | 7 : Sin_Out <= 25995 ; 278 | 8 : Sin_Out <= 28377 ; 279 | 9 : Sin_Out <= 30272 ; 280 | 10 : Sin_Out <= 31650 ; 281 | 11 : Sin_Out <= 32486 ; 282 | 12 : Sin_Out <= 32767 ; 283 | 13 : Sin_Out <= 32486 ; 284 | 14 : Sin_Out <= 31650 ; 285 | 15 : Sin_Out <= 30272 ; 286 | 16 : Sin_Out <= 28377 ; 287 | 17 : Sin_Out <= 25995 ; 288 | 18 : Sin_Out <= 23169 ; 289 | 19 : Sin_Out <= 19947 ; 290 | 20 : Sin_Out <= 16383 ; 291 | 21 : Sin_Out <= 12539 ; 292 | 22 : Sin_Out <= 8480 ; 293 | 23 : Sin_Out <= 4276 ; 294 | 24 : Sin_Out <= 0 ; 295 | 25 : Sin_Out <= 61259 ; 296 | 26 : Sin_Out <= 57056 ; 297 | 27 : Sin_Out <= 52997 ; 298 | 28 : Sin_Out <= 49153 ; 299 | 29 : Sin_Out <= 45589 ; 300 | 30 : Sin_Out <= 42366 ; 301 | 31 : Sin_Out <= 39540 ; 302 | 32 : Sin_Out <= 37159 ; 303 | 33 : Sin_Out <= 35263 ; 304 | 34 : Sin_Out <= 33885 ; 305 | 35 : Sin_Out <= 33049 ; 306 | 36 : Sin_Out <= 32768 ; 307 | 37 : Sin_Out <= 33049 ; 308 | 38 : Sin_Out <= 33885 ; 309 | 39 : Sin_Out <= 35263 ; 310 | 40 : Sin_Out <= 37159 ; 311 | 41 : Sin_Out <= 39540 ; 312 | 42 : Sin_Out <= 42366 ; 313 | 43 : Sin_Out <= 45589 ; 314 | 44 : Sin_Out <= 49152 ; 315 | 45 : Sin_Out <= 52997 ; 316 | 46 : Sin_Out <= 57056 ; 317 | 47 : Sin_Out <= 61259 ; 318 | default : 319 | Sin_Out <= 0 ; 320 | endcase 321 | end 322 | ////////////////////////////////////////////////// 323 | 324 | endmodule 325 | 326 | 327 | 328 | 329 | --------------------------------------------------------------------------------