├── Change_History ├── HDLGen.bin ├── HDLGen.pl ├── README.md ├── doc ├── AutoDef_Sample.PNG ├── AutoInstSig_Sample.PNG ├── AutoWarning_Sample.PNG ├── Design_Template_Sample.PNG ├── HDLGen_Intro_En.pdf ├── IPXACT_Sample.PNG ├── Instance_Sample.PNG ├── JSON_Sample.PNG └── WorkingFlow.PNG ├── plugins ├── AsyncIntfGen.pm ├── ClkGen.pm ├── Design_Template │ ├── AsyncFifo.tmpl.v │ ├── AsyncIntf.tmpl.v │ ├── Clk.tmpl.v │ ├── Fuse.tmpl.v │ ├── Mem.tmpl.v │ ├── Pmu.tmpl.v │ ├── Rst.tmpl.v │ └── SyncFifo.tmpl.v ├── FifoGen.pm ├── FuseGen.pm ├── HDLGen.pm ├── HDLGenIpxIntf.pm ├── MemGen.pm ├── PmuGen.pm ├── RstGen.pm ├── eFunc.pm └── eFuncPrint.pm ├── setenv.sh └── test ├── NV_NVDLA_CMAC_CORE_mac.v.Ref ├── NV_NVDLA_CMAC_CORE_mac.vp ├── cfg ├── AFifo_Cfg.json ├── APB.xml ├── AsyncIntf_Cfg.json ├── Clk_Cfg.json ├── Fuse_Cfg.json ├── Mem_Cfg.json ├── MyIntf.json ├── Pmu_Cfg.json ├── Regs.json ├── Rst_Cfg.json ├── SFifo_Cfg.json ├── my_test_design.JSON └── simple_spi.xml ├── incr ├── NV_NVDLA_CMAC_CORE_MAC_exp.v ├── NV_NVDLA_CMAC_CORE_MAC_mul.v ├── NV_NVDLA_CMAC_CORE_MAC_nan.v ├── apb_test.v └── test_sys_ctrl_apb_regs.v ├── src.list └── test_DAC.v /Change_History: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/HEAD/Change_History -------------------------------------------------------------------------------- /HDLGen.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/HEAD/HDLGen.bin -------------------------------------------------------------------------------- /HDLGen.pl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/WilsonChen003/HDLGen/HEAD/HDLGen.pl -------------------------------------------------------------------------------- /README.md: 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