├── _config.yml ├── CONTRIBUTING.md ├── quick_spi_api ├── QuickSPI.cpp └── QuickSPI.h ├── .gitignore ├── README.md ├── tests ├── quick_spi_soft_tests │ ├── quick_spi_soft_testbench.v │ └── __Previews │ │ └── quick_spi_soft_tests.vPreview ├── quick_spi_hard_be_lsb_tests │ └── quick_spi_hard_be_lsb_testbench.v ├── quick_spi_hard_be_msb_tests │ └── quick_spi_hard_be_msb_testbench.v ├── quick_spi_hard_le_lsb_tests │ └── quick_spi_hard_le_lsb_testbench.v └── quick_spi_hard_le_msb_tests │ └── quick_spi_hard_le_msb_testbench.v ├── CODE_OF_CONDUCT.md ├── quick_spi_soft.xpr ├── src ├── quick_spi_hard.v └── quick_spi_soft.v ├── quick_spi_hard.xpr └── LICENSE /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-hacker -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | VeryNiceGuy aka Alex Petrov 2 | EvilLord666 aka Michael Ushakov 3 | -------------------------------------------------------------------------------- /quick_spi_api/QuickSPI.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wissance/QuickSPI/HEAD/quick_spi_api/QuickSPI.cpp -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.o 3 | *.ko 4 | *.obj 5 | *.elf 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Libraries 12 | *.lib 13 | *.a 14 | *.la 15 | *.lo 16 | 17 | # Shared objects (inc. Windows DLLs) 18 | *.dll 19 | *.so 20 | *.so.* 21 | *.dylib 22 | 23 | # Executables 24 | *.exe 25 | *.out 26 | *.app 27 | *.i*86 28 | *.x86_64 29 | *.hex 30 | 31 | # Debug files 32 | *.dSYM/ 33 | *.su 34 | 35 | # Log files 36 | *.log 37 | # Jou files 38 | *.jou 39 | # Backups 40 | *.backup 41 | # Generated shit 42 | *.hw 43 | *.cache 44 | *.runs 45 | *.sim 46 | *.sdk 47 | *.ip_user_files 48 | *.str 49 | *.Xil 50 | *Debug/ 51 | *vivado_pid* 52 | ~$* 53 | *standalone_bsp_0* 54 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # QuickSPI 2 | 3 | SPI Verilog modules 2 SPI implementations: 4 | 1. Fully Hard for FPGA without CPU core like Spartan 6 or Cyclone 4, e.t.c. 5 | features: 6 | - setting bit (MSB, LSB) and bytes order (Little endian or Big endina) 7 | - adjustable number of extra clocks when some devices needs to make internal synchronizzation while CS is still active and clock keep going from clk (Dragster/Awaiba/Cmosis DR-2k-7) 8 | 9 | 2. Fully soft SPI with AXI Full interface with CPU. 10 | 11 | Docs on Russian: https://github.com/OpticalMeasurementsSystems/QuickSPI/wiki/How-to-use-:-%D0%9F%D0%BE%D0%BB%D0%BD%D0%BE%D0%B5-%D1%80%D1%83%D0%BA%D0%BE%D0%B2%D0%BE%D0%B4%D1%81%D1%82%D0%B2%D0%BE 12 | -------------------------------------------------------------------------------- /tests/quick_spi_soft_tests/quick_spi_soft_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module quick_spi_soft_testbench; 4 | reg clk; 5 | reg rst_n; 6 | wire end_of_transaction; 7 | wire[7:0] incoming_data; 8 | reg[15:0] outgoing_data; 9 | wire mosi; 10 | reg miso; 11 | wire sclk; 12 | wire[1:0] ss_n; 13 | reg start_transaction; 14 | reg operation; 15 | 16 | integer sclk_toggle_count; 17 | reg[8:0] incoming_data_buffer; 18 | reg spi_clock_phase; 19 | 20 | initial begin 21 | clk <= 1'b0; 22 | rst_n <= 1'b0; 23 | rst_n <= #50 1'b1; 24 | end 25 | 26 | always @ (posedge clk) begin 27 | if(!rst_n) begin 28 | outgoing_data <= {8'b00011010, 8'b01101010}; 29 | operation <= 1'b0; 30 | miso <= 1'b0; 31 | sclk_toggle_count <= 0; 32 | incoming_data_buffer <= {8'b10010101, 1'b1}; 33 | spi_clock_phase <= 1'b1; 34 | end 35 | 36 | else begin 37 | if(sclk_toggle_count > 36 && operation == 1'b0) begin 38 | if(!spi_clock_phase) begin 39 | miso <= incoming_data_buffer[0]; 40 | incoming_data_buffer <= incoming_data_buffer >> 1; 41 | end 42 | end 43 | 44 | sclk_toggle_count <= sclk_toggle_count + 1; 45 | spi_clock_phase <= ~spi_clock_phase; 46 | end 47 | end 48 | 49 | quick_spi_soft spi( 50 | .s_axi_aclk(clk), 51 | .s_axi_aresetn(rst_n), 52 | .mosi(mosi), 53 | .miso(miso), 54 | .sclk(sclk), 55 | .ss_n(ss_n)); 56 | 57 | always #25 clk <= ~clk; 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /tests/quick_spi_hard_be_lsb_tests/quick_spi_hard_be_lsb_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module quick_spi_hard_be_lsb_testbench; 4 | reg clk; 5 | reg rst_n; 6 | wire end_of_transaction; 7 | wire[7:0] incoming_data; 8 | reg[15:0] outgoing_data; 9 | wire mosi; 10 | reg miso; 11 | wire sclk; 12 | wire[1:0] ss_n; 13 | reg enable; 14 | reg start_transaction; 15 | reg operation; 16 | 17 | integer sclk_toggle_count; 18 | reg[8:0] incoming_data_buffer; 19 | reg spi_clock_phase; 20 | 21 | initial begin 22 | clk <= 1'b0; 23 | rst_n <= 1'b0; 24 | rst_n <= #50 1'b1; 25 | outgoing_data <= {8'b11001100, 8'b10000010}; 26 | end 27 | 28 | always @ (posedge clk) 29 | begin 30 | if(!rst_n) 31 | begin 32 | outgoing_data <= {8'b11001100, 8'b10000010}; 33 | enable <= 1'b1; 34 | start_transaction <= 1'b1; 35 | operation <= 1'b0; 36 | miso <= 1'b0; 37 | sclk_toggle_count <= 0; 38 | incoming_data_buffer <= {8'b10010101, 1'b1}; 39 | spi_clock_phase <= 1'b1; 40 | end 41 | 42 | else 43 | begin 44 | if(end_of_transaction) 45 | begin 46 | operation <= ~operation; 47 | sclk_toggle_count <= 0; 48 | spi_clock_phase <= 1'b1; 49 | incoming_data_buffer <= {8'b10010101, 1'b1}; 50 | miso <= 1'b0; 51 | end 52 | 53 | else 54 | begin 55 | if(sclk_toggle_count > 36) 56 | begin 57 | if(!spi_clock_phase) 58 | begin 59 | miso <= incoming_data_buffer[0]; 60 | incoming_data_buffer <= incoming_data_buffer >> 1; 61 | end 62 | end 63 | 64 | sclk_toggle_count <= sclk_toggle_count + 1; 65 | spi_clock_phase <= ~spi_clock_phase; 66 | end 67 | end 68 | end 69 | 70 | quick_spi_hard # 71 | ( 72 | .BYTES_ORDER(1), // big endian, 73 | .BITS_ORDER(0) // LSB First 74 | ) 75 | spi 76 | ( 77 | .clk(clk), 78 | .reset_n(rst_n), 79 | .enable(enable), 80 | .start_transaction(start_transaction), 81 | .slave(2'b01), 82 | .operation(operation), 83 | .end_of_transaction(end_of_transaction), 84 | .incoming_data(incoming_data), 85 | .outgoing_data(outgoing_data), 86 | .mosi(mosi), 87 | .miso(miso), 88 | .sclk(sclk), 89 | .ss_n(ss_n) 90 | ); 91 | 92 | always #25 clk <= ~clk; 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /tests/quick_spi_hard_be_msb_tests/quick_spi_hard_be_msb_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module quick_spi_hard_be_msb_testbench; 4 | reg clk; 5 | reg rst_n; 6 | wire end_of_transaction; 7 | wire[7:0] incoming_data; 8 | reg[15:0] outgoing_data; 9 | wire mosi; 10 | reg miso; 11 | wire sclk; 12 | wire[1:0] ss_n; 13 | reg enable; 14 | reg start_transaction; 15 | reg operation; 16 | 17 | integer sclk_toggle_count; 18 | reg[8:0] incoming_data_buffer; 19 | reg spi_clock_phase; 20 | 21 | initial begin 22 | clk <= 1'b0; 23 | rst_n <= 1'b0; 24 | rst_n <= #50 1'b1; 25 | outgoing_data <= {8'b11001100, 8'b10000010}; 26 | end 27 | 28 | always @ (posedge clk) 29 | begin 30 | if(!rst_n) 31 | begin 32 | outgoing_data <= {8'b11001100, 8'b10000010}; 33 | enable <= 1'b1; 34 | start_transaction <= 1'b1; 35 | operation <= 1'b0; 36 | miso <= 1'b0; 37 | sclk_toggle_count <= 0; 38 | incoming_data_buffer <= {8'b10010101, 1'b1}; 39 | spi_clock_phase <= 1'b1; 40 | end 41 | 42 | else 43 | begin 44 | if(end_of_transaction) 45 | begin 46 | operation <= ~operation; 47 | sclk_toggle_count <= 0; 48 | spi_clock_phase <= 1'b1; 49 | incoming_data_buffer <= {8'b10010101, 1'b1}; 50 | miso <= 1'b0; 51 | end 52 | 53 | else 54 | begin 55 | if(sclk_toggle_count > 36) 56 | begin 57 | if(!spi_clock_phase) 58 | begin 59 | miso <= incoming_data_buffer[0]; 60 | incoming_data_buffer <= incoming_data_buffer >> 1; 61 | end 62 | end 63 | 64 | sclk_toggle_count <= sclk_toggle_count + 1; 65 | spi_clock_phase <= ~spi_clock_phase; 66 | end 67 | end 68 | end 69 | 70 | quick_spi_hard # 71 | ( 72 | .BYTES_ORDER(1), // big endian, 73 | .BITS_ORDER(1) // MSB First 74 | ) 75 | spi 76 | ( 77 | .clk(clk), 78 | .reset_n(rst_n), 79 | .enable(enable), 80 | .start_transaction(start_transaction), 81 | .slave(2'b01), 82 | .operation(operation), 83 | .end_of_transaction(end_of_transaction), 84 | .incoming_data(incoming_data), 85 | .outgoing_data(outgoing_data), 86 | .mosi(mosi), 87 | .miso(miso), 88 | .sclk(sclk), 89 | .ss_n(ss_n) 90 | ); 91 | 92 | always #25 clk <= ~clk; 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /tests/quick_spi_hard_le_lsb_tests/quick_spi_hard_le_lsb_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module quick_spi_hard_le_lsb_testbench; 4 | reg clk; 5 | reg rst_n; 6 | wire end_of_transaction; 7 | wire[7:0] incoming_data; 8 | reg[15:0] outgoing_data; 9 | wire mosi; 10 | reg miso; 11 | wire sclk; 12 | wire[1:0] ss_n; 13 | reg enable; 14 | reg start_transaction; 15 | reg operation; 16 | 17 | integer sclk_toggle_count; 18 | reg[8:0] incoming_data_buffer; 19 | reg spi_clock_phase; 20 | 21 | initial begin 22 | clk <= 1'b0; 23 | rst_n <= 1'b0; 24 | rst_n <= #50 1'b1; 25 | outgoing_data <= {8'b11001100, 8'b10000010}; 26 | end 27 | 28 | always @ (posedge clk) 29 | begin 30 | if(!rst_n) 31 | begin 32 | outgoing_data <= {8'b11001100, 8'b10000010}; 33 | enable <= 1'b1; 34 | start_transaction <= 1'b1; 35 | operation <= 1'b0; 36 | miso <= 1'b0; 37 | sclk_toggle_count <= 0; 38 | incoming_data_buffer <= {8'b10010101, 1'b1}; 39 | spi_clock_phase <= 1'b1; 40 | end 41 | 42 | else 43 | begin 44 | if(end_of_transaction) 45 | begin 46 | operation <= ~operation; 47 | sclk_toggle_count <= 0; 48 | spi_clock_phase <= 1'b1; 49 | incoming_data_buffer <= {8'b10010101, 1'b1}; 50 | miso <= 1'b0; 51 | end 52 | 53 | else 54 | begin 55 | if(sclk_toggle_count > 36) 56 | begin 57 | if(!spi_clock_phase) 58 | begin 59 | miso <= incoming_data_buffer[0]; 60 | incoming_data_buffer <= incoming_data_buffer >> 1; 61 | end 62 | end 63 | 64 | sclk_toggle_count <= sclk_toggle_count + 1; 65 | spi_clock_phase <= ~spi_clock_phase; 66 | end 67 | end 68 | end 69 | 70 | quick_spi_hard # 71 | ( 72 | .BYTES_ORDER(0), // little endian, 73 | .BITS_ORDER(0) // LSB First 74 | ) 75 | spi 76 | ( 77 | .clk(clk), 78 | .reset_n(rst_n), 79 | .enable(enable), 80 | .start_transaction(start_transaction), 81 | .slave(2'b01), 82 | .operation(operation), 83 | .end_of_transaction(end_of_transaction), 84 | .incoming_data(incoming_data), 85 | .outgoing_data(outgoing_data), 86 | .mosi(mosi), 87 | .miso(miso), 88 | .sclk(sclk), 89 | .ss_n(ss_n) 90 | ); 91 | 92 | always #25 clk <= ~clk; 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /tests/quick_spi_hard_le_msb_tests/quick_spi_hard_le_msb_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module quick_spi_hard_le_msb_testbench; 4 | reg clk; 5 | reg rst_n; 6 | wire end_of_transaction; 7 | wire[7:0] incoming_data; 8 | reg[15:0] outgoing_data; 9 | wire mosi; 10 | reg miso; 11 | wire sclk; 12 | wire[1:0] ss_n; 13 | reg enable; 14 | reg start_transaction; 15 | reg operation; 16 | 17 | integer sclk_toggle_count; 18 | reg[8:0] incoming_data_buffer; 19 | reg spi_clock_phase; 20 | 21 | initial begin 22 | clk <= 1'b0; 23 | rst_n <= 1'b0; 24 | rst_n <= #50 1'b1; 25 | outgoing_data <= {8'b11001100, 8'b10000010}; 26 | end 27 | 28 | always @ (posedge clk) 29 | begin 30 | if(!rst_n) 31 | begin 32 | outgoing_data <= {8'b11001100, 8'b10000010}; 33 | enable <= 1'b1; 34 | start_transaction <= 1'b1; 35 | operation <= 1'b0; 36 | miso <= 1'b0; 37 | sclk_toggle_count <= 0; 38 | incoming_data_buffer <= {8'b10010101, 1'b1}; 39 | spi_clock_phase <= 1'b1; 40 | end 41 | 42 | else 43 | begin 44 | if(end_of_transaction) 45 | begin 46 | operation <= ~operation; 47 | sclk_toggle_count <= 0; 48 | spi_clock_phase <= 1'b1; 49 | incoming_data_buffer <= {8'b10010101, 1'b1}; 50 | miso <= 1'b0; 51 | end 52 | 53 | else 54 | begin 55 | if(sclk_toggle_count > 36) 56 | begin 57 | if(!spi_clock_phase) 58 | begin 59 | miso <= incoming_data_buffer[0]; 60 | incoming_data_buffer <= incoming_data_buffer >> 1; 61 | end 62 | end 63 | 64 | sclk_toggle_count <= sclk_toggle_count + 1; 65 | spi_clock_phase <= ~spi_clock_phase; 66 | end 67 | end 68 | end 69 | 70 | quick_spi_hard # 71 | ( 72 | .BYTES_ORDER(0), // little endian, 73 | .BITS_ORDER(1) // MSB First 74 | ) 75 | spi 76 | ( 77 | .clk(clk), 78 | .reset_n(rst_n), 79 | .enable(enable), 80 | .start_transaction(start_transaction), 81 | .slave(2'b01), 82 | .operation(operation), 83 | .end_of_transaction(end_of_transaction), 84 | .incoming_data(incoming_data), 85 | .outgoing_data(outgoing_data), 86 | .mosi(mosi), 87 | .miso(miso), 88 | .sclk(sclk), 89 | .ss_n(ss_n) 90 | ); 91 | 92 | always #25 clk <= ~clk; 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | # Contributor Covenant Code of Conduct 2 | 3 | ## Our Pledge 4 | 5 | In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation. 6 | 7 | ## Our Standards 8 | 9 | Examples of behavior that contributes to creating a positive environment include: 10 | 11 | * Using welcoming and inclusive language 12 | * Being respectful of differing viewpoints and experiences 13 | * Gracefully accepting constructive criticism 14 | * Focusing on what is best for the community 15 | * Showing empathy towards other community members 16 | 17 | Examples of unacceptable behavior by participants include: 18 | 19 | * The use of sexualized language or imagery and unwelcome sexual attention or advances 20 | * Trolling, insulting/derogatory comments, and personal or political attacks 21 | * Public or private harassment 22 | * Publishing others' private information, such as a physical or electronic address, without explicit permission 23 | * Other conduct which could reasonably be considered inappropriate in a professional setting 24 | 25 | ## Our Responsibilities 26 | 27 | Project maintainers are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. 28 | 29 | Project maintainers have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful. 30 | 31 | ## Scope 32 | 33 | This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by project maintainers. 34 | 35 | ## Enforcement 36 | 37 | Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at um.nix.user@gmail.com. The project team will review and investigate all complaints, and will respond in a way that it deems appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. 38 | 39 | Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. 40 | 41 | ## Attribution 42 | 43 | This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at [http://contributor-covenant.org/version/1/4][version] 44 | 45 | [homepage]: http://contributor-covenant.org 46 | [version]: http://contributor-covenant.org/version/1/4/ 47 | -------------------------------------------------------------------------------- /quick_spi_soft.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 57 | 58 | 59 | 60 | 61 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 82 | 83 | 84 | 85 | 86 | 89 | 90 | 92 | 93 | 95 | 96 | 98 | 99 | 101 | 102 | 104 | 105 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | -------------------------------------------------------------------------------- /src/quick_spi_hard.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | // Company: 3 | // Engineer: 4 | // 5 | // Create Date: 6 | // Design Name: 7 | // Module Name: quick_spi 8 | // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: spi module with arbitrary data length up to 64 bits, 12 | // i.e it could send 37 or 23 or 11 bits 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 1.0 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1ns / 1ps 22 | 23 | `define LSB_FIRST 0 24 | `define MSB_FIRST 1 25 | `define LITTLE_ENDIAN 0 26 | `define BIG_ENDIAN 1 27 | 28 | `define MAX_DATA_WIDTH 64 29 | 30 | module quick_spi_hard # 31 | ( 32 | // slaves number 33 | parameter NUMBER_OF_SLAVES = 2, 34 | // data transfer parameters (data bus width, words quantity, e.t.c) 35 | parameter INCOMING_DATA_WIDTH = 8, 36 | parameter OUTGOING_DATA_WIDTH = 16, 37 | // bits and bytes order (how outgoing data is popping from buffer) 38 | parameter BITS_ORDER = `MSB_FIRST, 39 | parameter BYTES_ORDER = `LITTLE_ENDIAN, 40 | // extra toggles 41 | parameter EXTRA_WRITE_SCLK_TOGGLES = 6, 42 | parameter EXTRA_READ_SCLK_TOGGLES = 4, 43 | // clock polarity and phase 44 | parameter CPOL = 0, 45 | parameter CPHA = 0, 46 | // idle values 47 | parameter MOSI_IDLE_VALUE = 1'b0 48 | ) 49 | ( 50 | input wire clk, 51 | input wire reset_n, 52 | input wire enable, 53 | input wire start_transaction, 54 | input wire[NUMBER_OF_SLAVES-1:0] slave, 55 | input wire operation, 56 | output reg end_of_transaction, 57 | output reg[INCOMING_DATA_WIDTH-1:0] incoming_data, 58 | input wire[OUTGOING_DATA_WIDTH-1:0] outgoing_data, 59 | output reg mosi, 60 | input wire miso, 61 | output reg sclk, 62 | output reg[NUMBER_OF_SLAVES-1:0] ss_n); 63 | 64 | localparam READ = 1'b0; 65 | localparam WRITE = 1'b1; 66 | 67 | localparam READ_SCLK_TOGGLES = (INCOMING_DATA_WIDTH * 2) + 2; 68 | localparam ALL_READ_TOGGLES = EXTRA_READ_SCLK_TOGGLES + READ_SCLK_TOGGLES; 69 | 70 | // at least 1, because we could transfer i.e. 6 or 5 bits () 71 | localparam NUMBER_OF_FULL_BYTES = OUTGOING_DATA_WIDTH > 1 ? (OUTGOING_DATA_WIDTH / 8) : 0; 72 | localparam NUMBER_OF_PARTICULAR_BITS = OUTGOING_DATA_WIDTH > (NUMBER_OF_FULL_BYTES * 8) ? 1 : 0; 73 | localparam NUMBER_OF_BYTES = NUMBER_OF_FULL_BYTES + NUMBER_OF_PARTICULAR_BITS; 74 | localparam MAX_BYTES_INDEX = NUMBER_OF_BYTES - 1; 75 | 76 | integer sclk_toggle_count; 77 | integer transaction_toggles; 78 | 79 | reg spi_clock_phase; 80 | reg[1:0] state; 81 | 82 | localparam IDLE = 2'b00; 83 | localparam ACTIVE = 2'b01; 84 | localparam WAIT = 2'b10; 85 | 86 | reg[INCOMING_DATA_WIDTH - 1:0] incoming_data_buffer; 87 | reg[OUTGOING_DATA_WIDTH - 1:0] outgoing_data_buffer; 88 | reg[`MAX_DATA_WIDTH - 1:0] intermediate_buffer; 89 | 90 | reg[2:0] bit_counter; 91 | reg[3:0] byte_counter; 92 | 93 | always @ (posedge clk) 94 | begin 95 | if(!reset_n) 96 | begin 97 | end_of_transaction <= 1'b0; 98 | mosi <= MOSI_IDLE_VALUE; 99 | sclk <= CPOL; 100 | ss_n <= {NUMBER_OF_SLAVES{1'b1}}; 101 | sclk_toggle_count <= 0; 102 | transaction_toggles <= 0; 103 | spi_clock_phase <= ~CPHA; 104 | incoming_data <= {INCOMING_DATA_WIDTH{1'b0}}; 105 | incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}}; 106 | outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}}; 107 | state <= IDLE; 108 | bit_counter <= 0; 109 | byte_counter <= 0; 110 | end 111 | 112 | else begin 113 | case(state) 114 | IDLE: 115 | begin 116 | if(enable) 117 | begin 118 | bit_counter <= 0; 119 | byte_counter <= 0; 120 | if(start_transaction) 121 | begin 122 | transaction_toggles <= (operation == READ) ? ALL_READ_TOGGLES : EXTRA_WRITE_SCLK_TOGGLES; 123 | intermediate_buffer = put_data(outgoing_data, BYTES_ORDER); 124 | outgoing_data_buffer <= intermediate_buffer[15:0]; 125 | state <= ACTIVE; 126 | end 127 | end 128 | end 129 | 130 | ACTIVE: 131 | begin 132 | ss_n[slave] <= 1'b0; 133 | spi_clock_phase <= ~spi_clock_phase; 134 | 135 | if(ss_n[slave] == 1'b0) 136 | begin 137 | if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) + transaction_toggles) 138 | begin 139 | sclk <= ~sclk; 140 | sclk_toggle_count <= sclk_toggle_count + 1; 141 | end 142 | end 143 | 144 | if(spi_clock_phase == 1'b0) 145 | begin 146 | if(operation == READ) 147 | begin 148 | if(sclk_toggle_count > ((OUTGOING_DATA_WIDTH * 2) + EXTRA_READ_SCLK_TOGGLES)-1) 149 | begin 150 | incoming_data_buffer <= incoming_data_buffer >> 1; 151 | incoming_data_buffer[INCOMING_DATA_WIDTH-1] <= miso; 152 | end 153 | end 154 | end 155 | 156 | else 157 | begin 158 | if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) - 1) 159 | begin 160 | if(BITS_ORDER == `LSB_FIRST) 161 | begin 162 | mosi <= outgoing_data_buffer[0]; // posiibly here we are passing BITS ORDER 163 | outgoing_data_buffer <= outgoing_data_buffer >> 1; 164 | end 165 | else 166 | begin 167 | bit_counter <= bit_counter + 1; 168 | mosi <= outgoing_data_buffer[7 - bit_counter]; 169 | if(bit_counter == 7) 170 | outgoing_data_buffer <= outgoing_data_buffer >> 8; 171 | end 172 | end 173 | end 174 | 175 | if(sclk_toggle_count == (OUTGOING_DATA_WIDTH * 2) + transaction_toggles) 176 | begin 177 | ss_n[slave] <= 1'b1; 178 | mosi <= MOSI_IDLE_VALUE; 179 | incoming_data <= incoming_data_buffer; 180 | incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}}; 181 | outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}}; 182 | sclk <= CPOL; 183 | spi_clock_phase <= ~CPHA; 184 | sclk_toggle_count <= 0; 185 | end_of_transaction <= 1'b1; 186 | state <= WAIT; 187 | end 188 | end 189 | 190 | WAIT: 191 | begin 192 | incoming_data <= {INCOMING_DATA_WIDTH{1'b0}}; 193 | end_of_transaction <= 1'b0; 194 | state <= IDLE; 195 | end 196 | endcase 197 | end 198 | end 199 | 200 | function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order); 201 | reg [`MAX_DATA_WIDTH - 1:0] result; 202 | reg[7:0] shift; 203 | begin 204 | shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8; 205 | if (order == `BIG_ENDIAN)//`LITTLE_ENDIAN) 206 | begin 207 | result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]}; 208 | if(shift > 0) 209 | put_data = result >> shift; 210 | //put_data[NUMBER_OF_BYTES * 8 - 1 : 0] = result[`MAX_DATA_WIDTH - 1 : `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8]; 211 | else put_data = result; 212 | end 213 | else if (order == `LITTLE_ENDIAN)//`BIG_ENDIAN) 214 | begin 215 | put_data = data; 216 | end 217 | end 218 | endfunction 219 | 220 | endmodule 221 | -------------------------------------------------------------------------------- /quick_spi_api/QuickSPI.h: -------------------------------------------------------------------------------- 1 | #ifndef SRC_QUICKSPI_H_ 2 | #define SRC_QUICKSPI_H_ 3 | 4 | #include 5 | #include "xscugic.h" 6 | 7 | class QuickSPI 8 | { 9 | public: 10 | QuickSPI(); 11 | ~QuickSPI(); 12 | 13 | static size_t getControlSize(); 14 | static size_t getBufferSize(); 15 | static size_t getWriteBufferStart(); 16 | static size_t getWriteBufferEnd(); 17 | static size_t getReadBufferStart(); 18 | static size_t getReadBufferEnd(); 19 | 20 | void* getMemory(); 21 | void* getWriteBuffer(); 22 | void* getReadBuffer(); 23 | 24 | unsigned char getCPOL() const; 25 | void setCPOL(unsigned char pmCPOL); 26 | 27 | unsigned char getCPHA() const; 28 | void setCPHA(unsigned char pmCPHA); 29 | 30 | bool getBurst() const; 31 | void setBurst(bool pmBurst); 32 | 33 | bool getRead() const; 34 | void setRead(bool pmRead); 35 | 36 | unsigned char getSlave() const; 37 | void setSlave(unsigned char pmSlave); 38 | 39 | unsigned char getDivider() const; 40 | void setDivider(unsigned char pmDivider); 41 | 42 | unsigned short getIncomingElementSize() const; 43 | void setIncomingElementSize(unsigned short pmIncomingElementSize); 44 | 45 | unsigned short getOutgoingElementSize() const; 46 | void setOutgoingElementSize(unsigned short pmOutgoingElementSize); 47 | 48 | unsigned short getNumIncomingElements() const; 49 | void setNumIncomingElements(unsigned short pmNumIncomingElements); 50 | 51 | unsigned short getNumOutgoingElements() const; 52 | void setNumOutgoingElements(unsigned short pmNumOutgoingElements); 53 | 54 | unsigned short getNumReadExtraToggles() const; 55 | void setNumReadExtraToggles(unsigned short pmNumReadExtraToggles); 56 | 57 | unsigned short getNumWriteExtraToggles() const; 58 | void setNumWriteExtraToggles(unsigned short pmNumWriteExtraToggles); 59 | void setIRQReceived(bool pmIRQReceived); 60 | 61 | void* getBaseAddress() const; 62 | void setBaseAddress(void* pmBaseAddress); 63 | 64 | static size_t computeNumBytesIncludingBitRemainder(size_t numBits); 65 | static size_t computeNumBytesExcludingBitRemainder(size_t numBits); 66 | static size_t computeBitRemainder(size_t numBits); 67 | 68 | static void copyBits( 69 | size_t numBits, 70 | const void* source, 71 | void* destination, 72 | size_t sourceStartBit, 73 | size_t destinationStartBit); 74 | 75 | void readBits(size_t numBits, void* buffer, size_t startBit); 76 | void writeBits(size_t numBits, const void* buffer, size_t startBit); 77 | 78 | static void reverseByteOrder(size_t numBytes, const void* source, void* destination); 79 | static void reverseBitOrder( 80 | size_t numBits, 81 | const void* source, 82 | void* destination, 83 | size_t sourceStartBit, 84 | size_t destinationStartBit); 85 | 86 | size_t computeNumIncomingBytes() const; 87 | size_t computeNumOutgoingBytes() const; 88 | 89 | void startTransaction(); 90 | void syncMemory(); 91 | private: 92 | void configureInterruptController(); 93 | void updateControl(); 94 | 95 | static const size_t MEMORY_SIZE = 64; 96 | static const size_t CONTROL_SIZE = 14; 97 | 98 | unsigned char CPOL; 99 | unsigned char CPHA; 100 | bool burst; 101 | bool read; 102 | unsigned char slave; 103 | unsigned char numClocksToSkip; 104 | unsigned short incomingElementSize; 105 | unsigned short outgoingElementSize; 106 | unsigned short numIncomingElements; 107 | unsigned short numOutgoingElements; 108 | unsigned short numReadExtraToggles; 109 | unsigned short numWriteExtraToggles; 110 | bool IRQReceived; 111 | unsigned char* memory; 112 | void* baseAddress; 113 | size_t numWrittenBits; 114 | size_t numReadBits; 115 | XScuGic_Config* GICconfig; 116 | XScuGic interruptController; 117 | }; 118 | 119 | inline size_t QuickSPI::getControlSize() 120 | { 121 | return CONTROL_SIZE; 122 | } 123 | 124 | inline size_t QuickSPI::getBufferSize() 125 | { 126 | return (MEMORY_SIZE - getWriteBufferStart()) / 2; 127 | } 128 | 129 | inline size_t QuickSPI::getWriteBufferStart() 130 | { 131 | return getControlSize(); 132 | } 133 | 134 | inline size_t QuickSPI::getWriteBufferEnd() 135 | { 136 | return getWriteBufferStart() + (getBufferSize() - 1); 137 | } 138 | 139 | inline size_t QuickSPI::getReadBufferStart() 140 | { 141 | return getWriteBufferStart() + getBufferSize(); 142 | } 143 | 144 | inline size_t QuickSPI::getReadBufferEnd() 145 | { 146 | return getReadBufferStart() + (getBufferSize() - 1); 147 | } 148 | 149 | inline void* QuickSPI::getMemory() 150 | { 151 | return memory; 152 | } 153 | 154 | inline void* QuickSPI::getWriteBuffer() 155 | { 156 | return &memory[getWriteBufferStart()]; 157 | } 158 | 159 | inline void* QuickSPI::getReadBuffer() 160 | { 161 | return &memory[getReadBufferStart()]; 162 | } 163 | 164 | inline void* QuickSPI::getBaseAddress() const 165 | { 166 | return baseAddress; 167 | } 168 | 169 | inline void QuickSPI::setBaseAddress(void* pmBaseAddress) 170 | { 171 | baseAddress = pmBaseAddress; 172 | } 173 | 174 | inline unsigned char QuickSPI::getCPOL() const 175 | { 176 | return CPOL; 177 | } 178 | 179 | inline void QuickSPI::setCPOL(unsigned char pmCPOL) 180 | { 181 | CPOL = pmCPOL; 182 | } 183 | 184 | inline unsigned char QuickSPI::getCPHA() const 185 | { 186 | return CPHA; 187 | } 188 | 189 | inline void QuickSPI::setCPHA(unsigned char pmCPHA) 190 | { 191 | CPHA = pmCPHA; 192 | } 193 | 194 | inline bool QuickSPI::getBurst() const 195 | { 196 | return burst; 197 | } 198 | 199 | inline void QuickSPI::setBurst(bool pmBurst) 200 | { 201 | burst = pmBurst; 202 | } 203 | 204 | inline bool QuickSPI::getRead() const 205 | { 206 | return read; 207 | } 208 | 209 | inline void QuickSPI::setRead(bool pmRead) 210 | { 211 | read = pmRead; 212 | } 213 | 214 | inline unsigned char QuickSPI::getSlave() const 215 | { 216 | return slave; 217 | } 218 | 219 | inline void QuickSPI::setSlave(unsigned char pmSlave) 220 | { 221 | slave = pmSlave; 222 | } 223 | 224 | inline unsigned char QuickSPI::getDivider() const 225 | { 226 | unsigned char lvDivider = 2; 227 | unsigned char lvNumClocksToSkip = numClocksToSkip; 228 | 229 | while(lvNumClocksToSkip) 230 | { 231 | lvDivider <<= 1; 232 | --lvNumClocksToSkip; 233 | } 234 | 235 | return lvDivider; 236 | } 237 | 238 | inline void QuickSPI::setDivider(unsigned char pmDivider) 239 | { 240 | if(pmDivider && !(pmDivider % 2)) 241 | { 242 | numClocksToSkip = 0; 243 | 244 | unsigned char lvDivider = pmDivider; 245 | while(lvDivider != 2) 246 | { 247 | lvDivider >>= 1; 248 | ++numClocksToSkip; 249 | } 250 | } 251 | } 252 | 253 | inline unsigned short QuickSPI::getIncomingElementSize() const 254 | { 255 | return incomingElementSize; 256 | } 257 | 258 | inline void QuickSPI::setIncomingElementSize(unsigned short pmIncomingElementSize) 259 | { 260 | incomingElementSize = pmIncomingElementSize; 261 | } 262 | 263 | inline unsigned short QuickSPI::getOutgoingElementSize() const 264 | { 265 | return outgoingElementSize; 266 | } 267 | 268 | inline void QuickSPI::setOutgoingElementSize(unsigned short pmOutgoingElementSize) 269 | { 270 | outgoingElementSize = pmOutgoingElementSize; 271 | } 272 | 273 | inline unsigned short QuickSPI::getNumIncomingElements() const 274 | { 275 | return numIncomingElements; 276 | } 277 | 278 | inline void QuickSPI::setNumIncomingElements(unsigned short pmNumIncomingElements) 279 | { 280 | numIncomingElements = pmNumIncomingElements; 281 | } 282 | 283 | inline unsigned short QuickSPI::getNumOutgoingElements() const 284 | { 285 | return numOutgoingElements; 286 | } 287 | 288 | inline void QuickSPI::setNumOutgoingElements(unsigned short pmNumOutgoingElements) 289 | { 290 | numOutgoingElements = pmNumOutgoingElements; 291 | } 292 | 293 | inline unsigned short QuickSPI::getNumReadExtraToggles() const 294 | { 295 | return numReadExtraToggles; 296 | } 297 | 298 | inline void QuickSPI::setNumReadExtraToggles(unsigned short pmNumReadExtraToggles) 299 | { 300 | numReadExtraToggles = pmNumReadExtraToggles; 301 | } 302 | 303 | inline unsigned short QuickSPI::getNumWriteExtraToggles() const 304 | { 305 | return numWriteExtraToggles; 306 | } 307 | 308 | inline void QuickSPI::setNumWriteExtraToggles(unsigned short pmNumWriteExtraToggles) 309 | { 310 | numWriteExtraToggles = pmNumWriteExtraToggles; 311 | } 312 | 313 | inline void QuickSPI::setIRQReceived(bool pmIRQReceived) 314 | { 315 | IRQReceived = pmIRQReceived; 316 | } 317 | 318 | inline size_t QuickSPI::computeNumBytesIncludingBitRemainder(size_t numBits) 319 | { 320 | return static_cast(ceil(static_cast(numBits) / 8.0)); 321 | } 322 | 323 | inline size_t QuickSPI::computeNumBytesExcludingBitRemainder(size_t numBits) 324 | { 325 | return static_cast(floor(static_cast(numBits) / 8.0)); 326 | } 327 | 328 | inline size_t QuickSPI::computeBitRemainder(size_t numBits) 329 | { 330 | return numBits - (computeNumBytesExcludingBitRemainder(numBits) * 8); 331 | } 332 | 333 | inline size_t QuickSPI::computeNumIncomingBytes() const 334 | { 335 | return computeNumBytesIncludingBitRemainder(getIncomingElementSize() * getNumIncomingElements()); 336 | } 337 | 338 | inline size_t QuickSPI::computeNumOutgoingBytes() const 339 | { 340 | return computeNumBytesIncludingBitRemainder(getOutgoingElementSize() * getNumOutgoingElements()); 341 | } 342 | 343 | #endif /* SRC_QUICKSPI_H_ */ 344 | -------------------------------------------------------------------------------- /quick_spi_hard.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 57 | 58 | 59 | 60 | 61 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 137 | 138 | 139 | 140 | 141 | 144 | 145 | 147 | 148 | 150 | 151 | 153 | 154 | 156 | 157 | 159 | 160 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | -------------------------------------------------------------------------------- /src/quick_spi_soft.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ps 2 | 3 | module quick_spi_soft # 4 | ( 5 | parameter integer C_S_AXI_ID_WIDTH = 1, 6 | parameter integer C_S_AXI_DATA_WIDTH = 32, 7 | parameter integer C_S_AXI_ADDR_WIDTH = 8, 8 | parameter integer C_S_AXI_AWUSER_WIDTH = 0, 9 | parameter integer C_S_AXI_ARUSER_WIDTH = 0, 10 | parameter integer C_S_AXI_WUSER_WIDTH = 0, 11 | parameter integer C_S_AXI_RUSER_WIDTH = 0, 12 | parameter integer C_S_AXI_BUSER_WIDTH = 0, 13 | parameter integer MEMORY_SIZE = 64, 14 | parameter integer NUMBER_OF_SLAVES = 2 15 | ) 16 | ( 17 | input wire s_axi_aclk, 18 | input wire s_axi_aresetn, 19 | input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid, 20 | input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, 21 | input wire [7:0] s_axi_awlen, 22 | input wire [2:0] s_axi_awsize, 23 | input wire [1:0] s_axi_awburst, 24 | input wire s_axi_awlock, 25 | input wire [3:0] s_axi_awcache, 26 | input wire [2:0] s_axi_awprot, 27 | input wire [3:0] s_axi_awqos, 28 | input wire [3:0] s_axi_awregion, 29 | input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, 30 | input wire s_axi_awvalid, 31 | output wire s_axi_awready, 32 | input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata, 33 | input wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb, 34 | input wire s_axi_wlast, 35 | input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser, 36 | input wire s_axi_wvalid, 37 | output wire s_axi_wready, 38 | output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid, 39 | output wire [1:0] s_axi_bresp, 40 | output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser, 41 | output wire s_axi_bvalid, 42 | input wire s_axi_bready, 43 | input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid, 44 | input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr, 45 | input wire [7:0] s_axi_arlen, 46 | input wire [2:0] s_axi_arsize, 47 | input wire [1:0] s_axi_arburst, 48 | input wire s_axi_arlock, 49 | input wire [3:0] s_axi_arcache, 50 | input wire [2:0] s_axi_arprot, 51 | input wire [3:0] s_axi_arqos, 52 | input wire [3:0] s_axi_arregion, 53 | input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, 54 | input wire s_axi_arvalid, 55 | output wire s_axi_arready, 56 | output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid, 57 | output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata, 58 | output wire [1:0] s_axi_rresp, 59 | output wire s_axi_rlast, 60 | output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser, 61 | output wire s_axi_rvalid, 62 | input wire s_axi_rready, 63 | output reg mosi, 64 | input wire miso, 65 | output reg sclk, 66 | output reg[NUMBER_OF_SLAVES-1:0] ss_n, 67 | output reg interrupt 68 | ); 69 | 70 | reg [C_S_AXI_ADDR_WIDTH-1:0] axi_awaddr; 71 | reg axi_awready; 72 | reg axi_wready; 73 | reg [1:0] axi_bresp; 74 | reg [C_S_AXI_BUSER_WIDTH-1:0] axi_buser; 75 | reg axi_bvalid; 76 | reg [C_S_AXI_ADDR_WIDTH-1:0] axi_araddr; 77 | reg axi_arready; 78 | reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata; 79 | reg [1:0] axi_rresp; 80 | reg axi_rlast; 81 | reg [C_S_AXI_RUSER_WIDTH-1:0] axi_ruser; 82 | reg axi_rvalid; 83 | 84 | wire aw_wrap_en; 85 | wire ar_wrap_en; 86 | wire [31:0] aw_wrap_size; 87 | wire [31:0] ar_wrap_size; 88 | reg axi_awv_awr_flag; 89 | reg axi_arv_arr_flag; 90 | 91 | reg [7:0] axi_awlen_cntr; 92 | reg [7:0] axi_arlen_cntr; 93 | reg [1:0] axi_arburst; 94 | reg [1:0] axi_awburst; 95 | reg [7:0] axi_arlen; 96 | reg [7:0] axi_awlen; 97 | 98 | localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1; 99 | localparam integer OPT_MEM_ADDR_BITS = 3; 100 | 101 | wire [OPT_MEM_ADDR_BITS:0] memory_address; 102 | reg [C_S_AXI_DATA_WIDTH-1:0] outgoing_data; 103 | 104 | assign s_axi_awready = axi_awready; 105 | assign s_axi_wready = axi_wready; 106 | assign s_axi_bresp = axi_bresp; 107 | assign s_axi_buser = axi_buser; 108 | assign s_axi_bvalid = axi_bvalid; 109 | assign s_axi_arready = axi_arready; 110 | assign s_axi_rdata = axi_rdata; 111 | assign s_axi_rresp = axi_rresp; 112 | assign s_axi_rlast = axi_rlast; 113 | assign s_axi_ruser = axi_ruser; 114 | assign s_axi_rvalid = axi_rvalid; 115 | assign s_axi_bid = s_axi_awid; 116 | assign s_axi_rid = s_axi_arid; 117 | assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen)); 118 | assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen)); 119 | assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0; 120 | assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0; 121 | assign s_axi_buser = 0; 122 | 123 | always @(posedge s_axi_aclk) begin 124 | if (s_axi_aresetn == 1'b0) begin 125 | axi_awready <= 1'b0; 126 | axi_awv_awr_flag <= 1'b0; 127 | end 128 | 129 | else begin 130 | if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin 131 | axi_awready <= 1'b1; 132 | axi_awv_awr_flag <= 1'b1; 133 | end 134 | 135 | else if (s_axi_wlast && axi_wready) begin 136 | axi_awv_awr_flag <= 1'b0; 137 | end 138 | 139 | else begin 140 | axi_awready <= 1'b0; 141 | end 142 | end 143 | end 144 | 145 | always @(posedge s_axi_aclk) begin 146 | if (s_axi_aresetn == 1'b0) begin 147 | axi_awaddr <= 0; 148 | axi_awlen_cntr <= 0; 149 | axi_awburst <= 0; 150 | axi_awlen <= 0; 151 | end 152 | 153 | else begin 154 | if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag) begin 155 | axi_awaddr <= s_axi_awaddr[C_S_AXI_ADDR_WIDTH-1:0]; 156 | axi_awburst <= s_axi_awburst; 157 | axi_awlen <= s_axi_awlen; 158 | axi_awlen_cntr <= 0; 159 | end 160 | 161 | else if((axi_awlen_cntr <= axi_awlen) && axi_wready && s_axi_wvalid) begin 162 | axi_awlen_cntr <= axi_awlen_cntr + 1; 163 | 164 | case (axi_awburst) 165 | 2'b00: begin 166 | axi_awaddr <= axi_awaddr; 167 | end 168 | 169 | 2'b01: begin 170 | axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 171 | axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}}; 172 | end 173 | 174 | 2'b10: 175 | if (aw_wrap_en) begin 176 | axi_awaddr <= (axi_awaddr - aw_wrap_size); 177 | end 178 | 179 | else begin 180 | axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 181 | axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}}; 182 | end 183 | 184 | default: begin 185 | axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 186 | end 187 | endcase 188 | end 189 | end 190 | end 191 | 192 | always @(posedge s_axi_aclk) begin 193 | if (s_axi_aresetn == 1'b0) begin 194 | axi_wready <= 1'b0; 195 | end 196 | 197 | else begin 198 | if (~axi_wready && s_axi_wvalid && axi_awv_awr_flag) begin 199 | axi_wready <= 1'b1; 200 | end 201 | //else if (~axi_awv_awr_flag) 202 | else if (s_axi_wlast && axi_wready) begin 203 | axi_wready <= 1'b0; 204 | end 205 | end 206 | end 207 | 208 | always @(posedge s_axi_aclk) begin 209 | if (s_axi_aresetn == 1'b0) begin 210 | axi_bvalid <= 0; 211 | axi_bresp <= 2'b0; 212 | end 213 | 214 | else begin 215 | if (axi_awv_awr_flag && axi_wready && s_axi_wvalid && ~axi_bvalid && s_axi_wlast) begin 216 | axi_bvalid <= 1'b1; 217 | axi_bresp <= 2'b0; 218 | end 219 | 220 | else begin 221 | if (s_axi_bready && axi_bvalid) begin 222 | axi_bvalid <= 1'b0; 223 | end 224 | end 225 | end 226 | end 227 | 228 | always @(posedge s_axi_aclk) begin 229 | if (s_axi_aresetn == 1'b0) begin 230 | axi_arready <= 1'b0; 231 | axi_arv_arr_flag <= 1'b0; 232 | end 233 | 234 | else begin 235 | if (~axi_arready && s_axi_arvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin 236 | axi_arready <= 1'b1; 237 | axi_arv_arr_flag <= 1'b1; 238 | end 239 | 240 | else if (axi_rvalid && s_axi_rready && axi_arlen_cntr == axi_arlen) begin 241 | axi_arv_arr_flag <= 1'b0; 242 | end 243 | 244 | else begin 245 | axi_arready <= 1'b0; 246 | end 247 | end 248 | end 249 | 250 | always @(posedge s_axi_aclk) begin 251 | if (s_axi_aresetn == 1'b0) begin 252 | axi_araddr <= 0; 253 | axi_arlen_cntr <= 0; 254 | axi_arburst <= 0; 255 | axi_arlen <= 0; 256 | axi_rlast <= 1'b0; 257 | end 258 | 259 | else begin 260 | if (~axi_arready && s_axi_arvalid && ~axi_arv_arr_flag) begin 261 | axi_araddr <= s_axi_araddr[C_S_AXI_ADDR_WIDTH - 1:0]; 262 | axi_arburst <= s_axi_arburst; 263 | axi_arlen <= s_axi_arlen; 264 | axi_arlen_cntr <= 0; 265 | axi_rlast <= 1'b0; 266 | end 267 | 268 | else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && s_axi_rready) begin 269 | axi_arlen_cntr <= axi_arlen_cntr + 1; 270 | axi_rlast <= 1'b0; 271 | 272 | case (axi_arburst) 273 | 2'b00: begin 274 | axi_araddr <= axi_araddr; 275 | end 276 | 277 | 2'b01: begin 278 | axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 279 | axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}}; 280 | end 281 | 282 | 2'b10: 283 | if (ar_wrap_en) begin 284 | axi_araddr <= (axi_araddr - ar_wrap_size); 285 | end 286 | 287 | else begin 288 | axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 289 | axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}}; 290 | end 291 | default: begin 292 | axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1; 293 | end 294 | endcase 295 | end 296 | 297 | else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag) begin 298 | axi_rlast <= 1'b1; 299 | end 300 | 301 | else if (s_axi_rready) begin 302 | axi_rlast <= 1'b0; 303 | end 304 | end 305 | end 306 | 307 | always @(posedge s_axi_aclk) begin 308 | if (s_axi_aresetn == 1'b0) begin 309 | axi_rvalid <= 0; 310 | axi_rresp <= 0; 311 | end 312 | 313 | else begin 314 | if (axi_arv_arr_flag && ~axi_rvalid) begin 315 | axi_rvalid <= 1'b1; 316 | axi_rresp <= 2'b0; 317 | end 318 | 319 | else if (axi_rvalid && s_axi_rready) begin 320 | axi_rvalid <= 1'b0; 321 | end 322 | end 323 | end 324 | 325 | assign memory_address = 326 | (axi_arv_arr_flag ? 327 | axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] : 328 | (axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0)); 329 | 330 | wire memory_write_enable = axi_wready && s_axi_wvalid; 331 | wire memory_read_enable = axi_arv_arr_flag; //& ~axi_rvalid 332 | 333 | reg[15:0] sclk_toggle_count; 334 | reg spi_clock_phase; 335 | 336 | localparam SM1_IDLE = 2'b00; 337 | localparam SM1_SELECT_SLAVE = 2'b01; 338 | localparam SM1_TRANSFER_DATA = 2'b10; 339 | reg[1:0] sm1_state; 340 | 341 | localparam SM2_WRITE = 2'b00; 342 | localparam SM2_READ = 2'b01; 343 | localparam SM2_WAIT = 2'b10; 344 | localparam SM2_END_DATA_TRANSFER = 2'b11; 345 | reg[1:0] sm2_state; 346 | 347 | reg wait_after_read; 348 | reg[15:0] num_toggles_to_wait; 349 | reg [7:0] memory [0:MEMORY_SIZE-1]; 350 | 351 | wire CPOL = memory[0][0]; 352 | wire CPHA = memory[0][1]; 353 | wire burst = memory[0][3]; 354 | wire read = memory[0][4]; 355 | 356 | wire[7:0] slave = memory[1]; 357 | wire[7:0] num_clocks_to_skip = memory[2]; 358 | 359 | wire[15:0] outgoing_element_size = {memory[5], memory[4]}; 360 | wire[15:0] num_outgoing_elements = {memory[7], memory[6]}; 361 | wire[15:0] incoming_element_size = {memory[9], memory[8]}; 362 | wire[15:0] num_write_extra_toggles = {memory[11], memory[10]}; 363 | wire[15:0] num_read_extra_toggles = {memory[13], memory[12]}; 364 | 365 | reg[15:0] num_bits_read; 366 | reg[15:0] num_bits_written; 367 | reg[15:0] num_elements_written; 368 | reg[3:0] incoming_byte_bit; 369 | reg[3:0] outgoing_byte_bit; 370 | reg[15:0] num_bytes_read; 371 | reg[15:0] num_bytes_written; 372 | 373 | localparam write_buffer_start = 14; 374 | localparam read_buffer_start = 39; 375 | localparam num_initial_axi_transfer_bytes = read_buffer_start; 376 | 377 | reg[15:0] extra_toggle_count; 378 | integer num_initial_axi_transfer_bytes_received; 379 | integer i; 380 | integer clock_count; 381 | 382 | always @(posedge s_axi_aclk) begin 383 | if (s_axi_aresetn == 1'b0) begin 384 | for (i = 0; i < MEMORY_SIZE - 1; i = i + 1) 385 | memory[i] <= 0; 386 | 387 | clock_count <= 0; 388 | num_initial_axi_transfer_bytes_received <= 0; 389 | num_elements_written <= 0; 390 | num_bits_read <= 0; 391 | num_bits_written <= 0; 392 | incoming_byte_bit <= 0; 393 | outgoing_byte_bit <= 0; 394 | num_bytes_read <= 0; 395 | num_bytes_written <= 0; 396 | extra_toggle_count <= 0; 397 | wait_after_read <= 1'b0; 398 | mosi <= 1'bz; 399 | sclk <= 0; 400 | ss_n <= {NUMBER_OF_SLAVES{1'b1}}; 401 | sclk_toggle_count <= 0; 402 | spi_clock_phase <= 0; 403 | interrupt <= 1'b0; 404 | sm1_state <= SM1_IDLE; 405 | sm2_state <= SM2_WRITE; 406 | end 407 | 408 | else begin 409 | if(memory_write_enable) begin 410 | if (s_axi_wstrb[0]) 411 | memory[(memory_address*4) + 0] <= s_axi_wdata[(0*8+7) -: 8]; 412 | if (s_axi_wstrb[1]) 413 | memory[(memory_address*4) + 1] <= s_axi_wdata[(1*8+7) -: 8]; 414 | if (s_axi_wstrb[2]) 415 | memory[(memory_address*4) + 2] <= s_axi_wdata[(2*8+7) -: 8]; 416 | if (s_axi_wstrb[3]) 417 | memory[(memory_address*4) + 3] <= s_axi_wdata[(3*8+7) -: 8]; 418 | 419 | num_initial_axi_transfer_bytes_received <= 420 | num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3]; 421 | end 422 | 423 | else begin 424 | if(num_initial_axi_transfer_bytes_received == read_buffer_start) begin 425 | if(clock_count == num_clocks_to_skip) begin 426 | clock_count <= 0; 427 | 428 | case(sm1_state) 429 | SM1_IDLE: begin 430 | sclk <= CPOL; 431 | spi_clock_phase <= CPHA; 432 | interrupt <= 1'b0; 433 | sm1_state <= SM1_SELECT_SLAVE; 434 | end 435 | 436 | SM1_SELECT_SLAVE: begin 437 | ss_n[slave] <= 1'b0; 438 | 439 | if(!CPHA) begin 440 | outgoing_byte_bit <= outgoing_byte_bit + 1; 441 | mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit]; 442 | num_bits_written <= num_bits_written + 1; 443 | 444 | if(outgoing_element_size == 1) begin 445 | num_elements_written <= 1; 446 | 447 | if(num_outgoing_elements == 1) begin 448 | if(!num_write_extra_toggles) begin 449 | if(read) 450 | sm2_state <= SM2_READ; 451 | else 452 | sm2_state <= SM2_END_DATA_TRANSFER; 453 | end 454 | 455 | else 456 | sm2_state <= SM2_WAIT; 457 | end 458 | 459 | else begin 460 | if(read) 461 | sm2_state <= SM2_READ; 462 | else 463 | sm2_state <= SM2_WRITE; 464 | end 465 | end 466 | 467 | else 468 | sm2_state <= SM2_WRITE; 469 | end 470 | 471 | sm1_state <= SM1_TRANSFER_DATA; 472 | end 473 | 474 | SM1_TRANSFER_DATA: begin 475 | sclk <= ~sclk; 476 | spi_clock_phase <= ~spi_clock_phase; 477 | sclk_toggle_count <= sclk_toggle_count + 1; 478 | 479 | case(sm2_state) 480 | SM2_WRITE: begin 481 | if(spi_clock_phase) begin 482 | outgoing_byte_bit <= outgoing_byte_bit + 1; 483 | 484 | if(outgoing_byte_bit == 7) begin 485 | num_bytes_written <= num_bytes_written + 1; 486 | outgoing_byte_bit <= 0; 487 | end 488 | 489 | mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit]; 490 | num_bits_written <= num_bits_written + 1; 491 | 492 | if(num_bits_written == outgoing_element_size - 1) begin 493 | num_elements_written <= num_elements_written + 1; 494 | 495 | if(burst) begin 496 | if(num_elements_written == num_outgoing_elements - 1) begin 497 | if(!num_write_extra_toggles) 498 | sm2_state <= SM2_END_DATA_TRANSFER; 499 | else 500 | sm2_state <= SM2_WAIT; 501 | end 502 | 503 | else 504 | num_bits_written <= 0; 505 | end 506 | 507 | else begin 508 | if(!num_write_extra_toggles) 509 | if(read) 510 | sm2_state <= SM2_READ; 511 | else 512 | sm2_state <= SM2_END_DATA_TRANSFER; 513 | else 514 | sm2_state <= SM2_WAIT; 515 | end 516 | end 517 | end 518 | end 519 | 520 | SM2_READ: begin 521 | if(!spi_clock_phase) begin 522 | incoming_byte_bit <= incoming_byte_bit + 1; 523 | 524 | if(incoming_byte_bit == 7) begin 525 | num_bytes_read <= num_bytes_read + 1; 526 | incoming_byte_bit <= 0; 527 | end 528 | 529 | memory[read_buffer_start + num_bytes_read][incoming_byte_bit] <= miso; 530 | num_bits_read <= num_bits_read + 1; 531 | 532 | if(num_bits_read == incoming_element_size - 1) begin 533 | if(!num_read_extra_toggles) 534 | sm2_state <= SM2_END_DATA_TRANSFER; 535 | else begin 536 | wait_after_read <= 1'b1; 537 | sm2_state <= SM2_WAIT; 538 | end 539 | end 540 | end 541 | end 542 | 543 | SM2_WAIT: begin 544 | extra_toggle_count <= extra_toggle_count + 1; 545 | 546 | if(wait_after_read) begin 547 | if(extra_toggle_count == (num_read_extra_toggles - 1)) begin 548 | extra_toggle_count <= 0; 549 | sm2_state <= SM2_END_DATA_TRANSFER; 550 | end 551 | end 552 | 553 | else begin 554 | if(extra_toggle_count == (num_write_extra_toggles - 1)) begin 555 | extra_toggle_count <= 0; 556 | 557 | if(read) 558 | sm2_state <= SM2_READ; 559 | else 560 | sm2_state <= SM2_END_DATA_TRANSFER; 561 | end 562 | end 563 | end 564 | 565 | SM2_END_DATA_TRANSFER: begin 566 | sclk <= CPOL; 567 | spi_clock_phase <= CPHA; 568 | sclk_toggle_count <= 0; 569 | ss_n[slave] <= 1'b1; 570 | mosi <= 1'bz; 571 | num_bits_read <= 0; 572 | num_bits_written <= 0; 573 | 574 | if(num_elements_written == num_outgoing_elements) begin 575 | num_initial_axi_transfer_bytes_received <= 0; 576 | interrupt <= 1'b1; 577 | num_elements_written <= 0; 578 | num_bytes_written <= 0; 579 | sm1_state <= SM1_IDLE; 580 | end 581 | 582 | else 583 | sm1_state <= SM1_SELECT_SLAVE; 584 | end 585 | endcase 586 | end 587 | endcase 588 | end 589 | 590 | else 591 | clock_count <= clock_count + 1; 592 | end 593 | end 594 | end 595 | end 596 | 597 | always @(posedge s_axi_aclk) begin 598 | if (memory_read_enable) begin 599 | outgoing_data[(0*8+7) -: 8] <= memory[(memory_address*4) + 0]; 600 | outgoing_data[(1*8+7) -: 8] <= memory[(memory_address*4) + 1]; 601 | outgoing_data[(2*8+7) -: 8] <= memory[(memory_address*4) + 2]; 602 | outgoing_data[(3*8+7) -: 8] <= memory[(memory_address*4) + 3]; 603 | end 604 | end 605 | 606 | always @(outgoing_data, axi_rvalid) begin 607 | if (axi_rvalid) begin 608 | axi_rdata <= outgoing_data; 609 | end 610 | 611 | else begin 612 | axi_rdata <= 32'h00000000; 613 | end 614 | end 615 | 616 | endmodule 617 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /tests/quick_spi_soft_tests/__Previews/quick_spi_soft_tests.vPreview: -------------------------------------------------------------------------------- 1 | [Preview] 2 | LargeImageOriginalSize=708000 3 | LargeImageWidth=354 4 | LargeImageHeight=500 5 | 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