├── .gitignore ├── .gitmodules ├── LICENSE ├── Readme.md ├── doc ├── anklesoc_arch.drawio ├── anklesoc_arch.png ├── anklesoc_logo.png ├── hazard2_pipeline.drawio └── hazard2_pipeline.png ├── hdl ├── .gitignore ├── anklesoc.py ├── generate.py └── hazard2.py ├── sim ├── blinky │ ├── Makefile │ ├── blinky.S │ └── blinky.gtkw ├── common │ ├── init.S │ ├── memmap.ld │ ├── memmap_cpubench.ld │ ├── platform_defs.h │ ├── soft_uart.S │ ├── soft_uart.h │ ├── src_only_app.mk │ └── tb_io.h ├── hello_asm │ ├── Makefile │ ├── hello_asm.S │ └── hello_asm.gtkw ├── hello_uart_asm │ ├── Makefile │ └── hello_uart_asm.S ├── hello_uart_c │ ├── Makefile │ └── hello_uart.c ├── riscv-compliance │ ├── .gitignore │ ├── Makefile │ ├── compare_testvec │ ├── include │ │ ├── arch_test.h │ │ ├── encoding.h │ │ └── model_test.h │ ├── memmap.ld │ └── test.gtkw ├── soc.gtkw ├── tb_cpu.py └── tb_soc.py └── synth ├── .gitignore └── synth_soc.py /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/.gitmodules -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/LICENSE -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/Readme.md -------------------------------------------------------------------------------- /doc/anklesoc_arch.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/doc/anklesoc_arch.drawio -------------------------------------------------------------------------------- /doc/anklesoc_arch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/doc/anklesoc_arch.png -------------------------------------------------------------------------------- /doc/anklesoc_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/doc/anklesoc_logo.png -------------------------------------------------------------------------------- /doc/hazard2_pipeline.drawio: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/doc/hazard2_pipeline.drawio -------------------------------------------------------------------------------- /doc/hazard2_pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/doc/hazard2_pipeline.png -------------------------------------------------------------------------------- /hdl/.gitignore: -------------------------------------------------------------------------------- 1 | hazard2_cpu.v 2 | -------------------------------------------------------------------------------- /hdl/anklesoc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/hdl/anklesoc.py -------------------------------------------------------------------------------- /hdl/generate.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/hdl/generate.py -------------------------------------------------------------------------------- /hdl/hazard2.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/hdl/hazard2.py -------------------------------------------------------------------------------- /sim/blinky/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/blinky/Makefile -------------------------------------------------------------------------------- /sim/blinky/blinky.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/blinky/blinky.S -------------------------------------------------------------------------------- /sim/blinky/blinky.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/blinky/blinky.gtkw -------------------------------------------------------------------------------- /sim/common/init.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/init.S -------------------------------------------------------------------------------- /sim/common/memmap.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/memmap.ld -------------------------------------------------------------------------------- /sim/common/memmap_cpubench.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/memmap_cpubench.ld -------------------------------------------------------------------------------- /sim/common/platform_defs.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/platform_defs.h -------------------------------------------------------------------------------- /sim/common/soft_uart.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/soft_uart.S -------------------------------------------------------------------------------- /sim/common/soft_uart.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/soft_uart.h -------------------------------------------------------------------------------- /sim/common/src_only_app.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/src_only_app.mk -------------------------------------------------------------------------------- /sim/common/tb_io.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/common/tb_io.h -------------------------------------------------------------------------------- /sim/hello_asm/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_asm/Makefile -------------------------------------------------------------------------------- /sim/hello_asm/hello_asm.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_asm/hello_asm.S -------------------------------------------------------------------------------- /sim/hello_asm/hello_asm.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_asm/hello_asm.gtkw -------------------------------------------------------------------------------- /sim/hello_uart_asm/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_uart_asm/Makefile -------------------------------------------------------------------------------- /sim/hello_uart_asm/hello_uart_asm.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_uart_asm/hello_uart_asm.S -------------------------------------------------------------------------------- /sim/hello_uart_c/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_uart_c/Makefile -------------------------------------------------------------------------------- /sim/hello_uart_c/hello_uart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/hello_uart_c/hello_uart.c -------------------------------------------------------------------------------- /sim/riscv-compliance/.gitignore: -------------------------------------------------------------------------------- 1 | tmp 2 | -------------------------------------------------------------------------------- /sim/riscv-compliance/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/riscv-compliance/Makefile -------------------------------------------------------------------------------- /sim/riscv-compliance/compare_testvec: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/riscv-compliance/compare_testvec -------------------------------------------------------------------------------- /sim/riscv-compliance/include/arch_test.h: -------------------------------------------------------------------------------- 1 | ../riscv-arch-test/riscv-test-env/arch_test.h -------------------------------------------------------------------------------- /sim/riscv-compliance/include/encoding.h: -------------------------------------------------------------------------------- 1 | ../riscv-arch-test/riscv-test-env/encoding.h -------------------------------------------------------------------------------- /sim/riscv-compliance/include/model_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/riscv-compliance/include/model_test.h -------------------------------------------------------------------------------- /sim/riscv-compliance/memmap.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/riscv-compliance/memmap.ld -------------------------------------------------------------------------------- /sim/riscv-compliance/test.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/riscv-compliance/test.gtkw -------------------------------------------------------------------------------- /sim/soc.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/soc.gtkw -------------------------------------------------------------------------------- /sim/tb_cpu.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/tb_cpu.py -------------------------------------------------------------------------------- /sim/tb_soc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/sim/tb_soc.py -------------------------------------------------------------------------------- /synth/.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | -------------------------------------------------------------------------------- /synth/synth_soc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Wren6991/Hazard2/HEAD/synth/synth_soc.py --------------------------------------------------------------------------------