├── README.md
├── Lab06
    ├── B2BCD_IP.v
    └── UT_TOP.v
├── Lab02
    ├── TT.v
    ├── TT.2.v
    └── TT.1.v
├── Lab03
    └── BP.v
├── Lab01
    └── HD.v
├── Lab05
    └── MMSA.v
├── Lab07
    └── CDC.v
├── Lab09
    └── FD.sv
├── Lab10
    ├── dram.dat
    └── PATTERN.sv
├── Lab08
    └── SP.v
├── Midterm
    └── EDH.v
├── Final
    └── MH.v
├── Lab11
    └── MMSA.v
└── Lab04
    └── NN.v


/README.md:
--------------------------------------------------------------------------------
 1 | # 交大 ICLAB 2022 FALL Code 分享
 2 | 
 3 | > [交大 ICLAB 2022 FALL 修課分享 - Dcard](https://www.dcard.tw/f/graduate_school/p/240982318?cid=c9143783-859d-48e6-94dc-cd59db93382c)
 4 | 
 5 | ## Performance
 6 | 
 7 | ```
 8 | Lab01      - No.66   [1.002 (2), 1.006 (3), 1.008 (4), 1.008 (5), 1.123 (66)]
 9 | Lab02      - No. 1   [1.010 (2), 1.075 (3), 1.382 (4), 1.391 (5)]
10 | Lab03      - No. 2   [1.044 (2), 1.063 (3), 1.091 (4), 1.131 (5)]
11 | Lab04      - No. 4   [1.034 (2), 1.051 (3), 1.055 (4), 1.057 (5)]
12 | Lab05      - No. 1*  [1.110 (2), 1.165 (3), 1.213 (4), 1.400 (5)]
13 | Lab06      - No. 1   [1.213 (2), 1.792 (3), 2.383 (4), 2.761 (5)]
14 | Lab07      - No. 2   [1.152 (2), 1.375 (3), 1.644 (4), 1.710 (5)]
15 | Lab08      - No. 1   [1.744 (2), 2.991 (3), 2.993 (4), 3.329 (5)]
16 | Lab09      - No. 2   [1.047 (2), 1.081 (3), 1.084 (4), 1.230 (5)]
17 | Lab10      - No. 1*  [1.001 (2), 1.024 (3), 1.025 (4), 1.027 (5)]
18 | Lab11      - No. 1 - [2.578 (2), 4.559 (3), 5.666 (4), 7.797 (5)]
19 | Lab12      - No. 0   []
20 | Midterm    - No. 2   [1.047 (2), 1.229 (3), 1.299 (4), 1.521 (5)]
21 | Final      - No. 1   [1.067 (2), 1.250 (3), 1.274 (4), 1.867 (5)]
22 | ('*': Best code, '-': 2nd demo)
23 | ```
24 | 


--------------------------------------------------------------------------------
/Lab06/B2BCD_IP.v:
--------------------------------------------------------------------------------
 1 | //############################################################################
 2 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 | //   File Name   : B2BCD_IP.v
 4 | //   Module Name : B2BCD_IP
 5 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 6 | //############################################################################
 7 | 
 8 | module B2BCD_IP #(parameter WIDTH = 4, parameter DIGIT = 2) (
 9 |     // Input signals
10 |     Binary_code,
11 |     // Output signals
12 |     BCD_code
13 | );
14 | 
15 | // ===============================================================
16 | // Declaration
17 | // ===============================================================
18 | input  [WIDTH-1:0]   Binary_code;
19 | output [DIGIT*4-1:0] BCD_code;
20 | 
21 | // ===============================================================
22 | // Soft IP DESIGN
23 | // ===============================================================
24 | 
25 | wire [WIDTH - 1:0] binary_shift [0:WIDTH - 1];
26 | wire [3:0] BCD_add3 [0:WIDTH - 1][0:DIGIT - 1];
27 | wire [3:0] BCD_shift [0:WIDTH - 1][0:DIGIT - 1]; 
28 | 
29 | genvar gv_j, gv_i;
30 | 
31 | assign binary_shift[0] = Binary_code;
32 | generate
33 | 	for (gv_i = 1; gv_i < WIDTH; gv_i = gv_i + 1) begin
34 | 		assign binary_shift[gv_i] = {binary_shift[gv_i - 1][WIDTH - 2:0], 1'b0};
35 | 	end
36 | endgenerate
37 | 
38 | generate
39 | 	for (gv_j = 0; gv_j < DIGIT; gv_j = gv_j + 1) begin
40 | 		assign BCD_add3[0][gv_j] = 4'b0;
41 | 	end
42 | 	for (gv_i = 1; gv_i < WIDTH; gv_i = gv_i + 1) begin
43 | 		for (gv_j = 0; gv_j < DIGIT; gv_j = gv_j + 1) begin
44 | 			//if (gv_j * 4 - 1 <= gv_i - 1) begin
45 | 				assign BCD_add3[gv_i][gv_j] = (BCD_shift[gv_i - 1][gv_j] > 4'd4 ? BCD_shift[gv_i - 1][gv_j] + 4'd3 : BCD_shift[gv_i - 1][gv_j]);
46 | 			/*end
47 | 			else begin
48 | 				assign BCD_add3[gv_i][gv_j] = BCD_shift[gv_i - 1][gv_j];
49 | 			end*/
50 | 		end
51 | 	end
52 | endgenerate
53 | 
54 | generate
55 | 	for (gv_i = 0; gv_i < WIDTH; gv_i = gv_i + 1) begin
56 | 		assign BCD_shift[gv_i][0] = {BCD_add3[gv_i][0][2:0], binary_shift[gv_i][WIDTH - 1]};
57 | 		for (gv_j = 1; gv_j < DIGIT; gv_j = gv_j + 1) begin
58 | 			assign BCD_shift[gv_i][gv_j] = {BCD_add3[gv_i][gv_j][2:0], BCD_add3[gv_i][gv_j - 1][3]};
59 | 		end
60 | 	end
61 | endgenerate
62 | 
63 | generate
64 | 	assign BCD_code[0] = BCD_shift[WIDTH - 1][0][0];
65 | 	assign BCD_code[1] = BCD_shift[WIDTH - 1][0][1];
66 | 	assign BCD_code[2] = BCD_shift[WIDTH - 1][0][2];
67 | 	assign BCD_code[3] = BCD_shift[WIDTH - 1][0][3];
68 | 	for (gv_j = 1; gv_j < DIGIT; gv_j = gv_j + 1) begin
69 | 		assign BCD_code[gv_j * 4    ] = BCD_shift[WIDTH - 1][gv_j][0];
70 | 		assign BCD_code[gv_j * 4 + 1] = BCD_shift[WIDTH - 1][gv_j][1];
71 | 		assign BCD_code[gv_j * 4 + 2] = BCD_shift[WIDTH - 1][gv_j][2];
72 | 		assign BCD_code[gv_j * 4 + 3] = BCD_shift[WIDTH - 1][gv_j][3];
73 | 	end
74 | endgenerate
75 | 
76 | endmodule
77 | 


--------------------------------------------------------------------------------
/Lab02/TT.v:
--------------------------------------------------------------------------------
  1 | module TT(
  2 | 	//Input Port
  3 | 	clk,
  4 | 	rst_n,
  5 | 	in_valid,
  6 | 	source,
  7 | 	destination,
  8 | 
  9 | 	//Output Port
 10 | 	out_valid,
 11 | 	cost
 12 | 	);
 13 | 
 14 | input			   clk, rst_n, in_valid;
 15 | input	   [3:0]   source;
 16 | input	   [3:0]   destination;
 17 | 
 18 | output reg		  out_valid;
 19 | output reg  [3:0]   cost;
 20 | 
 21 | //==============================================//
 22 | reg [1:0] state, nxt_state;
 23 | localparam Idle		= 2'd3;
 24 | localparam Read		= 2'd0;
 25 | localparam Bfs		= 2'd1;
 26 | localparam Output1	= 2'd2;
 27 | 
 28 | reg [3:0] s, d;
 29 | reg adj [0:15][0:15];
 30 | reg vis [0:15];
 31 | reg [3:0] dis;
 32 | wire [3:0] dis_add_1 = dis + 4'd1;
 33 | 
 34 | integer i, j;
 35 | genvar gv_i, gv_j;
 36 | 
 37 | wire adj_next [0:15][0:15];
 38 | generate
 39 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 40 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 41 | 			assign adj_next[gv_i][gv_j] = ((gv_i == source && gv_j == destination) || (gv_i == destination && gv_j == source) ? 1'b1 : adj[gv_i][gv_j]);
 42 | 		end
 43 | 	end
 44 | endgenerate
 45 | 
 46 | wor vis_next [0:15];
 47 | generate
 48 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 49 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 50 | 			if (gv_j < gv_i) begin
 51 | 				assign vis_next[gv_i] = (vis[gv_j] && adj[gv_j][gv_i]);
 52 | 			end
 53 | 			else if (gv_j == gv_i) begin
 54 | 				assign vis_next[gv_i] = vis[gv_j];
 55 | 			end
 56 | 			else if (gv_j > gv_i) begin
 57 | 				assign vis_next[gv_i] = (vis[gv_j] && adj[gv_i][gv_j]);
 58 | 			end
 59 | 		end
 60 | 	end
 61 | endgenerate
 62 | 
 63 | wire bfs_found = vis_next[d];
 64 | wand bfs_end;
 65 | generate
 66 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 67 | 		assign bfs_end = (vis[gv_i] == vis_next[gv_i]);
 68 | 	end
 69 | endgenerate
 70 | 
 71 | always @(*) begin
 72 | 	nxt_state <= state;
 73 | 	case(state)
 74 | 		Idle :
 75 | 			if (in_valid) nxt_state <= Read;
 76 | 		Read :
 77 | 			if (!in_valid) begin
 78 | 				if (bfs_found) nxt_state <= Output1;
 79 | 				else nxt_state <= Bfs;
 80 | 			end
 81 | 		Bfs : 
 82 | 			if (bfs_found || bfs_end) nxt_state <= Idle;
 83 | 		Output1 : nxt_state <= Idle;
 84 | 	endcase
 85 | end
 86 | 
 87 | always @(posedge clk or negedge rst_n) begin
 88 | 	if(!rst_n) state <= Idle;
 89 | 	else state <= nxt_state;
 90 | end
 91 | 
 92 | always @(posedge clk) begin
 93 | 	for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'bx; //
 94 | 	dis <= 4'bx; //
 95 | 	case (state)
 96 | 		Idle : begin
 97 | 			for (i = 0; i <= 15; i = i + 1)
 98 | 				for (j = i + 1; j <= 15; j = j + 1) adj[i][j] <= 1'b0;
 99 | 			//if (in_valid) begin
100 | 				//s <= source;
101 | 				d <= destination;
102 | 
103 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'b0;
104 | 				vis[source] <= 1'b1;
105 | 				dis <= 4'd0;
106 | 			//end
107 | 		end
108 | 		Read : begin
109 | 			if (in_valid) begin
110 | 				for (i = 0; i <= 15; i = i + 1)
111 | 					for (j = i + 1; j <= 15; j = j + 1) adj[i][j] <= adj_next[i][j];
112 | 
113 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis[i];
114 | 				dis <= 4'd0;
115 | 			end
116 | 			else begin
117 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next[i];
118 | 				dis <= dis_add_1;
119 | 			end
120 | 		end
121 | 		Bfs : begin
122 | 			for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next[i];
123 | 			dis <= dis_add_1;
124 | 		end
125 | 	endcase
126 | end
127 | 
128 | always @(*) begin
129 | 	out_valid <= 1'b0;
130 | 	cost <= 4'b0;
131 | 	case (state)
132 | 		Bfs : begin
133 | 			if (bfs_found) begin
134 | 				out_valid <= 1'b1;
135 | 				cost <= dis_add_1;
136 | 			end
137 | 			else if (bfs_end) begin
138 | 				out_valid <= 1'b1;
139 | 				cost <= 4'd0;
140 | 			end
141 | 		end
142 | 		Output1 : begin
143 | 			out_valid <= 1'b1;
144 | 			cost <= 4'd1;
145 | 		end
146 | 	endcase
147 | end
148 | 
149 | endmodule 
150 | 


--------------------------------------------------------------------------------
/Lab03/BP.v:
--------------------------------------------------------------------------------
  1 | module BP(
  2 |   clk,
  3 |   rst_n,
  4 |   in_valid,
  5 |   guy,
  6 |   in0,
  7 |   in1,
  8 |   in2,
  9 |   in3,
 10 |   in4,
 11 |   in5,
 12 |   in6,
 13 |   in7,
 14 |   
 15 |   out_valid,
 16 |   out
 17 | );
 18 | 
 19 | input             clk, rst_n;
 20 | input             in_valid;
 21 | input       [2:0] guy;
 22 | input       [1:0] in0, in1, in2, in3, in4, in5, in6, in7;
 23 | output reg        out_valid;
 24 | output reg  [1:0] out;
 25 | //=====+++++-----!!!!!//    
 26 | localparam MOV_STOP		= 2'd0;
 27 | localparam MOV_RIGHT	= 2'd1;
 28 | localparam MOV_LEFT		= 2'd2;
 29 | localparam MOV_JUMP		= 2'd3;
 30 | integer i;
 31 | 
 32 | reg in_flag;
 33 | reg [2:0] in_pos;
 34 | reg in_jump;
 35 | always @(*) begin
 36 | 	in_flag <= |in0;
 37 | 	in_pos <= 3'bx;
 38 | 	case (1'b0) // synopsys parallel_case
 39 | 		in0[0], in0[1] : in_pos <= 3'd0;
 40 | 		in1[0], in1[1] : in_pos <= 3'd1;
 41 | 		in2[0], in2[1] : in_pos <= 3'd2;
 42 | 		in3[0], in3[1] : in_pos <= 3'd3;
 43 | 		in4[0], in4[1] : in_pos <= 3'd4;
 44 | 		in5[0], in5[1] : in_pos <= 3'd5;
 45 | 		in6[0], in6[1] : in_pos <= 3'd6;
 46 | 		in7[0], in7[1] : in_pos <= 3'd7;
 47 | 	endcase
 48 | 	in_jump <= in0[0] & in1[0] & in2[0] & in3[0] & in4[0] & in5[0] & in6[0] & in7[0];
 49 | end
 50 | 
 51 | reg [2:0] player;
 52 | wire [2:0] player_right = player + 3'd1;
 53 | wire [2:0] player_left = player - 3'd1;
 54 | reg flag [1:4];
 55 | reg [2:0] pos [1:4];
 56 | reg [1:0] ans [5:64];
 57 | 
 58 | reg [1:0] mov;
 59 | reg [2:0] player_next;
 60 | reg [2:0] target;
 61 | always @(*) begin
 62 | 	target <= 3'd3;
 63 | 	if (in_valid && in_flag) target <= in_pos;
 64 | 	for (i = 1; i <= 4; i = i + 1) begin
 65 | 		if (flag[i]) target <= pos[i];
 66 | 	end
 67 | end
 68 | always @(*) begin
 69 | 	if (!flag[4] && pos[4][0]) mov <= MOV_JUMP;
 70 | 	else if (player == target) mov <= MOV_STOP;
 71 | 	else if (player < target) mov <= MOV_RIGHT;
 72 | 	else mov <= MOV_LEFT;
 73 | 
 74 | 	if (!flag[4] && pos[4][0]) player_next <= player;
 75 | 	else if (player == target) player_next <= player;
 76 | 	else if (player < target) player_next <= player_right;
 77 | 	else player_next <= player_left;
 78 | end
 79 | 
 80 | reg in_valid_last;
 81 | always @(posedge clk or negedge rst_n) begin
 82 | 	if (!rst_n) in_valid_last <= 1'b0;
 83 | 	else in_valid_last <= in_valid;
 84 | end
 85 | wire in_valid_begin = !in_valid_last && in_valid;
 86 | wire in_valid_end = in_valid_last && !in_valid;
 87 | 
 88 | reg [5:0] cnt;
 89 | always @(posedge clk or negedge rst_n) begin
 90 | 	if (!rst_n) begin
 91 | 		cnt <= 6'd0;
 92 | 	end
 93 | 	else begin
 94 | 		if (in_valid_end) cnt <= 6'd1;
 95 | 		else if (cnt) cnt <= cnt + 6'd1;
 96 | 	end
 97 | end
 98 | 
 99 | always @(posedge clk) begin
100 | 	player <= 3'bx; //
101 | 	for (i = 1; i <= 4; i = i + 1) begin //
102 | 		flag[i] <= 1'bx;
103 | 		pos[i] <= 3'bx;
104 | 	end
105 | 	for (i = 5; i <= 64; i = i + 1) ans[i] <= 2'bx; //
106 | 
107 | 	if (in_valid_begin) begin
108 | 		player <= guy;
109 | 		for (i = 2; i <= 4; i = i + 1) begin
110 | 			flag[i] <= 1'b0;
111 | 			pos[i][0] <= 1'b0;
112 | 		end
113 | 		flag[1] <= 1'b1;
114 | 		pos[1] <= guy;
115 | 	end
116 | 	else begin
117 | 		player <= player_next;
118 | 		for (i = 2; i <= 4; i = i + 1) begin
119 | 			flag[i] <= flag[i - 1];
120 | 			pos[i] <= pos[i - 1];
121 | 		end
122 | 		if (in_valid) begin
123 | 			if (in_flag && in_jump) begin
124 | 				flag[2] <= 1'b1;
125 | 				pos[2] <= in_pos;
126 | 				flag[1] <= 1'b0;
127 | 				pos[1][0] <= 1'b1;
128 | 			end
129 | 			else begin
130 | 				flag[1] <= in_flag;
131 | 				if (in_flag) pos[1] <= in_pos;
132 | 				else pos[1][0] <= 1'b0;
133 | 			end
134 | 		end
135 | 		else begin
136 | 			flag[1] <= 1'b0;
137 | 			pos[1][0] <= 1'b0;
138 | 		end
139 | 	end
140 | 	for (i = 6; i <= 64; i = i + 1) ans[i] <= ans[i - 1];
141 | 	ans[5] <= mov;
142 | end
143 | 
144 | always @(*) begin
145 | 	out_valid <= 1'b0;
146 | 	out <= 2'b00;
147 | 	if (cnt) begin
148 | 		out_valid <= 1'b1;
149 | 		out <= ans[64];
150 | 	end
151 | end
152 | 
153 | endmodule
154 | 
155 | 


--------------------------------------------------------------------------------
/Lab02/TT.2.v:
--------------------------------------------------------------------------------
  1 | module TT(
  2 | 	//Input Port
  3 | 	clk,
  4 | 	rst_n,
  5 | 	in_valid,
  6 | 	source,
  7 | 	destination,
  8 | 
  9 | 	//Output Port
 10 | 	out_valid,
 11 | 	cost
 12 | 	);
 13 | 
 14 | input			   clk, rst_n, in_valid;
 15 | input	   [3:0]   source;
 16 | input	   [3:0]   destination;
 17 | 
 18 | output reg		  out_valid;
 19 | output reg  [3:0]   cost;
 20 | 
 21 | //==============================================//
 22 | reg [1:0] state, nxt_state;
 23 | localparam Idle		= 2'd0;
 24 | localparam Read		= 2'd3;
 25 | localparam Bfs		= 2'd1;
 26 | localparam Output	= 2'd2;
 27 | 
 28 | reg [3:0] s, d;
 29 | reg adj [0:15][0:15];
 30 | reg vis [0:15];
 31 | reg [2:0] dis2;
 32 | wire [2:0] dis2_add_1 = dis2 + 3'd1;
 33 | reg output1;
 34 | 
 35 | integer i, j;
 36 | genvar gv_i, gv_j;
 37 | 
 38 | wor vis_next1 [0:15];
 39 | generate
 40 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 41 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 42 | 			if (gv_j < gv_i) begin
 43 | 				assign vis_next1[gv_i] = (vis[gv_j] && adj[gv_j][gv_i]);
 44 | 			end
 45 | 			else if (gv_j == gv_i) begin
 46 | 				assign vis_next1[gv_i] = vis[gv_j];
 47 | 			end
 48 | 			else if (gv_j > gv_i) begin
 49 | 				assign vis_next1[gv_i] = (vis[gv_j] && adj[gv_i][gv_j]);
 50 | 			end
 51 | 		end
 52 | 	end
 53 | endgenerate
 54 | wor vis_next2 [0:15];
 55 | generate
 56 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 57 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 58 | 			if (gv_j < gv_i) begin
 59 | 				assign vis_next2[gv_i] = (vis_next1[gv_j] && adj[gv_j][gv_i]);
 60 | 			end
 61 | 			else if (gv_j == gv_i) begin
 62 | 				assign vis_next2[gv_i] = vis_next1[gv_j];
 63 | 			end
 64 | 			else if (gv_j > gv_i) begin
 65 | 				assign vis_next2[gv_i] = (vis_next1[gv_j] && adj[gv_i][gv_j]);
 66 | 			end
 67 | 		end
 68 | 	end
 69 | endgenerate
 70 | 
 71 | wire bfs_found1 = vis_next1[d];
 72 | wire bfs_found2 = vis_next2[d];
 73 | wire bfs_found = bfs_found1 || bfs_found2;
 74 | 
 75 | wand bfs_end;
 76 | generate
 77 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 78 | 		assign bfs_end = (vis[gv_i] == vis_next2[gv_i]);
 79 | 	end
 80 | endgenerate
 81 | 
 82 | always @(*) begin
 83 | 	nxt_state <= state;
 84 | 	case(state)
 85 | 		Idle :
 86 | 			if (in_valid) nxt_state <= Read;
 87 | 		Read :
 88 | 			if (!in_valid) begin
 89 | 				if (bfs_found) nxt_state <= Output;
 90 | 				else nxt_state <= Bfs;
 91 | 			end
 92 | 		Bfs : 
 93 | 			if (bfs_found || bfs_end) nxt_state <= Idle;
 94 | 		Output : nxt_state <= Idle;
 95 | 	endcase
 96 | end
 97 | 
 98 | always @(posedge clk or negedge rst_n) begin
 99 | 	if(!rst_n) state <= Idle;
100 | 	else state <= nxt_state;
101 | end
102 | 
103 | always @(posedge clk) begin
104 | 	for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'bx; //
105 | 	dis2 <= 3'bx; //
106 | 	case (state)
107 | 		Idle : begin
108 | 			for (i = 0; i <= 15; i = i + 1)
109 | 				for (j = i + 1; j <= 15; j = j + 1) adj[i][j] <= 1'b0;
110 | 			//if (in_valid) begin
111 | 				//s <= source;
112 | 				d <= destination;
113 | 
114 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'b0;
115 | 				vis[source] <= 1'b1;
116 | 				dis2 <= 3'd0;
117 | 			//end
118 | 		end
119 | 		Read : begin
120 | 			if (in_valid) begin
121 | 				//if (source < destination)
122 | 					adj[source][destination] <= 1'b1;
123 | 				//else /*if (destination < source)*/
124 | 					adj[destination][source] <= 1'b1;
125 | 
126 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis[i];
127 | 				dis2 <= 3'd0;
128 | 			end
129 | 			else begin
130 | 				output1 <= bfs_found1;
131 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next2[i];
132 | 				dis2 <= dis2_add_1;
133 | 			end
134 | 		end
135 | 		Bfs : begin
136 | 			for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next2[i];
137 | 			dis2 <= dis2_add_1;
138 | 		end
139 | 	endcase
140 | end
141 | 
142 | always @(*) begin
143 | 	out_valid <= 1'b0;
144 | 	cost <= 4'b0;
145 | 	case (state)
146 | 		Bfs : begin
147 | 			if (bfs_found) begin
148 | 				out_valid <= 1'b1;
149 | 				cost <= bfs_found1 ? {dis2, 1'b1} : {dis2_add_1, 1'b0};
150 | 			end
151 | 			else if (bfs_end) begin
152 | 				out_valid <= 1'b1;
153 | 				cost <= 4'd0;
154 | 			end
155 | 		end
156 | 		Output : begin
157 | 			out_valid <= 1'b1;
158 | 			cost <= output1 ? 4'd1 : 4'd2;
159 | 		end
160 | 	endcase
161 | end
162 | 
163 | endmodule 
164 | 


--------------------------------------------------------------------------------
/Lab01/HD.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | 
  3 | `include ...
  4 | 
  5 | // synopsys translate_on
  6 | 
  7 | module HD(code_word1, code_word2, out_n);
  8 | input [6:0] code_word1;
  9 | input [6:0] code_word2;
 10 | output signed [5:0] out_n;
 11 | 
 12 | wire eb1;
 13 | wire signed [3:0] c1;
 14 | HD_cwc cwc1(code_word1, eb1, c1);
 15 | wire eb2;
 16 | wire signed [3:0] c2;
 17 | HD_cwc cwc2(code_word2, eb2, c2);
 18 | 
 19 | reg signed [5:0] a, b;
 20 | reg add_sub;
 21 | always @(*) begin
 22 | 	/*
 23 | 	a <= (eb1 ? c1 : (c1 << 1));
 24 | 	b <= (eb1 ? (c2 << 1) : c2);
 25 | 	add_sub <= eb1 ^ eb2;
 26 | 	*/
 27 | 	case ({eb1, eb2})
 28 | 		2'b00, 2'b01 : a <= (c1 << 1);
 29 | 		2'b10, 2'b11 : a <= c1;
 30 | 	endcase
 31 | 	case ({eb1, eb2})
 32 | 		2'b00, 2'b01 : b <= c2;
 33 | 		2'b10, 2'b11 : b <= (c2 << 1);
 34 | 	endcase
 35 | 	case ({eb1, eb2})
 36 | 		2'b00, 2'b11 : add_sub <= 1'b0;
 37 | 		2'b01, 2'b10 : add_sub <= 1'b1;
 38 | 	endcase
 39 | end
 40 | 
 41 | DW01_addsub #(6) addsuber (.A(a), .B(b), .CI(1'b0), .ADD_SUB(add_sub), .SUM(out_n), .CO());
 42 | //ADDSUB#(.width(6)) adder(a, b, add_sub, out_n);
 43 | 
 44 | endmodule
 45 | 
 46 | module HD_cwc(code_word, eb, c); // codeword correction
 47 | input [6:0] code_word;
 48 | output reg eb; // error bit
 49 | output reg signed [3:0] c; // correct original information
 50 | 
 51 | wire circle1 = code_word[6] ^ code_word[3] ^ code_word[2] ^ code_word[1];
 52 | wire circle2 = code_word[5] ^ code_word[3] ^ code_word[2] ^ code_word[0];
 53 | wire circle3 = code_word[4] ^ code_word[3] ^ code_word[1] ^ code_word[0];
 54 | always @(*) begin
 55 | 	eb <= 1'bx;
 56 | 	c <= code_word[3:0];
 57 | 	case ({circle1, circle2, circle3})
 58 | 		3'b111 : begin
 59 | 			eb <= code_word[3];
 60 | 			c[3] <= ~code_word[3];
 61 | 		end
 62 | 		3'b110 : begin
 63 | 			eb <= code_word[2];
 64 | 			c[2] <= ~code_word[2];
 65 | 		end
 66 | 		3'b101 : begin
 67 | 			eb <= code_word[1];
 68 | 			c[1] <= ~code_word[1];
 69 | 		end
 70 | 		3'b011 : begin
 71 | 			eb <= code_word[0];
 72 | 			c[0] <= ~code_word[0];
 73 | 		end
 74 | 		3'b100 : eb <= code_word[6];
 75 | 		3'b010 : eb <= code_word[5];
 76 | 		3'b001 : eb <= code_word[4];
 77 | 		default : c <= 4'bx;
 78 | 	endcase
 79 | end
 80 | 
 81 | /*
 82 | wire [7:1] rcw = {code_word[3:1], code_word[6], code_word[0], code_word[5:4]}; // rearranged clock word
 83 | wire circle1 = rcw[4] ^ rcw[7] ^ rcw[6] ^ rcw[5];
 84 | wire circle2 = rcw[2] ^ rcw[7] ^ rcw[6] ^ rcw[3];
 85 | wire circle3 = rcw[1] ^ rcw[7] ^ rcw[5] ^ rcw[3];
 86 | wire [2:0] ep = {circle1, circle2, circle3}; // error position
 87 | always @(*) begin
 88 | 	eb <= rcw[ep];
 89 | 	c <= {rcw[7:5], rcw[3]};
 90 | 	case (ep)
 91 | 		3'd7 : c[3] <= ~rcw[7];
 92 | 		3'd6 : c[2] <= ~rcw[6];
 93 | 		3'd5 : c[1] <= ~rcw[5];
 94 | 		3'd3 : c[0] <= ~rcw[3];
 95 | 	endcase
 96 | end
 97 | */
 98 | 
 99 | /*
100 | wire circle1 = code_word[6] ^ code_word[3] ^ code_word[2] ^ code_word[1];
101 | wire circle2 = code_word[5] ^ code_word[3] ^ code_word[2] ^ code_word[0];
102 | wire circle3 = code_word[4] ^ code_word[3] ^ code_word[1] ^ code_word[0];
103 | reg [6:0] err;
104 | always @(*) begin
105 | 	err <= 7'b0;
106 | 	case ({circle1, circle2, circle3})
107 | 		3'b111 : err[3] <= 1'b1;
108 | 		3'b110 : err[2] <= 1'b1;
109 | 		3'b101 : err[1] <= 1'b1;
110 | 		3'b011 : err[0] <= 1'b1;
111 | 		3'b100 : err[6] <= 1'b1;
112 | 		3'b010 : err[5] <= 1'b1;
113 | 		3'b001 : err[4] <= 1'b1;
114 | 		default : err <= 7'bx;
115 | 	endcase
116 | end
117 | always @(*) begin
118 | 	eb <= |(code_word & err);
119 | 	c <= code_word[3:0] ^ err[3:0];
120 | end
121 | */
122 | 
123 | endmodule
124 | 
125 | module HA(a, b, s, c);
126 | input a;
127 | input b;
128 | output s;
129 | output c;
130 | 
131 | assign s = a ^ b;
132 | assign c = a & b;
133 | endmodule
134 | 
135 | module FA(a, b, cin, s, cout);
136 | input a;
137 | input b;
138 | input cin;
139 | output s;
140 | output cout;
141 | 
142 | wire s1, c1;
143 | HA ha1(a, b, s1, c1);
144 | wire s2, c2;
145 | HA ha2(s1, cin, s2, c2);
146 | assign s = s2;
147 | assign cout = c1 | c2;
148 | endmodule
149 | 
150 | module ADDSUB#(parameter width = 1) (a, b, add_sub, s);
151 | input [width - 1:0] a;
152 | input [width - 1:0] b;
153 | input add_sub;
154 | output [width - 1:0] s;
155 | 
156 | wire [width - 1:0] c;
157 | FA fa0(a[0], b[0] ^ add_sub, add_sub, s[0], c[0]);
158 | genvar gv_i;
159 | generate
160 | 	for (gv_i = 1; gv_i < width; gv_i = gv_i + 1) begin
161 | 		FA fa(a[gv_i], b[gv_i] ^ add_sub, c[gv_i - 1], s[gv_i], c[gv_i]);
162 | 	end
163 | endgenerate
164 | endmodule
165 | 
166 | 
167 | 
168 | 
169 | 
170 | 


--------------------------------------------------------------------------------
/Lab02/TT.1.v:
--------------------------------------------------------------------------------
  1 | module TT(
  2 | 	//Input Port
  3 | 	clk,
  4 | 	rst_n,
  5 | 	in_valid,
  6 | 	source,
  7 | 	destination,
  8 | 
  9 | 	//Output Port
 10 | 	out_valid,
 11 | 	cost
 12 | 	);
 13 | 
 14 | input			   clk, rst_n, in_valid;
 15 | input	   [3:0]   source;
 16 | input	   [3:0]   destination;
 17 | 
 18 | output reg		  out_valid;
 19 | output reg  [3:0]   cost;
 20 | 
 21 | //==============================================//
 22 | reg [1:0] state, nxt_state;
 23 | localparam Idle		= 2'd0;
 24 | localparam Read		= 2'd3;
 25 | localparam Bfs		= 2'd1;
 26 | localparam Output	= 2'd2;
 27 | 
 28 | reg [3:0] s, d;
 29 | reg adj [0:15][0:15];
 30 | reg vis [0:15];
 31 | reg vid [0:15];
 32 | reg [2:0] dis2;
 33 | wire [2:0] dis2_add_1 = dis2 + 3'd1;
 34 | reg output1;
 35 | 
 36 | integer i, j;
 37 | genvar gv_i, gv_j;
 38 | 
 39 | wor vis_next [0:15];
 40 | generate
 41 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 42 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 43 | 			if (gv_j < gv_i) begin
 44 | 				assign vis_next[gv_i] = (vis[gv_j] && adj[gv_j][gv_i]);
 45 | 			end
 46 | 			else if (gv_j == gv_i) begin
 47 | 				assign vis_next[gv_i] = vis[gv_j];
 48 | 			end
 49 | 			else if (gv_j > gv_i) begin
 50 | 				assign vis_next[gv_i] = (vis[gv_j] && adj[gv_i][gv_j]);
 51 | 			end
 52 | 		end
 53 | 	end
 54 | endgenerate
 55 | wor vid_next [0:15];
 56 | generate
 57 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 58 | 		for (gv_j = 0; gv_j <= 15; gv_j = gv_j + 1) begin
 59 | 			if (gv_j < gv_i) begin
 60 | 				assign vid_next[gv_i] = (vid[gv_j] && adj[gv_j][gv_i]);
 61 | 			end
 62 | 			else if (gv_j == gv_i) begin
 63 | 				assign vid_next[gv_i] = vid[gv_j];
 64 | 			end
 65 | 			else if (gv_j > gv_i) begin
 66 | 				assign vid_next[gv_i] = (vid[gv_j] && adj[gv_i][gv_j]);
 67 | 			end
 68 | 		end
 69 | 	end
 70 | endgenerate
 71 | 
 72 | wor bfs_found1;
 73 | generate
 74 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 75 | 		assign bfs_found1 = (vis_next[gv_i] & vid[gv_i]);
 76 | 	end
 77 | endgenerate
 78 | wor bfs_found2;
 79 | generate
 80 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 81 | 		assign bfs_found2 = (vis_next[gv_i] & vid_next[gv_i]);
 82 | 	end
 83 | endgenerate
 84 | wire bfs_found = bfs_found1 || bfs_found2;
 85 | 
 86 | wand bfs_ends;
 87 | generate
 88 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 89 | 		assign bfs_ends = (vis[gv_i] == vis_next[gv_i]);
 90 | 	end
 91 | endgenerate
 92 | wand bfs_endd;
 93 | generate
 94 | 	for (gv_i = 0; gv_i <= 15; gv_i = gv_i + 1) begin
 95 | 		assign bfs_endd = (vid[gv_i] == vid_next[gv_i]);
 96 | 	end
 97 | endgenerate
 98 | wire bfs_end = (bfs_ends || bfs_endd);
 99 | 
100 | always @(*) begin
101 | 	nxt_state <= state;
102 | 	case(state)
103 | 		Idle :
104 | 			if (in_valid) nxt_state <= Read;
105 | 		Read :
106 | 			if (!in_valid) begin
107 | 				if (bfs_found) nxt_state <= Output;
108 | 				else nxt_state <= Bfs;
109 | 			end
110 | 		Bfs : 
111 | 			if (bfs_found || bfs_end) nxt_state <= Idle;
112 | 		Output : nxt_state <= Idle;
113 | 	endcase
114 | end
115 | 
116 | always @(posedge clk or negedge rst_n) begin
117 | 	if(!rst_n) state <= Idle;
118 | 	else state <= nxt_state;
119 | end
120 | 
121 | always @(posedge clk) begin
122 | 	for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'bx; //
123 | 	for (i = 0; i <= 15; i = i + 1) vid[i] <= 1'bx; //
124 | 	dis2 <= 3'bx; //
125 | 	case (state)
126 | 		Idle : begin
127 | 			for (i = 0; i <= 15; i = i + 1)
128 | 				for (j = i + 1; j <= 15; j = j + 1) adj[i][j] <= 1'b0;
129 | 			//if (in_valid) begin
130 | 				//s <= source;
131 | 				//d <= destination;
132 | 
133 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= 1'b0;
134 | 				vis[source] <= 1'b1;
135 | 				for (i = 0; i <= 15; i = i + 1) vid[i] <= 1'b0;
136 | 				vid[destination] <= 1'b1;
137 | 				dis2 <= 3'd0;
138 | 			//end
139 | 		end
140 | 		Read : begin
141 | 			if (in_valid) begin
142 | 				//if (source < destination)
143 | 					adj[source][destination] <= 1'b1;
144 | 				//else /*if (destination < source)*/
145 | 					adj[destination][source] <= 1'b1;
146 | 
147 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis[i];
148 | 				for (i = 0; i <= 15; i = i + 1) vid[i] <= vid[i];
149 | 				dis2 <= 3'd0;
150 | 			end
151 | 			else begin
152 | 				output1 <= bfs_found1;
153 | 				for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next[i];
154 | 				for (i = 0; i <= 15; i = i + 1) vid[i] <= vid_next[i];
155 | 				dis2 <= dis2_add_1;
156 | 			end
157 | 		end
158 | 		Bfs : begin
159 | 			for (i = 0; i <= 15; i = i + 1) vis[i] <= vis_next[i];
160 | 			for (i = 0; i <= 15; i = i + 1) vid[i] <= vid_next[i];
161 | 			dis2 <= dis2_add_1;
162 | 		end
163 | 	endcase
164 | end
165 | 
166 | always @(*) begin
167 | 	out_valid <= 1'b0;
168 | 	cost <= 4'b0;
169 | 	case (state)
170 | 		Bfs : begin
171 | 			if (bfs_found) begin
172 | 				out_valid <= 1'b1;
173 | 				cost <= bfs_found1 ? {dis2, 1'b1} : {dis2_add_1, 1'b0};
174 | 			end
175 | 			else if (bfs_end) begin
176 | 				out_valid <= 1'b1;
177 | 				cost <= 4'd0;
178 | 			end
179 | 		end
180 | 		Output : begin
181 | 			out_valid <= 1'b1;
182 | 			cost <= output1 ? 4'd1 : 4'd2;
183 | 		end
184 | 	endcase
185 | end
186 | 
187 | endmodule 
188 | 


--------------------------------------------------------------------------------
/Lab05/MMSA.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | 
  3 | `include ...
  4 | 
  5 | // synopsys translate_on
  6 | 
  7 | module MMSA(
  8 | // input signals
  9 |     clk,
 10 |     rst_n,
 11 |     in_valid,
 12 | 	in_valid2,
 13 |     matrix,
 14 | 	matrix_size,
 15 |     i_mat_idx,
 16 |     w_mat_idx,
 17 | 	
 18 | // output signals
 19 |     out_valid,
 20 |     out_value
 21 | );
 22 | input        clk, rst_n, in_valid, in_valid2;
 23 | input signed [15:0] matrix;
 24 | input [1:0]  matrix_size;
 25 | input [3:0]  i_mat_idx, w_mat_idx;
 26 | 
 27 | output reg       	     out_valid;
 28 | output reg signed [39:0] out_value;
 29 | //---------------------------------------------------------------------
 30 | //
 31 | //---------------------------------------------------------------------
 32 | genvar gv_i, gv_j;
 33 | integer i, j;
 34 | 
 35 | wire signed [15:0] m_Q;
 36 | reg m_WEN;
 37 | reg [11:0] m_A;
 38 | reg signed [15:0] m_D;
 39 | sram_4096x16 u_sram_4096x16_m(.Q(m_Q), .CLK(clk), .CEN(1'b0), .WEN(m_WEN), .A(m_A), .D(m_D), .OEN(1'b0));
 40 | wire signed [15:0] w_Q [0:15];
 41 | reg w_WEN [0:15];
 42 | reg [7:0] w_A [0:15];
 43 | reg signed [15:0] w_D [0:15];
 44 | generate
 45 | 	for (gv_i = 0; gv_i < 16; gv_i = gv_i + 1) begin:SRAM_BLOCK
 46 | 		sram_256x16 u_sram_256x16_w(.Q(w_Q[gv_i]), .CLK(clk), .CEN(1'b0), .WEN(w_WEN[gv_i]), .A(w_A[gv_i]), .D(w_D[gv_i]), .OEN(1'b0));
 47 | 	end
 48 | endgenerate
 49 | 
 50 | reg signed [15:0] mult_a [0:15];
 51 | reg signed [15:0] mult_b [0:15];
 52 | wire signed [31:0] mult_product [0:15];
 53 | generate
 54 | 	for (gv_i = 0; gv_i < 16; gv_i = gv_i + 1) begin:MULT_BLOCK
 55 | 		DW02_mult_2_stage #(.A_width(16), .B_width(16))
 56 | 			u_DW02_mult_2_stage(.A(mult_a[gv_i]), .B(mult_b[gv_i]), .TC(1'b1), .CLK(clk), .PRODUCT(mult_product[gv_i]));
 57 | 	end
 58 | endgenerate
 59 | 
 60 | reg signed [39:0] add_a [0:15];
 61 | reg signed [39:0] add_b [0:15];
 62 | wire signed [39:0] add_sum [0:15];
 63 | generate
 64 | 	for (gv_i = 0; gv_i < 16; gv_i = gv_i + 1) begin:ADD_BLOCK
 65 | 		DW01_add #(.width(40))
 66 | 			u_DW01_add(.A(add_a[gv_i]), .B(add_b[gv_i]), .CI(1'b0), .SUM(add_sum[gv_i]), .CO());
 67 | 	end
 68 | endgenerate
 69 | 
 70 | reg [1:0] sz;
 71 | reg [3:0] size_sub_1;
 72 | reg [3:0] mi, wi;
 73 | 
 74 | reg signed [39:0] ans [0:30];
 75 | 
 76 | reg [3:0] rcnt;
 77 | wire [3:0] rcnt_end = size_sub_1;
 78 | wire rcnt_is_end = (rcnt == rcnt_end);
 79 | wire [3:0] rcnt_add_1 = rcnt + 4'd1;
 80 | wire [3:0] rcnt_next = (rcnt_is_end ? 4'd0 : rcnt_add_1);
 81 | 
 82 | reg [3:0] ccnt;
 83 | wire [3:0] ccnt_end = size_sub_1;
 84 | wire ccnt_is_begin = (ccnt == 4'd0);
 85 | wire ccnt_is_end = (ccnt == ccnt_end);
 86 | wire [3:0] ccnt_add_1 = ccnt + 4'd1;
 87 | wire [3:0] ccnt_next = (ccnt_is_end ? 4'd0 : ccnt_add_1);
 88 | 
 89 | reg [3:0] cnt;
 90 | wire cnt_eq_15 = (cnt == 4'd15);
 91 | wire [3:0] cnt_next = cnt + 4'd1;
 92 | 
 93 | localparam [5:0] wait_cycles = 6'd4;
 94 | reg [5:0] ocnt;
 95 | //wire signed [5:0] _ocnt_sub_wait_cycles = ocnt - wait_cycles;
 96 | //wire output_is_begin = !_ocnt_sub_wait_cycles[5];
 97 | //wire [4:0] ocnt_sub_wait_cycles = (output_is_begin ? _ocnt_sub_wait_cycles[4:0] : 5'd0);
 98 | //wire output_is_end = (ocnt_sub_wait_cycles == {size_sub_1, 1'b0});
 99 | wire output_is_begin = (ocnt >= wait_cycles);
100 | wire output_is_end = (ocnt == {size_sub_1, 1'b0} + wait_cycles);
101 | wire [5:0] ocnt_add_1 = ocnt + 6'd1;
102 | 
103 | reg [4:0] icnt;
104 | wire [4:0] icnt_add_1 = icnt + 5'd1;
105 | 
106 | reg [2:0] state, nxt_state;
107 | localparam Idle1	= 3'd0;
108 | localparam Readm	= 3'd1;
109 | localparam Readw	= 3'd2;
110 | localparam Idle2	= 3'd3;
111 | localparam Wait		= 3'd4;
112 | localparam Work		= 3'd5;
113 | localparam Output	= 3'd6;
114 | 
115 | always @(*) begin
116 | 	nxt_state <= state;
117 | 	case (state)
118 | 		Idle1 :
119 | 			if (in_valid) begin
120 | 				nxt_state <= Readm;
121 | 			end
122 | 		Readm :
123 | 			//if (in_valid) begin
124 | 				if (ccnt_is_end && rcnt_is_end && cnt_eq_15) nxt_state <= Readw;
125 | 			//end
126 | 		Readw :
127 | 			//if (in_valid) begin
128 | 				if (ccnt_is_end && rcnt_is_end && cnt_eq_15) nxt_state <= Idle2;
129 | 			//end
130 | 		Idle2 :
131 | 			if (in_valid2) begin
132 | 				nxt_state <= Wait;
133 | 			end
134 | 		Wait : nxt_state <= Work;
135 | 		Work :
136 | 			if (ccnt_is_end && rcnt_is_end) nxt_state <= Output;
137 | 		Output :
138 | 			if (output_is_end) begin
139 | 				if (cnt_eq_15) nxt_state <= Idle1;
140 | 				else nxt_state <= Idle2;
141 | 			end
142 | 	endcase
143 | end
144 | 
145 | always @(posedge clk or negedge rst_n) begin
146 | 	if (!rst_n) state <= Idle1;
147 | 	else state <= nxt_state;
148 | end
149 | 
150 | always @(*) begin
151 | 	m_WEN <= 1'b1;
152 | 	m_A <= 12'bx;
153 | 	m_D <= 16'sbx;
154 | 	for (i = 0; i < 16; i = i + 1) begin
155 | 		w_WEN[i] <= 1'b1;
156 | 		w_A[i] <= 8'bx;
157 | 		w_D[i] <= 16'sbx;
158 | 	end
159 | 	case (state)
160 | 		Idle1 : begin
161 | 			//if(in_valid) begin
162 | 				m_WEN <= 1'b0;
163 | 				m_A <= {4'd0, 4'd0, 4'd0};
164 | 				m_D <= matrix;
165 | 			//end
166 | 		end
167 | 		Readm : begin
168 | 			//if(in_valid) begin
169 | 				m_WEN <= 1'b0;
170 | 				m_A <= {cnt, rcnt, ccnt};
171 | 				m_D <= matrix;
172 | 			//end
173 | 		end
174 | 		Readw : begin
175 | 			//if(in_valid) begin
176 | 				w_WEN[ccnt] <= 1'b0;
177 | 				w_A[ccnt] <= {cnt, rcnt};
178 | 				w_D[ccnt] <= matrix;
179 | 			//end
180 | 		end
181 | 		Wait : begin
182 | 			m_A <= {mi, 4'd0, 4'd0};
183 | 			for (i = 0; i < 16; i = i + 1) w_A[i] <= {wi, 4'd0};
184 | 		end
185 | 		Work : begin
186 | 			//if (!(ccnt_is_end && rcnt_is_end)) begin
187 | 				if (ccnt_is_end) m_A <= {mi, rcnt_next, ccnt_next};
188 | 				else m_A <= {mi, rcnt, ccnt_next};
189 | 				for (i = 0; i < 16; i = i + 1) w_A[i] <= {wi, ccnt_next};
190 | 			//end
191 | 		end
192 | 	endcase
193 | end
194 | 
195 | reg reset_flag, reset_flag_mult, reset_flag_add;
196 | always @(posedge clk) begin
197 | 	reset_flag <= 1'b0;
198 | 	reset_flag_mult <= reset_flag;
199 | 	reset_flag_add <= reset_flag_mult;
200 | 	case (state)
201 | 		Wait : begin
202 | 			reset_flag <= 1'b1;
203 | 		end
204 | 	endcase
205 | end
206 | 
207 | reg shift_flag, shift_flag_mult, shift_flag_add;
208 | always @(posedge clk) begin
209 | 	shift_flag <= 1'b0;
210 | 	shift_flag_mult <= shift_flag;
211 | 	shift_flag_add <= shift_flag_mult;
212 | 	case (state)
213 | 		Work : begin
214 | 			if (ccnt_is_end && !rcnt_is_end) shift_flag <= 1'b1;
215 | 		end
216 | 	endcase
217 | end
218 | 
219 | reg signed [15:0] _mult_a [0:15];
220 | reg signed [15:0] _mult_b [0:15];
221 | always @(posedge clk) begin
222 | 	for (i = 0; i < 16; i = i + 1) begin
223 | 		_mult_a[i] <= 16'sd0;
224 | 		_mult_b[i] <= 16'sd0;
225 | 	end
226 | 	case (state)
227 | 		Work : begin
228 | 			for (i = 0; i < 16; i = i + 1) begin
229 | 				_mult_a[i] <= m_Q;
230 | 				_mult_b[i] <= w_Q[i];
231 | 			end
232 | 		end
233 | 	endcase
234 | end
235 | 
236 | always @(*) begin
237 | 	for (i = 0; i < 16; i = i + 1) begin
238 | 		mult_a[i] <= _mult_a[i];
239 | 		mult_b[i] <= _mult_b[i];
240 | 	end
241 | end
242 | 
243 | reg signed [31:0] _mult_product [0:15];
244 | always @(posedge clk) begin
245 | 	for (i = 0; i < 16; i = i + 1) begin
246 | 		_mult_product[i] <= mult_product[i];
247 | 	end
248 | end
249 | 
250 | always @(*) begin
251 | 	for (i = 0; i < 16; i = i + 1) begin
252 | 		add_a[i] <= ans[15 + i];
253 | 		add_b[i] <= _mult_product[i];
254 | 	end
255 | end
256 | 
257 | reg signed [39:0] ans_temp [0:30];
258 | always @(*) begin
259 | 	for (i = 0; i < 15; i = i + 1) begin
260 | 		ans_temp[i] <= ans[i];
261 | 	end
262 | 	for (i = 15; i < 31; i = i + 1) begin
263 | 		ans_temp[i] <= add_sum[i - 15];
264 | 	end
265 | end
266 | 
267 | reg signed [39:0] ans_next [0:30];
268 | always @(*) begin
269 | 	if (reset_flag_add) begin
270 | 		for (i = 0; i < 31; i = i + 1) begin
271 | 			ans_next[i] <= 40'd0;
272 | 		end
273 | 	end
274 | 	else if (shift_flag_add) begin
275 | 		for (i = 0; i < 31; i = i + 1) begin
276 | 			if (i == 16) begin
277 | 				if (sz == 2'b00) ans_next[16] <= 40'sb0;
278 | 				else ans_next[16] <= ans_temp[17];
279 | 			end
280 | 			else if (i == 18) begin
281 | 				if (sz == 2'b01) ans_next[18] <= 40'sb0;
282 | 				else ans_next[18] <= ans_temp[19];
283 | 			end
284 | 			else if (i == 22) begin
285 | 				if (sz == 2'b10) ans_next[22] <= 40'sb0;
286 | 				else ans_next[22] <= ans_temp[23];
287 | 			end
288 | 			else if (i == 30) begin
289 | 				ans_next[30] <= 40'sb0;
290 | 			end
291 | 			else begin
292 | 				ans_next[i] <= ans_temp[i + 1];
293 | 			end
294 | 		end
295 | 	end
296 | 	else begin
297 | 		for (i = 0; i < 31; i = i + 1) begin
298 | 			ans_next[i] <= ans_temp[i];
299 | 		end
300 | 	end
301 | end
302 | 
303 | always @(posedge clk) begin
304 | 	for (i = 0; i < 31; i = i + 1) begin
305 | 		ans[i] <= ans_next[i];
306 | 	end
307 | end
308 | 
309 | always @(posedge clk) begin
310 | 	ccnt <= 4'd0; //
311 | 	ocnt <= 6'd0; //
312 | 	icnt <= 5'd15 - size_sub_1; //
313 | 	case (state)
314 | 		Idle1 : begin
315 | 			//if (in_valid) begin
316 | 				sz <= matrix_size;
317 | 				case (matrix_size)
318 | 					2'b00 : size_sub_1 <= 4'd1;
319 | 					2'b01 : size_sub_1 <= 4'd3;
320 | 					2'b10 : size_sub_1 <= 4'd7;
321 | 					2'b11 : size_sub_1 <= 4'd15;
322 | 				endcase
323 | 				ccnt <= 4'd1;
324 | 				rcnt <= 4'd0;
325 | 				cnt <= 4'd0;
326 | 			//end
327 | 		end
328 | 		Readm : begin
329 | 			//if (in_valid) begin
330 | 				ccnt <= ccnt_next;
331 | 				if (ccnt_is_end) rcnt <= rcnt_next;
332 | 				if (ccnt_is_end && rcnt_is_end) cnt <= cnt_next;
333 | 			//end
334 | 		end
335 | 		Readw : begin
336 | 			//if (in_valid) begin
337 | 				ccnt <= ccnt_next;
338 | 				if (ccnt_is_end) rcnt <= rcnt_next;
339 | 				if (ccnt_is_end && rcnt_is_end) cnt <= cnt_next;
340 | 			//end
341 | 		end
342 | 		Idle2 : begin
343 | 			//if (in_valid2) begin
344 | 				mi <= i_mat_idx;
345 | 				wi <= w_mat_idx;
346 | 				ocnt <= 6'd0;
347 | 				icnt <= 5'd15 - size_sub_1;
348 | 			//end
349 | 		end
350 | 		Work : begin
351 | 			ccnt <= ccnt_next;
352 | 			if (ccnt_is_end) rcnt <= rcnt_next;
353 | 			if (rcnt_is_end) ocnt <= ocnt_add_1;
354 | 			if (output_is_begin) icnt <= icnt_add_1;
355 | 		end
356 | 		Output : begin
357 | 			ocnt <= ocnt_add_1;
358 | 			if (output_is_begin) icnt <= icnt_add_1;
359 | 			if (output_is_end) cnt <= cnt_next;
360 | 		end
361 | 	endcase
362 | end
363 | 
364 | always @(posedge clk or negedge rst_n) begin
365 | 	if (!rst_n) begin
366 | 		out_valid <= 1'b0;
367 | 		out_value <= 40'sb0;
368 | 	end
369 | 	else begin
370 | 		out_valid <= 1'b0;
371 | 		out_value <= 40'sbx;
372 | 		case (state)
373 | 			Work, Output : begin
374 | 				if (output_is_begin) begin
375 | 					out_valid <= 1'b1;
376 | 					out_value <= ans[icnt];
377 | 				end
378 | 			end
379 | 		endcase
380 | 	end
381 | end
382 | 
383 | endmodule
384 | 
385 | 
386 | 
387 | 
388 | 
389 | 


--------------------------------------------------------------------------------
/Lab06/UT_TOP.v:
--------------------------------------------------------------------------------
  1 | //############################################################################
  2 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  3 | //   File Name   : UT_TOP.v
  4 | //   Module Name : UT_TOP
  5 | //++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  6 | //############################################################################
  7 | 
  8 | // synopsys translate_off
  9 | 
 10 | `include "B2BCD_IP.v"
 11 | `include ...
 12 | 
 13 | // synopsys translate_on
 14 | 
 15 | module UT_TOP (
 16 |     // Input signals
 17 |     clk, rst_n, in_valid, in_time,
 18 |     // Output signals
 19 |     out_valid, out_display, out_day
 20 | );
 21 | input clk, rst_n, in_valid;
 22 | input [30:0] in_time;
 23 | output reg out_valid;
 24 | output reg [3:0] out_display;
 25 | output reg [2:0] out_day;
 26 | // ===============================================================
 27 | //
 28 | // ===============================================================
 29 | 
 30 | reg [6:0] binary;
 31 | wire [7:0] bcd;
 32 | B2BCD_IP #(.WIDTH(7), .DIGIT(2)) u_B2BCD_IP(.Binary_code(binary), .BCD_code(bcd));
 33 | 
 34 | reg [3:0] state, nxt_state;
 35 | localparam Idle	= 4'd0;
 36 | localparam S1	= 4'd1;
 37 | localparam S2	= 4'd2;
 38 | localparam S3	= 4'd3;
 39 | localparam S4	= 4'd4;
 40 | localparam S5	= 4'd5;
 41 | localparam S6	= 4'd6;
 42 | localparam S7	= 4'd7;
 43 | localparam S8	= 4'd8;
 44 | localparam S9	= 4'd9;
 45 | localparam S10	= 4'd10;
 46 | localparam S11	= 4'd11;
 47 | localparam S12	= 4'd12;
 48 | localparam S13	= 4'd13;
 49 | localparam S14	= 4'd14;
 50 | localparam S15	= 4'd15;
 51 | 
 52 | always @(*) begin
 53 | 	nxt_state <= state;
 54 | 	case (state)
 55 | 		Idle :
 56 | 			if (in_valid) nxt_state <= S1;
 57 | 		S1  : nxt_state <= S2;
 58 | 		S2  : nxt_state <= S3;
 59 | 		S3  : nxt_state <= S4;
 60 | 		S4  : nxt_state <= S5;
 61 | 		S5  : nxt_state <= S6;
 62 | 		S6  : nxt_state <= S7;
 63 | 		S7  : nxt_state <= S8;
 64 | 		S8  : nxt_state <= S9;
 65 | 		S9  : nxt_state <= S10;
 66 | 		S10 : nxt_state <= S11;
 67 | 		S11 : nxt_state <= S12;
 68 | 		S12 : nxt_state <= S13;
 69 | 		S13 : nxt_state <= S14;
 70 | 		S14 : nxt_state <= S15;
 71 | 		S15 : nxt_state <= Idle;
 72 | 	endcase
 73 | end
 74 | 
 75 | always @(posedge clk or negedge rst_n) begin
 76 | 	if (!rst_n) state <= Idle;
 77 | 	else state <= nxt_state;
 78 | end
 79 | 
 80 | reg is_21th_century;
 81 | reg [30:0] seconds;
 82 | 
 83 | localparam UT_20000101_000000 = 31'd946684800;
 84 | wire signed [31:0] _temp_1 = in_time - UT_20000101_000000;
 85 | wire _is_21th_century = !_temp_1[31];
 86 | wire [30:0] _seconds = (_is_21th_century ? _temp_1[30:0] : in_time); // [0:1200798848)
 87 | /*------------------------------------------------------------*/
 88 | 
 89 | reg [13:0] days;
 90 | 
 91 | /*
 92 | wire [23:0] div_86400_quotient;
 93 | DW_div #(.a_width(24), .b_width(10), .tc_mode(0), .rem_mode(1))
 94 | 	u_DW_div_675(.a(seconds[30:7]), .b(10'd675), .quotient(div_86400_quotient), .remainder(), .divide_by_0());
 95 | wire [13:0] _temp_2_2 = div_86400_quotient;
 96 | */
 97 | wire [45:0] _temp_2_1 = seconds[30:7] * 23'd6362915; // Magic
 98 | wire [13:0] _temp_2_2 = _temp_2_1[45:32];
 99 | wire [13:0] _days = _temp_2_2; // [0:13899)
100 | /*------------------------------------------------------------*/
101 | 
102 | reg [6:0] years;
103 | 
104 | localparam DAYS_1968_1969 = 31'd731;
105 | wire [13:0] _temp_3_1 = days + DAYS_1968_1969;
106 | wire [13:0] _dayss = (is_21th_century ? days : _temp_3_1);
107 | //wire [13:0] div_1461_quotient;
108 | //DW_div #(.a_width(14), .b_width(11), .tc_mode(0), .rem_mode(1))
109 | //	u_DW_div_1461(.a(_dayss), .b(11'd1461), .quotient(div_1461_quotient), .remainder(), .divide_by_0());
110 | reg [3:0] div_1461_quotient;
111 | always @(*) begin
112 | 	if (_dayss < 14'd1461) div_1461_quotient <= 4'd0;
113 | 	else if (_dayss < 14'd2922) div_1461_quotient <= 4'd1;
114 | 	else if (_dayss < 14'd4383) div_1461_quotient <= 4'd2;
115 | 	else if (_dayss < 14'd5844) div_1461_quotient <= 4'd3;
116 | 	else if (_dayss < 14'd7305) div_1461_quotient <= 4'd4;
117 | 	else if (_dayss < 14'd8766) div_1461_quotient <= 4'd5;
118 | 	else if (_dayss < 14'd10227) div_1461_quotient <= 4'd6;
119 | 	else if (_dayss < 14'd11688) div_1461_quotient <= 4'd7;
120 | 	else if (_dayss < 14'd13149) div_1461_quotient <= 4'd8;
121 | 	else div_1461_quotient <= 4'd9;
122 | end
123 | wire [3:0] _temp_3_3 = div_1461_quotient;
124 | //wire [25:0] _temp_3_2 = _dayss * 12'd2871; // Magic
125 | //wire [3:0] _temp_3_3 = _temp_3_2[25:22];
126 | wire [3:0] _ye4rs = _temp_3_3; // [0:10)
127 | /*------------------------------------------------------------*/
128 | 
129 | reg leap;
130 | 
131 | wire [13:0] _temp_4_1 = years[5:2] * 11'd1461;
132 | wire [10:0] _temp_4_2 = _dayss - _temp_4_1;
133 | reg [1:0] _ears;
134 | reg _leap;
135 | reg [8:0] _days_iy; // [0:367)
136 | always @(*) begin
137 | 	if (_temp_4_2 < 11'd366) begin
138 | 		_leap <= 1'b1;
139 | 		_ears <= 2'd0;
140 | 		_days_iy <= _temp_4_2;
141 | 	end
142 | 	else if (_temp_4_2 < 11'd731) begin
143 | 		_leap <= 1'b0;
144 | 		_ears <= 2'd1;
145 | 		_days_iy <= _temp_4_2 - 11'd366;
146 | 	end
147 | 	else if (_temp_4_2 < 11'd1096) begin
148 | 		_leap <= 1'b0;
149 | 		_ears <= 2'd2;
150 | 		_days_iy <= _temp_4_2 - 11'd731;
151 | 	end
152 | 	else begin
153 | 		_leap <= 1'b0;
154 | 		_ears <= 2'd3;
155 | 		_days_iy <= _temp_4_2 - 11'd1096;
156 | 	end
157 | end
158 | /*------------------------------*/
159 | 
160 | wire [4:0] _temp_4_3 = years[5:2] + 5'd17;
161 | wire [4:0] _temp_4_4 = (is_21th_century ? years[5:2] : _temp_4_3);
162 | wire [6:0] _years = {_temp_4_4, _ears}; // [70:100) or [0:39)
163 | /*------------------------------------------------------------*/
164 | 
165 | reg [3:0] months;
166 | 
167 | wire [8:0] _days_before_month [1:12];
168 | assign _days_before_month[1]	= -9'sd1;
169 | assign _days_before_month[2]	= 9'd30;
170 | assign _days_before_month[3]	= 9'd58 + leap;
171 | assign _days_before_month[4]	= 9'd89 + leap;
172 | assign _days_before_month[5]	= 9'd119 + leap;
173 | assign _days_before_month[6]	= 9'd150 + leap;
174 | assign _days_before_month[7]	= 9'd180 + leap;
175 | assign _days_before_month[8]	= 9'd211 + leap;
176 | assign _days_before_month[9]	= 9'd242 + leap;
177 | assign _days_before_month[10]	= 9'd272 + leap;
178 | assign _days_before_month[11]	= 9'd303 + leap;
179 | assign _days_before_month[12]	= 9'd333 + leap;
180 | //assign _days_before_month[13]	= 9'd364 + leap;
181 | reg [8:0] _temp_5;
182 | reg [3:0] _months_iy; // [0:13)
183 | reg [4:0] _days_im; // [0:32)
184 | integer i;
185 | always @(*) begin
186 | 	_months_iy <= 4'd12;
187 | 	_temp_5 <= _days_before_month[12];
188 | 	for (i = 11; i >= 1; i = i - 1) begin
189 | 		if (days[8:0] <= _days_before_month[i + 1]) begin
190 | 			_months_iy <= i;
191 | 			_temp_5 <= _days_before_month[i];
192 | 		end
193 | 	end
194 | 	_days_im <= days[8:0] - _temp_5;
195 | end
196 | //=====+++++-----!!!!!//
197 | 
198 | wire [23:0] _temp_6_1 = days * 10'd675;
199 | wire [9:0] _temp_6_2 = seconds[30:7] - _temp_6_1;
200 | wire [16:0] _seconds_id = {_temp_6_2, seconds[6:0]}; // [0:86400)
201 | /*------------------------------------------------------------*/
202 | 
203 | reg [16:0] div_60_a;
204 | wire [14:0] div_60_quotient;
205 | wire [5:0] div_60_remainder;
206 | assign div_60_remainder[1:0] = div_60_a[1:0];
207 | DW_div #(.a_width(15), .b_width(4), .tc_mode(0), .rem_mode(1))
208 | 	u_DW_div_15(.a(div_60_a[16:2]), .b(4'd15), .quotient(div_60_quotient), .remainder(div_60_remainder[5:2]), .divide_by_0());
209 | // synopsys dc_script_begin
210 | //
211 | // set_implementation mlt u_DW_div_15
212 | //
213 | // synopsys dc_script_end
214 | /*------------------------------*/
215 | 
216 | reg [10:0] minutes;
217 | 
218 | wire [10:0] _minutes_id = div_60_quotient; // [0:1440)
219 | wire [5:0] _seconds_im = div_60_remainder; // [0:60)
220 | /*------------------------------------------------------------*/
221 | 
222 | reg [4:0] hours;
223 | 
224 | wire [4:0] _hours_id = div_60_quotient; // [0:24)
225 | wire [5:0] _minutes_ih = div_60_remainder; // [0:60)
226 | /*------------------------------*/
227 | 
228 | always @(*) begin
229 | 	div_60_a <= 17'bx;
230 | 	case (state)
231 | 		S3 : div_60_a <= seconds[16:0];
232 | 		S4 : div_60_a <= minutes;
233 | 	endcase
234 | end
235 | //=====+++++-----!!!!!//
236 | 
237 | reg [13:0] dc;
238 | 
239 | wire [13:0] _temp_8 = _days + (is_21th_century ? 3'd6 : 3'd4);
240 | wire [13:0] _dc = _temp_8;
241 | /*------------------------------------------------------------*/
242 | 
243 | wire [2:0] div_7_remainder;
244 | DW_div #(.a_width(14), .b_width(3), .tc_mode(0), .rem_mode(1))
245 | 	u_DW_div_7(.a(dc), .b(3'd7), .quotient(), .remainder(div_7_remainder), .divide_by_0());
246 | // synopsys dc_script_begin
247 | //
248 | // set_implementation mlt u_DW_div_7
249 | //
250 | // synopsys dc_script_end
251 | wire [2:0] _temp_9_3 = div_7_remainder;
252 | //wire [27:0] _temp_9_1 = dc * 15'd18725; // Magic
253 | //wire [13:0] _temp_9_2 = _temp_9_1[27:17] * 3'd7;
254 | //wire [2:0] _temp_9_3 = dc - _temp_9_2;
255 | wire [2:0] _dow = _temp_9_3;
256 | //=====+++++-----!!!!!//
257 | 
258 | always @(posedge clk) begin
259 | 	case (state)
260 | 		Idle : begin
261 | 			//if (in_valid) begin
262 | 				is_21th_century <= _is_21th_century;
263 | 				seconds <= _seconds;
264 | 			//end
265 | 		end
266 | 		S1 : begin
267 | 			dc <= _dc;
268 | 
269 | 			days <= _days;
270 | 		end
271 | 		S2 : begin
272 | 			years[5:2] <= _ye4rs;
273 | 
274 | 			seconds <= _seconds_id;
275 | 		end
276 | 		S3 : begin
277 | 			years <= _years;
278 | 			leap <= _leap;
279 | 			days <= _days_iy;
280 | 
281 | 			minutes <= _minutes_id;
282 | 			seconds <= _seconds_im;
283 | 		end
284 | 		S4 : begin
285 | 			months <= _months_iy;
286 | 			days <= _days_im;
287 | 
288 | 			hours <= _hours_id;
289 | 			minutes <= _minutes_ih;
290 | 		end
291 | 	endcase
292 | end
293 | 
294 | always @(posedge clk) begin
295 | 	binary <= 7'bx;
296 | 	case (state)
297 | 		S3 : binary <= _years;
298 | 		S4 : binary <= years;
299 | 		S5, S6 : binary <= months;
300 | 		S7, S8 : binary <= days[4:0];
301 | 		S9, S10 : binary <= hours;
302 | 		S11, S12 : binary <= minutes[5:0];
303 | 		S13, S14 : binary <= seconds[5:0];
304 | 	endcase
305 | end
306 | 
307 | always @(*) begin
308 | 	out_valid <= 1'b0;
309 | 	case (state)
310 | 		S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 : out_valid <= 1'b1;
311 | 	endcase
312 | 	out_display <= 4'b0;
313 | 	case (state)
314 | 		S2 : out_display <= (is_21th_century ? 4'd2 : 4'd1);
315 | 		S3 : out_display <= (is_21th_century ? 4'd0 : 4'd9);
316 | 		S4, S6, S8, S10, S12, S14 : out_display <= bcd[7:4];
317 | 		S5, S7, S9, S11, S13, S15 : out_display <= bcd[3:0];
318 | 	endcase
319 | 	out_day <= 3'd0;
320 | 	case (state)
321 | 		S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 : out_day <= _dow;
322 | 	endcase
323 | end
324 | 
325 | endmodule
326 | 
327 | 
328 | 
329 | 
330 | 


--------------------------------------------------------------------------------
/Lab07/CDC.v:
--------------------------------------------------------------------------------
  1 | `include "synchronizer.v"
  2 | `include "syn_XOR.v"
  3 | module CDC(
  4 | 	//Input Port
  5 | 	clk1,
  6 |     clk2,
  7 |     clk3,
  8 | 	rst_n,
  9 | 	in_valid1,
 10 | 	in_valid2,
 11 | 	user1,
 12 | 	user2,
 13 | 
 14 |     //Output Port
 15 |     out_valid1,
 16 |     out_valid2,
 17 | 	equal,
 18 | 	exceed,
 19 | 	winner
 20 | ); 
 21 | input 		clk1, clk2, clk3, rst_n;
 22 | input 		in_valid1, in_valid2;
 23 | input [3:0]	user1, user2;
 24 | 
 25 | output reg	out_valid1, out_valid2;
 26 | output reg	equal, exceed, winner;
 27 | //---------------------------------------------------------------------
 28 | //
 29 | //---------------------------------------------------------------------
 30 | reg prob_flag_1;
 31 | wire prob_flag_3;
 32 | reg [4:0] prob_dividend1_reg_1, prob_dividend1_reg_3;
 33 | reg [5:0] prob_dividend2_reg_1, prob_dividend2_reg_3;
 34 | reg [5:0] prob_divisor_reg_1, prob_divisor_reg_3;
 35 | syn_XOR u_syn_XOR_prob_flag(.IN(prob_flag_1), .OUT(prob_flag_3), .TX_CLK(clk1), .RX_CLK(clk3), .RST_N(rst_n));
 36 | always @(posedge clk3) begin
 37 | 	if (prob_flag_3) begin
 38 | 		prob_dividend1_reg_3 <= prob_dividend1_reg_1;
 39 | 		prob_dividend2_reg_3 <= prob_dividend2_reg_1;
 40 | 		prob_divisor_reg_3 <= prob_divisor_reg_1;
 41 | 	end
 42 | end
 43 | 
 44 | reg winner_flag_1;
 45 | wire winner_flag_3;
 46 | reg [1:0] winner_reg_1, winner_reg_3;
 47 | syn_XOR u_syn_XOR_winner_flag(.IN(winner_flag_1), .OUT(winner_flag_3), .TX_CLK(clk1), .RX_CLK(clk3), .RST_N(rst_n));
 48 | always @(posedge clk3) begin
 49 | 	if (winner_flag_3) begin
 50 | 		winner_reg_3 <= winner_reg_1;
 51 | 	end
 52 | end
 53 | /*------------------------------*/
 54 | 
 55 | reg [3:0] point1, point2;
 56 | always @(*) begin
 57 | 	point1 <= 4'bx;
 58 | 	case (user1)
 59 | 		4'd1, 4'd11, 4'd12, 4'd13 : point1 <= 4'd1;
 60 | 		4'd2 : point1 <= 4'd2;
 61 | 		4'd3 : point1 <= 4'd3;
 62 | 		4'd4 : point1 <= 4'd4;
 63 | 		4'd5 : point1 <= 4'd5;
 64 | 		4'd6 : point1 <= 4'd6;
 65 | 		4'd7 : point1 <= 4'd7;
 66 | 		4'd8 : point1 <= 4'd8;
 67 | 		4'd9 : point1 <= 4'd9;
 68 | 		4'd10 : point1 <= 4'd10;
 69 | 	endcase
 70 | 	point2 <= 4'bx;
 71 | 	case (user2)
 72 | 		4'd1, 4'd11, 4'd12, 4'd13 : point2 <= 4'd1;
 73 | 		4'd2 : point2 <= 4'd2;
 74 | 		4'd3 : point2 <= 4'd3;
 75 | 		4'd4 : point2 <= 4'd4;
 76 | 		4'd5 : point2 <= 4'd5;
 77 | 		4'd6 : point2 <= 4'd6;
 78 | 		4'd7 : point2 <= 4'd7;
 79 | 		4'd8 : point2 <= 4'd8;
 80 | 		4'd9 : point2 <= 4'd9;
 81 | 		4'd10 : point2 <= 4'd10;
 82 | 	endcase
 83 | end
 84 | wire [3:0] point = (in_valid1 ? point1 : point2);
 85 | 
 86 | reg [4:0] player1, player2;
 87 | 
 88 | reg [4:0] player_next;
 89 | reg [4:0] _player_temp1;
 90 | reg [5:0] _player_temp2;
 91 | always @(*) begin
 92 | 	_player_temp1 <= (in_valid1 ? player1 : player2);
 93 | 	_player_temp2 <= _player_temp1 + point;
 94 | 	player_next <= (_player_temp2[5] ? _player_temp1 : _player_temp2);
 95 | end
 96 | 
 97 | reg [5:0] g0cnt; // 52
 98 | reg [5:0] g1cnt; // 36
 99 | reg [5:0] g2cnt; // 32
100 | reg [4:0] g3cnt; // 28
101 | reg [4:0] g4cnt; // 24
102 | reg [4:0] g5cnt; // 20
103 | reg [4:0] g6cnt; // 16
104 | reg [3:0] g7cnt; // 12
105 | reg [3:0] g8cnt; // 8
106 | reg [2:0] g9cnt; // 4
107 | reg [5:0] g0cnt_next;
108 | reg [5:0] g1cnt_next;
109 | reg [5:0] g2cnt_next;
110 | reg [4:0] g3cnt_next;
111 | reg [4:0] g4cnt_next;
112 | reg [4:0] g5cnt_next;
113 | reg [4:0] g6cnt_next;
114 | reg [3:0] g7cnt_next;
115 | reg [3:0] g8cnt_next;
116 | reg [2:0] g9cnt_next;
117 | always @(*) begin
118 | 	g0cnt_next <= g0cnt - 6'd1;
119 | 	g1cnt_next <= g1cnt - (point > 1);
120 | 	g2cnt_next <= g2cnt - (point > 2);
121 | 	g3cnt_next <= g3cnt - (point > 3);
122 | 	g4cnt_next <= g4cnt - (point > 4);
123 | 	g5cnt_next <= g5cnt - (point > 5);
124 | 	g6cnt_next <= g6cnt - (point > 6);
125 | 	g7cnt_next <= g7cnt - (point > 7);
126 | 	g8cnt_next <= g8cnt - (point > 8);
127 | 	g9cnt_next <= g9cnt - (point > 9);
128 | end
129 | 
130 | reg [5:0] dividend1_temp1;
131 | reg [5:0] dividend2_temp;
132 | always @(*) begin
133 | 	case (player_next)
134 | 		5'd31, 5'd30, 5'd29, 5'd28, 5'd27, 5'd26, 5'd25, 5'd24, 5'd23, 5'd22, 5'd21 : begin
135 | 			dividend1_temp1 <= g0cnt_next;
136 | 			dividend2_temp <= g0cnt_next;
137 | 		end
138 | 		5'd20 : begin
139 | 			dividend1_temp1 <= g0cnt_next;
140 | 			dividend2_temp <= g1cnt_next;
141 | 		end
142 | 		5'd19 : begin
143 | 			dividend1_temp1 <= g1cnt_next;
144 | 			dividend2_temp <= g2cnt_next;
145 | 		end
146 | 		5'd18 : begin
147 | 			dividend1_temp1 <= g2cnt_next;
148 | 			dividend2_temp <= g3cnt_next;
149 | 		end
150 | 		5'd17 : begin
151 | 			dividend1_temp1 <= g3cnt_next;
152 | 			dividend2_temp <= g4cnt_next;
153 | 		end
154 | 		5'd16 : begin
155 | 			dividend1_temp1 <= g4cnt_next;
156 | 			dividend2_temp <= g5cnt_next;
157 | 		end
158 | 		5'd15 : begin
159 | 			dividend1_temp1 <= g5cnt_next;
160 | 			dividend2_temp <= g6cnt_next;
161 | 		end
162 | 		5'd14 : begin
163 | 			dividend1_temp1 <= g6cnt_next;
164 | 			dividend2_temp <= g7cnt_next;
165 | 		end
166 | 		5'd13 : begin
167 | 			dividend1_temp1 <= g7cnt_next;
168 | 			dividend2_temp <= g8cnt_next;
169 | 		end
170 | 		5'd12 : begin
171 | 			dividend1_temp1 <= g8cnt_next;
172 | 			dividend2_temp <= g9cnt_next;
173 | 		end
174 | 		5'd11 : begin
175 | 			dividend1_temp1 <= g9cnt_next;
176 | 			dividend2_temp <= 6'd0;
177 | 		end
178 | 		default : begin
179 | 			dividend1_temp1 <= 6'd0;
180 | 			dividend2_temp <= 6'd0;
181 | 		end
182 | 	endcase
183 | end
184 | wire [4:0] dividend1_temp = dividend1_temp1 - dividend2_temp;
185 | 
186 | reg [3:0] state_1, nxt_state_1;
187 | localparam Idle_1	= 4'b0000;
188 | localparam Work0_1	= 4'b0001;
189 | localparam Work1_1	= 4'b0011;
190 | localparam Work2_1	= 4'b0010;
191 | localparam Work3_1	= 4'b0110;
192 | localparam Work4_1	= 4'b0111;
193 | localparam Work5_1	= 4'b0101;
194 | localparam Work6_1	= 4'b0100;
195 | localparam Work7_1	= 4'b1100;
196 | localparam Work8_1	= 4'b1101;
197 | localparam Work9_1	= 4'b1111;
198 | 
199 | reg [2:0] epoch_cnt;
200 | wire epoch_cnt_is_5 = (epoch_cnt == 3'd5);
201 | 
202 | always @(*) begin
203 | 	nxt_state_1 <= state_1;
204 | 	case (state_1)
205 | 		Idle_1 : nxt_state_1 <= Work0_1;
206 | 		Work0_1 :
207 | 			if (in_valid1) nxt_state_1 <= Work1_1;
208 | 		Work1_1 : nxt_state_1 <= Work2_1;
209 | 		Work2_1 : nxt_state_1 <= Work3_1;
210 | 		Work3_1 : nxt_state_1 <= Work4_1;
211 | 		Work4_1 : nxt_state_1 <= Work5_1;
212 | 		Work5_1 : nxt_state_1 <= Work6_1;
213 | 		Work6_1 : nxt_state_1 <= Work7_1;
214 | 		Work7_1 : nxt_state_1 <= Work8_1;
215 | 		Work8_1 : nxt_state_1 <= Work9_1;
216 | 		Work9_1 : nxt_state_1 <= Work0_1;
217 | 	endcase
218 | end
219 | 
220 | always @(posedge clk1 or negedge rst_n) begin
221 | 	if(!rst_n) state_1 <= Idle_1;
222 | 	else state_1 <= nxt_state_1;
223 | end
224 | 
225 | always @(posedge clk1) begin
226 | 	g0cnt <= 6'd52; g1cnt <= 6'd36; g2cnt <= 6'd32; g3cnt <= 5'd28; g4cnt <= 5'd24; //
227 | 	g5cnt <= 5'd20; g6cnt <= 5'd16; g7cnt <= 5'd12; g8cnt <= 5'd8; g9cnt <= 5'd4; //
228 | 	case (state_1)
229 | 		Idle_1 : begin
230 | 			epoch_cnt <= 3'd1;
231 | 			g0cnt <= 6'd52; g1cnt <= 6'd36; g2cnt <= 6'd32; g3cnt <= 5'd28; g4cnt <= 5'd24;
232 | 			g5cnt <= 5'd20; g6cnt <= 5'd16; g7cnt <= 5'd12; g8cnt <= 5'd8; g9cnt <= 5'd4;
233 | 		end
234 | 		Work0_1 : begin
235 | 			if (in_valid1) begin
236 | 				g0cnt <= g0cnt_next; g1cnt <= g1cnt_next; g2cnt <= g2cnt_next; g3cnt <= g3cnt_next; g4cnt <= g4cnt_next;
237 | 				g5cnt <= g5cnt_next; g6cnt <= g6cnt_next; g7cnt <= g7cnt_next; g8cnt <= g8cnt_next; g9cnt <= g9cnt_next;
238 | 			end
239 | 		end
240 | 		Work1_1, Work2_1, Work3_1, Work4_1, Work5_1, Work6_1, Work7_1, Work8_1 : begin
241 | 				g0cnt <= g0cnt_next; g1cnt <= g1cnt_next; g2cnt <= g2cnt_next; g3cnt <= g3cnt_next; g4cnt <= g4cnt_next;
242 | 				g5cnt <= g5cnt_next; g6cnt <= g6cnt_next; g7cnt <= g7cnt_next; g8cnt <= g8cnt_next; g9cnt <= g9cnt_next;
243 | 		end
244 | 		Work9_1 : begin
245 | 			if (epoch_cnt_is_5) begin
246 | 				epoch_cnt <= 3'd1;
247 | 				g0cnt <= 6'd52; g1cnt <= 6'd36; g2cnt <= 6'd32; g3cnt <= 5'd28; g4cnt <= 5'd24;
248 | 				g5cnt <= 5'd20; g6cnt <= 5'd16; g7cnt <= 5'd12; g8cnt <= 5'd8; g9cnt <= 5'd4;
249 | 			end
250 | 			else begin
251 | 				epoch_cnt <= epoch_cnt + 3'd1;
252 | 				g0cnt <= g0cnt_next; g1cnt <= g1cnt_next; g2cnt <= g2cnt_next; g3cnt <= g3cnt_next; g4cnt <= g4cnt_next;
253 | 				g5cnt <= g5cnt_next; g6cnt <= g6cnt_next; g7cnt <= g7cnt_next; g8cnt <= g8cnt_next; g9cnt <= g9cnt_next;
254 | 			end
255 | 		end
256 | 	endcase
257 | end
258 | 
259 | always @(posedge clk1) begin
260 | 	player2 <= point2; //
261 | 	case (state_1)
262 | 		Work0_1 : begin
263 | 			player1 <= point1;
264 | 		end
265 | 		Work1_1, Work2_1, Work3_1, Work4_1 : begin
266 | 			player1 <= player_next;
267 | 		end
268 | 		Work5_1 : begin
269 | 			player2 <= point2;
270 | 		end
271 | 		Work6_1, Work7_1, Work8_1, Work9_1 : begin
272 | 			player2 <= player_next;
273 | 		end
274 | 	endcase
275 | end
276 | 
277 | always @(posedge clk1 or negedge rst_n) begin
278 | 	if (!rst_n) begin
279 | 		prob_flag_1 <= 1'b0;
280 | 		winner_flag_1 <= 1'b0;
281 | 	end
282 | 	else begin
283 | 		prob_flag_1 <= 1'b0;
284 | 		winner_flag_1 <= 1'b0;
285 | 		case (state_1)
286 | 			Work1_1, Work2_1, Work6_1, Work7_1 : begin
287 | 				prob_flag_1 <= 1'b1;
288 | 			end
289 | 			Work8_1 : begin
290 | 				winner_flag_1 <= 1'b1;
291 | 			end
292 | 		endcase
293 | 	end
294 | end
295 | 
296 | always @(posedge clk1) begin
297 | 	prob_dividend1_reg_1 <= dividend1_temp; //
298 | 	prob_dividend2_reg_1 <= dividend2_temp; //
299 | 	prob_divisor_reg_1 <= g0cnt_next; //
300 | 	winner_reg_1 <= 2'bx; //
301 | 	case (state_1)
302 | 		Work2_1, Work3_1, Work7_1, Work8_1 : begin
303 | 			prob_dividend1_reg_1 <= dividend1_temp;
304 | 			prob_dividend2_reg_1 <= dividend2_temp;
305 | 			prob_divisor_reg_1 <= g0cnt_next;
306 | 		end
307 | 		Work9_1 : begin
308 | 			if (player1 <= 6'd21 && player_next <= 6'd21) begin
309 | 				if (player1 > player_next) winner_reg_1 <= 2'b10;
310 | 				else if (player_next > player1) winner_reg_1 <= 2'b11;
311 | 				else winner_reg_1[1] <= 1'b0;
312 | 			end
313 | 			else if (player1 <= 6'd21) winner_reg_1 <= 2'b10;
314 | 			else if (player_next <= 6'd21) winner_reg_1 <= 2'b11;
315 | 			else winner_reg_1[1] <= 1'b0;
316 | 		end
317 | 	endcase
318 | end
319 | /*------------------------------*/
320 | 
321 | wire [5:0] divisor = prob_divisor_reg_3;
322 | 
323 | reg [12:0] rq1_cur;
324 | wire [12:0] rq1_nxt;
325 | wire [6:0] rq1_temp_0 = rq1_cur[12:6];
326 | wire signed [7:0] rq1_temp_1 = rq1_temp_0 - divisor;
327 | assign rq1_nxt = (rq1_temp_1[7] ?
328 | 	{rq1_temp_0[5:0], rq1_cur[5:0], 1'b0} :
329 | 	{rq1_temp_1[5:0], rq1_cur[5:0], 1'b1});
330 | reg [12:0] rq2_cur;
331 | wire [12:0] rq2_nxt;
332 | wire [6:0] rq2_temp_0 = rq2_cur[12:6];
333 | wire signed [7:0] rq2_temp_1 = rq2_temp_0 - divisor;
334 | assign rq2_nxt = (rq2_temp_1[7] ?
335 | 	{rq2_temp_0[5:0], rq2_cur[5:0], 1'b0} :
336 | 	{rq2_temp_1[5:0], rq2_cur[5:0], 1'b1});
337 | 
338 | reg [3:0] state_1_3, nxt_state_1_3;
339 | localparam Idle_1_3		= 4'b0000;
340 | localparam Work0_1_3	= 4'b0001;
341 | localparam Work1_1_3	= 4'b0011;
342 | localparam Work2_1_3	= 4'b0010;
343 | localparam Work3_1_3	= 4'b0110;
344 | localparam Work4_1_3	= 4'b0111;
345 | localparam Work5_1_3	= 4'b0101;
346 | localparam Work6_1_3	= 4'b0100;
347 | localparam Work7_1_3	= 4'b1100;
348 | localparam Work8_1_3	= 4'b1101;
349 | 
350 | wire [10:0] prob_dividend1_reg_3x100 = prob_dividend1_reg_3 * 7'd100;
351 | wire [12:0] prob_dividend2_reg_3x100 = prob_dividend2_reg_3 * 7'd100;
352 | 
353 | always @(*) begin
354 | 	nxt_state_1_3 <= state_1_3;
355 | 	case (state_1_3)
356 | 		Idle_1_3 :
357 | 			if (prob_flag_3) nxt_state_1_3 <= Work0_1_3;
358 | 		Work0_1_3 : nxt_state_1_3 <= Work1_1_3;
359 | 		Work1_1_3 : nxt_state_1_3 <= Work2_1_3;
360 | 		Work2_1_3 : nxt_state_1_3 <= Work3_1_3;
361 | 		Work3_1_3 : nxt_state_1_3 <= Work4_1_3;
362 | 		Work4_1_3 : nxt_state_1_3 <= Work5_1_3;
363 | 		Work5_1_3 : nxt_state_1_3 <= Work6_1_3;
364 | 		Work6_1_3 : nxt_state_1_3 <= Work7_1_3;
365 | 		Work7_1_3 : nxt_state_1_3 <= Work8_1_3;
366 | 		Work8_1_3 : nxt_state_1_3 <= Idle_1_3;
367 | 	endcase
368 | end
369 | 
370 | always @(posedge clk3 or negedge rst_n) begin
371 | 	if(!rst_n) state_1_3 <= Idle_1_3;
372 | 	else state_1_3 <= nxt_state_1_3;
373 | end
374 | 
375 | always @(posedge clk3) begin
376 | 	case (state_1_3)
377 | 		Work0_1_3 : begin
378 | 			rq1_cur <= prob_dividend1_reg_3x100;
379 | 			rq2_cur <= prob_dividend2_reg_3x100;
380 | 		end
381 | 		Work1_1_3, Work2_1_3, Work3_1_3, Work4_1_3, Work5_1_3, Work6_1_3, Work7_1_3 : begin
382 | 			rq1_cur <= rq1_nxt;
383 | 			rq2_cur <= rq2_nxt;
384 | 		end
385 | 	endcase
386 | end
387 | 
388 | always @(*) begin
389 | 	out_valid1 <= 1'b0;
390 | 	equal <= 1'b0;
391 | 	exceed <= 1'b0;
392 | 	case (state_1_3)
393 | 		Work2_1_3, Work3_1_3, Work4_1_3, Work5_1_3, Work6_1_3, Work7_1_3, Work8_1_3 : begin
394 | 			out_valid1 <= 1'b1;
395 | 			equal <= rq1_cur[0];
396 | 			exceed <= rq2_cur[0];
397 | 		end
398 | 	endcase
399 | end
400 | /*---------------*/
401 | 
402 | reg [1:0] state_2_3, nxt_state_2_3;
403 | localparam Idle_2_3		= 2'b00;
404 | localparam Work0_2_3	= 2'b01;
405 | localparam Work1_2_3	= 2'b11;
406 | 
407 | always @(*) begin
408 | 	nxt_state_2_3 <= state_2_3;
409 | 	case (state_2_3)
410 | 		Idle_2_3 :
411 | 			if (winner_flag_3) nxt_state_2_3 <= Work0_2_3;
412 | 		Work0_2_3 :
413 | 			if (winner_reg_3[1]) nxt_state_2_3 <= Work1_2_3;
414 | 			else nxt_state_2_3 <= Idle_2_3;
415 | 		Work1_2_3 : nxt_state_2_3 <= Idle_2_3;
416 | 	endcase
417 | end
418 | 
419 | always @(posedge clk3 or negedge rst_n) begin
420 | 	if(!rst_n) state_2_3 <= Idle_2_3;
421 | 	else state_2_3 <= nxt_state_2_3;
422 | end
423 | 
424 | always @(*) begin
425 | 	out_valid2 <= 1'b0;
426 | 	winner <= 1'b0;
427 | 	case (state_2_3)
428 | 		Work0_2_3 : begin
429 | 			out_valid2 <= 1'b1;
430 | 			winner <= winner_reg_3[1];
431 | 		end
432 | 		Work1_2_3 : begin
433 | 			out_valid2 <= 1'b1;
434 | 			winner <= winner_reg_3[0];
435 | 		end
436 | 	endcase
437 | end
438 | 
439 | endmodule
440 | 


--------------------------------------------------------------------------------
/Lab09/FD.sv:
--------------------------------------------------------------------------------
  1 | module FD(input clk, INF.FD_inf inf);
  2 | import usertype::*;
  3 | 
  4 | Action				d_act;
  5 | Restaurant_id		d_res_id;
  6 | Food_id             d_food_ID;
  7 | servings_of_food    d_ser_food;
  8 | Delivery_man_id		d_id;
  9 | Customer_status		d_ctm_status;
 10 | logic rd_id_is_same;
 11 | assign rd_id_is_same = (d_res_id == d_id);
 12 | 
 13 | logic restaurant_flag;
 14 | D_man_Info restaurant_data;
 15 | res_info restaurant;
 16 | 
 17 | logic delivery_man_flag;
 18 | D_man_Info delivery_man;
 19 | res_info delivery_man_data;
 20 | 
 21 | Error_Msg err_msg;
 22 | 
 23 | // Order
 24 | Error_Msg err_msg_ordered;
 25 | res_info restaurant_ordered;
 26 | logic order_ok;
 27 | assign order_ok = (err_msg_ordered == No_Err);
 28 | limit_of_orders order_temp;
 29 | always_ff @(posedge clk) begin
 30 | 	order_temp <= restaurant.limit_num_orders - restaurant.ser_FOOD1 - restaurant.ser_FOOD2 - restaurant.ser_FOOD3;
 31 | end
 32 | always_comb begin
 33 | 	err_msg_ordered <= No_Err;
 34 | 	if (order_temp < d_ser_food) err_msg_ordered <= Res_busy;
 35 | 
 36 | 	restaurant_ordered <= restaurant;
 37 | 	case (d_food_ID)
 38 | 		FOOD1 : restaurant_ordered.ser_FOOD1 <= restaurant.ser_FOOD1 + d_ser_food;
 39 | 		FOOD2 : restaurant_ordered.ser_FOOD2 <= restaurant.ser_FOOD2 + d_ser_food;
 40 | 		FOOD3 : restaurant_ordered.ser_FOOD3 <= restaurant.ser_FOOD3 + d_ser_food;
 41 | 	endcase
 42 | end
 43 | 
 44 | // Take
 45 | Error_Msg err_msg_took;
 46 | res_info restaurant_took;
 47 | D_man_Info delivery_man_took;
 48 | logic take_ok;
 49 | assign take_ok = (err_msg_took == No_Err);
 50 | servings_of_FOOD take_temp1;
 51 | always_comb begin
 52 | 	take_temp1 <= 'bx;
 53 | 	case (d_food_ID)
 54 | 		FOOD1 : take_temp1 <= restaurant.ser_FOOD1;
 55 | 		FOOD2 : take_temp1 <= restaurant.ser_FOOD2;
 56 | 		FOOD3 : take_temp1 <= restaurant.ser_FOOD3;
 57 | 	endcase
 58 | end
 59 | always_comb begin
 60 | 	err_msg_took <= No_Err;
 61 | 	if (delivery_man.ctm_info2.ctm_status != None) err_msg_took <= D_man_busy;
 62 | 	else if (take_temp1 < d_ser_food) err_msg_took <= No_Food;
 63 | 
 64 | 	restaurant_took <= restaurant;
 65 | 	case (d_food_ID)
 66 | 		FOOD1 : restaurant_took.ser_FOOD1 <= restaurant.ser_FOOD1 - d_ser_food;
 67 | 		FOOD2 : restaurant_took.ser_FOOD2 <= restaurant.ser_FOOD2 - d_ser_food;
 68 | 		FOOD3 : restaurant_took.ser_FOOD3 <= restaurant.ser_FOOD3 - d_ser_food;
 69 | 	endcase
 70 | 	delivery_man_took <= delivery_man;
 71 | 	if (delivery_man.ctm_info1.ctm_status == None || (delivery_man.ctm_info1.ctm_status == Normal && d_ctm_status == VIP)) begin
 72 | 		delivery_man_took.ctm_info1.ctm_status <= d_ctm_status;
 73 | 		delivery_man_took.ctm_info1.res_ID <= d_res_id;
 74 | 		delivery_man_took.ctm_info1.food_ID <= d_food_ID;
 75 | 		delivery_man_took.ctm_info1.ser_food <= d_ser_food;
 76 | 		delivery_man_took.ctm_info2 <= delivery_man.ctm_info1;
 77 | 	end
 78 | 	else begin
 79 | 		delivery_man_took.ctm_info2.ctm_status <= d_ctm_status;
 80 | 		delivery_man_took.ctm_info2.res_ID <= d_res_id;
 81 | 		delivery_man_took.ctm_info2.food_ID <= d_food_ID;
 82 | 		delivery_man_took.ctm_info2.ser_food <= d_ser_food;
 83 | 	end
 84 | end
 85 | 
 86 | // Deliver
 87 | Error_Msg err_msg_delivered;
 88 | D_man_Info delivery_man_delivered;
 89 | logic deliver_ok;
 90 | assign deliver_ok = (err_msg_delivered == No_Err);
 91 | always_comb begin
 92 | 	err_msg_delivered <= No_Err;
 93 | 	if (delivery_man.ctm_info1.ctm_status == None) err_msg_delivered <= No_customers;
 94 | 
 95 | 	delivery_man_delivered <= {delivery_man.ctm_info2, 16'b0};
 96 | end
 97 | 
 98 | // Cancel
 99 | Error_Msg err_msg_canceled;
100 | D_man_Info delivery_man_canceled;
101 | logic cancel_ok;
102 | assign cancel_ok = (err_msg_canceled == No_Err);
103 | logic res1_eq, food1_eq, ctm1_eq, res2_eq, food2_eq, ctm2_eq;
104 | always_comb begin
105 | 	res1_eq <= (/*delivery_man.ctm_info1.ctm_status != None && */delivery_man.ctm_info1.res_ID == d_res_id);
106 | 	food1_eq <= (delivery_man.ctm_info1.food_ID == d_food_ID);
107 | 	res2_eq <= (delivery_man.ctm_info2.ctm_status != None && delivery_man.ctm_info2.res_ID == d_res_id);
108 | 	food2_eq <= (delivery_man.ctm_info2.food_ID == d_food_ID);
109 | end
110 | assign ctm1_eq = (res1_eq && food1_eq);
111 | assign ctm2_eq = (res2_eq && food2_eq);
112 | always_comb begin
113 | 	err_msg_canceled <= No_Err;
114 | 	if (delivery_man.ctm_info1.ctm_status == None) err_msg_canceled <= Wrong_cancel;
115 | 	else if (!res1_eq && !res2_eq) err_msg_canceled <= Wrong_res_ID;
116 | 	else if (!ctm1_eq && !ctm2_eq) err_msg_canceled <= Wrong_food_ID;
117 | 
118 | 	delivery_man_canceled <= delivery_man;
119 | 	if (ctm1_eq) begin
120 | 		if (ctm2_eq) delivery_man_canceled.ctm_info1 <= 16'b0;
121 | 		else delivery_man_canceled.ctm_info1 <= delivery_man.ctm_info2;
122 | 		delivery_man_canceled.ctm_info2 <= 16'b0;
123 | 	end
124 | 	else begin
125 | 		if (ctm2_eq) delivery_man_canceled.ctm_info2 <= 16'b0;
126 | 	end
127 | end
128 | 
129 | enum logic [4:0] {
130 | 	Idle			= 5'd0,
131 | 	Order_res		= 5'd1,
132 | 	Order_food1		= 5'd2,
133 | 	Order_food2		= 5'd3,
134 | 	Order_Readr		= 5'd4,
135 | 	Take_id			= 5'd5,
136 | 	Take_cus1		= 5'd6,
137 | 	Take_cus2		= 5'd7,
138 | 	Take_Readd		= 5'd8,
139 | 	Deliver_id		= 5'd9,
140 | 	Cancel_res		= 5'd10,
141 | 	Cancel_food		= 5'd11,
142 | 	Cancel_id		= 5'd12,
143 | 	Read_res1		= 5'd13,
144 | 	Read_res2		= 5'd14,
145 | 	Read_d_man1		= 5'd15,
146 | 	Read_d_man2		= 5'd16,
147 | 	Order_calc		= 5'd17,
148 | 	Order_calc2		= 5'd18,
149 | 	Take_calc		= 5'd19,
150 | 	Deliver_calc	= 5'd20,
151 | 	Cancel_calc		= 5'd21,
152 | 	Write_res1		= 5'd22,
153 | 	Write_res2		= 5'd23,
154 | 	Write_d_man1	= 5'd24,
155 | 	Write_d_man2	= 5'd25,
156 | 	Output			= 5'd26
157 | } state, nxt_state;
158 | 
159 | always_comb begin
160 | 	nxt_state <= state;
161 | 	case (state)
162 | 		Idle :
163 | 			if (inf.act_valid) begin
164 | 				case (inf.D.d_act[0])
165 | 					Order	: nxt_state <= Order_res;
166 | 					Take	: nxt_state <= Take_id;
167 | 					Deliver	: nxt_state <= Deliver_id;
168 | 					Cancel	: nxt_state <= Cancel_res;
169 | 				endcase
170 | 			end
171 | 		Order_res :
172 | 			if (inf.res_valid) nxt_state <= Order_food1;
173 | 			else if (inf.food_valid) nxt_state <= Order_calc;
174 | 		Order_food1 :
175 | 			if (inf.food_valid) nxt_state <= Order_Readr;
176 | 			else nxt_state <= Order_food2;
177 | 		Order_food2 :
178 | 			if (inf.food_valid) begin
179 | 				if (restaurant_flag || inf.C_out_valid) nxt_state <= Order_calc;
180 | 				else nxt_state <= Order_Readr;
181 | 			end
182 | 		Order_Readr :
183 | 			if (restaurant_flag || inf.C_out_valid) nxt_state <= Order_calc;
184 | 		Take_id :
185 | 			if (inf.id_valid) nxt_state <= Take_cus1;
186 | 			else if (inf.cus_valid) nxt_state <= Read_res1;
187 | 		Take_cus1 :
188 | 			if (inf.cus_valid) nxt_state <= Read_res1;
189 | 			else nxt_state <= Take_cus2;
190 | 		Take_cus2 :
191 | 			if (inf.cus_valid) begin
192 | 				if (delivery_man_flag || inf.C_out_valid) nxt_state <= Read_res1;
193 | 				else nxt_state <= Take_Readd;
194 | 			end
195 | 		Take_Readd :
196 | 			if (delivery_man_flag || inf.C_out_valid) nxt_state <= Read_res1;
197 | 		Deliver_id :
198 | 			if (inf.id_valid) nxt_state <= Read_d_man1;
199 | 		Cancel_res :
200 | 			if (inf.res_valid) nxt_state <= Cancel_food;
201 | 		Cancel_food :
202 | 			if (inf.food_valid) nxt_state <= Cancel_id;
203 | 		Cancel_id :
204 | 			if (inf.id_valid) nxt_state <= Read_d_man1;
205 | 		Read_res1 : nxt_state <= Read_res2;
206 | 		Read_res2 :
207 | 			if (inf.C_out_valid) begin
208 | 				case (d_act)
209 | 					Take	: nxt_state <= Take_calc;
210 | 				endcase
211 | 			end
212 | 		Read_d_man1 : nxt_state <= Read_d_man2;
213 | 		Read_d_man2 :
214 | 			if (inf.C_out_valid) begin
215 | 				case (d_act)
216 | 					Deliver	: nxt_state <= Deliver_calc;
217 | 					Cancel	: nxt_state <= Cancel_calc;
218 | 				endcase
219 | 			end
220 | 		Order_calc : nxt_state <= Order_calc2;
221 | 		Order_calc2 :
222 | 			if (order_ok) nxt_state <= Write_res1;
223 | 			else nxt_state <= Output;
224 | 		Take_calc :
225 | 			if (take_ok) begin
226 | 				if (rd_id_is_same) nxt_state <= Write_d_man1;
227 | 				else nxt_state <= Write_res1;
228 | 			end
229 | 			else nxt_state <= Output;
230 | 		Deliver_calc :
231 | 			if (deliver_ok) nxt_state <= Write_d_man1;
232 | 			else nxt_state <= Output;
233 | 		Cancel_calc :
234 | 			if (cancel_ok) nxt_state <= Write_d_man1;
235 | 			else nxt_state <= Output;
236 | 		Write_res1 : nxt_state <= Write_res2;
237 | 		Write_res2 :
238 | 			if (inf.C_out_valid) begin
239 | 				nxt_state <= Output;
240 | 				case (d_act)
241 | 					//Order	: nxt_state <= Output;
242 | 					Take	: nxt_state <= Write_d_man1;
243 | 				endcase
244 | 			end
245 | 		Write_d_man1 : nxt_state <= Write_d_man2;
246 | 		Write_d_man2 :
247 | 			if (inf.C_out_valid) begin
248 | 				nxt_state <= Output;
249 | 				/*case (d_act)
250 | 					Take	: nxt_state <= Output;
251 | 					Deliver	: nxt_state <= Output;
252 | 					Cancel	: nxt_state <= Output;
253 | 				endcase*/
254 | 			end
255 | 		Output : nxt_state <= Idle;
256 | 	endcase
257 | end
258 | 
259 | always_ff @(posedge clk or negedge inf.rst_n) begin
260 | 	if (!inf.rst_n) state <= Idle;
261 | 	else state <= nxt_state;
262 | end
263 | 
264 | always_comb begin
265 | 	inf.C_in_valid <= 1'b0;
266 | 	inf.C_r_wb <= 1'b0;
267 | 	inf.C_addr <= 8'b0;
268 | 	inf.C_data_w <= 64'b0;
269 | 	case (state)
270 | 		Order_food1, Read_res1 : begin
271 | 			inf.C_in_valid <= 1'b1;
272 | 			inf.C_r_wb <= 1'b1;
273 | 			inf.C_addr <= d_res_id;
274 | 		end
275 | 		Take_cus1, Read_d_man1 : begin
276 | 			inf.C_in_valid <= 1'b1;
277 | 			inf.C_r_wb <= 1'b1;
278 | 			inf.C_addr <= d_id;
279 | 		end
280 | 		Write_res1 : begin
281 | 			inf.C_in_valid <= 1'b1;
282 | 			inf.C_r_wb <= 1'b0;
283 | 			inf.C_addr <= d_res_id;
284 | 			inf.C_data_w <= {restaurant_data, restaurant};
285 | 		end
286 | 		Write_d_man1 : begin
287 | 			inf.C_in_valid <= 1'b1;
288 | 			inf.C_r_wb <= 1'b0;
289 | 			inf.C_addr <= d_id;
290 | 			inf.C_data_w <= {delivery_man, delivery_man_data};
291 | 		end
292 | 	endcase
293 | end
294 | 
295 | always_ff @(posedge clk) begin
296 | 	case (state)
297 | 		Idle : begin
298 | 			if (inf.act_valid) begin
299 | 				d_act <= inf.D.d_act[0];
300 | 			end
301 | 		end
302 | 		Order_res : begin
303 | 			if (inf.res_valid) begin
304 | 				d_res_id <= inf.D.d_res_id[0];
305 | 			end
306 | 			else if (inf.food_valid) begin
307 | 				d_food_ID <= inf.D.d_food_ID_ser[0].d_food_ID;
308 | 				d_ser_food <= inf.D.d_food_ID_ser[0].d_ser_food;
309 | 			end
310 | 		end
311 | 		Order_food1, Order_food2 : begin
312 | 			if (inf.food_valid) begin
313 | 				d_food_ID <= inf.D.d_food_ID_ser[0].d_food_ID;
314 | 				d_ser_food <= inf.D.d_food_ID_ser[0].d_ser_food;
315 | 			end
316 | 		end
317 | 		Take_id : begin
318 | 			if (inf.id_valid) begin
319 | 				d_id <= inf.D.d_id[0];
320 | 			end
321 | 			else if (inf.cus_valid) begin
322 | 				d_ctm_status <= inf.D.d_ctm_info[0].ctm_status;
323 | 				d_res_id <= inf.D.d_ctm_info[0].res_ID;
324 | 				d_food_ID <= inf.D.d_ctm_info[0].food_ID;
325 | 				d_ser_food <= inf.D.d_ctm_info[0].ser_food;
326 | 			end
327 | 		end
328 | 		Take_cus1, Take_cus2 : begin
329 | 			if (inf.cus_valid) begin
330 | 				d_ctm_status <= inf.D.d_ctm_info[0].ctm_status;
331 | 				d_res_id <= inf.D.d_ctm_info[0].res_ID;
332 | 				d_food_ID <= inf.D.d_ctm_info[0].food_ID;
333 | 				d_ser_food <= inf.D.d_ctm_info[0].ser_food;
334 | 			end
335 | 		end
336 | 		Deliver_id : begin
337 | 			if (inf.id_valid) begin
338 | 				d_id <= inf.D.d_id[0];
339 | 			end
340 | 		end
341 | 		Cancel_res : begin
342 | 			if (inf.res_valid) begin
343 | 				d_res_id <= inf.D.d_res_id[0];
344 | 			end
345 | 		end
346 | 		Cancel_food : begin
347 | 			if (inf.food_valid) begin
348 | 				d_food_ID <= inf.D.d_food_ID_ser[0].d_food_ID;
349 | 				d_ser_food <= inf.D.d_food_ID_ser[0].d_ser_food;
350 | 			end
351 | 		end
352 | 		Cancel_id : begin
353 | 			if (inf.id_valid) begin
354 | 				d_id <= inf.D.d_id[0];
355 | 			end
356 | 		end
357 | 	endcase
358 | end
359 | 
360 | always_ff @(posedge clk) begin
361 | 	case (state)
362 | 		Idle : begin
363 | 			restaurant_flag <= 1'b0;
364 | 			delivery_man_flag <= 1'b0;
365 | 			err_msg <= No_Err;
366 | 		end
367 | 		Order_food2 : begin
368 | 			if (inf.C_out_valid) begin
369 | 				restaurant_flag <= 1'b1;
370 | 				restaurant_data	<= inf.C_data_r[63:32];
371 | 				restaurant		<= inf.C_data_r[31: 0];
372 | 			end
373 | 		end
374 | 		Take_cus2 : begin
375 | 			if (inf.C_out_valid) begin
376 | 				delivery_man_flag <= 1'b1;
377 | 				delivery_man		<= inf.C_data_r[63:32];
378 | 				delivery_man_data	<= inf.C_data_r[31: 0];
379 | 			end
380 | 		end
381 | 		Order_Readr, Read_res2 : begin
382 | 			if (inf.C_out_valid) begin
383 | 				restaurant_data	<= inf.C_data_r[63:32];
384 | 				restaurant		<= inf.C_data_r[31: 0];
385 | 			end
386 | 		end
387 | 		Take_Readd, Read_d_man2 : begin
388 | 			if (inf.C_out_valid) begin
389 | 				delivery_man		<= inf.C_data_r[63:32];
390 | 				delivery_man_data	<= inf.C_data_r[31: 0];
391 | 			end
392 | 		end
393 | 		Order_calc2 : begin
394 | 			err_msg <= err_msg_ordered;
395 | 			if (order_ok) begin
396 | 				restaurant <= restaurant_ordered;
397 | 				//if (rd_id_is_same) delivery_man_data <= restaurant_ordered;//
398 | 			end
399 | 		end
400 | 		Take_calc : begin
401 | 			err_msg <= err_msg_took;
402 | 			if (take_ok) begin
403 | 				restaurant <= restaurant_took;
404 | 				if (rd_id_is_same) delivery_man_data <= restaurant_took;
405 | 				delivery_man <= delivery_man_took;
406 | 				//if (rd_id_is_same) restaurant_data <= delivery_man_took;//
407 | 			end
408 | 		end
409 | 		Deliver_calc : begin
410 | 			err_msg <= err_msg_delivered;
411 | 			if (deliver_ok) begin
412 | 				delivery_man <= delivery_man_delivered;
413 | 				//if (rd_id_is_same) restaurant_data <= delivery_man_delivered;//
414 | 			end
415 | 		end
416 | 		Cancel_calc : begin
417 | 			err_msg <= err_msg_canceled;
418 | 			if (cancel_ok) begin
419 | 				delivery_man <= delivery_man_canceled;
420 | 				//if (rd_id_is_same) restaurant_data <= delivery_man_canceled;//
421 | 			end
422 | 		end
423 | 	endcase
424 | end
425 | 
426 | always_comb begin
427 | 	inf.out_valid <= 1'b0;
428 | 	inf.err_msg <= No_Err;
429 | 	inf.complete <= 1'b0;
430 | 	inf.out_info <= 64'b0;
431 | 	case (state)
432 | 		Output : begin
433 | 			inf.out_valid <= 1'b1;
434 | 			inf.err_msg <= err_msg;
435 | 			if (err_msg == No_Err) begin
436 | 				inf.complete <= 1'b1;
437 | 				case (d_act)
438 | 					Order	: inf.out_info <= {32'b0, restaurant};
439 | 					Take	: inf.out_info <= {delivery_man, restaurant};
440 | 					Deliver	: inf.out_info <= {delivery_man, 32'b0};
441 | 					Cancel	: inf.out_info <= {delivery_man, 32'b0};
442 | 				endcase
443 | 			end
444 | 		end
445 | 	endcase
446 | end
447 | 
448 | endmodule
449 | 


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 152 | 00 00 00 00
 153 | @10130
 154 | 0e 02 02 02
 155 | @10134
 156 | 00 00 00 00
 157 | @10138
 158 | 0e 02 02 02
 159 | @1013c
 160 | 00 00 00 00
 161 | @10140
 162 | 0e 02 02 02
 163 | @10144
 164 | 00 00 00 00
 165 | @10148
 166 | 0e 02 02 02
 167 | @1014c
 168 | 00 00 00 00
 169 | @10150
 170 | 0e 02 02 02
 171 | @10154
 172 | 00 00 00 00
 173 | @10158
 174 | 0e 02 02 02
 175 | @1015c
 176 | 00 00 00 00
 177 | @10160
 178 | 0e 02 02 02
 179 | @10164
 180 | 00 00 00 00
 181 | @10168
 182 | 0e 02 02 02
 183 | @1016c
 184 | 00 00 00 00
 185 | @10170
 186 | 0e 02 02 02
 187 | @10174
 188 | 00 00 00 00
 189 | @10178
 190 | 0e 02 02 02
 191 | @1017c
 192 | 00 00 00 00
 193 | @10180
 194 | 0e 02 02 02
 195 | @10184
 196 | 00 00 00 00
 197 | @10188
 198 | 0e 02 02 02
 199 | @1018c
 200 | 00 00 00 00
 201 | @10190
 202 | 0e 02 02 02
 203 | @10194
 204 | 00 00 00 00
 205 | @10198
 206 | 0e 02 02 02
 207 | @1019c
 208 | 00 00 00 00
 209 | @101a0
 210 | 0e 02 02 02
 211 | @101a4
 212 | 00 00 00 00
 213 | @101a8
 214 | 0e 02 02 02
 215 | @101ac
 216 | 00 00 00 00
 217 | @101b0
 218 | 0e 02 02 02
 219 | @101b4
 220 | 00 00 00 00
 221 | @101b8
 222 | 0e 02 02 02
 223 | @101bc
 224 | 00 00 00 00
 225 | @101c0
 226 | 0e 02 02 02
 227 | @101c4
 228 | 00 00 00 00
 229 | @101c8
 230 | 0e 02 02 02
 231 | @101cc
 232 | 00 00 00 00
 233 | @101d0
 234 | 0e 02 02 02
 235 | @101d4
 236 | 00 00 00 00
 237 | @101d8
 238 | 0e 02 02 02
 239 | @101dc
 240 | 00 00 00 00
 241 | @101e0
 242 | 0e 02 02 02
 243 | @101e4
 244 | 40 11 40 11
 245 | @101e8
 246 | 0e 02 02 02
 247 | @101ec
 248 | 40 11 40 11
 249 | @101f0
 250 | 0e 02 02 02
 251 | @101f4
 252 | 40 11 40 11
 253 | @101f8
 254 | 0e 02 02 02
 255 | @101fc
 256 | 40 11 40 11
 257 | @10200
 258 | 0e 02 02 02
 259 | @10204
 260 | 40 11 40 11
 261 | @10208
 262 | 0e 02 02 02
 263 | @1020c
 264 | 40 11 40 11
 265 | @10210
 266 | 0e 02 02 02
 267 | @10214
 268 | 40 11 40 11
 269 | @10218
 270 | 0e 02 02 02
 271 | @1021c
 272 | 40 11 40 11
 273 | @10220
 274 | 0e 02 02 02
 275 | @10224
 276 | 40 11 40 11
 277 | @10228
 278 | 0e 02 02 02
 279 | @1022c
 280 | 40 11 40 11
 281 | @10230
 282 | 0e 02 02 02
 283 | @10234
 284 | 40 11 40 11
 285 | @10238
 286 | 0e 02 02 02
 287 | @1023c
 288 | 40 11 40 11
 289 | @10240
 290 | 0e 02 02 02
 291 | @10244
 292 | 40 11 40 11
 293 | @10248
 294 | 0e 02 02 02
 295 | @1024c
 296 | 40 11 40 11
 297 | @10250
 298 | 0e 02 02 02
 299 | @10254
 300 | 40 11 40 11
 301 | @10258
 302 | 0e 02 02 02
 303 | @1025c
 304 | 40 11 40 11
 305 | @10260
 306 | 0e 02 02 02
 307 | @10264
 308 | 40 11 40 11
 309 | @10268
 310 | 0e 02 02 02
 311 | @1026c
 312 | 40 11 40 11
 313 | @10270
 314 | 0e 02 02 02
 315 | @10274
 316 | 40 11 40 11
 317 | @10278
 318 | 0e 02 02 02
 319 | @1027c
 320 | 40 11 40 11
 321 | @10280
 322 | 0e 02 02 02
 323 | @10284
 324 | 40 11 40 11
 325 | @10288
 326 | 0e 02 02 02
 327 | @1028c
 328 | 40 11 40 11
 329 | @10290
 330 | 0e 02 02 02
 331 | @10294
 332 | 40 11 40 11
 333 | @10298
 334 | 0e 02 02 02
 335 | @1029c
 336 | 40 11 40 11
 337 | @102a0
 338 | 0e 02 02 02
 339 | @102a4
 340 | 40 11 40 11
 341 | @102a8
 342 | 0e 02 02 02
 343 | @102ac
 344 | 40 11 40 11
 345 | @102b0
 346 | 0e 02 02 02
 347 | @102b4
 348 | 40 11 40 11
 349 | @102b8
 350 | 0e 02 02 02
 351 | @102bc
 352 | 40 11 40 11
 353 | @102c0
 354 | 0e 02 02 02
 355 | @102c4
 356 | 40 11 40 11
 357 | @102c8
 358 | 0e 02 02 02
 359 | @102cc
 360 | 40 11 40 11
 361 | @102d0
 362 | 0e 02 02 02
 363 | @102d4
 364 | 40 11 40 11
 365 | @102d8
 366 | 0e 02 02 02
 367 | @102dc
 368 | 40 11 40 11
 369 | @102e0
 370 | 0e 02 02 02
 371 | @102e4
 372 | 40 11 40 11
 373 | @102e8
 374 | 0e 02 02 02
 375 | @102ec
 376 | 40 11 40 11
 377 | @102f0
 378 | 0e 02 02 02
 379 | @102f4
 380 | 40 11 40 11
 381 | @102f8
 382 | 0e 02 02 02
 383 | @102fc
 384 | 40 11 40 11
 385 | @10300
 386 | 0e 02 02 02
 387 | @10304
 388 | 40 11 40 11
 389 | @10308
 390 | 0e 02 02 02
 391 | @1030c
 392 | 40 11 40 11
 393 | @10310
 394 | 0e 02 02 02
 395 | @10314
 396 | 40 11 40 11
 397 | @10318
 398 | 0e 02 02 02
 399 | @1031c
 400 | 40 11 40 11
 401 | @10320
 402 | 0e 02 02 02
 403 | @10324
 404 | 40 11 40 11
 405 | @10328
 406 | 0e 02 02 02
 407 | @1032c
 408 | 40 11 40 11
 409 | @10330
 410 | 0e 02 02 02
 411 | @10334
 412 | 40 11 40 11
 413 | @10338
 414 | 0e 02 02 02
 415 | @1033c
 416 | 40 11 40 11
 417 | @10340
 418 | 0e 02 02 02
 419 | @10344
 420 | 40 11 40 11
 421 | @10348
 422 | 0e 02 02 02
 423 | @1034c
 424 | 40 11 40 11
 425 | @10350
 426 | 0e 02 02 02
 427 | @10354
 428 | 40 11 40 11
 429 | @10358
 430 | 0e 02 02 02
 431 | @1035c
 432 | 40 11 40 11
 433 | @10360
 434 | 0e 02 02 02
 435 | @10364
 436 | 40 11 40 11
 437 | @10368
 438 | 0e 02 02 02
 439 | @1036c
 440 | 40 11 40 11
 441 | @10370
 442 | 0e 02 02 02
 443 | @10374
 444 | 40 11 40 11
 445 | @10378
 446 | 0e 02 02 02
 447 | @1037c
 448 | 40 11 40 11
 449 | @10380
 450 | 0e 02 02 02
 451 | @10384
 452 | 40 11 40 11
 453 | @10388
 454 | 0e 02 02 02
 455 | @1038c
 456 | 40 11 40 11
 457 | @10390
 458 | 0e 02 02 02
 459 | @10394
 460 | 40 11 40 11
 461 | @10398
 462 | 0e 02 02 02
 463 | @1039c
 464 | 40 11 40 11
 465 | @103a0
 466 | 0e 02 02 02
 467 | @103a4
 468 | 40 11 40 11
 469 | @103a8
 470 | 0e 02 02 02
 471 | @103ac
 472 | 40 11 40 11
 473 | @103b0
 474 | 0e 02 02 02
 475 | @103b4
 476 | 40 11 40 11
 477 | @103b8
 478 | 0e 02 02 02
 479 | @103bc
 480 | 40 11 40 11
 481 | @103c0
 482 | 0e 02 02 02
 483 | @103c4
 484 | 40 11 40 11
 485 | @103c8
 486 | 0e 02 02 02
 487 | @103cc
 488 | 40 11 40 11
 489 | @103d0
 490 | 0e 02 02 02
 491 | @103d4
 492 | 40 11 40 11
 493 | @103d8
 494 | 0e 02 02 02
 495 | @103dc
 496 | 40 11 40 11
 497 | @103e0
 498 | 0e 02 02 02
 499 | @103e4
 500 | 40 11 40 11
 501 | @103e8
 502 | 0e 02 02 02
 503 | @103ec
 504 | 40 11 40 11
 505 | @103f0
 506 | 0e 02 02 02
 507 | @103f4
 508 | 40 11 40 11
 509 | @103f8
 510 | 0e 02 02 02
 511 | @103fc
 512 | 40 11 40 11
 513 | @10400
 514 | 0e 02 02 02
 515 | @10404
 516 | 40 11 40 11
 517 | @10408
 518 | 0e 02 02 02
 519 | @1040c
 520 | 40 11 40 11
 521 | @10410
 522 | 0e 02 02 02
 523 | @10414
 524 | 40 11 40 11
 525 | @10418
 526 | 0e 02 02 02
 527 | @1041c
 528 | 40 11 40 11
 529 | @10420
 530 | 0e 02 02 02
 531 | @10424
 532 | 40 11 40 11
 533 | @10428
 534 | 0e 02 02 02
 535 | @1042c
 536 | 40 11 40 11
 537 | @10430
 538 | 0e 02 02 02
 539 | @10434
 540 | 40 11 40 11
 541 | @10438
 542 | 0e 02 02 02
 543 | @1043c
 544 | 40 11 40 11
 545 | @10440
 546 | 0e 02 02 02
 547 | @10444
 548 | 40 11 40 11
 549 | @10448
 550 | 0e 02 02 02
 551 | @1044c
 552 | 40 11 40 11
 553 | @10450
 554 | 0e 02 02 02
 555 | @10454
 556 | 40 11 40 11
 557 | @10458
 558 | 0e 02 02 02
 559 | @1045c
 560 | 40 11 40 11
 561 | @10460
 562 | 0e 02 02 02
 563 | @10464
 564 | 40 11 40 11
 565 | @10468
 566 | 0e 02 02 02
 567 | @1046c
 568 | 40 11 40 11
 569 | @10470
 570 | 0e 02 02 02
 571 | @10474
 572 | 40 11 40 11
 573 | @10478
 574 | 0e 02 02 02
 575 | @1047c
 576 | 40 11 40 11
 577 | @10480
 578 | 0e 02 02 02
 579 | @10484
 580 | 40 11 40 11
 581 | @10488
 582 | 0e 02 02 02
 583 | @1048c
 584 | 40 11 40 11
 585 | @10490
 586 | 0e 02 02 02
 587 | @10494
 588 | 40 11 40 11
 589 | @10498
 590 | 0e 02 02 02
 591 | @1049c
 592 | 40 11 40 11
 593 | @104a0
 594 | 0e 02 02 02
 595 | @104a4
 596 | 40 11 40 11
 597 | @104a8
 598 | 0e 02 02 02
 599 | @104ac
 600 | 40 11 40 11
 601 | @104b0
 602 | 0e 02 02 02
 603 | @104b4
 604 | 40 11 40 11
 605 | @104b8
 606 | 0e 02 02 02
 607 | @104bc
 608 | 40 11 40 11
 609 | @104c0
 610 | 0e 02 02 02
 611 | @104c4
 612 | 40 11 40 11
 613 | @104c8
 614 | 0e 02 02 02
 615 | @104cc
 616 | 40 11 40 11
 617 | @104d0
 618 | 0e 02 02 02
 619 | @104d4
 620 | 40 11 40 11
 621 | @104d8
 622 | 0e 02 02 02
 623 | @104dc
 624 | 40 11 40 11
 625 | @104e0
 626 | 0e 02 02 02
 627 | @104e4
 628 | 40 11 40 11
 629 | @104e8
 630 | 0e 02 02 02
 631 | @104ec
 632 | 40 11 40 11
 633 | @104f0
 634 | 0e 02 02 02
 635 | @104f4
 636 | 40 11 40 11
 637 | @104f8
 638 | 0e 02 02 02
 639 | @104fc
 640 | 40 11 40 11
 641 | @10500
 642 | 0e 02 02 02
 643 | @10504
 644 | 40 11 40 11
 645 | @10508
 646 | 0e 02 02 02
 647 | @1050c
 648 | 40 11 40 11
 649 | @10510
 650 | 0e 02 02 02
 651 | @10514
 652 | 40 11 40 11
 653 | @10518
 654 | 0e 02 02 02
 655 | @1051c
 656 | 40 11 40 11
 657 | @10520
 658 | 0e 02 02 02
 659 | @10524
 660 | 40 11 40 11
 661 | @10528
 662 | 0e 02 02 02
 663 | @1052c
 664 | 40 11 40 11
 665 | @10530
 666 | 0e 02 02 02
 667 | @10534
 668 | 40 11 40 11
 669 | @10538
 670 | 0e 02 02 02
 671 | @1053c
 672 | 40 11 40 11
 673 | @10540
 674 | 0e 02 02 02
 675 | @10544
 676 | 40 11 40 11
 677 | @10548
 678 | 0e 02 02 02
 679 | @1054c
 680 | 40 11 40 11
 681 | @10550
 682 | 0e 02 02 02
 683 | @10554
 684 | 40 11 40 11
 685 | @10558
 686 | 0e 02 02 02
 687 | @1055c
 688 | 40 11 40 11
 689 | @10560
 690 | 0e 02 02 02
 691 | @10564
 692 | 40 11 40 11
 693 | @10568
 694 | 0e 02 02 02
 695 | @1056c
 696 | 40 11 40 11
 697 | @10570
 698 | 0e 02 02 02
 699 | @10574
 700 | 40 11 40 11
 701 | @10578
 702 | 0e 02 02 02
 703 | @1057c
 704 | 40 11 40 11
 705 | @10580
 706 | 0e 02 02 02
 707 | @10584
 708 | 40 11 40 11
 709 | @10588
 710 | 0e 02 02 02
 711 | @1058c
 712 | 40 11 40 11
 713 | @10590
 714 | 0e 02 02 02
 715 | @10594
 716 | 40 11 40 11
 717 | @10598
 718 | 0e 02 02 02
 719 | @1059c
 720 | 40 11 40 11
 721 | @105a0
 722 | 0e 02 02 02
 723 | @105a4
 724 | 40 11 40 11
 725 | @105a8
 726 | 0e 02 02 02
 727 | @105ac
 728 | 40 11 40 11
 729 | @105b0
 730 | 0e 02 02 02
 731 | @105b4
 732 | 40 11 40 11
 733 | @105b8
 734 | 0e 02 02 02
 735 | @105bc
 736 | 40 11 40 11
 737 | @105c0
 738 | 0e 02 02 02
 739 | @105c4
 740 | 40 11 40 11
 741 | @105c8
 742 | 0e 02 02 02
 743 | @105cc
 744 | 40 11 40 11
 745 | @105d0
 746 | 0e 02 02 02
 747 | @105d4
 748 | 40 11 40 11
 749 | @105d8
 750 | 0e 02 02 02
 751 | @105dc
 752 | 40 11 40 11
 753 | @105e0
 754 | 0e 02 02 02
 755 | @105e4
 756 | 40 11 40 11
 757 | @105e8
 758 | 0e 02 02 02
 759 | @105ec
 760 | 40 11 40 11
 761 | @105f0
 762 | 0e 02 02 02
 763 | @105f4
 764 | 40 11 40 11
 765 | @105f8
 766 | 0e 02 02 02
 767 | @105fc
 768 | 40 11 40 11
 769 | @10600
 770 | 0e 02 02 02
 771 | @10604
 772 | 40 11 40 11
 773 | @10608
 774 | 0e 02 02 02
 775 | @1060c
 776 | 40 11 40 11
 777 | @10610
 778 | 0e 02 02 02
 779 | @10614
 780 | 40 11 40 11
 781 | @10618
 782 | 0e 02 02 02
 783 | @1061c
 784 | 40 11 40 11
 785 | @10620
 786 | 0e 02 02 02
 787 | @10624
 788 | 40 11 40 11
 789 | @10628
 790 | 0e 02 02 02
 791 | @1062c
 792 | 40 11 40 11
 793 | @10630
 794 | 0e 02 02 02
 795 | @10634
 796 | 40 11 40 11
 797 | @10638
 798 | 0e 02 02 02
 799 | @1063c
 800 | 40 11 40 11
 801 | @10640
 802 | 0e 02 02 02
 803 | @10644
 804 | 40 11 40 11
 805 | @10648
 806 | 0e 02 02 02
 807 | @1064c
 808 | 40 11 40 11
 809 | @10650
 810 | 0e 02 02 02
 811 | @10654
 812 | 40 11 40 11
 813 | @10658
 814 | 0e 02 02 02
 815 | @1065c
 816 | 40 11 40 11
 817 | @10660
 818 | 0e 02 02 02
 819 | @10664
 820 | 40 11 40 11
 821 | @10668
 822 | 0e 02 02 02
 823 | @1066c
 824 | 40 11 40 11
 825 | @10670
 826 | 0e 02 02 02
 827 | @10674
 828 | 40 11 40 11
 829 | @10678
 830 | 0e 02 02 02
 831 | @1067c
 832 | 40 11 40 11
 833 | @10680
 834 | 0e 02 02 02
 835 | @10684
 836 | 40 11 40 11
 837 | @10688
 838 | 0e 02 02 02
 839 | @1068c
 840 | 40 11 40 11
 841 | @10690
 842 | 0e 02 02 02
 843 | @10694
 844 | 40 11 40 11
 845 | @10698
 846 | 0e 02 02 02
 847 | @1069c
 848 | 40 11 40 11
 849 | @106a0
 850 | 0e 02 02 02
 851 | @106a4
 852 | 40 11 40 11
 853 | @106a8
 854 | 0e 02 02 02
 855 | @106ac
 856 | 40 11 40 11
 857 | @106b0
 858 | 0e 02 02 02
 859 | @106b4
 860 | 40 11 40 11
 861 | @106b8
 862 | 0e 02 02 02
 863 | @106bc
 864 | 40 11 40 11
 865 | @106c0
 866 | 0e 02 02 02
 867 | @106c4
 868 | 40 11 40 11
 869 | @106c8
 870 | 0e 02 02 02
 871 | @106cc
 872 | 40 11 40 11
 873 | @106d0
 874 | 0e 02 02 02
 875 | @106d4
 876 | 40 11 40 11
 877 | @106d8
 878 | 0e 02 02 02
 879 | @106dc
 880 | 40 11 40 11
 881 | @106e0
 882 | 0e 02 02 02
 883 | @106e4
 884 | 40 11 40 11
 885 | @106e8
 886 | 0e 02 02 02
 887 | @106ec
 888 | 40 11 40 11
 889 | @106f0
 890 | 0e 02 02 02
 891 | @106f4
 892 | 40 11 40 11
 893 | @106f8
 894 | 0e 02 02 02
 895 | @106fc
 896 | 40 11 40 11
 897 | @10700
 898 | 0e 02 02 02
 899 | @10704
 900 | 40 11 40 11
 901 | @10708
 902 | 0e 02 02 02
 903 | @1070c
 904 | 40 11 40 11
 905 | @10710
 906 | 0e 02 02 02
 907 | @10714
 908 | 40 11 40 11
 909 | @10718
 910 | 0e 02 02 02
 911 | @1071c
 912 | 40 11 40 11
 913 | @10720
 914 | 0e 02 02 02
 915 | @10724
 916 | 40 11 40 11
 917 | @10728
 918 | 0e 02 02 02
 919 | @1072c
 920 | 40 11 40 11
 921 | @10730
 922 | 0e 02 02 02
 923 | @10734
 924 | 40 11 40 11
 925 | @10738
 926 | 0e 02 02 02
 927 | @1073c
 928 | 40 11 40 11
 929 | @10740
 930 | 0e 02 02 02
 931 | @10744
 932 | 40 11 40 11
 933 | @10748
 934 | 0e 02 02 02
 935 | @1074c
 936 | 40 11 40 11
 937 | @10750
 938 | 0e 02 02 02
 939 | @10754
 940 | 40 11 40 11
 941 | @10758
 942 | 0e 02 02 02
 943 | @1075c
 944 | 40 11 40 11
 945 | @10760
 946 | 0e 02 02 02
 947 | @10764
 948 | 40 11 40 11
 949 | @10768
 950 | 0e 02 02 02
 951 | @1076c
 952 | 40 11 40 11
 953 | @10770
 954 | 0e 02 02 02
 955 | @10774
 956 | 40 11 40 11
 957 | @10778
 958 | 0e 02 02 02
 959 | @1077c
 960 | 40 11 40 11
 961 | @10780
 962 | 0e 02 02 02
 963 | @10784
 964 | 40 11 40 11
 965 | @10788
 966 | 0e 02 02 02
 967 | @1078c
 968 | 40 11 40 11
 969 | @10790
 970 | 0e 02 02 02
 971 | @10794
 972 | 40 11 40 11
 973 | @10798
 974 | 0e 02 02 02
 975 | @1079c
 976 | 40 11 40 11
 977 | @107a0
 978 | 0e 02 02 02
 979 | @107a4
 980 | 40 11 40 11
 981 | @107a8
 982 | 0e 02 02 02
 983 | @107ac
 984 | 40 11 40 11
 985 | @107b0
 986 | 0e 02 02 02
 987 | @107b4
 988 | 40 11 40 11
 989 | @107b8
 990 | 0e 02 02 02
 991 | @107bc
 992 | 40 11 40 11
 993 | @107c0
 994 | 0e 02 02 02
 995 | @107c4
 996 | 40 11 40 11
 997 | @107c8
 998 | 0e 02 02 02
 999 | @107cc
1000 | 40 11 40 11
1001 | @107d0
1002 | 0e 02 02 02
1003 | @107d4
1004 | 40 11 40 11
1005 | @107d8
1006 | 0e 02 02 02
1007 | @107dc
1008 | 40 11 40 11
1009 | @107e0
1010 | 0e 02 02 02
1011 | @107e4
1012 | 40 11 40 11
1013 | @107e8
1014 | 0e 02 02 02
1015 | @107ec
1016 | 40 11 40 11
1017 | @107f0
1018 | 0e 02 02 02
1019 | @107f4
1020 | 40 11 40 11
1021 | @107f8
1022 | ff 00 00 00
1023 | @107fc
1024 | 40 11 40 11
1025 | 


--------------------------------------------------------------------------------
/Lab10/PATTERN.sv:
--------------------------------------------------------------------------------
  1 | `include "../00_TESTBED/pseudo_DRAM.sv"
  2 | `include "Usertype_FD.sv"
  3 | 
  4 | program automatic PATTERN(input clk, INF.PATTERN inf);
  5 | import usertype::*;
  6 | 
  7 | // Read from DRAM
  8 | logic [7:0] dram ['h10000 : 'h10000 + 256 * 8 - 1];
  9 | res_info restaurants [0:255];
 10 | D_man_Info deliver_men [0:255];
 11 | initial begin
 12 | 	$readmemh("../00_TESTBED/DRAM/dram.dat", dram);
 13 | 	for (int i = 0; i < 256; ++i) begin
 14 | 		restaurants[i] = {dram['h10000 + i * 8 + 0], dram['h10000 + i * 8 + 1], dram['h10000 + i * 8 + 2], dram['h10000 + i * 8 + 3]};
 15 | 		deliver_men[i] = {dram['h10000 + i * 8 + 4], dram['h10000 + i * 8 + 5], dram['h10000 + i * 8 + 6], dram['h10000 + i * 8 + 7]};
 16 | 	end
 17 | end
 18 | 
 19 | // Main
 20 | typedef struct {
 21 |     Action				d_act;
 22 | 	int same;
 23 | 	Restaurant_id 		d_res_id;
 24 | 	Food_id             d_food_ID;
 25 | 	servings_of_food    d_ser_food;
 26 | 	Delivery_man_id		d_id;
 27 | 	Customer_status     d_ctm_status;
 28 | } input_info;
 29 | typedef struct {
 30 | 	logic complete;
 31 | 	Error_Msg err_msg;
 32 | 	logic [63:0] out_info;
 33 | } output_info;
 34 | 
 35 | `define act_num 400
 36 | 
 37 | input_info inputs [0:`act_num];
 38 | output_info outputs [0:`act_num];
 39 | 
 40 | int latency, total_latency;
 41 | 
 42 | initial begin
 43 | 	gen_input_task;
 44 | 	calc_output_task;
 45 | 
 46 | 	total_latency = 0;
 47 | 
 48 | 	reset_task;
 49 | 	@(negedge clk);
 50 | 	for (int act_cnt = 0; act_cnt < `act_num; ++act_cnt) begin
 51 | 
 52 | 		give_input_task(act_cnt);
 53 | 		check_output_task(act_cnt);
 54 | 
 55 | 		//$display("%3d %p lat=%0d", act_cnt, inputs[act_cnt].d_act, latency); //
 56 | 
 57 | 		total_latency = total_latency + latency;
 58 | 
 59 | 		if (act_cnt != `act_num - 1) begin
 60 | 			int gap = $urandom_range(2, 10);
 61 | 			gap = 2; //
 62 | 			repeat(gap) @(negedge clk);
 63 | 		end
 64 | 		else @(negedge clk);
 65 | 	end
 66 | 	//$display("tot_lat=%0d", total_latency); //
 67 | 	//$display("Total coverage %f\%",$get_coverage()); //
 68 | 	$finish;
 69 | end
 70 | 
 71 | // Task
 72 | task reset_task;
 73 | 	inf.act_valid = 1'b0; inf.res_valid = 1'b0; inf.food_valid = 1'b0; inf.id_valid = 1'b0; inf.cus_valid = 1'b0; inf.D = 'bx;
 74 | 
 75 | 	inf.rst_n = 1'b1;
 76 | 	#1 inf.rst_n = 1'b0;
 77 | 	#14 inf.rst_n = 1'b1;
 78 | endtask
 79 | 
 80 | task gen_input_task;
 81 | 	int act_cnt = 0;
 82 | 
 83 | 	// restaurants 0 - 254
 84 | 	// (14, 0, 0, 0)
 85 | 	// restaurants 255
 86 | 	// (255, 0, 0, 0)
 87 | 
 88 | 	int id1 = 0, id2 = 60;
 89 | 	// delivery men 0 - 59
 90 | 	// (false, false)
 91 | 	// delivery men 60 - 256
 92 | 	// (true, true)
 93 | 
 94 | 	input_info order_Res_busy, order_success;
 95 | 	input_info take_No_Food, take_D_man_busy;
 96 | 	input_info deliver_No_customers, deliver_success;
 97 | 	input_info cancel_Wrong_cancel, cancel_Wrong_res_ID, cancel_Wrong_food_ID;
 98 | 
 99 | // Order
100 | 	order_Res_busy.d_act = Order; order_Res_busy.same = 0;
101 | 	order_Res_busy.d_res_id = 0; order_Res_busy.d_food_ID = FOOD1; order_Res_busy.d_ser_food = 15;
102 | 
103 | 	order_success.d_act = Order; order_success.same = 0;
104 | 	order_success.d_res_id = 255; order_success.d_food_ID = FOOD1; order_success.d_ser_food = 1;
105 | 
106 | // Take
107 | 	take_D_man_busy.d_act = Take; take_D_man_busy.same = 0;
108 | 	take_D_man_busy.d_id = id2;
109 | 	take_D_man_busy.d_res_id = id2; take_D_man_busy.d_food_ID = FOOD1; take_D_man_busy.d_ser_food = 1;
110 | 
111 | 	take_No_Food.d_act = Take; take_No_Food.same = 0;
112 | 	take_No_Food.d_id = id1;
113 | 	take_No_Food.d_res_id = id1; take_No_Food.d_food_ID = FOOD1; take_No_Food.d_ser_food = 15;
114 | 
115 | // Deliver
116 | 	deliver_No_customers.d_act = Deliver;
117 | 	deliver_No_customers.d_id = id1;
118 | 
119 | 	deliver_success.d_act = Deliver;
120 | 	deliver_success.d_id = id2;
121 | 
122 | // Cancel
123 | 	cancel_Wrong_cancel.d_act = Cancel;
124 | 	cancel_Wrong_cancel.d_id = id1;
125 | 	cancel_Wrong_cancel.d_res_id = 0; cancel_Wrong_cancel.d_food_ID = FOOD1; cancel_Wrong_cancel.d_ser_food = 0;
126 | 
127 | 	cancel_Wrong_res_ID.d_act = Cancel;
128 | 	cancel_Wrong_res_ID.d_id = id2;
129 | 	cancel_Wrong_res_ID.d_res_id = 1; cancel_Wrong_res_ID.d_food_ID = FOOD1; cancel_Wrong_res_ID.d_ser_food = 0;
130 | 
131 | 	cancel_Wrong_food_ID.d_act = Cancel;
132 | 	cancel_Wrong_food_ID.d_id = id2;
133 | 	cancel_Wrong_food_ID.d_res_id = 0; cancel_Wrong_food_ID.d_food_ID = FOOD3; cancel_Wrong_food_ID.d_ser_food = 0;
134 | 
135 | // errs (200 + 75)
136 | 	// 20 (Deliver <-> Take)
137 | 	for (int i = 0; i < 10; ++i) begin
138 | 		inputs[act_cnt] = deliver_No_customers;
139 | 		inputs[act_cnt].d_id = id1; ++id1;
140 | 		++act_cnt;
141 | 		inputs[act_cnt] = take_No_Food;
142 | 		inputs[act_cnt].d_id = id1; inputs[act_cnt].d_res_id = id1; ++id1;
143 | 		++act_cnt;
144 | 	end
145 | 	// 20 (Deliver <-> Order)
146 | 	for (int i = 0; i < 10; ++i) begin
147 | 		inputs[act_cnt] = deliver_No_customers;
148 | 		inputs[act_cnt].d_id = id1; ++id1;
149 | 		++act_cnt;
150 | 		inputs[act_cnt] = order_Res_busy;
151 | 		++act_cnt;
152 | 	end
153 | 	// 19 (Deliver <-> Cancel)
154 | 	for (int i = 0; i < 10; ++i) begin
155 | 		inputs[act_cnt] = deliver_success; // **
156 | 		inputs[act_cnt].d_id = id2; ++id2;
157 | 		++act_cnt;
158 | 		if (i != 9) begin
159 | 			inputs[act_cnt] = cancel_Wrong_cancel;
160 | 			inputs[act_cnt].d_id = id1; ++id1;
161 | 			++act_cnt;
162 | 		end
163 | 	end
164 | 	// 20 (Cancel <-> Take)
165 | 	for (int i = 0; i < 10; ++i) begin
166 | 		inputs[act_cnt] = cancel_Wrong_cancel;
167 | 		inputs[act_cnt].d_id = id1; ++id1;
168 | 		++act_cnt;
169 | 		inputs[act_cnt] = take_No_Food;
170 | 		inputs[act_cnt].d_id = id1; inputs[act_cnt].d_res_id = id1; ++id1;
171 | 		++act_cnt;
172 | 	end
173 | 	// 19 (Cancel <-> Order)
174 | 	for (int i = 0; i < 10; ++i) begin
175 | 		inputs[act_cnt] = cancel_Wrong_res_ID;
176 | 		inputs[act_cnt].d_id = id2; ++id2;
177 | 		++act_cnt;
178 | 		if (i != 9) begin
179 | 			inputs[act_cnt] = order_success; // **
180 | 			++act_cnt;
181 | 		end
182 | 	end
183 | 	// 20 (Order <-> Take)
184 | 	for (int i = 0; i < 10; ++i) begin
185 | 		inputs[act_cnt] = order_Res_busy;
186 | 		++act_cnt;
187 | 		inputs[act_cnt] = take_D_man_busy;
188 | 		inputs[act_cnt].d_id = id2; inputs[act_cnt].d_res_id = id2; ++id2;
189 | 		++act_cnt;
190 | 	end
191 | 	// 10 (Take <-> Take)
192 | 	for (int i = 0; i < 10; ++i) begin
193 | 		inputs[act_cnt] = take_D_man_busy; inputs[act_cnt].same = 1;
194 | 		inputs[act_cnt].d_id = id2 - 1; inputs[act_cnt].d_res_id = id2 - 1;
195 | 		++act_cnt;
196 | 	end
197 | 
198 | 	// 60
199 | 	for (int i = 0; i < 60; ++i) begin
200 | 		inputs[act_cnt] = take_D_man_busy; inputs[act_cnt].same = 1;
201 | 		inputs[act_cnt].d_id = id2 - 1; inputs[act_cnt].d_res_id = id2 - 1;
202 | 		++act_cnt;
203 | 	end
204 | 
205 | 	// 1 (Take -> Order)
206 | 	inputs[act_cnt] = order_success; // **
207 | 	++act_cnt;
208 | 	// 10 (Order <-> Order)
209 | 	for (int i = 0; i < 10; ++i) begin
210 | 		inputs[act_cnt] = order_success; inputs[act_cnt].same = 1; // **
211 | 		++act_cnt;
212 | 	end
213 | 
214 | 	// 34
215 | 	for (int i = 0; i < 34; ++i) begin
216 | 		inputs[act_cnt] = order_success; inputs[act_cnt].same = 1; // **
217 | 		++act_cnt;
218 | 	end
219 | 
220 | 	// 1 (Order -> Cancel)
221 | 	inputs[act_cnt] = cancel_Wrong_cancel;
222 | 	inputs[act_cnt].d_id = id1; ++id1;
223 | 	++act_cnt;
224 | 	// 10 (Cancel <-> Cancel)
225 | 	for (int i = 0; i < 10; ++i) begin
226 | 		inputs[act_cnt] = cancel_Wrong_res_ID;
227 | 		inputs[act_cnt].d_id = id2; ++id2;
228 | 		++act_cnt;
229 | 	end
230 | 
231 | 	// 20
232 | 	for (int i = 0; i < 20; ++i) begin
233 | 		inputs[act_cnt] = cancel_Wrong_food_ID;
234 | 		inputs[act_cnt].d_id = id2; ++id2;
235 | 		++act_cnt;
236 | 	end
237 | 
238 | 	// 1 (Cancel -> Deliver)
239 | 	inputs[act_cnt] = deliver_success; // **
240 | 	inputs[act_cnt].d_id = id2; ++id2;
241 | 	++act_cnt;
242 | 	// 10 (Deliver <-> Deliver)
243 | 	for (int i = 0; i < 10; ++i) begin
244 | 		inputs[act_cnt] = deliver_success; // **
245 | 		inputs[act_cnt].d_id = id2; ++id2;
246 | 		++act_cnt;
247 | 	end
248 | 
249 | // complete (200 - 75)
250 | 	// 125
251 | 	for (int i = 131; i < 256; ++i) begin
252 | 		inputs[act_cnt] = deliver_success;
253 | 		inputs[act_cnt].d_id = id2; ++id2;
254 | 		++act_cnt;
255 | 	end
256 | 
257 | 	//$display("%d, %d, %d", id1, id2, act_cnt);
258 | endtask
259 | 
260 | task calc_output_task;
261 | 	for (int act_cnt = 0; act_cnt < `act_num; ++act_cnt) begin
262 | 		outputs[act_cnt].complete = 1'b0;
263 | 		outputs[act_cnt].err_msg = No_Err;
264 | 		outputs[act_cnt].out_info = 64'b0;
265 | 		if (inputs[act_cnt].d_act == Order) begin
266 | 			if (restaurants[inputs[act_cnt].d_res_id].limit_num_orders >=
267 | 					{1'b0, restaurants[inputs[act_cnt].d_res_id].ser_FOOD1} +
268 | 					restaurants[inputs[act_cnt].d_res_id].ser_FOOD2 +
269 | 					restaurants[inputs[act_cnt].d_res_id].ser_FOOD3 +
270 | 					inputs[act_cnt].d_ser_food) begin
271 | 				case (inputs[act_cnt].d_food_ID)
272 | 					FOOD1 : restaurants[inputs[act_cnt].d_res_id].ser_FOOD1 += inputs[act_cnt].d_ser_food;
273 | 					FOOD2 : restaurants[inputs[act_cnt].d_res_id].ser_FOOD2 += inputs[act_cnt].d_ser_food;
274 | 					FOOD3 : restaurants[inputs[act_cnt].d_res_id].ser_FOOD3 += inputs[act_cnt].d_ser_food;
275 | 				endcase
276 | 				outputs[act_cnt].complete = 1'b1;
277 | 				outputs[act_cnt].out_info = {32'b0, restaurants[inputs[act_cnt].d_res_id]};
278 | 			end
279 | 			else outputs[act_cnt].err_msg = Res_busy;
280 | 		end
281 | 		else if (inputs[act_cnt].d_act == Take) begin
282 | 			if (deliver_men[inputs[act_cnt].d_id].ctm_info2.ctm_status != None) outputs[act_cnt].err_msg = D_man_busy;
283 | 			else begin
284 | 				case (inputs[act_cnt].d_food_ID)
285 | 					FOOD1 : begin
286 | 						if (restaurants[inputs[act_cnt].d_res_id].ser_FOOD1 >= inputs[act_cnt].d_ser_food)
287 | 							restaurants[inputs[act_cnt].d_res_id].ser_FOOD1 -= inputs[act_cnt].d_ser_food;
288 | 						else outputs[act_cnt].err_msg = No_Food;
289 | 					end
290 | 					FOOD2 : begin
291 | 						if (restaurants[inputs[act_cnt].d_res_id].ser_FOOD2 >= inputs[act_cnt].d_ser_food)
292 | 							restaurants[inputs[act_cnt].d_res_id].ser_FOOD2 -= inputs[act_cnt].d_ser_food;
293 | 						else outputs[act_cnt].err_msg = No_Food;
294 | 					end
295 | 					FOOD3 : begin
296 | 						if (restaurants[inputs[act_cnt].d_res_id].ser_FOOD3 >= inputs[act_cnt].d_ser_food)
297 | 							restaurants[inputs[act_cnt].d_res_id].ser_FOOD3 -= inputs[act_cnt].d_ser_food;
298 | 						else outputs[act_cnt].err_msg = No_Food;
299 | 					end
300 | 				endcase
301 | 				if (outputs[act_cnt].err_msg == No_Err) begin
302 | 					if (deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status == None || (deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status == Normal && inputs[act_cnt].d_ctm_status == VIP)) begin
303 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2 = deliver_men[inputs[act_cnt].d_id].ctm_info1;
304 | 						deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status = inputs[act_cnt].d_ctm_status;
305 | 						deliver_men[inputs[act_cnt].d_id].ctm_info1.res_ID = inputs[act_cnt].d_res_id;
306 | 						deliver_men[inputs[act_cnt].d_id].ctm_info1.food_ID = inputs[act_cnt].d_food_ID;
307 | 						deliver_men[inputs[act_cnt].d_id].ctm_info1.ser_food = inputs[act_cnt].d_ser_food;
308 | 					end
309 | 					else begin
310 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2.ctm_status = inputs[act_cnt].d_ctm_status;
311 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2.res_ID = inputs[act_cnt].d_res_id;
312 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2.food_ID = inputs[act_cnt].d_food_ID;
313 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2.ser_food = inputs[act_cnt].d_ser_food;
314 | 					end
315 | 					outputs[act_cnt].complete = 1'b1;
316 | 					outputs[act_cnt].out_info = {deliver_men[inputs[act_cnt].d_id], restaurants[inputs[act_cnt].d_res_id]};
317 | 				end
318 | 			end
319 | 		end
320 | 		else if (inputs[act_cnt].d_act == Deliver) begin
321 | 			if (deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status == None) outputs[act_cnt].err_msg = No_customers;
322 | 			else begin
323 | 				deliver_men[inputs[act_cnt].d_id].ctm_info1 = deliver_men[inputs[act_cnt].d_id].ctm_info2;
324 | 				deliver_men[inputs[act_cnt].d_id].ctm_info2 = 16'b0;
325 | 				outputs[act_cnt].complete = 1'b1;
326 | 				outputs[act_cnt].out_info = {deliver_men[inputs[act_cnt].d_id], 32'b0};
327 | 			end
328 | 		end
329 | 		else if (inputs[act_cnt].d_act == Cancel) begin
330 | 			if (deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status == None) outputs[act_cnt].err_msg = Wrong_cancel;
331 | 			else if (deliver_men[inputs[act_cnt].d_id].ctm_info1.res_ID != inputs[act_cnt].d_res_id &&
332 | 					(deliver_men[inputs[act_cnt].d_id].ctm_info2.res_ID != inputs[act_cnt].d_res_id))
333 | 				outputs[act_cnt].err_msg = Wrong_res_ID;
334 | 			else begin
335 | 				if (deliver_men[inputs[act_cnt].d_id].ctm_info1.res_ID == inputs[act_cnt].d_res_id &&
336 | 						deliver_men[inputs[act_cnt].d_id].ctm_info1.food_ID == inputs[act_cnt].d_food_ID) begin
337 | 					deliver_men[inputs[act_cnt].d_id].ctm_info1 = 16'b0;
338 | 					outputs[act_cnt].complete = 1'b1;
339 | 				end
340 | 				if (deliver_men[inputs[act_cnt].d_id].ctm_info2.res_ID == inputs[act_cnt].d_res_id &&
341 | 						deliver_men[inputs[act_cnt].d_id].ctm_info2.food_ID == inputs[act_cnt].d_food_ID) begin
342 | 					deliver_men[inputs[act_cnt].d_id].ctm_info2 = 16'b0;
343 | 					outputs[act_cnt].complete = 1'b1;
344 | 				end
345 | 				if (deliver_men[inputs[act_cnt].d_id].ctm_info1.ctm_status == None) begin
346 | 					deliver_men[inputs[act_cnt].d_id].ctm_info1 = deliver_men[inputs[act_cnt].d_id].ctm_info2;
347 | 					deliver_men[inputs[act_cnt].d_id].ctm_info2 = 16'b0;
348 | 				end
349 | 				if (outputs[act_cnt].complete == 1'b1) outputs[act_cnt].out_info = {deliver_men[inputs[act_cnt].d_id], 32'b0};
350 | 				else outputs[act_cnt].err_msg = Wrong_food_ID;
351 | 			end
352 | 		end
353 | 	end
354 | endtask
355 | 
356 | task give_input_task (input int act_cnt);
357 | 	int arr [4], size = 0;
358 | 
359 | 	arr[size++] = 0;
360 | 	if (inputs[act_cnt].d_act == Order) begin
361 | 		if (!inputs[act_cnt].same) arr[size++] = 1; // res
362 | 		arr[size++] = 2; // food
363 | 	end
364 | 	else if (inputs[act_cnt].d_act == Take) begin
365 | 		if (!inputs[act_cnt].same) arr[size++] = 3; // id
366 | 		arr[size++] = 4; // cus
367 | 	end
368 | 	else if (inputs[act_cnt].d_act == Deliver) begin
369 | 		arr[size++] = 3; // id
370 | 	end
371 | 	else if (inputs[act_cnt].d_act == Cancel) begin
372 | 		arr[size++] = 1; // res
373 | 		arr[size++] = 2; // food
374 | 		arr[size++] = 3; // id
375 | 	end
376 | 
377 | 	for (int i = 0; i < size; ++i) begin
378 | 		case (arr[i])
379 | 			0 : begin // act
380 | 				inf.act_valid = 1'b1;
381 | 				inf.D.d_act[0] = inputs[act_cnt].d_act;
382 | 			end
383 | 			1 : begin // res
384 | 				inf.res_valid = 1'b1;
385 | 				inf.D.d_res_id[0] = inputs[act_cnt].d_res_id;
386 | 			end
387 | 			2 : begin // food
388 | 				inf.food_valid = 1'b1;
389 | 				inf.D.d_food_ID_ser[0].d_food_ID = inputs[act_cnt].d_food_ID;
390 | 				inf.D.d_food_ID_ser[0].d_ser_food = inputs[act_cnt].d_ser_food;
391 | 			end
392 | 			3 : begin // id
393 | 				inf.id_valid = 1'b1;
394 | 				inf.D.d_id[0] = inputs[act_cnt].d_id;
395 | 			end
396 | 			4 : begin // cus
397 | 				inf.cus_valid = 1'b1;
398 | 				inf.D.d_ctm_info[0].ctm_status = inputs[act_cnt].d_ctm_status;
399 | 				inf.D.d_ctm_info[0].res_ID = inputs[act_cnt].d_res_id;
400 | 				inf.D.d_ctm_info[0].food_ID = inputs[act_cnt].d_food_ID;
401 | 				inf.D.d_ctm_info[0].ser_food = inputs[act_cnt].d_ser_food;
402 | 			end
403 | 		endcase
404 | 		@(negedge clk);
405 | 		inf.act_valid = 1'b0; inf.res_valid = 1'b0; inf.food_valid = 1'b0; inf.id_valid = 1'b0; inf.cus_valid = 1'b0; inf.D = 'bx;
406 | 		if (i != size - 1) begin
407 | 			int gap = $urandom_range(1, 5);
408 | 			gap = 1; //
409 | 			repeat(gap) @(negedge clk);
410 | 		end
411 | 	end
412 | 	@(negedge clk);
413 | endtask
414 | 
415 | task check_output_task (input int act_cnt);
416 | 	latency = 1;
417 | 	while (inf.out_valid === 1'b0) begin
418 | 		latency = latency + 1;
419 | 		@(negedge clk);
420 | 	end
421 | 
422 | 	if (inf.complete !== outputs[act_cnt].complete || inf.err_msg !== outputs[act_cnt].err_msg || inf.out_info !== outputs[act_cnt].out_info) begin
423 | 		$display("Wrong Answer");
424 | 		$finish;
425 | 	end
426 | endtask
427 | 
428 | endprogram
429 | 


--------------------------------------------------------------------------------
/Lab08/SP.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | `ifdef RTL
  3 | `include "GATED_OR.v"
  4 | `else
  5 | `include "Netlist/GATED_OR_SYN.v"
  6 | `endif
  7 | // synopsys translate_on
  8 | 
  9 | module SP(
 10 | 	// Input signals
 11 | 	clk,
 12 | 	rst_n,
 13 | 	cg_en,
 14 | 	in_valid,
 15 | 	in_data,
 16 | 	in_mode,
 17 | 	// Output signals
 18 | 	out_valid,
 19 | 	out_data
 20 | );
 21 | 
 22 | // INPUT AND OUTPUT DECLARATION  
 23 | input		clk;
 24 | input		rst_n;
 25 | input		in_valid;
 26 | input		cg_en;
 27 | input [8:0] in_data;
 28 | input [2:0] in_mode;
 29 | 
 30 | output reg				out_valid;
 31 | output reg signed [9:0]	out_data;
 32 | /* My Design */
 33 | integer i;
 34 | genvar gv_i;
 35 | 
 36 | reg [2:0] mode;
 37 | reg signed [8:0] data [0:8];
 38 | reg signed [8:0] mx, mn, md, hd;
 39 | reg signed [8:0] maximum, median, minimum;
 40 | 
 41 | reg signed [8:0] element_tbg2b;
 42 | wire signed [8:0] g2bed;
 43 | wire [7:0] g2b_temp;
 44 | generate
 45 | 	assign g2b_temp[7] = element_tbg2b[7];
 46 | 	for (gv_i = 6; gv_i >= 0; gv_i = gv_i - 1) begin
 47 | 		assign g2b_temp[gv_i] = element_tbg2b[gv_i] ^ g2b_temp[gv_i + 1];
 48 | 	end
 49 | endgenerate
 50 | assign g2bed = (element_tbg2b[8] ? -g2b_temp : g2b_temp);
 51 | 
 52 | reg signed [8:0] element_tbmnx;
 53 | wire signed [8:0] mned = (element_tbmnx < mn ? element_tbmnx : mn);
 54 | wire signed [8:0] mxed = (element_tbmnx > mx ? element_tbmnx : mx);
 55 | 
 56 | reg signed [8:0] element_tbmhd [0:1];
 57 | wire signed [9:0] mded_temp = element_tbmhd[0] + element_tbmhd[1];
 58 | wire signed [9:0] hded_temp = element_tbmhd[0] - element_tbmhd[1];
 59 | //wire signed [8:0] mded = mded_temp / 2;
 60 | wire signed [8:0] mded = mded_temp[9:1] + (mded_temp[9] & mded_temp[0]);
 61 | wire signed [8:0] hded = hded_temp[9:1];
 62 | 
 63 | reg signed [8:0] element_tba [0:8];
 64 | wire signed [8:0] adjusted [0:8];
 65 | generate
 66 | 	for (gv_i = 0; gv_i < 9; gv_i = gv_i + 1) begin
 67 | 		wire adjusted_temp0;
 68 | 		//wire signed [8:0] adjusted_temp1;
 69 | 		wire signed [8:0] adjusted_temp2;
 70 | 		assign adjusted_temp0 = (element_tba[gv_i] > md);
 71 | 		AddSub#(.width(9)) u_AddSub(element_tba[gv_i], hd, adjusted_temp0, adjusted_temp2);
 72 | 		//assign adjusted_temp2 = (adjusted_temp0 ? element_tba[gv_i] - hd : element_tba[gv_i] + hd);
 73 | 		//assign adjusted_temp1 = (adjusted_temp0 ? -hd : hd);
 74 | 		//assign adjusted_temp2 = element_tba[gv_i] + adjusted_temp1;
 75 | 		assign adjusted[gv_i] = (element_tba[gv_i] == md ? element_tba[gv_i] : adjusted_temp2);
 76 | 	end
 77 | endgenerate
 78 | 
 79 | reg signed [8:0] element_tbSMA3 [0:8];
 80 | wire signed [8:0] SMA3ed [0:8];
 81 | generate
 82 | 	for (gv_i = 0; gv_i < 9; gv_i = gv_i + 1) begin
 83 | 		wire signed [10:0] SMA3ed_temp0;
 84 | 		//wire [9:0] SMA3ed_temp1;
 85 | 		//wire [18:0] SMA3ed_temp2;
 86 | 		//wire [7:0] SMA3ed_temp3;
 87 | 		assign SMA3ed_temp0 = element_tbSMA3[(gv_i - 1 + 9) % 9] + element_tbSMA3[gv_i] + element_tbSMA3[(gv_i + 1) % 9];
 88 | 		//assign SMA3ed_temp1 = (SMA3ed_temp0[10] ? -SMA3ed_temp0 : SMA3ed_temp0);
 89 | 		//assign SMA3ed_temp2 = SMA3ed_temp1 * 10'd683;
 90 | 		//assign SMA3ed_temp3 = SMA3ed_temp2[18:11];
 91 | 		//assign SMA3ed[gv_i] = (SMA3ed_temp0[10] ? -SMA3ed_temp3 : SMA3ed_temp3);
 92 | 		assign SMA3ed[gv_i] = SMA3ed_temp0 / 3;
 93 | 	end
 94 | endgenerate
 95 | 
 96 | reg signed [8:0] element_tbMMM [0:8];
 97 | wire signed [8:0] maximumed, medianed, minimumed;
 98 | 
 99 | wire signed [8:0] MMMed_temp0 [0:8];
100 | Sort3#(.width(9)) u_Sort3_1(element_tbMMM[0], element_tbMMM[1], element_tbMMM[2], MMMed_temp0[0], MMMed_temp0[1], MMMed_temp0[2]);
101 | Sort3#(.width(9)) u_Sort3_2(element_tbMMM[3], element_tbMMM[4], element_tbMMM[5], MMMed_temp0[3], MMMed_temp0[4], MMMed_temp0[5]);
102 | Sort3#(.width(9)) u_Sort3_3(element_tbMMM[6], element_tbMMM[7], element_tbMMM[8], MMMed_temp0[6], MMMed_temp0[7], MMMed_temp0[8]);
103 | wire signed [8:0] MMMed_temp1 [0:8];
104 | Sort3#(.width(9)) u_Sort3_4(MMMed_temp0[0], MMMed_temp0[3], MMMed_temp0[6], MMMed_temp1[0], MMMed_temp1[1], MMMed_temp1[2]);
105 | Sort3#(.width(9)) u_Sort3_5(MMMed_temp0[1], MMMed_temp0[4], MMMed_temp0[7], MMMed_temp1[3], MMMed_temp1[4], MMMed_temp1[5]);
106 | Sort3#(.width(9)) u_Sort3_6(MMMed_temp0[2], MMMed_temp0[5], MMMed_temp0[8], MMMed_temp1[6], MMMed_temp1[7], MMMed_temp1[8]);
107 | wire signed [8:0] MMMed_temp2 [3:5];
108 | Sort3#(.width(9)) u_Sort3_7(MMMed_temp1[2], MMMed_temp1[4], MMMed_temp1[6], MMMed_temp2[3], MMMed_temp2[4], MMMed_temp2[5]);
109 | assign maximumed = MMMed_temp1[0];
110 | assign medianed = MMMed_temp2[4];
111 | assign minimumed = MMMed_temp1[8];
112 | 
113 | reg [1:0] state, nxt_state;
114 | localparam Idle		= 2'b00;
115 | localparam Read		= 2'b01;
116 | localparam Work		= 2'b10;
117 | localparam Output	= 2'b11;
118 | 
119 | reg [2:0] cnt;
120 | wire [2:0] cnt_add_1 = cnt + 3'd1;
121 | wire cnt_eq [0:7];
122 | assign cnt_eq[0] = (cnt == 3'd0);
123 | assign cnt_eq[1] = (cnt == 3'd1);
124 | assign cnt_eq[2] = (cnt == 3'd2);
125 | assign cnt_eq[3] = (cnt == 3'd3);
126 | assign cnt_eq[4] = (cnt == 3'd4);
127 | assign cnt_eq[5] = (cnt == 3'd5);
128 | assign cnt_eq[6] = (cnt == 3'd6);
129 | assign cnt_eq[7] = (cnt == 3'd7);
130 | 
131 | always @(*) begin
132 | 	nxt_state <= state;
133 | 	case (state)
134 | 		Idle :
135 | 			if (in_valid) nxt_state <= Read;
136 | 		Read :
137 | 			if (cnt_eq[7]) nxt_state <= Work;
138 | 		Work : nxt_state <= Output;
139 | 		Output :
140 | 			if (cnt_eq[2]) nxt_state <= Idle;
141 | 	endcase
142 | end
143 | 
144 | always @(posedge clk or negedge rst_n) begin
145 | 	if (!rst_n) state <= Idle;
146 | 	else state <= nxt_state;
147 | end
148 | 
149 | reg sleep_ctrl_g2b;
150 | always @(*) begin
151 | 	sleep_ctrl_g2b <= 1'b1;
152 | 	case (state)
153 | 		Idle : begin
154 | 			if (in_valid) begin
155 | 				if (in_mode[0]) begin
156 | 					sleep_ctrl_g2b <= 1'b0;
157 | 				end
158 | 			end
159 | 		end
160 | 		Read : begin
161 | 			if (mode[0]) begin
162 | 				sleep_ctrl_g2b <= 1'b0;
163 | 			end
164 | 		end
165 | 	endcase
166 | end
167 | reg signed [8:0] _element_tbg2b;
168 | always @(*) begin
169 | 	_element_tbg2b <= 9'sbx;
170 | 	case (state)
171 | 		Idle : begin
172 | 			if (in_valid) begin
173 | 				if (in_mode[0]) begin
174 | 					_element_tbg2b <= in_data;
175 | 				end
176 | 			end
177 | 		end
178 | 		Read : begin
179 | 			if (mode[0]) begin
180 | 				_element_tbg2b <= in_data;
181 | 			end
182 | 		end
183 | 	endcase
184 | end
185 | always @(*) begin
186 | 	element_tbg2b <= (sleep_ctrl_g2b ? 9'sb0 : _element_tbg2b);
187 | end
188 | 
189 | reg sleep_ctrl_mnx;
190 | always @(*) begin
191 | 	sleep_ctrl_mnx <= 1'b1;
192 | 	case (state)
193 | 		Read : begin
194 | 			if (mode[1]) begin
195 | 				sleep_ctrl_mnx <= 1'b0;
196 | 			end
197 | 		end
198 | 	endcase
199 | end
200 | reg signed [8:0] _element_tbmnx;
201 | always @(*) begin
202 | 	_element_tbmnx <= 9'sbx;
203 | 	case (state)
204 | 		Read : begin
205 | 			if (mode[1]) begin
206 | 				if (mode[0]) begin
207 | 					_element_tbmnx <= g2bed;
208 | 				end
209 | 				else begin
210 | 					_element_tbmnx <= in_data;
211 | 				end
212 | 			end
213 | 		end
214 | 	endcase
215 | end
216 | always @(*) begin
217 | 	element_tbmnx <= (sleep_ctrl_mnx ? 9'sb0 : _element_tbmnx);
218 | end
219 | 
220 | reg sleep_ctrl_mhd;
221 | always @(*) begin
222 | 	sleep_ctrl_mhd <= 1'b1;
223 | 	case (state)
224 | 		Read : begin
225 | 			if (mode[1] && cnt_eq[7]) begin
226 | 				sleep_ctrl_mhd <= 1'b0;
227 | 			end
228 | 		end
229 | 	endcase
230 | end
231 | reg signed [8:0] _element_tbmhd [0:1];
232 | always @(*) begin
233 | 	_element_tbmhd[0] <= 9'sbx;
234 | 	_element_tbmhd[1] <= 9'sbx;
235 | 	case (state)
236 | 		Read : begin
237 | 			if (mode[1] && cnt_eq[7]) begin
238 | 				_element_tbmhd[0] <= mxed;
239 | 				_element_tbmhd[1] <= mned;
240 | 			end
241 | 		end
242 | 	endcase
243 | end
244 | always @(*) begin
245 | 	element_tbmhd[0] <= (sleep_ctrl_mhd ? 9'sb0 :  _element_tbmhd[0]);
246 | 	element_tbmhd[1] <= (sleep_ctrl_mhd ? 9'sb0 :  _element_tbmhd[1]);
247 | end
248 | 
249 | reg sleep_ctrl_adjust;
250 | wire gclk_adjust;
251 | GATED_OR GATED_adjust(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_adjust & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_adjust));
252 | always @(*) begin
253 | 	sleep_ctrl_adjust <= 1'b1;
254 | 	case (state)
255 | 		Read : begin
256 | 			if (mode[1] && cnt_eq[7]) begin
257 | 				sleep_ctrl_adjust <= 1'b0;
258 | 			end
259 | 		end
260 | 	endcase
261 | end
262 | always @(posedge gclk_adjust) begin
263 | 	for (i = 0; i < 9; i = i + 1) element_tba[i] <= 9'sbx;
264 | 	case (state)
265 | 		Read : begin
266 | 			if (mode[1] && cnt_eq[7]) begin
267 | 				if (mode[0]) begin
268 | 					for (i = 0; i <= 7; i = i + 1) element_tba[i] <= data[i];
269 | 					element_tba[8] <= g2bed;
270 | 				end
271 | 				else begin
272 | 					for (i = 0; i <= 7; i = i + 1) element_tba[i] <= data[i];
273 | 					element_tba[8] <= in_data;
274 | 				end
275 | 			end
276 | 		end
277 | 	endcase
278 | end
279 | 
280 | reg sleep_ctrl_SMA3;
281 | always @(*) begin
282 | 	sleep_ctrl_SMA3 <= 1'b1;
283 | 	case (state)
284 | 		Work : begin
285 | 			if (mode[2]) begin
286 | 				sleep_ctrl_SMA3 <= 1'b0;
287 | 			end
288 | 		end
289 | 	endcase
290 | end
291 | reg signed [8:0] _element_tbSMA3 [0:8];
292 | always @(*) begin
293 | 	for (i = 0; i < 9; i = i + 1) _element_tbSMA3[i] <= 9'sbx;
294 | 	case (state)
295 | 		Work : begin
296 | 			if (mode[2]) begin
297 | 				for (i = 0; i < 9; i = i + 1) begin
298 | 					if (mode[1]) _element_tbSMA3[i] <= adjusted[i];
299 | 					else _element_tbSMA3[i] <= data[i];
300 | 				end
301 | 			end
302 | 		end
303 | 	endcase
304 | end
305 | always @(*) begin
306 | 	for (i = 0; i < 9; i = i + 1) element_tbSMA3[i] <= (sleep_ctrl_SMA3 ? 9'sb0 : _element_tbSMA3[i]);
307 | end
308 | 
309 | reg sleep_ctrl_MMM;
310 | wire gclk_MMM;
311 | GATED_OR GATED_MMM(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_MMM & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_MMM));
312 | always @(*) begin
313 | 	sleep_ctrl_MMM <= 1'b1;
314 | 	case (state)
315 | 		Work : begin
316 | 			sleep_ctrl_MMM <= 1'b0;
317 | 		end
318 | 	endcase
319 | end
320 | always @(posedge gclk_MMM) begin
321 | 	for (i = 0; i < 9; i = i + 1) element_tbMMM[i] <= 9'sbx;
322 | 	case (state)
323 | 		Work : begin
324 | 			for (i = 0; i < 9; i = i + 1) begin
325 | 				if (mode[2]) element_tbMMM[i] <= SMA3ed[i];
326 | 				else if (mode[1]) element_tbMMM[i] <= adjusted[i];
327 | 				else element_tbMMM[i] <= data[i];
328 | 			end
329 | 		end
330 | 	endcase
331 | end
332 | 
333 | always @(posedge clk) begin
334 | 	cnt <= 3'd0;
335 | 	case (state)
336 | 		Read : begin
337 | 			if (!cnt_eq[7]) cnt <= cnt_add_1;
338 | 		end
339 | 		Output : begin
340 | 			if (!cnt_eq[2]) cnt <= cnt_add_1;
341 | 		end
342 | 	endcase
343 | end
344 | 
345 | reg sleep_ctrl_dataassign0;
346 | wire gclk_dataassign0;
347 | GATED_OR GATED_dataassign0(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_dataassign0 & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_dataassign0));
348 | always @(*) begin
349 | 	sleep_ctrl_dataassign0 <= 1'b1;
350 | 	case (state)
351 | 		Idle : begin // For OR gate, the allow switching cycle is clock at high period.
352 | 			sleep_ctrl_dataassign0 <= 1'b0;
353 | 		end
354 | 	endcase
355 | end
356 | always @(posedge gclk_dataassign0) begin
357 | 	case (state)
358 | 		Idle : begin
359 | 			if (in_valid) begin
360 | 				mode <= in_mode;
361 | 				if (in_mode[0]) begin
362 | 					data[0] <= g2bed;
363 | 				end
364 | 				else begin
365 | 					data[0] <= in_data;
366 | 				end
367 | 			end
368 | 		end
369 | 	endcase
370 | end
371 | 
372 | generate
373 | 	for (gv_i = 1; gv_i < 9; gv_i = gv_i + 1) begin
374 | 		reg sleep_ctrl_dataassign;
375 | 		wire gclk_dataassign;
376 | 		GATED_OR GATED_dataassign(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_dataassign & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_dataassign));
377 | 		always @(*) begin
378 | 			sleep_ctrl_dataassign <= 1'b1;
379 | 			case (state)
380 | 				Read : begin
381 | 					if (cnt_eq[gv_i - 1]) begin
382 | 						sleep_ctrl_dataassign <= 1'b0;
383 | 					end
384 | 				end
385 | 			endcase
386 | 		end
387 | 		always @(posedge gclk_dataassign) begin
388 | 			case (state)
389 | 				Read : begin
390 | 					if (cnt_eq[gv_i - 1]) begin
391 | 						if (mode[0]) begin
392 | 							data[gv_i] <= g2bed;
393 | 						end
394 | 						else begin
395 | 							data[gv_i] <= in_data;
396 | 						end
397 | 					end
398 | 				end
399 | 			endcase
400 | 		end
401 | 	end
402 | endgenerate
403 | 
404 | reg sleep_ctrl_mnxassign;
405 | wire gclk_mnxassign;
406 | GATED_OR GATED_mnxassign(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_mnxassign & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_mnxassign));
407 | always @(*) begin
408 | 	sleep_ctrl_mnxassign <= 1'b1;
409 | 	case (state)
410 | 		Idle : begin // For OR gate, the allow switching cycle is clock at high period.
411 | 			sleep_ctrl_mnxassign <= 1'b0;
412 | 		end
413 | 		Read : begin
414 | 			if (mode[1] && !cnt_eq[7]) begin
415 | 				sleep_ctrl_mnxassign <= 1'b0;
416 | 			end
417 | 		end
418 | 	endcase
419 | end
420 | always @(posedge gclk_mnxassign) begin
421 | 	mn <= 9'sb0;
422 | 	mx <= 9'sb0;
423 | 	case (state)
424 | 		Idle : begin
425 | 			if (in_valid) begin
426 | 				if (in_mode[1]) begin
427 | 					if (in_mode[0]) begin
428 | 						mn <= g2bed;
429 | 						mx <= g2bed;
430 | 					end
431 | 					else begin
432 | 						mn <= in_data;
433 | 						mx <= in_data;
434 | 					end
435 | 				end
436 | 			end
437 | 		end
438 | 		Read : begin
439 | 			if (mode[1] && !cnt_eq[7]) begin
440 | 				if (mode[0]) begin
441 | 					mn <= mned;
442 | 					mx <= mxed;
443 | 				end
444 | 				else begin
445 | 					mn <= mned;
446 | 					mx <= mxed;
447 | 				end
448 | 			end
449 | 		end
450 | 	endcase
451 | end
452 | 
453 | reg sleep_ctrl_mhdassignassign;
454 | wire gclk_mhdassignassign;
455 | GATED_OR GATED_mhdassignassign(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_mhdassignassign & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_mhdassignassign));
456 | always @(*) begin
457 | 	sleep_ctrl_mhdassignassign <= 1'b1;
458 | 	case (state)
459 | 		Read : begin
460 | 			if (mode[1] && cnt_eq[7]) begin
461 | 				sleep_ctrl_mhdassignassign <= 1'b0;
462 | 			end
463 | 		end
464 | 	endcase
465 | end
466 | always @(posedge gclk_mhdassignassign) begin
467 | 	md <= 9'sbx;
468 | 	hd <= 9'sbx;
469 | 	case (state)
470 | 		Read : begin
471 | 			if (mode[1] && cnt_eq[7]) begin
472 | 				md <= mded;
473 | 				hd <= hded;
474 | 			end
475 | 		end
476 | 	endcase
477 | end
478 | 
479 | reg sleep_ctrl_MMMassign;
480 | wire gclk_MMMassign;
481 | GATED_OR GATED_MMMassign(.CLOCK(clk), .SLEEP_CTRL(sleep_ctrl_MMMassign & cg_en), .RST_N(rst_n), .CLOCK_GATED(gclk_MMMassign));
482 | always @(*) begin
483 | 	sleep_ctrl_MMMassign <= 1'b1;
484 | 	case (state)
485 | 		Output : begin
486 | 			if (cnt_eq[0]) begin
487 | 				sleep_ctrl_MMMassign <= 1'b0;
488 | 			end
489 | 		end
490 | 	endcase
491 | end
492 | always @(posedge gclk_MMMassign) begin
493 | 	case (state)
494 | 		Output : begin
495 | 			if (cnt_eq[0]) begin
496 | 				median <= medianed;
497 | 				minimum <= minimumed;
498 | 			end
499 | 		end
500 | 	endcase
501 | end
502 | 
503 | always @(*) begin
504 | 	out_valid <= 1'b0;
505 | 	out_data <= 10'sb0;
506 | 	case (state)
507 | 		Output : begin
508 | 			out_valid <= 1'b1;
509 | 			case (cnt)
510 | 				3'd0 : out_data <= maximumed;
511 | 				3'd1 : out_data <= median;
512 | 				3'd2 : out_data <= minimum;
513 | 			endcase
514 | 		end
515 | 	endcase
516 | end
517 | 
518 | endmodule
519 | 
520 | module AddSub#(parameter width = 1) (a, b, add_sub, s);
521 | input [width - 1:0] a;
522 | input [width - 1:0] b;
523 | input add_sub;
524 | output [width - 1:0] s;
525 | 
526 | wire [width - 1:0] c;
527 | Fall_adder fa0(a[0], b[0] ^ add_sub, add_sub, s[0], c[0]);
528 | genvar gv_i;
529 | generate
530 | 	for (gv_i = 1; gv_i < width; gv_i = gv_i + 1) begin
531 | 		Fall_adder fa(a[gv_i], b[gv_i] ^ add_sub, c[gv_i - 1], s[gv_i], c[gv_i]);
532 | 	end
533 | endgenerate
534 | endmodule
535 | 
536 | module Half_adder(a, b, s, c);
537 | input a;
538 | input b;
539 | output s;
540 | output c;
541 | 
542 | assign s = a ^ b;
543 | assign c = a & b;
544 | endmodule
545 | 
546 | module Fall_adder(a, b, cin, s, cout);
547 | input a;
548 | input b;
549 | input cin;
550 | output s;
551 | output cout;
552 | 
553 | wire s1, c1;
554 | Half_adder ha1(a, b, s1, c1);
555 | wire s2, c2;
556 | Half_adder ha2(s1, cin, s2, c2);
557 | assign s = s2;
558 | assign cout = c1 | c2;
559 | endmodule
560 | 
561 | module Sort3#(parameter width = 1) (a, b, c, x, y, z);
562 | input signed [width - 1:0] a, b, c;
563 | output signed [width - 1:0] x, y, z;
564 | 
565 | wire signed [width - 1:0] layer1 [0:2];
566 | wire layer1_cmp = (b < c);
567 | assign layer1[0] = a;
568 | assign layer1[1] = (layer1_cmp ? c : b);
569 | assign layer1[2] = (layer1_cmp ? b : c);
570 | 
571 | wire signed [width - 1:0] layer2 [0:2];
572 | wire layer2_cmp = (layer1[0] < layer1[1]);
573 | assign layer2[0] = (layer2_cmp ? layer1[1] : layer1[0]);
574 | assign layer2[1] = (layer2_cmp ? layer1[0] : layer1[1]);
575 | assign layer2[2] = layer1[2];
576 | 
577 | wire layer3_cmp = (layer2[1] < layer2[2]);
578 | assign x = layer2[0];
579 | assign y = (layer3_cmp ? layer2[2] : layer2[1]);
580 | assign z = (layer3_cmp ? layer2[1] : layer2[2]);
581 | 
582 | endmodule
583 | 
584 | 


--------------------------------------------------------------------------------
/Midterm/EDH.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | 
  3 | `include ...
  4 | 
  5 | // synopsys translate_on
  6 | 
  7 | module EDH#(parameter ID_WIDTH=4, DATA_WIDTH=128, ADDR_WIDTH=32) (
  8 | 	//Connection wires
  9 | 	input clk,
 10 | 	input rst_n,
 11 | 	input in_valid,
 12 | 	input [1:0] op,
 13 | 	input [3:0] pic_no,     
 14 | 	input [5:0] se_no,     
 15 | 	output reg busy,          
 16 | 	// axi write address channel 
 17 | 	output     [ID_WIDTH-1:0] awid_m_inf,
 18 | 	output reg [ADDR_WIDTH-1:0] awaddr_m_inf,
 19 | 	output     [2:0] awsize_m_inf,
 20 | 	output     [1:0] awburst_m_inf,
 21 | 	output reg [7:0] awlen_m_inf,
 22 | 	output reg awvalid_m_inf,
 23 | 	input awready_m_inf,
 24 | 	// axi write data channel 
 25 | 	output reg [DATA_WIDTH-1:0] wdata_m_inf,
 26 | 	output reg wlast_m_inf,
 27 | 	output reg wvalid_m_inf,
 28 | 	input wready_m_inf,
 29 | 	// axi write response channel
 30 | 	input [ID_WIDTH-1:0] bid_m_inf,
 31 | 	input [1:0] bresp_m_inf,
 32 | 	input bvalid_m_inf,
 33 | 	output reg bready_m_inf,
 34 | 	// -----------------------------
 35 | 	// axi read address channel 
 36 | 	output     [ID_WIDTH-1:0] arid_m_inf,
 37 | 	output reg [ADDR_WIDTH-1:0] araddr_m_inf,
 38 | 	output reg [7:0] arlen_m_inf,
 39 | 	output     [2:0] arsize_m_inf,
 40 | 	output     [1:0] arburst_m_inf,
 41 | 	output reg arvalid_m_inf,
 42 | 	input arready_m_inf,
 43 | 	// -----------------------------
 44 | 	// axi read data channel 
 45 | 	input [ID_WIDTH-1:0] rid_m_inf,
 46 | 	input [DATA_WIDTH-1:0] rdata_m_inf,
 47 | 	input [1:0] rresp_m_inf,
 48 | 	input rlast_m_inf,
 49 | 	input rvalid_m_inf,
 50 | 	output reg rready_m_inf
 51 | 	// -----------------------------
 52 | );
 53 | integer i, j, k;
 54 | genvar gv_i, gv_j, gv_k;
 55 | 
 56 | reg [1:0] op_reg;
 57 | reg [3:0] pic_no_reg;
 58 | reg [5:0] se_no_reg;
 59 | reg [7:0] se [0:3][0:3];
 60 | 
 61 | wire [127:0] sram_Q;
 62 | reg sram_WEN;
 63 | reg [7:0] sram_A;
 64 | reg [127:0] sram_D;
 65 | sram_256x128 u_sram_256x128(.Q(sram_Q), .CLK(clk), .CEN(1'b0), .WEN(sram_WEN), .A(sram_A), .D(sram_D), .OEN(1'b0));
 66 | 
 67 | reg [127:0] word;
 68 | reg [127:0] temp;
 69 | /*------------------------------*/
 70 | 
 71 | localparam ed_lat = 16 + 3;
 72 | reg ed_reset;
 73 | reg ed_stall;
 74 | reg [127:0] ed_input;
 75 | reg [127:0] ed_res;
 76 | 
 77 | reg [7:0] ed_data [0:3][0:63];
 78 | reg ed_data_flag [0:3];
 79 | 
 80 | wire [7:0] _ed_data [0:3][0:63];
 81 | wire _ed_data_flag [0:3];
 82 | generate
 83 | 	for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
 84 | 		for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
 85 | 			for (gv_k = 0; gv_k < 16; gv_k = gv_k + 1) begin
 86 | 				if (gv_j == 3) begin
 87 | 					if (gv_i == 3) begin
 88 | 						assign _ed_data[3][48 + gv_k] = ed_input[gv_k * 8 + 7-:8];
 89 | 					end
 90 | 					else begin
 91 | 						assign _ed_data[gv_i][48 + gv_k] = ed_data[gv_i + 1][gv_k];
 92 | 					end
 93 | 				end
 94 | 				else begin
 95 | 					assign _ed_data[gv_i][gv_j * 16 + gv_k] = ed_data[gv_i][gv_j * 16 + 16 + gv_k];
 96 | 				end
 97 | 			end
 98 | 		end
 99 | 		assign _ed_data_flag[gv_i] = ed_data_flag[(gv_i + 1) % 4];
100 | 	end
101 | endgenerate
102 | always @(posedge clk) begin
103 | 	if (!ed_stall) begin
104 | 		for (i = 0; i < 4; i = i + 1)
105 | 			for (j = 0; j < 64; j = j + 1) ed_data[i][j] <= _ed_data[i][j];
106 | 	end
107 | 	if (ed_reset) begin
108 | 		ed_data_flag[0] <= 1'b0; ed_data_flag[1] <= 1'b0; ed_data_flag[2] <= 1'b0; ed_data_flag[3] <= 1'b1;
109 | 	end
110 | 	else if (!ed_stall) begin
111 | 		for (i = 0; i < 4; i = i + 1) ed_data_flag[i] <= _ed_data_flag[i];
112 | 	end
113 | end
114 | 
115 | wire [127:0] _ed_res;
116 | generate
117 | 	wire [7:0] _ed_data0 [0:3][0:18];
118 | 	for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
119 | 		for (gv_j = 0; gv_j < 16; gv_j = gv_j + 1) begin
120 | 			assign _ed_data0[gv_i][gv_j] = ed_data[gv_i][gv_j];
121 | 		end
122 | 		for (gv_j = 16; gv_j < 19; gv_j = gv_j + 1) begin
123 | 			assign _ed_data0[gv_i][gv_j] = (ed_data_flag[0] ? 8'd0 : ed_data[gv_i][gv_j]);
124 | 		end
125 | 	end
126 | 	for (gv_k = 0; gv_k < 16; gv_k = gv_k + 1) begin
127 | 		wire signed [9:0] _data1 [0:3][0:3];
128 | 		for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
129 | 			for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
130 | 				DW01_addsub#(.width(10)) u_DW01_addsub(.A({2'b0, _ed_data0[gv_i][gv_k + gv_j]}), .B({2'b0, se[gv_i][gv_j]}), .CI(1'b0), .ADD_SUB(~op_reg[0]), .SUM(_data1[gv_i][gv_j]), .CO());
131 | 			end
132 | 		end
133 | 
134 | 		reg [7:0] data2 [0:3][0:3];
135 | 		wire [7:0] _data2 [0:3][0:3];
136 | 		for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
137 | 			for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
138 | 				assign _data2[gv_i][gv_j] = (_data1[gv_i][gv_j][9] ? 8'd0 : (_data1[gv_i][gv_j][8] ? 8'd255 : _data1[gv_i][gv_j]));
139 | 			end
140 | 		end
141 | 		always @(posedge clk) begin
142 | 			for (i = 0; i < 4; i = i + 1)
143 | 				for (j = 0; j < 4; j = j + 1) data2[i][j] <= _data2[i][j];
144 | 		end
145 | 		wire [127:0] data2_flatten;
146 | 		for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
147 | 			for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
148 | 				assign data2_flatten[(gv_i * 4 + gv_j) * 8 + 7-:8] = data2[gv_i][gv_j];
149 | 			end
150 | 		end
151 | 
152 | 		reg [31:0] data3_flatten;
153 | 		wire [31:0] _data3_flatten;
154 | 		for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
155 | 			DW_minmax#(.width(8), .num_inputs(4)) u_DW_minmax_1(.a(data2_flatten[gv_i * 32 + 31-:32]), .tc(1'b0), .min_max(op_reg[0]), .value(_data3_flatten[gv_i * 8 + 7-:8]), .index());
156 | 		end
157 | 		always @(posedge clk) begin
158 | 			data3_flatten <= _data3_flatten;
159 | 		end
160 | 
161 | 		DW_minmax#(.width(8), .num_inputs(4)) u_DW_minmax_2(.a(data3_flatten), .tc(1'b0), .min_max(op_reg[0]), .value(_ed_res[8 * gv_k + 7-:8]), .index());
162 | 	end
163 | endgenerate
164 | always @(posedge clk) begin
165 | 	ed_res <= _ed_res;
166 | end
167 | /*------------------------------*/
168 | 
169 | reg [11:0] h_data [0:255];
170 | 
171 | reg [127:0] _word_sr;
172 | always @(*) begin
173 | 	_word_sr <= word;
174 | 	_word_sr[63:0] <= word[127:64];
175 | end
176 | 
177 | reg [11:0] _h_data_cdf [0:255];
178 | always @(*) begin
179 | 	for (i = 0; i < 256; i = i + 1) begin
180 | 		_h_data_cdf[i] <= h_data[i] +
181 | 						(word[7:0] == i) +
182 | 						(word[15:8] == i) +
183 | 						(word[23:16] == i) +
184 | 						(word[31:24] == i) +
185 | 						(word[39:32] == i) +
186 | 						(word[47:40] == i) +
187 | 						(word[55:48] == i) +
188 | 						(word[63:56] == i);
189 | 	end
190 | end
191 | /*------------------------------*/
192 | 
193 | localparam h_map_lat = 8;
194 | reg [11:0] cdf_min;
195 | 
196 | wire [11:0] _h_data_0_add_1 = h_data[1] + h_data[0];
197 | wire [11:0] cdf_min_next = (cdf_min ? cdf_min : h_data[1]);
198 | 
199 | reg [11:0] divisor;
200 | wire [11:0] _cdf_max_sub_cdf_min = 13'd4096 - cdf_min;
201 | always @(posedge clk) begin
202 | 	divisor <= _cdf_max_sub_cdf_min;
203 | end
204 | reg [19:0] cdfi_sub_cdf_minx255;
205 | wire [11:0] _cdfi_sub_cdf_min = h_data[0] - cdf_min;
206 | wire [19:0] _cdfi_sub_cdf_minx255 = (_cdfi_sub_cdf_min << 8) - _cdfi_sub_cdf_min;
207 | always @(posedge clk) begin
208 | 	cdfi_sub_cdf_minx255 <= _cdfi_sub_cdf_minx255;
209 | end
210 | 
211 | wire [19:0] rq_cur [0:7];
212 | wire [19:0] _rq_nxt [0:7];
213 | wire [12:0] _rq_temp_0 [0:7];
214 | wire signed [13:0] _rq_temp_1 [0:7];
215 | reg [19:0] _rq_nxt_reg [0:7];
216 | generate
217 | 	assign rq_cur[0] = cdfi_sub_cdf_minx255;
218 | 	for (gv_i = 1; gv_i < 8; gv_i = gv_i + 1) begin
219 | 		assign rq_cur[gv_i] = _rq_nxt_reg[gv_i - 1];
220 | 	end
221 | 	for (gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin
222 | 		assign _rq_temp_0[gv_i] = rq_cur[gv_i][19:7];
223 | 		assign _rq_temp_1[gv_i] = _rq_temp_0[gv_i] - divisor;
224 | 		assign _rq_nxt[gv_i] = (_rq_temp_1[gv_i][13] ?
225 | 			{_rq_temp_0[gv_i][11:0], rq_cur[gv_i][6:0], 1'b0} :
226 | 			{_rq_temp_1[gv_i][11:0], rq_cur[gv_i][6:0], 1'b1});
227 | 	end
228 | 	for (gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin
229 | 		always @(posedge clk) begin
230 | 			_rq_nxt_reg[gv_i] <= _rq_nxt[gv_i];
231 | 		end
232 | 	end
233 | endgenerate
234 | wire [7:0] _pixel_map = _rq_nxt[7][7:0];
235 | /*------------------------------*/
236 | 
237 | localparam h_res_lat = 1;
238 | reg h_res_stall;
239 | reg [127:0] h_res;
240 | 
241 | wire [127:0] _h_res;
242 | generate
243 | 	for (gv_k = 0; gv_k < 16; gv_k = gv_k + 1) begin
244 | 		assign _h_res[gv_k * 8 + 7-:8] = h_data[word[gv_k * 8 + 7-:8]];
245 | 	end
246 | endgenerate
247 | always @(posedge clk) begin
248 | 	if (!h_res_stall) begin
249 | 		h_res <= _h_res;
250 | 	end
251 | end
252 | /*------------------------------*/
253 | 
254 | reg [4:0] state, nxt_state;
255 | localparam Idle		= 5'b00000;
256 | //...
257 | localparam ED_0		= 5'b00001;
258 | localparam ED_1		= 5'b00011;
259 | localparam ED_2		= 5'b00010;
260 | localparam ED_3		= 5'b00110;
261 | localparam ED_4		= 5'b00111;
262 | localparam ED_5		= 5'b00101;
263 | localparam ED_6		= 5'b00100;
264 | localparam ED_7		= 5'b01100;
265 | localparam ED_8		= 5'b01101;
266 | localparam ED_9		= 5'b01111;
267 | localparam ED_10	= 5'b01110;
268 | //...
269 | localparam H_0		= 5'b01010;
270 | localparam H_1		= 5'b01011;
271 | localparam H_2		= 5'b01001;
272 | localparam H_3		= 5'b01000;
273 | localparam H_4		= 5'b11000;
274 | localparam H_5		= 5'b11001;
275 | localparam H_6		= 5'b11011;
276 | localparam H_7		= 5'b11010;
277 | localparam H_8		= 5'b11110;
278 | localparam H_9		= 5'b11111;
279 | localparam H_10		= 5'b11101;
280 | /*
281 | localparam Idle		= 5'd0;
282 | //...
283 | localparam ED_0		= 5'd1;
284 | localparam ED_1		= 5'd2;
285 | localparam ED_2		= 5'd3;
286 | localparam ED_3		= 5'd4;
287 | localparam ED_4		= 5'd5;
288 | localparam ED_5		= 5'd6;
289 | localparam ED_6		= 5'd7;
290 | localparam ED_7		= 5'd8;
291 | localparam ED_8		= 5'd9;
292 | localparam ED_9		= 5'd10;
293 | localparam ED_10	= 5'd11;
294 | //...
295 | localparam H_0		= 5'd12;
296 | localparam H_1		= 5'd13;
297 | localparam H_2		= 5'd14;
298 | localparam H_3		= 5'd15;
299 | localparam H_4		= 5'd16;
300 | localparam H_5		= 5'd17;
301 | localparam H_6		= 5'd18;
302 | localparam H_7		= 5'd19;
303 | localparam H_8		= 5'd20;
304 | localparam H_9		= 5'd21;
305 | localparam H_10		= 5'd22;
306 | //...
307 | */
308 | 
309 | reg [7:0] cnt;
310 | 
311 | wire [7:0] cnt_add_1 = cnt + 8'd1;
312 | wire [7:0] cnt_add_2 = cnt + 8'd2;
313 | wire cnt_is_255 = (cnt == 8'd255);
314 | 
315 | wire ed_3_end = (cnt == ed_lat - 1);
316 | wire ed_5_end = cnt_is_255;
317 | wire ed_8_end = cnt_is_255;
318 | wire h_2_end = cnt_is_255;
319 | wire h_5_end = (cnt == h_map_lat - 1);
320 | wire h_6_end = h_5_end;
321 | wire h_7_end = (cnt == h_res_lat - 1);
322 | wire h_8_end = h_7_end;
323 | 
324 | always @(*) begin
325 | 	nxt_state <= state;
326 | 	case (state)
327 | 		Idle :
328 | 			if (in_valid) begin
329 | 				if (op[1]/*op == 2'd2*/) nxt_state <= H_0;
330 | 				else/* if (op == 2'd0 || op == 2'd1)*/ nxt_state <= ED_0;
331 | 			end
332 | 		ED_0 :
333 | 			if (arready_m_inf) nxt_state <= ED_1;
334 | 		ED_1 :
335 | 			if (rvalid_m_inf) nxt_state <= ED_2;
336 | 		ED_2 :
337 | 			if (arready_m_inf) nxt_state <= ED_3;
338 | 		ED_3 :
339 | 			if (ed_3_end) nxt_state <= ED_4;
340 | 		ED_4 :
341 | 			if (rlast_m_inf) nxt_state <= ED_5;
342 | 		ED_5 :
343 | 			if (ed_5_end) nxt_state <= ED_6;
344 | 		ED_6 :
345 | 			if (awready_m_inf) nxt_state <= ED_7;
346 | 		ED_7 : nxt_state <= ED_8;
347 | 		ED_8 :
348 | 			if (wready_m_inf) begin
349 | 				if (ed_8_end) nxt_state <= ED_10;
350 | 			end
351 | 			else nxt_state <= ED_9;
352 | 		ED_9 :
353 | 			if (wready_m_inf) begin
354 | 				if (ed_8_end) nxt_state <= ED_10;
355 | 				else nxt_state <= ED_8;
356 | 			end
357 | 		ED_10 :
358 | 			if (bvalid_m_inf) nxt_state <= Idle;
359 | 		H_0 :
360 | 			if (arready_m_inf) nxt_state <= H_1;
361 | 		H_1 :
362 | 			if (rvalid_m_inf) nxt_state <= H_2;
363 | 		H_2 :
364 | 			if (h_2_end) nxt_state <= H_3;
365 | 			else nxt_state <= H_1;
366 | 		H_3 : nxt_state <= H_4;
367 | 		H_4 :
368 | 			if (awready_m_inf) nxt_state <= H_5;
369 | 		H_5 :
370 | 			if (h_5_end) nxt_state <= H_6;
371 | 		H_6 :
372 | 			if (h_6_end) nxt_state <= H_7;
373 | 		H_7 :
374 | 			if (h_7_end) nxt_state <= H_8;
375 | 		H_8 :
376 | 			if (wready_m_inf) begin
377 | 				if (h_8_end) nxt_state <= H_10;
378 | 			end
379 | 			else nxt_state <= H_9;
380 | 		H_9 :
381 | 			if (wready_m_inf) begin
382 | 				if (h_8_end) nxt_state <= H_10;
383 | 				else nxt_state <= H_8;
384 | 			end
385 | 		H_10 :
386 | 			if (bvalid_m_inf) nxt_state <= Idle;
387 | 	endcase
388 | end
389 | 
390 | always @(posedge clk or negedge rst_n) begin
391 | 	if (!rst_n) state <= Idle;
392 | 	else state <= nxt_state;
393 | end
394 | 
395 | // SRAM
396 | always @(*) begin
397 | 	sram_WEN <= 1'b1;
398 | 	sram_A <= 8'bx;
399 | 	sram_D <= 128'bx;
400 | 	case (state)
401 | 		ED_4, ED_5 : begin
402 | 			sram_WEN <= 1'b0;
403 | 			sram_A <= cnt;
404 | 			sram_D <= ed_res;
405 | 		end
406 | 		ED_6 : begin
407 | 			//if (awready_m_inf) begin //
408 | 				sram_A <= 8'd0;
409 | 			//end
410 | 		end
411 | 		ED_7 : begin
412 | 			sram_A <= 8'd1;
413 | 		end
414 | 		ED_8, ED_9, H_8, H_9 : begin
415 | 			//if (wready_m_inf) begin //
416 | 				sram_A <= cnt_add_2;
417 | 			//end
418 | 		end
419 | 		H_2 : begin
420 | 			sram_WEN <= 1'b0;
421 | 			sram_A <= cnt;
422 | 			sram_D <= word;
423 | 		end
424 | 		H_6 : begin
425 | 			if (h_6_end) sram_A <= 8'd1;
426 | 			else sram_A <= 8'd0;
427 | 		end
428 | 		H_7 : begin
429 | 			sram_A <= cnt_add_2;
430 | 		end
431 | 	endcase
432 | end
433 | 
434 | // DRAM read
435 | assign arid_m_inf = 4'b0;
436 | assign arsize_m_inf = 3'b100;
437 | assign arburst_m_inf = 2'b01;
438 | always @(*) begin
439 | 	araddr_m_inf <= 32'bx;
440 | 	arlen_m_inf <= 8'bx;
441 | 	arvalid_m_inf <= 1'b0;
442 | 	rready_m_inf <= 1'b0;
443 | 	case (state)
444 | 		ED_0 : begin
445 | 			araddr_m_inf <= {16'h0003, 6'b0, se_no_reg, 4'b0};
446 | 			arlen_m_inf <= 8'd0;
447 | 			arvalid_m_inf <= 1'b1;
448 | 		end
449 | 		ED_1 : begin
450 | 			rready_m_inf <= 1'b1;
451 | 		end
452 | 		ED_2, H_0 : begin
453 | 			araddr_m_inf <= {16'h0004, pic_no_reg, 12'b0};
454 | 			arlen_m_inf <= 8'd255;
455 | 			arvalid_m_inf <= 1'b1;
456 | 		end
457 | 		ED_3, ED_4, H_1 : begin
458 | 			rready_m_inf <= 1'b1;
459 | 		end
460 | 	endcase
461 | end
462 | 
463 | // DRAM write
464 | assign awid_m_inf = 4'b0;
465 | assign awsize_m_inf = 3'b100;
466 | assign awburst_m_inf = 2'b01;
467 | always @(*) begin
468 | 	awaddr_m_inf <= 32'bx;
469 | 	awlen_m_inf <= 8'bx;
470 | 	awvalid_m_inf <= 1'b0;
471 | 	wdata_m_inf <= 128'bx;
472 | 	wlast_m_inf <= 1'bx;
473 | 	wvalid_m_inf <= 1'b0;
474 | 	bready_m_inf <= 1'b0;
475 | 	case (state)
476 | 		ED_6 : begin
477 | 			awaddr_m_inf <= {16'h0004, pic_no_reg, 12'b0};
478 | 			awlen_m_inf <= 8'd255;
479 | 			awvalid_m_inf <= 1'b1;
480 | 		end
481 | 		ED_8, ED_9 : begin
482 | 			wdata_m_inf <= word;
483 | 			wlast_m_inf <= ed_8_end;
484 | 			wvalid_m_inf <= 1'b1;
485 | 		end
486 | 		ED_10 : begin
487 | 			bready_m_inf <= 1'b1;
488 | 		end
489 | 		H_4 : begin
490 | 			awaddr_m_inf <= {16'h0004, pic_no_reg, 12'b0};
491 | 			awlen_m_inf <= 8'd255;
492 | 			awvalid_m_inf <= 1'b1;
493 | 		end
494 | 		H_8, H_9 : begin
495 | 			wdata_m_inf <= h_res;
496 | 			wlast_m_inf <= h_8_end;
497 | 			wvalid_m_inf <= 1'b1;
498 | 		end
499 | 		H_10 : begin
500 | 			bready_m_inf <= 1'b1;
501 | 		end
502 | 	endcase
503 | end
504 | 
505 | always @(*) begin
506 | 	ed_reset <= 1'b0;
507 | 	ed_stall <= 1'b1;
508 | 	ed_input <= 128'bx;
509 | 	h_res_stall <= 1'b1;
510 | 	case (state)
511 | 		ED_2 : begin
512 | 			//if (arready_m_inf) begin //
513 | 				ed_reset <= 1'b1;
514 | 			//end
515 | 		end
516 | 		ED_3, ED_4 : begin
517 | 			if (rvalid_m_inf) begin
518 | 				ed_stall <= 1'b0;
519 | 				ed_input <= rdata_m_inf;
520 | 			end
521 | 		end
522 | 		ED_5 : begin
523 | 			ed_stall <= 1'b0;
524 | 			ed_input <= 8'd0;
525 | 		end
526 | 		H_7 : begin
527 | 			h_res_stall <= 1'b0;
528 | 		end
529 | 		H_8, H_9 : begin
530 | 			if (wready_m_inf) begin
531 | 				h_res_stall <= 1'b0;
532 | 			end
533 | 		end
534 | 	endcase
535 | end
536 | 
537 | always @(posedge clk) begin
538 | 	case (state)
539 | 		Idle : begin
540 | 			if (in_valid) begin //
541 | 				op_reg <= op;
542 | 				pic_no_reg <= pic_no;
543 | 				se_no_reg <= se_no;
544 | 			end
545 | 		end
546 | 		ED_1 : begin
547 | 			if (rvalid_m_inf) begin //
548 | 				for (i = 0; i < 4; i = i + 1)
549 | 					for (j = 0; j < 4; j = j + 1) begin
550 | 						if (op_reg[0]/*op_reg == 2'd1*/) se[i][j] <= rdata_m_inf[(3 - i) * 32 + (3 - j) * 8 + 7-:8];
551 | 						else/* if (op_reg == 2'd0)*/ se[i][j] <= rdata_m_inf[i * 32 + j * 8 + 7-:8];
552 | 					end
553 | 				cnt <= 8'd0;
554 | 			end
555 | 		end
556 | 		ED_3: begin
557 | 			if (rvalid_m_inf) begin
558 | 				if (ed_3_end) cnt <= 8'd0;
559 | 				else cnt <= cnt_add_1;
560 | 			end
561 | 		end
562 | 		ED_4 : begin
563 | 			if (rvalid_m_inf) begin
564 | 				cnt <= cnt_add_1;
565 | 			end
566 | 		end
567 | 		ED_5 : begin
568 | 			cnt <= cnt_add_1;
569 | 		end
570 | 		ED_6 : begin
571 | 			//if (awready_m_inf) begin //
572 | 				cnt <= 8'd0;
573 | 			//end
574 | 		end
575 | 		ED_7 : begin
576 | 			word <= sram_Q;
577 | 		end
578 | 		ED_8 : begin
579 | 			if (wready_m_inf) begin
580 | 				word <= sram_Q;
581 | 				cnt <= cnt_add_1;
582 | 			end
583 | 			//else begin //
584 | 				temp <= sram_Q;
585 | 			//end
586 | 		end
587 | 		ED_9 : begin
588 | 			if (wready_m_inf) begin
589 | 				word <= temp;
590 | 				cnt <= cnt_add_1;
591 | 			end
592 | 		end
593 | 		H_0 : begin
594 | 			cnt <= 8'd0;
595 | 			word <= 128'hFF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF;
596 | 			for (i = 0; i < 256; i = i + 1) h_data[i] <= 12'd0;
597 | 		end
598 | 		H_1 : begin
599 | 			if (rvalid_m_inf) begin
600 | 				word <= rdata_m_inf;
601 | 			end
602 | 			else word <= 128'hFF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF;
603 | 			for (i = 0; i < 256; i = i + 1) h_data[i] <= _h_data_cdf[i];
604 | 		end
605 | 		H_2 : begin
606 | 			cnt <= cnt_add_1;
607 | 			word <= _word_sr;
608 | 			for (i = 0; i < 256; i = i + 1) h_data[i] <= _h_data_cdf[i];
609 | 		end
610 | 		H_3 : begin
611 | 			for (i = 0; i < 256; i = i + 1) h_data[i] <= _h_data_cdf[i];
612 | 		end
613 | 		H_4 : begin
614 | 			//if (awready_m_inf) begin //
615 | 				cnt <= 8'd0;
616 | 				cdf_min <= h_data[0];
617 | 			//end
618 | 		end
619 | 		H_5 : begin
620 | 			cnt <= cnt_add_1;
621 | 			cdf_min <= cdf_min_next;
622 | 			h_data[0] <= _h_data_0_add_1;
623 | 			for (i = 1; i + 1 < 256; i = i + 1) h_data[i] <= h_data[i + 1];
624 | 		end
625 | 		H_6 : begin
626 | 			cnt <= cnt_add_1;
627 | 			cdf_min <= cdf_min_next;
628 | 			if (h_6_end) h_data[0] <= h_data[1];
629 | 			else h_data[0] <= _h_data_0_add_1;
630 | 			for (i = 1; i + 1 < 256; i = i + 1) h_data[i] <= h_data[i + 1];
631 | 			if (h_6_end) h_data[255] <= 8'd255;
632 | 			else h_data[255] <= _pixel_map;
633 | 
634 | 			if (h_6_end) begin
635 | 				cnt <= 8'd0;
636 | 			end//
637 | 				word <= sram_Q;
638 | 			//end
639 | 		end
640 | 		H_7 : begin
641 | 			cnt <= cnt_add_1;
642 | 			word <= sram_Q;
643 | 		end
644 | 		H_8 : begin
645 | 			if (wready_m_inf) begin
646 | 				cnt <= cnt_add_1;
647 | 				word <= sram_Q;
648 | 			end
649 | 			//else begin //
650 | 				temp <= sram_Q;
651 | 			//end
652 | 		end
653 | 		H_9 : begin
654 | 			if (wready_m_inf) begin
655 | 				cnt <= cnt_add_1;
656 | 				word <= temp;
657 | 			end
658 | 		end
659 | 	endcase
660 | end
661 | 
662 | always @(posedge clk or negedge rst_n) begin
663 | 	if (!rst_n) begin
664 | 		busy <= 1'b0;
665 | 	end
666 | 	else begin
667 | 		busy <= 1'b1;
668 | 		case (state)
669 | 			Idle : busy <= 1'b0;
670 | 		endcase
671 | 	end
672 | end
673 | 
674 | endmodule
675 | 


--------------------------------------------------------------------------------
/Final/MH.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | 
  3 | `include ...
  4 | 
  5 | // synopsys translate_on
  6 | 
  7 | module MH (
  8 | 	clk,
  9 | 	clk2,
 10 | 	rst_n,
 11 | 	in_valid,
 12 | 	op_valid,
 13 | 	pic_data,
 14 | 	se_data,
 15 | 	op,
 16 | 	out_valid,
 17 | 	out_data
 18 | );
 19 | input			clk;
 20 | input			clk2;
 21 | input			rst_n;
 22 | input			in_valid;
 23 | input			op_valid;
 24 | input [31:0]	pic_data;
 25 | input [7:0]		se_data;
 26 | input [2:0]		op;
 27 | output reg			out_valid;
 28 | output reg [31:0]	out_data;
 29 | // 
 30 | integer i, j;
 31 | genvar gv_i, gv_j;
 32 | 
 33 | localparam EROSION	= 3'b010;
 34 | localparam DILATION	= 3'b011;
 35 | localparam HIS_EQ	= 3'b000;
 36 | localparam OPENING	= 3'b110;
 37 | localparam CLOSING	= 3'b111;
 38 | 
 39 | reg _in_valid;
 40 | reg [43:0] _in_data;
 41 | always @(*) begin
 42 | 	_in_valid <= in_valid;
 43 | 	_in_data <= {op_valid, op, se_data, pic_data};
 44 | end
 45 | wire datain_valid;
 46 | wire [43:0] datain;
 47 | DW_data_qsync_lh #(.width(44), .clk_ratio(4), .reg_data_s(1), .reg_data_d(1), .tst_mode(0))
 48 | 	u_DW_data_qsync_lh(.clk_s(clk), .rst_s_n(rst_n), .init_s_n(1'b1), .send_s(_in_valid), .data_s(_in_data),
 49 | 		.clk_d(clk2), .rst_d_n(rst_n), .init_d_n(1'b1), .data_avail_d(datain_valid), .data_d(datain), .test());
 50 | 
 51 | reg dataout_valid;
 52 | reg [31:0] dataout;
 53 | wire _out_valid;
 54 | wire [31:0] _out_data;
 55 | DW_data_qsync_hl #(.width(32), .clk_ratio(4), .tst_mode(0))
 56 | 	u_DW_data_qsync_hl(.clk_s(clk2), .rst_s_n(rst_n), .init_s_n(1'b1), .send_s(dataout_valid), .data_s(dataout),
 57 | 		.clk_d(clk), .rst_d_n(rst_n), .init_d_n(1'b1), .test(), .data_d(_out_data), .data_avail_d(_out_valid));
 58 | always @(posedge clk or negedge rst_n) begin
 59 | 	if (!rst_n) begin
 60 | 		out_valid <= 1'b0;
 61 | 		out_data <= 32'b0;
 62 | 	end
 63 | 	else begin
 64 | 		out_valid <= 1'b0;
 65 | 		out_data <= 32'b0;
 66 | 		if (_out_valid) begin
 67 | 			out_valid <= 1'b1;
 68 | 			out_data <= _out_data;
 69 | 		end
 70 | 	end
 71 | end
 72 | 
 73 | wire [31:0] sram_Q;
 74 | reg sram_WEN;
 75 | reg [7:0] sram_A;
 76 | reg [31:0] sram_D;
 77 | sram_256x32 u_sram_256x32(.Q(sram_Q), .CLK(clk2), .CEN(1'b0), .WEN(sram_WEN), .A(sram_A), .D(sram_D), .OEN(1'b0));
 78 | //
 79 | reg [7:0] data_buffer [0:3][0:31];
 80 | reg [7:0] data_temp [0:3];
 81 | reg [2:0] data_op;
 82 | reg [7:0] data_se [0:3][0:3];
 83 | 
 84 | reg [9:0] cdf [0:255];
 85 | reg [9:0] cdf_min;
 86 | reg [7:0] cdf_min_idx;
 87 | 
 88 | reg [4:0] state, nxt_state;
 89 | localparam Idle		= 5'd0;
 90 | localparam Read1	= 5'd1;
 91 | localparam Read2	= 5'd2;
 92 | localparam Read3	= 5'd3;
 93 | localparam Read4	= 5'd4;
 94 | localparam Out_ED1	= 5'd5;
 95 | localparam Out_ED2	= 5'd6;
 96 | localparam Out_ED3	= 5'd7;
 97 | localparam Out_ED4	= 5'd8;
 98 | localparam Tmp_OC1	= 5'd9;
 99 | localparam Tmp_OC2	= 5'd10;
100 | localparam Tmp_OC3	= 5'd11;
101 | localparam Tmp_OC4	= 5'd12;
102 | localparam Out_OC1	= 5'd13;
103 | localparam Out_OC2	= 5'd14;
104 | localparam Out_OC3	= 5'd15;
105 | localparam Out_OC4	= 5'd16;
106 | localparam Out_OC5	= 5'd17;
107 | localparam Out_OC6	= 5'd18;
108 | localparam Out_HE1	= 5'd19;
109 | localparam Out_HE2	= 5'd20;
110 | localparam Out_HE3	= 5'd21;
111 | localparam Out_HE4	= 5'd22;
112 | localparam Out_HE5	= 5'd23;
113 | localparam Out_HE6	= 5'd24;
114 | localparam Out_HE7	= 5'd25;
115 | localparam Out_HE8	= 5'd26;
116 | 
117 | reg [7:0] cnt;
118 | wire [7:0] cnt_add_1	= cnt + 8'd1;
119 | wire [7:0] cnt_sub_33	= cnt - 8'd33;
120 | wire cnt_eq_0	= (cnt == 8'd0);
121 | wire cnt_eq_1	= (cnt == 8'd1);
122 | wire cnt_eq_31	= (cnt == 8'd31);
123 | wire cnt_eq_255	= (cnt == 8'd255);
124 | wire cnt_ne_32	= (cnt != 8'd32);
125 | wire cnt_lt_16	= (cnt < 8'd16);
126 | wire cnt_lt_32	= (cnt < 8'd32);
127 | wire cnt_gt_1	= (cnt > 8'd1);
128 | wire cnt_ge_8	= (cnt >= 8'd8);
129 | wire cnt_ge_16	= (cnt >= 8'd16);
130 | wire cnt_ge_24	= (cnt >= 8'd24);
131 | wire cnt_bt_24_31	= (cnt_lt_32 && cnt_ge_24);
132 | wire cnt_bt_16_31	= (cnt_lt_32 && cnt_ge_16);
133 | wire cnt_bt_8_31	= (cnt_lt_32 && cnt_ge_8);
134 | wire cnt_eq_last_col = (cnt[2:0] == 3'd7);
135 | 
136 | always @(*) begin
137 | 	nxt_state <= state;
138 | 	case (state)
139 | 		Idle :
140 | 			if (datain_valid) nxt_state <= Read2;
141 | 		Read1 : nxt_state <= Read2;
142 | 		Read2 : nxt_state <= Read3;
143 | 		Read3 : nxt_state <= Read4;
144 | 		Read4 :
145 | 			if (cnt_eq_255) begin
146 | 				case (data_op)
147 | 					EROSION, DILATION : nxt_state <= Out_ED1;
148 | 					OPENING, CLOSING : nxt_state <= Tmp_OC1;
149 | 					HIS_EQ : nxt_state <= Out_HE1;
150 | 				endcase
151 | 			end
152 | 			else nxt_state <= Read1;
153 | 		Out_ED1 : nxt_state <= Out_ED2;
154 | 		Out_ED2 : nxt_state <= Out_ED3;
155 | 		Out_ED3 : nxt_state <= Out_ED4;
156 | 		Out_ED4 :
157 | 			if (cnt_eq_255) nxt_state <= Idle;
158 | 			else nxt_state <= Out_ED1;
159 | 		Tmp_OC1 : nxt_state <= Tmp_OC2;
160 | 		Tmp_OC2 : nxt_state <= Tmp_OC3;
161 | 		Tmp_OC3 : nxt_state <= Tmp_OC4;
162 | 		Tmp_OC4 :
163 | 			if (cnt_eq_31) nxt_state <= Out_OC1;
164 | 			else nxt_state <= Tmp_OC1;
165 | 		Out_OC1 : nxt_state <= Out_OC2;
166 | 		Out_OC2 : nxt_state <= Out_OC3;
167 | 		Out_OC3 : nxt_state <= Out_OC4;
168 | 		Out_OC4 :
169 | 			if (cnt_eq_31) nxt_state <= Out_OC5;
170 | 			else nxt_state <= Out_OC1;
171 | 		Out_OC5 : nxt_state <= Out_OC6;
172 | 		Out_OC6 : nxt_state <= Idle;
173 | 		Out_HE1 : nxt_state <= Out_HE2;
174 | 		Out_HE2 : nxt_state <= Out_HE3;
175 | 		Out_HE3 : nxt_state <= Out_HE4;
176 | 		Out_HE4 :
177 | 			if (cnt_eq_255) nxt_state <= Out_HE5;
178 | 			else nxt_state <= Out_HE1;
179 | 		Out_HE5 : nxt_state <= Out_HE6;
180 | 		Out_HE6 : nxt_state <= Out_HE7;
181 | 		Out_HE7 : nxt_state <= Out_HE8;
182 | 		Out_HE8 :
183 | 			if (cnt_eq_1) nxt_state <= Idle;
184 | 			else nxt_state <= Out_HE5;
185 | 	endcase
186 | end
187 | 
188 | always @(posedge clk2 or negedge rst_n) begin
189 | 	if (!rst_n) state <= Idle;
190 | 	else state <= nxt_state;
191 | end
192 | 
193 | //
194 | reg ed_flag0;
195 | always @(*) begin
196 | 	ed_flag0 <= 1'bx;
197 | 	case (state)
198 | 		Read1, Read2, Read3, Read4, Out_ED1, Out_ED2, Out_ED3, Out_ED4, Tmp_OC1, Tmp_OC2, Tmp_OC3, Tmp_OC4 : begin
199 | 			case (data_op)
200 | 				EROSION, OPENING : ed_flag0 <= 1'b1;
201 | 				DILATION, CLOSING : ed_flag0 <= 1'b0;
202 | 			endcase
203 | 		end
204 | 		Out_OC1, Out_OC2, Out_OC3, Out_OC4 : begin
205 | 			case (data_op)
206 | 				OPENING : ed_flag0 <= 1'b0;
207 | 				CLOSING : ed_flag0 <= 1'b1;
208 | 			endcase
209 | 		end
210 | 	endcase
211 | end
212 | reg [7:0] ed_se [0:3][0:3];
213 | always @(*) begin
214 | 	for (i = 0; i < 4; i = i + 1)
215 | 		for (j = 0; j < 4; j = j + 1)
216 | 			if (ed_flag0) begin
217 | 				ed_se[i][j] <= data_se[i][j];
218 | 			end
219 | 			else begin
220 | 				ed_se[i][j] <= data_se[3 - i][3 - j];
221 | 			end
222 | end
223 | reg [7:0] ed_data0_1 [0:3][0:3];
224 | always @(*) begin
225 | 	for (i = 0; i < 4; i = i + 1)
226 | 		for (j = 0; j < 4; j = j + 1) begin
227 | 			ed_data0_1[i][j] <= 8'bx;
228 | 		end
229 | 	case (state)
230 | 		Read1, Out_ED1, Tmp_OC1, Out_OC1 : begin
231 | 			for (j = 0; j < 4; j = j + 1) begin
232 | 				ed_data0_1[0][j] <= data_buffer[0][j];
233 | 			end
234 | 			for (j = 0; j < 4; j = j + 1) begin
235 | 				if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
236 | 				else ed_data0_1[1][j] <= data_buffer[1][j];
237 | 			end
238 | 			for (j = 0; j < 4; j = j + 1) begin
239 | 				if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
240 | 				else ed_data0_1[2][j] <= data_buffer[2][j];
241 | 			end
242 | 			for (j = 0; j < 4; j = j + 1) begin
243 | 				if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
244 | 				else ed_data0_1[3][j] <= data_buffer[3][j];
245 | 			end
246 | 		end
247 | 		Read2, Out_ED2, Tmp_OC2, Out_OC2 : begin
248 | 			for (j = 0; j < 4; j = j + 1)
249 | 				if (j == 3) begin
250 | 					ed_data0_1[0][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[0][j]);
251 | 				end
252 | 				else begin
253 | 					ed_data0_1[0][j] <= data_buffer[0][j];
254 | 				end
255 | 			for (j = 0; j < 4; j = j + 1)
256 | 				if (j == 3) begin
257 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
258 | 					else ed_data0_1[1][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[1][j]);
259 | 				end
260 | 				else begin
261 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
262 | 					else ed_data0_1[1][j] <= data_buffer[1][j];
263 | 				end
264 | 			for (j = 0; j < 4; j = j + 1)
265 | 				if (j == 3) begin
266 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
267 | 					else ed_data0_1[2][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[2][j]);
268 | 				end
269 | 				else begin
270 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
271 | 					else ed_data0_1[2][j] <= data_buffer[2][j];
272 | 				end
273 | 			for (j = 0; j < 4; j = j + 1)
274 | 				if (j == 3) begin
275 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
276 | 					else ed_data0_1[3][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[3][j]);
277 | 				end
278 | 				else begin
279 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
280 | 					else ed_data0_1[3][j] <= data_buffer[3][j];
281 | 				end
282 | 		end
283 | 		Read3, Out_ED3, Tmp_OC3, Out_OC3 : begin
284 | 			for (j = 0; j < 4; j = j + 1)
285 | 				if (j == 3 || j == 2) begin
286 | 					ed_data0_1[0][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[0][j]);
287 | 				end
288 | 				else begin
289 | 					ed_data0_1[0][j] <= data_buffer[0][j];
290 | 				end
291 | 			for (j = 0; j < 4; j = j + 1)
292 | 				if (j == 3 || j == 2) begin
293 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
294 | 					else ed_data0_1[1][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[1][j]);
295 | 				end
296 | 				else begin
297 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
298 | 					else ed_data0_1[1][j] <= data_buffer[1][j];
299 | 				end
300 | 			for (j = 0; j < 4; j = j + 1)
301 | 				if (j == 3 || j == 2) begin
302 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
303 | 					else ed_data0_1[2][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[2][j]);
304 | 				end
305 | 				else begin
306 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
307 | 					else ed_data0_1[2][j] <= data_buffer[2][j];
308 | 				end
309 | 			for (j = 0; j < 4; j = j + 1)
310 | 				if (j == 3 || j == 2) begin
311 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
312 | 					else ed_data0_1[3][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[3][j]);
313 | 				end
314 | 				else begin
315 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
316 | 					else ed_data0_1[3][j] <= data_buffer[3][j];
317 | 				end
318 | 		end
319 | 		Read4, Out_ED4, Tmp_OC4, Out_OC4 : begin
320 | 			for (j = 0; j < 4; j = j + 1)
321 | 				if (j == 3 || j == 2 || j == 1) begin
322 | 					ed_data0_1[0][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[0][j]);
323 | 				end
324 | 				else begin
325 | 					ed_data0_1[0][j] <= data_buffer[0][j];
326 | 				end
327 | 			for (j = 0; j < 4; j = j + 1)
328 | 				if (j == 3 || j == 2 || j == 1) begin
329 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
330 | 					else ed_data0_1[1][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[1][j]);
331 | 				end
332 | 				else begin
333 | 					if (cnt_bt_24_31) ed_data0_1[1][j] <= 8'd0;
334 | 					else ed_data0_1[1][j] <= data_buffer[1][j];
335 | 				end
336 | 			for (j = 0; j < 4; j = j + 1)
337 | 				if (j == 3 || j == 2 || j == 1) begin
338 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
339 | 					else ed_data0_1[2][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[2][j]);
340 | 				end
341 | 				else begin
342 | 					if (cnt_bt_16_31) ed_data0_1[2][j] <= 8'd0;
343 | 					else ed_data0_1[2][j] <= data_buffer[2][j];
344 | 				end
345 | 			for (j = 0; j < 4; j = j + 1)
346 | 				if (j == 3 || j == 2 || j == 1) begin
347 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
348 | 					else ed_data0_1[3][j] <= (cnt_eq_last_col ? 8'd0 : data_buffer[3][j]);
349 | 				end
350 | 				else begin
351 | 					if (cnt_bt_8_31) ed_data0_1[3][j] <= 8'd0;
352 | 					else ed_data0_1[3][j] <= data_buffer[3][j];
353 | 				end
354 | 		end
355 | 	endcase
356 | end
357 | 
358 | wire [8:0] ed_data0_2 [0:3][0:3];
359 | for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
360 | 	for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
361 | 		DW01_addsub#(.width(8))
362 | 			u_DW01_addsub(.A(ed_data0_1[gv_i][gv_j]), .B(ed_se[gv_i][gv_j]), .CI(1'b0), .ADD_SUB(ed_flag0), .SUM(ed_data0_2[gv_i][gv_j][7:0]), .CO(ed_data0_2[gv_i][gv_j][8]));
363 | 	end
364 | end
365 | 
366 | reg ed_flag1;
367 | reg [7:0] ed_data1 [0:3][0:3];
368 | wire [7:0] _ed_data1 [0:3][0:3];
369 | for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
370 | 	for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
371 | 		assign _ed_data1[gv_i][gv_j] = (ed_data0_2[gv_i][gv_j][8] ? (ed_flag0 ? 8'd0 : 8'd255) : ed_data0_2[gv_i][gv_j][7:0]);
372 | 	end
373 | end
374 | always @(posedge clk2) begin
375 | 	ed_flag1 <= ed_flag0;
376 | 	for (i = 0; i < 4; i = i + 1)
377 | 		for (j = 0; j < 4; j = j + 1) begin
378 | 			ed_data1[i][j] <= _ed_data1[i][j];
379 | 		end
380 | end
381 | wire [127:0] ed_data1_flatten;
382 | for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin
383 | 	for (gv_j = 0; gv_j < 4; gv_j = gv_j + 1) begin
384 | 		assign ed_data1_flatten[(gv_i * 4 + gv_j) * 8 + 7-:8] = ed_data1[gv_i][gv_j];
385 | 	end
386 | end
387 | 
388 | reg [31:0] ed_res;
389 | wire [7:0] _ed_res;
390 | DW_minmax#(.width(8), .num_inputs(16))
391 | 	u_DW_minmax(.a(ed_data1_flatten), .tc(1'b0), .min_max(!ed_flag1), .value(_ed_res), .index());
392 | always @(posedge clk2) begin
393 | 	ed_res[ 7: 0] <= ed_res[15: 8];
394 | 	ed_res[15: 8] <= ed_res[23:16];
395 | 	ed_res[23:16] <= ed_res[31:24];
396 | 	ed_res[31:24] <= _ed_res;
397 | end
398 | 
399 | //
400 | reg [9:0] cdf_next [0:255];
401 | reg [9:0] cdf_min_next;
402 | reg [7:0] cdf_min_idx_next;
403 | always @(*) begin
404 | 	for (i = 0; i < 256; i = i + 1) begin
405 | 		if (i >= data_temp[0]) cdf_next[i] <= cdf[i] + 10'd1;
406 | 		else cdf_next[i] <= cdf[i];
407 | 	end
408 | end
409 | always @(*) begin
410 | 	if (cdf_min_idx >= data_temp[0]) begin
411 | 		cdf_min_next <= cdf[data_temp[0]] + 10'd1;
412 | 		cdf_min_idx_next <= data_temp[0];
413 | 	end
414 | 	else begin
415 | 		cdf_min_next <= cdf_min;
416 | 		cdf_min_idx_next <= cdf_min_idx;
417 | 	end
418 | end
419 | 
420 | reg [9:0] he_cdf_max_sub_cdf_min;
421 | wire [9:0] _he_cdf_max_sub_cdf_min = 11'd1024 - cdf_min;
422 | always @(posedge clk2) begin
423 | 	he_cdf_max_sub_cdf_min <= _he_cdf_max_sub_cdf_min;
424 | end
425 | 
426 | reg [9:0] he_cdfi;
427 | wire [9:0] _he_cdfi = cdf[data_temp[0]];
428 | always @(posedge clk2) begin
429 | 	he_cdfi <= _he_cdfi;
430 | end
431 | 
432 | reg [17:0] he_cdfi_sub_cdf_minx255;
433 | wire [9:0] _he_cdfi_sub_cdf_min = he_cdfi - cdf_min;
434 | wire [17:0] _he_cdfi_sub_cdf_minx255 = _he_cdfi_sub_cdf_min * 8'd255;
435 | always @(posedge clk2) begin
436 | 	he_cdfi_sub_cdf_minx255 <= _he_cdfi_sub_cdf_minx255;
437 | end
438 | 
439 | wire [17:0] rq_cur [0:7];
440 | wire [17:0] _rq_nxt [0:7];
441 | wire [10:0] _rq_temp_0 [0:7];
442 | wire signed [11:0] _rq_temp_1 [0:7];
443 | reg [17:0] _rq_nxt_reg [0:7];
444 | generate
445 | 	assign rq_cur[0] = he_cdfi_sub_cdf_minx255;
446 | 	for (gv_i = 1; gv_i < 8; gv_i = gv_i + 1) begin
447 | 		assign rq_cur[gv_i] = _rq_nxt_reg[gv_i - 1];
448 | 	end
449 | 	for (gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin
450 | 		assign _rq_temp_0[gv_i] = rq_cur[gv_i][17:7];
451 | 		assign _rq_temp_1[gv_i] = _rq_temp_0[gv_i] - he_cdf_max_sub_cdf_min;
452 | 		assign _rq_nxt[gv_i] = (_rq_temp_1[gv_i][11] ?
453 | 			{_rq_temp_0[gv_i][9:0], rq_cur[gv_i][6:0], 1'b0} :
454 | 			{_rq_temp_1[gv_i][9:0], rq_cur[gv_i][6:0], 1'b1});
455 | 	end
456 | 	for (gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin
457 | 		if (gv_i % 2 == 1) begin
458 | 			always @(posedge clk2) begin
459 | 				_rq_nxt_reg[gv_i] <= _rq_nxt[gv_i];
460 | 			end
461 | 		end
462 | 		else begin
463 | 			always @(*) begin
464 | 				_rq_nxt_reg[gv_i] <= _rq_nxt[gv_i];
465 | 			end
466 | 		end
467 | 	end
468 | endgenerate
469 | 
470 | reg [31:0] he_res;
471 | wire [7:0] _he_res = _rq_nxt[7][7:0];
472 | always @(posedge clk2) begin
473 | 	he_res[ 7: 0] <= he_res[15: 8];
474 | 	he_res[15: 8] <= he_res[23:16];
475 | 	he_res[23:16] <= he_res[31:24];
476 | 	he_res[31:24] <= _he_res;
477 | end
478 | 
479 | always @(*) begin
480 | 	sram_WEN <= 1'b1;
481 | 	sram_A <= cnt_add_1;
482 | 	sram_D <= 32'bx;
483 | 	case (state)
484 | 		Idle : begin
485 | 			sram_WEN <= 1'b0;
486 | 			sram_A <= cnt;
487 | 			sram_D <= datain[31:0];
488 | 		end
489 | 		Read1 : begin
490 | 			sram_WEN <= 1'b0;
491 | 			sram_A <= cnt;
492 | 			sram_D <= datain[31:0];
493 | 		end
494 | 		Read2 : begin
495 | 			if (!cnt_lt_16 && data_op != HIS_EQ) begin
496 | 				sram_WEN <= 1'b0;
497 | 				sram_A <= cnt_sub_33;
498 | 				sram_D <= ed_res;
499 | 			end
500 | 		end
501 | 		Out_ED2, Tmp_OC2, Out_OC2 : begin
502 | 			sram_WEN <= 1'b0;
503 | 			sram_A <= cnt_sub_33;
504 | 			sram_D <= ed_res;
505 | 		end
506 | 	endcase
507 | end
508 | 
509 | always @(posedge clk2) begin
510 | 	case (state)
511 | 		Idle : begin
512 | 			cnt <= 8'd0;
513 | 		end
514 | 		Read4, Out_ED4, Tmp_OC4, Out_OC4, Out_HE4, Out_HE8 : begin
515 | 			cnt <= cnt_add_1;
516 | 		end
517 | 	endcase
518 | end
519 | 
520 | always @(posedge clk2) begin
521 | 	for (i = 0; i < 4; i = i + 1)
522 | 		for (j = 0; j < 32; j = j + 1)
523 | 			if (i == 3 && j == 31) begin
524 | 				data_buffer[3][31] <= 8'bx;
525 | 			end
526 | 			else if (j == 31) begin
527 | 				data_buffer[i][31] <= data_buffer[i + 1][0];
528 | 			end
529 | 			else begin
530 | 				data_buffer[i][j] <= data_buffer[i][j + 1];
531 | 			end
532 | 	case (state)
533 | 		Idle, Read1 : begin
534 | 			data_buffer[3][31] <= datain[7:0];
535 | 			if (datain[43]) begin
536 | 				data_op <= datain[42:40];
537 | 			end
538 | 			if (cnt_lt_16) begin
539 | 				for (i = 0; i < 4; i = i + 1)
540 | 					for (j = 0; j < 4; j = j + 1)
541 | 						if (i == 3 && j == 3) begin
542 | 							data_se[3][3] <= datain[39:32];
543 | 						end
544 | 						else if (j == 3) begin
545 | 							data_se[i][3] <= data_se[i + 1][0];
546 | 						end
547 | 						else begin
548 | 							data_se[i][j] <= data_se[i][j + 1];
549 | 						end
550 | 			end
551 | 		end
552 | 		Read2 : begin
553 | 			data_buffer[3][31] <= datain[15:8];
554 | 		end
555 | 		Read3 : begin
556 | 			data_buffer[3][31] <= datain[23:16];
557 | 		end
558 | 		Read4 : begin
559 | 			data_buffer[3][31] <= datain[31:24];
560 | 		end
561 | 		Out_ED1, Tmp_OC1, Out_OC1 : begin
562 | 			data_buffer[3][31] <= sram_Q[7:0];
563 | 		end
564 | 		Out_ED2, Out_ED3, Out_ED4, Tmp_OC2, Tmp_OC3, Tmp_OC4, Out_OC2, Out_OC3, Out_OC4 : begin
565 | 			data_buffer[3][31] <= data_temp[1];
566 | 		end
567 | 	endcase
568 | end
569 | 
570 | always @(posedge clk2) begin
571 | 	data_temp[0] <= data_temp[1];
572 | 	data_temp[1] <= data_temp[2];
573 | 	data_temp[2] <= data_temp[3];
574 | 	data_temp[3] <= 8'bx;
575 | 	case (state)
576 | 		Idle, Read1 : begin
577 | 			data_temp[0] <= datain[7:0];
578 | 			data_temp[1] <= datain[15:8];
579 | 			data_temp[2] <= datain[23:16];
580 | 			data_temp[3] <= datain[31:24];
581 | 		end
582 | 		Out_ED1, Tmp_OC1, Out_OC1, Out_HE1 : begin
583 | 			data_temp[0] <= sram_Q[7:0];
584 | 			data_temp[1] <= sram_Q[15:8];
585 | 			data_temp[2] <= sram_Q[23:16];
586 | 			data_temp[3] <= sram_Q[31:24];
587 | 		end
588 | 	endcase
589 | end
590 | 
591 | always @(posedge clk2) begin //= =
592 | 	case (state)
593 | 		Idle : begin
594 | 			for (i = 0; i < 256; i = i + 1) begin
595 | 				cdf[i] <= 10'd0;
596 | 			end
597 | 		end
598 | 		Read1, Read2, Read3, Read4 : begin
599 | 			for (i = 0; i < 256; i = i + 1) begin
600 | 				cdf[i] <= cdf_next[i];
601 | 			end
602 | 		end
603 | 		Out_HE1 : begin
604 | 			for (i = 0; i < 256; i = i + 1) begin
605 | 				if (cnt_eq_0) cdf[i] <= cdf_next[i];
606 | 			end
607 | 		end
608 | 	endcase
609 | end
610 | 
611 | always @(posedge clk2) begin
612 | 	case (state)
613 | 		Idle : begin
614 | 			cdf_min_idx <= 8'd255;
615 | 		end
616 | 		Read1, Read2, Read3, Read4 : begin
617 | 			cdf_min <= cdf_min_next;
618 | 			cdf_min_idx <= cdf_min_idx_next;
619 | 		end
620 | 		Out_HE1 : begin
621 | 			if (cnt_eq_0) begin
622 | 				cdf_min <= cdf_min_next;
623 | 				cdf_min_idx <= cdf_min_idx_next;
624 | 			end
625 | 		end
626 | 	endcase
627 | end
628 | 
629 | always @(posedge clk2) begin
630 | 	dataout_valid <= 1'b0;
631 | 	dataout <= 32'b0;
632 | 	case (state)
633 | 		Out_ED1 : begin
634 | 			dataout_valid <= 1'b1;
635 | 			dataout <= sram_Q;
636 | 		end
637 | 		Out_OC2 : begin
638 | 			if (cnt_ne_32) begin
639 | 				dataout_valid <= 1'b1;
640 | 				dataout <= ed_res;
641 | 			end
642 | 		end
643 | 		Out_OC6 : begin
644 | 			dataout_valid <= 1'b1;
645 | 			dataout <= ed_res;
646 | 		end
647 | 		Out_HE3 : begin
648 | 			if (cnt_gt_1) begin
649 | 				dataout_valid <= 1'b1;
650 | 				dataout <= he_res;
651 | 			end
652 | 		end
653 | 		Out_HE7 : begin
654 | 			dataout_valid <= 1'b1;
655 | 			dataout <= he_res;
656 | 		end
657 | 	endcase
658 | end
659 | 
660 | endmodule
661 | 


--------------------------------------------------------------------------------
/Lab11/MMSA.v:
--------------------------------------------------------------------------------
  1 | // synopsys translate_off
  2 | 
  3 | `include ...
  4 | 
  5 | // synopsys translate_on
  6 | 
  7 | module MMSA(
  8 | // input signals
  9 |     clk,
 10 |     rst_n,
 11 |     in_valid,
 12 |     in_valid2,
 13 |     matrix,
 14 |     matrix_size,
 15 |     i_mat_idx,
 16 |     w_mat_idx,
 17 | 
 18 | // output signals
 19 |     out_valid,
 20 |     out_value
 21 | );
 22 | input clk;
 23 | input rst_n;
 24 | input in_valid;
 25 | input in_valid2;
 26 | input matrix;
 27 | input [1:0]  matrix_size;
 28 | input i_mat_idx, w_mat_idx;
 29 | 
 30 | output reg out_valid;
 31 | output reg out_value;
 32 | //---------------------------------------------------------------------
 33 | //
 34 | //---------------------------------------------------------------------
 35 | genvar gv_i, gv_j;
 36 | integer i, j;
 37 | 
 38 | wire signed [127:0] m_Q;
 39 | reg m_WEN;
 40 | reg [6:0] m_A;
 41 | reg signed [127:0] m_D;
 42 | sram_128x128 u_sram_128x128_m(.Q(m_Q), .CLK(clk), .CEN(1'b0), .WEN(m_WEN), .A(m_A), .D(m_D), .OEN(1'b0));
 43 | wire [127:0] w_Q;
 44 | reg w_WEN;
 45 | reg [6:0] w_A;
 46 | reg [127:0] w_D;
 47 | sram_128x128 u_sram_128x128_w(.Q(w_Q), .CLK(clk), .CEN(1'b0), .WEN(w_WEN), .A(w_A), .D(w_D), .OEN(1'b0));
 48 | 
 49 | reg [127:0] data_in;
 50 | reg [1:0] sz;
 51 | reg [2:0] size_sub_1;
 52 | reg [3:0] mi, wi;
 53 | reg signed [37:0] ans [0:14];
 54 | reg signed [39:0] data_out;
 55 | 
 56 | reg output_is_begin;
 57 | reg output_is_end;
 58 | 
 59 | reg [3:0] bcnt;
 60 | wire bcnt_eq_0 = (bcnt == 4'd0);
 61 | wire bcnt_eq_3 = (bcnt == 4'd3);
 62 | wire bcnt_eq_15 = (bcnt == 4'd15);
 63 | wire [3:0] bcnt_add_1 = bcnt + 4'd1;
 64 | 
 65 | reg [2:0] ccnt;
 66 | wire [2:0] ccnt_end = size_sub_1;
 67 | wire ccnt_is_begin = (ccnt == 3'd0);
 68 | wire ccnt_is_end = (ccnt == ccnt_end);
 69 | wire [2:0] ccnt_add_1 = ccnt + 3'd1;
 70 | wire [2:0] ccnt_next = (ccnt_is_end ? 3'd0 : ccnt_add_1);
 71 | 
 72 | reg [2:0] rcnt;
 73 | wire [2:0] rcnt_end = size_sub_1;
 74 | wire rcnt_is_begin = (rcnt == 3'd0);
 75 | wire rcnt_is_end = (rcnt == rcnt_end);
 76 | wire [2:0] rcnt_add_1 = rcnt + 3'd1;
 77 | wire [2:0] rcnt_next = (rcnt_is_end ? 3'd0 : rcnt_add_1);
 78 | 
 79 | wire rcnt_eq_ccnt = (rcnt == ccnt);
 80 | wire ccnt_eq_size_sub_1_sub_rcnt = (ccnt == size_sub_1 - rcnt);
 81 | wire [2:0] rcnt_sub_ccnt_next = rcnt - ccnt_next;
 82 | wire [2:0] size_sub_1_sub_rcnt_next = size_sub_1 - rcnt_next;
 83 | wire [2:0] ccnt_add_rcnt_next = ccnt + rcnt_next;
 84 | 
 85 | reg [3:0] cnt;
 86 | wire cnt_eq_15 = (cnt == 4'd15);
 87 | wire [3:0] cnt_next = cnt + 4'd1;
 88 | 
 89 | reg [2:0] state, nxt_state;
 90 | localparam Idle1	= 3'd0;
 91 | localparam Readm	= 3'd1;
 92 | localparam Readw	= 3'd2;
 93 | localparam Idle2	= 3'd3;
 94 | localparam Work1	= 3'd4;
 95 | localparam Work2	= 3'd5;
 96 | localparam Output	= 3'd6;
 97 | 
 98 | wire [127:0] data_in_next_b = {{127{1'b0}}, matrix};
 99 | wire [127:0] data_in_next_m = {data_in[126:0], matrix};
100 | wire [127:0] data_in_next_w = {w_Q[111:0], data_in[14:0], matrix};
101 | wire [3:0] mi_next = {mi[2:0], i_mat_idx};
102 | wire [3:0] wi_next = {wi[2:0], w_mat_idx};
103 | 
104 | wire signed [31:0] p [0:7];
105 | generate
106 | 	for (gv_i = 0; gv_i < 8; gv_i = gv_i + 1) begin:MULT_BLOCK
107 | 		DW02_mult #(.A_width(16), .B_width(16))
108 | 			u_DW02_mult(.A(m_Q[(7 - gv_i) * 16 + 15 -: 16]), .B(w_Q[(7 - gv_i) * 16 + 15 -: 16]), .TC(1'b1), .PRODUCT(p[gv_i]));
109 | 	end
110 | endgenerate
111 | wire signed [32:0] dp_aux1 [0:3];
112 | generate
113 | 	for (gv_i = 0; gv_i < 4; gv_i = gv_i + 1) begin:ADD_BLOCK_1
114 | 		DW01_add #(.width(33))
115 | 			u_DW01_add(.A({p[gv_i * 2][31], p[gv_i * 2]}), .B({p[gv_i * 2 + 1][31], p[gv_i * 2 + 1]}), .CI(1'b0), .SUM(dp_aux1[gv_i]), .CO());
116 | 	end
117 | endgenerate
118 | wire signed [33:0] dp_aux2 [0:1];
119 | generate
120 | 	for (gv_i = 0; gv_i < 2; gv_i = gv_i + 1) begin:ADD_BLOCK_2
121 | 		DW01_add #(.width(34))
122 | 			u_DW01_add(.A({dp_aux1[gv_i * 2][32], dp_aux1[gv_i * 2]}), .B({dp_aux1[gv_i * 2 + 1][32], dp_aux1[gv_i * 2 + 1]}), .CI(1'b0), .SUM(dp_aux2[gv_i]), .CO());
123 | 	end
124 | endgenerate
125 | wire signed [34:0] dp;
126 | DW01_add #(.width(35))
127 | 	u_DW01_add(.A({dp_aux2[0][33], dp_aux2[0]}), .B({dp_aux2[1][33], dp_aux2[1]}), .CI(1'b0), .SUM(dp), .CO());
128 | reg signed [37:0] ans_next [0:14];
129 | 
130 | always @(*) begin
131 | 	nxt_state <= state;
132 | 	case (state)
133 | 		Idle1 :
134 | 			if (in_valid) begin
135 | 				nxt_state <= Readm;
136 | 			end
137 | 		Readm :
138 | 			//if (in_valid) begin
139 | 				if (bcnt_eq_15 && ccnt_is_end && rcnt_is_end && cnt_eq_15) nxt_state <= Readw;
140 | 			//end
141 | 		Readw :
142 | 			//if (in_valid) begin
143 | 				if (bcnt_eq_15 && ccnt_is_end && rcnt_is_end && cnt_eq_15) nxt_state <= Idle2;
144 | 			//end
145 | 		Idle2 :
146 | 			if (bcnt_eq_3) begin
147 | 				nxt_state <= Work1;
148 | 			end
149 | 		Work1 :
150 | 			if (rcnt_eq_ccnt && rcnt_is_end) nxt_state <= Work2;
151 | 		Work2 :
152 | 			if (ccnt_eq_size_sub_1_sub_rcnt && ccnt_is_end) nxt_state <= Output;
153 | 		Output :
154 | 			if (output_is_end) begin
155 | 				if (cnt_eq_15) nxt_state <= Idle1;
156 | 				else nxt_state <= Idle2;
157 | 			end
158 | 	endcase
159 | end
160 | 
161 | always @(posedge clk or negedge rst_n) begin
162 | 	if (!rst_n) state <= Idle1;
163 | 	else state <= nxt_state;
164 | end
165 | 
166 | always @(*) begin
167 | 	m_WEN <= 1'b1;
168 | 	m_A <= 7'bx;
169 | 	m_D <= 128'bx;
170 | 	w_WEN <= 1'b1;
171 | 	w_A <= 7'bx;
172 | 	w_D <= 128'bx;
173 | 	case (state)
174 | 		Readm : begin
175 | 			//if(in_valid) begin
176 | 				if (bcnt_eq_15 && ccnt_is_end) begin//
177 | 					m_A <= {cnt, rcnt};
178 | 					m_WEN <= 1'b0;
179 | 					m_D <= data_in_next_m;
180 | 				end
181 | 			//end
182 | 		end
183 | 		Readw : begin
184 | 			//if(in_valid) begin
185 | 				w_A <= {cnt, ccnt};
186 | 				if (bcnt_eq_15) begin
187 | 					w_WEN <= 1'b0;
188 | 					if (rcnt_is_begin) w_D <= {{112{1'b0}}, data_in_next_w[15:0]};
189 | 					else w_D <= data_in_next_w;
190 | 				end
191 | 			//end
192 | 		end
193 | 		Idle2 : begin
194 | 			//if (bcnt_eq_3) begin
195 | 				m_A <= {mi_next, 3'd0};
196 | 				w_A <= {wi_next, 3'd0};
197 | 			//end
198 | 		end
199 | 		Work1 : begin
200 | 			if (rcnt_eq_ccnt) begin
201 | 				m_A <= {mi, rcnt_next};
202 | 				if (rcnt_is_end) m_A <= {mi, rcnt_end};
203 | 			end
204 | 			else m_A <= {mi, rcnt_sub_ccnt_next};
205 | 			if (rcnt_eq_ccnt) begin
206 | 				w_A <= {wi, 3'd0};
207 | 				if (rcnt_is_end) w_A <= {wi, 3'd1};
208 | 			end
209 | 			else w_A <= {wi, ccnt_next};
210 | 		end
211 | 		Work2 : begin
212 | 			if (ccnt_eq_size_sub_1_sub_rcnt) m_A <= {mi, size_sub_1};
213 | 			else m_A <= {mi, size_sub_1_sub_rcnt_next};
214 | 			if (ccnt_eq_size_sub_1_sub_rcnt) w_A <= {wi, ccnt_next};
215 | 			else w_A <= {wi, ccnt_add_rcnt_next};
216 | 		end
217 | 	endcase
218 | end
219 | 
220 | reg signed [37:0] ans_old;
221 | always @(*) begin
222 | 	ans_old <= 38'sbx;
223 | 	case (state)
224 | 		Work1 : begin
225 | 			ans_old <= ans[rcnt];
226 | 		end
227 | 		Work2 : begin
228 | 			ans_old <= ans[{1'b0, size_sub_1} + ccnt];
229 | 		end
230 | 	endcase
231 | end
232 | 
233 | wire signed [37:0] ans_new;
234 | DW01_add #(.width(38))
235 | 	u_DW01_add_2(.A(ans_old), .B({{3{dp[34]}}, dp}), .CI(1'b0), .SUM(ans_new), .CO());
236 | 
237 | always @(*) begin
238 | 	for (i = 0; i < 15; i = i + 1) ans_next[i] <= ans[i];
239 | 	case (state)
240 | 		Work1 : begin
241 | 			for (i = 0; i < 8; i = i + 1) begin
242 | 				if (i == 0) begin
243 | 					if (rcnt == i) ans_next[i] <= dp;
244 | 				end
245 | 				else begin
246 | 					if (rcnt == i) ans_next[i] <= ans_new;
247 | 				end
248 | 			end
249 | 		end
250 | 		Work2 : begin
251 | 			for (i = 1; i < 15; i = i + 1) begin
252 | 				if (i == 14) begin
253 | 					if (size_sub_1 + ccnt == i) ans_next[i] <= dp;
254 | 				end
255 | 				else begin
256 | 					if (size_sub_1 + ccnt == i) ans_next[i] <= ans_new;
257 | 				end
258 | 			end
259 | 		end
260 | 	endcase
261 | end
262 | 
263 | always @(*) begin
264 | 	output_is_begin <= 1'b0;
265 | 	case (state)
266 | 		Work1 : begin
267 | 			if (rcnt_is_begin && ccnt_is_begin) output_is_begin <= 1'b1;
268 | 		end
269 | 	endcase
270 | end
271 | 
272 | always @(posedge clk) begin
273 | 	case (state)
274 | 		Idle1 : begin
275 | 			//if (in_valid) begin
276 | 				sz <= matrix_size;
277 | 				case (matrix_size)
278 | 					2'b00 : size_sub_1 <= 4'd1;
279 | 					2'b01 : size_sub_1 <= 4'd3;
280 | 					2'b10 : size_sub_1 <= 4'd7;
281 | 				endcase
282 | 				data_in <= data_in_next_b; // reading
283 | 			//end
284 | 			bcnt <= 4'd1;
285 | 			ccnt <= 3'd0;
286 | 			rcnt <= 3'd0;
287 | 			cnt <= 4'd0;
288 | 		end
289 | 		Readm : begin
290 | 			//if (in_valid) begin
291 | 				if (bcnt_eq_0 && ccnt_is_begin) data_in <= data_in_next_b; // reading
292 | 				else data_in <= data_in_next_m; // reading
293 | 				bcnt <= (bcnt_eq_15 ? 4'd0 : bcnt_add_1);
294 | 				if (bcnt_eq_15) ccnt <= ccnt_next;
295 | 				if (bcnt_eq_15 && ccnt_is_end) rcnt <= rcnt_next;
296 | 				if (bcnt_eq_15 && ccnt_is_end && rcnt_is_end) cnt <= cnt_next;
297 | 			//end
298 | 		end
299 | 		Readw : begin
300 | 			//if (in_valid) begin
301 | 				data_in <= data_in_next_w; // reading
302 | 				bcnt <= (bcnt_eq_15 ? 4'd0 : bcnt_add_1);
303 | 				if (bcnt_eq_15) ccnt <= ccnt_next;
304 | 				if (bcnt_eq_15 && ccnt_is_end) rcnt <= rcnt_next;
305 | 				if (bcnt_eq_15 && ccnt_is_end && rcnt_is_end) cnt <= cnt_next;
306 | 			//end
307 | 		end
308 | 		Idle2 : begin
309 | 			//if (in_valid2) begin
310 | 				mi <= mi_next; // reading
311 | 				wi <= wi_next; // reading
312 | 			if (in_valid2) begin
313 | 				bcnt <= (bcnt_eq_3 ? 4'd0 : bcnt_add_1);
314 | 			end//
315 | 			for (i = 0; i < 15; i = i + 1) ans[i] <= 38'sd0;
316 | 		end
317 | 		Work1 : begin
318 | 			for (i = 0; i < 15; i = i + 1) ans[i] <= ans_next[i];
319 | 			ccnt <= ccnt_next;
320 | 			if (rcnt_eq_ccnt) begin
321 | 				rcnt <= rcnt_next;
322 | 				ccnt <= 3'd0;
323 | 				if (rcnt_is_end) begin
324 | 					ccnt <= 3'd1;
325 | 					rcnt <= 3'd0;
326 | 				end
327 | 			end
328 | 		end
329 | 		Work2 : begin
330 | 			for (i = 0; i < 15; i = i + 1) ans[i] <= ans_next[i];
331 | 			rcnt <= rcnt_next;
332 | 			if (ccnt_eq_size_sub_1_sub_rcnt) begin
333 | 				ccnt <= ccnt_next;
334 | 				rcnt <= 3'd0;
335 | 			end
336 | 		end
337 | 		Output : begin
338 | 			if (output_is_end) cnt <= cnt_next;
339 | 		end
340 | 	endcase
341 | end
342 | 
343 | 
344 | reg [2:0] state2, nxt_state2;
345 | localparam Idle_s2		= 3'd0;
346 | localparam Lout_5_s2	= 3'd1;
347 | localparam Lout_4_s2	= 3'd2;
348 | localparam Lout_3_s2	= 3'd3;
349 | localparam Lout_210_s2	= 3'd4;
350 | localparam Lout_s2		= 3'd5;
351 | localparam Dout_s2		= 3'd6;
352 | 
353 | reg [2:0] llcnt;
354 | wire [2:0] llcnt_sub_1 = llcnt - 3'd1;
355 | wire llcnt_is_end = (llcnt == 3'd0);
356 | 
357 | reg [5:0] lcnt;
358 | wire [5:0] lcnt_sub_1 = lcnt - 6'd1;
359 | wire lcnt_is_end = (lcnt == 6'd1);
360 | 
361 | reg [3:0] ocnt;
362 | wire [3:0] ocnt_add_1 = ocnt + 4'd1;
363 | wire [3:0] ocnt_is_end = (ocnt == {size_sub_1, 1'b1});
364 | 
365 | reg find1_b;
366 | reg [2:0] llcnt_next_b;
367 | reg [5:0] lcnt_next_b;
368 | reg signed [39:0] data_out_next_b;
369 | 
370 | reg find1;
371 | reg [2:0] llcnt_next;
372 | reg [5:0] lcnt_next;
373 | reg signed [39:0] data_out_next;
374 | 
375 | always @(*) begin
376 | 	nxt_state2 <= state2;
377 | 	case (state2)
378 | 		Idle_s2 :
379 | 			if (output_is_begin) begin
380 | 				if (find1_b) nxt_state2 <= Lout_s2;
381 | 				else nxt_state2 <= Lout_4_s2;
382 | 			end
383 | 		Lout_5_s2 :
384 | 			if (find1) nxt_state2 <= Lout_s2;
385 | 			else nxt_state2 <= Lout_4_s2;
386 | 		Lout_4_s2 :
387 | 			if (find1) nxt_state2 <= Lout_s2;
388 | 			else nxt_state2 <= Lout_3_s2;
389 | 		Lout_3_s2 :
390 | 			if (find1) nxt_state2 <= Lout_s2;
391 | 			else nxt_state2 <= Lout_210_s2;
392 | 		Lout_210_s2 : nxt_state2 <= Lout_s2;
393 | 		Lout_s2 :
394 | 			if (llcnt_is_end) nxt_state2 <= Dout_s2;
395 | 		Dout_s2 :
396 | 			if (lcnt_is_end) begin
397 | 				if (ocnt_is_end) nxt_state2 <= Idle_s2;
398 | 				else nxt_state2 <= Lout_5_s2;
399 | 			end
400 | 	endcase
401 | end
402 | 
403 | always @(posedge clk or negedge rst_n) begin
404 | 	if (!rst_n) state2 <= Idle_s2;
405 | 	else state2 <= nxt_state2;
406 | end
407 | 
408 | /*** WARNING ***/
409 | // Using dp (dot product) directly is dangerous!!
410 | // It depends on whether output_is_begin is high instantly.
411 | always @(*) begin
412 | 	find1_b <= 1'b1;
413 | 	llcnt_next_b <= 3'bx;
414 | 	lcnt_next_b <= 6'bx;
415 | 	data_out_next_b <= 40'sbx;
416 | 
417 | 	llcnt_next_b <= 3'd4;
418 | 	if (dp[34]) begin
419 | 		lcnt_next_b <= 6'd40;
420 | 		data_out_next_b <= {{5{1'b1}}, dp};
421 | 	end
422 | 	else if (dp[33]) begin
423 | 		lcnt_next_b <= 6'd34;
424 | 		data_out_next_b <= {dp[33:0], 6'bx};
425 | 	end
426 | 	else if (dp[32]) begin
427 | 		lcnt_next_b <= 6'd33;
428 | 		data_out_next_b <= {dp[32:0], 7'bx};
429 | 	end
430 | 	else if (dp[31]) begin
431 | 		lcnt_next_b <= 6'd32;
432 | 		data_out_next_b <= {dp[31:0], 8'bx};
433 | 	end
434 | 	else begin
435 | 		find1_b <= 1'b0;
436 | 		//llcnt_next_b <= 3'bx;
437 | 		data_out_next_b <= {dp[30:0], 9'bx};
438 | 	end
439 | end
440 | 
441 | always @(*) begin
442 | 	find1 <= 1'b1;
443 | 	llcnt_next <= 3'bx;
444 | 	lcnt_next <= 6'bx;
445 | 	data_out_next <= 40'sbx;
446 | 	case (state2)
447 | 		Lout_5_s2 : begin
448 | 			llcnt_next <= 3'd4;
449 | 			if (data_out[37]) begin
450 | 				lcnt_next <= 6'd40;
451 | 				data_out_next <= data_out;
452 | 			end
453 | 			else if (data_out[36]) begin
454 | 				lcnt_next <= 6'd37;
455 | 				data_out_next <= {data_out[36:0], 3'bx};
456 | 			end
457 | 			else if (data_out[35]) begin
458 | 				lcnt_next <= 6'd36;
459 | 				data_out_next <= {data_out[35:0], 4'bx};
460 | 			end
461 | 			else if (data_out[34]) begin
462 | 				lcnt_next <= 6'd35;
463 | 				data_out_next <= {data_out[34:0], 5'bx};
464 | 			end
465 | 			else if (data_out[33]) begin
466 | 				lcnt_next <= 6'd34;
467 | 				data_out_next <= {data_out[33:0], 6'bx};
468 | 			end
469 | 			else if (data_out[32]) begin
470 | 				lcnt_next <= 6'd33;
471 | 				data_out_next <= {data_out[32:0], 7'bx};
472 | 			end
473 | 			else if (data_out[31]) begin
474 | 				lcnt_next <= 6'd32;
475 | 				data_out_next <= {data_out[31:0], 8'bx};
476 | 			end
477 | 			else begin
478 | 				find1 <= 1'b0;
479 | 				//llcnt_next <= 3'bx;
480 | 				data_out_next <= {data_out[30:0], 9'bx};
481 | 			end
482 | 		end
483 | 		Lout_4_s2 : begin
484 | 			llcnt_next <= 3'd3;
485 | 			if (data_out[39]) begin
486 | 				lcnt_next <= 6'd31;
487 | 				data_out_next <= data_out;
488 | 			end
489 | 			else if (data_out[38]) begin
490 | 				lcnt_next <= 6'd30;
491 | 				data_out_next <= {data_out[38:0], 1'bx};
492 | 			end
493 | 			else if (data_out[37]) begin
494 | 				lcnt_next <= 6'd29;
495 | 				data_out_next <= {data_out[37:0], 2'bx};
496 | 			end
497 | 			else if (data_out[36]) begin
498 | 				lcnt_next <= 6'd28;
499 | 				data_out_next <= {data_out[36:0], 3'bx};
500 | 			end
501 | 			else if (data_out[35]) begin
502 | 				lcnt_next <= 6'd27;
503 | 				data_out_next <= {data_out[35:0], 4'bx};
504 | 			end
505 | 			else if (data_out[34]) begin
506 | 				lcnt_next <= 6'd26;
507 | 				data_out_next <= {data_out[34:0], 5'bx};
508 | 			end
509 | 			else if (data_out[33]) begin
510 | 				lcnt_next <= 6'd25;
511 | 				data_out_next <= {data_out[33:0], 6'bx};
512 | 			end
513 | 			else if (data_out[32]) begin
514 | 				lcnt_next <= 6'd24;
515 | 				data_out_next <= {data_out[32:0], 7'bx};
516 | 			end
517 | 			else if (data_out[31]) begin
518 | 				lcnt_next <= 6'd23;
519 | 				data_out_next <= {data_out[31:0], 8'bx};
520 | 			end
521 | 			else if (data_out[30]) begin
522 | 				lcnt_next <= 6'd22;
523 | 				data_out_next <= {data_out[30:0], 9'bx};
524 | 			end
525 | 			else if (data_out[29]) begin
526 | 				lcnt_next <= 6'd21;
527 | 				data_out_next <= {data_out[29:0], 10'bx};
528 | 			end
529 | 			else if (data_out[28]) begin
530 | 				lcnt_next <= 6'd20;
531 | 				data_out_next <= {data_out[28:0], 11'bx};
532 | 			end
533 | 			else if (data_out[27]) begin
534 | 				lcnt_next <= 6'd19;
535 | 				data_out_next <= {data_out[27:0], 12'bx};
536 | 			end
537 | 			else if (data_out[26]) begin
538 | 				lcnt_next <= 6'd18;
539 | 				data_out_next <= {data_out[26:0], 13'bx};
540 | 			end
541 | 			else if (data_out[25]) begin
542 | 				lcnt_next <= 6'd17;
543 | 				data_out_next <= {data_out[25:0], 14'bx};
544 | 			end
545 | 			else if (data_out[24]) begin
546 | 				lcnt_next <= 6'd16;
547 | 				data_out_next <= {data_out[24:0], 15'bx};
548 | 			end
549 | 			else begin
550 | 				find1 <= 1'b0;
551 | 				//llcnt_next <= 3'bx;
552 | 				data_out_next <= {data_out[23:0], 16'bx};
553 | 			end
554 | 		end
555 | 		Lout_3_s2 : begin
556 | 			llcnt_next <= 3'd2;
557 | 			if (data_out[39]) begin
558 | 				lcnt_next <= 6'd15;
559 | 				data_out_next <= data_out;
560 | 			end
561 | 			else if (data_out[38]) begin
562 | 				lcnt_next <= 6'd14;
563 | 				data_out_next <= {data_out[38:0], 1'bx};
564 | 			end
565 | 			else if (data_out[37]) begin
566 | 				lcnt_next <= 6'd13;
567 | 				data_out_next <= {data_out[37:0], 2'bx};
568 | 			end
569 | 			else if (data_out[36]) begin
570 | 				lcnt_next <= 6'd12;
571 | 				data_out_next <= {data_out[36:0], 3'bx};
572 | 			end
573 | 			else if (data_out[35]) begin
574 | 				lcnt_next <= 6'd11;
575 | 				data_out_next <= {data_out[35:0], 4'bx};
576 | 			end
577 | 			else if (data_out[34]) begin
578 | 				lcnt_next <= 6'd10;
579 | 				data_out_next <= {data_out[34:0], 5'bx};
580 | 			end
581 | 			else if (data_out[33]) begin
582 | 				lcnt_next <= 6'd9;
583 | 				data_out_next <= {data_out[33:0], 6'bx};
584 | 			end
585 | 			else if (data_out[32]) begin
586 | 				lcnt_next <= 6'd8;
587 | 				data_out_next <= {data_out[32:0], 7'bx};
588 | 			end
589 | 			else begin
590 | 				find1 <= 1'b0;
591 | 				//llcnt_next <= 3'bx;
592 | 				data_out_next <= {data_out[31:0], 8'bx};
593 | 			end
594 | 		end
595 | 		Lout_210_s2 : begin
596 | 			llcnt_next <= 3'd1;
597 | 			if (data_out[39]) begin
598 | 				lcnt_next <= 6'd7;
599 | 				data_out_next <= data_out;
600 | 			end
601 | 			else if (data_out[38]) begin
602 | 				lcnt_next <= 6'd6;
603 | 				data_out_next <= {data_out[38:0], 1'bx};
604 | 			end
605 | 			else if (data_out[37]) begin
606 | 				lcnt_next <= 6'd5;
607 | 				data_out_next <= {data_out[37:0], 2'bx};
608 | 			end
609 | 			else if (data_out[36]) begin
610 | 				lcnt_next <= 6'd4;
611 | 				data_out_next <= {data_out[36:0], 3'bx};
612 | 			end
613 | 			else if (data_out[35]) begin
614 | 				find1 <= 1'b0;
615 | 				lcnt_next <= 6'd3;
616 | 				data_out_next <= {data_out[35:0], 4'bx};
617 | 			end
618 | 			else if (data_out[34]) begin
619 | 				find1 <= 1'b0;
620 | 				lcnt_next <= 6'd2;
621 | 				data_out_next <= {data_out[34:0], 5'bx};
622 | 			end
623 | 			else if (data_out[33]) begin
624 | 				find1 <= 1'b0;
625 | 				lcnt_next <= 6'd1;
626 | 				data_out_next <= {data_out[33:0], 6'bx};
627 | 			end
628 | 			else begin
629 | 				find1 <= 1'b0;
630 | 				//llcnt_next <= 3'bx;
631 | 				lcnt_next <= 6'd1;
632 | 				data_out_next <= {data_out[33:0], 6'bx};
633 | 			end
634 | 		end
635 | 	endcase
636 | end
637 | 
638 | always @(posedge clk) begin
639 | 	case (state2)
640 | 		Idle_s2 : begin
641 | 			//if (output_is_begin) begin
642 | 				llcnt <= llcnt_next_b;
643 | 				lcnt <= lcnt_next_b;
644 | 				data_out <= data_out_next_b;
645 | 			//end
646 | 			ocnt <= 4'd1;
647 | 		end
648 | 		Lout_5_s2 : begin
649 | 			//if (find1) begin
650 | 				llcnt <= llcnt_next;
651 | 				lcnt <= lcnt_next;
652 | 			//end
653 | 			data_out <= data_out_next;
654 | 			ocnt <= ocnt_add_1;
655 | 		end
656 | 		Lout_4_s2, Lout_3_s2, Lout_210_s2 : begin
657 | 			//if (find1) begin
658 | 				llcnt <= llcnt_next;
659 | 				lcnt <= lcnt_next;
660 | 			//end
661 | 			data_out <= data_out_next;
662 | 		end
663 | 		Lout_s2 : begin
664 | 			llcnt <= llcnt_sub_1;
665 | 		end
666 | 		Dout_s2 : begin
667 | 			lcnt <= lcnt_sub_1;
668 | 			data_out <= {data_out[38:0], 1'b0};
669 | 			if (lcnt_is_end) data_out <= ans[ocnt];
670 | 		end
671 | 	endcase
672 | end
673 | 
674 | always @(*) begin
675 | 	output_is_end <= 1'b0;
676 | 	case (state2)
677 | 		Dout_s2 : begin
678 | 			if (lcnt_is_end && ocnt_is_end) output_is_end <= 1'b1;
679 | 		end
680 | 	endcase
681 | end
682 | 
683 | always @(posedge clk or negedge rst_n) begin
684 | 	if (!rst_n) begin
685 | 		out_valid <= 1'b0;
686 | 		out_value <= 1'b0;
687 | 	end
688 | 	else begin
689 | 		out_valid <= 1'b0;
690 | 		out_value <= 1'b0;
691 | 		case (state2)
692 | 			Idle_s2 : begin
693 | 				if (output_is_begin) begin
694 | 					out_valid <= 1'b1;
695 | 					out_value <= find1_b;
696 | 				end
697 | 			end
698 | 			Lout_5_s2, Lout_4_s2, Lout_3_s2, Lout_210_s2 : begin
699 | 				out_valid <= 1'b1;
700 | 				out_value <= find1;
701 | 			end
702 | 			Lout_s2 : begin
703 | 				out_valid <= 1'b1;
704 | 				out_value <= lcnt[llcnt];
705 | 			end
706 | 			Dout_s2 : begin
707 | 				out_valid <= 1'b1;
708 | 				out_value <= data_out[39];
709 | 			end
710 | 		endcase
711 | 	end
712 | end
713 | 
714 | endmodule
715 | 
716 | 


--------------------------------------------------------------------------------
/Lab04/NN.v:
--------------------------------------------------------------------------------
  1 | module NN(
  2 | 	// Input signals
  3 | 	clk,
  4 | 	rst_n,
  5 | 	in_valid_u,
  6 | 	in_valid_w,
  7 | 	in_valid_v,
  8 | 	in_valid_x,
  9 | 	weight_u,
 10 | 	weight_w,
 11 | 	weight_v,
 12 | 	data_x,
 13 | 	// Output signals
 14 | 	out_valid,
 15 | 	out
 16 | );
 17 | parameter inst_sig_width = 23;
 18 | parameter inst_exp_width = 8;
 19 | parameter inst_ieee_compliance = 0;
 20 | parameter inst_arch = 2;
 21 | 
 22 | input  clk, rst_n, in_valid_u, in_valid_w, in_valid_v, in_valid_x;
 23 | input [inst_sig_width+inst_exp_width:0] weight_u, weight_w, weight_v;
 24 | input [inst_sig_width+inst_exp_width:0] data_x;
 25 | output reg	out_valid;
 26 | output reg [inst_sig_width+inst_exp_width:0] out;
 27 | //---------------------------------------------------------------------
 28 | //
 29 | //---------------------------------------------------------------------
 30 | localparam sig_width = inst_sig_width;
 31 | localparam exp_width = inst_exp_width;
 32 | localparam ieee_compliance = inst_ieee_compliance;
 33 | localparam fp_width = sig_width + exp_width + 1;
 34 | localparam fp_one = {1'b0, {1'b0, {exp_width - 1{1'b1}}}, {sig_width{1'b0}}};
 35 | 
 36 | integer i, j;
 37 | 
 38 | wire in_valid = in_valid_u/* && in_valid_w && in_valid_v && in_valid_x*/;
 39 | 
 40 | reg [fp_width - 1:0] u [0:2][0:2];
 41 | reg [fp_width - 1:0] w [0:2][0:2];
 42 | reg [fp_width - 1:0] v [0:2][0:2];
 43 | reg [fp_width - 1:0] x [1:3][0:2];
 44 | reg [fp_width - 1:0] h [1:3][0:2];
 45 | 
 46 | reg [fp_width - 1:0] mult_a, mult_b;
 47 | wire [fp_width - 1:0] mult_z;
 48 | DW_fp_mult #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 49 | 	u_DW_fp_mult(.a(mult_a), .b(mult_b), .rnd(3'b000), .z(mult_z), .status());
 50 | reg [fp_width - 1:0] mac_c;
 51 | wire [fp_width - 1:0] mac_z;
 52 | DW_fp_add #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 53 | 	u_DW_fp_add(.a(mult_z), .b(mac_c), .z(mac_z), .status(), .rnd(3'b000));
 54 | 
 55 | reg [fp_width - 1:0] mult_a_2, mult_b_2;
 56 | wire [fp_width - 1:0] mult_z_2;
 57 | DW_fp_mult #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 58 | 	u_DW_fp_mult_2(.a(mult_a_2), .b(mult_b_2), .rnd(3'b000), .z(mult_z_2), .status());
 59 | reg [fp_width - 1:0] mac_c_2;
 60 | wire [fp_width - 1:0] mac_z_2;
 61 | DW_fp_add #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 62 | 	u_DW_fp_add_2(.a(mult_z_2), .b(mac_c_2), .z(mac_z_2), .status(), .rnd(3'b000));
 63 | 
 64 | reg [fp_width - 1:0] add_a, add_b;
 65 | wire [fp_width - 1:0] add_z;
 66 | DW_fp_add #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 67 | 	u_DW_fp_add_3(.a(add_a), .b(add_b), .z(add_z), .status(), .rnd(3'b000));
 68 | 
 69 | reg [fp_width - 1:0] sigmoid1_a;
 70 | wire [fp_width - 1:0] sigmoid1_z;
 71 | DW_fp_exp #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance), .arch(1))
 72 | 	u_DW_fp_exp_sigmoid(.a({~sigmoid1_a[fp_width - 1], sigmoid1_a[fp_width - 2:0]}), .z(sigmoid1_z), .status());
 73 | reg [fp_width - 1:0] sigmoid2_a;
 74 | wire [fp_width - 1:0] sigmoid2_z;
 75 | DW_fp_add #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance))
 76 | 	u_DW_fp_add_sigmoid(.a(fp_one), .b(sigmoid2_a), .z(sigmoid2_z), .status(), .rnd(3'b000));
 77 | reg [fp_width - 1:0] sigmoid3_a;
 78 | wire [fp_width - 1:0] sigmoid3_z;
 79 | DW_fp_recip #(.sig_width(sig_width), .exp_width(exp_width), .ieee_compliance(ieee_compliance), .faithful_round(1))
 80 | 	u_DW_fp_recip_sigmoid(.a(sigmoid3_a), .rnd(3'b000), .z(sigmoid3_z), .status());
 81 | // synopsys dc_script_begin
 82 | //
 83 | // set_implementation rtl u_DW_fp_mult
 84 | // set_implementation rtl u_DW_fp_add
 85 | //
 86 | // set_implementation rtl u_DW_fp_mult_2
 87 | // set_implementation rtl u_DW_fp_add_2
 88 | //
 89 | // set_implementation rtl u_DW_fp_add_3
 90 | //
 91 | // set_implementation rtl u_DW_fp_exp_sigmoid
 92 | // set_implementation rtl u_DW_fp_add_sigmoid
 93 | // set_implementation rtl u_DW_fp_recip_sigmoid
 94 | //
 95 | // synopsys dc_script_end
 96 | 
 97 | reg [5:0] state, nxt_state;
 98 | wire [5:0] state_add_1 = state + 6'd1;
 99 | localparam R1	= 6'd00;
100 | localparam R2	= 6'd25;
101 | localparam R3	= 6'd26;
102 | localparam R4	= 6'd27;
103 | localparam R5	= 6'd28;
104 | localparam R6	= 6'd29;
105 | localparam R7	= 6'd30;
106 | localparam R8	= 6'd31;
107 | localparam R9	= 6'd32;
108 | localparam S1	= 6'd33;
109 | localparam S2	= 6'd34;
110 | localparam S3	= 6'd35;
111 | localparam S4	= 6'd36;
112 | localparam S5	= 6'd37;
113 | localparam S6	= 6'd38;
114 | localparam S7	= 6'd39;
115 | localparam S8	= 6'd40;
116 | localparam S9	= 6'd41;
117 | localparam S10	= 6'd42;
118 | localparam S11	= 6'd43;
119 | localparam S12	= 6'd44;
120 | localparam S13	= 6'd45;
121 | localparam S14	= 6'd46;
122 | localparam S15	= 6'd47;
123 | localparam S16	= 6'd48;
124 | localparam S17	= 6'd49;
125 | localparam S18	= 6'd50;
126 | localparam S19	= 6'd51;
127 | localparam S20	= 6'd52;
128 | localparam S21	= 6'd53;
129 | localparam S22	= 6'd54;
130 | localparam O1	= 6'd55;
131 | localparam O2	= 6'd56;
132 | localparam O3	= 6'd57;
133 | localparam O4	= 6'd58;
134 | localparam O5	= 6'd59;
135 | localparam O6	= 6'd60;
136 | localparam O7	= 6'd61;
137 | localparam O8	= 6'd62;
138 | localparam O9	= 6'd63;
139 | 
140 | always @(*) begin
141 | 	nxt_state <= state_add_1;
142 | 	case (state)
143 | 		R1 :
144 | 			if (in_valid) nxt_state <= R2;
145 | 			else nxt_state <= R1;
146 | 		//R9 : nxt_state <= S1;
147 | 		//S22 : nxt_state <= O1;
148 | 		//O9 : nxt_state <= R1;
149 | 	endcase
150 | end
151 | 
152 | always @(posedge clk or negedge rst_n) begin
153 | 	if (!rst_n) state <= R1;
154 | 	else state <= nxt_state;
155 | end
156 | 
157 | always @(posedge clk) begin
158 | 	mult_a <= {fp_width{1'bx}};
159 | 	mult_b <= {fp_width{1'bx}};
160 | 	mac_c <= {fp_width{1'bx}};
161 | 	mult_a_2 <= {fp_width{1'bx}};
162 | 	mult_b_2 <= {fp_width{1'bx}};
163 | 	mac_c_2 <= {fp_width{1'bx}};
164 | 	add_a <= {fp_width{1'bx}};
165 | 	add_b <= {fp_width{1'bx}};
166 | 	sigmoid1_a <= {fp_width{1'bx}};
167 | 	sigmoid2_a <= {fp_width{1'bx}};
168 | 	sigmoid3_a <= {fp_width{1'bx}};
169 | 	case (state)
170 | 		R1 : begin
171 | 			mult_a <= weight_u;// u[0][0]
172 | 			mult_b <= data_x;// x[1][0]
173 | 		end
174 | 		R2 : begin
175 | 			mult_a <= weight_u;// u[0][1]
176 | 			mult_b <= data_x;// x[1][1]
177 | 			mac_c <= mult_z;
178 | 		end
179 | 		R3 : begin
180 | 			mult_a <= weight_u;// u[0][2]
181 | 			mult_b <= data_x;// x[1][2]
182 | 			mac_c <= mac_z;
183 | 		end
184 | 		R4 : begin
185 | 			mult_a <= weight_u;// u[1][0]
186 | 			mult_b <= x[1][0];
187 | 
188 | 			mult_a_2 <= u[0][0];
189 | 			mult_b_2 <= data_x;// x[2][0]
190 | 
191 | 			sigmoid1_a <= mac_z;// h[1][0]
192 | 		end
193 | 		R5 : begin
194 | 			mult_a <= weight_u;// u[1][1]
195 | 			mult_b <= x[1][1];
196 | 			mac_c <= mult_z;
197 | 
198 | 			mult_a_2 <= u[0][1];
199 | 			mult_b_2 <= data_x;// x[2][1]
200 | 			mac_c_2 <= mult_z_2;
201 | 
202 | 			sigmoid2_a <= sigmoid1_z;
203 | 		end
204 | 		R6 : begin
205 | 			mult_a <= weight_u;// u[1][2]
206 | 			mult_b <= x[1][2];
207 | 			mac_c <= mac_z;
208 | 
209 | 			mult_a_2 <= u[0][2];
210 | 			mult_b_2 <= data_x;// x[2][2]
211 | 			mac_c_2 <= mac_z_2;
212 | 
213 | 			sigmoid3_a <= sigmoid2_z;
214 | 		end
215 | 		R7 : begin
216 | 			mult_a <= weight_u;// u[2][0]
217 | 			mult_b <= x[1][0];
218 | 
219 | 			mult_a_2 <= w[0][0];
220 | 			mult_b_2 <= sigmoid3_z;// h[1][0]
221 | 
222 | 			sigmoid1_a <= mac_z;// h[1][1]
223 | 		end
224 | 		R8 : begin
225 | 			mult_a <= weight_u;// u[2][1]
226 | 			mult_b <= x[1][1];
227 | 			mac_c <= mult_z;
228 | 
229 | 			mult_a_2 <= w[1][0];
230 | 			mult_b_2 <= h[1][0];
231 | 
232 | 			sigmoid2_a <= sigmoid1_z;
233 | 		end
234 | 		R9 : begin
235 | 			mult_a <= weight_u;// u[2][2]
236 | 			mult_b <= x[1][2];
237 | 			mac_c <= mac_z;
238 | 
239 | 			mult_a_2 <= w[2][0];
240 | 			mult_b_2 <= h[1][0];
241 | 
242 | 			sigmoid3_a <= sigmoid2_z;
243 | 		end
244 | 		S1 : begin
245 | 			mult_a <= u[1][0];
246 | 			mult_b <= x[2][0];
247 | 
248 | 			mult_a_2 <= w[0][1];
249 | 			mult_b_2 <= sigmoid3_z;// h[1][1]
250 | 			mac_c_2 <= h[3][0];
251 | 
252 | 			sigmoid1_a <= mac_z;// h[1][2]
253 | 		end
254 | 		S2 : begin
255 | 			mult_a <= u[1][1];
256 | 			mult_b <= x[2][1];
257 | 			mac_c <= mult_z;
258 | 
259 | 			mult_a_2 <= w[1][1];
260 | 			mult_b_2 <= h[1][1];
261 | 			mac_c_2 <= h[3][1];
262 | 
263 | 			sigmoid2_a <= sigmoid1_z;
264 | 		end
265 | 		S3 : begin
266 | 			mult_a <= u[1][2];
267 | 			mult_b <= x[2][2];
268 | 			mac_c <= mac_z;
269 | 
270 | 			mult_a_2 <= w[2][1];
271 | 			mult_b_2 <= h[1][1];
272 | 			mac_c_2 <= h[3][2];
273 | 
274 | 			sigmoid3_a <= sigmoid2_z;
275 | 		end
276 | 		S4 : begin
277 | 			mult_a <= u[2][0];
278 | 			mult_b <= x[2][0];
279 | 
280 | 			mult_a_2 <= w[0][2];
281 | 			mult_b_2 <= sigmoid3_z;// h[1][2]
282 | 			mac_c_2 <= h[3][0];
283 | 		end
284 | 		S5 : begin
285 | 			mult_a <= u[2][1];
286 | 			mult_b <= x[2][1];
287 | 			mac_c <= mult_z;
288 | 
289 | 			mult_a_2 <= w[1][2];
290 | 			mult_b_2 <= h[1][2];
291 | 			mac_c_2 <= h[3][1];
292 | 
293 | 			add_a <= h[2][0];
294 | 			add_b <= mac_z_2;// h[3][0] (tmp[0])
295 | 		end
296 | 		S6 : begin
297 | 			mult_a <= u[2][2];
298 | 			mult_b <= x[2][2];
299 | 			mac_c <= mac_z;
300 | 
301 | 			mult_a_2 <= w[2][2];
302 | 			mult_b_2 <= h[1][2];
303 | 			mac_c_2 <= h[3][2];
304 | 
305 | 			add_a <= h[2][1];
306 | 			add_b <= mac_z_2;// h[3][1] (tmp[1])
307 | 
308 | 			sigmoid1_a <= add_z;// h[2][0]
309 | 		end
310 | 		S7 : begin
311 | 			mult_a <= u[0][0];
312 | 			mult_b <= x[3][0];
313 | 
314 | 			add_a <= mac_z;// h[2][2]
315 | 			add_b <= mac_z_2;// h[3][2] (tmp[2])
316 | 
317 | 			sigmoid2_a <= sigmoid1_z;
318 | 
319 | 			sigmoid1_a <= add_z;// h[2][1]
320 | 
321 | /*------------------------------------------------------------*/
322 | 			mult_a_2 <= v[0][0];
323 | 			mult_b_2 <= h[1][0];
324 | 		end
325 | 		S8 : begin
326 | 			mult_a <= u[0][1];
327 | 			mult_b <= x[3][1];
328 | 			mac_c <= mult_z;
329 | 
330 | 			sigmoid3_a <= sigmoid2_z;
331 | 
332 | 			sigmoid2_a <= sigmoid1_z;
333 | 
334 | 			sigmoid1_a <= add_z;// h[2][2]
335 | 
336 | /*------------------------------------------------------------*/
337 | 			mult_a_2 <= v[0][1];
338 | 			mult_b_2 <= h[1][1];
339 | 			mac_c_2 <= mult_z_2;
340 | 		end
341 | 		S9 : begin
342 | 			mult_a <= u[0][2];
343 | 			mult_b <= x[3][2];
344 | 			mac_c <= mac_z;
345 | 
346 | 			mult_a_2 <= w[0][0];
347 | 			mult_b_2 <= sigmoid3_z;// h[2][0]
348 | 
349 | 			sigmoid3_a <= sigmoid2_z;
350 | 
351 | 			sigmoid2_a <= sigmoid1_z;
352 | 		end
353 | 		S10 : begin
354 | 			mult_a <= u[1][0];
355 | 			mult_b <= x[3][0];
356 | 
357 | 			mult_a_2 <= w[0][1];
358 | 			mult_b_2 <= sigmoid3_z;// h[2][1]
359 | 			mac_c_2 <= mult_z_2;
360 | 
361 | 			sigmoid3_a <= sigmoid2_z;
362 | 		end
363 | 		S11 : begin
364 | 			mult_a <= u[1][1];
365 | 			mult_b <= x[3][1];
366 | 			mac_c <= mult_z;
367 | 
368 | 			mult_a_2 <= w[0][2];
369 | 			mult_b_2 <= sigmoid3_z;// h[2][2]
370 | 			mac_c_2 <= mac_z_2;
371 | 		end
372 | 		S12 : begin
373 | 			mult_a <= u[1][2];
374 | 			mult_b <= x[3][2];
375 | 			mac_c <= mac_z;
376 | 
377 | 			mult_a_2 <= w[1][0];
378 | 			mult_b_2 <= h[2][0];
379 | 
380 | 			add_a <= h[3][0];
381 | 			add_b <= mac_z_2;// h[3][0]
382 | 		end
383 | 		S13 : begin
384 | 			mult_a <= u[2][0];
385 | 			mult_b <= x[3][0];
386 | 
387 | 			mult_a_2 <= w[1][1];
388 | 			mult_b_2 <= h[2][1];
389 | 			mac_c_2 <= mult_z_2;
390 | 
391 | 			sigmoid1_a <= add_z;// h[3][0]
392 | 		end
393 | 		S14 : begin
394 | 			mult_a <= u[2][1];
395 | 			mult_b <= x[3][1];
396 | 			mac_c <= mult_z;
397 | 
398 | 			mult_a_2 <= w[1][2];
399 | 			mult_b_2 <= h[2][2];
400 | 			mac_c_2 <= mac_z_2;
401 | 
402 | 			sigmoid2_a <= sigmoid1_z;
403 | 		end
404 | 		S15 : begin
405 | 			mult_a <= u[2][2];
406 | 			mult_b <= x[3][2];
407 | 			mac_c <= mac_z;
408 | 
409 | 			mult_a_2 <= w[2][0];
410 | 			mult_b_2 <= h[2][0];
411 | 
412 | 			add_a <= h[3][1];
413 | 			add_b <= mac_z_2;// h[3][1]
414 | 
415 | 			sigmoid3_a <= sigmoid2_z;
416 | 		end
417 | 		S16 : begin
418 | 			mult_a_2 <= w[2][1];
419 | 			mult_b_2 <= h[2][1];
420 | 			mac_c_2 <= mult_z_2;
421 | 
422 | 			sigmoid1_a <= add_z;// h[3][1]
423 | 
424 | /*------------------------------------------------------------*/
425 | 			mult_a <= v[0][2];
426 | 			mult_b <= h[1][2];
427 | 			mac_c <= x[1][0];
428 | 		end
429 | 		S17 : begin
430 | 			mult_a_2 <= w[2][2];
431 | 			mult_b_2 <= h[2][2];
432 | 			mac_c_2 <= mac_z_2;
433 | 
434 | 			sigmoid2_a <= sigmoid1_z;
435 | 
436 | /*------------------------------------------------------------*/
437 | 			mult_a <= v[1][0];
438 | 			mult_b <= h[1][0];
439 | 		end
440 | 		S18 : begin
441 | 			add_a <= h[3][2];
442 | 			add_b <= mac_z_2;// h[3][2]
443 | 
444 | 			sigmoid3_a <= sigmoid2_z;
445 | 
446 | /*------------------------------------------------------------*/
447 | 			mult_a <= v[1][1];
448 | 			mult_b <= h[1][1];
449 | 			mac_c <= mult_z;
450 | 
451 | 			mult_a_2 <= v[2][0];
452 | 			mult_b_2 <= h[1][0];
453 | 		end
454 | 		S19 : begin
455 | 			sigmoid1_a <= add_z;// h[3][2]
456 | 
457 | /*------------------------------------------------------------*/
458 | 			mult_a <= v[1][2];
459 | 			mult_b <= h[1][2];
460 | 			mac_c <= mac_z;
461 | 
462 | 			mult_a_2 <= v[2][1];
463 | 			mult_b_2 <= h[1][1];
464 | 			mac_c_2 <= mult_z_2;
465 | 		end
466 | 		S20 : begin
467 | 			sigmoid2_a <= sigmoid1_z;
468 | 
469 | /*------------------------------------------------------------*/
470 | 			mult_a_2 <= v[2][2];
471 | 			mult_b_2 <= h[1][2];
472 | 			mac_c_2 <= mac_z_2;
473 | 
474 | 			mult_a <= v[0][0];
475 | 			mult_b <= h[2][0];
476 | 		end
477 | 		S21 : begin
478 | 			sigmoid3_a <= sigmoid2_z;
479 | 
480 | /*------------------------------------------------------------*/
481 | 			mult_a <= v[0][1];
482 | 			mult_b <= h[2][1];
483 | 			mac_c <= mult_z;
484 | 
485 | 			mult_a_2 <= v[1][0];
486 | 			mult_b_2 <= h[2][0];
487 | 		end
488 | 		S22 : begin
489 | 			mult_a <= v[0][2];
490 | 			mult_b <= h[2][2];
491 | 			mac_c <= mac_z;
492 | 
493 | 			mult_a_2 <= v[1][1];
494 | 			mult_b_2 <= h[2][1];
495 | 			mac_c_2 <= mult_z_2;
496 | 		end
497 | 		O1 : begin
498 | 			mult_a_2 <= v[1][2];
499 | 			mult_b_2 <= h[2][2];
500 | 			mac_c_2 <= mac_z_2;
501 | 
502 | 			mult_a <= v[2][0];
503 | 			mult_b <= h[2][0];
504 | 		end
505 | 		O2 : begin
506 | 			mult_a <= v[2][1];
507 | 			mult_b <= h[2][1];
508 | 			mac_c <= mult_z;
509 | 
510 | 			mult_a_2 <= v[0][0];
511 | 			mult_b_2 <= h[3][0];
512 | 		end
513 | 		O3 : begin
514 | 			mult_a <= v[2][2];
515 | 			mult_b <= h[2][2];
516 | 			mac_c <= mac_z;
517 | 
518 | 			mult_a_2 <= v[0][1];
519 | 			mult_b_2 <= h[3][1];
520 | 			mac_c_2 <= mult_z_2;
521 | 		end
522 | 		O4 : begin
523 | 			mult_a_2 <= v[0][2];
524 | 			mult_b_2 <= h[3][2];
525 | 			mac_c_2 <= mac_z_2;
526 | 
527 | 			mult_a <= v[1][0];
528 | 			mult_b <= h[3][0];
529 | 		end
530 | 		O5 : begin
531 | 			mult_a <= v[1][1];
532 | 			mult_b <= h[3][1];
533 | 			mac_c <= mult_z;
534 | 
535 | 			mult_a_2 <= v[2][0];
536 | 			mult_b_2 <= h[3][0];
537 | 		end
538 | 		O6 : begin
539 | 			mult_a <= v[1][2];
540 | 			mult_b <= h[3][2];
541 | 			mac_c <= mac_z;
542 | 
543 | 			mult_a_2 <= v[2][1];
544 | 			mult_b_2 <= h[3][1];
545 | 			mac_c_2 <= mult_z_2;
546 | 		end
547 | 		O7 : begin
548 | 			mult_a_2 <= v[2][2];
549 | 			mult_b_2 <= h[3][2];
550 | 			mac_c_2 <= mac_z_2;
551 | 		end
552 | 		O8 : begin end
553 | 		O9 : begin end
554 | 	endcase
555 | end
556 | 
557 | always @(posedge clk) begin
558 | 	case (state)
559 | 		R1 : begin
560 | 			u[0][0] <= weight_u;
561 | 			w[0][0] <= weight_w;
562 | 			v[0][0] <= weight_v;
563 | 			x[1][0] <= data_x;
564 | 		end
565 | 		R2 : begin
566 | 			u[0][1] <= weight_u;
567 | 			w[0][1] <= weight_w;
568 | 			v[0][1] <= weight_v;
569 | 			x[1][1] <= data_x;
570 | 		end
571 | 		R3 : begin
572 | 			u[0][2] <= weight_u;
573 | 			w[0][2] <= weight_w;
574 | 			v[0][2] <= weight_v;
575 | 			x[1][2] <= data_x;
576 | 		end
577 | 		R4 : begin
578 | 			u[1][0] <= weight_u;
579 | 			w[1][0] <= weight_w;
580 | 			v[1][0] <= weight_v;
581 | 			x[2][0] <= data_x;
582 | 
583 | 			h[1][0] <= mac_z; // u[0] * x1
584 | 		end
585 | 		R5 : begin
586 | 			u[1][1] <= weight_u;
587 | 			w[1][1] <= weight_w;
588 | 			v[1][1] <= weight_v;
589 | 			x[2][1] <= data_x;
590 | 		end
591 | 		R6 : begin
592 | 			u[1][2] <= weight_u;
593 | 			w[1][2] <= weight_w;
594 | 			v[1][2] <= weight_v;
595 | 			x[2][2] <= data_x;
596 | 		end
597 | 		R7 : begin
598 | 			u[2][0] <= weight_u;
599 | 			w[2][0] <= weight_w;
600 | 			v[2][0] <= weight_v;
601 | 			x[3][0] <= data_x;
602 | 
603 | 			h[1][1] <= mac_z; // u[1] * x1
604 | 
605 | 			h[2][0] <= mac_z_2; // u[0] * x2
606 | 
607 | 			h[1][0] <= sigmoid3_z; // h1[0]
608 | 		end
609 | 		R8 : begin
610 | 			u[2][1] <= weight_u;
611 | 			w[2][1] <= weight_w;
612 | 			v[2][1] <= weight_v;
613 | 			x[3][1] <= data_x;
614 | 
615 | 			h[3][0] <= mult_z_2;
616 | 		end
617 | 		R9 : begin
618 | 			u[2][2] <= weight_u;
619 | 			w[2][2] <= weight_w;
620 | 			v[2][2] <= weight_v;
621 | 			x[3][2] <= data_x;
622 | 
623 | 			h[3][1] <= mult_z_2;
624 | 		end
625 | 		S1 : begin
626 | 			h[1][2] <= mac_z; // u[2] * x1
627 | 
628 | 			h[3][2] <= mult_z_2;
629 | 
630 | 			h[1][1] <= sigmoid3_z; // h1[1]
631 | 		end
632 | 		S2 : begin
633 | 			h[3][0] <= mac_z_2;
634 | 		end
635 | 		S3 : begin
636 | 			h[3][1] <= mac_z_2;
637 | 		end
638 | 		S4 : begin
639 | 			h[2][1] <= mac_z; // u[1] * x2
640 | 
641 | 			h[3][2] <= mac_z_2;
642 | 
643 | 			h[1][2] <= sigmoid3_z; // h1[2]
644 | 		end
645 | 		S5 : begin end
646 | 		S6 : begin
647 | 			h[2][0] <= add_z; // u[0] * x2 + w[0] * h1
648 | 		end
649 | 		S7 : begin
650 | 			h[2][2] <= mac_z; // u[2] * x2
651 | 
652 | 			h[2][1] <= add_z; // u[1] * x2 + w[1] * h1
653 | 		end
654 | 		S8 : begin
655 | 			h[2][2] <= add_z; // u[2] * x2 + w[2] * h1
656 | 		end
657 | 		S9 : begin
658 | 			h[2][0] <= sigmoid3_z; // h2[0]
659 | 
660 | 
661 | /*------------------------------------------------------------*/
662 | 			x[1][0] <= mac_z_2; // y1[0] (2 / 3)
663 | 		end
664 | 		S10 : begin
665 | 			h[3][0] <= mac_z; // u[0] * x3
666 | 
667 | 			h[2][1] <= sigmoid3_z; // h2[1]
668 | 		end
669 | 		S11 : begin
670 | 			h[2][2] <= sigmoid3_z; // h2[2]
671 | 		end
672 | 		S12 : begin end
673 | 		S13 : begin
674 | 			h[3][1] <= mac_z; // u[1] * x3
675 | 
676 | 			h[3][0] <= add_z; // u[0] * x3 + w[0] * h2
677 | 		end
678 | 		S14 : begin end
679 | 		S15 : begin end
680 | 		S16 : begin
681 | 			h[3][2] <= mac_z; // u[2] * x3
682 | 
683 | 			h[3][1] <= add_z; // u[1] * x3 + w[1] * h2
684 | 
685 | 			h[3][0] <= sigmoid3_z; // h3[0]
686 | 		end
687 | 		S17 : begin
688 | 			x[1][0] <= mac_z; // y1[0]
689 | 		end
690 | 		S18 : begin end
691 | 		S19 : begin
692 | 			h[3][2] <= add_z; // u[2] * x3 + w[2] * h2
693 | 
694 | 			h[3][1] <= sigmoid3_z; // h3[1]
695 | 		end
696 | 		S20 : begin
697 | 			x[1][1] <= mac_z; // y1[1]
698 | 		end
699 | 		S21 : begin
700 | 			x[1][2] <= mac_z_2; // y1[2]
701 | 		end
702 | 		S22 : begin
703 | 			h[3][2] <= sigmoid3_z; // h3[2]
704 | 
705 | /*------------------------------------------------------------*/
706 | 		end
707 | 		O1 : begin
708 | 			x[2][0] <= mac_z; // y2[0]
709 | 		end
710 | 		O2 : begin
711 | 			x[2][1] <= mac_z_2; // y2[1]
712 | 		end
713 | 		O3 : begin end
714 | 		O4 : begin
715 | 			x[2][2] <= mac_z; // y2[2]
716 | 		end
717 | 		O5 : begin
718 | 			x[3][0] <= mac_z_2; // y3[0]
719 | 		end
720 | 		O6 : begin end
721 | 		O7 : begin
722 | 			x[3][1] <= mac_z; // y3[1]
723 | 		end
724 | 		O8 : begin
725 | 			x[3][2] <= mac_z_2; // y3[2]
726 | 		end
727 | 		O9 : begin end
728 | 	endcase
729 | end
730 | 
731 | always @(*) begin
732 | 	out_valid <= 1'b0;
733 | 	out <= {fp_width{1'b0}};
734 | 	case (state)
735 | 		O1 : begin
736 | 			out_valid <= 1'b1;
737 | 			if (!x[1][0][fp_width - 1]) out[fp_width - 2:0] <= x[1][0][fp_width - 2:0];
738 | 		end
739 | 		O2 : begin
740 | 			out_valid <= 1'b1;
741 | 			if (!x[1][1][fp_width - 1]) out[fp_width - 2:0] <= x[1][1][fp_width - 2:0];
742 | 		end
743 | 		O3 : begin
744 | 			out_valid <= 1'b1;
745 | 			if (!x[1][2][fp_width - 1]) out[fp_width - 2:0] <= x[1][2][fp_width - 2:0];
746 | 		end
747 | 		O4 : begin
748 | 			out_valid <= 1'b1;
749 | 			if (!x[2][0][fp_width - 1]) out[fp_width - 2:0] <= x[2][0][fp_width - 2:0];
750 | 		end
751 | 		O5 : begin
752 | 			out_valid <= 1'b1;
753 | 			if (!x[2][1][fp_width - 1]) out[fp_width - 2:0] <= x[2][1][fp_width - 2:0];
754 | 		end
755 | 		O6 : begin
756 | 			out_valid <= 1'b1;
757 | 			if (!x[2][2][fp_width - 1]) out[fp_width - 2:0] <= x[2][2][fp_width - 2:0];
758 | 		end
759 | 		O7 : begin
760 | 			out_valid <= 1'b1;
761 | 			if (!x[3][0][fp_width - 1]) out[fp_width - 2:0] <= x[3][0][fp_width - 2:0];
762 | 		end
763 | 		O8 : begin
764 | 			out_valid <= 1'b1;
765 | 			if (!x[3][1][fp_width - 1]) out[fp_width - 2:0] <= x[3][1][fp_width - 2:0];
766 | 		end
767 | 		O9 : begin
768 | 			out_valid <= 1'b1;
769 | 			if (!x[3][2][fp_width - 1]) out[fp_width - 2:0] <= x[3][2][fp_width - 2:0];
770 | 		end
771 | 	endcase
772 | end
773 | 
774 | endmodule
775 | 


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