├── .mxproject
├── Drivers
├── CMSIS
│ ├── Device
│ │ └── ST
│ │ │ └── STM32G0xx
│ │ │ └── Include
│ │ │ ├── stm32g030xx.h
│ │ │ ├── stm32g0xx.h
│ │ │ └── system_stm32g0xx.h
│ └── Include
│ │ ├── cmsis_armcc.h
│ │ ├── cmsis_armclang.h
│ │ ├── cmsis_compiler.h
│ │ ├── cmsis_gcc.h
│ │ ├── cmsis_iccarm.h
│ │ ├── cmsis_version.h
│ │ ├── core_armv8mbl.h
│ │ ├── core_armv8mml.h
│ │ ├── core_cm0.h
│ │ ├── core_cm0plus.h
│ │ ├── core_cm1.h
│ │ ├── core_cm23.h
│ │ ├── core_cm3.h
│ │ ├── core_cm33.h
│ │ ├── core_cm4.h
│ │ ├── core_cm7.h
│ │ ├── core_sc000.h
│ │ ├── core_sc300.h
│ │ ├── mpu_armv7.h
│ │ ├── mpu_armv8.h
│ │ └── tz_context.h
└── STM32G0xx_HAL_Driver
│ ├── Inc
│ ├── Legacy
│ │ └── stm32_hal_legacy.h
│ ├── stm32g0xx_hal.h
│ ├── stm32g0xx_hal_adc.h
│ ├── stm32g0xx_hal_adc_ex.h
│ ├── stm32g0xx_hal_cortex.h
│ ├── stm32g0xx_hal_def.h
│ ├── stm32g0xx_hal_dma.h
│ ├── stm32g0xx_hal_dma_ex.h
│ ├── stm32g0xx_hal_exti.h
│ ├── stm32g0xx_hal_flash.h
│ ├── stm32g0xx_hal_flash_ex.h
│ ├── stm32g0xx_hal_gpio.h
│ ├── stm32g0xx_hal_gpio_ex.h
│ ├── stm32g0xx_hal_iwdg.h
│ ├── stm32g0xx_hal_pwr.h
│ ├── stm32g0xx_hal_pwr_ex.h
│ ├── stm32g0xx_hal_rcc.h
│ ├── stm32g0xx_hal_rcc_ex.h
│ ├── stm32g0xx_hal_tim.h
│ ├── stm32g0xx_hal_tim_ex.h
│ ├── stm32g0xx_hal_uart.h
│ ├── stm32g0xx_hal_uart_ex.h
│ ├── stm32g0xx_ll_adc.h
│ ├── stm32g0xx_ll_rcc.h
│ └── stm32g0xx_ll_system.h
│ └── Src
│ ├── stm32g0xx_hal.c
│ ├── stm32g0xx_hal_adc.c
│ ├── stm32g0xx_hal_adc_ex.c
│ ├── stm32g0xx_hal_cortex.c
│ ├── stm32g0xx_hal_dma.c
│ ├── stm32g0xx_hal_dma_ex.c
│ ├── stm32g0xx_hal_exti.c
│ ├── stm32g0xx_hal_flash.c
│ ├── stm32g0xx_hal_flash_ex.c
│ ├── stm32g0xx_hal_gpio.c
│ ├── stm32g0xx_hal_iwdg.c
│ ├── stm32g0xx_hal_pwr.c
│ ├── stm32g0xx_hal_pwr_ex.c
│ ├── stm32g0xx_hal_rcc.c
│ ├── stm32g0xx_hal_rcc_ex.c
│ ├── stm32g0xx_hal_tim.c
│ ├── stm32g0xx_hal_tim_ex.c
│ ├── stm32g0xx_hal_uart.c
│ ├── stm32g0xx_hal_uart_ex.c
│ ├── stm32g0xx_ll_adc.c
│ └── stm32g0xx_ll_rcc.c
├── Inc
├── adc.h
├── dma.h
├── gpio.h
├── iwdg.h
├── main.h
├── stm32g0xx_hal_conf.h
├── stm32g0xx_it.h
├── tim.h
└── usart.h
├── MDK-ARM
├── RTE
│ └── _drone
│ │ └── RTE_Components.h
├── drone.uvprojx
└── startup_stm32g030xx.s
├── README.md
├── Src
├── adc.c
├── dma.c
├── gpio.c
├── iwdg.c
├── main.c
├── stm32g0xx_hal_msp.c
├── stm32g0xx_it.c
├── system_stm32g0xx.c
├── tim.c
└── usart.c
├── chip3d.png
├── drone.ioc
├── image
├── chip3d.png
├── control1.06.png
└── logo.jpg
└── user
├── adrc.c
├── adrc.h
├── control.c
├── imu.c
├── imu.h
├── mpu6050.c
├── mpu6050.h
├── mpuiic.c
├── mpuiic.h
├── mymath.c
├── mymath.h
├── protocol.c
├── protocol.h
├── task.c
└── task.h
/.mxproject:
--------------------------------------------------------------------------------
1 | [PreviousGenFiles]
2 | HeaderPath=E:/stm32/newprojects/drone/Inc
3 | HeaderFiles=gpio.h;tim.h;stm32g0xx_it.h;stm32g0xx_hal_conf.h;main.h;dma.h;usart.h;i2c.h;adc.h;iwdg.h;
4 | SourcePath=E:/stm32/newprojects/drone/Src
5 | SourceFiles=gpio.c;tim.c;stm32g0xx_it.c;stm32g0xx_hal_msp.c;main.c;dma.c;usart.c;i2c.c;adc.c;iwdg.c;
6 |
7 | [PreviousLibFiles]
8 | LibFiles=Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
9 |
10 | [PreviousUsedKeilFiles]
11 | SourceFiles=..\Src\main.c;..\Src\gpio.c;..\Src\adc.c;..\Src\dma.c;..\Src\iwdg.c;..\Src\tim.c;..\Src\usart.c;..\Src\stm32g0xx_it.c;..\Src\stm32g0xx_hal_msp.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;..\\Src/system_stm32g0xx.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;..\\Src/system_stm32g0xx.c;..\Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;;
12 | HeaderPath=..\Drivers\STM32G0xx_HAL_Driver\Inc;..\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32G0xx\Include;..\Drivers\CMSIS\Include;..\Inc;
13 | CDefines=USE_HAL_DRIVER;STM32G030xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
14 |
15 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
6 | *
7 | * The file is the unique include file that the application programmer
8 | * is using in the C source code, usually in main.c. This file contains:
9 | * - Configuration section that allows to select:
10 | * - The STM32G0xx device used in the target application
11 | * - To use or not the peripherals drivers in application code(i.e.
12 | * code will be based on direct access to peripherals registers
13 | * rather than drivers API), this option is controlled by
14 | * "#define USE_HAL_DRIVER"
15 | *
16 | ******************************************************************************
17 | * @attention
18 | *
19 | * © Copyright (c) 2018 STMicroelectronics.
20 | * All rights reserved.
21 | *
22 | * This software component is licensed by ST under BSD 3-Clause license,
23 | * the "License"; You may not use this file except in compliance with the
24 | * License. You may obtain a copy of the License at:
25 | * opensource.org/licenses/BSD-3-Clause
26 | *
27 | ******************************************************************************
28 | */
29 |
30 | /** @addtogroup CMSIS
31 | * @{
32 | */
33 |
34 | /** @addtogroup stm32g0xx
35 | * @{
36 | */
37 |
38 | #ifndef STM32G0xx_H
39 | #define STM32G0xx_H
40 |
41 | #ifdef __cplusplus
42 | extern "C" {
43 | #endif /* __cplusplus */
44 |
45 | /** @addtogroup Library_configuration_section
46 | * @{
47 | */
48 |
49 | /**
50 | * @brief STM32 Family
51 | */
52 | #if !defined (STM32G0)
53 | #define STM32G0
54 | #endif /* STM32G0 */
55 |
56 | /* Uncomment the line below according to the target STM32G0 device used in your
57 | application
58 | */
59 |
60 | #if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx)
61 | /* #define STM32G070xx */ /*!< STM32G070xx Devices */
62 | /* #define STM32G071xx */ /*!< STM32G071xx Devices */
63 | /* #define STM32G081xx */ /*!< STM32G081xx Devices */
64 | /* #define STM32G030xx */ /*!< STM32G030xx Devices */
65 | /* #define STM32G031xx */ /*!< STM32G031xx Devices */
66 | /* #define STM32G041xx */ /*!< STM32G041xx Devices */
67 | #endif
68 |
69 | /* Tip: To avoid modifying this file each time you need to switch between these
70 | devices, you can define the device in your toolchain compiler preprocessor.
71 | */
72 | #if !defined (USE_HAL_DRIVER)
73 | /**
74 | * @brief Comment the line below if you will not use the peripherals drivers.
75 | In this case, these drivers will not be included and the application code will
76 | be based on direct access to peripherals registers
77 | */
78 | /*#define USE_HAL_DRIVER */
79 | #endif /* USE_HAL_DRIVER */
80 |
81 | /**
82 | * @brief CMSIS Device version number $VERSION$
83 | */
84 | #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
85 | #define __STM32G0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
86 | #define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
87 | #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
88 | #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
89 | |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
90 | |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
91 | |(__STM32G0_CMSIS_VERSION_RC))
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /** @addtogroup Device_Included
98 | * @{
99 | */
100 |
101 | #if defined(STM32G071xx)
102 | #include "stm32g071xx.h"
103 | #elif defined(STM32G081xx)
104 | #include "stm32g081xx.h"
105 | #elif defined(STM32G070xx)
106 | #include "stm32g070xx.h"
107 | #elif defined(STM32G031xx)
108 | #include "stm32g031xx.h"
109 | #elif defined(STM32G041xx)
110 | #include "stm32g041xx.h"
111 | #elif defined(STM32G030xx)
112 | #include "stm32g030xx.h"
113 | #else
114 | #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
115 | #endif
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /** @addtogroup Exported_types
122 | * @{
123 | */
124 | typedef enum
125 | {
126 | RESET = 0,
127 | SET = !RESET
128 | } FlagStatus, ITStatus;
129 |
130 | typedef enum
131 | {
132 | DISABLE = 0,
133 | ENABLE = !DISABLE
134 | } FunctionalState;
135 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
136 |
137 | typedef enum
138 | {
139 | SUCCESS = 0,
140 | ERROR = !SUCCESS
141 | } ErrorStatus;
142 |
143 | /**
144 | * @}
145 | */
146 |
147 |
148 | /** @addtogroup Exported_macros
149 | * @{
150 | */
151 | #define SET_BIT(REG, BIT) ((REG) |= (BIT))
152 |
153 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
154 |
155 | #define READ_BIT(REG, BIT) ((REG) & (BIT))
156 |
157 | #define CLEAR_REG(REG) ((REG) = (0x0))
158 |
159 | #define WRITE_REG(REG, VAL) ((REG) = (VAL))
160 |
161 | #define READ_REG(REG) ((REG))
162 |
163 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
164 |
165 | /*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
166 | /**
167 | * @}
168 | */
169 |
170 | #if defined (USE_HAL_DRIVER)
171 | #include "stm32g0xx_hal.h"
172 | #endif /* USE_HAL_DRIVER */
173 |
174 | #ifdef __cplusplus
175 | }
176 | #endif /* __cplusplus */
177 |
178 | #endif /* STM32G0xx_H */
179 | /**
180 | * @}
181 | */
182 |
183 | /**
184 | * @}
185 | */
186 |
187 |
188 |
189 |
190 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
191 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32g0xx.h
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /** @addtogroup CMSIS
21 | * @{
22 | */
23 |
24 | /** @addtogroup stm32g0xx_system
25 | * @{
26 | */
27 |
28 | /**
29 | * @brief Define to prevent recursive inclusion
30 | */
31 | #ifndef SYSTEM_STM32G0XX_H
32 | #define SYSTEM_STM32G0XX_H
33 |
34 | #ifdef __cplusplus
35 | extern "C" {
36 | #endif
37 |
38 | /** @addtogroup STM32G0xx_System_Includes
39 | * @{
40 | */
41 |
42 | /**
43 | * @}
44 | */
45 |
46 |
47 | /** @addtogroup STM32G0xx_System_Exported_types
48 | * @{
49 | */
50 | /* This variable is updated in three ways:
51 | 1) by calling CMSIS function SystemCoreClockUpdate()
52 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
53 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
54 | Note: If you use this function to configure the system clock; then there
55 | is no need to call the 2 first functions listed above, since SystemCoreClock
56 | variable is updated automatically.
57 | */
58 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
59 |
60 | extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
61 | extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /** @addtogroup STM32G0xx_System_Exported_Constants
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /** @addtogroup STM32G0xx_System_Exported_Macros
76 | * @{
77 | */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /** @addtogroup STM32G0xx_System_Exported_Functions
84 | * @{
85 | */
86 |
87 | extern void SystemInit(void);
88 | extern void SystemCoreClockUpdate(void);
89 | /**
90 | * @}
91 | */
92 |
93 | #ifdef __cplusplus
94 | }
95 | #endif
96 |
97 | #endif /*SYSTEM_STM32G0XX_H */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | /**
104 | * @}
105 | */
106 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
107 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/cmsis_compiler.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_compiler.h
3 | * @brief CMSIS compiler generic header file
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #ifndef __CMSIS_COMPILER_H
26 | #define __CMSIS_COMPILER_H
27 |
28 | #include
29 |
30 | /*
31 | * Arm Compiler 4/5
32 | */
33 | #if defined ( __CC_ARM )
34 | #include "cmsis_armcc.h"
35 |
36 |
37 | /*
38 | * Arm Compiler 6 (armclang)
39 | */
40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41 | #include "cmsis_armclang.h"
42 |
43 |
44 | /*
45 | * GNU Compiler
46 | */
47 | #elif defined ( __GNUC__ )
48 | #include "cmsis_gcc.h"
49 |
50 |
51 | /*
52 | * IAR Compiler
53 | */
54 | #elif defined ( __ICCARM__ )
55 | #include
56 |
57 |
58 | /*
59 | * TI Arm Compiler
60 | */
61 | #elif defined ( __TI_ARM__ )
62 | #include
63 |
64 | #ifndef __ASM
65 | #define __ASM __asm
66 | #endif
67 | #ifndef __INLINE
68 | #define __INLINE inline
69 | #endif
70 | #ifndef __STATIC_INLINE
71 | #define __STATIC_INLINE static inline
72 | #endif
73 | #ifndef __STATIC_FORCEINLINE
74 | #define __STATIC_FORCEINLINE __STATIC_INLINE
75 | #endif
76 | #ifndef __NO_RETURN
77 | #define __NO_RETURN __attribute__((noreturn))
78 | #endif
79 | #ifndef __USED
80 | #define __USED __attribute__((used))
81 | #endif
82 | #ifndef __WEAK
83 | #define __WEAK __attribute__((weak))
84 | #endif
85 | #ifndef __PACKED
86 | #define __PACKED __attribute__((packed))
87 | #endif
88 | #ifndef __PACKED_STRUCT
89 | #define __PACKED_STRUCT struct __attribute__((packed))
90 | #endif
91 | #ifndef __PACKED_UNION
92 | #define __PACKED_UNION union __attribute__((packed))
93 | #endif
94 | #ifndef __UNALIGNED_UINT32 /* deprecated */
95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; };
96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
97 | #endif
98 | #ifndef __UNALIGNED_UINT16_WRITE
99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
101 | #endif
102 | #ifndef __UNALIGNED_UINT16_READ
103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
105 | #endif
106 | #ifndef __UNALIGNED_UINT32_WRITE
107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
109 | #endif
110 | #ifndef __UNALIGNED_UINT32_READ
111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
113 | #endif
114 | #ifndef __ALIGNED
115 | #define __ALIGNED(x) __attribute__((aligned(x)))
116 | #endif
117 | #ifndef __RESTRICT
118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
119 | #define __RESTRICT
120 | #endif
121 |
122 |
123 | /*
124 | * TASKING Compiler
125 | */
126 | #elif defined ( __TASKING__ )
127 | /*
128 | * The CMSIS functions have been implemented as intrinsics in the compiler.
129 | * Please use "carm -?i" to get an up to date list of all intrinsics,
130 | * Including the CMSIS ones.
131 | */
132 |
133 | #ifndef __ASM
134 | #define __ASM __asm
135 | #endif
136 | #ifndef __INLINE
137 | #define __INLINE inline
138 | #endif
139 | #ifndef __STATIC_INLINE
140 | #define __STATIC_INLINE static inline
141 | #endif
142 | #ifndef __STATIC_FORCEINLINE
143 | #define __STATIC_FORCEINLINE __STATIC_INLINE
144 | #endif
145 | #ifndef __NO_RETURN
146 | #define __NO_RETURN __attribute__((noreturn))
147 | #endif
148 | #ifndef __USED
149 | #define __USED __attribute__((used))
150 | #endif
151 | #ifndef __WEAK
152 | #define __WEAK __attribute__((weak))
153 | #endif
154 | #ifndef __PACKED
155 | #define __PACKED __packed__
156 | #endif
157 | #ifndef __PACKED_STRUCT
158 | #define __PACKED_STRUCT struct __packed__
159 | #endif
160 | #ifndef __PACKED_UNION
161 | #define __PACKED_UNION union __packed__
162 | #endif
163 | #ifndef __UNALIGNED_UINT32 /* deprecated */
164 | struct __packed__ T_UINT32 { uint32_t v; };
165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
166 | #endif
167 | #ifndef __UNALIGNED_UINT16_WRITE
168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
170 | #endif
171 | #ifndef __UNALIGNED_UINT16_READ
172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
174 | #endif
175 | #ifndef __UNALIGNED_UINT32_WRITE
176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
178 | #endif
179 | #ifndef __UNALIGNED_UINT32_READ
180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
182 | #endif
183 | #ifndef __ALIGNED
184 | #define __ALIGNED(x) __align(x)
185 | #endif
186 | #ifndef __RESTRICT
187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
188 | #define __RESTRICT
189 | #endif
190 |
191 |
192 | /*
193 | * COSMIC Compiler
194 | */
195 | #elif defined ( __CSMC__ )
196 | #include
197 |
198 | #ifndef __ASM
199 | #define __ASM _asm
200 | #endif
201 | #ifndef __INLINE
202 | #define __INLINE inline
203 | #endif
204 | #ifndef __STATIC_INLINE
205 | #define __STATIC_INLINE static inline
206 | #endif
207 | #ifndef __STATIC_FORCEINLINE
208 | #define __STATIC_FORCEINLINE __STATIC_INLINE
209 | #endif
210 | #ifndef __NO_RETURN
211 | // NO RETURN is automatically detected hence no warning here
212 | #define __NO_RETURN
213 | #endif
214 | #ifndef __USED
215 | #warning No compiler specific solution for __USED. __USED is ignored.
216 | #define __USED
217 | #endif
218 | #ifndef __WEAK
219 | #define __WEAK __weak
220 | #endif
221 | #ifndef __PACKED
222 | #define __PACKED @packed
223 | #endif
224 | #ifndef __PACKED_STRUCT
225 | #define __PACKED_STRUCT @packed struct
226 | #endif
227 | #ifndef __PACKED_UNION
228 | #define __PACKED_UNION @packed union
229 | #endif
230 | #ifndef __UNALIGNED_UINT32 /* deprecated */
231 | @packed struct T_UINT32 { uint32_t v; };
232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
233 | #endif
234 | #ifndef __UNALIGNED_UINT16_WRITE
235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
237 | #endif
238 | #ifndef __UNALIGNED_UINT16_READ
239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
241 | #endif
242 | #ifndef __UNALIGNED_UINT32_WRITE
243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
245 | #endif
246 | #ifndef __UNALIGNED_UINT32_READ
247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
249 | #endif
250 | #ifndef __ALIGNED
251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
252 | #define __ALIGNED(x)
253 | #endif
254 | #ifndef __RESTRICT
255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
256 | #define __RESTRICT
257 | #endif
258 |
259 |
260 | #else
261 | #error Unknown compiler.
262 | #endif
263 |
264 |
265 | #endif /* __CMSIS_COMPILER_H */
266 |
267 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/cmsis_version.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file cmsis_version.h
3 | * @brief CMSIS Core(M) Version definitions
4 | * @version V5.0.2
5 | * @date 19. April 2017
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef __CMSIS_VERSION_H
32 | #define __CMSIS_VERSION_H
33 |
34 | /* CMSIS Version definitions */
35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39 | #endif
40 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv7.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv7.h
3 | * @brief CMSIS MPU API for Armv7-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV7_H
32 | #define ARM_MPU_ARMV7_H
33 |
34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62 |
63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69 |
70 | /** MPU Region Base Address Register Value
71 | *
72 | * \param Region The region to be configured, number 0 to 15.
73 | * \param BaseAddress The base address for the region.
74 | */
75 | #define ARM_MPU_RBAR(Region, BaseAddress) \
76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 | ((Region) & MPU_RBAR_REGION_Msk) | \
78 | (MPU_RBAR_VALID_Msk))
79 |
80 | /**
81 | * MPU Memory Access Attributes
82 | *
83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 | * \param IsShareable Region is shareable between multiple bus masters.
85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 | */
88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93 |
94 | /**
95 | * MPU Region Attribute and Size Register Value
96 | *
97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 | * \param SubRegionDisable Sub-region disable field.
101 | * \param Size Region size of the region to be configured, for example 4K, 8K.
102 | */
103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107 |
108 | /**
109 | * MPU Region Attribute and Size Register Value
110 | *
111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 | * \param IsShareable Region is shareable between multiple bus masters.
115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 | * \param SubRegionDisable Sub-region disable field.
118 | * \param Size Region size of the region to be configured, for example 4K, 8K.
119 | */
120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122 |
123 | /**
124 | * MPU Memory Access Attribute for strongly ordered memory.
125 | * - TEX: 000b
126 | * - Shareable
127 | * - Non-cacheable
128 | * - Non-bufferable
129 | */
130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131 |
132 | /**
133 | * MPU Memory Access Attribute for device memory.
134 | * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 | * - Shareable or non-shareable
136 | * - Non-cacheable
137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 | *
139 | * \param IsShareable Configures the device memory as shareable or non-shareable.
140 | */
141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142 |
143 | /**
144 | * MPU Memory Access Attribute for normal memory.
145 | * - TEX: 1BBb (reflecting outer cacheability rules)
146 | * - Shareable or non-shareable
147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 | *
150 | * \param OuterCp Configures the outer cache policy.
151 | * \param InnerCp Configures the inner cache policy.
152 | * \param IsShareable Configures the memory as shareable or non-shareable.
153 | */
154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155 |
156 | /**
157 | * MPU Memory Access Attribute non-cacheable policy.
158 | */
159 | #define ARM_MPU_CACHEP_NOCACHE 0U
160 |
161 | /**
162 | * MPU Memory Access Attribute write-back, write and read allocate policy.
163 | */
164 | #define ARM_MPU_CACHEP_WB_WRA 1U
165 |
166 | /**
167 | * MPU Memory Access Attribute write-through, no write allocate policy.
168 | */
169 | #define ARM_MPU_CACHEP_WT_NWA 2U
170 |
171 | /**
172 | * MPU Memory Access Attribute write-back, no write allocate policy.
173 | */
174 | #define ARM_MPU_CACHEP_WB_NWA 3U
175 |
176 |
177 | /**
178 | * Struct for a single MPU Region
179 | */
180 | typedef struct {
181 | uint32_t RBAR; //!< The region base address register value (RBAR)
182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 | } ARM_MPU_Region_t;
184 |
185 | /** Enable the MPU.
186 | * \param MPU_Control Default access permissions for unconfigured regions.
187 | */
188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 | {
190 | __DSB();
191 | __ISB();
192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 | #endif
196 | }
197 |
198 | /** Disable the MPU.
199 | */
200 | __STATIC_INLINE void ARM_MPU_Disable(void)
201 | {
202 | __DSB();
203 | __ISB();
204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 | #endif
207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 | }
209 |
210 | /** Clear and disable the given MPU region.
211 | * \param rnr Region number to be cleared.
212 | */
213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 | {
215 | MPU->RNR = rnr;
216 | MPU->RASR = 0U;
217 | }
218 |
219 | /** Configure an MPU region.
220 | * \param rbar Value for RBAR register.
221 | * \param rsar Value for RSAR register.
222 | */
223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 | {
225 | MPU->RBAR = rbar;
226 | MPU->RASR = rasr;
227 | }
228 |
229 | /** Configure the given MPU region.
230 | * \param rnr Region number to be configured.
231 | * \param rbar Value for RBAR register.
232 | * \param rsar Value for RSAR register.
233 | */
234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 | {
236 | MPU->RNR = rnr;
237 | MPU->RBAR = rbar;
238 | MPU->RASR = rasr;
239 | }
240 |
241 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 | * \param dst Destination data is copied to.
243 | * \param src Source data is copied from.
244 | * \param len Amount of data words to be copied.
245 | */
246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 | {
248 | uint32_t i;
249 | for (i = 0U; i < len; ++i)
250 | {
251 | dst[i] = src[i];
252 | }
253 | }
254 |
255 | /** Load the given number of MPU regions from a table.
256 | * \param table Pointer to the MPU configuration table.
257 | * \param cnt Amount of regions to be configured.
258 | */
259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 | {
261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 | while (cnt > MPU_TYPE_RALIASES) {
263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 | table += MPU_TYPE_RALIASES;
265 | cnt -= MPU_TYPE_RALIASES;
266 | }
267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 | }
269 |
270 | #endif
271 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/mpu_armv8.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file mpu_armv8.h
3 | * @brief CMSIS MPU API for Armv8-M MPU
4 | * @version V5.0.4
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef ARM_MPU_ARMV8_H
32 | #define ARM_MPU_ARMV8_H
33 |
34 | /** \brief Attribute for device memory (outer only) */
35 | #define ARM_MPU_ATTR_DEVICE ( 0U )
36 |
37 | /** \brief Attribute for non-cacheable, normal memory */
38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39 |
40 | /** \brief Attribute for normal memory (outer and inner)
41 | * \param NT Non-Transient: Set to 1 for non-transient data.
42 | * \param WB Write-Back: Set to 1 to use write-back update policy.
43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45 | */
46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
48 |
49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51 |
52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54 |
55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57 |
58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60 |
61 | /** \brief Memory Attribute
62 | * \param O Outer memory attributes
63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64 | */
65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
66 |
67 | /** \brief Normal memory non-shareable */
68 | #define ARM_MPU_SH_NON (0U)
69 |
70 | /** \brief Normal memory outer shareable */
71 | #define ARM_MPU_SH_OUTER (2U)
72 |
73 | /** \brief Normal memory inner shareable */
74 | #define ARM_MPU_SH_INNER (3U)
75 |
76 | /** \brief Memory access permissions
77 | * \param RO Read-Only: Set to 1 for read-only memory.
78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79 | */
80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
81 |
82 | /** \brief Region Base Address Register value
83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84 | * \param SH Defines the Shareability domain for this memory region.
85 | * \param RO Read-Only: Set to 1 for a read-only memory region.
86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
88 | */
89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90 | ((BASE & MPU_RBAR_BASE_Msk) | \
91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94 |
95 | /** \brief Region Limit Address Register value
96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97 | * \param IDX The attribute index to be associated with this memory region.
98 | */
99 | #define ARM_MPU_RLAR(LIMIT, IDX) \
100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102 | (MPU_RLAR_EN_Msk))
103 |
104 | /**
105 | * Struct for a single MPU Region
106 | */
107 | typedef struct {
108 | uint32_t RBAR; /*!< Region Base Address Register value */
109 | uint32_t RLAR; /*!< Region Limit Address Register value */
110 | } ARM_MPU_Region_t;
111 |
112 | /** Enable the MPU.
113 | * \param MPU_Control Default access permissions for unconfigured regions.
114 | */
115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
116 | {
117 | __DSB();
118 | __ISB();
119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
122 | #endif
123 | }
124 |
125 | /** Disable the MPU.
126 | */
127 | __STATIC_INLINE void ARM_MPU_Disable(void)
128 | {
129 | __DSB();
130 | __ISB();
131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
133 | #endif
134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
135 | }
136 |
137 | #ifdef MPU_NS
138 | /** Enable the Non-secure MPU.
139 | * \param MPU_Control Default access permissions for unconfigured regions.
140 | */
141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
142 | {
143 | __DSB();
144 | __ISB();
145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
148 | #endif
149 | }
150 |
151 | /** Disable the Non-secure MPU.
152 | */
153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void)
154 | {
155 | __DSB();
156 | __ISB();
157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk
158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
159 | #endif
160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
161 | }
162 | #endif
163 |
164 | /** Set the memory attribute encoding to the given MPU.
165 | * \param mpu Pointer to the MPU to be configured.
166 | * \param idx The attribute index to be set [0-7]
167 | * \param attr The attribute value to be set.
168 | */
169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
170 | {
171 | const uint8_t reg = idx / 4U;
172 | const uint32_t pos = ((idx % 4U) * 8U);
173 | const uint32_t mask = 0xFFU << pos;
174 |
175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
176 | return; // invalid index
177 | }
178 |
179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
180 | }
181 |
182 | /** Set the memory attribute encoding.
183 | * \param idx The attribute index to be set [0-7]
184 | * \param attr The attribute value to be set.
185 | */
186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
187 | {
188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr);
189 | }
190 |
191 | #ifdef MPU_NS
192 | /** Set the memory attribute encoding to the Non-secure MPU.
193 | * \param idx The attribute index to be set [0-7]
194 | * \param attr The attribute value to be set.
195 | */
196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
197 | {
198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
199 | }
200 | #endif
201 |
202 | /** Clear and disable the given MPU region of the given MPU.
203 | * \param mpu Pointer to MPU to be used.
204 | * \param rnr Region number to be cleared.
205 | */
206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
207 | {
208 | mpu->RNR = rnr;
209 | mpu->RLAR = 0U;
210 | }
211 |
212 | /** Clear and disable the given MPU region.
213 | * \param rnr Region number to be cleared.
214 | */
215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
216 | {
217 | ARM_MPU_ClrRegionEx(MPU, rnr);
218 | }
219 |
220 | #ifdef MPU_NS
221 | /** Clear and disable the given Non-secure MPU region.
222 | * \param rnr Region number to be cleared.
223 | */
224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
225 | {
226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr);
227 | }
228 | #endif
229 |
230 | /** Configure the given MPU region of the given MPU.
231 | * \param mpu Pointer to MPU to be used.
232 | * \param rnr Region number to be configured.
233 | * \param rbar Value for RBAR register.
234 | * \param rlar Value for RLAR register.
235 | */
236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
237 | {
238 | mpu->RNR = rnr;
239 | mpu->RBAR = rbar;
240 | mpu->RLAR = rlar;
241 | }
242 |
243 | /** Configure the given MPU region.
244 | * \param rnr Region number to be configured.
245 | * \param rbar Value for RBAR register.
246 | * \param rlar Value for RLAR register.
247 | */
248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
249 | {
250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
251 | }
252 |
253 | #ifdef MPU_NS
254 | /** Configure the given Non-secure MPU region.
255 | * \param rnr Region number to be configured.
256 | * \param rbar Value for RBAR register.
257 | * \param rlar Value for RLAR register.
258 | */
259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
260 | {
261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
262 | }
263 | #endif
264 |
265 | /** Memcopy with strictly ordered memory access, e.g. for register targets.
266 | * \param dst Destination data is copied to.
267 | * \param src Source data is copied from.
268 | * \param len Amount of data words to be copied.
269 | */
270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
271 | {
272 | uint32_t i;
273 | for (i = 0U; i < len; ++i)
274 | {
275 | dst[i] = src[i];
276 | }
277 | }
278 |
279 | /** Load the given number of MPU regions from a table to the given MPU.
280 | * \param mpu Pointer to the MPU registers to be used.
281 | * \param rnr First region number to be configured.
282 | * \param table Pointer to the MPU configuration table.
283 | * \param cnt Amount of regions to be configured.
284 | */
285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
286 | {
287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
288 | if (cnt == 1U) {
289 | mpu->RNR = rnr;
290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
291 | } else {
292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
294 |
295 | mpu->RNR = rnrBase;
296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
299 | table += c;
300 | cnt -= c;
301 | rnrOffset = 0U;
302 | rnrBase += MPU_TYPE_RALIASES;
303 | mpu->RNR = rnrBase;
304 | }
305 |
306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
307 | }
308 | }
309 |
310 | /** Load the given number of MPU regions from a table.
311 | * \param rnr First region number to be configured.
312 | * \param table Pointer to the MPU configuration table.
313 | * \param cnt Amount of regions to be configured.
314 | */
315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
316 | {
317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt);
318 | }
319 |
320 | #ifdef MPU_NS
321 | /** Load the given number of MPU regions from a table to the Non-secure MPU.
322 | * \param rnr First region number to be configured.
323 | * \param table Pointer to the MPU configuration table.
324 | * \param cnt Amount of regions to be configured.
325 | */
326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
327 | {
328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
329 | }
330 | #endif
331 |
332 | #endif
333 |
334 |
--------------------------------------------------------------------------------
/Drivers/CMSIS/Include/tz_context.h:
--------------------------------------------------------------------------------
1 | /******************************************************************************
2 | * @file tz_context.h
3 | * @brief Context Management for Armv8-M TrustZone
4 | * @version V1.0.1
5 | * @date 10. January 2018
6 | ******************************************************************************/
7 | /*
8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 | *
10 | * SPDX-License-Identifier: Apache-2.0
11 | *
12 | * Licensed under the Apache License, Version 2.0 (the License); you may
13 | * not use this file except in compliance with the License.
14 | * You may obtain a copy of the License at
15 | *
16 | * www.apache.org/licenses/LICENSE-2.0
17 | *
18 | * Unless required by applicable law or agreed to in writing, software
19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 | * See the License for the specific language governing permissions and
22 | * limitations under the License.
23 | */
24 |
25 | #if defined ( __ICCARM__ )
26 | #pragma system_include /* treat file as system include file for MISRA check */
27 | #elif defined (__clang__)
28 | #pragma clang system_header /* treat file as system include file */
29 | #endif
30 |
31 | #ifndef TZ_CONTEXT_H
32 | #define TZ_CONTEXT_H
33 |
34 | #include
35 |
36 | #ifndef TZ_MODULEID_T
37 | #define TZ_MODULEID_T
38 | /// \details Data type that identifies secure software modules called by a process.
39 | typedef uint32_t TZ_ModuleId_t;
40 | #endif
41 |
42 | /// \details TZ Memory ID identifies an allocated memory slot.
43 | typedef uint32_t TZ_MemoryId_t;
44 |
45 | /// Initialize secure context memory system
46 | /// \return execution status (1: success, 0: error)
47 | uint32_t TZ_InitContextSystem_S (void);
48 |
49 | /// Allocate context memory for calling secure software modules in TrustZone
50 | /// \param[in] module identifies software modules called from non-secure mode
51 | /// \return value != 0 id TrustZone memory slot identifier
52 | /// \return value 0 no memory available or internal error
53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54 |
55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56 | /// \param[in] id TrustZone memory slot identifier
57 | /// \return execution status (1: success, 0: error)
58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59 |
60 | /// Load secure context (called on RTOS thread context switch)
61 | /// \param[in] id TrustZone memory slot identifier
62 | /// \return execution status (1: success, 0: error)
63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64 |
65 | /// Store secure context (called on RTOS thread context switch)
66 | /// \param[in] id TrustZone memory slot identifier
67 | /// \return execution status (1: success, 0: error)
68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69 |
70 | #endif // TZ_CONTEXT_H
71 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_adc_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of ADC HAL extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_ADC_EX_H
22 | #define STM32G0xx_HAL_ADC_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup ADCEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @}
46 | */
47 |
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
51 | * @{
52 | */
53 |
54 | /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
55 | * @{
56 | */
57 | #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
58 | /**
59 | * @}
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /* Exported macros -----------------------------------------------------------*/
67 |
68 | /* Private macros ------------------------------------------------------------*/
69 |
70 | /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
71 | * @{
72 | */
73 | /* Macro reserved for internal HAL driver usage, not intended to be used in */
74 | /* code of final user. */
75 |
76 | /**
77 | * @brief Check whether or not ADC is independent.
78 | * @param __HANDLE__ ADC handle.
79 | * @note When multimode feature is not available, the macro always returns SET.
80 | * @retval SET (ADC is independent) or RESET (ADC is not).
81 | */
82 | #define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
83 |
84 |
85 | /**
86 | * @brief Calibration factor size verification (7 bits maximum).
87 | * @param __CALIBRATION_FACTOR__ Calibration factor value.
88 | * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
89 | */
90 | #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
91 |
92 | /**
93 | * @brief Verify the ADC oversampling ratio.
94 | * @param __RATIO__ programmed ADC oversampling ratio.
95 | * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
96 | */
97 | #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
98 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
99 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
100 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
101 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
102 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
103 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
104 | ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
105 |
106 | /**
107 | * @brief Verify the ADC oversampling shift.
108 | * @param __SHIFT__ programmed ADC oversampling shift.
109 | * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
110 | */
111 | #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
112 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
113 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
114 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
115 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
116 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
117 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
118 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
119 | ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
120 |
121 | /**
122 | * @brief Verify the ADC oversampling triggered mode.
123 | * @param __MODE__ programmed ADC oversampling triggered mode.
124 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
125 | */
126 | #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
127 | ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
128 |
129 |
130 | /**
131 | * @}
132 | */
133 |
134 |
135 | /* Exported functions --------------------------------------------------------*/
136 | /** @addtogroup ADCEx_Exported_Functions
137 | * @{
138 | */
139 |
140 | /** @addtogroup ADCEx_Exported_Functions_Group1
141 | * @{
142 | */
143 | /* IO operation functions *****************************************************/
144 |
145 | /* ADC calibration */
146 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
147 | uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc);
148 | HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t CalibrationFactor);
149 |
150 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
151 | void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
152 | void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
153 | void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
154 | void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef* hadc);
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /** @addtogroup ADCEx_Exported_Functions_Group2
161 | * @{
162 | */
163 | /* Peripheral Control functions ***********************************************/
164 | HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
165 |
166 | /**
167 | * @}
168 | */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /**
175 | * @}
176 | */
177 |
178 | /**
179 | * @}
180 | */
181 |
182 | #ifdef __cplusplus
183 | }
184 | #endif
185 |
186 | #endif /* STM32G0xx_HAL_ADC_EX_H */
187 |
188 |
189 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
190 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_def.h
4 | * @author MCD Application Team
5 | * @brief This file contains HAL common defines, enumeration, macros and
6 | * structures definitions.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2018 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef STM32G0xx_HAL_DEF
23 | #define STM32G0xx_HAL_DEF
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Includes ------------------------------------------------------------------*/
30 | #include "stm32g0xx.h"
31 | #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
32 | #include
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 |
36 | /**
37 | * @brief HAL Status structures definition
38 | */
39 | typedef enum
40 | {
41 | HAL_OK = 0x00U,
42 | HAL_ERROR = 0x01U,
43 | HAL_BUSY = 0x02U,
44 | HAL_TIMEOUT = 0x03U
45 | } HAL_StatusTypeDef;
46 |
47 | /**
48 | * @brief HAL Lock structures definition
49 | */
50 | typedef enum
51 | {
52 | HAL_UNLOCKED = 0x00U,
53 | HAL_LOCKED = 0x01U
54 | } HAL_LockTypeDef;
55 |
56 | /* Exported macros -----------------------------------------------------------*/
57 |
58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
59 |
60 | #define HAL_MAX_DELAY 0xFFFFFFFFU
61 |
62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
64 |
65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
66 | do{ \
67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \
69 | } while(0U)
70 |
71 | /** @brief Reset the Handles State field.
72 | * @param __HANDLE__ specifies the Peripheral Handle.
73 | * @note This macro can be used for the following purpose:
74 | * - When the Handle is declared as local variable; before passing it as parameter
75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
76 | * to set to 0 the Handles "State" field.
77 | * Otherwise, "State" field may have any random value and the first time the function
78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed
79 | * (i.e. HAL_PPP_MspInit() will not be executed).
80 | * - When there is a need to reconfigure the low level hardware: instead of calling
81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
82 | * In this later function, when the Handles "State" field is set to 0, it will execute the function
83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware.
84 | * @retval None
85 | */
86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
87 |
88 | #if (USE_RTOS == 1U)
89 | /* Reserved for future use */
90 | #error " USE_RTOS should be 0 in the current HAL release "
91 | #else
92 | #define __HAL_LOCK(__HANDLE__) \
93 | do{ \
94 | if((__HANDLE__)->Lock == HAL_LOCKED) \
95 | { \
96 | return HAL_BUSY; \
97 | } \
98 | else \
99 | { \
100 | (__HANDLE__)->Lock = HAL_LOCKED; \
101 | } \
102 | }while (0U)
103 |
104 | #define __HAL_UNLOCK(__HANDLE__) \
105 | do{ \
106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \
107 | }while (0U)
108 | #endif /* USE_RTOS */
109 |
110 | #if defined ( __GNUC__ )
111 | #ifndef __weak
112 | #define __weak __attribute__((weak))
113 | #endif /* __weak */
114 | #ifndef __packed
115 | #define __packed __attribute__((__packed__))
116 | #endif /* __packed */
117 | #endif /* __GNUC__ */
118 |
119 |
120 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
121 | /* GNU Compiler */
122 | #if defined (__GNUC__)
123 | #ifndef __ALIGN_END
124 | #define __ALIGN_END __attribute__ ((aligned (4U)))
125 | #endif /* __ALIGN_END */
126 | #ifndef __ALIGN_BEGIN
127 | #define __ALIGN_BEGIN
128 | #endif /* __ALIGN_BEGIN */
129 | #else
130 | #ifndef __ALIGN_END
131 | #define __ALIGN_END
132 | #endif /* __ALIGN_END */
133 | #ifndef __ALIGN_BEGIN
134 | /* ARM Compiler */
135 | #if defined (__CC_ARM)
136 | #define __ALIGN_BEGIN __align(4U)
137 | /* IAR Compiler */
138 | #elif defined (__ICCARM__)
139 | #define __ALIGN_BEGIN
140 | #endif /* __CC_ARM */
141 | #endif /* __ALIGN_BEGIN */
142 | #endif /* __GNUC__ */
143 |
144 | /**
145 | * @brief __RAM_FUNC definition
146 | */
147 | #if defined ( __CC_ARM )
148 | /* ARM Compiler
149 | ------------
150 | RAM functions are defined using the toolchain options.
151 | Functions that are executed in RAM should reside in a separate source module.
152 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
153 | area of a module to a memory space in physical RAM.
154 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
155 | dialog.
156 | */
157 | #define __RAM_FUNC
158 |
159 | #elif defined ( __ICCARM__ )
160 | /* ICCARM Compiler
161 | ---------------
162 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
163 | */
164 | #define __RAM_FUNC __ramfunc
165 |
166 | #elif defined ( __GNUC__ )
167 | /* GNU Compiler
168 | ------------
169 | RAM functions are defined using a specific toolchain attribute
170 | "__attribute__((section(".RamFunc")))".
171 | */
172 | #define __RAM_FUNC __attribute__((section(".RamFunc")))
173 |
174 | #endif
175 |
176 | /**
177 | * @brief __NOINLINE definition
178 | */
179 | #if defined ( __CC_ARM ) || defined ( __GNUC__ )
180 | /* ARM & GNUCompiler
181 | ----------------
182 | */
183 | #define __NOINLINE __attribute__ ( (noinline) )
184 |
185 | #elif defined ( __ICCARM__ )
186 | /* ICCARM Compiler
187 | ---------------
188 | */
189 | #define __NOINLINE _Pragma("optimize = no_inline")
190 |
191 | #endif
192 |
193 |
194 | #ifdef __cplusplus
195 | }
196 | #endif
197 |
198 | #endif /* STM32G0xx_HAL_DEF */
199 |
200 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
201 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_flash_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_FLASH_EX_H
22 | #define STM32G0xx_HAL_FLASH_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup FLASHEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
42 | * @{
43 | */
44 | /** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
45 | * @{
46 | */
47 | #define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
48 | #define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
49 | /**
50 | * @}
51 | */
52 | /**
53 | * @}
54 | */
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 | /* Exported functions --------------------------------------------------------*/
58 | /** @addtogroup FLASHEx_Exported_Functions
59 | * @{
60 | */
61 |
62 | /* Extended Program operation functions *************************************/
63 | /** @addtogroup FLASHEx_Exported_Functions_Group1
64 | * @{
65 | */
66 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
67 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
68 | void HAL_FLASHEx_EnableDebugger(void);
69 | void HAL_FLASHEx_DisableDebugger(void);
70 | uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
71 | void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
72 | #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
73 | void HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
74 | #endif
75 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
76 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
77 | /**
78 | * @}
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /* Private macros ------------------------------------------------------------*/
86 | /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
87 | * @{
88 | */
89 | #define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */
90 | #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */
91 | /**
92 | * @}
93 | */
94 |
95 |
96 | /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
97 | * @{
98 | */
99 | #define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
100 | void FLASH_PageErase(uint32_t Page);
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /**
110 | * @}
111 | */
112 |
113 | #ifdef __cplusplus
114 | }
115 | #endif
116 |
117 | #endif /* STM32G0xx_HAL_FLASH_EX_H */
118 |
119 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
120 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_iwdg.h
4 | * @author MCD Application Team
5 | * @brief Header file of IWDG HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_IWDG_H
22 | #define STM32G0xx_HAL_IWDG_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup IWDG IWDG
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup IWDG_Exported_Types IWDG Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief IWDG Init structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
50 | This parameter can be a value of @ref IWDG_Prescaler */
51 |
52 | uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
53 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
54 |
55 | uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
56 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
57 |
58 | } IWDG_InitTypeDef;
59 |
60 | /**
61 | * @brief IWDG Handle Structure definition
62 | */
63 | typedef struct
64 | {
65 | IWDG_TypeDef *Instance; /*!< Register base address */
66 |
67 | IWDG_InitTypeDef Init; /*!< IWDG required parameters */
68 | } IWDG_HandleTypeDef;
69 |
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /* Exported constants --------------------------------------------------------*/
76 | /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
77 | * @{
78 | */
79 |
80 | /** @defgroup IWDG_Prescaler IWDG Prescaler
81 | * @{
82 | */
83 | #define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
84 | #define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
85 | #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
86 | #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
87 | #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
88 | #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
89 | #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /** @defgroup IWDG_Window_option IWDG Window option
96 | * @{
97 | */
98 | #define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
99 | /**
100 | * @}
101 | */
102 |
103 |
104 | /**
105 | * @}
106 | */
107 |
108 | /* Exported macros -----------------------------------------------------------*/
109 | /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
110 | * @{
111 | */
112 |
113 | /**
114 | * @brief Enable the IWDG peripheral.
115 | * @param __HANDLE__ IWDG handle
116 | * @retval None
117 | */
118 | #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
119 |
120 | /**
121 | * @brief Reload IWDG counter with value defined in the reload register
122 | * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
123 | * @param __HANDLE__ IWDG handle
124 | * @retval None
125 | */
126 | #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
127 |
128 | /**
129 | * @}
130 | */
131 |
132 | /* Exported functions --------------------------------------------------------*/
133 | /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
134 | * @{
135 | */
136 |
137 | /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
138 | * @{
139 | */
140 | /* Initialization/Start functions ********************************************/
141 | HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
147 | * @{
148 | */
149 | /* I/O operation functions ****************************************************/
150 | HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
151 | /**
152 | * @}
153 | */
154 |
155 | /**
156 | * @}
157 | */
158 |
159 | /* Private constants ---------------------------------------------------------*/
160 | /** @defgroup IWDG_Private_Constants IWDG Private Constants
161 | * @{
162 | */
163 |
164 | /**
165 | * @brief IWDG Key Register BitMask
166 | */
167 | #define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
168 | #define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
169 | #define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
170 | #define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
171 |
172 | /**
173 | * @}
174 | */
175 |
176 | /* Private macros ------------------------------------------------------------*/
177 | /** @defgroup IWDG_Private_Macros IWDG Private Macros
178 | * @{
179 | */
180 |
181 | /**
182 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
183 | * @param __HANDLE__ IWDG handle
184 | * @retval None
185 | */
186 | #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
187 |
188 | /**
189 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
190 | * @param __HANDLE__ IWDG handle
191 | * @retval None
192 | */
193 | #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
194 |
195 | /**
196 | * @brief Check IWDG prescaler value.
197 | * @param __PRESCALER__ IWDG prescaler value
198 | * @retval None
199 | */
200 | #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
201 | ((__PRESCALER__) == IWDG_PRESCALER_8) || \
202 | ((__PRESCALER__) == IWDG_PRESCALER_16) || \
203 | ((__PRESCALER__) == IWDG_PRESCALER_32) || \
204 | ((__PRESCALER__) == IWDG_PRESCALER_64) || \
205 | ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
206 | ((__PRESCALER__) == IWDG_PRESCALER_256))
207 |
208 | /**
209 | * @brief Check IWDG reload value.
210 | * @param __RELOAD__ IWDG reload value
211 | * @retval None
212 | */
213 | #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
214 |
215 | /**
216 | * @brief Check IWDG window value.
217 | * @param __WINDOW__ IWDG window value
218 | * @retval None
219 | */
220 | #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
221 |
222 |
223 | /**
224 | * @}
225 | */
226 |
227 | /**
228 | * @}
229 | */
230 |
231 | /**
232 | * @}
233 | */
234 |
235 |
236 | #ifdef __cplusplus
237 | }
238 | #endif
239 |
240 | #endif /* STM32G0xx_HAL_IWDG_H */
241 |
242 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
243 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_pwr_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of PWR HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_PWR_EX_H
22 | #define STM32G0xx_HAL_PWR_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup PWREx PWREx
36 | * @brief PWR Extended HAL module driver
37 | * @{
38 | */
39 |
40 | /* Exported types ------------------------------------------------------------*/
41 | /* Exported constants --------------------------------------------------------*/
42 | /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
43 | * @{
44 | */
45 |
46 | /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
47 | * @{
48 | */
49 | #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u) /*!< VBAT charging through a 5 kOhms resistor */
50 | #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
51 | /**
52 | * @}
53 | */
54 |
55 | /** @defgroup PWREx_GPIO_Bit_Number GPIO bit position
56 | * @brief for I/O pull up/down setting in standby/shutdown mode
57 | * @{
58 | */
59 | #define PWR_GPIO_BIT_0 PWR_PUCRB_PU0 /*!< GPIO port I/O pin 0 */
60 | #define PWR_GPIO_BIT_1 PWR_PUCRB_PU1 /*!< GPIO port I/O pin 1 */
61 | #define PWR_GPIO_BIT_2 PWR_PUCRB_PU2 /*!< GPIO port I/O pin 2 */
62 | #define PWR_GPIO_BIT_3 PWR_PUCRB_PU3 /*!< GPIO port I/O pin 3 */
63 | #define PWR_GPIO_BIT_4 PWR_PUCRB_PU4 /*!< GPIO port I/O pin 4 */
64 | #define PWR_GPIO_BIT_5 PWR_PUCRB_PU5 /*!< GPIO port I/O pin 5 */
65 | #define PWR_GPIO_BIT_6 PWR_PUCRB_PU6 /*!< GPIO port I/O pin 6 */
66 | #define PWR_GPIO_BIT_7 PWR_PUCRB_PU7 /*!< GPIO port I/O pin 7 */
67 | #define PWR_GPIO_BIT_8 PWR_PUCRB_PU8 /*!< GPIO port I/O pin 8 */
68 | #define PWR_GPIO_BIT_9 PWR_PUCRB_PU9 /*!< GPIO port I/O pin 9 */
69 | #define PWR_GPIO_BIT_10 PWR_PUCRB_PU10 /*!< GPIO port I/O pin 10 */
70 | #define PWR_GPIO_BIT_11 PWR_PUCRB_PU11 /*!< GPIO port I/O pin 11 */
71 | #define PWR_GPIO_BIT_12 PWR_PUCRB_PU12 /*!< GPIO port I/O pin 12 */
72 | #define PWR_GPIO_BIT_13 PWR_PUCRB_PU13 /*!< GPIO port I/O pin 13 */
73 | #define PWR_GPIO_BIT_14 PWR_PUCRB_PU14 /*!< GPIO port I/O pin 14 */
74 | #define PWR_GPIO_BIT_15 PWR_PUCRB_PU15 /*!< GPIO port I/O pin 15 */
75 | /**
76 | * @}
77 | */
78 |
79 | /** @defgroup PWREx_GPIO_Port GPIO Port
80 | * @{
81 | */
82 | #define PWR_GPIO_A (0x00000000u) /*!< GPIO port A */
83 | #define PWR_GPIO_B (0x00000001u) /*!< GPIO port B */
84 | #define PWR_GPIO_C (0x00000002u) /*!< GPIO port C */
85 | #define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */
86 | #define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */
87 | /**
88 | * @}
89 | */
90 |
91 | /** @defgroup PWREx_Flash_PowerDown Flash Power Down modes
92 | * @{
93 | */
94 | #define PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN /*!< Enable Flash power down in low power run mode */
95 | #define PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP /*!< Enable Flash power down in low power sleep mode */
96 | #define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP /*!< Enable Flash power down in stop mode */
97 | /**
98 | * @}
99 | */
100 |
101 | /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
102 | * @{
103 | */
104 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */
105 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
106 | /**
107 | * @}
108 | */
109 |
110 | /**
111 | * @}
112 | */
113 |
114 | /* Exported macros -----------------------------------------------------------*/
115 | /* Private macros ------------------------------------------------------------*/
116 | /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
117 | * @{
118 | */
119 | #define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
120 | ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
121 |
122 | #define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \
123 | (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u))
124 |
125 | #define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \
126 | ((__GPIO__) == PWR_GPIO_B) || \
127 | ((__GPIO__) == PWR_GPIO_C) || \
128 | ((__GPIO__) == PWR_GPIO_D) || \
129 | ((__GPIO__) == PWR_GPIO_F))
130 |
131 | #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \
132 | (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u))
133 |
134 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
135 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
136 |
137 | /**
138 | * @}
139 | */
140 |
141 | /* Exported functions --------------------------------------------------------*/
142 | /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
143 | * @{
144 | */
145 |
146 | /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
147 | * @{
148 | */
149 |
150 | /* Peripheral Control functions **********************************************/
151 | void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
152 | void HAL_PWREx_DisableBatteryCharging(void);
153 | #if defined(PWR_CR3_ENB_ULP)
154 | void HAL_PWREx_EnablePORMonitorSampling(void);
155 | void HAL_PWREx_DisablePORMonitorSampling(void);
156 | #endif
157 | void HAL_PWREx_EnableInternalWakeUpLine(void);
158 | void HAL_PWREx_DisableInternalWakeUpLine(void);
159 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
160 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
161 | HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
162 | HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
163 | void HAL_PWREx_EnablePullUpPullDownConfig(void);
164 | void HAL_PWREx_DisablePullUpPullDownConfig(void);
165 | #if defined(PWR_CR3_RRS)
166 | void HAL_PWREx_EnableSRAMRetention(void);
167 | void HAL_PWREx_DisableSRAMRetention(void);
168 | #endif
169 | void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
170 | void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
171 | uint32_t HAL_PWREx_GetVoltageRange(void);
172 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
173 |
174 | /* Low Power modes configuration functions ************************************/
175 | void HAL_PWREx_EnableLowPowerRunMode(void);
176 | HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
177 | #if defined(PWR_SHDW_SUPPORT)
178 | void HAL_PWREx_EnterSHUTDOWNMode(void);
179 | #endif
180 |
181 | /**
182 | * @}
183 | */
184 |
185 | /**
186 | * @}
187 | */
188 |
189 | /**
190 | * @}
191 | */
192 |
193 | /**
194 | * @}
195 | */
196 |
197 | #ifdef __cplusplus
198 | }
199 | #endif
200 |
201 |
202 | #endif /* STM32G0xx_HAL_PWR_EX_H */
203 |
204 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
205 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_adc_ex.c
4 | * @author MCD Application Team
5 | * @brief This file provides firmware functions to manage the following
6 | * functionalities of the Analog to Digital Convertor (ADC)
7 | * peripheral:
8 | * + Operation functions
9 | * ++ Calibration
10 | * +++ ADC automatic self-calibration
11 | * +++ Calibration factors get or set
12 | * Other functions (generic functions) are available in file
13 | * "stm32g0xx_hal_adc.c".
14 | *
15 | @verbatim
16 | [..]
17 | (@) Sections "ADC peripheral features" and "How to use this driver" are
18 | available in file of generic functions "stm32g0xx_hal_adc.c".
19 | [..]
20 | @endverbatim
21 | ******************************************************************************
22 | * @attention
23 | *
24 | * © Copyright (c) 2018 STMicroelectronics.
25 | * All rights reserved.
26 | *
27 | * This software component is licensed by ST under BSD 3-Clause license,
28 | * the "License"; You may not use this file except in compliance with the
29 | * License. You may obtain a copy of the License at:
30 | * opensource.org/licenses/BSD-3-Clause
31 | *
32 | ******************************************************************************
33 | */
34 |
35 | /* Includes ------------------------------------------------------------------*/
36 | #include "stm32g0xx_hal.h"
37 |
38 | /** @addtogroup STM32G0xx_HAL_Driver
39 | * @{
40 | */
41 |
42 | /** @defgroup ADCEx ADCEx
43 | * @brief ADC Extended HAL module driver
44 | * @{
45 | */
46 |
47 | #ifdef HAL_ADC_MODULE_ENABLED
48 |
49 | /* Private typedef -----------------------------------------------------------*/
50 | /* Private define ------------------------------------------------------------*/
51 |
52 | /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
53 | * @{
54 | */
55 |
56 | /* Fixed timeout value for ADC calibration. */
57 | /* Values defined to be higher than worst cases: maximum ratio between ADC */
58 | /* and CPU clock frequencies. */
59 | /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */
60 | /* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 52MHz. */
61 | /* Calibration time max = 116 / fADC (refer to datasheet) */
62 | /* = 193 024 CPU cycles */
63 | #define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /* Private macro -------------------------------------------------------------*/
70 | /* Private variables ---------------------------------------------------------*/
71 | /* Private function prototypes -----------------------------------------------*/
72 | /* Exported functions --------------------------------------------------------*/
73 |
74 | /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
75 | * @{
76 | */
77 |
78 | /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
79 | * @brief Extended IO operation functions
80 | *
81 | @verbatim
82 | ===============================================================================
83 | ##### IO operation functions #####
84 | ===============================================================================
85 | [..] This section provides functions allowing to:
86 |
87 | (+) Perform the ADC self-calibration.
88 | (+) Get calibration factors.
89 | (+) Set calibration factors.
90 |
91 | @endverbatim
92 | * @{
93 | */
94 |
95 | /**
96 | * @brief Perform an ADC automatic self-calibration
97 | * Calibration prerequisite: ADC must be disabled (execute this
98 | * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
99 | * @note Calibration factor can be read after calibration, using function
100 | * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
101 | * @param hadc ADC handle
102 | * @retval HAL status
103 | */
104 | HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
105 | {
106 | HAL_StatusTypeDef tmp_hal_status;
107 | __IO uint32_t wait_loop_index = 0UL;
108 | uint32_t backup_setting_adc_dma_transfer; /* Note: Variable not declared as volatile because register read is already declared as volatile */
109 |
110 | /* Check the parameters */
111 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
112 |
113 | /* Process locked */
114 | __HAL_LOCK(hadc);
115 |
116 | /* Calibration prerequisite: ADC must be disabled. */
117 |
118 | /* Disable the ADC (if not already disabled) */
119 | tmp_hal_status = ADC_Disable(hadc);
120 |
121 | /* Check if ADC is effectively disabled */
122 | if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
123 | {
124 | /* Set ADC state */
125 | ADC_STATE_CLR_SET(hadc->State,
126 | HAL_ADC_STATE_REG_BUSY,
127 | HAL_ADC_STATE_BUSY_INTERNAL);
128 |
129 | /* Disable ADC DMA transfer request during calibration */
130 | /* Note: Specificity of this STM32 serie: Calibration factor is */
131 | /* available in data register and also transfered by DMA. */
132 | /* To not insert ADC calibration factor among ADC conversion data */
133 | /* in array variable, DMA transfer must be disabled during */
134 | /* calibration. */
135 | backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
136 | CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
137 |
138 | /* Start ADC calibration */
139 | SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
140 |
141 | /* Wait for calibration completion */
142 | while(LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
143 | {
144 | wait_loop_index++;
145 | if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
146 | {
147 | /* Update ADC state machine to error */
148 | ADC_STATE_CLR_SET(hadc->State,
149 | HAL_ADC_STATE_BUSY_INTERNAL,
150 | HAL_ADC_STATE_ERROR_INTERNAL);
151 |
152 | /* Process unlocked */
153 | __HAL_UNLOCK(hadc);
154 |
155 | return HAL_ERROR;
156 | }
157 | }
158 |
159 | /* Restore ADC DMA transfer request after calibration */
160 | SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
161 |
162 | /* Set ADC state */
163 | ADC_STATE_CLR_SET(hadc->State,
164 | HAL_ADC_STATE_BUSY_INTERNAL,
165 | HAL_ADC_STATE_READY);
166 | }
167 | else
168 | {
169 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
170 |
171 | /* Note: No need to update variable "tmp_hal_status" here: already set */
172 | /* to state "HAL_ERROR" by function disabling the ADC. */
173 | }
174 |
175 | /* Process unlocked */
176 | __HAL_UNLOCK(hadc);
177 |
178 | /* Return function status */
179 | return tmp_hal_status;
180 | }
181 |
182 | /**
183 | * @brief Get the calibration factor.
184 | * @param hadc ADC handle.
185 | * @retval Calibration value.
186 | */
187 | uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc)
188 | {
189 | /* Check the parameters */
190 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
191 |
192 | /* Return the selected ADC calibration value */
193 | return ((hadc->Instance->CALFACT) & 0x0000007FU);
194 | }
195 |
196 | /**
197 | * @brief Set the calibration factor to overwrite automatic conversion result.
198 | * ADC must be enabled and no conversion is ongoing.
199 | * @param hadc ADC handle
200 | * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
201 | * @retval HAL state
202 | */
203 | HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t CalibrationFactor)
204 | {
205 | HAL_StatusTypeDef tmp_hal_status = HAL_OK;
206 | uint32_t tmp_adc_is_conversion_on_going_regular;
207 |
208 | /* Check the parameters */
209 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
210 | assert_param(IS_ADC_CALFACT(CalibrationFactor));
211 |
212 | /* Process locked */
213 | __HAL_LOCK(hadc);
214 |
215 | /* Verification of hardware constraints before modifying the calibration */
216 | /* factors register: ADC must be enabled, no conversion on going. */
217 | tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
218 |
219 | if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
220 | && (tmp_adc_is_conversion_on_going_regular == 0UL)
221 | )
222 | {
223 | hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
224 | hadc->Instance->CALFACT |= CalibrationFactor;
225 | }
226 | else
227 | {
228 | /* Update ADC state machine */
229 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
230 | /* Update ADC error code */
231 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
232 |
233 | /* Update ADC state machine to error */
234 | tmp_hal_status = HAL_ERROR;
235 | }
236 |
237 | /* Process unlocked */
238 | __HAL_UNLOCK(hadc);
239 |
240 | /* Return function status */
241 | return tmp_hal_status;
242 | }
243 |
244 | /**
245 | * @brief Analog watchdog 2 callback in non-blocking mode.
246 | * @param hadc ADC handle
247 | * @retval None
248 | */
249 | __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
250 | {
251 | /* Prevent unused argument(s) compilation warning */
252 | UNUSED(hadc);
253 |
254 | /* NOTE : This function should not be modified. When the callback is needed,
255 | function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
256 | */
257 | }
258 |
259 | /**
260 | * @brief Analog watchdog 3 callback in non-blocking mode.
261 | * @param hadc ADC handle
262 | * @retval None
263 | */
264 | __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
265 | {
266 | /* Prevent unused argument(s) compilation warning */
267 | UNUSED(hadc);
268 |
269 | /* NOTE : This function should not be modified. When the callback is needed,
270 | function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
271 | */
272 | }
273 |
274 |
275 | /**
276 | * @brief End Of Sampling callback in non-blocking mode.
277 | * @param hadc ADC handle
278 | * @retval None
279 | */
280 | __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
281 | {
282 | /* Prevent unused argument(s) compilation warning */
283 | UNUSED(hadc);
284 |
285 | /* NOTE : This function should not be modified. When the callback is needed,
286 | function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
287 | */
288 | }
289 |
290 | /**
291 | * @brief ADC channel configuration ready callback in non-blocking mode.
292 | * @param hadc ADC handle
293 | * @retval None
294 | */
295 | __weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef* hadc)
296 | {
297 | /* Prevent unused argument(s) compilation warning */
298 | UNUSED(hadc);
299 |
300 | /* NOTE : This function should not be modified. When the callback is needed,
301 | function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
302 | */
303 | }
304 |
305 | /**
306 | * @}
307 | */
308 |
309 | /**
310 | * @brief Disable ADC voltage regulator.
311 | * @note Disabling voltage regulator allows to save power. This operation can
312 | * be carried out only when ADC is disabled.
313 | * @note To enable again the voltage regulator, the user is expected to
314 | * resort to HAL_ADC_Init() API.
315 | * @param hadc ADC handle
316 | * @retval HAL status
317 | */
318 | HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
319 | {
320 | HAL_StatusTypeDef tmp_hal_status;
321 |
322 | /* Check the parameters */
323 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
324 |
325 | /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
326 | if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
327 | {
328 | LL_ADC_DisableInternalRegulator(hadc->Instance);
329 | tmp_hal_status = HAL_OK;
330 | }
331 | else
332 | {
333 | tmp_hal_status = HAL_ERROR;
334 | }
335 |
336 | return tmp_hal_status;
337 | }
338 |
339 | /**
340 | * @}
341 | */
342 |
343 | /**
344 | * @}
345 | */
346 |
347 | #endif /* HAL_ADC_MODULE_ENABLED */
348 | /**
349 | * @}
350 | */
351 |
352 | /**
353 | * @}
354 | */
355 |
356 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
357 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_dma_ex.c
4 | * @author MCD Application Team
5 | * @brief DMA Extension HAL module driver
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the DMA Extension peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### How to use this driver #####
13 | ==============================================================================
14 | [..]
15 | The DMA Extension HAL driver can be used as follows:
16 |
17 | (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
18 | (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
19 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
20 | to respectively enable/disable the request generator.
21 |
22 | (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
23 | the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
24 | As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
25 | called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
26 | (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
27 |
28 | @endverbatim
29 | ******************************************************************************
30 | * @attention
31 | *
32 | * © Copyright (c) 2018 STMicroelectronics.
33 | * All rights reserved.
34 | *
35 | * This software component is licensed by ST under BSD 3-Clause license,
36 | * the "License"; You may not use this file except in compliance with the
37 | * License. You may obtain a copy of the License at:
38 | * opensource.org/licenses/BSD-3-Clause
39 | *
40 | ******************************************************************************
41 | */
42 |
43 | /* Includes ------------------------------------------------------------------*/
44 | #include "stm32g0xx_hal.h"
45 |
46 | /** @addtogroup STM32G0xx_HAL_Driver
47 | * @{
48 | */
49 |
50 | /** @defgroup DMAEx DMAEx
51 | * @brief DMA Extended HAL module driver
52 | * @{
53 | */
54 |
55 | #ifdef HAL_DMA_MODULE_ENABLED
56 |
57 | /* Private typedef -----------------------------------------------------------*/
58 | /* Private define ------------------------------------------------------------*/
59 | /* Private macro -------------------------------------------------------------*/
60 | /* Private variables ---------------------------------------------------------*/
61 | /* Private Constants ---------------------------------------------------------*/
62 | /* Private function prototypes -----------------------------------------------*/
63 | /* Private functions ---------------------------------------------------------*/
64 |
65 |
66 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
67 | * @{
68 | */
69 |
70 | /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
71 | * @brief Extended features functions
72 | *
73 | @verbatim
74 | ===============================================================================
75 | ##### Extended features functions #####
76 | ===============================================================================
77 | [..] This section provides functions allowing to:
78 |
79 | (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
80 | (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
81 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
82 | to respectively enable/disable the request generator.
83 |
84 | @endverbatim
85 | * @{
86 | */
87 |
88 | /**
89 | * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
90 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
91 | * the configuration information for the specified DMA channel.
92 | * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
93 | * @retval HAL status
94 | */
95 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
96 | {
97 | /* Check the parameters */
98 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
99 |
100 | assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
101 |
102 | assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
103 | assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
104 | assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
105 | assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
106 |
107 | /*Check if the DMA state is ready */
108 | if (hdma->State == HAL_DMA_STATE_READY)
109 | {
110 | /* Process Locked */
111 | __HAL_LOCK(hdma);
112 |
113 | /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
114 | MODIFY_REG(hdma->DMAmuxChannel->CCR, \
115 | (~DMAMUX_CxCR_DMAREQ_ID), \
116 | ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
117 | pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
118 | ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
119 |
120 | /* Process UnLocked */
121 | __HAL_UNLOCK(hdma);
122 |
123 | return HAL_OK;
124 | }
125 | else
126 | {
127 | /*DMA State not Ready*/
128 | return HAL_ERROR;
129 | }
130 | }
131 |
132 | /**
133 | * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
134 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
135 | * the configuration information for the specified DMA channel.
136 | * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
137 | * contains the request generator parameters.
138 | *
139 | * @retval HAL status
140 | */
141 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
142 | {
143 | /* Check the parameters */
144 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
145 |
146 | assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
147 |
148 | assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
149 | assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
150 |
151 | /* check if the DMA state is ready
152 | and DMA is using a DMAMUX request generator block
153 | */
154 | if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
155 | {
156 | /* Process Locked */
157 | __HAL_LOCK(hdma);
158 |
159 | /* Set the request generator new parameters*/
160 | hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
161 | ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
162 | pRequestGeneratorConfig->Polarity;
163 | /* Process UnLocked */
164 | __HAL_UNLOCK(hdma);
165 |
166 | return HAL_OK;
167 | }
168 | else
169 | {
170 | return HAL_ERROR;
171 | }
172 | }
173 |
174 | /**
175 | * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
176 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
177 | * the configuration information for the specified DMA channel.
178 | * @retval HAL status
179 | */
180 | HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
181 | {
182 | /* Check the parameters */
183 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
184 |
185 | /* check if the DMA state is ready
186 | and DMA is using a DMAMUX request generator block
187 | */
188 | if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
189 | {
190 |
191 | /* Enable the request generator*/
192 | hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
193 |
194 | return HAL_OK;
195 | }
196 | else
197 | {
198 | return HAL_ERROR;
199 | }
200 | }
201 |
202 | /**
203 | * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
204 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
205 | * the configuration information for the specified DMA channel.
206 | * @retval HAL status
207 | */
208 | HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
209 | {
210 | /* Check the parameters */
211 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
212 |
213 | /* check if the DMA state is ready
214 | and DMA is using a DMAMUX request generator block
215 | */
216 | if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
217 | {
218 |
219 | /* Disable the request generator*/
220 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
221 |
222 | return HAL_OK;
223 | }
224 | else
225 | {
226 | return HAL_ERROR;
227 | }
228 | }
229 |
230 | /**
231 | * @brief Handles DMAMUX interrupt request.
232 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
233 | * the configuration information for the specified DMA channel.
234 | * @retval None
235 | */
236 | void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
237 | {
238 | /* Check for DMAMUX Synchronization overrun */
239 | if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
240 | {
241 | /* Disable the synchro overrun interrupt */
242 | hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
243 |
244 | /* Clear the DMAMUX synchro overrun flag */
245 | hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
246 |
247 | /* Update error code */
248 | hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
249 |
250 | if (hdma->XferErrorCallback != NULL)
251 | {
252 | /* Transfer error callback */
253 | hdma->XferErrorCallback(hdma);
254 | }
255 | }
256 |
257 | if (hdma->DMAmuxRequestGen != 0)
258 | {
259 | /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
260 | if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
261 | {
262 | /* Disable the request gen overrun interrupt */
263 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
264 |
265 | /* Clear the DMAMUX request generator overrun flag */
266 | hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
267 |
268 | /* Update error code */
269 | hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
270 |
271 | if (hdma->XferErrorCallback != NULL)
272 | {
273 | /* Transfer error callback */
274 | hdma->XferErrorCallback(hdma);
275 | }
276 | }
277 | }
278 | }
279 |
280 | /**
281 | * @}
282 | */
283 |
284 | /**
285 | * @}
286 | */
287 |
288 | #endif /* HAL_DMA_MODULE_ENABLED */
289 | /**
290 | * @}
291 | */
292 |
293 | /**
294 | * @}
295 | */
296 |
297 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
298 |
--------------------------------------------------------------------------------
/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_iwdg.c
4 | * @author MCD Application Team
5 | * @brief IWDG HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * functionalities of the Independent Watchdog (IWDG) peripheral:
8 | * + Initialization and Start functions
9 | * + IO operation functions
10 | *
11 | @verbatim
12 | ==============================================================================
13 | ##### IWDG Generic features #####
14 | ==============================================================================
15 | [..]
16 | (+) The IWDG can be started by either software or hardware (configurable
17 | through option byte).
18 |
19 | (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
20 | if the main clock fails.
21 |
22 | (+) Once the IWDG is started, the LSI is forced ON and both can not be
23 | disabled. The counter starts counting down from the reset value (0xFFF).
24 | When it reaches the end of count value (0x000) a reset signal is
25 | generated (IWDG reset).
26 |
27 | (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
28 | the IWDG_RLR value is reloaded in the counter and the watchdog reset is
29 | prevented.
30 |
31 | (+) The IWDG is implemented in the VDD voltage domain that is still functional
32 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
33 | IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
34 | reset occurs.
35 |
36 | (+) Debug mode : When the microcontroller enters debug mode (core halted),
37 | the IWDG counter either continues to work normally or stops, depending
38 | on DBG_IWDG_STOP configuration bit in DBG module, accessible through
39 | __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
40 |
41 | [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
42 | The IWDG timeout may vary due to LSI frequency dispersion. STM32G0xx
43 | devices provide the capability to measure the LSI frequency (LSI clock
44 | connected internally to TIM16 CH1 input capture). The measured value
45 | can be used to have an IWDG timeout with an acceptable accuracy.
46 |
47 | ##### How to use this driver #####
48 | ==============================================================================
49 | [..]
50 | (#) Use IWDG using HAL_IWDG_Init() function to :
51 | (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
52 | clock is forced ON and IWDG counter starts counting down.
53 | (++) Enable write access to configuration registers:
54 | IWDG_PR, IWDG_RLR and IWDG_WINR.
55 | (++) Configure the IWDG prescaler and counter reload value. This reload
56 | value will be loaded in the IWDG counter each time the watchdog is
57 | reloaded, then the IWDG will start counting down from this value.
58 | (++) Wait for status flags to be reset.
59 | (++) Depending on window parameter:
60 | (+++) If Window Init parameter is same as Window register value,
61 | nothing more is done but reload counter value in order to exit
62 | function with exact time base.
63 | (+++) Else modify Window register. This will automatically reload
64 | watchdog counter.
65 |
66 | (#) Then the application program must refresh the IWDG counter at regular
67 | intervals during normal operation to prevent an MCU reset, using
68 | HAL_IWDG_Refresh() function.
69 |
70 | *** IWDG HAL driver macros list ***
71 | ====================================
72 | [..]
73 | Below the list of most used macros in IWDG HAL driver:
74 | (+) __HAL_IWDG_START: Enable the IWDG peripheral
75 | (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
76 | the reload register
77 |
78 | @endverbatim
79 | ******************************************************************************
80 | * @attention
81 | *
82 | * © Copyright (c) 2018 STMicroelectronics.
83 | * All rights reserved.
84 | *
85 | * This software component is licensed by ST under BSD 3-Clause license,
86 | * the "License"; You may not use this file except in compliance with the
87 | * License. You may obtain a copy of the License at:
88 | * opensource.org/licenses/BSD-3-Clause
89 | *
90 | ******************************************************************************
91 | */
92 |
93 | /* Includes ------------------------------------------------------------------*/
94 | #include "stm32g0xx_hal.h"
95 |
96 | /** @addtogroup STM32G0xx_HAL_Driver
97 | * @{
98 | */
99 |
100 | #ifdef HAL_IWDG_MODULE_ENABLED
101 | /** @addtogroup IWDG
102 | * @brief IWDG HAL module driver.
103 | * @{
104 | */
105 |
106 | /* Private typedef -----------------------------------------------------------*/
107 | /* Private define ------------------------------------------------------------*/
108 | /** @defgroup IWDG_Private_Defines IWDG Private Defines
109 | * @{
110 | */
111 | /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
112 | higher prescaler (256), and according to LSI variation, we need to wait at
113 | least 6 cycles so 48 ms. */
114 | #define HAL_IWDG_DEFAULT_TIMEOUT 48u
115 | /**
116 | * @}
117 | */
118 |
119 | /* Private macro -------------------------------------------------------------*/
120 | /* Private variables ---------------------------------------------------------*/
121 | /* Private function prototypes -----------------------------------------------*/
122 | /* Exported functions --------------------------------------------------------*/
123 |
124 | /** @addtogroup IWDG_Exported_Functions
125 | * @{
126 | */
127 |
128 | /** @addtogroup IWDG_Exported_Functions_Group1
129 | * @brief Initialization and Start functions.
130 | *
131 | @verbatim
132 | ===============================================================================
133 | ##### Initialization and Start functions #####
134 | ===============================================================================
135 | [..] This section provides functions allowing to:
136 | (+) Initialize the IWDG according to the specified parameters in the
137 | IWDG_InitTypeDef of associated handle.
138 | (+) Manage Window option.
139 | (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
140 | is reloaded in order to exit function with correct time base.
141 |
142 | @endverbatim
143 | * @{
144 | */
145 |
146 | /**
147 | * @brief Initialize the IWDG according to the specified parameters in the
148 | * IWDG_InitTypeDef and start watchdog. Before exiting function,
149 | * watchdog is refreshed in order to have correct time base.
150 | * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
151 | * the configuration information for the specified IWDG module.
152 | * @retval HAL status
153 | */
154 | HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
155 | {
156 | uint32_t tickstart;
157 |
158 | /* Check the IWDG handle allocation */
159 | if (hiwdg == NULL)
160 | {
161 | return HAL_ERROR;
162 | }
163 |
164 | /* Check the parameters */
165 | assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
166 | assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
167 | assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
168 | assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
169 |
170 | /* Enable IWDG. LSI is turned on automatically */
171 | __HAL_IWDG_START(hiwdg);
172 |
173 | /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
174 | 0x5555 in KR */
175 | IWDG_ENABLE_WRITE_ACCESS(hiwdg);
176 |
177 | /* Write to IWDG registers the Prescaler & Reload values to work with */
178 | hiwdg->Instance->PR = hiwdg->Init.Prescaler;
179 | hiwdg->Instance->RLR = hiwdg->Init.Reload;
180 |
181 | /* Check pending flag, if previous update not done, return timeout */
182 | tickstart = HAL_GetTick();
183 |
184 | /* Wait for register to be updated */
185 | while (hiwdg->Instance->SR != 0x00u)
186 | {
187 | if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
188 | {
189 | return HAL_TIMEOUT;
190 | }
191 | }
192 |
193 | /* If window parameter is different than current value, modify window
194 | register */
195 | if (hiwdg->Instance->WINR != hiwdg->Init.Window)
196 | {
197 | /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
198 | even if window feature is disabled, Watchdog will be reloaded by writing
199 | windows register */
200 | hiwdg->Instance->WINR = hiwdg->Init.Window;
201 | }
202 | else
203 | {
204 | /* Reload IWDG counter with value defined in the reload register */
205 | __HAL_IWDG_RELOAD_COUNTER(hiwdg);
206 | }
207 |
208 | /* Return function status */
209 | return HAL_OK;
210 | }
211 |
212 | /**
213 | * @}
214 | */
215 |
216 |
217 | /** @addtogroup IWDG_Exported_Functions_Group2
218 | * @brief IO operation functions
219 | *
220 | @verbatim
221 | ===============================================================================
222 | ##### IO operation functions #####
223 | ===============================================================================
224 | [..] This section provides functions allowing to:
225 | (+) Refresh the IWDG.
226 |
227 | @endverbatim
228 | * @{
229 | */
230 |
231 |
232 | /**
233 | * @brief Refresh the IWDG.
234 | * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
235 | * the configuration information for the specified IWDG module.
236 | * @retval HAL status
237 | */
238 | HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
239 | {
240 | /* Reload IWDG counter with value defined in the reload register */
241 | __HAL_IWDG_RELOAD_COUNTER(hiwdg);
242 |
243 | /* Return function status */
244 | return HAL_OK;
245 | }
246 |
247 | /**
248 | * @}
249 | */
250 |
251 | /**
252 | * @}
253 | */
254 |
255 | #endif /* HAL_IWDG_MODULE_ENABLED */
256 | /**
257 | * @}
258 | */
259 |
260 | /**
261 | * @}
262 | */
263 |
264 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
265 |
--------------------------------------------------------------------------------
/Inc/adc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : ADC.h
4 | * Description : This file provides code for the configuration
5 | * of the ADC instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __adc_H
21 | #define __adc_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern ADC_HandleTypeDef hadc1;
34 |
35 | /* USER CODE BEGIN Private defines */
36 |
37 | /* USER CODE END Private defines */
38 |
39 | void MX_ADC1_Init(void);
40 |
41 | /* USER CODE BEGIN Prototypes */
42 | u16 Get_Battery_Voltage(void);
43 | /* USER CODE END Prototypes */
44 |
45 | #ifdef __cplusplus
46 | }
47 | #endif
48 | #endif /*__ adc_H */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
59 |
--------------------------------------------------------------------------------
/Inc/dma.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : dma.h
4 | * Description : This file contains all the function prototypes for
5 | * the dma.c file
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __dma_H
21 | #define __dma_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* DMA memory to memory transfer handles -------------------------------------*/
31 |
32 | /* USER CODE BEGIN Includes */
33 |
34 | /* USER CODE END Includes */
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_DMA_Init(void);
41 |
42 | /* USER CODE BEGIN Prototypes */
43 |
44 | /* USER CODE END Prototypes */
45 |
46 | #ifdef __cplusplus
47 | }
48 | #endif
49 |
50 | #endif /* __dma_H */
51 |
52 | /**
53 | * @}
54 | */
55 |
56 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
57 |
--------------------------------------------------------------------------------
/Inc/gpio.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : gpio.h
4 | * Description : This file contains all the functions prototypes for
5 | * the gpio
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef __gpio_H
22 | #define __gpio_H
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "main.h"
29 |
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* USER CODE BEGIN Private defines */
35 |
36 | /* USER CODE END Private defines */
37 |
38 | void MX_GPIO_Init(void);
39 |
40 | /* USER CODE BEGIN Prototypes */
41 |
42 | /* USER CODE END Prototypes */
43 |
44 | #ifdef __cplusplus
45 | }
46 | #endif
47 | #endif /*__ pinoutConfig_H */
48 |
49 | /**
50 | * @}
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
58 |
--------------------------------------------------------------------------------
/Inc/iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : IWDG.h
4 | * Description : This file provides code for the configuration
5 | * of the IWDG instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __iwdg_H
21 | #define __iwdg_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern IWDG_HandleTypeDef hiwdg;
34 |
35 | /* USER CODE BEGIN Private defines */
36 |
37 | /* USER CODE END Private defines */
38 |
39 | void MX_IWDG_Init(void);
40 |
41 | /* USER CODE BEGIN Prototypes */
42 |
43 | /* USER CODE END Prototypes */
44 |
45 | #ifdef __cplusplus
46 | }
47 | #endif
48 | #endif /*__ iwdg_H */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
59 |
--------------------------------------------------------------------------------
/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32g0xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | #define TXD_Pin GPIO_PIN_2
62 | #define TXD_GPIO_Port GPIOA
63 | #define RXD_Pin GPIO_PIN_3
64 | #define RXD_GPIO_Port GPIOA
65 | #define STAT_Pin GPIO_PIN_4
66 | #define STAT_GPIO_Port GPIOA
67 | #define BATTERY_Pin GPIO_PIN_5
68 | #define BATTERY_GPIO_Port GPIOA
69 | #define MOTOR4_Pin GPIO_PIN_8
70 | #define MOTOR4_GPIO_Port GPIOA
71 | #define LED4_Pin GPIO_PIN_9
72 | #define LED4_GPIO_Port GPIOA
73 | #define LED3_Pin GPIO_PIN_6
74 | #define LED3_GPIO_Port GPIOC
75 | #define MOTOR3_Pin GPIO_PIN_11
76 | #define MOTOR3_GPIO_Port GPIOA
77 | #define MOTOR2_Pin GPIO_PIN_3
78 | #define MOTOR2_GPIO_Port GPIOB
79 | #define LED2_Pin GPIO_PIN_4
80 | #define LED2_GPIO_Port GPIOB
81 | #define LED1_Pin GPIO_PIN_5
82 | #define LED1_GPIO_Port GPIOB
83 | #define MOTOR1_Pin GPIO_PIN_6
84 | #define MOTOR1_GPIO_Port GPIOB
85 | #define SDA_Pin GPIO_PIN_7
86 | #define SDA_GPIO_Port GPIOB
87 | #define SCL_Pin GPIO_PIN_8
88 | #define SCL_GPIO_Port GPIOB
89 | /* USER CODE BEGIN Private defines */
90 | #define LED1_PORT LED1_GPIO_Port->ODR
91 | #define LED2_PORT LED2_GPIO_Port->ODR
92 | #define LED3_PORT LED3_GPIO_Port->ODR
93 | #define LED4_PORT LED4_GPIO_Port->ODR
94 | #define STAT_PORT STAT_GPIO_Port->IDR
95 | typedef unsigned char u8;
96 | typedef unsigned short u16;
97 | typedef unsigned int u32;
98 | typedef short s16;
99 | typedef long s32;
100 | /* USER CODE END Private defines */
101 |
102 | #ifdef __cplusplus
103 | }
104 | #endif
105 |
106 | #endif /* __MAIN_H */
107 |
108 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
109 |
--------------------------------------------------------------------------------
/Inc/stm32g0xx_hal_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_conf.h
4 | * @author MCD Application Team
5 | * @brief HAL configuration file.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_CONF_H
22 | #define STM32G0xx_HAL_CONF_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Exported types ------------------------------------------------------------*/
29 | /* Exported constants --------------------------------------------------------*/
30 |
31 | /* ########################## Module Selection ############################## */
32 | /**
33 | * @brief This is the list of modules to be used in the HAL driver
34 | */
35 | #define HAL_MODULE_ENABLED
36 |
37 | #define HAL_ADC_MODULE_ENABLED
38 | /* #define HAL_CEC_MODULE_ENABLED */
39 | /* #define HAL_COMP_MODULE_ENABLED */
40 | /* #define HAL_CRC_MODULE_ENABLED */
41 | /* #define HAL_CRYP_MODULE_ENABLED */
42 | /* #define HAL_DAC_MODULE_ENABLED */
43 | /* #define HAL_EXTI_MODULE_ENABLED */
44 | /* #define HAL_I2C_MODULE_ENABLED */
45 | /* #define HAL_I2S_MODULE_ENABLED */
46 | #define HAL_IWDG_MODULE_ENABLED
47 | /* #define HAL_IRDA_MODULE_ENABLED */
48 | /* #define HAL_LPTIM_MODULE_ENABLED */
49 | /* #define HAL_RNG_MODULE_ENABLED */
50 | /* #define HAL_RTC_MODULE_ENABLED */
51 | /* #define HAL_SMARTCARD_MODULE_ENABLED */
52 | /* #define HAL_SMBUS_MODULE_ENABLED */
53 | /* #define HAL_SPI_MODULE_ENABLED */
54 | #define HAL_TIM_MODULE_ENABLED
55 | #define HAL_UART_MODULE_ENABLED
56 | /* #define HAL_USART_MODULE_ENABLED */
57 | /* #define HAL_WWDG_MODULE_ENABLED */
58 | #define HAL_GPIO_MODULE_ENABLED
59 | #define HAL_EXTI_MODULE_ENABLED
60 | #define HAL_DMA_MODULE_ENABLED
61 | #define HAL_RCC_MODULE_ENABLED
62 | #define HAL_FLASH_MODULE_ENABLED
63 | #define HAL_PWR_MODULE_ENABLED
64 | #define HAL_CORTEX_MODULE_ENABLED
65 |
66 | /* ########################## Register Callbacks selection ############################## */
67 | /**
68 | * @brief This is the list of modules where register callback can be used
69 | */
70 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0u
71 | #define USE_HAL_CEC_REGISTER_CALLBACKS 0u
72 | #define USE_HAL_COMP_REGISTER_CALLBACKS 0u
73 | #define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
74 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0u
75 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0u
76 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0u
77 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
78 | #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
79 | #define USE_HAL_RNG_REGISTER_CALLBACKS 0u
80 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0u
81 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
82 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0u
83 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0u
84 | #define USE_HAL_UART_REGISTER_CALLBACKS 0u
85 | #define USE_HAL_USART_REGISTER_CALLBACKS 0u
86 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
87 |
88 | /* ########################## Oscillator Values adaptation ####################*/
89 | /**
90 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
91 | * This value is used by the RCC HAL module to compute the system frequency
92 | * (when HSE is used as system clock source, directly or through the PLL).
93 | */
94 | #if !defined (HSE_VALUE)
95 | #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
96 | #endif /* HSE_VALUE */
97 |
98 | #if !defined (HSE_STARTUP_TIMEOUT)
99 | #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
100 | #endif /* HSE_STARTUP_TIMEOUT */
101 |
102 | /**
103 | * @brief Internal High Speed oscillator (HSI) value.
104 | * This value is used by the RCC HAL module to compute the system frequency
105 | * (when HSI is used as system clock source, directly or through the PLL).
106 | */
107 | #if !defined (HSI_VALUE)
108 | #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
109 | #endif /* HSI_VALUE */
110 |
111 | /**
112 | * @brief Internal Low Speed oscillator (LSI) value.
113 | */
114 | #if !defined (LSI_VALUE)
115 | #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
116 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
117 | The real value may vary depending on the variations
118 | in voltage and temperature.*/
119 | /**
120 | * @brief External Low Speed oscillator (LSE) value.
121 | * This value is used by the UART, RTC HAL module to compute the system frequency
122 | */
123 | #if !defined (LSE_VALUE)
124 | #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
125 | #endif /* LSE_VALUE */
126 |
127 | #if !defined (LSE_STARTUP_TIMEOUT)
128 | #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
129 | #endif /* LSE_STARTUP_TIMEOUT */
130 |
131 | /**
132 | * @brief External clock source for I2S1 peripheral
133 | * This value is used by the RCC HAL module to compute the I2S1 clock source
134 | * frequency.
135 | */
136 | #if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
137 | #define EXTERNAL_I2S1_CLOCK_VALUE 12288000U /*!< Value of the I2S1 External clock source in Hz*/
138 | #endif /* EXTERNAL_I2S1_CLOCK_VALUE */
139 |
140 | /* Tip: To avoid modifying this file each time you need to use different HSE,
141 | === you can define the HSE value in your toolchain compiler preprocessor. */
142 |
143 | /* ########################### System Configuration ######################### */
144 | /**
145 | * @brief This is the HAL system configuration section
146 | */
147 | #define VDD_VALUE 3300U /*!< Value of VDD in mv */
148 | #define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */
149 | #define USE_RTOS 0U
150 | #define PREFETCH_ENABLE 1U
151 | #define INSTRUCTION_CACHE_ENABLE 1U
152 |
153 | /* ################## SPI peripheral configuration ########################## */
154 |
155 | /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
156 | * Activated: CRC code is present inside driver
157 | * Deactivated: CRC code cleaned from driver
158 | */
159 |
160 | #define USE_SPI_CRC 0U
161 |
162 | /* ################## CRYP peripheral configuration ########################## */
163 |
164 | #define USE_HAL_CRYP_SUSPEND_RESUME 1U
165 |
166 | /* ########################## Assert Selection ############################## */
167 | /**
168 | * @brief Uncomment the line below to expanse the "assert_param" macro in the
169 | * HAL drivers code
170 | */
171 | /* #define USE_FULL_ASSERT 1U */
172 |
173 | /* Includes ------------------------------------------------------------------*/
174 | /**
175 | * @brief Include module's header file
176 | */
177 |
178 | #ifdef HAL_RCC_MODULE_ENABLED
179 | #include "stm32g0xx_hal_rcc.h"
180 | #endif /* HAL_RCC_MODULE_ENABLED */
181 |
182 | #ifdef HAL_GPIO_MODULE_ENABLED
183 | #include "stm32g0xx_hal_gpio.h"
184 | #endif /* HAL_GPIO_MODULE_ENABLED */
185 |
186 | #ifdef HAL_DMA_MODULE_ENABLED
187 | #include "stm32g0xx_hal_dma.h"
188 | #endif /* HAL_DMA_MODULE_ENABLED */
189 |
190 | #ifdef HAL_CORTEX_MODULE_ENABLED
191 | #include "stm32g0xx_hal_cortex.h"
192 | #endif /* HAL_CORTEX_MODULE_ENABLED */
193 |
194 | #ifdef HAL_ADC_MODULE_ENABLED
195 | #include "stm32g0xx_hal_adc.h"
196 | #include "stm32g0xx_hal_adc_ex.h"
197 | #endif /* HAL_ADC_MODULE_ENABLED */
198 |
199 | #ifdef HAL_CEC_MODULE_ENABLED
200 | #include "stm32g0xx_hal_cec.h"
201 | #endif /* HAL_CEC_MODULE_ENABLED */
202 |
203 | #ifdef HAL_COMP_MODULE_ENABLED
204 | #include "stm32g0xx_hal_comp.h"
205 | #endif /* HAL_COMP_MODULE_ENABLED */
206 |
207 | #ifdef HAL_CRC_MODULE_ENABLED
208 | #include "stm32g0xx_hal_crc.h"
209 | #endif /* HAL_CRC_MODULE_ENABLED */
210 |
211 | #ifdef HAL_CRYP_MODULE_ENABLED
212 | #include "stm32g0xx_hal_cryp.h"
213 | #endif /* HAL_CRYP_MODULE_ENABLED */
214 |
215 | #ifdef HAL_DAC_MODULE_ENABLED
216 | #include "stm32g0xx_hal_dac.h"
217 | #endif /* HAL_DAC_MODULE_ENABLED */
218 |
219 | #ifdef HAL_EXTI_MODULE_ENABLED
220 | #include "stm32g0xx_hal_exti.h"
221 | #endif /* HAL_EXTI_MODULE_ENABLED */
222 |
223 | #ifdef HAL_FLASH_MODULE_ENABLED
224 | #include "stm32g0xx_hal_flash.h"
225 | #endif /* HAL_FLASH_MODULE_ENABLED */
226 |
227 | #ifdef HAL_I2C_MODULE_ENABLED
228 | #include "stm32g0xx_hal_i2c.h"
229 | #endif /* HAL_I2C_MODULE_ENABLED */
230 |
231 | #ifdef HAL_I2S_MODULE_ENABLED
232 | #include "stm32g0xx_hal_i2s.h"
233 | #endif /* HAL_I2S_MODULE_ENABLED */
234 |
235 | #ifdef HAL_IRDA_MODULE_ENABLED
236 | #include "stm32g0xx_hal_irda.h"
237 | #endif /* HAL_IRDA_MODULE_ENABLED */
238 |
239 | #ifdef HAL_IWDG_MODULE_ENABLED
240 | #include "stm32g0xx_hal_iwdg.h"
241 | #endif /* HAL_IWDG_MODULE_ENABLED */
242 |
243 | #ifdef HAL_LPTIM_MODULE_ENABLED
244 | #include "stm32g0xx_hal_lptim.h"
245 | #endif /* HAL_LPTIM_MODULE_ENABLED */
246 |
247 | #ifdef HAL_PWR_MODULE_ENABLED
248 | #include "stm32g0xx_hal_pwr.h"
249 | #endif /* HAL_PWR_MODULE_ENABLED */
250 |
251 | #ifdef HAL_RNG_MODULE_ENABLED
252 | #include "stm32g0xx_hal_rng.h"
253 | #endif /* HAL_RNG_MODULE_ENABLED */
254 |
255 | #ifdef HAL_RTC_MODULE_ENABLED
256 | #include "stm32g0xx_hal_rtc.h"
257 | #endif /* HAL_RTC_MODULE_ENABLED */
258 |
259 | #ifdef HAL_SMARTCARD_MODULE_ENABLED
260 | #include "stm32g0xx_hal_smartcard.h"
261 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */
262 |
263 | #ifdef HAL_SMBUS_MODULE_ENABLED
264 | #include "stm32g0xx_hal_smbus.h"
265 | #endif /* HAL_SMBUS_MODULE_ENABLED */
266 |
267 | #ifdef HAL_SPI_MODULE_ENABLED
268 | #include "stm32g0xx_hal_spi.h"
269 | #endif /* HAL_SPI_MODULE_ENABLED */
270 |
271 | #ifdef HAL_TIM_MODULE_ENABLED
272 | #include "stm32g0xx_hal_tim.h"
273 | #endif /* HAL_TIM_MODULE_ENABLED */
274 |
275 | #ifdef HAL_UART_MODULE_ENABLED
276 | #include "stm32g0xx_hal_uart.h"
277 | #endif /* HAL_UART_MODULE_ENABLED */
278 |
279 | #ifdef HAL_USART_MODULE_ENABLED
280 | #include "stm32g0xx_hal_usart.h"
281 | #endif /* HAL_USART_MODULE_ENABLED */
282 |
283 | #ifdef HAL_WWDG_MODULE_ENABLED
284 | #include "stm32g0xx_hal_wwdg.h"
285 | #endif /* HAL_WWDG_MODULE_ENABLED */
286 |
287 | /* Exported macro ------------------------------------------------------------*/
288 | #ifdef USE_FULL_ASSERT
289 | /**
290 | * @brief The assert_param macro is used for functions parameters check.
291 | * @param expr If expr is false, it calls assert_failed function
292 | * which reports the name of the source file and the source
293 | * line number of the call that failed.
294 | * If expr is true, it returns no value.
295 | * @retval None
296 | */
297 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
298 | /* Exported functions ------------------------------------------------------- */
299 | void assert_failed(uint8_t *file, uint32_t line);
300 | #else
301 | #define assert_param(expr) ((void)0U)
302 | #endif /* USE_FULL_ASSERT */
303 |
304 | #ifdef __cplusplus
305 | }
306 | #endif
307 |
308 | #endif /* STM32G0xx_HAL_CONF_H */
309 |
310 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
311 |
--------------------------------------------------------------------------------
/Inc/stm32g0xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g0xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32G0xx_IT_H
23 | #define __STM32G0xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void SVC_Handler(void);
53 | void PendSV_Handler(void);
54 | void SysTick_Handler(void);
55 | void DMA1_Channel1_IRQHandler(void);
56 | void DMA1_Channel2_3_IRQHandler(void);
57 | void ADC1_IRQHandler(void);
58 | void TIM3_IRQHandler(void);
59 | void USART2_IRQHandler(void);
60 | /* USER CODE BEGIN EFP */
61 |
62 | /* USER CODE END EFP */
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __STM32G0xx_IT_H */
69 |
70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
71 |
--------------------------------------------------------------------------------
/Inc/tim.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : TIM.h
4 | * Description : This file provides code for the configuration
5 | * of the TIM instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __tim_H
21 | #define __tim_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern TIM_HandleTypeDef htim1;
34 | extern TIM_HandleTypeDef htim3;
35 |
36 | /* USER CODE BEGIN Private defines */
37 |
38 | /* USER CODE END Private defines */
39 |
40 | void MX_TIM1_Init(void);
41 | void MX_TIM3_Init(void);
42 |
43 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
44 |
45 | /* USER CODE BEGIN Prototypes */
46 |
47 | /* USER CODE END Prototypes */
48 |
49 | #ifdef __cplusplus
50 | }
51 | #endif
52 | #endif /*__ tim_H */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
63 |
--------------------------------------------------------------------------------
/Inc/usart.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : USART.h
4 | * Description : This file provides code for the configuration
5 | * of the USART instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef __usart_H
21 | #define __usart_H
22 | #ifdef __cplusplus
23 | extern "C" {
24 | #endif
25 |
26 | /* Includes ------------------------------------------------------------------*/
27 | #include "main.h"
28 |
29 | /* USER CODE BEGIN Includes */
30 |
31 | /* USER CODE END Includes */
32 |
33 | extern UART_HandleTypeDef huart2;
34 |
35 | /* USER CODE BEGIN Private defines */
36 |
37 | /* USER CODE END Private defines */
38 |
39 | void MX_USART2_UART_Init(void);
40 |
41 | /* USER CODE BEGIN Prototypes */
42 |
43 | /* USER CODE END Prototypes */
44 |
45 | #ifdef __cplusplus
46 | }
47 | #endif
48 | #endif /*__ usart_H */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 | /**
55 | * @}
56 | */
57 |
58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
59 |
--------------------------------------------------------------------------------
/MDK-ARM/RTE/_drone/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'drone'
7 | * Target: 'drone'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32g0xx.h"
18 |
19 |
20 |
21 | #endif /* RTE_COMPONENTS_H */
22 |
--------------------------------------------------------------------------------
/MDK-ARM/startup_stm32g030xx.s:
--------------------------------------------------------------------------------
1 | ;******************************************************************************
2 | ;* File Name : startup_stm32g030xx.s
3 | ;* Author : MCD Application Team
4 | ;* Description : STM32G030xx devices vector table for MDK-ARM toolchain.
5 | ;* This module performs:
6 | ;* - Set the initial SP
7 | ;* - Set the initial PC == Reset_Handler
8 | ;* - Set the vector table entries with the exceptions ISR address
9 | ;* - Branches to __main in the C library (which eventually
10 | ;* calls main()).
11 | ;* After Reset the CortexM0 processor is in Thread mode,
12 | ;* priority is Privileged, and the Stack is set to Main.
13 | ;* <<< Use Configuration Wizard in Context Menu >>>
14 | ;******************************************************************************
15 | ;* @attention
16 | ;*
17 | ;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
18 | ;*
19 | ;* This software component is licensed by ST under BSD 3-Clause license,
20 | ;* the "License"; You may not use this file except in compliance with the
21 | ;* License. You may obtain a copy of the License at:
22 | ;* opensource.org/licenses/BSD-3-Clause
23 | ;*
24 | ;******************************************************************************
25 |
26 | ; Amount of memory (in bytes) allocated for Stack
27 | ; Tailor this value to your application needs
28 | ; Stack Configuration
29 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
30 | ;
31 |
32 | Stack_Size EQU 0x400
33 |
34 | AREA STACK, NOINIT, READWRITE, ALIGN=3
35 | Stack_Mem SPACE Stack_Size
36 | __initial_sp
37 |
38 |
39 | ; Heap Configuration
40 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
41 | ;
42 |
43 | Heap_Size EQU 0x200
44 |
45 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
46 | __heap_base
47 | Heap_Mem SPACE Heap_Size
48 | __heap_limit
49 |
50 | PRESERVE8
51 | THUMB
52 |
53 |
54 | ; Vector Table Mapped to Address 0 at Reset
55 | AREA RESET, DATA, READONLY
56 | EXPORT __Vectors
57 | EXPORT __Vectors_End
58 | EXPORT __Vectors_Size
59 |
60 | __Vectors DCD __initial_sp ; Top of Stack
61 | DCD Reset_Handler ; Reset Handler
62 | DCD NMI_Handler ; NMI Handler
63 | DCD HardFault_Handler ; Hard Fault Handler
64 | DCD 0 ; Reserved
65 | DCD 0 ; Reserved
66 | DCD 0 ; Reserved
67 | DCD 0 ; Reserved
68 | DCD 0 ; Reserved
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD SVC_Handler ; SVCall Handler
72 | DCD 0 ; Reserved
73 | DCD 0 ; Reserved
74 | DCD PendSV_Handler ; PendSV Handler
75 | DCD SysTick_Handler ; SysTick Handler
76 |
77 | ; External Interrupts
78 | DCD WWDG_IRQHandler ; Window Watchdog
79 | DCD 0 ; Reserved
80 | DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line
81 | DCD FLASH_IRQHandler ; FLASH
82 | DCD RCC_IRQHandler ; RCC
83 | DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
84 | DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
85 | DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
86 | DCD 0 ; Reserved
87 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
88 | DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
89 | DCD DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 5, DMAMUX1 overrun
90 | DCD ADC1_IRQHandler ; ADC1
91 | DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
92 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
93 | DCD 0 ; Reserved
94 | DCD TIM3_IRQHandler ; TIM3
95 | DCD 0 ; Reserved
96 | DCD 0 ; Reserved
97 | DCD TIM14_IRQHandler ; TIM14
98 | DCD 0 ; Reserved
99 | DCD TIM16_IRQHandler ; TIM16
100 | DCD TIM17_IRQHandler ; TIM17
101 | DCD I2C1_IRQHandler ; I2C1
102 | DCD I2C2_IRQHandler ; I2C2
103 | DCD SPI1_IRQHandler ; SPI1
104 | DCD SPI2_IRQHandler ; SPI2
105 | DCD USART1_IRQHandler ; USART1
106 | DCD USART2_IRQHandler ; USART2
107 | DCD 0 ; Reserved
108 | DCD 0 ; Reserved
109 | DCD 0 ; Reserved
110 |
111 | __Vectors_End
112 |
113 | __Vectors_Size EQU __Vectors_End - __Vectors
114 |
115 | AREA |.text|, CODE, READONLY
116 |
117 | ; Reset handler routine
118 | Reset_Handler PROC
119 | EXPORT Reset_Handler [WEAK]
120 | IMPORT __main
121 | IMPORT SystemInit
122 | LDR R0, =SystemInit
123 | BLX R0
124 | LDR R0, =__main
125 | BX R0
126 | ENDP
127 |
128 | ; Dummy Exception Handlers (infinite loops which can be modified)
129 |
130 | NMI_Handler PROC
131 | EXPORT NMI_Handler [WEAK]
132 | B .
133 | ENDP
134 | HardFault_Handler\
135 | PROC
136 | EXPORT HardFault_Handler [WEAK]
137 | B .
138 | ENDP
139 | SVC_Handler PROC
140 | EXPORT SVC_Handler [WEAK]
141 | B .
142 | ENDP
143 | PendSV_Handler PROC
144 | EXPORT PendSV_Handler [WEAK]
145 | B .
146 | ENDP
147 | SysTick_Handler PROC
148 | EXPORT SysTick_Handler [WEAK]
149 | B .
150 | ENDP
151 |
152 | Default_Handler PROC
153 |
154 | EXPORT WWDG_IRQHandler [WEAK]
155 | EXPORT RTC_TAMP_IRQHandler [WEAK]
156 | EXPORT FLASH_IRQHandler [WEAK]
157 | EXPORT RCC_IRQHandler [WEAK]
158 | EXPORT EXTI0_1_IRQHandler [WEAK]
159 | EXPORT EXTI2_3_IRQHandler [WEAK]
160 | EXPORT EXTI4_15_IRQHandler [WEAK]
161 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
162 | EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
163 | EXPORT DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler [WEAK]
164 | EXPORT ADC1_IRQHandler [WEAK]
165 | EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
166 | EXPORT TIM1_CC_IRQHandler [WEAK]
167 | EXPORT TIM3_IRQHandler [WEAK]
168 | EXPORT TIM14_IRQHandler [WEAK]
169 | EXPORT TIM16_IRQHandler [WEAK]
170 | EXPORT TIM17_IRQHandler [WEAK]
171 | EXPORT I2C1_IRQHandler [WEAK]
172 | EXPORT I2C2_IRQHandler [WEAK]
173 | EXPORT SPI1_IRQHandler [WEAK]
174 | EXPORT SPI2_IRQHandler [WEAK]
175 | EXPORT USART1_IRQHandler [WEAK]
176 | EXPORT USART2_IRQHandler [WEAK]
177 |
178 |
179 | WWDG_IRQHandler
180 | RTC_TAMP_IRQHandler
181 | FLASH_IRQHandler
182 | RCC_IRQHandler
183 | EXTI0_1_IRQHandler
184 | EXTI2_3_IRQHandler
185 | EXTI4_15_IRQHandler
186 | DMA1_Channel1_IRQHandler
187 | DMA1_Channel2_3_IRQHandler
188 | DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
189 | ADC1_IRQHandler
190 | TIM1_BRK_UP_TRG_COM_IRQHandler
191 | TIM1_CC_IRQHandler
192 | TIM3_IRQHandler
193 | TIM14_IRQHandler
194 | TIM16_IRQHandler
195 | TIM17_IRQHandler
196 | I2C1_IRQHandler
197 | I2C2_IRQHandler
198 | SPI1_IRQHandler
199 | SPI2_IRQHandler
200 | USART1_IRQHandler
201 | USART2_IRQHandler
202 |
203 | B .
204 |
205 | ENDP
206 |
207 | ALIGN
208 |
209 | ;*******************************************************************************
210 | ; User Stack and Heap initialization
211 | ;*******************************************************************************
212 | IF :DEF:__MICROLIB
213 |
214 | EXPORT __initial_sp
215 | EXPORT __heap_base
216 | EXPORT __heap_limit
217 |
218 | ELSE
219 |
220 | IMPORT __use_two_region_memory
221 | EXPORT __user_initial_stackheap
222 |
223 | __user_initial_stackheap
224 |
225 | LDR R0, = Heap_Mem
226 | LDR R1, =(Stack_Mem + Stack_Size)
227 | LDR R2, = (Heap_Mem + Heap_Size)
228 | LDR R3, = Stack_Mem
229 | BX LR
230 |
231 | ALIGN
232 |
233 | ENDIF
234 |
235 | END
236 |
237 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
238 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # 小四轴飞控
2 |
3 | 
4 |
5 | [](https://app.codacy.com/gh/uav-operation-system/Drone_Master_ADRC?utm_source=github.com&utm_medium=referral&utm_content=uav-operation-system/Drone_Master_ADRC&utm_campaign=Badge_Grade_Dashboard)
6 |
7 | version V1.02
8 |
9 | HEAD
10 | M2 ↑ M3
11 |
12 | \ /
13 |
14 | \ /
15 |
16 | \ /
17 |
18 | / \
19 |
20 | / \
21 |
22 | / \
23 |
24 | M1 M4
25 |
26 | 
27 |
28 | 电机M1至M4分别为逆顺逆顺。
29 |
30 | 默认为姿态模式,可通过地面站进行更改。
31 |
32 | [地面站](https://github.com/XDU-Educational-UAV/GroundStation/releases)
33 |
34 | # 代码说明
35 | version V1.06
36 |
37 | ### 用户代码
38 | 尽量不改动自动生成的代码文件，用户添加的代码文件在user文件夹中，与自动生成的代码文件分离。
39 | 自动生成的代码文件中加入的用户代码包括:
40 | 1. main.c:初始化,死循环,定时器3任务调度
41 | 2. main.h:数据类型定义,如u8,u16,u32等;IO端口定义,如LED1_PORT,STAT_PORT等
42 | 3. adc.c:测电池电压函数
43 | 用户代码文件中存在的底层代码包括:
44 | 1. mpuiic.c mpuiic.h:
45 | 2. protocol.c:串口发送和接收完成回调函数
46 |
47 | ### 变量/函数/宏定义命名格式
48 | 变量:全部小写或首字母大写 xxx/Xxx/XxxXxx
49 | 函数:首字母大写加下划线分隔 Xxx_Xxx()
50 | 宏定义:全部大写加下划线分隔 XXX_XXX
51 |
52 | ### 控制链路
53 | 控制协议见 https://github.com/XDU-Educational-UAV/GroundStation
54 |
55 | 锁定与解锁均需要上位机发送正确的指令。
56 |
57 | 起飞后（即油门超过一定值）2秒内未接收到正确的遥控信号或飞机姿态倾角过大，将进入失控保护模式尝试平稳降落，
58 | 长时间未收到信号则关闭油门。重新收到信号或姿态恢复正常则可随时恢复控制。
59 |
60 | 解锁后2秒内未接收到正确的遥控信号自动锁定。
61 |
62 | 起飞前建议进行传感器校准。
63 |
64 | ### 控制与调参
65 | 
66 |
67 | 注：图中的控制器相关的增益参数为横滚方向参考值，不同的飞机可能需要另外调整。
68 |
69 | 内环控制频率500Hz，外环控制频率100Hz。
70 |
71 | 每个通道的控制器关键运行参数范围大致如下(一般在范围内，不排除超过范围的可能):
72 |
73 | 控制器输出u:±
74 | 角速度(°/s)gyro:±1000
75 | 角加速度(°/s^2)AccEst±1000
76 | 总扰动w:±
77 |
78 | 调参方法：
79 | 1. 将飞行模式更改为速度模式；
80 | 2. 将Kp与Kd置0；
81 | 3. 先将B取一个较大的值，逐渐减小直到出现任何微小的自激振荡现象时，再适当增大；
82 | 4. 此时被控对象将表现出近似双积分器串联的形式，开始调Kp与Kd；
83 | 5. 此时Kp与Kd近似满足wc²与2×wc的关系，与PID的调参方法也类似。
84 |
85 | 注意：
86 | * 如果有条件进行参数辨识，可以辨识出B的值，具体请参考ADRC相关资料。
87 | * 如果觉得观测器带宽不合适则需要在程序中修改。
88 | * B的值不能取0，否则后果自负。
89 |
90 | ### 版本更新
91 | V1.06更新内容
92 |
93 | * 对LADRC稍作更改
94 | * 发送高速数据期间禁止其它发送任务
95 |
96 | 此版本通过了飞行测试。
97 | =======
98 | [地面站](https://github.com/XDU-Educational-UAV/GroundStation/blob/master/GroundStation/bin/Release/GroundStation.exe)
99 |
100 | ## 代码说明
101 |
102 | ### 用户代码
103 | 尽量不改动自动生成的代码文件，用户添加的代码文件在user文件夹中，与自动生成的代码文件分离。
104 |
105 | 自动生成的代码文件中加入的用户代码包括:
106 |
107 | 1. main.c:初始化,死循环,定时器3任务调度
108 |
109 | 2. main.h:数据类型定义,如u8,u16,u32等;IO端口定义,如LED1_PORT,STAT_PORT等
110 |
111 | 3. adc.c:测电池电压函数
112 |
113 | 用户代码文件中存在的底层代码包括:
114 |
115 | 1. mpuiic.c mpuiic.h:
116 |
117 | 2. protocol.c:串口发送和接收完成回调函数
118 |
119 | ### 变量/函数/宏定义命名格式
120 | 变量:全部小写或首字母大写 xxx/Xxx/XxxXxx
121 |
122 | 函数:首字母大写加下划线分隔 Xxx_Xxx()
123 |
124 | 宏定义:全部大写加下划线分隔 XXX_XXX
125 |
126 | ### 控制链路
127 | 控制协议见 https://github.com/XDU-Educational-UAV/GroundStation
128 |
129 | 锁定与解锁均需要上位机发送正确的指令。
130 |
131 | 起飞后（即油门超过一定值）2秒内未接收到正确的遥控信号或飞机姿态倾角过大，将进入失控保护模式尝试平稳降落，重新收到信号或姿态恢复正常则可随时恢复控制。
132 |
133 | 解锁后2秒内未接收到正确的遥控信号自动锁定。
134 |
135 | 起飞前建议进行传感器校准。
136 |
137 | ## bug与隐患
138 |
--------------------------------------------------------------------------------
/Src/adc.c:
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https://raw.githubusercontent.com/XDU-Educational-UAV/Drone_Master_ADRC/0370a958ae8152d38db1626389214440f4073242/Src/adc.c
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/Src/dma.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : dma.c
4 | * Description : This file provides code for the configuration
5 | * of all the requested memory to memory DMA transfers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "dma.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | /*----------------------------------------------------------------------------*/
28 | /* Configure DMA */
29 | /*----------------------------------------------------------------------------*/
30 |
31 | /* USER CODE BEGIN 1 */
32 |
33 | /* USER CODE END 1 */
34 |
35 | /**
36 | * Enable DMA controller clock
37 | */
38 | void MX_DMA_Init(void)
39 | {
40 |
41 | /* DMA controller clock enable */
42 | __HAL_RCC_DMA1_CLK_ENABLE();
43 |
44 | /* DMA interrupt init */
45 | /* DMA1_Channel1_IRQn interrupt configuration */
46 | HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
47 | HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
48 | /* DMA1_Channel2_3_IRQn interrupt configuration */
49 | HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
50 | HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
51 |
52 | }
53 |
54 | /* USER CODE BEGIN 2 */
55 |
56 | /* USER CODE END 2 */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
67 |
--------------------------------------------------------------------------------
/Src/gpio.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : gpio.c
4 | * Description : This file provides code for the configuration
5 | * of all used GPIO pins.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "gpio.h"
22 | /* USER CODE BEGIN 0 */
23 |
24 | /* USER CODE END 0 */
25 |
26 | /*----------------------------------------------------------------------------*/
27 | /* Configure GPIO */
28 | /*----------------------------------------------------------------------------*/
29 | /* USER CODE BEGIN 1 */
30 |
31 | /* USER CODE END 1 */
32 |
33 | /** Configure pins as
34 | * Analog
35 | * Input
36 | * Output
37 | * EVENT_OUT
38 | * EXTI
39 | */
40 | void MX_GPIO_Init(void)
41 | {
42 |
43 | GPIO_InitTypeDef GPIO_InitStruct = {0};
44 |
45 | /* GPIO Ports Clock Enable */
46 | __HAL_RCC_GPIOA_CLK_ENABLE();
47 | __HAL_RCC_GPIOC_CLK_ENABLE();
48 | __HAL_RCC_GPIOB_CLK_ENABLE();
49 |
50 | /*Configure GPIO pin Output Level */
51 | HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET);
52 |
53 | /*Configure GPIO pin Output Level */
54 | HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
55 |
56 | /*Configure GPIO pin Output Level */
57 | HAL_GPIO_WritePin(GPIOB, LED2_Pin|LED1_Pin|SDA_Pin|SCL_Pin, GPIO_PIN_RESET);
58 |
59 | /*Configure GPIO pin : PtPin */
60 | GPIO_InitStruct.Pin = STAT_Pin;
61 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
62 | GPIO_InitStruct.Pull = GPIO_PULLDOWN;
63 | HAL_GPIO_Init(STAT_GPIO_Port, &GPIO_InitStruct);
64 |
65 | /*Configure GPIO pin : PtPin */
66 | GPIO_InitStruct.Pin = LED4_Pin;
67 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
68 | GPIO_InitStruct.Pull = GPIO_NOPULL;
69 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
70 | HAL_GPIO_Init(LED4_GPIO_Port, &GPIO_InitStruct);
71 |
72 | /*Configure GPIO pin : PtPin */
73 | GPIO_InitStruct.Pin = LED3_Pin;
74 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
75 | GPIO_InitStruct.Pull = GPIO_NOPULL;
76 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
77 | HAL_GPIO_Init(LED3_GPIO_Port, &GPIO_InitStruct);
78 |
79 | /*Configure GPIO pins : PBPin PBPin PBPin PBPin */
80 | GPIO_InitStruct.Pin = LED2_Pin|LED1_Pin|SDA_Pin|SCL_Pin;
81 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
82 | GPIO_InitStruct.Pull = GPIO_NOPULL;
83 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
84 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
85 |
86 | }
87 |
88 | /* USER CODE BEGIN 2 */
89 |
90 | /* USER CODE END 2 */
91 |
92 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
93 |
--------------------------------------------------------------------------------
/Src/iwdg.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : IWDG.c
4 | * Description : This file provides code for the configuration
5 | * of the IWDG instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "iwdg.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | IWDG_HandleTypeDef hiwdg;
28 |
29 | /* IWDG init function */
30 | void MX_IWDG_Init(void)
31 | {
32 |
33 | hiwdg.Instance = IWDG;
34 | hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
35 | hiwdg.Init.Window = 4095;
36 | hiwdg.Init.Reload = 4095;
37 | if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
38 | {
39 | Error_Handler();
40 | }
41 |
42 | }
43 |
44 | /* USER CODE BEGIN 1 */
45 |
46 | /* USER CODE END 1 */
47 |
48 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
49 |
--------------------------------------------------------------------------------
/Src/main.c:
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/Src/stm32g0xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * File Name : stm32g0xx_hal_msp.c
5 | * Description : This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /* USER CODE BEGIN MspInit 1 */
76 |
77 | /* USER CODE END MspInit 1 */
78 | }
79 |
80 | /* USER CODE BEGIN 1 */
81 |
82 | /* USER CODE END 1 */
83 |
84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
85 |
--------------------------------------------------------------------------------
/Src/stm32g0xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g0xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32g0xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 | extern DMA_HandleTypeDef hdma_adc1;
60 | extern ADC_HandleTypeDef hadc1;
61 | extern TIM_HandleTypeDef htim3;
62 | extern DMA_HandleTypeDef hdma_usart2_rx;
63 | extern DMA_HandleTypeDef hdma_usart2_tx;
64 | extern UART_HandleTypeDef huart2;
65 | /* USER CODE BEGIN EV */
66 |
67 | /* USER CODE END EV */
68 |
69 | /******************************************************************************/
70 | /* Cortex-M0+ Processor Interruption and Exception Handlers */
71 | /******************************************************************************/
72 | /**
73 | * @brief This function handles Non maskable interrupt.
74 | */
75 | void NMI_Handler(void)
76 | {
77 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
78 |
79 | /* USER CODE END NonMaskableInt_IRQn 0 */
80 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
81 |
82 | /* USER CODE END NonMaskableInt_IRQn 1 */
83 | }
84 |
85 | /**
86 | * @brief This function handles Hard fault interrupt.
87 | */
88 | void HardFault_Handler(void)
89 | {
90 | /* USER CODE BEGIN HardFault_IRQn 0 */
91 |
92 | /* USER CODE END HardFault_IRQn 0 */
93 | while (1)
94 | {
95 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
96 | /* USER CODE END W1_HardFault_IRQn 0 */
97 | }
98 | }
99 |
100 | /**
101 | * @brief This function handles System service call via SWI instruction.
102 | */
103 | void SVC_Handler(void)
104 | {
105 | /* USER CODE BEGIN SVC_IRQn 0 */
106 |
107 | /* USER CODE END SVC_IRQn 0 */
108 | /* USER CODE BEGIN SVC_IRQn 1 */
109 |
110 | /* USER CODE END SVC_IRQn 1 */
111 | }
112 |
113 | /**
114 | * @brief This function handles Pendable request for system service.
115 | */
116 | void PendSV_Handler(void)
117 | {
118 | /* USER CODE BEGIN PendSV_IRQn 0 */
119 |
120 | /* USER CODE END PendSV_IRQn 0 */
121 | /* USER CODE BEGIN PendSV_IRQn 1 */
122 |
123 | /* USER CODE END PendSV_IRQn 1 */
124 | }
125 |
126 | /**
127 | * @brief This function handles System tick timer.
128 | */
129 | void SysTick_Handler(void)
130 | {
131 | /* USER CODE BEGIN SysTick_IRQn 0 */
132 |
133 | /* USER CODE END SysTick_IRQn 0 */
134 | HAL_IncTick();
135 | /* USER CODE BEGIN SysTick_IRQn 1 */
136 |
137 | /* USER CODE END SysTick_IRQn 1 */
138 | }
139 |
140 | /******************************************************************************/
141 | /* STM32G0xx Peripheral Interrupt Handlers */
142 | /* Add here the Interrupt Handlers for the used peripherals. */
143 | /* For the available peripheral interrupt handler names, */
144 | /* please refer to the startup file (startup_stm32g0xx.s). */
145 | /******************************************************************************/
146 |
147 | /**
148 | * @brief This function handles DMA1 channel 1 interrupt.
149 | */
150 | void DMA1_Channel1_IRQHandler(void)
151 | {
152 | /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
153 |
154 | /* USER CODE END DMA1_Channel1_IRQn 0 */
155 | HAL_DMA_IRQHandler(&hdma_usart2_rx);
156 | /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
157 |
158 | /* USER CODE END DMA1_Channel1_IRQn 1 */
159 | }
160 |
161 | /**
162 | * @brief This function handles DMA1 channel 2 and channel 3 interrupts.
163 | */
164 | void DMA1_Channel2_3_IRQHandler(void)
165 | {
166 | /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
167 |
168 | /* USER CODE END DMA1_Channel2_3_IRQn 0 */
169 | HAL_DMA_IRQHandler(&hdma_usart2_tx);
170 | HAL_DMA_IRQHandler(&hdma_adc1);
171 | /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
172 |
173 | /* USER CODE END DMA1_Channel2_3_IRQn 1 */
174 | }
175 |
176 | /**
177 | * @brief This function handles ADC1 interrupt.
178 | */
179 | void ADC1_IRQHandler(void)
180 | {
181 | /* USER CODE BEGIN ADC1_IRQn 0 */
182 |
183 | /* USER CODE END ADC1_IRQn 0 */
184 | HAL_ADC_IRQHandler(&hadc1);
185 | /* USER CODE BEGIN ADC1_IRQn 1 */
186 |
187 | /* USER CODE END ADC1_IRQn 1 */
188 | }
189 |
190 | /**
191 | * @brief This function handles TIM3 global interrupt.
192 | */
193 | void TIM3_IRQHandler(void)
194 | {
195 | /* USER CODE BEGIN TIM3_IRQn 0 */
196 |
197 | /* USER CODE END TIM3_IRQn 0 */
198 | HAL_TIM_IRQHandler(&htim3);
199 | /* USER CODE BEGIN TIM3_IRQn 1 */
200 |
201 | /* USER CODE END TIM3_IRQn 1 */
202 | }
203 |
204 | /**
205 | * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
206 | */
207 | void USART2_IRQHandler(void)
208 | {
209 | /* USER CODE BEGIN USART2_IRQn 0 */
210 |
211 | /* USER CODE END USART2_IRQn 0 */
212 | HAL_UART_IRQHandler(&huart2);
213 | /* USER CODE BEGIN USART2_IRQn 1 */
214 |
215 | /* USER CODE END USART2_IRQn 1 */
216 | }
217 |
218 | /* USER CODE BEGIN 1 */
219 |
220 | /* USER CODE END 1 */
221 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
222 |
--------------------------------------------------------------------------------
/Src/system_stm32g0xx.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32g0xx.c
4 | * @author MCD Application Team
5 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
6 | *
7 | * This file provides two functions and one global variable to be called from
8 | * user application:
9 | * - SystemInit(): This function is called at startup just after reset and
10 | * before branch to main program. This call is made inside
11 | * the "startup_stm32g0xx.s" file.
12 | *
13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 | * by the user application to setup the SysTick
15 | * timer or configure other parameters.
16 | *
17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 | * be called whenever the core clock is changed
19 | * during program execution.
20 | *
21 | * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
22 | * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
23 | * configure the system clock before to branch to main program.
24 | *
25 | * This file configures the system clock as follows:
26 | *=============================================================================
27 | *-----------------------------------------------------------------------------
28 | * System Clock source | HSI
29 | *-----------------------------------------------------------------------------
30 | * SYSCLK(Hz) | 16000000
31 | *-----------------------------------------------------------------------------
32 | * HCLK(Hz) | 16000000
33 | *-----------------------------------------------------------------------------
34 | * AHB Prescaler | 1
35 | *-----------------------------------------------------------------------------
36 | * APB Prescaler | 1
37 | *-----------------------------------------------------------------------------
38 | * HSI Division factor | 1
39 | *-----------------------------------------------------------------------------
40 | * PLL_M | 1
41 | *-----------------------------------------------------------------------------
42 | * PLL_N | 8
43 | *-----------------------------------------------------------------------------
44 | * PLL_P | 7
45 | *-----------------------------------------------------------------------------
46 | * PLL_Q | 2
47 | *-----------------------------------------------------------------------------
48 | * PLL_R | 2
49 | *-----------------------------------------------------------------------------
50 | * Require 48MHz for RNG | Disabled
51 | *-----------------------------------------------------------------------------
52 | *=============================================================================
53 | ******************************************************************************
54 | * @attention
55 | *
56 | * © Copyright (c) 2018 STMicroelectronics.
57 | * All rights reserved.
58 | *
59 | * This software component is licensed by ST under BSD 3-Clause license,
60 | * the "License"; You may not use this file except in compliance with the
61 | * License. You may obtain a copy of the License at:
62 | * opensource.org/licenses/BSD-3-Clause
63 | *
64 | ******************************************************************************
65 | */
66 |
67 | /** @addtogroup CMSIS
68 | * @{
69 | */
70 |
71 | /** @addtogroup stm32g0xx_system
72 | * @{
73 | */
74 |
75 | /** @addtogroup STM32G0xx_System_Private_Includes
76 | * @{
77 | */
78 |
79 | #include "stm32g0xx.h"
80 |
81 | #if !defined (HSE_VALUE)
82 | #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
83 | #endif /* HSE_VALUE */
84 |
85 | #if !defined (HSI_VALUE)
86 | #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
87 | #endif /* HSI_VALUE */
88 |
89 | #if !defined (LSI_VALUE)
90 | #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
91 | #endif /* LSI_VALUE */
92 |
93 | #if !defined (LSE_VALUE)
94 | #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
95 | #endif /* LSE_VALUE */
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /** @addtogroup STM32G0xx_System_Private_TypesDefinitions
102 | * @{
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /** @addtogroup STM32G0xx_System_Private_Defines
110 | * @{
111 | */
112 |
113 | /************************* Miscellaneous Configuration ************************/
114 | /*!< Uncomment the following line if you need to relocate your vector Table in
115 | Internal SRAM. */
116 | /* #define VECT_TAB_SRAM */
117 | #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
118 | This value must be a multiple of 0x100. */
119 | /******************************************************************************/
120 | /**
121 | * @}
122 | */
123 |
124 | /** @addtogroup STM32G0xx_System_Private_Macros
125 | * @{
126 | */
127 |
128 | /**
129 | * @}
130 | */
131 |
132 | /** @addtogroup STM32G0xx_System_Private_Variables
133 | * @{
134 | */
135 | /* The SystemCoreClock variable is updated in three ways:
136 | 1) by calling CMSIS function SystemCoreClockUpdate()
137 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
138 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
139 | Note: If you use this function to configure the system clock; then there
140 | is no need to call the 2 first functions listed above, since SystemCoreClock
141 | variable is updated automatically.
142 | */
143 | uint32_t SystemCoreClock = 16000000UL;
144 |
145 | const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
146 | const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
153 | * @{
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /** @addtogroup STM32G0xx_System_Private_Functions
161 | * @{
162 | */
163 |
164 | /**
165 | * @brief Setup the microcontroller system.
166 | * @param None
167 | * @retval None
168 | */
169 | void SystemInit(void)
170 | {
171 | /* Configure the Vector Table location add offset address ------------------*/
172 | #ifdef VECT_TAB_SRAM
173 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
174 | #else
175 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
176 | #endif
177 | }
178 |
179 | /**
180 | * @brief Update SystemCoreClock variable according to Clock Register Values.
181 | * The SystemCoreClock variable contains the core clock (HCLK), it can
182 | * be used by the user application to setup the SysTick timer or configure
183 | * other parameters.
184 | *
185 | * @note Each time the core clock (HCLK) changes, this function must be called
186 | * to update SystemCoreClock variable value. Otherwise, any configuration
187 | * based on this variable will be incorrect.
188 | *
189 | * @note - The system frequency computed by this function is not the real
190 | * frequency in the chip. It is calculated based on the predefined
191 | * constant and the selected clock source:
192 | *
193 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
194 | *
195 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
196 | *
197 | * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
198 | *
199 | * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
200 | *
201 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
202 | * or HSI_VALUE(*) multiplied/divided by the PLL factors.
203 | *
204 | * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
205 | * 16 MHz) but the real value may vary depending on the variations
206 | * in voltage and temperature.
207 | *
208 | * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
209 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real
210 | * frequency of the crystal used. Otherwise, this function may
211 | * have wrong result.
212 | *
213 | * - The result of this function could be not correct when using fractional
214 | * value for HSE crystal.
215 | *
216 | * @param None
217 | * @retval None
218 | */
219 | void SystemCoreClockUpdate(void)
220 | {
221 | uint32_t tmp;
222 | uint32_t pllvco;
223 | uint32_t pllr;
224 | uint32_t pllsource;
225 | uint32_t pllm;
226 | uint32_t hsidiv;
227 |
228 | /* Get SYSCLK source -------------------------------------------------------*/
229 | switch (RCC->CFGR & RCC_CFGR_SWS)
230 | {
231 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
232 | SystemCoreClock = HSE_VALUE;
233 | break;
234 |
235 | case RCC_CFGR_SWS_LSI: /* LSI used as system clock */
236 | SystemCoreClock = LSI_VALUE;
237 | break;
238 |
239 | case RCC_CFGR_SWS_LSE: /* LSE used as system clock */
240 | SystemCoreClock = LSE_VALUE;
241 | break;
242 |
243 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
244 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
245 | SYSCLK = PLL_VCO / PLLR
246 | */
247 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
248 | pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
249 |
250 | if(pllsource == 0x03UL) /* HSE used as PLL clock source */
251 | {
252 | pllvco = (HSE_VALUE / pllm);
253 | }
254 | else /* HSI used as PLL clock source */
255 | {
256 | pllvco = (HSI_VALUE / pllm);
257 | }
258 | pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
259 | pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
260 |
261 | SystemCoreClock = pllvco/pllr;
262 | break;
263 |
264 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
265 | default: /* HSI used as system clock */
266 | hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
267 | SystemCoreClock = (HSI_VALUE/hsidiv);
268 | break;
269 | }
270 | /* Compute HCLK clock frequency --------------------------------------------*/
271 | /* Get HCLK prescaler */
272 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
273 | /* HCLK clock frequency */
274 | SystemCoreClock >>= tmp;
275 | }
276 |
277 |
278 | /**
279 | * @}
280 | */
281 |
282 | /**
283 | * @}
284 | */
285 |
286 | /**
287 | * @}
288 | */
289 |
290 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
291 |
--------------------------------------------------------------------------------
/Src/tim.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : TIM.c
4 | * Description : This file provides code for the configuration
5 | * of the TIM instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "tim.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | TIM_HandleTypeDef htim1;
28 | TIM_HandleTypeDef htim3;
29 |
30 | /* TIM1 init function */
31 | void MX_TIM1_Init(void)
32 | {
33 | TIM_ClockConfigTypeDef sClockSourceConfig = {0};
34 | TIM_MasterConfigTypeDef sMasterConfig = {0};
35 | TIM_OC_InitTypeDef sConfigOC = {0};
36 | TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
37 |
38 | htim1.Instance = TIM1;
39 | htim1.Init.Prescaler = 3;
40 | htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
41 | htim1.Init.Period = 999;
42 | htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
43 | htim1.Init.RepetitionCounter = 0;
44 | htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
45 | if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
46 | {
47 | Error_Handler();
48 | }
49 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
50 | if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
51 | {
52 | Error_Handler();
53 | }
54 | if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
55 | {
56 | Error_Handler();
57 | }
58 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
59 | sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
60 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
61 | if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
62 | {
63 | Error_Handler();
64 | }
65 | sConfigOC.OCMode = TIM_OCMODE_PWM1;
66 | sConfigOC.Pulse = 0;
67 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
68 | sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
69 | sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
70 | sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
71 | sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
72 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
73 | {
74 | Error_Handler();
75 | }
76 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
77 | {
78 | Error_Handler();
79 | }
80 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
81 | {
82 | Error_Handler();
83 | }
84 | if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
85 | {
86 | Error_Handler();
87 | }
88 | sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
89 | sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
90 | sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
91 | sBreakDeadTimeConfig.DeadTime = 0;
92 | sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
93 | sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
94 | sBreakDeadTimeConfig.BreakFilter = 0;
95 | sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
96 | sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
97 | sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
98 | sBreakDeadTimeConfig.Break2Filter = 0;
99 | sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
100 | sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
101 | if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
102 | {
103 | Error_Handler();
104 | }
105 | HAL_TIM_MspPostInit(&htim1);
106 |
107 | }
108 | /* TIM3 init function */
109 | void MX_TIM3_Init(void)
110 | {
111 | TIM_ClockConfigTypeDef sClockSourceConfig = {0};
112 | TIM_MasterConfigTypeDef sMasterConfig = {0};
113 |
114 | htim3.Instance = TIM3;
115 | htim3.Init.Prescaler = 63;
116 | htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
117 | htim3.Init.Period = 1999;
118 | htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
119 | htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
120 | if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
121 | {
122 | Error_Handler();
123 | }
124 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
125 | if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
126 | {
127 | Error_Handler();
128 | }
129 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
130 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
131 | if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
132 | {
133 | Error_Handler();
134 | }
135 |
136 | }
137 |
138 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
139 | {
140 |
141 | if(tim_baseHandle->Instance==TIM1)
142 | {
143 | /* USER CODE BEGIN TIM1_MspInit 0 */
144 |
145 | /* USER CODE END TIM1_MspInit 0 */
146 | /* TIM1 clock enable */
147 | __HAL_RCC_TIM1_CLK_ENABLE();
148 | /* USER CODE BEGIN TIM1_MspInit 1 */
149 |
150 | /* USER CODE END TIM1_MspInit 1 */
151 | }
152 | else if(tim_baseHandle->Instance==TIM3)
153 | {
154 | /* USER CODE BEGIN TIM3_MspInit 0 */
155 |
156 | /* USER CODE END TIM3_MspInit 0 */
157 | /* TIM3 clock enable */
158 | __HAL_RCC_TIM3_CLK_ENABLE();
159 |
160 | /* TIM3 interrupt Init */
161 | HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
162 | HAL_NVIC_EnableIRQ(TIM3_IRQn);
163 | /* USER CODE BEGIN TIM3_MspInit 1 */
164 |
165 | /* USER CODE END TIM3_MspInit 1 */
166 | }
167 | }
168 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
169 | {
170 |
171 | GPIO_InitTypeDef GPIO_InitStruct = {0};
172 | if(timHandle->Instance==TIM1)
173 | {
174 | /* USER CODE BEGIN TIM1_MspPostInit 0 */
175 |
176 | /* USER CODE END TIM1_MspPostInit 0 */
177 |
178 | __HAL_RCC_GPIOA_CLK_ENABLE();
179 | __HAL_RCC_GPIOB_CLK_ENABLE();
180 | /**TIM1 GPIO Configuration
181 | PA8 ------> TIM1_CH1
182 | PA11 [PA9] ------> TIM1_CH4
183 | PB3 ------> TIM1_CH2
184 | PB6 ------> TIM1_CH3
185 | */
186 | GPIO_InitStruct.Pin = MOTOR4_Pin|MOTOR3_Pin;
187 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
188 | GPIO_InitStruct.Pull = GPIO_NOPULL;
189 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
190 | GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
191 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
192 |
193 | GPIO_InitStruct.Pin = MOTOR2_Pin|MOTOR1_Pin;
194 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
195 | GPIO_InitStruct.Pull = GPIO_NOPULL;
196 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
197 | GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
198 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
199 |
200 | /* USER CODE BEGIN TIM1_MspPostInit 1 */
201 |
202 | /* USER CODE END TIM1_MspPostInit 1 */
203 | }
204 |
205 | }
206 |
207 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
208 | {
209 |
210 | if(tim_baseHandle->Instance==TIM1)
211 | {
212 | /* USER CODE BEGIN TIM1_MspDeInit 0 */
213 |
214 | /* USER CODE END TIM1_MspDeInit 0 */
215 | /* Peripheral clock disable */
216 | __HAL_RCC_TIM1_CLK_DISABLE();
217 | /* USER CODE BEGIN TIM1_MspDeInit 1 */
218 |
219 | /* USER CODE END TIM1_MspDeInit 1 */
220 | }
221 | else if(tim_baseHandle->Instance==TIM3)
222 | {
223 | /* USER CODE BEGIN TIM3_MspDeInit 0 */
224 |
225 | /* USER CODE END TIM3_MspDeInit 0 */
226 | /* Peripheral clock disable */
227 | __HAL_RCC_TIM3_CLK_DISABLE();
228 |
229 | /* TIM3 interrupt Deinit */
230 | HAL_NVIC_DisableIRQ(TIM3_IRQn);
231 | /* USER CODE BEGIN TIM3_MspDeInit 1 */
232 |
233 | /* USER CODE END TIM3_MspDeInit 1 */
234 | }
235 | }
236 |
237 | /* USER CODE BEGIN 1 */
238 |
239 | /* USER CODE END 1 */
240 |
241 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
242 |
--------------------------------------------------------------------------------
/Src/usart.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * File Name : USART.c
4 | * Description : This file provides code for the configuration
5 | * of the USART instances.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Includes ------------------------------------------------------------------*/
21 | #include "usart.h"
22 |
23 | /* USER CODE BEGIN 0 */
24 |
25 | /* USER CODE END 0 */
26 |
27 | UART_HandleTypeDef huart2;
28 | DMA_HandleTypeDef hdma_usart2_rx;
29 | DMA_HandleTypeDef hdma_usart2_tx;
30 |
31 | /* USART2 init function */
32 |
33 | void MX_USART2_UART_Init(void)
34 | {
35 |
36 | huart2.Instance = USART2;
37 | huart2.Init.BaudRate = 115200;
38 | huart2.Init.WordLength = UART_WORDLENGTH_8B;
39 | huart2.Init.StopBits = UART_STOPBITS_1;
40 | huart2.Init.Parity = UART_PARITY_NONE;
41 | huart2.Init.Mode = UART_MODE_TX_RX;
42 | huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
43 | huart2.Init.OverSampling = UART_OVERSAMPLING_16;
44 | huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
45 | huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
46 | huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
47 | if (HAL_UART_Init(&huart2) != HAL_OK)
48 | {
49 | Error_Handler();
50 | }
51 |
52 | }
53 |
54 | void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
55 | {
56 |
57 | GPIO_InitTypeDef GPIO_InitStruct = {0};
58 | if(uartHandle->Instance==USART2)
59 | {
60 | /* USER CODE BEGIN USART2_MspInit 0 */
61 |
62 | /* USER CODE END USART2_MspInit 0 */
63 | /* USART2 clock enable */
64 | __HAL_RCC_USART2_CLK_ENABLE();
65 |
66 | __HAL_RCC_GPIOA_CLK_ENABLE();
67 | /**USART2 GPIO Configuration
68 | PA2 ------> USART2_TX
69 | PA3 ------> USART2_RX
70 | */
71 | GPIO_InitStruct.Pin = TXD_Pin|RXD_Pin;
72 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
73 | GPIO_InitStruct.Pull = GPIO_NOPULL;
74 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
75 | GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
76 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
77 |
78 | /* USART2 DMA Init */
79 | /* USART2_RX Init */
80 | hdma_usart2_rx.Instance = DMA1_Channel1;
81 | hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
82 | hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
83 | hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
84 | hdma_usart2_rx.Init.MemInc = DMA_MINC_DISABLE;
85 | hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
86 | hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
87 | hdma_usart2_rx.Init.Mode = DMA_CIRCULAR;
88 | hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
89 | if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
90 | {
91 | Error_Handler();
92 | }
93 |
94 | __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx);
95 |
96 | /* USART2_TX Init */
97 | hdma_usart2_tx.Instance = DMA1_Channel2;
98 | hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
99 | hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
100 | hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
101 | hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
102 | hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
103 | hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
104 | hdma_usart2_tx.Init.Mode = DMA_NORMAL;
105 | hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
106 | if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
107 | {
108 | Error_Handler();
109 | }
110 |
111 | __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
112 |
113 | /* USART2 interrupt Init */
114 | HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
115 | HAL_NVIC_EnableIRQ(USART2_IRQn);
116 | /* USER CODE BEGIN USART2_MspInit 1 */
117 |
118 | /* USER CODE END USART2_MspInit 1 */
119 | }
120 | }
121 |
122 | void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
123 | {
124 |
125 | if(uartHandle->Instance==USART2)
126 | {
127 | /* USER CODE BEGIN USART2_MspDeInit 0 */
128 |
129 | /* USER CODE END USART2_MspDeInit 0 */
130 | /* Peripheral clock disable */
131 | __HAL_RCC_USART2_CLK_DISABLE();
132 |
133 | /**USART2 GPIO Configuration
134 | PA2 ------> USART2_TX
135 | PA3 ------> USART2_RX
136 | */
137 | HAL_GPIO_DeInit(GPIOA, TXD_Pin|RXD_Pin);
138 |
139 | /* USART2 DMA DeInit */
140 | HAL_DMA_DeInit(uartHandle->hdmarx);
141 | HAL_DMA_DeInit(uartHandle->hdmatx);
142 |
143 | /* USART2 interrupt Deinit */
144 | HAL_NVIC_DisableIRQ(USART2_IRQn);
145 | /* USER CODE BEGIN USART2_MspDeInit 1 */
146 |
147 | /* USER CODE END USART2_MspDeInit 1 */
148 | }
149 | }
150 |
151 | /* USER CODE BEGIN 1 */
152 |
153 | /* USER CODE END 1 */
154 |
155 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
156 |
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/chip3d.png:
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/drone.ioc:
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1 | #MicroXplorer Configuration settings - do not modify
2 | ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
3 | ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
4 | ADC1.NbrOfConversionFlag=1
5 | ADC1.Rank-0\#ChannelRegularConversion=1
6 | ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1
7 | ADC1.master=1
8 | Dma.ADC1.2.Direction=DMA_PERIPH_TO_MEMORY
9 | Dma.ADC1.2.EventEnable=DISABLE
10 | Dma.ADC1.2.Instance=DMA1_Channel3
11 | Dma.ADC1.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
12 | Dma.ADC1.2.MemInc=DMA_MINC_DISABLE
13 | Dma.ADC1.2.Mode=DMA_NORMAL
14 | Dma.ADC1.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
15 | Dma.ADC1.2.PeriphInc=DMA_PINC_DISABLE
16 | Dma.ADC1.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING
17 | Dma.ADC1.2.Priority=DMA_PRIORITY_LOW
18 | Dma.ADC1.2.RequestNumber=1
19 | Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
20 | Dma.ADC1.2.SignalID=NONE
21 | Dma.ADC1.2.SyncEnable=DISABLE
22 | Dma.ADC1.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
23 | Dma.ADC1.2.SyncRequestNumber=1
24 | Dma.ADC1.2.SyncSignalID=NONE
25 | Dma.Request0=USART2_RX
26 | Dma.Request1=USART2_TX
27 | Dma.Request2=ADC1
28 | Dma.RequestsNb=3
29 | Dma.USART2_RX.0.Direction=DMA_PERIPH_TO_MEMORY
30 | Dma.USART2_RX.0.EventEnable=DISABLE
31 | Dma.USART2_RX.0.Instance=DMA1_Channel1
32 | Dma.USART2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
33 | Dma.USART2_RX.0.MemInc=DMA_MINC_DISABLE
34 | Dma.USART2_RX.0.Mode=DMA_CIRCULAR
35 | Dma.USART2_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
36 | Dma.USART2_RX.0.PeriphInc=DMA_PINC_DISABLE
37 | Dma.USART2_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
38 | Dma.USART2_RX.0.Priority=DMA_PRIORITY_LOW
39 | Dma.USART2_RX.0.RequestNumber=1
40 | Dma.USART2_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
41 | Dma.USART2_RX.0.SignalID=NONE
42 | Dma.USART2_RX.0.SyncEnable=DISABLE
43 | Dma.USART2_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
44 | Dma.USART2_RX.0.SyncRequestNumber=1
45 | Dma.USART2_RX.0.SyncSignalID=NONE
46 | Dma.USART2_TX.1.Direction=DMA_MEMORY_TO_PERIPH
47 | Dma.USART2_TX.1.EventEnable=DISABLE
48 | Dma.USART2_TX.1.Instance=DMA1_Channel2
49 | Dma.USART2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
50 | Dma.USART2_TX.1.MemInc=DMA_MINC_ENABLE
51 | Dma.USART2_TX.1.Mode=DMA_NORMAL
52 | Dma.USART2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
53 | Dma.USART2_TX.1.PeriphInc=DMA_PINC_DISABLE
54 | Dma.USART2_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
55 | Dma.USART2_TX.1.Priority=DMA_PRIORITY_LOW
56 | Dma.USART2_TX.1.RequestNumber=1
57 | Dma.USART2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
58 | Dma.USART2_TX.1.SignalID=NONE
59 | Dma.USART2_TX.1.SyncEnable=DISABLE
60 | Dma.USART2_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
61 | Dma.USART2_TX.1.SyncRequestNumber=1
62 | Dma.USART2_TX.1.SyncSignalID=NONE
63 | File.Version=6
64 | GPIO.groupedBy=Group By Peripherals
65 | IWDG.IPParameters=Prescaler
66 | IWDG.Prescaler=IWDG_PRESCALER_4
67 | KeepUserPlacement=false
68 | Mcu.Family=STM32G0
69 | Mcu.IP0=ADC1
70 | Mcu.IP1=DMA
71 | Mcu.IP2=IWDG
72 | Mcu.IP3=NVIC
73 | Mcu.IP4=RCC
74 | Mcu.IP5=SYS
75 | Mcu.IP6=TIM1
76 | Mcu.IP7=TIM3
77 | Mcu.IP8=USART2
78 | Mcu.IPNb=9
79 | Mcu.Name=STM32G030K(6-8)Tx
80 | Mcu.Package=LQFP32
81 | Mcu.Pin0=PA2
82 | Mcu.Pin1=PA3
83 | Mcu.Pin10=PB3
84 | Mcu.Pin11=PB4
85 | Mcu.Pin12=PB5
86 | Mcu.Pin13=PB6
87 | Mcu.Pin14=PB7
88 | Mcu.Pin15=PB8
89 | Mcu.Pin16=VP_IWDG_VS_IWDG
90 | Mcu.Pin17=VP_SYS_VS_Systick
91 | Mcu.Pin18=VP_TIM1_VS_ClockSourceINT
92 | Mcu.Pin19=VP_TIM3_VS_ClockSourceINT
93 | Mcu.Pin2=PA4
94 | Mcu.Pin3=PA5
95 | Mcu.Pin4=PA8
96 | Mcu.Pin5=PA9
97 | Mcu.Pin6=PC6
98 | Mcu.Pin7=PA11 [PA9]
99 | Mcu.Pin8=PA13
100 | Mcu.Pin9=PA14-BOOT0
101 | Mcu.PinsNb=20
102 | Mcu.ThirdPartyNb=0
103 | Mcu.UserConstants=
104 | Mcu.UserName=STM32G030K8Tx
105 | MxCube.Version=5.6.0
106 | MxDb.Version=DB.5.0.60
107 | NVIC.ADC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
108 | NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true
109 | NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
110 | NVIC.ForceEnableDMAVector=true
111 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
112 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
113 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
114 | NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
115 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
116 | NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
117 | NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
118 | PA11\ [PA9].GPIOParameters=GPIO_Label
119 | PA11\ [PA9].GPIO_Label=MOTOR3
120 | PA11\ [PA9].Locked=true
121 | PA11\ [PA9].Signal=S_TIM1_CH4
122 | PA13.Mode=Serial_Wire
123 | PA13.Signal=SYS_SWDIO
124 | PA14-BOOT0.Locked=true
125 | PA14-BOOT0.Mode=Serial_Wire
126 | PA14-BOOT0.Signal=SYS_SWCLK
127 | PA2.GPIOParameters=GPIO_Label
128 | PA2.GPIO_Label=TXD
129 | PA2.Mode=Asynchronous
130 | PA2.Signal=USART2_TX
131 | PA3.GPIOParameters=GPIO_Label
132 | PA3.GPIO_Label=RXD
133 | PA3.Mode=Asynchronous
134 | PA3.Signal=USART2_RX
135 | PA4.GPIOParameters=GPIO_PuPd,GPIO_Label
136 | PA4.GPIO_Label=STAT
137 | PA4.GPIO_PuPd=GPIO_PULLDOWN
138 | PA4.Locked=true
139 | PA4.Signal=GPIO_Input
140 | PA5.GPIOParameters=GPIO_Label
141 | PA5.GPIO_Label=BATTERY
142 | PA5.Locked=true
143 | PA5.Mode=IN5
144 | PA5.Signal=ADC1_IN5
145 | PA8.GPIOParameters=GPIO_Label
146 | PA8.GPIO_Label=MOTOR4
147 | PA8.Locked=true
148 | PA8.Signal=S_TIM1_CH1
149 | PA9.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
150 | PA9.GPIO_Label=LED4
151 | PA9.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
152 | PA9.Locked=true
153 | PA9.Signal=GPIO_Output
154 | PB3.GPIOParameters=GPIO_Label
155 | PB3.GPIO_Label=MOTOR2
156 | PB3.Signal=S_TIM1_CH2
157 | PB4.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
158 | PB4.GPIO_Label=LED2
159 | PB4.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
160 | PB4.Locked=true
161 | PB4.Signal=GPIO_Output
162 | PB5.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
163 | PB5.GPIO_Label=LED1
164 | PB5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
165 | PB5.Locked=true
166 | PB5.Signal=GPIO_Output
167 | PB6.GPIOParameters=GPIO_Label
168 | PB6.GPIO_Label=MOTOR1
169 | PB6.Locked=true
170 | PB6.Signal=S_TIM1_CH3
171 | PB7.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
172 | PB7.GPIO_Label=SDA
173 | PB7.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
174 | PB7.Locked=true
175 | PB7.Signal=GPIO_Output
176 | PB8.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
177 | PB8.GPIO_Label=SCL
178 | PB8.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
179 | PB8.Locked=true
180 | PB8.Signal=GPIO_Output
181 | PC6.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
182 | PC6.GPIO_Label=LED3
183 | PC6.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
184 | PC6.Locked=true
185 | PC6.Signal=GPIO_Output
186 | PinOutPanel.RotationAngle=0
187 | ProjectManager.AskForMigrate=true
188 | ProjectManager.BackupPrevious=false
189 | ProjectManager.CompilerOptimize=6
190 | ProjectManager.ComputerToolchain=false
191 | ProjectManager.CoupleFile=true
192 | ProjectManager.CustomerFirmwarePackage=
193 | ProjectManager.DefaultFWLocation=true
194 | ProjectManager.DeletePrevious=true
195 | ProjectManager.DeviceId=STM32G030K8Tx
196 | ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.3.0
197 | ProjectManager.FreePins=false
198 | ProjectManager.HalAssertFull=false
199 | ProjectManager.HeapSize=0x200
200 | ProjectManager.KeepUserCode=true
201 | ProjectManager.LastFirmware=true
202 | ProjectManager.LibraryCopy=1
203 | ProjectManager.MainLocation=Src
204 | ProjectManager.NoMain=false
205 | ProjectManager.PreviousToolchain=
206 | ProjectManager.ProjectBuild=false
207 | ProjectManager.ProjectFileName=drone.ioc
208 | ProjectManager.ProjectName=drone
209 | ProjectManager.StackSize=0x400
210 | ProjectManager.TargetToolchain=MDK-ARM V5.27
211 | ProjectManager.ToolChainLocation=
212 | ProjectManager.UnderRoot=false
213 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_TIM1_Init-TIM1-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true,6-MX_USART2_UART_Init-USART2-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_IWDG_Init-IWDG-false-HAL-true
214 | RCC.ADCFreq_Value=64000000
215 | RCC.AHBFreq_Value=64000000
216 | RCC.APBFreq_Value=64000000
217 | RCC.APBTimFreq_Value=64000000
218 | RCC.CortexFreq_Value=64000000
219 | RCC.EXTERNAL_CLOCK_VALUE=12288000
220 | RCC.FCLKCortexFreq_Value=64000000
221 | RCC.FamilyName=M
222 | RCC.HCLKFreq_Value=64000000
223 | RCC.HSE_VALUE=8000000
224 | RCC.HSI_VALUE=16000000
225 | RCC.I2C1Freq_Value=64000000
226 | RCC.I2S1Freq_Value=64000000
227 | RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
228 | RCC.LSCOPinFreq_Value=32000
229 | RCC.LSE_VALUE=32768
230 | RCC.LSI_VALUE=32000
231 | RCC.MCO1PinFreq_Value=64000000
232 | RCC.PLLPoutputFreq_Value=64000000
233 | RCC.PLLRCLKFreq_Value=64000000
234 | RCC.PWRFreq_Value=64000000
235 | RCC.SYSCLKFreq_VALUE=64000000
236 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
237 | RCC.USART1Freq_Value=64000000
238 | RCC.VCOInputFreq_Value=16000000
239 | RCC.VCOOutputFreq_Value=128000000
240 | SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
241 | SH.S_TIM1_CH1.ConfNb=1
242 | SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2
243 | SH.S_TIM1_CH2.ConfNb=1
244 | SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3
245 | SH.S_TIM1_CH3.ConfNb=1
246 | SH.S_TIM1_CH4.0=TIM1_CH4,PWM Generation4 CH4
247 | SH.S_TIM1_CH4.ConfNb=1
248 | TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
249 | TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
250 | TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
251 | TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
252 | TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
253 | TIM1.IPParameters=Prescaler,Period,AutoReloadPreload,Channel-PWM Generation1 CH1,Pulse-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
254 | TIM1.Period=999
255 | TIM1.Prescaler=3
256 | TIM1.Pulse-PWM\ Generation1\ CH1=0
257 | TIM3.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
258 | TIM3.IPParameters=Prescaler,Period,AutoReloadPreload
259 | TIM3.Period=1999
260 | TIM3.Prescaler=63
261 | USART2.BaudRate=115200
262 | USART2.IPParameters=VirtualMode-Asynchronous,BaudRate
263 | USART2.VirtualMode-Asynchronous=VM_ASYNC
264 | VP_IWDG_VS_IWDG.Mode=IWDG_Activate
265 | VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
266 | VP_SYS_VS_Systick.Mode=SysTick
267 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
268 | VP_TIM1_VS_ClockSourceINT.Mode=Internal
269 | VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
270 | VP_TIM3_VS_ClockSourceINT.Mode=Internal
271 | VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
272 | board=custom
273 |
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/user/control.c:
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/user/imu.c:
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/user/imu.h:
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1 | #ifndef _IMU_H_
2 | #define _IMU_H_
3 |
4 | #include "mymath.h"
5 | typedef unsigned char u8;
6 |
7 | typedef struct
8 | {
9 | float x,y,z;
10 | }Axis;
11 | typedef struct
12 | {
13 | short x,y,z;
14 | }AxisInt;
15 |
16 | void Acc_Correct(AxisInt *acc);
17 | void Gyro_Correct(AxisInt *gyro);
18 | u8 Acc_Calibrate(AxisInt acc);
19 | u8 Gyro_Calibrate(AxisInt gyro);
20 | void IMUupdate(AxisInt acc,AxisInt gyro,float *rol,float *pit,float *yaw);
21 |
22 | #endif
23 |
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/user/mpu6050.c:
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/user/mpu6050.h:
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1 | #ifndef __MPU6050_H
2 | #define __MPU6050_H
3 |
4 | #include "mpuiic.h"
5 |
6 | u8 MPU_Init(void);
7 | u8 MPU_Get_Gyroscope(short *gx,short *gy,short *gz);
8 | u8 MPU_Get_Accelerometer(short *ax,short *ay,short *az);
9 | void Delay_ms(unsigned short time_ms);
10 |
11 | #endif
12 |
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/user/protocol.c:
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/user/task.c:
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