├── .gitignore ├── CONTRIBUTING.md ├── LICENSE.txt ├── README.md ├── catalog └── catalog_2017.1.json ├── cpp ├── README.md └── getting_started │ ├── Makefile │ ├── README.md │ ├── array_partition │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── matmul.cpp │ │ └── matmul.h │ ├── burst_rw │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vec_incr.cpp │ │ └── vec_incr.h │ ├── cpu_to_fpga │ ├── 01_mmult_sw │ │ ├── Makefile │ │ ├── README.md │ │ ├── description.json │ │ └── src │ │ │ └── main.cpp │ ├── 02_mmult_hw │ │ ├── Makefile │ │ ├── README.md │ │ ├── description.json │ │ └── src │ │ │ ├── main.cpp │ │ │ ├── mmult_accel.cpp │ │ │ └── mmult_accel.h │ ├── 03_mmult_pipeline │ │ ├── Makefile │ │ ├── README.md │ │ ├── description.json │ │ └── src │ │ │ ├── main.cpp │ │ │ ├── mmult_accel.cpp │ │ │ └── mmult_accel.h │ ├── 04_mmult_zero_copy │ │ ├── Makefile │ │ ├── README.md │ │ ├── description.json │ │ └── src │ │ │ ├── main.cpp │ │ │ ├── mmult_accel.cpp │ │ │ └── mmult_accel.h │ ├── 05_mmult_array_partition │ │ ├── Makefile │ │ ├── README.md │ │ ├── description.json │ │ └── src │ │ │ ├── main.cpp │ │ │ ├── mmult_accel.cpp │ │ │ └── mmult_accel.h │ ├── Makefile │ ├── README.md │ └── summary.json │ ├── custom_data_type │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── rgb_to_hsv.cpp │ │ └── rgb_to_hsv.h │ ├── data_access_random │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── dependence_inter │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vconv.cpp │ │ └── vconv.h │ ├── direct_connect │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── dma_sg │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd.cpp │ │ └── vadd.h │ ├── dma_simple │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd.cpp │ │ └── vadd.h │ ├── full_array_2d │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── hello_vadd │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vector_addition.cpp │ │ └── vector_addition.h │ ├── lmem_2rw │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd.cpp │ │ └── vadd.h │ ├── loop_fusion │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── nearest_neighbor.cpp │ │ └── nearest_neighbor.h │ ├── loop_perfect │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── nearest.cpp │ │ └── nearest.h │ ├── loop_reorder │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── multi_threading │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult_accel.cpp │ │ └── mmult_accel.h │ ├── multiple_hw_instance │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── parallel_accel │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd_vmul.cpp │ │ └── vadd_vmul.h │ ├── row_array_2d │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── row_array_2d.cpp │ │ └── row_array_2d.h │ ├── shift_register │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── fir.cpp │ │ ├── fir.h │ │ └── main.cpp │ ├── summary.json │ ├── sys_port │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd.cpp │ │ └── vadd.h │ ├── systolic_array │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── mmult.cpp │ │ └── mmult.h │ ├── wide_memory_rw │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── main.cpp │ │ ├── vadd.cpp │ │ └── vadd.h │ └── window_array_2d │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ ├── main.cpp │ ├── window_array_2d.cpp │ └── window_array_2d.h ├── libs ├── README.md ├── bitmap │ ├── bitmap.cpp │ ├── bitmap.h │ └── bitmap.mk ├── opencl │ └── opencl.mk ├── sds_utils │ ├── sds_utils.h │ └── sds_utils.mk └── xcl2 │ ├── xcl2.cpp │ ├── xcl2.hpp │ └── xcl2.mk ├── ocl ├── README.md ├── common │ ├── check_json.py │ ├── makefile_gen │ │ ├── makegen.py │ │ └── update_makegen_all.sh │ └── readme_gen │ │ ├── gs_summary.py │ │ ├── gs_summary_subdir.py │ │ ├── gs_summary_util.py │ │ ├── readme_gen.py │ │ └── update_readme_all.sh └── getting_started │ ├── custom_datatype_ocl │ ├── Makefile │ ├── README.md │ ├── data │ │ └── input.bmp │ ├── description.json │ └── src │ │ ├── host.cpp │ │ ├── rgb_to_hsv.cl │ │ └── rgb_to_hsv.h │ ├── dataflow_func_ocl │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── adder.cl │ │ └── host.cpp │ ├── hello_vadd_ocl │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── host.cpp │ │ └── vadd.cl │ ├── multiple_interfaces_ocl │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ │ ├── host.cpp │ │ └── vadd.cpp │ └── wide_mem_rw_ocl │ ├── Makefile │ ├── README.md │ ├── description.json │ └── src │ ├── host.cpp │ └── vadd.cl └── utility ├── check_license.sh ├── check_readme.sh ├── create_catalog.py ├── emu_run.sh ├── license ├── commands.txt ├── lic.txt ├── source_lic.sh └── update_license_all.sh ├── makefile_gen ├── makegen.py └── update_makegen_all.sh ├── readme_gen ├── gs_summary.py ├── gs_summary_util.py ├── readme_gen.py ├── table_readme.py └── update_readme_all.sh └── test_repo ├── clean_all.sh ├── test_all.sh └── test_emu.sh /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Object files 2 | *.slo 3 | *.lo 4 | *.o 5 | *.obj 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Compiled Dynamic libraries 12 | *.so 13 | *.dylib 14 | *.dll 15 | 16 | # Fortran module files 17 | *.mod 18 | *.smod 19 | 20 | # Compiled Static libraries 21 | *.lai 22 | *.la 23 | *.a 24 | *.lib 25 | 26 | # Executables 27 | *.exe 28 | *.out 29 | *.app 30 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | ## Contributor guidelines 2 | 3 | Contributing code to this project is intended to be light weight and intuitive to users familiar with GitHub to actively encourage contributions, but a process is documented and should be followed to prevent chaos, confusion and despair. 4 | 5 | ## The mechanics of contributing code 6 | Firstly, in order to contribute code to this project, a contributor must have a valid and current [GitHub account](https://help.github.com/articles/set-up-git) available to use. Given an account, 7 | * The potential contributor forks this project into his/her account following the traditional [forking](https://help.github.com/articles/fork-a-repo) model native to GitHub 8 | * After forking, the contributor [clones their repository](https://help.github.com/articles/create-a-repo) locally on their machine 9 | * Code is developed and checked into the contributor's repository. These commits are eventually pushed upstream to their GitHub repository 10 | * The contributor then issues a [pull-request](https://help.github.com/articles/using-pull-requests) against the **master** branch of this repository. 11 | 12 | At this point, the repository maintainers will be notified by GitHub that a 'pull request' exists pending against their repository. A code review should be completed within a few days, depending on the scope of submitted code, and the code will either be accepted, rejected or commented on for extra feedback. 13 | 14 | ## Code submission guidelines 15 | We want to ensure that the project code base maintains a level of quality over time, such that future contributors find it as easy to jump into the code as hopefully it is today. As such, pull requests should 16 | * Remember that all of the code in this project is licensed under the [3-Clause BSD]( http://choosealicense.com/licenses/bsd-3-clause/ ). If you are not already familiar, please review the license before issuing a pull request. We intend this project to be open to external contributors, and encourage developers to contribute code back that they believe will provide value to the overall community. We will interpret an explicit 'pull request' back to this repository as an implicit acknowledgement from the contributor that they wish to share the code with the community under the terms of the BSD. 17 | * Target the **master** branch in the repository 18 | 19 | Pull requests will be reviewed by the set of collaborators that are assigned for the repository. Pull requests may be accepted, declined or a conversation may start on the pull request thread with feedback. If the pull request is trivial and all the submission guidelines defined above are honored, the pull request may be accepted without delay. If the pull request is good, but the guidelines defined above are not followed, the collaborators may leave feedback on the pull request and engage in a conversation with the contributor with what they can do to improve the pull request. At any time, collaborators may decline a pull request if they decide the contribution is not appropriate for the project, or the feedback from reviewers on a pull request is not being addressed in an appropriate amount of time. 20 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | SDSoC Example Repository 2 | =========================== 3 | 4 | ### Note: Please do not use this repository for Xilinx Latest Vitis Tool Chain. A entire new Repository is created here: https://github.com/Xilinx/Vitis_Accel_Examples for Xilinx new Vitis Tool chain. Use SDSoC Examples Git Repository only for Xilinx previously released product SDSoC. 5 | 6 | Welcome to the SDSoC example repository. This repository contains the latest examples to get you started with application optimization targeting Xilinx Embedded FPGA acceleration boards. All the examples are ready to be compiled and executed on boards. These examples are developed in C/C++ flow. The "cpp" directory of this repository contains SDSoC examples in C/C++ form. 7 | 8 | This repository is organized as follows internally. 9 | 10 | 1. CPP 11 | 2. OCL 12 | 3. LIBS 13 | 4. UTILITY 14 | 5. OTHER INFORMATION 15 | 6. SUPPORT 16 | 7. REVISION HISTORY 17 | 18 | 19 | ### 1. CPP 20 | 21 | Collection of examples geared at teaching the user best practices in how to use 22 | different features of SDSoC (C/C++) and start on their own application. 23 | 24 | ### 2. OCL 25 | 26 | Collection of examples geared at teaching the user best practices in how to use 27 | different features of OpenCL and start on their own application for 28 | OpenCL Unified Platform. 29 | 30 | ### 3. LIBS 31 | 32 | Collection of common libraries used across all examples to assist in the quick 33 | development of source code which is not targeted to programmable logic (PL). 34 | 35 | ### 4. UTILITY 36 | 37 | Collection of utility functions used as part of the Makefiles in all of the 38 | examples. This set includes Makefile rules and scripts to launch SDSoC compiled 39 | applications onto SDSoC emulation flow. It also contains Makefile and Readme 40 | generation scripts. 41 | 42 | 43 | ## 5. OTHER INFORMATION 44 | 45 | For more information check here: 46 | [SDSoC User Guides][] 47 | 48 | ## 6. SUPPORT 49 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 50 | 51 | ## 7. REVISION HISTORY 52 | 53 | Date | Readme Version | Revision Description 54 | --------|----------------|------------------------- 55 | JUNE2017 | 1.0 | Initial Xilinx release 56 | 57 | 58 | 59 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 60 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 61 | 62 | 63 | -------------------------------------------------------------------------------- /cpp/README.md: -------------------------------------------------------------------------------- 1 | SDSoC (C/C++) Example Repository 2 | =============================== 3 | 4 | Welcome to the SDSoC (C/C++) example repository. This repository contains 5 | latest examples to get you started with application optimization targeting 6 | Xilinx Embedded FPGA acceleration boards. All examples are ready to be compiled 7 | and executed on boards. The "getting_started" directory contains latest SDSoC 8 | examples which are intended to help in quick learning of various SDSoC key 9 | concepts. It also provides insights into new features and optimization tricks 10 | which are quite handy in identical scenarios. 11 | 12 | 13 | -------------------------------------------------------------------------------- /cpp/getting_started/Makefile: -------------------------------------------------------------------------------- 1 | COMMON_REPO=../../ 2 | 3 | docs: README.md 4 | 5 | README.md:summary.json 6 | $(COMMON_REPO)/utility/readme_gen/gs_summary.py 7 | -------------------------------------------------------------------------------- /cpp/getting_started/array_partition/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Array Partitioning", 3 | "overview": [ 4 | "This example shows how to use array partitioning to improve performance of a hardware function" 5 | ], 6 | "key_concepts": [ "Hardware Function Optimization", "Array Partitioning"], 7 | "keywords": ["#pragma HLS ARRAY_PARTITION", "complete"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "matmul_partition_accel", 27 | "location" : "matmul.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/array_partition/src/matmul.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef MATMUL_H_ 30 | #define MATMUL_H_ 31 | 32 | // Maximum Array Size 33 | #define MAX_SIZE 64 34 | 35 | //TRIPCOUNT identifier 36 | const unsigned int c_size = MAX_SIZE; 37 | 38 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 39 | // Which has Direct Memory Interface with DDR and PL. 40 | #pragma SDS data zero_copy(in1[0:mat_dim*mat_dim], in2[0:mat_dim*mat_dim], out[0:mat_dim*mat_dim]) 41 | void matmul_partition_accel(int *in1, // Read-Only Matrix 1 42 | int *in2, // Read-Only Matrix 2 43 | int *out, // Output Result 44 | int mat_dim); // Matrix Dim (assumed only square matrix) 45 | #endif 46 | -------------------------------------------------------------------------------- /cpp/getting_started/burst_rw/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Burst Read/Write", 3 | "overview": [ 4 | "This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write" 5 | ], 6 | "key_concepts": [ "Burst Access"], 7 | "contributors" : [ 8 | { 9 | "group": "Xilinx", 10 | "url" : "http://www.xilinx.com" 11 | } 12 | ], 13 | "revision" : [ 14 | { 15 | "date" : "JUNE2017", 16 | "version": "1.0", 17 | "description": "Initial Xilinx Release" 18 | } 19 | ], 20 | "compiler" : { 21 | "options" : "-Wno-unused-label" 22 | }, 23 | "accelerators": [ 24 | { 25 | "name" : "vec_incr_accel", 26 | "location" : "vec_incr.cpp" 27 | } 28 | ], 29 | "libs": [ 30 | "sds_utils" 31 | ], 32 | "os" : [ 33 | "linux", 34 | "standalone" 35 | ], 36 | "runtime" : [ 37 | "C/C++" 38 | ], 39 | "source_dir" : "src/*.cpp", 40 | "pass_string" : "TEST PASSED", 41 | "fail_string" : "TEST FAILED" 42 | } 43 | -------------------------------------------------------------------------------- /cpp/getting_started/burst_rw/src/vec_incr.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /******************************************************************************* 31 | 32 | This is a vector increment example to demonstrate burst access between DDR 33 | and programmable logic (PL) using HLS AXI-master Interface 34 | 35 | *******************************************************************************/ 36 | #include "vec_incr.h" 37 | 38 | void vec_incr_accel(int *in, int *out, int size, int inc_value){ 39 | 40 | // Variables in and out utilizes multiple memory interfaces that are 41 | // available. Burst read and writes can be inferred by default with the 42 | // logic below. 43 | calc_write: for(int j=0; j < size; j++){ 44 | #pragma HLS LOOP_TRIPCOUNT min=c_min max=c_max 45 | #pragma HLS PIPELINE 46 | out[j] = in[j] + inc_value; 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /cpp/getting_started/burst_rw/src/vec_incr.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VEC_INCR_H_ 30 | #define VEC_INCR_H_ 31 | 32 | #define DATA_SIZE 2048 33 | #define INCR_VALUE 10 34 | 35 | //TRIPCOUNT indentifier 36 | const unsigned int c_min = 1; 37 | const unsigned int c_max = DATA_SIZE; 38 | 39 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 40 | // Which has Direct Memory Interface with DDR and PL. 41 | #pragma SDS data zero_copy(in[0:size],out[0:size]) 42 | void vec_incr_accel(int *in, int *out, int size, int inc_value); 43 | #endif 44 | 45 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/01_mmult_sw/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "01_mmult_sw", 3 | "overview": [ 4 | "This example shows how to perform matrix multiplication on software with no hardware function involved." 5 | ], 6 | "contributors" : [ 7 | { 8 | "group": "Xilinx", 9 | "url" : "http://www.xilinx.com" 10 | } 11 | ], 12 | "revision" : [ 13 | { 14 | "date" : "FEB2018", 15 | "version": "1.0", 16 | "description": "Initial Xilinx Release" 17 | } 18 | ], 19 | "compiler" : { 20 | "options" : "-Wno-unused-label" 21 | }, 22 | "accelerators" : [], 23 | "libs": [ 24 | "sds_utils" 25 | ], 26 | "os" : [ 27 | "linux", 28 | "standalone" 29 | ], 30 | "runtime" : [ 31 | "C/C++" 32 | ], 33 | "source_dir" : "src/*.cpp", 34 | "pass_string" : "TEST PASSED", 35 | "fail_string" : "TEST FAILED" 36 | } 37 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/01_mmult_sw/src/main.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | //This is a simple example of Matrix Multiplication on CPU. 31 | // 32 | #include 33 | #include 34 | 35 | //Array size to access 36 | #define DATA_SIZE 64 37 | 38 | void mmult_sw( int *in1, // Input matrix 1 39 | int *in2, // Input matrix 2 40 | int *out, // Output matrix (out = A x B) 41 | int dim // Size of one dimension of matrix 42 | ) 43 | { 44 | //Performs matrix multiplication out = in1 x in2 45 | for (int i = 0; i < dim; i++){ 46 | for (int j = 0; j < dim; j++){ 47 | for (int k = 0; k < dim; k++){ 48 | out[i * dim + j] += in1[i * dim + k] * in2[k * dim + j]; 49 | } 50 | } 51 | } 52 | } 53 | 54 | int main(int argc, char** argv) 55 | { 56 | int dim = DATA_SIZE; 57 | size_t matrix_size_bytes = sizeof(int) * DATA_SIZE * DATA_SIZE; 58 | 59 | //Allocate memory 60 | int *in1 = (int *) malloc(matrix_size_bytes); 61 | int *in2 = (int *) malloc(matrix_size_bytes); 62 | int *sw_result = (int *) malloc(matrix_size_bytes); 63 | 64 | //Creates test data 65 | for(int index = 0; index < dim * dim; index++){ 66 | in1[index] = rand() % dim; 67 | in2[index] = rand() % dim; 68 | sw_result[index] = 0; 69 | } 70 | 71 | //Function call to perform matrix multiplication 72 | mmult_sw(in1, in2, sw_result, dim); 73 | std::cout << "TEST PASSED" << std::endl; 74 | 75 | //Release Memory 76 | free(in1); 77 | free(in2); 78 | free(sw_result); 79 | 80 | return 0; 81 | } 82 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/02_mmult_hw/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "02_mmult_hw", 3 | "overview": [ 4 | "This example shows how to perform matrix multiplication on hardware without specifying any optimizations (the same software function is taken and just targeted to hardware). This results in default random data access and DMA transfers the data to BRAM blocks. The hardware results are compared with the software results for verification and speedup is shown withrespect to running on hardware versus software." 5 | ], 6 | "keywords": ["#pragma HLS loop_tripcount"], 7 | 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "FEB2018", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_hw", 27 | "location" : "mmult_accel.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/02_mmult_hw/src/mmult_accel.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #include "mmult_accel.h" 31 | 32 | void mmult_hw(int in1[DATA_SIZE * DATA_SIZE], int in2[DATA_SIZE * DATA_SIZE], int out[DATA_SIZE * DATA_SIZE], int dim) 33 | { 34 | //loop tripcount constant 35 | const int c_size = DATA_SIZE; 36 | 37 | //Reads the data from DDR, performs the computation 38 | //and writes back the result to DDR. 39 | for (int i = 0 ; i < dim ; i++){ 40 | #pragma HLS loop_tripcount min=c_size max=c_size 41 | //In cases where the loop latency is unknown or cannot be calculated 42 | //due to variable loop boundaries, the loop_tripcount pragma tells the HLS compiler 43 | //about the minimum and maximum iterations for a loop. 44 | for(int j = 0; j < dim; j++){ 45 | #pragma HLS loop_tripcount min=c_size max=c_size 46 | int result = 0; 47 | for(int k = 0; k < dim; k++){ 48 | #pragma HLS loop_tripcount min=c_size max=c_size 49 | result += in1[i * dim + k] * in2[k * dim + j]; 50 | } 51 | out[i*dim +j] = result; 52 | } 53 | } 54 | } 55 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/02_mmult_hw/src/mmult_accel.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef MMULT_ACC_H 31 | #define MMULT_ACC_H 32 | 33 | //Array size to access 34 | #define DATA_SIZE 32 35 | 36 | //Declaring the hardware function 37 | void mmult_hw(int in1[DATA_SIZE*DATA_SIZE] , int in2[DATA_SIZE*DATA_SIZE] , int out[DATA_SIZE*DATA_SIZE] , int dim); 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/03_mmult_pipeline/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "03_mmult_pipeline", 3 | "overview": [ 4 | "This example takes the same hardware function from the previous example and highlights the pipeline kernel optimization in hardware function to achieve better performance. Pipelining a loop results in lower initiation interval(II), which is the number of clock cycles between the start times of consecutive loop iterations by allowing multiple iterations of a loop to run in parallel." 5 | ], 6 | "key_concepts": ["Pipelining"], 7 | "keywords": ["#pragma HLS PIPIELINE"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "FEB2018", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_pipeline", 27 | "location" : "mmult_accel.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/03_mmult_pipeline/src/mmult_accel.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #include "mmult_accel.h" 31 | 32 | void mmult_pipeline(int in1[DATA_SIZE * DATA_SIZE], int in2[DATA_SIZE * DATA_SIZE], int out[DATA_SIZE * DATA_SIZE], int dim) 33 | { 34 | //loop tripcount constant 35 | const int c_size = DATA_SIZE; 36 | 37 | //Reads the data from DDR, performs the computation 38 | //and writes back the result to DDR. 39 | loop1: for (int i = 0 ; i < dim ; i++){ 40 | #pragma HLS loop_tripcount min=c_size max=c_size 41 | loop2: for(int j = 0; j < dim; j++){ 42 | #pragma HLS loop_tripcount min=c_size max=c_size 43 | int result = 0; 44 | loop3: for(int k = 0; k < dim; k++){ 45 | #pragma HLS loop_tripcount min=c_size max=c_size 46 | #pragma HLS PIPELINE 47 | //The PIPELINE pragma reduces the initiation interval, which is the 48 | //number of clock cycles between the start times of consecutive loop 49 | //iterations by allowing multiple iterations of a loop to run in parallel. 50 | result += in1[i * dim + k] * in2[k * dim + j]; 51 | } 52 | out[i*dim +j] = result; 53 | } 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/03_mmult_pipeline/src/mmult_accel.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef MMULT_ACC_H 31 | #define MMULT_ACC_H 32 | 33 | //Array size to access 34 | #define DATA_SIZE 64 35 | 36 | //Declaring hardware function 37 | void mmult_pipeline(int in1[DATA_SIZE*DATA_SIZE], int in2[DATA_SIZE*DATA_SIZE] , int out[DATA_SIZE*DATA_SIZE], int dim); 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/04_mmult_zero_copy/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "04_mmult_zero_copy", 3 | "overview": [ 4 | "This example shows how matrix multiplication can be made more efficent in the same hardware function by using local buffers and direct memory interface technique using the zero_copy pragma. The local buffers are implemented as BRAM memory blocks in Programmable Logic (PL) and the zero_copy pragma allows burst read/write from/to DDR memory to/from local memory by generating a direct memory interface between DDR and hardware function via an AXI master bus interface." 5 | ], 6 | "key_concepts": [ "Local buffers, Zero_copy"], 7 | "keywords": ["#pragma SDS data zero_copy"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "FEB2018", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_zero_copy", 27 | "location" : "mmult_accel.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/04_mmult_zero_copy/src/mmult_accel.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #include "mmult_accel.h" 31 | 32 | void mmult_zero_copy(int *in1, int *in2, int *out, int dim) 33 | { 34 | //loop tripcount constant 35 | const int c_size = DATA_SIZE; 36 | 37 | //Local memory to store input and output matrices 38 | //Local memory is implemented as BRAM memory blocks 39 | //MAX_SIZE * MAX_SIZE buffer is created because the size 40 | //to create buffer needs to be known at compile time. 41 | int local_in1[MAX_SIZE][MAX_SIZE]; 42 | int local_in2[MAX_SIZE][MAX_SIZE]; 43 | int local_out[MAX_SIZE][MAX_SIZE]; 44 | 45 | //read/write data from memory in bursts and store it in a local memory. 46 | //Burst read on input matrices local_in1 and local_in2 from DDR memory. 47 | read_in1: for(int iter = 0, i=0, j=0; iter< dim*dim; iter++,j++){ 48 | #pragma HLS loop_tripcount min=c_size*c_size max=c_size*c_size 49 | #pragma HLS PIPELINE 50 | if( j== dim){ j = 0; i++; } 51 | local_in1[i][j] = in1[iter]; 52 | } 53 | read_in2: for(int iter = 0, i=0, j=0; iter< dim*dim; iter++,j++){ 54 | #pragma HLS loop_tripcount min=c_size*c_size max=c_size*c_size 55 | #pragma HLS PIPELINE 56 | if( j== dim){ j = 0; i++; } 57 | local_in2[i][j] = in2[iter]; 58 | } 59 | 60 | //Reads the input data from local memory, performs the 61 | //computations and writes the data back to local memory. 62 | loop_1: for (int i = 0 ; i < dim ; i++){ 63 | #pragma HLS loop_tripcount min=c_size max=c_size 64 | loop_2: for(int j = 0 ; j < dim ; j++){ 65 | #pragma HLS loop_tripcount min=c_size max=c_size 66 | int result = 0; 67 | loop_3: for(int k = 0; k < dim; k++){ 68 | #pragma HLS loop_tripcount min=c_size max=c_size 69 | #pragma HLS PIPELINE 70 | result += local_in1[i][k]*local_in2[k][j]; 71 | } 72 | local_out[i][j] = result; 73 | } 74 | } 75 | 76 | //Burst write from output matrix local_out to DDR memory. 77 | write_out: for(int iter = 0, i = 0, j = 0; iter < dim * dim; iter++, j++){ 78 | #pragma HLS loop_tripcount min=c_size*c_size max=c_size*c_size 79 | #pragma HLS PIPELINE 80 | if(j == dim){ j = 0; i++; } 81 | out[iter] = local_out[i][j]; 82 | } 83 | } 84 | 85 | 86 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/04_mmult_zero_copy/src/mmult_accel.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef MMULT_ACC_H 31 | #define MMULT_ACC_H 32 | 33 | //Max Array Size 34 | #define MAX_SIZE 64 35 | 36 | //Array size to access 37 | #define DATA_SIZE 32 38 | 39 | //The zero_copy pragma specifies the sds++ compiler to generate a Programmable Logic Design 40 | //which allows the hardware function to access data directly from the DDR memory. 41 | #pragma SDS data zero_copy(in1[0:dim*dim], in2[0:dim*dim], out[0:dim*dim]) 42 | void mmult_zero_copy(int *in1, int *in2, int *out, int dim); 43 | 44 | #endif 45 | 46 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/05_mmult_array_partition/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "05_mmult_array_partition", 3 | "overview": [ 4 | "This example shows how matrix multiplication using array partitioning technique on top of the same hardware function from previous example achieves better performance. Array partitioning results in increased number of effective read/write ports for a local BRAM array by partitioning the array into smaller arrays. Increase in number of read/write ports leads to parallel processing of the data elements." 5 | ], 6 | "key_concepts": [ "Array Partitioning"], 7 | "keywords": ["#pragma HLS ARRAY_PARTITION"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "FEB2018", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_array_partition", 27 | "location" : "mmult_accel.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/05_mmult_array_partition/src/mmult_accel.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef MMULT_ACC_H 31 | #define MMULT_ACC_H 32 | 33 | //Max Array Size 34 | #define MAX_SIZE 64 35 | 36 | //Array size to access 37 | #define DATA_SIZE 64 38 | 39 | #pragma SDS data zero_copy(in1[0:dim*dim], in2[0:dim*dim], out[0:dim*dim]) 40 | void mmult_array_partition(int *in1, int *in2, int *out, int dim); 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/Makefile: -------------------------------------------------------------------------------- 1 | COMMON_REPO=../../../ 2 | 3 | docs: README.md 4 | 5 | README.md:summary.json 6 | $(COMMON_REPO)/utility/readme_gen/gs_summary.py 7 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/README.md: -------------------------------------------------------------------------------- 1 | CPU_To_FPGA Examples 2 | ================================== 3 | Labs to showcase cpu to fpga conversion with kernel optimizations. 4 | 5 | __Examples Table__ 6 | 7 | Example | Description | Key Concepts / Keywords 8 | ---------------|-----------------------|------------------------- 9 | [01_mmult_sw/][]|This example shows how to perform matrix multiplication on software with no hardware function involved.| 10 | [02_mmult_hw/][]|This example shows how to perform matrix multiplication on hardware without specifying any optimizations (the same software function is taken and just targeted to hardware). This results in default random data access and DMA transfers the data to BRAM blocks. The hardware results are compared with the software results for verification and speedup is shown withrespect to running on hardware versus software.|__Keywords__
- #pragma HLS loop_tripcount 11 | [03_mmult_pipeline/][]|This example takes the same hardware function from the previous example and highlights the pipeline kernel optimization in hardware function to achieve better performance. Pipelining a loop results in lower initiation interval(II), which is the number of clock cycles between the start times of consecutive loop iterations by allowing multiple iterations of a loop to run in parallel.|__Key__ __Concepts__
- Pipelining
__Keywords__
- #pragma HLS PIPIELINE 12 | [04_mmult_zero_copy/][]|This example shows how matrix multiplication can be made more efficent in the same hardware function by using local buffers and direct memory interface technique using the zero_copy pragma. The local buffers are implemented as BRAM memory blocks in Programmable Logic (PL) and the zero_copy pragma allows burst read/write from/to DDR memory to/from local memory by generating a direct memory interface between DDR and hardware function via an AXI master bus interface.|__Key__ __Concepts__
- Local buffers, Zero_copy
__Keywords__
- #pragma SDS data zero_copy 13 | [05_mmult_array_partition/][]|This example shows how matrix multiplication using array partitioning technique on top of the same hardware function from previous example achieves better performance. Array partitioning results in increased number of effective read/write ports for a local BRAM array by partitioning the array into smaller arrays. Increase in number of read/write ports leads to parallel processing of the data elements.|__Key__ __Concepts__
- Array Partitioning
__Keywords__
- #pragma HLS ARRAY_PARTITION 14 | 15 | [.]:. 16 | [01_mmult_sw/]:01_mmult_sw/ 17 | [02_mmult_hw/]:02_mmult_hw/ 18 | [03_mmult_pipeline/]:03_mmult_pipeline/ 19 | [04_mmult_zero_copy/]:04_mmult_zero_copy/ 20 | [05_mmult_array_partition/]:05_mmult_array_partition/ 21 | -------------------------------------------------------------------------------- /cpp/getting_started/cpu_to_fpga/summary.json: -------------------------------------------------------------------------------- 1 | { 2 | "overview": [ 3 | "CPU_To_FPGA Examples" 4 | ], 5 | "description": [ 6 | "Labs to showcase cpu to fpga conversion with kernel optimizations." 7 | ] 8 | } 9 | -------------------------------------------------------------------------------- /cpp/getting_started/custom_data_type/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Custom Data Type", 3 | "overview": [ 4 | "This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR" 5 | ], 6 | "key_concepts": [ "Custom Data type"], 7 | "keywords": ["struct", "packed", "aligned"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "rgb_to_hsv_accel", 27 | "location" : "rgb_to_hsv.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "targets": ["hw"], 34 | "os" : [ 35 | "linux", 36 | "standalone" 37 | ], 38 | "runtime" : [ 39 | "C/C++" 40 | ], 41 | "source_dir" : "src/*.cpp", 42 | "pass_string" : "TEST PASSED", 43 | "fail_string" : "TEST FAILED" 44 | } 45 | -------------------------------------------------------------------------------- /cpp/getting_started/custom_data_type/src/rgb_to_hsv.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef RGB_TO_HSV_H_ 31 | #define RGB_TO_HSV_H_ 32 | 33 | //Min and Max Macro Function 34 | #define imin(X, Y) (((X) < (Y)) ? (X) : (Y)) 35 | #define imax(X, Y) (((X) > (Y)) ? (X) : (Y)) 36 | 37 | #define IMAGE_DIM 128 38 | 39 | //TRIPCOUNT identifier 40 | const unsigned int c_size = IMAGE_DIM*IMAGE_DIM; 41 | 42 | //Custom Data Type for RGB Image Pixel containing Red(r), Green(g) and Blue(b) 43 | //element. Extra pad element is added to make struct size to 32bit. 44 | // It is recommended to make custom data type multiple of 32 bit to use global 45 | // memory access efficiently. 46 | typedef struct RGBcolor_struct 47 | { 48 | unsigned char r; 49 | unsigned char g; 50 | unsigned char b; 51 | unsigned char pad; 52 | } __attribute__ ((packed, aligned(4))) RGBcolor; 53 | 54 | 55 | //Custom Data Type for HSV Image Pixel containing Hue(h), Saturation(s), 56 | //and Value(v) element. Extra pad element is added to make struct size to 32bit. 57 | // It is recommended to make custom data type multiple of 32 bit to use global 58 | // memory access efficiently. 59 | typedef struct HSVcolor_struct 60 | { 61 | unsigned char h; 62 | unsigned char s; 63 | unsigned char v; 64 | unsigned char pad; 65 | } __attribute__ ((packed, aligned(4))) HSVcolor; 66 | 67 | #pragma SDS data zero_copy(in[0:image_size],out[0:image_size]) 68 | void rgb_to_hsv_accel(RGBcolor *in, // Access DDR memory as RGBcolor struct-wise 69 | HSVcolor *out, // Access Global Memory as HSVcolor struct-wise 70 | int image_size); 71 | #endif 72 | -------------------------------------------------------------------------------- /cpp/getting_started/data_access_random/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Random Data Access Pattern", 3 | "overview": [ 4 | "This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern." 5 | ], 6 | "key_concepts": [ "Data Access Random"], 7 | "keywords": ["#pragma HLS PIPELINE", 8 | "#pragma sds data access_pattern(a:RANDOM, b:RANDOM)", 9 | "#pragma sds data copy"], 10 | "contributors" : [ 11 | { 12 | "group": "Xilinx", 13 | "url" : "http://www.xilinx.com" 14 | } 15 | ], 16 | "revision" : [ 17 | { 18 | "date" : "JUL2017", 19 | "version": "1.0", 20 | "description": "Initial Xilinx Release" 21 | } 22 | ], 23 | "compiler" : { 24 | "options" : "-Wno-unused-label" 25 | }, 26 | "accelerators": [ 27 | { 28 | "name" : "mmult_accel", 29 | "location" : "mmult.cpp" 30 | } 31 | ], 32 | "libs": [ 33 | "sds_utils" 34 | ], 35 | "os" : [ 36 | "linux", 37 | "standalone" 38 | ], 39 | "runtime" : [ 40 | "C/C++" 41 | ], 42 | "source_dir" : "src/*.cpp", 43 | "pass_string" : "TEST PASSED", 44 | "fail_string" : "TEST FAILED" 45 | } 46 | -------------------------------------------------------------------------------- /cpp/getting_started/data_access_random/src/mmult.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /******************************************************************************* 31 | 32 | This is a matrix multiplication based example which showcases even with 33 | random data access pattern a pipeline initiation interval(II) of 1 34 | is achieved. 35 | 36 | *******************************************************************************/ 37 | 38 | /* 39 | 40 | Description : 41 | 42 | Matrix multiply for matrices up to sizes (MAX_SIZE x MAX_SIZE) 43 | [MAX_SIZE defined below]. 44 | This example showcases random data access pattern. 45 | 46 | Arguments : 47 | 48 | int *in1 (input) --> Input Matrix 1 49 | int *in2 (input) --> Input Matrix 2 50 | int *out (output) --> Output Matrix 51 | int dim (input) --> Size of one dimension of the matrices 52 | 53 | */ 54 | 55 | #include "mmult.h" 56 | 57 | // Computes matrix multiply 58 | // C = A x B, where A, B and C are square matrices of dimension (dim x dim) 59 | void mmult_accel( 60 | const int in1[MAX_SIZE * MAX_SIZE], // Read-Only Matrix 1 61 | const int in2[MAX_SIZE * MAX_SIZE], // Read-Only Matrix 2 62 | int out[MAX_SIZE * MAX_SIZE], // Output Result 63 | int dim // Size of one dimension of the matrices 64 | ) 65 | { 66 | // Performs matrix multiply over matrices A and B and stores the result 67 | // in C. All the matrices are square matrices of the form (size x size) 68 | mmult1: for (int i = 0; i < dim ; i++) { 69 | #pragma HLS LOOP_TRIPCOUNT min=c_min max=c_max 70 | mmult2 : for (int j = 0; j < dim ; j++) { 71 | #pragma HLS LOOP_TRIPCOUNT min=c_min max=c_max 72 | int result = 0; 73 | mmult3: for (int k = 0; k < dim; k++) { 74 | #pragma HLS LOOP_TRIPCOUNT min=c_min max=c_max 75 | #pragma HLS PIPELINE 76 | result += in1[i * dim + k] * in2[k * dim + j]; 77 | } 78 | out[i * dim + j] = result; 79 | } 80 | } 81 | } 82 | 83 | -------------------------------------------------------------------------------- /cpp/getting_started/data_access_random/src/mmult.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef MMULT_H_ 30 | #define MMULT_H_ 31 | 32 | // Size of the input array 33 | #define DATA_SIZE 32 34 | 35 | // Maximum Supported Size 36 | #define MAX_SIZE 64 37 | 38 | // Max Number of times to run 39 | #define NUM_TIMES 2 40 | 41 | //TRIPCOUNT indentifier 42 | const unsigned int c_min = 1; 43 | const unsigned int c_max = DATA_SIZE; 44 | 45 | // By default access_pattern is RANDOM, to highlight, the access pattern is explicitly declared 46 | #pragma SDS data copy(in1[0:dim*dim], in2[0:dim*dim], out[0:dim*dim]) 47 | #pragma SDS data access_pattern(in1:RANDOM, in2:RANDOM, out:RANDOM) 48 | void mmult_accel( 49 | const int in1[MAX_SIZE * MAX_SIZE], // Read-Only Matrix 1 50 | const int in2[MAX_SIZE * MAX_SIZE], // Read-Only Matrix 2 51 | int out[MAX_SIZE * MAX_SIZE], // Output Result 52 | int dim // Size of one dimension of the matrices 53 | ); 54 | 55 | #endif 56 | -------------------------------------------------------------------------------- /cpp/getting_started/dependence_inter/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Loop Iteration Dependency", 3 | "overview": [ 4 | "This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance " 5 | ], 6 | "key_concepts": [ "Inter Dependence"], 7 | "keywords": ["DEPENDENCE", "inter"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "vconv_hw", 27 | "location" : "vconv.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/dependence_inter/src/vconv.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VCONV_H_ 30 | #define VCONV_H_ 31 | 32 | #define MAX_COLS 512 33 | #define K 11 34 | #define TEST_WIDTH 256 35 | #define TEST_HEIGHT 256 36 | 37 | const unsigned int vcoeff[K] = { 38 | 36, 111, 266, 498, 724, 821, 724, 498, 266, 111, 36 39 | }; 40 | 41 | //TRIPCOUNT identifier 42 | const unsigned int c_image_size = TEST_WIDTH * TEST_HEIGHT; 43 | 44 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 45 | // Which has Direct Memory Interface with DDR and PL. 46 | #pragma SDS data zero_copy(in[0:height*width], out[0:height*width]) 47 | void vconv_hw(int *in, int *out, int height, int width); 48 | #endif 49 | -------------------------------------------------------------------------------- /cpp/getting_started/direct_connect/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Direct Connection", 3 | "overview": [ 4 | "This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C)to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency." 5 | ], 6 | "key_concepts": [ "Direct Connection", "Multiple Accelerators"], 7 | "keywords": ["#pragma SDS data access_pattern"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUL2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_accel", 27 | "location" : "mmult.cpp" 28 | }, 29 | { 30 | "name" : "madd_accel", 31 | "location" : "mmult.cpp" 32 | } 33 | ], 34 | "libs": [ 35 | "sds_utils" 36 | ], 37 | "os" : [ 38 | "linux", 39 | "standalone" 40 | ], 41 | "runtime" : [ 42 | "C/C++" 43 | ], 44 | "source_dir" : "src/*.cpp", 45 | "pass_string" : "TEST PASSED", 46 | "fail_string" : "TEST FAILED" 47 | } 48 | -------------------------------------------------------------------------------- /cpp/getting_started/direct_connect/src/mmult.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef MMULT_H_ 30 | #define MMULT_H_ 31 | 32 | // Size of the input array 33 | #define DATA_SIZE 32 34 | 35 | // Maximum Supported Size 36 | #define MAX_SIZE 64 37 | 38 | // Maximum times run example 39 | #define NUM_TIMES 2 40 | 41 | //TRIPCOUNT identifiers 42 | const unsigned int c_min = 1; 43 | const unsigned int c_max = DATA_SIZE; 44 | 45 | #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL) 46 | void mmult_accel( 47 | const int *in1, // Read-Only Matrix 1 48 | const int *in2, // Read-Only Matrix 2 49 | int *out, // Output Matrix 50 | int dim // Size of one dimension of the matrices 51 | ); 52 | 53 | #pragma SDS data access_pattern(mmult_in:SEQUENTIAL, in3:SEQUENTIAL, out:SEQUENTIAL) 54 | void madd_accel( 55 | const int *mmult_in, // Read-Only Matrix 56 | const int *in3, // Read-Only Matrix 57 | int *out, // Output Matrix 58 | int dim // Size of one dimension of the matrices 59 | ); 60 | 61 | #endif 62 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_sg/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "DMA SG(scatter-Gather)", 3 | "overview": [ 4 | "This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator" 5 | ], 6 | "key_concepts": [ "Scatter Gather DMA", "FIFO Interface"], 7 | "keywords": ["#pragma SDS access_pattern(a:SEQUENTIAL)", 8 | "#pragma SDS data_mover(a:AXIDMA_SG)", 9 | "#pragma SDS data copy"], 10 | "contributors" : [ 11 | { 12 | "group": "Xilinx", 13 | "url" : "http://www.xilinx.com" 14 | } 15 | ], 16 | "revision" : [ 17 | { 18 | "date" : "JUNE2017", 19 | "version": "1.0", 20 | "description": "Initial Xilinx Release" 21 | } 22 | ], 23 | "compiler" : { 24 | "options" : "-Wno-unused-label" 25 | }, 26 | "accelerators": [ 27 | { 28 | "name" : "vadd_hw", 29 | "location" : "vadd.cpp" 30 | } 31 | ], 32 | "libs": [ 33 | "sds_utils" 34 | ], 35 | "os" : [ 36 | "linux", 37 | "standalone" 38 | ], 39 | "runtime" : [ 40 | "C/C++" 41 | ], 42 | "source_dir" : "src/*.cpp", 43 | "pass_string" : "TEST PASSED", 44 | "fail_string" : "TEST FAILED" 45 | } 46 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_sg/src/vadd.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #include "vadd.h" 31 | 32 | void vadd_hw(int *a, int *b, int *c, const int len) 33 | { 34 | vadd: for(int i = 0; i < len; i++) { 35 | #pragma HLS PIPELINE 36 | #pragma HLS LOOP_TRIPCOUNT min=c_dim max=c_dim 37 | c[i] = a[i] + b[i]; 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_sg/src/vadd.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef VECTOR_ADDITION_H_ 31 | #define VECTOR_ADDITION_H_ 32 | 33 | #define TEST_DATA_SIZE 1<<10 34 | 35 | //TRIPCOUNT identifier 36 | const unsigned int c_dim = TEST_DATA_SIZE; 37 | 38 | // Pragma data data_mover is used to Generate a Programmable Logic Design 39 | // with DMA IP (with scatter-Gather Functionality). SG DMA functionality is 40 | // is helpful to transfer buffers which are not allocated continuously in 41 | // physical memory. For example, if buffer is allocated using malloc(), it does 42 | // not give guarantee of continuous physical memory allocation. 43 | #pragma SDS data copy(a[0:len], b[0:len], c[0:len]) 44 | #pragma SDS data access_pattern(a:SEQUENTIAL, b:SEQUENTIAL, c:SEQUENTIAL) 45 | #pragma SDS data data_mover(a:AXIDMA_SG, b:AXIDMA_SG, c:AXIDMA_SG) 46 | void vadd_hw(int *a, int *b, int *c, const int len); 47 | #endif 48 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_simple/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "DMA Simple", 3 | "overview": [ 4 | "This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator" 5 | ], 6 | "key_concepts": [ "Simple DMA", "FIFO Interface"], 7 | "keywords": ["#pragma SDS access_pattern(a:SEQUENTIAL)", 8 | "#pragma SDS data_mover(a:AXIDMA_SIMPLE)", 9 | "#pragma SDS data copy"], 10 | "contributors" : [ 11 | { 12 | "group": "Xilinx", 13 | "url" : "http://www.xilinx.com" 14 | } 15 | ], 16 | "revision" : [ 17 | { 18 | "date" : "JUNE2017", 19 | "version": "1.0", 20 | "description": "Initial Xilinx Release" 21 | } 22 | ], 23 | "compiler" : { 24 | "options" : "-Wno-unused-label" 25 | }, 26 | "accelerators": [ 27 | { 28 | "name" : "vadd_hw", 29 | "location" : "vadd.cpp" 30 | } 31 | ], 32 | "libs": [ 33 | "sds_utils" 34 | ], 35 | "os" : [ 36 | "linux", 37 | "standalone" 38 | ], 39 | "runtime" : [ 40 | "C/C++" 41 | ], 42 | "source_dir" : "src/*.cpp", 43 | "pass_string" : "TEST PASSED", 44 | "fail_string" : "TEST FAILED" 45 | } 46 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_simple/src/vadd.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #include "vadd.h" 30 | 31 | void vadd_hw(int *a, int *b, int *c, const int len) 32 | { 33 | vadd: for(int i = 0; i < len; i++) { 34 | #pragma HLS PIPELINE 35 | #pragma HLS LOOP_TRIPCOUNT min=c_dim max=c_dim 36 | c[i] = a[i] + b[i]; 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /cpp/getting_started/dma_simple/src/vadd.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VECTOR_ADDITION_H_ 30 | #define VECTOR_ADDITION_H_ 31 | 32 | #define TEST_DATA_SIZE 1<<10 33 | 34 | //TRIPCOUNT identifier 35 | const unsigned int c_dim = TEST_DATA_SIZE; 36 | 37 | // Pragma data data_mover is used to generate a Programmable Logic Design with DMA IP 38 | // for simple DMA operation. For correct functionality of DMA, it is assumed that 39 | // memory buffers are allocated to continuous Physical memory Location using sds_alloc. 40 | #pragma SDS data copy(a[0:len], b[0:len], c[0:len]) 41 | #pragma SDS data access_pattern(a:SEQUENTIAL, b:SEQUENTIAL, c:SEQUENTIAL) 42 | #pragma SDS data data_mover(a:AXIDMA_SIMPLE, b:AXIDMA_SIMPLE, c:AXIDMA_SIMPLE) 43 | void vadd_hw(int *a, int *b, int *c, const int len); 44 | #endif 45 | -------------------------------------------------------------------------------- /cpp/getting_started/full_array_2d/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Full 2D Array Read/Write", 3 | "overview": [ 4 | "This is a simple example of accessing full data from 2D array" 5 | ], 6 | "key_concepts": [ "2D data array access"], 7 | "nboard": ["zc702", "microzed", "zed", "zybo"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_accel", 27 | "location" : "mmult.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/full_array_2d/src/mmult.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /******************************************************************************* 31 | 32 | This is simple matrix multiplication example to demonstrate full 2D-array 33 | access 34 | 35 | *******************************************************************************/ 36 | #include "mmult.h" 37 | 38 | void mmult_accel(int *a, int *b, int *c, int dim) { 39 | 40 | //2D Array is used to store input and output matrices 41 | int bufa[MAX_MATRIX_DIM][MAX_MATRIX_DIM]; 42 | int bufb[MAX_MATRIX_DIM][MAX_MATRIX_DIM]; 43 | int bufc[MAX_MATRIX_DIM][MAX_MATRIX_DIM]; 44 | 45 | int matrix_size = dim*dim; 46 | 47 | // Burst Read data from DDR memory and write into 2D local buffer for a & b. 48 | int x = 0, y = 0; 49 | read_data: for (int i = 0 ; i < matrix_size ; i++){ 50 | #pragma HLS PIPELINE 51 | #pragma HLS LOOP_TRIPCOUNT min=c_dim_min*c_dim_min max=c_dim_max*c_dim_max 52 | bufa[x][y] = a[i]; 53 | bufb[x][y] = b[i]; 54 | if (y == dim-1){ x++; y = 0; } else{ y++; } 55 | } 56 | 57 | // Calculate matrix multiplication using local data buffers 58 | // and write result into local buffer for c 59 | matrix_mult: for (int row = 0; row < dim; row++) { 60 | #pragma HLS LOOP_TRIPCOUNT min=c_dim_min max=c_dim_max 61 | for (int col = 0; col < dim; col++) { 62 | #pragma HLS LOOP_TRIPCOUNT min=c_dim_min max=c_dim_max 63 | int result = 0; 64 | for (int k = 0; k < dim; k++) { 65 | #pragma HLS LOOP_TRIPCOUNT min=c_dim_min max=c_dim_max 66 | #pragma HLS pipeline 67 | result += bufa[row][k] * bufb[k][col]; 68 | } 69 | bufc[row][col] = result; 70 | } 71 | } 72 | 73 | // Burst Write result to DDR memory from local buffer 74 | int m = 0, n = 0; 75 | write_data: for (int i = 0 ; i < matrix_size ; i++){ 76 | #pragma HLS LOOP_TRIPCOUNT min=c_dim_min*c_dim_min max=c_dim_max*c_dim_max 77 | #pragma HLS PIPELINE 78 | int tmpData_c = bufc[m][n]; 79 | c[i] = tmpData_c; 80 | if (n == dim-1){ m++; n = 0; }else{ n++; } 81 | } 82 | } 83 | 84 | -------------------------------------------------------------------------------- /cpp/getting_started/full_array_2d/src/mmult.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef MMULT_H_ 31 | #define MMULT_H_ 32 | 33 | // Define Test Matrix Size 34 | #define TEST_MATRIX_DIM 64 35 | 36 | // Define max matrix dimension supported by accelerator 37 | #define MAX_MATRIX_DIM 128 38 | 39 | //TRIPCOUNT identifiers 40 | const unsigned int c_dim_min = 1; 41 | const unsigned int c_dim_max = TEST_MATRIX_DIM; 42 | 43 | // Zero copy interface enabled 44 | #pragma SDS data zero_copy(a[0:dim*dim], b[0:dim*dim], c[0:dim*dim]) 45 | void mmult_accel(int *a, int *b, int *c, int dim); 46 | #endif 47 | -------------------------------------------------------------------------------- /cpp/getting_started/hello_vadd/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Hello Vector Addition", 3 | "overview": [ 4 | "This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function." 5 | ], 6 | "key_concepts": ["Loop Pipelining"], 7 | "keywords": ["#pragma HLS PIPELINE"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "vadd_accel", 27 | "location" : "vector_addition.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/hello_vadd/src/vector_addition.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /********************************************************************************** 31 | Loop Pipelining 32 | 33 | Pipelining is a form of parallelism that allows the FPGA to reuse the 34 | hardware for the next instruction before the current instruction has finished 35 | processing. This maximizes the utilization of the FPGA fabric and allows the 36 | processing of multiple elements of data at the same time. 37 | 38 | In this example we will demonstrate ways to improve the throughput of a 39 | vector addition hardware function using the HLS PIPELINE pragma. 40 | ************************************************************************************/ 41 | 42 | #include "vector_addition.h" 43 | 44 | void vadd_accel(int *a, int *b, int *c, const int len) 45 | { 46 | //Loop will do burst read from A and B and will do burst write 47 | //to C due to pipeline pragma 48 | vadd: for(int i = 0; i < len; i++) { 49 | //By-Default SDSoC accelerators will create separate AXI master interface 50 | //for each memory accessing arguments (here it is a,b, and c), so 51 | //accelerator can initiate burst request to all interfaces concurrently. 52 | #pragma HLS PIPELINE 53 | #pragma HLS LOOP_TRIPCOUNT min=c_dim max=c_dim 54 | c[i] = a[i] + b[i]; 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /cpp/getting_started/hello_vadd/src/vector_addition.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef VECTOR_ADDITION_H_ 31 | #define VECTOR_ADDITION_H_ 32 | 33 | #define TEST_DATA_SIZE 1<<10 34 | 35 | //TRIPCOUNT identifier 36 | const unsigned int c_dim = TEST_DATA_SIZE; 37 | 38 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 39 | // Which has Direct Memory Interface with DDR and PL. 40 | #pragma SDS data zero_copy(a[0:len], b[0:len], c[0:len]) 41 | void vadd_accel(int *a, 42 | int *b, 43 | int *c, 44 | const int len); 45 | #endif 46 | -------------------------------------------------------------------------------- /cpp/getting_started/lmem_2rw/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Two Parallel Read/Write on Local Memory", 3 | "overview": [ 4 | "This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory " 5 | ], 6 | "key_concepts": [ "Hardware Function Optimization", "2port BRAM Utilization", "Two read/write Local Memory"], 7 | "keywords": ["#pragma HLS UNROLL FACTOR=2"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "vadd_accel", 27 | "location" : "vadd.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/lmem_2rw/src/vadd.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef VADD_H_ 31 | #define VADD_H_ 32 | 33 | #define DATA_SIZE 4096 34 | #define BUFFER_SIZE 1024 35 | 36 | //TRIPCOUNT identifiers 37 | const unsigned int c_size = DATA_SIZE/BUFFER_SIZE; 38 | const unsigned int c_chunk_sz = BUFFER_SIZE; 39 | 40 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic 41 | // Design which has Direct Memory Interface with DDR and PL. 42 | #pragma SDS data zero_copy(in1[0:size], in2[0:size], out[0:size]) 43 | void vadd_accel(const int *in1, 44 | const int *in2, 45 | int *out, 46 | int size); 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_fusion/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Loop Fusion", 3 | "overview": [ 4 | "This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function." 5 | ], 6 | "key_concepts": [ "Hardware Function Optimization", "Loop Fusion", "Loop Pipelining"], 7 | "keywords": ["#pragma HLS PIPELINE"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "nearest_neighbor_accel", 27 | "location" : "nearest_neighbor.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_fusion/src/nearest_neighbor.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef NEAREST_NEIGHBOR_H_ 31 | #define NEAREST_NEIGHBOR_H_ 32 | 33 | #define NUM_DIMS 2 34 | #define NUM_POINTS 512 35 | 36 | #define MAX_DIMS 5 37 | 38 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 39 | // Which has Direct Memory Interface with DDR and PL. 40 | #pragma SDS data zero_copy(out[0:dim], points[0:len*dim], search_point[0:dim]) 41 | void nearest_neighbor_accel(int *out, const int *points, 42 | const int *search_point, const int len, 43 | const int dim); 44 | #endif 45 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_perfect/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Loop Perfect", 3 | "overview": [ 4 | "This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop." 5 | ], 6 | "key_concepts": [ "Loop perfect"], 7 | "keywords": ["#pragma HLS PIPELINE", "#pragma HLS ARRAY_PARTITION"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "nearest_accel", 27 | "location" : "nearest.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_perfect/src/nearest.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef NEAREST_H_ 31 | #define NEAREST_H_ 32 | 33 | // Current #Dimension and size of point array 34 | #define DATA_DIM 16 35 | #define DATA_SIZE 1024 36 | 37 | // Maximum #Dimensions for a point 38 | #define MAX_DIM 16 39 | 40 | // Maximum size of point array 41 | #define MAX_SIZE 1024 42 | 43 | //TRIPCOUNT identifiers 44 | const unsigned int c_dim = DATA_DIM; 45 | const unsigned int c_size = DATA_SIZE; 46 | 47 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 48 | // Which has Direct Memory Interface with DDR and PL. 49 | #pragma SDS data zero_copy(in[0:size*dim],point[0:dim],out[0:dim]) 50 | void nearest_accel( 51 | const int *in, // Input Points Array 52 | const int *point, // Current Point 53 | int *out, // Output Point 54 | int size, // Size of the input array 55 | int dim // #Dimensions of the points 56 | ); 57 | #endif 58 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_reorder/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Loop Reorder for better Performance", 3 | "overview": [ 4 | "This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering." 5 | ], 6 | "key_concepts": [ "Hardware Function Optimization", "Loop Reorder to Improve II"], 7 | "keywords": ["#pragma HLS PIPELINE", "#pragma HLS ARRAY_PARTITION"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "mmult_accel", 27 | "location" : "mmult.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/loop_reorder/src/mmult.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef MMULT_H_ 30 | #define MMULT_H_ 31 | 32 | // Size of the input array 33 | #define DATA_SIZE 32 34 | 35 | // Maximum Supported Size 36 | #define MAX_SIZE 32 37 | 38 | //TRIPCOUNT identifiers 39 | const unsigned int c_size_min = 1; 40 | const unsigned int c_size_max = DATA_SIZE; 41 | 42 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 43 | // Which has Direct Memory Interface with DDR and PL. 44 | #pragma SDS data zero_copy(in1[0:dim*dim], in2[0:dim*dim], out[0:dim*dim]) 45 | void mmult_accel( 46 | const int *in1, // Read-Only Matrix 1 47 | const int *in2, // Read-Only Matrix 2 48 | int *out, // Output Result 49 | int dim // Size of one dimension of the matrices 50 | ); 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /cpp/getting_started/multi_threading/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Multi Threading", 3 | "overview": [ 4 | "Simple Multi-Threading application demonstrating performance comparision between software and hardware - with and without threads" 5 | ], 6 | "key_concepts": [ "multi threading"], 7 | "keywords": ["#pragma HLS array_partition", "#pragma HLS PIPELINE", "#pragma SDS data access_pattern"], 8 | "contributors" : [ 9 | { 10 | "group" : "Xilinx, Inc.", 11 | "url" : "http://www.xilinx.com/" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "MARCH2018", 17 | "version": "1.0", 18 | "desc": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "board": [ 25 | "zcu102", 26 | "zc706" 27 | ], 28 | "nboard": [ 29 | "zc702", 30 | "zed" 31 | ], 32 | 33 | "os": [ 34 | "Linux" 35 | ], 36 | "accelerators": [ 37 | { 38 | "name": "mmult_accel", 39 | "location": "mmult_accel.cpp" 40 | } 41 | ], 42 | "libs": [ 43 | "sds_utils" 44 | ], 45 | "runtime" : [ 46 | "C/C++" 47 | ], 48 | "source_dir" : "src/*.cpp", 49 | "pass_string" : "TEST PASSED", 50 | "fail_string" : "TEST FAILED" 51 | } 52 | -------------------------------------------------------------------------------- /cpp/getting_started/multi_threading/src/mmult_accel.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #include 31 | #include 32 | 33 | #include "mmult_accel.h" 34 | 35 | 36 | // Design principles to achieve II = 1 37 | // 1. Stream data into local RAM for inputs (multiple access required) 38 | // 2. Partition local RAMs into N/2 sub-arrays for fully parallel access (dual-port read) 39 | // 3. Pipeline the dot-product loop, to fully unroll it 40 | // 4. Separate multiply-accumulate in inner loop to force two FP operators 41 | 42 | void mmult_accel(float A[N*N], float B[N*N], float C[N*N]) 43 | { 44 | float A_tmp[N][N], B_tmp[N][N]; 45 | #pragma HLS array_partition variable=A_tmp block factor=16 dim=2 46 | #pragma HLS array_partition variable=B_tmp block factor=16 dim=1 47 | 48 | for(int i=0; i Input Vector 1 50 | int *in2 (input) --> Input Vector 2 51 | int *out (output) --> Output Vector 52 | int dim (input) --> Size of one dimension of the vector 53 | 54 | */ 55 | 56 | #include "vadd_vmul.h" 57 | 58 | // Computes vector addition 59 | // out = (in1 + in2) , where in1, in2 are of dimension (dim x dim) 60 | void vadd_accel( 61 | const int *in1, // Read-Only Vector 1 62 | const int *in2, // Read-Only Vector 2 63 | int *out, // Output vector 64 | int dim // Size of one dimension of the vector 65 | ) 66 | { 67 | // Performs vector addition over in1 and in2, and 68 | // writes the result to output 69 | vadd_write_out: for(int j = 0; j < dim; j++) { 70 | #pragma HLS PIPELINE 71 | #pragma HLS LOOP_TRIPCOUNT min=c_size_min max=c_size_max 72 | out[j] = in1[j] + in2[j]; 73 | } 74 | } 75 | 76 | // Computes vector multiplication 77 | // out = (in1 x in2) , where in1, in2 are of dimension (dim x dim) 78 | void vmul_accel( 79 | const int *in1, // Read-Only Vector 1 80 | const int *in2, // Read-Only Vector 2 81 | int *out, // Output Result 82 | int dim // Size of one dimension of the vector 83 | ) 84 | { 85 | // Performs vector multiplication over in1 and in2, and 86 | // writes the result to output 87 | vmul_write_out: for(int j = 0; j < dim; j++) { 88 | #pragma HLS PIPELINE 89 | #pragma HLS LOOP_TRIPCOUNT min=c_size_min max=c_size_max 90 | out[j] = in1[j] * in2[j]; 91 | } 92 | 93 | } 94 | -------------------------------------------------------------------------------- /cpp/getting_started/parallel_accel/src/vadd_vmul.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VADD_VMUL_H_ 30 | #define VADD_VMUL_H_ 31 | 32 | // Size of the input array 33 | #define TEST_DATA_SIZE 4096 34 | 35 | // Maximum times run example 36 | #define NUM_TIMES 4 37 | 38 | //TRIPCOUNT identifiers 39 | const unsigned int c_size_min = 1; 40 | const unsigned int c_size_max = TEST_DATA_SIZE; 41 | 42 | #pragma SDS data zero_copy(in1[0:dim], in2[0:dim], out[0:dim]) 43 | void vadd_accel( 44 | const int *in1, // Read-Only Vector 1 45 | const int *in2, // Read-Only Vector 2 46 | int *out, // Output Vector 47 | int dim // Size of dimension of the vector 48 | ); 49 | 50 | #pragma SDS data zero_copy(in1[0:dim], in2[0:dim], out[0:dim]) 51 | void vmul_accel( 52 | const int *in1, // Read-Only Vector 1 53 | const int *in2, // Read-Only Vector 2 54 | int *out, // Output Vector 55 | int dim // Size of dimension of the vector 56 | ); 57 | 58 | #endif 59 | -------------------------------------------------------------------------------- /cpp/getting_started/row_array_2d/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Read/Write Row of 2D Array", 3 | "overview": [ 4 | "This is a simple example of accessing each row of data from 2D array" 5 | ], 6 | "key_concepts": [ "Row of 2D data array access"], 7 | "keywords": ["hls::stream"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "row_array_2d_accel", 27 | "location" : "row_array_2d.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/row_array_2d/src/row_array_2d.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef ROW_ARRAY_2D_H_ 31 | #define ROW_ARRAY_2D_H_ 32 | 33 | // Parameters Description: 34 | // NUM_ROWS: matrix height 35 | // WORD_PER_ROW: number of words in a row 36 | // BLOCK_SIZE: number of words in an array 37 | #define NUM_ROWS 64 38 | #define WORD_PER_ROW 64 39 | #define BLOCK_SIZE (WORD_PER_ROW*NUM_ROWS) 40 | 41 | #include 42 | // Default data type is integer 43 | typedef int DTYPE; 44 | // use HLS stream library for easy use of AXI-stream interface 45 | typedef hls::stream my_data_fifo; 46 | 47 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 48 | // Which has Direct Memory Interface with DDR and PL. 49 | #pragma SDS data zero_copy(inx[0:BLOCK_SIZE], outx[0:BLOCK_SIZE]) 50 | void row_array_2d_accel(DTYPE *inx, DTYPE *outx, DTYPE alpha); 51 | #endif 52 | -------------------------------------------------------------------------------- /cpp/getting_started/shift_register/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Shift Register", 3 | "overview": [ 4 | "This example demonstrates how to shift values in each clock cycle" 5 | ], 6 | "key_concepts": [ "Hardware Function Optimization", "Shift Register", "FIR"], 7 | "keywords": ["#pragma HLS ARRAY_PARTITION"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "fir_shift_register_accel", 27 | "location" : "fir.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/shift_register/src/fir.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef FIR_H_ 31 | #define FIR_H_ 32 | 33 | #define N_COEFF 11 34 | #define SIGNAL_SIZE 2048 35 | 36 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 37 | // Which has Direct Memory Interface with DDR and PL. 38 | #pragma SDS data zero_copy(signal[0:signal_length],coeff[0:N_COEFF],hw_out[0:signal_length]) 39 | void fir_shift_register_accel(int *signal, 40 | int *coeff, 41 | int *hw_out, 42 | int signal_length); 43 | #endif 44 | -------------------------------------------------------------------------------- /cpp/getting_started/summary.json: -------------------------------------------------------------------------------- 1 | { 2 | "overview": [ 3 | "Getting Started Examples" 4 | ], 5 | "description": [ 6 | "This page contains examples for users who are new to Xilinx SDx SDSoC Flows." 7 | ] 8 | } 9 | -------------------------------------------------------------------------------- /cpp/getting_started/sys_port/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Sysport", 3 | "overview": [ 4 | "This is a simple example which demonstrates sys_port usage" 5 | ], 6 | "key_concepts": [ "sys_port", "memory interface", "memory non-caching"], 7 | "keywords": ["#pragma SDS data sys_port", "#pragms HLS PIPELINE", "sds_alloc_non_cacheable"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "vadd_accel", 27 | "location" : "vadd.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/sys_port/src/vadd.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /******************************************************************************* 31 | 32 | This is a vector addition example to demonstrate "sys_port" feature of 33 | SDSoC compiler. 34 | 35 | *******************************************************************************/ 36 | 37 | #include 38 | #include 39 | #include "vadd.h" 40 | 41 | void vadd_accel(int *a, 42 | int *b, 43 | int *out, 44 | const int size) { 45 | 46 | vadd: for(int i = 0; i < size; i++) { 47 | // By-default SDSoC accelerators generates separate 48 | // AXI master interface for each array arguments (i.e., a,b and out). 49 | // This helps in burst access of all the memory interfaces concurrently. 50 | #pragma HLS PIPELINE 51 | #pragma HLS LOOP_TRIPCOUNT min=c_dim max=c_dim 52 | out[i] = a[i] + b[i]; 53 | } 54 | } 55 | -------------------------------------------------------------------------------- /cpp/getting_started/sys_port/src/vadd.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VADD_H_ 30 | #define VADD_H_ 31 | 32 | #include "sds_utils.h" 33 | 34 | #define DATA_SIZE 2048 35 | 36 | //TRIPCOUNT identifier 37 | const unsigned int c_dim = DATA_SIZE; 38 | 39 | // SDSoC "sys_port" pragma below specifies sds++ compiler to generate 40 | // a design which uses AFI (HP) ports for memory interfacing. 41 | // In this example both input and output buffers uses AFI ports. 42 | // AFI (HP) port is recommended to use with non-cached allocation of buffers 43 | // In this example buffers (a, b & out) are allocated using sds_alloc_non_cached() 44 | // API to make it compatible with sys_port AFI port specification 45 | #pragma SDS data sys_port(a:AFI, b:AFI, out:AFI) 46 | 47 | // SDSoC "access_pattern" pragma below intimates sds++ compiler about the 48 | // access pattern of input and output buffers 49 | // In this example the access pattern is sequential 50 | #pragma SDS data access_pattern(a:SEQUENTIAL) 51 | #pragma SDS data access_pattern(b:SEQUENTIAL) 52 | #pragma SDS data access_pattern(out:SEQUENTIAL) 53 | 54 | // SDSoC "copy" pragma below maps the argument onto a stream 55 | // It requires array elements needs to be accessed in index order. 56 | #pragma SDS data copy(a[0:size], b[0:size], out[0:size]) 57 | void vadd_accel(int *a, int *b, int *out, int size); 58 | #endif 59 | 60 | -------------------------------------------------------------------------------- /cpp/getting_started/systolic_array/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Systolic Array Implementation", 3 | "overview": [ 4 | "This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA." 5 | ], 6 | "key_concepts": [ "Systolic Array"], 7 | "keywords": ["#pragma HLS PIPELINE", "#pragma HLS ARRAY_PARTITION"], 8 | "nboard": ["zc702", "microzed", "zed", "zybo"], 9 | "contributors" : [ 10 | { 11 | "group": "Xilinx", 12 | "url" : "http://www.xilinx.com" 13 | } 14 | ], 15 | "revision" : [ 16 | { 17 | "date" : "JUNE2017", 18 | "version": "1.0", 19 | "description": "Initial Xilinx Release" 20 | } 21 | ], 22 | "compiler" : { 23 | "options" : "-Wno-unused-label" 24 | }, 25 | "accelerators": [ 26 | { 27 | "name" : "mmult_accel", 28 | "location" : "mmult.cpp" 29 | } 30 | ], 31 | "libs": [ 32 | "sds_utils" 33 | ], 34 | "os" : [ 35 | "linux", 36 | "standalone" 37 | ], 38 | "runtime" : [ 39 | "C/C++" 40 | ], 41 | "source_dir" : "src/*.cpp", 42 | "pass_string" : "TEST PASSED", 43 | "fail_string" : "TEST FAILED" 44 | } 45 | -------------------------------------------------------------------------------- /cpp/getting_started/systolic_array/src/mmult.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef MMULT_H_ 30 | #define MMULT_H_ 31 | 32 | // Array Size to access 33 | #define DATA_SIZE 12 34 | 35 | // Maximum Array Size 36 | #define MAX_SIZE 12 37 | 38 | //TRIPCOUNT identifier 39 | const unsigned int c_dim = DATA_SIZE; 40 | 41 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 42 | // Which has Direct Memory Interface with DDR and PL. 43 | #pragma SDS data zero_copy(a[0:a_row*a_col], b[0:a_col*b_col], c[0:a_row*b_col]) 44 | void mmult_accel( 45 | const int *a, // Read-Only Matrix A 46 | const int *b, // Read-Only Matrix B 47 | int *c, // Output Result 48 | int a_row, // Matrix A Row Size 49 | int a_col, // Matrix A Col Size 50 | int b_col // Matrix B Col Size 51 | ); 52 | #endif 53 | -------------------------------------------------------------------------------- /cpp/getting_started/wide_memory_rw/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Wide Memory Read/Write", 3 | "overview": [ 4 | "This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator." 5 | ], 6 | "key_concepts": [ "wide memory access", "burst read and write", "custom datatype"], 7 | "keywords": ["struct"], 8 | "nboard": ["zc702", "microzed", "zed", "zybo"], 9 | "contributors" : [ 10 | { 11 | "group": "Xilinx", 12 | "url" : "http://www.xilinx.com" 13 | } 14 | ], 15 | "revision" : [ 16 | { 17 | "date" : "JUNE2017", 18 | "version": "1.0", 19 | "description": "Initial Xilinx Release" 20 | } 21 | ], 22 | "compiler" : { 23 | "options" : "-Wno-unused-label" 24 | }, 25 | "accelerators": [ 26 | { 27 | "name" : "vadd_accel", 28 | "location" : "vadd.cpp" 29 | } 30 | ], 31 | "libs": [ 32 | "sds_utils" 33 | ], 34 | "os" : [ 35 | "linux" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/wide_memory_rw/src/vadd.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | /******************************************************************************* 31 | 32 | Wide Memory Access Example using struct data type of 128bit size 33 | 34 | This is vector addition example to demonstrate Wide Memory access of 128bit 35 | data width using struct datatype of 128bit size 36 | 37 | *******************************************************************************/ 38 | #include "vadd.h" 39 | 40 | //Memory Datawidth of accelerator is calculated based on argument type. 41 | //Here argument type of in1 and in2 is wide_dt which is 128bit wide, so memory 42 | //interface will be created to 128bit wide. 43 | void vadd_accel( 44 | const wide_dt *in1, // Read-Only Vector 1 45 | const wide_dt *in2, // Read-Only Vector 2 46 | wide_dt *out, // Output Result 47 | int size // Size of total elements 48 | ) 49 | { 50 | vadd:for(int i = 0; i < size; ++i) 51 | { 52 | //Pipelined this loop which will eventually infer burst read/write 53 | //for in1, in2 and out as access pattern is sequential 54 | #pragma HLS pipeline 55 | #pragma HLS LOOP_TRIPCOUNT min=c_size max=c_size 56 | wide_dt tmpV1 = in1[i]; 57 | wide_dt tmpV2 = in2[i]; 58 | wide_dt tmpOut; 59 | for (int k = 0 ; k < NUM_ELEMENTS ; k++){ 60 | //As Upper loop "vadd" is marked for Pipeline so this loop 61 | //will be unrolled and will do parallel vector addition for 62 | //all elements of structure. 63 | tmpOut.data[k] = tmpV1.data[k] + tmpV2.data[k]; 64 | } 65 | out[i] = tmpOut; 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /cpp/getting_started/wide_memory_rw/src/vadd.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef VADD_H_ 30 | #define VADD_H_ 31 | 32 | #define NUM_ELEMENTS 4 // To make structure size 128bit 33 | //Structure overall width is set to 4 Integers = 4 *32 = 128bit to match to 34 | //Zynq ultrascale Memory Interface Datawidth to get the optimum memory access 35 | //performance. 36 | typedef struct wide_dt_struct{ 37 | int data[NUM_ELEMENTS]; 38 | } __attribute__ ((packed, aligned(4))) wide_dt; 39 | 40 | #define DATA_SIZE 16384 41 | 42 | //TRIPCOUNT identifier 43 | const unsigned int c_size = DATA_SIZE/NUM_ELEMENTS; 44 | 45 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 46 | // Which has Direct Memory Interface with DDR and PL. 47 | #pragma SDS data zero_copy(in1[0:size],in2[0:size],out[0:size]) 48 | void vadd_accel(const wide_dt *in1, // Read-Only Vector 1 49 | const wide_dt *in2, // Read-Only Vector 2 50 | wide_dt *out, // Output Result 51 | int size // Size in integer 52 | ); 53 | #endif 54 | -------------------------------------------------------------------------------- /cpp/getting_started/window_array_2d/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Read/Write Window of 2D Array", 3 | "overview": [ 4 | "This is a simple example of accessing window of data from 2D array" 5 | ], 6 | "key_concepts": [ "Window of 2D data array access"], 7 | "keywords": ["#pragma HLS DATAFLOW", "#pragma HLS PIPELINE", "#pragma HLS stream"], 8 | "contributors" : [ 9 | { 10 | "group": "Xilinx", 11 | "url" : "http://www.xilinx.com" 12 | } 13 | ], 14 | "revision" : [ 15 | { 16 | "date" : "JUNE2017", 17 | "version": "1.0", 18 | "description": "Initial Xilinx Release" 19 | } 20 | ], 21 | "compiler" : { 22 | "options" : "-Wno-unused-label" 23 | }, 24 | "accelerators": [ 25 | { 26 | "name" : "window_array_2d_accel", 27 | "location" : "window_array_2d.cpp" 28 | } 29 | ], 30 | "libs": [ 31 | "sds_utils" 32 | ], 33 | "os" : [ 34 | "linux", 35 | "standalone" 36 | ], 37 | "runtime" : [ 38 | "C/C++" 39 | ], 40 | "source_dir" : "src/*.cpp", 41 | "pass_string" : "TEST PASSED", 42 | "fail_string" : "TEST FAILED" 43 | } 44 | -------------------------------------------------------------------------------- /cpp/getting_started/window_array_2d/src/window_array_2d.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | #ifndef WINDOW_ARRAY_2D_H_ 31 | #define WINDOW_ARRAY_2D_H_ 32 | // Parameters Description: 33 | // TILE_PER_ROW: number of tiles/windows in each matrix row 34 | // TILE_WIDTH: number of words in each tile/window 35 | // TILE_PER_COLUMN: number of tiles/windows in each matrix column 36 | // TILE_HEIGHT: number of rows in matrix tile/window 37 | // BLOCK_SIZE: number of words in an matrix 38 | 39 | #define TILE_PER_ROW 4 40 | #define TILE_WIDTH 16 41 | #define TILE_PER_COLUMN 8 42 | #define TILE_HEIGHT 8 43 | #define BLOCK_SIZE (TILE_WIDTH*TILE_PER_ROW*TILE_PER_COLUMN*TILE_HEIGHT) 44 | 45 | #include 46 | // Default data type is integer 47 | typedef int DTYPE; 48 | // use HLS stream library for easy use of AXI-stream interface 49 | typedef hls::stream my_data_fifo; 50 | 51 | // Pragma below Specifies sds++ Compiler to Generate a Programmable Logic Design 52 | // Which has Direct Memory Interface with DDR and PL. 53 | #pragma SDS data zero_copy(inx[0:BLOCK_SIZE], outx[0:BLOCK_SIZE]) 54 | void window_array_2d_accel(DTYPE *inx, DTYPE *outx, DTYPE alpha); 55 | #endif 56 | -------------------------------------------------------------------------------- /libs/README.md: -------------------------------------------------------------------------------- 1 | Support Library 2 | ================= 3 | 4 | Welcome to support library directory which contains various useful 5 | support implementations. Content in this directory is used in PS (Processing System) 6 | only. 7 | 8 | -------------------------------------------------------------------------------- /libs/bitmap/bitmap.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef BITMAP_DOT_H 30 | #define BITMAP_DOT_H 31 | 32 | #include 33 | 34 | class BitmapInterface 35 | { 36 | private: 37 | char* core ; 38 | char* dib ; 39 | const char* filename ; 40 | int* image ; 41 | 42 | // Core header information 43 | unsigned short magicNumber ; 44 | unsigned int fileSize ; 45 | unsigned int offsetOfImage ; 46 | 47 | // DIB information 48 | int sizeOfDIB ; 49 | int sizeOfImage ; 50 | int height ; 51 | int width ; 52 | 53 | public: 54 | BitmapInterface(const char* f) ; 55 | ~BitmapInterface() ; 56 | 57 | bool readBitmapFile() ; 58 | bool writeBitmapFile(int* otherImage = NULL); 59 | 60 | inline int* bitmap() { return image ; } 61 | unsigned int numPixels() { return sizeOfImage/3 ; } 62 | 63 | inline int getHeight() { return height ; } 64 | inline int getWidth() { return width ; } 65 | 66 | } ; 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /libs/bitmap/bitmap.mk: -------------------------------------------------------------------------------- 1 | bitmap_SRCS:=${COMMON_REPO}/libs/bitmap/bitmap.cpp 2 | bitmap_HDRS:=${COMMON_REPO}/libs/bitmap/bitmap.h 3 | bitmap_CXXFLAGS:=-I${COMMON_REPO}/libs/bitmap 4 | -------------------------------------------------------------------------------- /libs/opencl/opencl.mk: -------------------------------------------------------------------------------- 1 | # Definition of include file locations 2 | OPENCL12_INCLUDE:= $(XILINX_SDACCEL)/runtime/include/1_2 3 | 4 | # Library directories 5 | SDA_LIB:=$(XILINX_SDACCEL)/lib/lnx64.o 6 | 7 | opencl_CXXFLAGS=-I$(OPENCL12_INCLUDE) 8 | 9 | OPENCL_LIB:=$(XILINX_SDACCEL)/runtime/lib/aarch64 10 | opencl_LDFLAGS=-L$(OPENCL_LIB) -L$(SDA_LIB) -lxilinxopencl -lpthread 11 | -------------------------------------------------------------------------------- /libs/sds_utils/sds_utils.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | #ifndef SDS_UTILS_H_ 30 | #define SDS_UTILS_H_ 31 | #include 32 | #include "sds_lib.h" 33 | namespace sds_utils { 34 | class perf_counter 35 | { 36 | 37 | private: 38 | uint64_t tot, cnt, calls; 39 | 40 | public: 41 | perf_counter() : tot(0), cnt(0), calls(0) {}; 42 | inline void reset() { tot = cnt = calls = 0; } 43 | inline void start() { cnt = sds_clock_counter(); calls++; }; 44 | inline void stop() { tot += (sds_clock_counter() - cnt); }; 45 | inline uint64_t avg_cpu_cycles() {return (tot / calls); }; 46 | }; 47 | } 48 | #endif 49 | -------------------------------------------------------------------------------- /libs/sds_utils/sds_utils.mk: -------------------------------------------------------------------------------- 1 | sds_utils_HDRS:=$(ABS_COMMON_REPO)/libs/sds_utils/ 2 | -------------------------------------------------------------------------------- /libs/xcl2/xcl2.mk: -------------------------------------------------------------------------------- 1 | xcl2_SRCS:=${COMMON_REPO}/libs/xcl2/xcl2.cpp 2 | xcl2_HDRS:=${COMMON_REPO}/libs/xcl2/xcl2.hpp 3 | 4 | xcl2_CXXFLAGS:=-I${COMMON_REPO}/libs/xcl2 5 | -------------------------------------------------------------------------------- /ocl/README.md: -------------------------------------------------------------------------------- 1 | Zynq MPSoC OpenCL Example Repository 2 | =============================== 3 | 4 | Welcome to the Zynq MPSoC OpenCL example repository. This repository contains 5 | latest examples to get you started with application optimization targeting 6 | Xilinx Embedded FPGA acceleration boards. All examples are ready to be compiled 7 | and executed on boards. The "getting_started" directory contains latest Zynq MPSoC OpenCL 8 | examples which are intended to help in quick learning of various key concepts. 9 | It also provides insights into new features and optimization tricks which are 10 | quite handy in identical scenarios. 11 | -------------------------------------------------------------------------------- /ocl/common/makefile_gen/update_makegen_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | ../../common/makefile_gen/makegen.py description.json 5 | cd .. 6 | echo "$d" 7 | done 8 | -------------------------------------------------------------------------------- /ocl/common/readme_gen/gs_summary.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import os, re 4 | import fnmatch 5 | import json 6 | import sys 7 | sys.path.append(".") 8 | import gs_summary_util 9 | 10 | gs_summary_util.genReadMe(".") 11 | -------------------------------------------------------------------------------- /ocl/common/readme_gen/gs_summary_subdir.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import os, re 4 | import fnmatch 5 | import json 6 | import sys 7 | 8 | sys.path.append(".") 9 | import gs_summary_util 10 | 11 | gs_summary_util.genReadMe2(".") 12 | -------------------------------------------------------------------------------- /ocl/common/readme_gen/update_readme_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | ../../common/readme_gen/readme_gen.py description.json 5 | cd .. 6 | echo "$d" 7 | done 8 | -------------------------------------------------------------------------------- /ocl/getting_started/custom_datatype_ocl/Makefile: -------------------------------------------------------------------------------- 1 | REPORT := none 2 | TARGET := hw 3 | PLATFORM := zcu102 4 | BUILD_DIR := ./build/$(PLATFORM)_$(TARGET) 5 | 6 | CXX := aarch64-linux-gnu-g++ 7 | XOCC := xocc 8 | 9 | # Points to Utility Directory 10 | COMMON_REPO = ../../../ 11 | ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO)) 12 | 13 | # Include Libraries 14 | include $(ABS_COMMON_REPO)/libs/bitmap/bitmap.mk 15 | include $(ABS_COMMON_REPO)/libs/xcl2/xcl2.mk 16 | 17 | # Host compiler global settings 18 | CXXFLAGS += -I $(XILINX_SDX)/runtime/include/1_2/ -I/$(XILINX_SDX)/Vivado_HLS/include/ -O2 -g -Wall -fmessage-length=0 -std=c++14 19 | LDFLAGS += -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L$(XILINX_SDX)/runtime/lib/aarch64 $(bitmap_CXXFLAGS) $(xcl2_CXXFLAGS) 20 | 21 | # Kernel compiler global settings 22 | CLFLAGS = -t hw --platform $(PLATFORM) --save-temps --clkid 0 23 | 24 | ifneq ($(REPORT), none) 25 | CLFLAGS += --report $(REPORT) 26 | endif 27 | 28 | BINARY_CONTAINERS += $(BUILD_DIR)/rgb_to_hsv.xclbin 29 | BINARY_CONTAINER_1_OBJS += $(BUILD_DIR)/rgb_to_hsv.xo 30 | ALL_KERNEL_OBJS += $(BUILD_DIR)/rgb_to_hsv.xo 31 | 32 | 33 | ALL_MESSAGE_FILES = $(subst .xo,.mdb,$(ALL_KERNEL_OBJS)) $(subst .xclbin,.mdb,$(BINARY_CONTAINERS)) 34 | 35 | HOST_SRCS = src/host.cpp $(bitmap_SRCS) $(xcl2_SRCS) 36 | 37 | EXECUTABLE = rgb_to_hsv 38 | 39 | CP = cp -rf 40 | DATA = ./data 41 | 42 | .PHONY: all clean cleanall docs 43 | all: $(BUILD_DIR)/$(EXECUTABLE) $(BINARY_CONTAINERS) 44 | - $(CP) $(BUILD_DIR)/$(EXECUTABLE) $(BUILD_DIR)/sd_card/ 45 | - if test -d $(DATA); then $(CP) $(DATA) $(BUILD_DIR)/sd_card/; fi 46 | 47 | # Building kernel 48 | $(BUILD_DIR)/rgb_to_hsv.xo: ./src/rgb_to_hsv.cl 49 | mkdir -p $(BUILD_DIR) 50 | -@$(RM) $@ 51 | @echo 'Building Target: $@' 52 | $(XOCC) $(CLFLAGS) -c -k rgb_to_hsv --messageDb $(subst .xo,.mdb,$@) -I'$( or make all PLATFORM= 40 | ``` 41 | where the *PLATFORM* variable accepts one board. 42 | 43 | ## 4. DESIGN FILE HIERARCHY 44 | Application code is located in the src directory. Accelerator binary files will be compiled to the build directory. A listing of all the files in this example is shown below 45 | 46 | ``` 47 | Makefile 48 | README.md 49 | data/input.bmp 50 | description.json 51 | src/host.cpp 52 | src/rgb_to_hsv.cl 53 | src/rgb_to_hsv.h 54 | ``` 55 | 56 | ## 5. COMPILATION AND EXECUTION 57 | ### Compiling for Application Execution on the FPGA Board 58 | The command to compile the application for execution on the FPGA acceleration board is 59 | ``` 60 | make all 61 | ``` 62 | The default target for the makefile is to compile for hardware. Therefore, setting the TARGETS option is not required. 63 | 64 | *NOTE:* Compilation for application execution in hardware generates custom logic to implement the functionality of the kernels in an application. 65 | It is typical for hardware compile times to range from 30 minutes to a couple of hours. 66 | 67 | 68 | ## 6. SUPPORT 69 | For more information about SDSoC check the [SDSoC user Guides][] 70 | 71 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 72 | 73 | 74 | ## 7. LICENSE AND CONTRIBUTING TO THE REPOSITORY 75 | The source for this project is licensed under the [3-Clause BSD License][] 76 | 77 | To contribute to this project, follow the guidelines in the [Repository Contribution README][] 78 | 79 | ## 8. ACKNOWLEDGEMENTS 80 | This example is written by developers at 81 | - [Xilinx, Inc.](http://www.xilinx.com) 82 | 83 | 84 | [3-Clause BSD License]: ../../../LICENSE.txt 85 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 86 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 87 | [Repository Contribution README]: ../../../CONTRIBUTING.md 88 | -------------------------------------------------------------------------------- /ocl/getting_started/custom_datatype_ocl/data/input.bmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/SDSoC_Examples/4167f4ba94ca50fa8367aaf15f2e9169aa35a64b/ocl/getting_started/custom_datatype_ocl/data/input.bmp -------------------------------------------------------------------------------- /ocl/getting_started/custom_datatype_ocl/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Custom Data Type (CL)", 3 | "overview": [ 4 | "This is simple example of RGB to HSV conversion to demonstrate Custom DATA Type usages in OpenCL Based Kernel. Xilinx HLS Compiler Supports Custom Data Type to use for operation as well as Memory Interface between Kernel and Global Memory." 5 | ], 6 | "key_concepts": ["Custom Datatype"], 7 | "keywords": ["struct"], 8 | "os": [ 9 | "Linux" 10 | ], 11 | "libs": [ 12 | "bitmap","xcl2" 13 | ], 14 | "runtime": [ 15 | "OpenCL" 16 | ], 17 | "board": ["zcu102", "zcu104", "zcu106"], 18 | "cmd_args" : "BUILD/default.xclbin PROJECT/data/input.bmp", 19 | "containers" : [ 20 | { 21 | "name" : "rgb_to_hsv", 22 | "accelerators": [ 23 | { 24 | "name": "rgb_to_hsv", 25 | "location": "src/rgb_to_hsv.cl" 26 | } 27 | ] 28 | } 29 | ], 30 | "contributors" : [ 31 | { 32 | "group" : "Xilinx, Inc.", 33 | "url" : "http://www.xilinx.com" 34 | } 35 | ], 36 | "revision" : [ 37 | { 38 | "date" : "JUL2017", 39 | "version" : "1.0", 40 | "description" : "Initial revision" 41 | } 42 | ] 43 | } 44 | -------------------------------------------------------------------------------- /ocl/getting_started/custom_datatype_ocl/src/rgb_to_hsv.h: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | //Min and Max Macro Function 31 | #define imin(X, Y) (((X) < (Y)) ? (X) : (Y)) 32 | #define imax(X, Y) (((X) > (Y)) ? (X) : (Y)) 33 | 34 | #ifdef USE_IN_HOST 35 | typedef unsigned char UCHAR_DT; 36 | #else 37 | typedef uchar UCHAR_DT; 38 | #endif 39 | //Custom Data Type for RGB Image Pixel containing Red(r), Green(g) and Blue(b) 40 | //element. Extra Pad element is added to make struct size to 32bit. 41 | // It is recommended to make custom datatype multiple of 32 bit to use global 42 | // memory access efficiently. 43 | typedef struct RGBcolor_struct 44 | { 45 | UCHAR_DT r; 46 | UCHAR_DT g; 47 | UCHAR_DT b; 48 | UCHAR_DT pad; 49 | } RGBcolor; 50 | 51 | 52 | //Custom Data Type for HSV Image Pixel containing Hue(h), Saturation(s), 53 | //and Value(v) element. Extra pad element is added to make struct size to 32bit. 54 | // It is recommended to make custom datatype multiple of 32 bit to use global 55 | // memory access efficiently. 56 | typedef struct HSVcolor_struct 57 | { 58 | UCHAR_DT h; 59 | UCHAR_DT s; 60 | UCHAR_DT v; 61 | UCHAR_DT pad; 62 | }HSVcolor; 63 | -------------------------------------------------------------------------------- /ocl/getting_started/dataflow_func_ocl/.gitignore: -------------------------------------------------------------------------------- 1 | host 2 | -------------------------------------------------------------------------------- /ocl/getting_started/dataflow_func_ocl/Makefile: -------------------------------------------------------------------------------- 1 | REPORT := none 2 | TARGET := hw 3 | PLATFORM := zcu102 4 | BUILD_DIR := ./build/$(PLATFORM)_$(TARGET) 5 | 6 | CXX := aarch64-linux-gnu-g++ 7 | XOCC := xocc 8 | 9 | # Points to Utility Directory 10 | COMMON_REPO = ../../../ 11 | ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO)) 12 | 13 | # Include Libraries 14 | include $(ABS_COMMON_REPO)/libs/xcl2/xcl2.mk 15 | 16 | # Host compiler global settings 17 | CXXFLAGS += -I $(XILINX_SDX)/runtime/include/1_2/ -I/$(XILINX_SDX)/Vivado_HLS/include/ -O2 -g -Wall -fmessage-length=0 -std=c++14 18 | LDFLAGS += -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L$(XILINX_SDX)/runtime/lib/aarch64 $(xcl2_CXXFLAGS) 19 | 20 | # Kernel compiler global settings 21 | CLFLAGS = -t hw --platform $(PLATFORM) --save-temps --clkid 0 22 | 23 | ifneq ($(REPORT), none) 24 | CLFLAGS += --report $(REPORT) 25 | endif 26 | 27 | BINARY_CONTAINERS += $(BUILD_DIR)/adder.xclbin 28 | BINARY_CONTAINER_1_OBJS += $(BUILD_DIR)/adder.xo 29 | ALL_KERNEL_OBJS += $(BUILD_DIR)/adder.xo 30 | 31 | 32 | ALL_MESSAGE_FILES = $(subst .xo,.mdb,$(ALL_KERNEL_OBJS)) $(subst .xclbin,.mdb,$(BINARY_CONTAINERS)) 33 | 34 | HOST_SRCS = src/host.cpp $(xcl2_SRCS) 35 | 36 | EXECUTABLE = adder 37 | 38 | CP = cp -rf 39 | 40 | .PHONY: all clean cleanall docs 41 | all: $(BUILD_DIR)/$(EXECUTABLE) $(BINARY_CONTAINERS) 42 | - $(CP) $(BUILD_DIR)/$(EXECUTABLE) $(BUILD_DIR)/sd_card/ 43 | 44 | # Building kernel 45 | $(BUILD_DIR)/adder.xo: ./src/adder.cl 46 | mkdir -p $(BUILD_DIR) 47 | -@$(RM) $@ 48 | @echo 'Building Target: $@' 49 | $(XOCC) $(CLFLAGS) -c -k adder --messageDb $(subst .xo,.mdb,$@) -I'$( or make all PLATFORM= 36 | ``` 37 | where the *PLATFORM* variable accepts one board. 38 | 39 | ## 4. DESIGN FILE HIERARCHY 40 | Application code is located in the src directory. Accelerator binary files will be compiled to the build directory. A listing of all the files in this example is shown below 41 | 42 | ``` 43 | .gitignore 44 | Makefile 45 | README.md 46 | description.json 47 | src/adder.cl 48 | src/host.cpp 49 | ``` 50 | 51 | ## 5. COMPILATION AND EXECUTION 52 | ### Compiling for Application Execution on the FPGA Board 53 | The command to compile the application for execution on the FPGA acceleration board is 54 | ``` 55 | make all 56 | ``` 57 | The default target for the makefile is to compile for hardware. Therefore, setting the TARGETS option is not required. 58 | 59 | *NOTE:* Compilation for application execution in hardware generates custom logic to implement the functionality of the kernels in an application. 60 | It is typical for hardware compile times to range from 30 minutes to a couple of hours. 61 | 62 | 63 | ## 6. SUPPORT 64 | For more information about SDSoC check the [SDSoC user Guides][] 65 | 66 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 67 | 68 | 69 | ## 7. LICENSE AND CONTRIBUTING TO THE REPOSITORY 70 | The source for this project is licensed under the [3-Clause BSD License][] 71 | 72 | To contribute to this project, follow the guidelines in the [Repository Contribution README][] 73 | 74 | ## 8. ACKNOWLEDGEMENTS 75 | This example is written by developers at 76 | - [Xilinx, Inc.](http://www.xilinx.com) 77 | 78 | 79 | [3-Clause BSD License]: ../../../LICENSE.txt 80 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 81 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 82 | [Repository Contribution README]: ../../../CONTRIBUTING.md 83 | -------------------------------------------------------------------------------- /ocl/getting_started/dataflow_func_ocl/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Dataflow Function OpenCL (CL)", 3 | "overview": [ 4 | "This is simple example of vector addition to demonstrate Dataflow functionality in OpenCL Kernel. OpenCL Dataflow allows user to run multiple functions together to achieve higher throughput." 5 | ], 6 | "os": [ 7 | "Linux" 8 | ], 9 | "libs": [ 10 | "xcl2" 11 | ], 12 | "runtime": [ 13 | "OpenCL" 14 | ], 15 | "board": ["zcu102", "zcu104", "zcu106"], 16 | "containers" : [ 17 | { 18 | "name" : "adder", 19 | "accelerators": [ 20 | { 21 | "name": "adder", 22 | "location": "src/adder.cl", 23 | "clflags" : "--xp param:compiler.xclDataflowFifoDepth=32" 24 | } 25 | ] 26 | } 27 | ], 28 | "contributors" : [ 29 | { 30 | "group" : "Xilinx, Inc.", 31 | "url" : "http://www.xilinx.com" 32 | } 33 | ], 34 | "revision" : [ 35 | { 36 | "date" : "JUL2017", 37 | "version" : "1.0", 38 | "description" : "Initial revision" 39 | } 40 | ] 41 | } 42 | -------------------------------------------------------------------------------- /ocl/getting_started/hello_vadd_ocl/Makefile: -------------------------------------------------------------------------------- 1 | REPORT := none 2 | TARGET := hw 3 | PLATFORM := zcu102 4 | BUILD_DIR := ./build/$(PLATFORM)_$(TARGET) 5 | 6 | CXX := aarch64-linux-gnu-g++ 7 | XOCC := xocc 8 | 9 | # Points to Utility Directory 10 | COMMON_REPO = ../../../ 11 | ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO)) 12 | 13 | # Include Libraries 14 | include $(ABS_COMMON_REPO)/libs/xcl2/xcl2.mk 15 | 16 | # Host compiler global settings 17 | CXXFLAGS += -I $(XILINX_SDX)/runtime/include/1_2/ -I/$(XILINX_SDX)/Vivado_HLS/include/ -O2 -g -Wall -fmessage-length=0 -std=c++14 18 | LDFLAGS += -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L$(XILINX_SDX)/runtime/lib/aarch64 $(xcl2_CXXFLAGS) 19 | 20 | # Kernel compiler global settings 21 | CLFLAGS = -t hw --platform $(PLATFORM) --save-temps --clkid 0 22 | 23 | ifneq ($(REPORT), none) 24 | CLFLAGS += --report $(REPORT) 25 | endif 26 | 27 | BINARY_CONTAINERS += $(BUILD_DIR)/vadd.xclbin 28 | BINARY_CONTAINER_1_OBJS += $(BUILD_DIR)/vadd.xo 29 | ALL_KERNEL_OBJS += $(BUILD_DIR)/vadd.xo 30 | 31 | 32 | ALL_MESSAGE_FILES = $(subst .xo,.mdb,$(ALL_KERNEL_OBJS)) $(subst .xclbin,.mdb,$(BINARY_CONTAINERS)) 33 | 34 | HOST_SRCS = src/host.cpp $(xcl2_SRCS) 35 | 36 | EXECUTABLE = vadd 37 | 38 | CP = cp -rf 39 | 40 | .PHONY: all clean cleanall docs 41 | all: $(BUILD_DIR)/$(EXECUTABLE) $(BINARY_CONTAINERS) 42 | - $(CP) $(BUILD_DIR)/$(EXECUTABLE) $(BUILD_DIR)/sd_card/ 43 | 44 | # Building kernel 45 | $(BUILD_DIR)/vadd.xo: ./src/vadd.cl 46 | mkdir -p $(BUILD_DIR) 47 | -@$(RM) $@ 48 | @echo 'Building Target: $@' 49 | $(XOCC) $(CLFLAGS) -c -k vadd --messageDb $(subst .xo,.mdb,$@) -I'$( or make all PLATFORM= 36 | ``` 37 | where the *PLATFORM* variable accepts one board. 38 | 39 | ## 4. DESIGN FILE HIERARCHY 40 | Application code is located in the src directory. Accelerator binary files will be compiled to the build directory. A listing of all the files in this example is shown below 41 | 42 | ``` 43 | Makefile 44 | README.md 45 | description.json 46 | src/host.cpp 47 | src/vadd.cl 48 | ``` 49 | 50 | ## 5. COMPILATION AND EXECUTION 51 | ### Compiling for Application Execution on the FPGA Board 52 | The command to compile the application for execution on the FPGA acceleration board is 53 | ``` 54 | make all 55 | ``` 56 | The default target for the makefile is to compile for hardware. Therefore, setting the TARGETS option is not required. 57 | 58 | *NOTE:* Compilation for application execution in hardware generates custom logic to implement the functionality of the kernels in an application. 59 | It is typical for hardware compile times to range from 30 minutes to a couple of hours. 60 | 61 | 62 | ## 6. SUPPORT 63 | For more information about SDSoC check the [SDSoC user Guides][] 64 | 65 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 66 | 67 | 68 | ## 7. LICENSE AND CONTRIBUTING TO THE REPOSITORY 69 | The source for this project is licensed under the [3-Clause BSD License][] 70 | 71 | To contribute to this project, follow the guidelines in the [Repository Contribution README][] 72 | 73 | ## 8. ACKNOWLEDGEMENTS 74 | This example is written by developers at 75 | - [Xilinx, Inc.](http://www.xilinx.com) 76 | 77 | 78 | [3-Clause BSD License]: ../../../LICENSE.txt 79 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 80 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 81 | [Repository Contribution README]: ../../../CONTRIBUTING.md 82 | -------------------------------------------------------------------------------- /ocl/getting_started/hello_vadd_ocl/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Vector Addition (CL)", 3 | "overview": [ 4 | "This is a simple OpenCL example of vector addition. The purpose of this code is to introduce the user to application development in SDx." 5 | ], 6 | "os": [ 7 | "Linux" 8 | ], 9 | "libs": [ 10 | "xcl2" 11 | ], 12 | "runtime": [ 13 | "OpenCL" 14 | ], 15 | "board": ["zcu102", "zcu104", "zcu106"], 16 | "containers" : [ 17 | { 18 | "name" : "vadd", 19 | "accelerators": [ 20 | { 21 | "name": "vadd", 22 | "location": "src/vadd.cl" 23 | } 24 | ] 25 | } 26 | ], 27 | "contributors" : [ 28 | { 29 | "group" : "Xilinx, Inc.", 30 | "url" : "http://www.xilinx.com" 31 | } 32 | ], 33 | "revision" : [ 34 | { 35 | "date" : "JUNE2017", 36 | "version" : "1.0", 37 | "description" : "Initial revision" 38 | } 39 | ] 40 | } 41 | -------------------------------------------------------------------------------- /ocl/getting_started/hello_vadd_ocl/src/vadd.cl: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | //------------------------------------------------------------------------------ 31 | // 32 | // kernel: vadd 33 | // 34 | // Purpose: Demonstrate Vector Add in OpenCL 35 | // 36 | 37 | #define N 128 38 | 39 | __kernel void __attribute__ ((reqd_work_group_size(1, 1, 1))) 40 | vadd( 41 | __global int* a, 42 | __global int* b, 43 | __global int* c, 44 | const int length) { 45 | 46 | // optimized kernel code 47 | int result[N]; 48 | int iterations = (length-1)/N + 1; 49 | for(int i=0; i < iterations; i++) 50 | { 51 | int j; 52 | read_a: 53 | __attribute__((xcl_pipeline_loop)) 54 | for(j=0; j < N; j++) 55 | result[j] = a[i*N+j]; 56 | 57 | read_b_write_c: // simultaneously both read and write are supported 58 | __attribute__((xcl_pipeline_loop)) 59 | for(j=0; j < N; j++) 60 | c[i*N+j] = result[j] + b[i*N+j]; 61 | } 62 | 63 | return; 64 | } 65 | -------------------------------------------------------------------------------- /ocl/getting_started/multiple_interfaces_ocl/Makefile: -------------------------------------------------------------------------------- 1 | REPORT := none 2 | TARGET := hw 3 | PLATFORM := zcu102 4 | BUILD_DIR := ./build/$(PLATFORM)_$(TARGET) 5 | 6 | CXX := aarch64-linux-gnu-g++ 7 | XOCC := xocc 8 | 9 | # Points to Utility Directory 10 | COMMON_REPO = ../../../ 11 | ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO)) 12 | 13 | # Include Libraries 14 | include $(ABS_COMMON_REPO)/libs/xcl2/xcl2.mk 15 | 16 | # Host compiler global settings 17 | CXXFLAGS += -I $(XILINX_SDX)/runtime/include/1_2/ -I/$(XILINX_SDX)/Vivado_HLS/include/ -O2 -g -Wall -fmessage-length=0 -std=c++14 18 | LDFLAGS += -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L$(XILINX_SDX)/runtime/lib/aarch64 $(xcl2_CXXFLAGS) 19 | 20 | # Kernel compiler global settings 21 | CLFLAGS = -t hw --platform $(PLATFORM) --save-temps --clkid 0 22 | 23 | ifneq ($(REPORT), none) 24 | CLFLAGS += --report $(REPORT) 25 | endif 26 | 27 | BINARY_CONTAINERS += $(BUILD_DIR)/vadd_accel.xclbin 28 | BINARY_CONTAINER_1_OBJS += $(BUILD_DIR)/vadd_accel.xo 29 | ALL_KERNEL_OBJS += $(BUILD_DIR)/vadd_accel.xo 30 | 31 | 32 | ALL_MESSAGE_FILES = $(subst .xo,.mdb,$(ALL_KERNEL_OBJS)) $(subst .xclbin,.mdb,$(BINARY_CONTAINERS)) 33 | 34 | HOST_SRCS = src/host.cpp $(xcl2_SRCS) 35 | 36 | EXECUTABLE = vadd_accel 37 | 38 | CP = cp -rf 39 | 40 | .PHONY: all clean cleanall docs 41 | all: $(BUILD_DIR)/$(EXECUTABLE) $(BINARY_CONTAINERS) 42 | - $(CP) $(BUILD_DIR)/$(EXECUTABLE) $(BUILD_DIR)/sd_card/ 43 | 44 | # Building kernel 45 | $(BUILD_DIR)/vadd_accel.xo: ./src/vadd.cpp 46 | mkdir -p $(BUILD_DIR) 47 | -@$(RM) $@ 48 | @echo 'Building Target: $@' 49 | $(XOCC) $(CLFLAGS) -c -k vadd_accel --messageDb $(subst .xo,.mdb,$@) -I'$( or make all PLATFORM= 36 | ``` 37 | where the *PLATFORM* variable accepts one board. 38 | 39 | ## 4. DESIGN FILE HIERARCHY 40 | Application code is located in the src directory. Accelerator binary files will be compiled to the build directory. A listing of all the files in this example is shown below 41 | 42 | ``` 43 | Makefile 44 | README.md 45 | description.json 46 | src/host.cpp 47 | src/vadd.cpp 48 | ``` 49 | 50 | ## 5. COMPILATION AND EXECUTION 51 | ### Compiling for Application Execution on the FPGA Board 52 | The command to compile the application for execution on the FPGA acceleration board is 53 | ``` 54 | make all 55 | ``` 56 | The default target for the makefile is to compile for hardware. Therefore, setting the TARGETS option is not required. 57 | 58 | *NOTE:* Compilation for application execution in hardware generates custom logic to implement the functionality of the kernels in an application. 59 | It is typical for hardware compile times to range from 30 minutes to a couple of hours. 60 | 61 | 62 | ## 6. SUPPORT 63 | For more information about SDSoC check the [SDSoC user Guides][] 64 | 65 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 66 | 67 | 68 | ## 7. LICENSE AND CONTRIBUTING TO THE REPOSITORY 69 | The source for this project is licensed under the [3-Clause BSD License][] 70 | 71 | To contribute to this project, follow the guidelines in the [Repository Contribution README][] 72 | 73 | ## 8. ACKNOWLEDGEMENTS 74 | This example is written by developers at 75 | - [Xilinx, Inc.](http://www.xilinx.com) 76 | 77 | 78 | [3-Clause BSD License]: ../../../LICENSE.txt 79 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 80 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 81 | [Repository Contribution README]: ../../../CONTRIBUTING.md 82 | -------------------------------------------------------------------------------- /ocl/getting_started/multiple_interfaces_ocl/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Multiple Interfaces (CL)", 3 | "overview": [ 4 | "This is a simple example of vector addition. The purpose of this example is to demonstrate on how to use multiple interfaces and as a result allow C-kernel to access both interfaces simultaneous." 5 | ], 6 | "os": [ 7 | "Linux" 8 | ], 9 | "libs": [ 10 | "xcl2" 11 | ], 12 | "runtime": [ 13 | "OpenCL" 14 | ], 15 | "board": ["zcu102", "zcu104", "zcu106"], 16 | "containers" : [ 17 | { 18 | "name" : "vadd_accel", 19 | "accelerators": [ 20 | { 21 | "name": "vadd_accel", 22 | "location": "src/vadd.cpp" 23 | } 24 | ] 25 | } 26 | ], 27 | "contributors" : [ 28 | { 29 | "group" : "Xilinx, Inc.", 30 | "url" : "http://www.xilinx.com" 31 | } 32 | ], 33 | "revision" : [ 34 | { 35 | "date" : "JUL2017", 36 | "version" : "1.0", 37 | "description" : "Initial revision" 38 | } 39 | ] 40 | } 41 | -------------------------------------------------------------------------------- /ocl/getting_started/multiple_interfaces_ocl/src/vadd.cpp: -------------------------------------------------------------------------------- 1 | /********** 2 | Copyright (c) 2018, Xilinx, Inc. 3 | All rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without modification, 6 | are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, 9 | this list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its contributors 16 | may be used to endorse or promote products derived from this software 17 | without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | **********/ 29 | 30 | extern "C"{ 31 | void vadd_accel( 32 | int* a, 33 | int* b, 34 | int* c, 35 | const int length) { 36 | 37 | //TRIPCOUNT identifier 38 | const unsigned int c_size = length; 39 | 40 | // Using Separate interface bundle gmem0 and gmem1 for both argument 41 | // a and b, same interface bundle gmem0 is used for a and c since both 42 | // read and write can happen simultaneously. It will allow user to 43 | // create two separate interfaces and as a result allow kernel to 44 | // access both interfaces simultaneous. 45 | #pragma HLS INTERFACE m_axi port=a offset=slave bundle=gmem0 46 | #pragma HLS INTERFACE m_axi port=b offset=slave bundle=gmem1 47 | #pragma HLS INTERFACE m_axi port=c offset=slave bundle=gmem0 48 | #pragma HLS INTERFACE s_axilite port=a bundle=control 49 | #pragma HLS INTERFACE s_axilite port=b bundle=control 50 | #pragma HLS INTERFACE s_axilite port=c bundle=control 51 | #pragma HLS INTERFACE s_axilite port=length bundle=control 52 | #pragma HLS INTERFACE s_axilite port=return bundle=control 53 | 54 | multiple_interfaces: 55 | for(int i=0; i < length; i++) { 56 | #pragma HLS PIPELINE 57 | #pragma HLS LOOP_TRIPCOUNT min=c_size max=c_size 58 | c[i] = a[i] + b[i]; 59 | } 60 | return; 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /ocl/getting_started/wide_mem_rw_ocl/Makefile: -------------------------------------------------------------------------------- 1 | REPORT := none 2 | TARGET := hw 3 | PLATFORM := zcu102 4 | BUILD_DIR := ./build/$(PLATFORM)_$(TARGET) 5 | 6 | CXX := aarch64-linux-gnu-g++ 7 | XOCC := xocc 8 | 9 | # Points to Utility Directory 10 | COMMON_REPO = ../../../ 11 | ABS_COMMON_REPO = $(shell readlink -f $(COMMON_REPO)) 12 | 13 | # Include Libraries 14 | include $(ABS_COMMON_REPO)/libs/xcl2/xcl2.mk 15 | 16 | # Host compiler global settings 17 | CXXFLAGS += -I $(XILINX_SDX)/runtime/include/1_2/ -I/$(XILINX_SDX)/Vivado_HLS/include/ -O2 -g -Wall -fmessage-length=0 -std=c++14 18 | LDFLAGS += -lxilinxopencl -lpthread -lrt -ldl -lcrypt -lstdc++ -L$(XILINX_SDX)/runtime/lib/aarch64 $(xcl2_CXXFLAGS) 19 | 20 | # Kernel compiler global settings 21 | CLFLAGS = -t hw --platform $(PLATFORM) --save-temps --clkid 0 22 | 23 | ifneq ($(REPORT), none) 24 | CLFLAGS += --report $(REPORT) 25 | endif 26 | 27 | BINARY_CONTAINERS += $(BUILD_DIR)/vadd.xclbin 28 | BINARY_CONTAINER_1_OBJS += $(BUILD_DIR)/vadd.xo 29 | ALL_KERNEL_OBJS += $(BUILD_DIR)/vadd.xo 30 | 31 | 32 | ALL_MESSAGE_FILES = $(subst .xo,.mdb,$(ALL_KERNEL_OBJS)) $(subst .xclbin,.mdb,$(BINARY_CONTAINERS)) 33 | 34 | HOST_SRCS = src/host.cpp $(xcl2_SRCS) 35 | 36 | EXECUTABLE = vadd 37 | 38 | CP = cp -rf 39 | 40 | .PHONY: all clean cleanall docs 41 | all: $(BUILD_DIR)/$(EXECUTABLE) $(BINARY_CONTAINERS) 42 | - $(CP) $(BUILD_DIR)/$(EXECUTABLE) $(BUILD_DIR)/sd_card/ 43 | 44 | # Building kernel 45 | $(BUILD_DIR)/vadd.xo: ./src/vadd.cl 46 | mkdir -p $(BUILD_DIR) 47 | -@$(RM) $@ 48 | @echo 'Building Target: $@' 49 | $(XOCC) $(CLFLAGS) -c -k vadd --messageDb $(subst .xo,.mdb,$@) -I'$( or make all PLATFORM= 40 | ``` 41 | where the *PLATFORM* variable accepts one board. 42 | 43 | ## 4. DESIGN FILE HIERARCHY 44 | Application code is located in the src directory. Accelerator binary files will be compiled to the build directory. A listing of all the files in this example is shown below 45 | 46 | ``` 47 | Makefile 48 | README.md 49 | description.json 50 | src/host.cpp 51 | src/vadd.cl 52 | ``` 53 | 54 | ## 5. COMPILATION AND EXECUTION 55 | ### Compiling for Application Execution on the FPGA Board 56 | The command to compile the application for execution on the FPGA acceleration board is 57 | ``` 58 | make all 59 | ``` 60 | The default target for the makefile is to compile for hardware. Therefore, setting the TARGETS option is not required. 61 | 62 | *NOTE:* Compilation for application execution in hardware generates custom logic to implement the functionality of the kernels in an application. 63 | It is typical for hardware compile times to range from 30 minutes to a couple of hours. 64 | 65 | 66 | ## 6. SUPPORT 67 | For more information about SDSoC check the [SDSoC user Guides][] 68 | 69 | For questions and to get help on this project or your own projects, visit the [SDSoC Forums][]. 70 | 71 | 72 | ## 7. LICENSE AND CONTRIBUTING TO THE REPOSITORY 73 | The source for this project is licensed under the [3-Clause BSD License][] 74 | 75 | To contribute to this project, follow the guidelines in the [Repository Contribution README][] 76 | 77 | ## 8. ACKNOWLEDGEMENTS 78 | This example is written by developers at 79 | - [Xilinx, Inc.](http://www.xilinx.com) 80 | 81 | 82 | [3-Clause BSD License]: ../../../LICENSE.txt 83 | [SDSoC Forums]: https://forums.xilinx.com/t5/SDSoC-Development-Environment/bd-p/sdsoc 84 | [SDSoC User Guides]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1027-sdsoc-user-guide.pdf 85 | [Repository Contribution README]: ../../../CONTRIBUTING.md 86 | -------------------------------------------------------------------------------- /ocl/getting_started/wide_mem_rw_ocl/description.json: -------------------------------------------------------------------------------- 1 | { 2 | "example": "Wide Memory Read/Write (CL)", 3 | "overview": [ 4 | "This is simple example of vector addition to demonstrate Wide Memory Access using uint4 data type. Based on input argument type, xocc compiler will figure out the memory datawidth between Global Memory and Kernel. For this example, uint4 datatype is used, so memory datawidth will be 4 x (integer bit size) = 4 x 32 = 128 bit." 5 | ], 6 | "key_concepts": [ "Kernel to DDR", "wide memory access", "burst read and write"], 7 | "keywords": ["uint4", "xcl_pipeline_loop"], 8 | "os": [ 9 | "Linux" 10 | ], 11 | "libs": [ 12 | "xcl2" 13 | ], 14 | "runtime": [ 15 | "OpenCL" 16 | ], 17 | "board": ["zcu102", "zcu104", "zcu106"], 18 | "containers" : [ 19 | { 20 | "name" : "vadd", 21 | "accelerators": [ 22 | { 23 | "name": "vadd", 24 | "location": "src/vadd.cl" 25 | } 26 | ] 27 | } 28 | ], 29 | "contributors" : [ 30 | { 31 | "group" : "Xilinx, Inc.", 32 | "url" : "http://www.xilinx.com" 33 | } 34 | ], 35 | "revision" : [ 36 | { 37 | "date" : "JUL2017", 38 | "version" : "1.0", 39 | "description" : "Initial revision" 40 | } 41 | ] 42 | } 43 | -------------------------------------------------------------------------------- /utility/check_license.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Check if all source files have the correct license 4 | 5 | LICENSE=$1 6 | TYPES="c cpp h hpp cl" 7 | 8 | LICENSE_LEN=$(cat LICENSE.txt | wc -l) 9 | 10 | echo "-------------------------------------" 11 | echo "-- CHECKING LICENSE of all $TYPES --" 12 | echo "-------------------------------------" 13 | 14 | FAIL=0 15 | 16 | check_file() { 17 | if [[ $VERBOSE == "true" ]]; then 18 | echo -n "Checking $1 ... " 19 | fi 20 | 21 | diff $LICENSE <(head -n$LICENSE_LEN $1) 2>/dev/null 1>&2 22 | if [[ $? == 0 ]]; then 23 | if [[ $VERBOSE == "true" ]]; then 24 | echo "PASS" 25 | fi 26 | else 27 | if [[ $VERBOSE == "true" ]]; then 28 | echo "FAIL" 29 | diff $LICENSE <(head -n$LICENSE_LEN $1) 30 | else 31 | echo "$1" 32 | fi 33 | (( FAIL += 1 )) 34 | fi 35 | 36 | } 37 | 38 | 39 | VCS_FILES=$(git ls-files) 40 | 41 | for f in $VCS_FILES; do 42 | for t in $TYPES; do 43 | if [[ $f == *.$t ]]; then 44 | check_file $f 45 | fi 46 | done 47 | done 48 | 49 | if [[ $FAIL != 0 ]]; then 50 | echo "ERROR: License check failed" 51 | echo "ERROR: please fix the license in these files (or add to ignored if external)" 52 | fi 53 | 54 | exit $FAIL 55 | -------------------------------------------------------------------------------- /utility/check_readme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Check if all README files are updated correctly 4 | 5 | echo "-----------------------" 6 | echo "-- CHECKING READMEs --" 7 | echo "-----------------------" 8 | 9 | FAIL=0 10 | 11 | check_file() { 12 | ignore=0 13 | 14 | for i in $IGNORE; do 15 | if [[ $1 =~ ^descirption.json ]]; then 16 | ignore=1 17 | fi 18 | done 19 | 20 | if [[ $VERBOSE == "true" ]]; then 21 | echo -n "Checking $1 ... " 22 | fi 23 | if [[ $ignore == 1 ]]; then 24 | if [[ $VERBOSE == "true" ]]; then 25 | echo "SKIP" 26 | fi 27 | else 28 | pushd . > /dev/null 29 | cd $(dirname $1) 30 | mv README.md README.md.check > /dev/null 2>&1 31 | make README.md 2>/dev/null 1>&2 32 | rc=$? 33 | diff README.md README.md.check 2>/dev/null 1>&2 34 | if [[ $rc == 0 && $? == 0 ]]; then 35 | if [[ $VERBOSE == "true" ]]; then 36 | echo "PASS" 37 | fi 38 | else 39 | if [[ $VERBOSE == "true" ]]; then 40 | echo "FAIL" 41 | diff README.md README.md.check 42 | else 43 | echo "$1" 44 | fi 45 | (( FAIL += 1 )) 46 | fi 47 | mv README.md.check README.md > /dev/null 2>&1 48 | popd >/dev/null 49 | fi 50 | } 51 | 52 | 53 | VCS_FILES=$(git ls-files) 54 | 55 | for f in $VCS_FILES; do 56 | if [[ $f == */description.json ]]; then 57 | check_file $f 58 | fi 59 | done 60 | 61 | if [[ $FAIL != 0 ]]; then 62 | echo "ERROR: Readme check failed" 63 | echo "ERROR: please fix the README.md in these files" 64 | fi 65 | 66 | exit $FAIL 67 | -------------------------------------------------------------------------------- /utility/emu_run.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | if [ -f "$PWD/_sds/init.sh" ] 3 | then 4 | rm -rf $PWD/_sds/emulation/sd_card 5 | sdsoc_emulator -no-reboot |tee emulator.log 6 | else 7 | cat > "init.sh" <> "_sds/emulation/sd_card.manifest" 13 | mv init.sh _sds 14 | sdsoc_emulator -no-reboot |tee emulator.log 15 | fi 16 | -------------------------------------------------------------------------------- /utility/license/commands.txt: -------------------------------------------------------------------------------- 1 | :1 2 | 32dd 3 | :lic 4 | :wq 5 | -------------------------------------------------------------------------------- /utility/license/lic.txt: -------------------------------------------------------------------------------- 1 | /*********** 2 | # Copyright (c) 2017, Xilinx, Inc. All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # 1. Redistributions of source code must retain the above copyright notice, 8 | # this list of conditions and the following disclaimer. 9 | # 10 | # 2. Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # 3. Neither the name of the copyright holder nor the names of its contributors 15 | # may be used to endorse or promote products derived from this software 16 | # without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 20 | # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 | # ARE DISCLAIMED. 22 | # 23 | # IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY 24 | # DIRECT, INDIRECT,INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 | # (INCLUDING, BUT NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 | # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 | # 28 | # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 | # LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 | # OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | # 32 | ************/ 33 | -------------------------------------------------------------------------------- /utility/license/source_lic.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for filename in src/*.cpp; do 3 | vim -s ../../utility/license/commands.txt "$filename" 4 | done 5 | for filename in src/*.h; do 6 | vim -s ../../utility/license/commands.txt "$filename" 7 | done 8 | -------------------------------------------------------------------------------- /utility/license/update_license_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | cp ../../utility/license/lic.txt ~/.vim/ 3 | echo "map :lic :0r ~/.vim/lic.txt" | cat - ~/.vimrc > temp && mv temp ~/.vimrc 4 | echo "map :lic :0r ~/.vim/lic.txt" | cat - ~/.exrc > temp && mv temp ~/.exrc 5 | for d in */ ; do 6 | cd $d; 7 | source ../../utility/license/source_lic.sh 8 | cd .. 9 | echo "$d" 10 | done 11 | -------------------------------------------------------------------------------- /utility/makefile_gen/update_makegen_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | ../../../utility/makefile_gen/makegen.py description.json 5 | cd .. 6 | echo "$d" 7 | done 8 | -------------------------------------------------------------------------------- /utility/readme_gen/gs_summary.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | import os, re 4 | import fnmatch 5 | import json 6 | import sys 7 | 8 | sys.path.append(".") 9 | import gs_summary_util 10 | 11 | gs_summary_util.genReadMe2(".") 12 | -------------------------------------------------------------------------------- /utility/readme_gen/update_readme_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | ../../../utility/readme_gen/readme_gen.py description.json 5 | cd .. 6 | echo "$d" 7 | done 8 | -------------------------------------------------------------------------------- /utility/test_repo/clean_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | make ultraclean 5 | cd .. 6 | echo "$d" 7 | done 8 | -------------------------------------------------------------------------------- /utility/test_repo/test_all.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | make ultraclean 5 | make check PLATFORM=zcu102 6 | make check PLATFORM=zcu102 TARGET_OS=standalone 7 | cd .. 8 | echo "$d" 9 | done 10 | -------------------------------------------------------------------------------- /utility/test_repo/test_emu.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | for d in */ ; do 3 | cd $d; 4 | make ultraclean 5 | make check PLATFORM=$1 TARGET_OS=$2 6 | cd .. 7 | echo "$d" 8 | done 9 | --------------------------------------------------------------------------------