├── Xilinx_Official_Platforms ├── xilinx_vck190_base │ ├── hw │ │ ├── .gitignore │ │ ├── data │ │ │ ├── questa_sim.tcl │ │ │ └── qor_scripts │ │ │ │ └── prohibit_select_bli_bels_for_hold.tcl │ │ ├── Makefile │ │ └── xsa_scripts │ │ │ ├── bd.tcl │ │ │ ├── project.tcl │ │ │ └── xsa.tcl │ ├── sw │ │ ├── Makefile │ │ └── prebuilt_linux │ │ │ ├── user_dts │ │ │ ├── system-conf.dtsi │ │ │ └── system-user.dtsi │ │ │ ├── bootgen.bif │ │ │ ├── dtb_gen │ │ │ ├── Makefile │ │ │ └── lopper_settings.sh │ │ │ └── Makefile │ ├── platform │ │ ├── generate_platform.tcl │ │ └── generate_platform.py │ ├── platform.mk │ └── Makefile ├── xilinx_vmk180_base │ ├── hw │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── data │ │ │ └── qor_scripts │ │ │ │ └── prohibit_select_bli_bels_for_hold.tcl │ │ ├── xsa_scripts │ │ │ ├── bd.tcl │ │ │ ├── project.tcl │ │ │ └── xsa.tcl │ │ └── README.hw │ ├── sw │ │ ├── Makefile │ │ └── prebuilt_linux │ │ │ ├── user_dts │ │ │ ├── system-conf.dtsi │ │ │ └── system-user.dtsi │ │ │ ├── bootgen.bif │ │ │ ├── dtb_gen │ │ │ ├── lopper_settings.sh │ │ │ └── Makefile │ │ │ └── Makefile │ ├── platform │ │ ├── generate_platform.tcl │ │ └── generate_platform.py │ ├── platform.mk │ ├── Makefile │ └── README.md ├── xilinx_vck190_base_dfx │ ├── hw │ │ ├── .gitignore │ │ ├── data │ │ │ ├── questa_sim.tcl │ │ │ ├── qor_scripts │ │ │ │ └── prohibit_select_bli_bels_for_hold.tcl │ │ │ └── pblock.xdc │ │ ├── Makefile │ │ ├── xsa_scripts │ │ │ ├── project.tcl │ │ │ ├── bd.tcl │ │ │ └── xsa.tcl │ │ └── README.hw │ ├── .nfs000000002540a7fb00000234 │ ├── sw │ │ ├── Makefile │ │ └── prebuilt_linux │ │ │ ├── user_dts │ │ │ ├── system-conf.dtsi │ │ │ └── system-user.dtsi │ │ │ ├── bootgen.bif │ │ │ └── Makefile │ ├── platform │ │ ├── build_platform.py │ │ └── generate_platform.py │ ├── platform.mk │ ├── Makefile │ └── README.md ├── vek385_base │ ├── hw │ │ ├── data │ │ │ └── questa_sim.tcl │ │ ├── xsa_scripts │ │ │ ├── custom_platform.tcl │ │ │ ├── bd.tcl │ │ │ ├── project.tcl │ │ │ └── xsa.tcl │ │ ├── Makefile │ │ └── README.hw │ ├── Makefile │ ├── platform │ │ └── generate_platform.py │ └── platform.mk ├── vek385_base_reva │ ├── hw │ │ ├── data │ │ │ └── questa_sim.tcl │ │ ├── xsa_scripts │ │ │ ├── custom_platform.tcl │ │ │ ├── bd.tcl │ │ │ ├── project.tcl │ │ │ └── xsa.tcl │ │ ├── Makefile │ │ └── README.hw │ ├── Makefile │ ├── platform │ │ └── generate_platform.py │ └── platform.mk ├── xilinx_kv260_base │ ├── hw │ │ ├── data │ │ │ ├── questa_sim.tcl │ │ │ └── qor_scripts │ │ │ │ └── prohibit_select_bli_bels_for_hold.tcl │ │ ├── Makefile │ │ ├── xsa_scripts │ │ │ ├── bd.tcl │ │ │ ├── project.tcl │ │ │ └── xsa.tcl │ │ └── README.hw │ ├── sw │ │ ├── Makefile │ │ └── prebuilt_linux │ │ │ ├── bootgen.bif │ │ │ ├── user_dts │ │ │ ├── system-conf.dtsi │ │ │ └── system-user.dtsi │ │ │ └── Makefile │ ├── platform │ │ └── generate_platform.py │ ├── Makefile │ ├── platform.mk │ └── README.md └── xilinx_vek280_base │ ├── hw │ ├── data │ │ ├── questa_sim.tcl │ │ └── qor_scripts │ │ │ └── prohibit_select_bli_bels_for_hold.tcl │ ├── Makefile │ ├── xsa_scripts │ │ ├── bd.tcl │ │ ├── project.tcl │ │ └── xsa.tcl │ └── README.hw │ ├── sw │ ├── Makefile │ └── prebuilt_linux │ │ ├── user_dts │ │ ├── system-conf.dtsi │ │ └── system-user.dtsi │ │ ├── bootgen.bif │ │ ├── dtb_gen │ │ ├── Makefile │ │ └── lopper_settings.sh │ │ └── Makefile │ ├── platform │ ├── generate_platform.tcl │ └── generate_platform.py │ ├── platform.mk │ └── Makefile └── changelog.md /Xilinx_Official_Platforms/xilinx_vck190_base/hw/.gitignore: -------------------------------------------------------------------------------- 1 | vck190_base 2 | vivado.* 3 | .Xil/ 4 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/.gitignore: -------------------------------------------------------------------------------- 1 | vck190_base 2 | vivado.* 3 | .Xil/ 4 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/.gitignore: -------------------------------------------------------------------------------- 1 | vck190_base 2 | vivado.* 3 | .Xil/ 4 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/.nfs000000002540a7fb00000234: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/Vitis_Embedded_Platform_Source/HEAD/Xilinx_Official_Platforms/xilinx_vck190_base_dfx/.nfs000000002540a7fb00000234 -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/data/questa_sim.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | set_property -name questa.compile.sccom.more_options -value {-suppress sccom-6168} -objects [current_fileset -simset] 7 | 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | .PHONY: all linux clean 7 | 8 | include ../platform.mk 9 | 10 | all linux: 11 | $(MAKE) -C prebuilt_linux all 12 | 13 | clean: 14 | $(MAKE) -C prebuilt_linux clean; 15 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | .PHONY: all linux clean 7 | 8 | include ../platform.mk 9 | 10 | all linux: 11 | $(MAKE) -C prebuilt_linux all 12 | 13 | clean: 14 | $(MAKE) -C prebuilt_linux clean; 15 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/sw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | .PHONY: all linux clean 8 | 9 | include ../platform.mk 10 | 11 | all linux: 12 | $(MAKE) -C prebuilt_linux all 13 | 14 | clean: 15 | $(MAKE) -C prebuilt_linux clean; 16 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | .PHONY: all linux clean 8 | 9 | include ../platform.mk 10 | 11 | all linux: 12 | $(MAKE) -C prebuilt_linux all 13 | 14 | clean: 15 | $(MAKE) -C prebuilt_linux clean; 16 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/sw/Makefile: -------------------------------------------------------------------------------- 1 | #******************************************************************************* 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #******************************************************************************* 6 | 7 | .PHONY: all linux clean 8 | 9 | include ../platform.mk 10 | 11 | all linux: 12 | $(MAKE) -C prebuilt_linux all 13 | 14 | clean: 15 | $(MAKE) -C prebuilt_linux clean; 16 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/xsa_scripts/custom_platform.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This tcl is user defined to update CED based bd as per needed by custom platform over top of CED based bd design generated by bd.tcl 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/xsa_scripts/custom_platform.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This tcl is user defined to update CED based bd as per needed by custom platform over top of CED based bd design generated by bd.tcl 8 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/user_dts/system-conf.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | / { 8 | chosen { 9 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 10 | stdout-path = "serial0:115200n8"; 11 | }; 12 | }; 13 | 14 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/sw/prebuilt_linux/user_dts/system-conf.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | / { 8 | chosen { 9 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 10 | stdout-path = "serial0:115200n8"; 11 | }; 12 | }; 13 | 14 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/user_dts/system-conf.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | / { 8 | chosen { 9 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 10 | stdout-path = "serial0:115200n8"; 11 | }; 12 | }; 13 | 14 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/user_dts/system-conf.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | / { 8 | chosen { 9 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 10 | stdout-path = "serial0:115200n8"; 11 | }; 12 | }; 13 | 14 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | include ../platform.mk 7 | 8 | TCL_SOURCE=xsa_scripts/xsa.tcl 9 | 10 | .PHONY: all xsa 11 | 12 | all xsa : $(XSA) 13 | 14 | $(XSA): $(TCL_SOURCE) 15 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) 16 | 17 | clean: 18 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe 19 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe 20 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe 20 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe 20 | ${RM} -r $(PLATFORM_DIR) 21 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe 20 | ${RM} -r $(PLATFORM_DIR) 21 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/sw/prebuilt_linux/bootgen.bif: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | the_ROM_image: 8 | { 9 | image { 10 | { type=bootimage, file= sw/build/static.pdi } 11 | } 12 | image { 13 | id = 0x1c000000, name=apu_subsystem 14 | { type=raw, load=0x00001000, file= sw/build/platform/boot/system.dtb } 15 | { core=a72-0, exception_level=el-3, trustzone, file= sw/build/platform/boot/bl31.elf } 16 | { core=a72-0, exception_level=el-2, file= sw/build/platform/boot/u-boot.elf } 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/bootgen.bif: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | the_ROM_image: 8 | { 9 | image { 10 | { type=bootimage, file=../../sw/build/hw.pdi } 11 | } 12 | image { 13 | id = 0x1c000000, name=apu_subsystem 14 | { type=raw, load=0x00001000, file=../../sw/build/platform/boot/system.dtb } 15 | { core=a72-0, exception_level=el-3, trustzone, file=../../sw/build/platform/boot/bl31.elf } 16 | { core=a72-0, exception_level=el-2, file=../../sw/build/platform/boot/u-boot.elf } 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/bootgen.bif: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | the_ROM_image: 8 | { 9 | image { 10 | { type=bootimage, file=../../sw/build/hw.pdi } 11 | } 12 | image { 13 | id = 0x1c000000, name=apu_subsystem 14 | { type=raw, load=0x00001000, file=../../sw/build/platform/boot/system.dtb } 15 | { core=a72-0, exception_level=el-3, trustzone, file=../../sw/build/platform/boot/bl31.elf } 16 | { core=a72-0, exception_level=el-2, file=../../sw/build/platform/boot/u-boot.elf } 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | #for both flat (hw.xsa) and segmented (hw_segmented.xsa) xsa 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) "dynamic_reload" 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe *.xsa XilinxCEDStore 20 | ${RM} -r $(PLATFORM_DIR) 21 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/bootgen.bif: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | the_ROM_image: 8 | { 9 | image { 10 | { type=bootimage, file=../../sw/build/hw.pdi } 11 | } 12 | image { 13 | id = 0x1c000000, name=apu_subsystem 14 | { type=raw, load=0x00001000, file=../../sw/build/platform/boot/system.dtb } 15 | { core=a72-0, exception_level=el-3, trustzone, file=../../sw/build/platform/boot/bl31.elf } 16 | { core=a72-0, exception_level=el-2, file=../../sw/build/platform/boot/linux/u-boot.elf } 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include ../platform.mk 8 | 9 | TCL_SOURCE=xsa_scripts/xsa.tcl 10 | 11 | .PHONY: all xsa 12 | 13 | all xsa : $(XSA) 14 | #for both flat (hw.xsa) and segmented (hw_segmented.xsa) xsa 15 | $(XSA): $(TCL_SOURCE) 16 | $(VIVADO) -mode batch -notrace -source $(TCL_SOURCE) -tclargs $(PLATFORM_NAME) $(VER) $(PRE_SYNTH) "dynamic_reload" 17 | 18 | clean: 19 | $(RM) -r vivado* build .Xil *dynamic* *.log *.xpe *.xsa XilinxCEDStore 20 | ${RM} -r $(PLATFORM_DIR) 21 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/data/qor_scripts/prohibit_select_bli_bels_for_hold.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | foreach BLI_tile [get_tiles -filter TILE_TYPE=~BLI_?RAM_?OCF_T?_TILE] { 7 | foreach BLI_bel [get_bels -of $BLI_tile] { 8 | if {[get_site_pins -quiet -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_site_pins -quiet -of [get_bel_pins -quiet */D -of $BLI_bel]]]]]] -filter NAME=~*/?_T*] != ""} { 9 | set_property PROHIBIT TRUE $BLI_bel 10 | } 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/hw/data/qor_scripts/prohibit_select_bli_bels_for_hold.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | foreach BLI_tile [get_tiles -filter TILE_TYPE=~BLI_?RAM_?OCF_T?_TILE] { 7 | foreach BLI_bel [get_bels -of $BLI_tile] { 8 | if {[get_site_pins -quiet -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_site_pins -quiet -of [get_bel_pins -quiet */D -of $BLI_bel]]]]]] -filter NAME=~*/?_T*] != ""} { 9 | set_property PROHIBIT TRUE $BLI_bel 10 | } 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/data/qor_scripts/prohibit_select_bli_bels_for_hold.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | foreach BLI_tile [get_tiles -filter TILE_TYPE=~BLI_?RAM_?OCF_T?_TILE] { 7 | foreach BLI_bel [get_bels -of $BLI_tile] { 8 | if {[get_site_pins -quiet -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_site_pins -quiet -of [get_bel_pins -quiet */D -of $BLI_bel]]]]]] -filter NAME=~*/?_T*] != ""} { 9 | set_property PROHIBIT TRUE $BLI_bel 10 | } 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/data/qor_scripts/prohibit_select_bli_bels_for_hold.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | foreach BLI_tile [get_tiles -filter TILE_TYPE=~BLI_?RAM_?OCF_T?_TILE] { 8 | foreach BLI_bel [get_bels -of $BLI_tile] { 9 | if {[get_site_pins -quiet -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_site_pins -quiet -of [get_bel_pins -quiet */D -of $BLI_bel]]]]]] -filter NAME=~*/?_T*] != ""} { 10 | set_property PROHIBIT TRUE $BLI_bel 11 | } 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/sw/prebuilt_linux/bootgen.bif: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | the_ROM_image: 8 | { 9 | [bootloader, destination_cpu=a53-0] ../../sw/build/platform/boot/zynqmp_fsbl.elf 10 | [pmufw_image] ../../sw/build/platform/boot/pmufw.elf 11 | [destination_device=pl] ../../sw/build/hw.bit 12 | [destination_cpu=a53-0, exception_level=el-3, trustzone] ../../sw/build/platform/boot/bl31.elf 13 | [destination_cpu=a53-0, load=0x00100000] ../../sw/build/platform/boot/system.dtb 14 | [destination_cpu=a53-0, exception_level=el-2] ../../sw/build/platform/boot/u-boot.elf 15 | } 16 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/data/qor_scripts/prohibit_select_bli_bels_for_hold.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | foreach BLI_tile [get_tiles -filter TILE_TYPE=~BLI_?RAM_?OCF_T?_TILE] { 8 | foreach BLI_bel [get_bels -of $BLI_tile] { 9 | if {[get_site_pins -quiet -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_nodes -quiet -uphill -of [get_site_pins -quiet -of [get_bel_pins -quiet */D -of $BLI_bel]]]]]] -filter NAME=~*/?_T*] != ""} { 10 | set_property PROHIBIT TRUE $BLI_bel 11 | } 12 | } 13 | } 14 | #Set the clibrated dskew clock to off 15 | #set_property GCLK_DESKEW Off [get_nets -of [get_pins -of [get_cells -hier -filter PRIMITIVE_TYPE=~CLOCK.BUFFER.*] -filter DIRECTION==OUT]] 16 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/dtb_gen/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | 8 | SHELL := /bin/bash 9 | XSA ?= ../../../hw/build/hw.xsa 10 | SDT_OUT ?= sdt_out 11 | USER_DTSI ?= ../user_dts/system-user.dtsi 12 | 13 | #all: get_sources gen_sdt gen_dtb 14 | all: gen_sdt gen_dtb 15 | 16 | gen_sdt: 17 | $(RM) -rf $(SDT_OUT) 18 | $(info "DTB generation started using stdgen+lopper") 19 | sdtgen -eval "sdtgen set_dt_param -dir $(SDT_OUT) -xsa $(XSA) -board_dts versal-vek280-revb -zocl enable -include_dts $(USER_DTSI); sdtgen generate_sdt" 20 | 21 | gen_dtb: 22 | $(RM) -rf system.dtb 23 | lopper -f --enhanced -O . -i lop-a72-imux.dts $(SDT_OUT)/system-top.dts system.dtb -- gen_domain_dts psv_cortexa72_0 linux_dt 24 | clean: 25 | $(RM) -r *.dtb 26 | $(RM) -r *.pp 27 | $(RM) -r sdt_out 28 | $(RM) -r $(SDT_OUT) 29 | $(RM) -r lopper 30 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | # Instatiate CED design with configurable properties 15 | 16 | instantiate_example_design -template xilinx.com:design:versal_comn_platform:2.0 -design vitis_design -options { Design_type.VALUE Extensible Include_AIE.VALUE true} 17 | 18 | validate_bd_design 19 | save_bd_design 20 | 21 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 22 | 23 | update_compile_order -fileset sim_1 24 | update_compile_order -fileset sources_1 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | # Instatiate CED design with configurable properties 15 | 16 | instantiate_example_design -template xilinx.com:design:versal_comn_platform:2.0 -design vitis_design -options { Design_type.VALUE Extensible Include_AIE.VALUE true} 17 | 18 | validate_bd_design 19 | save_bd_design 20 | 21 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 22 | 23 | update_compile_order -fileset sim_1 24 | update_compile_order -fileset sources_1 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | set_property board_part xilinx.com:vek280:part0:* [current_project] 15 | 16 | instantiate_example_design -template xilinx.com:design:ext_platform:1.0 -design vitis_design -options { Clock_Options.VALUE {clk_out1 625.000 0 true clk_out2 100 1 false } Include_AIE.VALUE true Include_BDC.VALUE false IRQS.VALUE 63} 17 | 18 | validate_bd_design 19 | save_bd_design 20 | 21 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 22 | 23 | update_compile_order -fileset sim_1 24 | update_compile_order -fileset sources_1 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/sw/prebuilt_linux/user_dts/system-conf.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | / { 8 | chosen { 9 | bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=1536M"; 10 | stdout-path = "serial0:115200n8"; 11 | }; 12 | }; 13 | 14 | &gem3 { 15 | local-mac-address = [00 0a 35 00 22 01]; 16 | }; 17 | 18 | &qspi { 19 | #address-cells = <1>; 20 | #size-cells = <0>; 21 | flash0: flash@0 { 22 | spi-tx-bus-width=<1>; 23 | spi-rx-bus-width=<4>; 24 | spi-max-frequency = <108000000>; 25 | /delete-node/ partition@0; 26 | /delete-node/ partition@100000; 27 | /delete-node/ partition@600000; 28 | /delete-node/ partition@620000; 29 | partition@0 { 30 | label = "boot"; 31 | reg = <0x00000000 0x01e00000>; 32 | }; 33 | partition@1 { 34 | label = "bootenv"; 35 | reg = <0x01e00000 0x00040000>; 36 | }; 37 | partition@2 { 38 | label = "kernel"; 39 | reg = <0x01e40000 0x02400000>; 40 | }; 41 | }; 42 | }; 43 | 44 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | set_property board_part xilinx.com:vck190:part0:* [current_project] 15 | 16 | # Instatiate CED design with configurable properties 17 | instantiate_example_design -template xilinx.com:design:ext_platform:1.0 -design vitis_design -options { Clock_Options.VALUE {clk_out1 625.000 0 true clk_out2 100 1 false} Include_AIE.VALUE true Include_BDC.VALUE false IRQS.VALUE 63} 18 | 19 | validate_bd_design 20 | save_bd_design 21 | 22 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 23 | 24 | update_compile_order -fileset sim_1 25 | update_compile_order -fileset sources_1 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/user_dts/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | /* 8 | * /include/ "system-conf.dtsi" 9 | * Adding directly contents of system-conf file until CR-1139794 is fixed 10 | */ 11 | / { 12 | chosen { 13 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 14 | stdout-path = "serial0:115200n8"; 15 | }; 16 | }; 17 | 18 | / { 19 | chosen { 20 | stdout-path = "serial0:115200"; 21 | }; 22 | 23 | reserved-memory { 24 | #address-cells = <2>; 25 | #size-cells = <2>; 26 | ranges; 27 | pl_ddr: buffer@0 { 28 | no-map; 29 | reg = <0x08 0x00 0x00 0x80000000>; 30 | }; 31 | lpddr_memory: buffer@1 { 32 | no-map; 33 | reg = <0x500 0x0 0x2 0x0>; 34 | }; 35 | }; 36 | }; 37 | 38 | 39 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/user_dts/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | /* 8 | * /include/ "system-conf.dtsi" 9 | * Adding directly contents of system-conf file until CR-1139794 is fixed 10 | */ 11 | / { 12 | chosen { 13 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 14 | stdout-path = "serial0:115200n8"; 15 | }; 16 | }; 17 | 18 | / { 19 | chosen { 20 | stdout-path = "serial0:115200"; 21 | }; 22 | 23 | reserved-memory { 24 | #address-cells = <2>; 25 | #size-cells = <2>; 26 | ranges; 27 | pl_ddr: buffer@0 { 28 | no-map; 29 | reg = <0x08 0x00 0x01 0x80000000>; 30 | }; 31 | lpddr_memory: buffer@1 { 32 | no-map; 33 | reg = <0x500 0x0 0x2 0x0>; 34 | }; 35 | }; 36 | }; 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/dtb_gen/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | 8 | SHELL := /bin/bash 9 | XSA ?= ../../../hw/build/hw.xsa 10 | SDT_OUT ?= sdt_out 11 | USER_DTSI ?= ../user_dts/system-user.dtsi 12 | 13 | all: gen_sdt gen_dtb 14 | 15 | gen_sdt: 16 | $(RM) -rf $(SDT_OUT) 17 | $(info "DTB generation started using stdgen+lopper") 18 | sdtgen -eval "sdtgen set_dt_param -dir $(SDT_OUT) -xsa $(XSA) -board_dts versal-vck190-rev1.1 -zocl enable -include_dts $(USER_DTSI); sdtgen generate_sdt" 19 | 20 | gen_dtb: 21 | $(RM) -rf system.dtb 22 | #source lopper_settings.sh; \ 23 | #export LOPPER_DTC_FLAGS="-b 0 -@"; \ 24 | #lopper -f --enhanced -O . -i ./lopper/lopper/lops/lop-a72-imux.dts $(SDT_OUT)/system-top.dts system.dtb -- gen_domain_dts psv_cortexa72_0 linux_dt 25 | #use lopper from TA 26 | 27 | lopper -f --enhanced -O . -i lop-a72-imux.dts $(SDT_OUT)/system-top.dts system.dtb -- gen_domain_dts psv_cortexa72_0 linux_dt 28 | 29 | clean: 30 | $(RM) -r *.dtb 31 | $(RM) -r *.pp 32 | $(RM) -r sdt_out 33 | $(RM) -r $(SDT_OUT) 34 | $(RM) -r lopper 35 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | set_property board_part xilinx.com:vmk180:part0:* [current_project] 15 | 16 | instantiate_example_design -template xilinx.com:design:ext_platform:1.0 -design vitis_design -options { Clock_Options.VALUE {clk_out1 100.000 0 false clk_out2 156.250 1 false clk_out3 312.500 2 true clk_out4 78.125 3 false clk_out5 200.000 4 false clk_out6 400.000 5 false clk_out7 625.000 6 false} Include_AIE.VALUE false Include_BDC.VALUE false IRQS.VALUE 63} 17 | 18 | validate_bd_design 19 | save_bd_design 20 | 21 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 22 | 23 | update_compile_order -fileset sim_1 24 | update_compile_order -fileset sources_1 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | set_property board_part xilinx.com:kv260_som:part0:* [current_project] 15 | 16 | # Instatiate CED design with configurable properties 17 | 18 | instantiate_example_design -template xilinx.com:design:MPSoC_ext_platform:1.0 -design MPSoC_ext_platform -options { Clock_Options.VALUE {clk_out1 150.000 0 true clk_out2 300.000 1 false clk_out3 75.000 2 false clk_out4 100.000 3 false clk_out5 200.000 4 false clk_out6 400.000 5 false clk_out7 600.000 6 false} Include_DDR.VALUE false} 19 | 20 | validate_bd_design 21 | save_bd_design 22 | 23 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 24 | 25 | update_compile_order -fileset sim_1 26 | update_compile_order -fileset sources_1 27 | 28 | 29 | 30 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/platform/generate_platform.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ## parsing options 7 | set options [dict create {*}$argv] 8 | 9 | set xsa_path [dict get $options xsa_path] 10 | set platform_name [dict get $options platform_name] 11 | set emu_xsa_path [dict get $options emu_xsa_path] 12 | set platform_out [dict get $options platform_out] 13 | set boot_dir_path [dict get $options boot_dir_path] 14 | set img_dir_path [dict get $options img_dir_path] 15 | 16 | set plat_arg [list] 17 | if {$xsa_path ne "" && [file exists $xsa_path] } { 18 | lappend plat_arg -hw 19 | lappend plat_arg $xsa_path 20 | } 21 | if {$emu_xsa_path ne "" && [file exists $emu_xsa_path] } { 22 | lappend plat_arg -hw_emu 23 | lappend plat_arg $emu_xsa_path 24 | } 25 | 26 | platform create -name $platform_name -desc " A base platform targeting VMK180 .This board includes 8GB of DDR4 UDIMM, 8GB LPDDR4 component, 1968 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vmk180.html" {*}$plat_arg -out $platform_out -no-boot-bsp 27 | 28 | domain create -name xrt -proc psv_cortexa72 -os linux -sd-dir $img_dir_path 29 | domain config -boot $boot_dir_path 30 | domain config -generate-bif 31 | 32 | domain config -qemu-data $boot_dir_path 33 | 34 | platform generate 35 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/dtb_gen/lopper_settings.sh: -------------------------------------------------------------------------------- 1 | export XILINX_VITIS=/proj/xbuilds/2025.1_daily_latest/installs/lin64/Vitis/2025.1 2 | 3 | export PYTHON_VER="python-3.8.3" 4 | export CMAKE_VER="cmake-3.24.2" 5 | 6 | export XBUILDS_CMAKE_PATH=${XILINX_VITIS}/tps/lnx64/${CMAKE_VER} 7 | export XBUILDS_PYTHON_PATH=${XILINX_VITIS}/tps/lnx64/${PYTHON_VER} 8 | 9 | # LD_LIBRARY_PATH is needed to add the linker libraries (e.g. libffi) to the path 10 | export LD_LIBRARY_PATH=${XBUILDS_PYTHON_PATH}/lib:${XBUILDS_CMAKE_PATH}/libs/Ubuntu:${LD_LIBRARY_PATH} 11 | export LD_LIBRARY_PATH=${XILINX_VITIS}/lib/lnx64.o/Ubuntu/20:$LD_LIBRARY_PATH 12 | 13 | # Source Paths of different toolchains, python, cmake and lopper binary 14 | export PATH=${XILINX_VITIS}/bin:${XILINX_VITIS}/gnu/microblaze/lin/bin:${XILINX_VITIS}/gnu/arm/lin/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-none-eabi/bin:${XILINX_VITIS}/gnu/aarch64/lin/aarch64-none/bin:${XILINX_VITIS}/gnu/armr5/lin/gcc-arm-none-eabi/bin:${XBUILDS_PYTHON_PATH}/bin:${XBUILDS_CMAKE_PATH}/bin:$PATH 15 | 16 | # VALIDATE_ARGS flag is needed to enable the validation of inputs. Set this flag to "" when 17 | # using the GUI flow. 18 | export VALIDATE_ARGS="True" 19 | # OSF Flag is needed to be enabled for Open Source Flow. 20 | export OSF="False" 21 | 22 | # Below is a fallback mechanism to set an esw repo when no user repo is set 23 | # export ESW_REPO="${XILINX_VITIS}/data/embeddedsw-sdt" 24 | 25 | # LOPPER_DTC_FLAGS is needed to generate device tree with symbols in it. 26 | export LOPPER_DTC_FLAGS="-b 0 -@" 27 | 28 | source ${XILINX_VITIS}/tps/lnx64/lopper-1.1.0/env/bin/activate 29 | 30 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/dtb_gen/lopper_settings.sh: -------------------------------------------------------------------------------- 1 | export XILINX_VITIS=/proj/xbuilds/2025.2_daily_latest/installs/lin64/Vitis/2025.2 2 | 3 | export PYTHON_VER="python-3.8.3" 4 | export CMAKE_VER="cmake-3.24.2" 5 | 6 | export XBUILDS_CMAKE_PATH=${XILINX_VITIS}/tps/lnx64/${CMAKE_VER} 7 | export XBUILDS_PYTHON_PATH=${XILINX_VITIS}/tps/lnx64/${PYTHON_VER} 8 | 9 | # LD_LIBRARY_PATH is needed to add the linker libraries (e.g. libffi) to the path 10 | export LD_LIBRARY_PATH=${XBUILDS_PYTHON_PATH}/lib:${XBUILDS_CMAKE_PATH}/libs/Ubuntu:${LD_LIBRARY_PATH} 11 | export LD_LIBRARY_PATH=${XILINX_VITIS}/lib/lnx64.o/Ubuntu/20:$LD_LIBRARY_PATH 12 | 13 | # Source Paths of different toolchains, python, cmake and lopper binary 14 | export PATH=${XILINX_VITIS}/bin:${XILINX_VITIS}/gnu/microblaze/lin/bin:${XILINX_VITIS}/gnu/arm/lin/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-none-eabi/bin:${XILINX_VITIS}/gnu/aarch64/lin/aarch64-none/bin:${XILINX_VITIS}/gnu/armr5/lin/gcc-arm-none-eabi/bin:${XBUILDS_PYTHON_PATH}/bin:${XBUILDS_CMAKE_PATH}/bin:$PATH 15 | 16 | # VALIDATE_ARGS flag is needed to enable the validation of inputs. Set this flag to "" when 17 | # using the GUI flow. 18 | export VALIDATE_ARGS="True" 19 | # OSF Flag is needed to be enabled for Open Source Flow. 20 | export OSF="False" 21 | 22 | # Below is a fallback mechanism to set an esw repo when no user repo is set 23 | # export ESW_REPO="${XILINX_VITIS}/data/embeddedsw-sdt" 24 | 25 | # LOPPER_DTC_FLAGS is needed to generate device tree with symbols in it. 26 | export LOPPER_DTC_FLAGS="-b 0 -@" 27 | 28 | source ${XILINX_VITIS}/tps/lnx64/lopper-1.1.0/env/bin/activate 29 | 30 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/dtb_gen/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | 8 | SHELL := /bin/bash 9 | VER_MAIN ?= 2025 10 | VER_MIN ?= 1 11 | VERSION1 ?= $(VER_MAIN).$(VER_MIN) 12 | TOOLS ?= /proj/xbuilds/$(VERSION1)_daily_latest/installs/lin64/Vitis/$(VERSION1)/ 13 | XSA ?= ../../../hw/build/hw.xsa 14 | SDT_OUT ?= sdt_out 15 | USER_DTSI ?= ../user_dts/system-user.dtsi 16 | 17 | all: get_sources gen_sdt gen_dtb 18 | 19 | get_sources: 20 | if [ ! -d "./lopper" ];then \ 21 | git clone https://github.com/devicetree-org/lopper; \ 22 | cd lopper && git checkout v0.$(VER_MAIN).x; \ 23 | fi 24 | 25 | 26 | gen_sdt: 27 | $(RM) -rf $(SDT_OUT) 28 | $(info "DTB generation started using stdgen+lopper") 29 | sdtgen -eval "sdtgen set_dt_param -dir $(SDT_OUT) -xsa $(XSA) -board_dts versal-vmk180-rev1.1 -zocl enable -include_dts $(USER_DTSI); sdtgen generate_sdt" 30 | 31 | gen_dtb: 32 | $(RM) -rf system.dtb 33 | #source lopper_settings.sh; \ 34 | #export LOPPER_DTC_FLAGS="-b 0 -@"; \ 35 | #lopper -f --enhanced -O . -i ./lopper/lopper/lops/lop-a72-imux.dts $(SDT_OUT)/system-top.dts system.dtb -- gen_domain_dts psv_cortexa72_0 linux_dt 36 | lopper -f --enhanced -O . -i lop-a72-imux.dts $(SDT_OUT)/system-top.dts system.dtb -- gen_domain_dts psv_cortexa72_0 linux_dt 37 | 38 | 39 | clean: 40 | $(RM) -r *.dtb 41 | $(RM) -r *.pp 42 | $(RM) -r sdt_out 43 | $(RM) -r $(SDT_OUT) 44 | $(RM) -r lopper 45 | 46 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: xilinx_vck190_base 8 | 9 | # 10 | # Though there are limitations about the generated script, 11 | # the main purpose of this utility is to make learning 12 | # IP Integrator Tcl commands easier. 13 | ################################################################ 14 | 15 | 16 | # If there is no project opened, this script will create a 17 | # project, but make sure you do not have an existing project 18 | # <./xilinx_vck190_base/xilinx_vck190_base.xpr> in the current working folder. 19 | set list_projs [get_projects -quiet] 20 | if { $list_projs eq "" } { 21 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 22 | set projName "my_project" 23 | set my_board [get_board_parts xilinx.com:vck190:part0:* -latest_file_version] 24 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 25 | set_property board_part $my_board [current_project] 26 | } 27 | 28 | 29 | #get Platform Name 30 | set PLATFORM_NAME [lindex $argv 0] 31 | set VER [lindex $argv 1] 32 | 33 | # CHANGE DESIGN NAME HERE 34 | variable design_name 35 | set design_name vitis_design 36 | create_bd_design $design_name 37 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | ################################################################ 8 | # This is a generated script based on design: xilinx_vek280_base 9 | 10 | # 11 | # Though there are limitations about the generated script, 12 | # the main purpose of this utility is to make learning 13 | # IP Integrator Tcl commands easier. 14 | ################################################################ 15 | 16 | 17 | # If there is no project opened, this script will create a 18 | # project, but make sure you do not have an existing project 19 | # <./xilinx_vek280_base/xilinx_vek280_base.xpr> in the current working folder. 20 | set list_projs [get_projects -quiet] 21 | if { $list_projs eq "" } { 22 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 23 | set projName "my_project" 24 | set my_board [get_board_parts xilinx.com:vek280:part0:* -latest_file_version] 25 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 26 | set_property board_part $my_board [current_project] 27 | } 28 | 29 | #get Platform Name 30 | set PLATFORM_NAME [lindex $argv 0] 31 | set VER [lindex $argv 1] 32 | 33 | # CHANGE DESIGN NAME HERE 34 | variable design_name 35 | set design_name vitis_design 36 | create_bd_design $design_name 37 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: xilinx_kv260_base 8 | 9 | # 10 | # Though there are limitations about the generated script, 11 | # the main purpose of this utility is to make learning 12 | # IP Integrator Tcl commands easier. 13 | ################################################################ 14 | 15 | 16 | # If there is no project opened, this script will create a 17 | # project, but make sure you do not have an existing project 18 | # <./xilinx_kv260_base/xilinx_kv260_base.xpr> in the current working folder. 19 | set list_projs [get_projects -quiet] 20 | if { $list_projs eq "" } { 21 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 22 | set projName "my_project" 23 | set my_board [get_board_parts xilinx.com:kv260_som:part0:* -latest_file_version] 24 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 25 | set_property board_part $my_board [current_project] 26 | } 27 | 28 | 29 | #get Platform Name 30 | set PLATFORM_NAME [lindex $argv 0] 31 | set VER [lindex $argv 1] 32 | 33 | # CHANGE DESIGN NAME HERE 34 | variable design_name 35 | set design_name MPSoC_ext_platform 36 | create_bd_design $design_name 37 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vek385_base 8 | 9 | # 10 | # Though there are limitations about the generated script, 11 | # the main purpose of this utility is to make learning 12 | # IP Integrator Tcl commands easier. 13 | ################################################################# 14 | 15 | # If there is no project opened, this script will create a project, but make sure you do not have an existing project 16 | # <./my_project/my_project.xpr> in the current working folder. 17 | set list_projs [get_projects -quiet] 18 | if { $list_projs eq "" } { 19 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 20 | set projName "my_project" 21 | set my_board [get_board_parts xilinx.com:vek385_1:part0:* -latest_file_version] 22 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 23 | #create_project $projName ./$projName -part xc2ve3858-ssva2112-2MP-e-S 24 | 25 | set_property board_part $my_board [current_project] 26 | } 27 | 28 | 29 | #get Platform Name 30 | set PLATFORM_NAME [lindex $argv 0] 31 | set VER [lindex $argv 1] 32 | 33 | # CHANGE DESIGN NAME HERE 34 | variable design_name 35 | set design_name vitis_design 36 | create_bd_design $design_name 37 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | ################################################################ 8 | # This is a generated script based on design: xilinx_vck190_base_dfx 9 | 10 | # 11 | # Though there are limitations about the generated script, 12 | # the main purpose of this utility is to make learning 13 | # IP Integrator Tcl commands easier. 14 | ################################################################ 15 | 16 | 17 | # If there is no project opened, this script will create a 18 | # project, but make sure you do not have an existing project 19 | # <./xilinx_vck190_base_dfx/xilinx_vck190_base_dfx.xpr> in the current working folder. 20 | set list_projs [get_projects -quiet] 21 | if { $list_projs eq "" } { 22 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 23 | set projName "my_project" 24 | set my_board [get_board_parts xilinx.com:vck190:part0:* -latest_file_version] 25 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 26 | set_property board_part $my_board [current_project] 27 | } 28 | #get Platform Name 29 | set PLATFORM_NAME [lindex $argv 0] 30 | set VER [lindex $argv 1] 31 | 32 | # CHANGE DESIGN NAME HERE 33 | variable design_name 34 | set design_name vitis_design 35 | create_bd_design $design_name 36 | 37 | ##emulation scripts..... 38 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 39 | ######## 40 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: xilinx_vmk180_base 8 | 9 | # 10 | # Though there are limitations about the generated script, 11 | # the main purpose of this utility is to make learning 12 | # IP Integrator Tcl commands easier. 13 | ################################################################ 14 | 15 | # If there is no project opened, this script will create a 16 | # project, but make sure you do not have an existing project 17 | # <./xilinx_vmk180_base/xilinx_vmk180_base.xpr> in the current working folder. 18 | set list_projs [get_projects -quiet] 19 | if { $list_projs eq "" } { 20 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 21 | set projName "my_project" 22 | set my_board [get_board_parts xilinx.com:vmk180:part0:* -latest_file_version] 23 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 24 | set_property board_part $my_board [current_project] 25 | } 26 | 27 | 28 | #get Platform Name 29 | set PLATFORM_NAME [lindex $argv 0] 30 | set VER [lindex $argv 1] 31 | 32 | # CHANGE DESIGN NAME HERE 33 | variable design_name 34 | set design_name vitis_design 35 | create_bd_design $design_name 36 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 37 | set_param platform.forceEnablePreSynthPDI true 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/xsa_scripts/project.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vek385_base_reva 8 | 9 | # 10 | # Though there are limitations about the generated script, 11 | # the main purpose of this utility is to make learning 12 | # IP Integrator Tcl commands easier. 13 | ################################################################# 14 | 15 | # If there is no project opened, this script will create a project, but make sure you do not have an existing project 16 | # <./my_platform/my_platform.xpr> in the current working folder. 17 | set list_projs [get_projects -quiet] 18 | if { $list_projs eq "" } { 19 | set_param board.repoPaths $::env(XILINX_VIVADO)/data/xhub/boards/XilinxBoardStore/boards/Xilinx 20 | set projName "my_project" 21 | set my_board [get_board_parts xilinx.com:vek385:part0:* -latest_file_version] 22 | create_project $projName ./$projName -part [get_property PART_NAME [get_board_parts $my_board]] 23 | #create_project $projName ./$projName -part xc2ve3858-ssva2112-2MP-e-S 24 | 25 | set_property board_part $my_board [current_project] 26 | 27 | } 28 | 29 | 30 | #get Platform Name 31 | set PLATFORM_NAME [lindex $argv 0] 32 | set VER [lindex $argv 1] 33 | 34 | # CHANGE DESIGN NAME HERE 35 | variable design_name 36 | set design_name vitis_design 37 | create_bd_design $design_name 38 | set_property PREFERRED_SIM_MODEL "tlm" [current_project] 39 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include platform.mk 8 | 9 | ############################## Help Section ############################### 10 | .PHONY: help 11 | 12 | help:: 13 | @echo 'Makefile Usage:' 14 | @echo '' 15 | @echo ' All the make commands install platform to "platform_repo/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)"' 16 | @echo '' 17 | @echo ' make all' 18 | @echo ' Command used to generate platform with pre-built software components.' 19 | @echo '' 20 | @echo ' make all PRE_SYNTH=TRUE' 21 | @echo ' Command used to generate platform with post-impl xsa and pre-built software components.' 22 | @echo ' By default, PRE_SYNTH=FALSE.' 23 | @echo '' 24 | @echo ' make platform' 25 | @echo ' Run these commands when XSA is already built in some other folder and no modifications are needed to it.' 26 | @echo ' XSA should point to $(PLATFORM_NAME).xsa file.' 27 | @echo '' 28 | @echo ' make clean ' 29 | @echo ' Command to remove all the generated files.' 30 | @echo '' 31 | 32 | .PHONY: all xsa platform clean 33 | 34 | xsa: $(XSA) 35 | 36 | $(XSA): 37 | $(MAKE) -C hw all 38 | 39 | all platform: $(XSA) 40 | 41 | @echo "INFO: Creating Platform $(PLATFORM_NAME)" 42 | vitis -s $(PLATFORM_SW_SRC)/generate_platform.py --platform_name $(PLATFORM_NAME) --xsa_path $(XSA) --emu_xsa_path $(HW_EMU_XSA) --platform_out $(PLATFORM_DIR) 43 | 44 | @echo "INFO: Checking created platforms:" && find . -name "*.xpfm" 45 | echo "Platform created:" && \ 46 | find . -name "*.xpfm" 47 | 48 | clean: 49 | $(MAKE) -C hw clean 50 | ${RM} -r $(PLATFORM_DIR) 51 | 52 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include platform.mk 8 | 9 | ############################## Help Section ############################### 10 | .PHONY: help 11 | 12 | help:: 13 | @echo 'Makefile Usage:' 14 | @echo '' 15 | @echo ' All the make commands install platform to "platform_repo/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)"' 16 | @echo '' 17 | @echo ' make all' 18 | @echo ' Command used to generate platform with pre-built software components.' 19 | @echo '' 20 | @echo ' make all PRE_SYNTH=TRUE' 21 | @echo ' Command used to generate platform with post-impl xsa and pre-built software components.' 22 | @echo ' By default, PRE_SYNTH=FALSE.' 23 | @echo '' 24 | @echo ' make platform' 25 | @echo ' Run these commands when XSA is already built in some other folder and no modifications are needed to it.' 26 | @echo ' XSA should point to $(PLATFORM_NAME).xsa file.' 27 | @echo '' 28 | @echo ' make clean ' 29 | @echo ' Command to remove all the generated files.' 30 | @echo '' 31 | 32 | .PHONY: all xsa linux platform clean 33 | 34 | xsa: $(XSA) 35 | 36 | $(XSA): 37 | $(MAKE) -C hw all 38 | 39 | 40 | all platform: $(XSA) 41 | 42 | @echo "INFO: Creating Platform $(PLATFORM_NAME)" 43 | vitis -s $(PLATFORM_SW_SRC)/generate_platform.py --platform_name $(PLATFORM_NAME) --xsa_path $(XSA) --emu_xsa_path $(HW_EMU_XSA) --platform_out $(PLATFORM_DIR) 44 | 45 | @echo "INFO: Checking created platforms:" && find . -name "*.xpfm" 46 | echo "Platform created:" && \ 47 | find . -name "*.xpfm" 48 | 49 | 50 | clean: 51 | $(MAKE) -C hw clean 52 | ${RM} -r $(PLATFORM_DIR) 53 | 54 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/platform/generate_platform.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | # parsing options 8 | set options [dict create {*}$argv] 9 | 10 | set xsa_path [dict get $options xsa_path] 11 | set platform_name [dict get $options platform_name] 12 | set emu_xsa_path [dict get $options emu_xsa_path] 13 | set platform_out [dict get $options platform_out] 14 | set boot_dir_path [dict get $options boot_dir_path] 15 | set img_dir_path [dict get $options img_dir_path] 16 | 17 | set plat_arg [list] 18 | if {$xsa_path ne "" && [file exists $xsa_path]} { 19 | lappend plat_arg -hw 20 | lappend plat_arg $xsa_path 21 | } 22 | if {$emu_xsa_path ne "" && [file exists $emu_xsa_path]} { 23 | lappend plat_arg -hw_emu 24 | lappend plat_arg $emu_xsa_path 25 | } 26 | 27 | platform create -name $platform_name -desc " A base platform targeting VEK280 which is the first Versal AI Edge series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. This board includes 12GB LPDDR4 component, 304 AI engines, 1312 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vek280.html" {*}$plat_arg -out $platform_out -no-boot-bsp 28 | 29 | domain create -name aiengine -os aie_runtime -proc {ai_engine} 30 | domain config -qemu-data $boot_dir_path 31 | domain create -name xrt -proc psv_cortexa72 -os linux -sd-dir $img_dir_path 32 | domain config -boot $boot_dir_path 33 | domain config -generate-bif 34 | 35 | domain config -qemu-data $boot_dir_path 36 | 37 | platform generate 38 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/platform/generate_platform.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | # parsing options 7 | set options [dict create {*}$argv] 8 | 9 | set xsa_path [dict get $options xsa_path] 10 | set platform_name [dict get $options platform_name] 11 | set emu_xsa_path [dict get $options emu_xsa_path] 12 | set platform_out [dict get $options platform_out] 13 | set boot_dir_path [dict get $options boot_dir_path] 14 | set img_dir_path [dict get $options img_dir_path] 15 | 16 | set plat_arg [list] 17 | if {$xsa_path ne "" && [file exists $xsa_path]} { 18 | lappend plat_arg -hw 19 | lappend plat_arg $xsa_path 20 | } 21 | if {$emu_xsa_path ne "" && [file exists $emu_xsa_path]} { 22 | lappend plat_arg -hw_emu 23 | lappend plat_arg $emu_xsa_path 24 | } 25 | 26 | platform create -name $platform_name -desc " A base platform targeting VCK190 which is the first Versal AI Core series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. This board includes 8GB of DDR4 UDIMM, 8GB LPDDR4 component, 400 AI engines, 1968 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vck190.html" {*}$plat_arg -out $platform_out -no-boot-bsp 27 | 28 | domain create -name aiengine -os aie_runtime -proc {ai_engine} 29 | domain config -qemu-data $boot_dir_path 30 | domain create -name xrt -proc psv_cortexa72 -os linux -sd-dir $img_dir_path 31 | domain config -boot $boot_dir_path 32 | domain config -generate-bif 33 | 34 | domain config -qemu-data $boot_dir_path 35 | 36 | platform generate 37 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/dtb_gen/lopper_settings.sh: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | export XILINX_VITIS=/proj/xbuilds/2025.1_daily_latest/installs/lin64/Vitis/2025.1 7 | 8 | export PYTHON_VER="python-3.8.3" 9 | export CMAKE_VER="cmake-3.24.2" 10 | 11 | export XBUILDS_CMAKE_PATH=${XILINX_VITIS}/tps/lnx64/${CMAKE_VER} 12 | export XBUILDS_PYTHON_PATH=${XILINX_VITIS}/tps/lnx64/${PYTHON_VER} 13 | 14 | # LD_LIBRARY_PATH is needed to add the linker libraries (e.g. libffi) to the path 15 | export LD_LIBRARY_PATH=${XBUILDS_PYTHON_PATH}/lib:${XBUILDS_CMAKE_PATH}/libs/Ubuntu:${LD_LIBRARY_PATH} 16 | export LD_LIBRARY_PATH=${XILINX_VITIS}/lib/lnx64.o/Ubuntu/20:$LD_LIBRARY_PATH 17 | 18 | # Source Paths of different toolchains, python, cmake and lopper binary 19 | export PATH=${XILINX_VITIS}/bin:${XILINX_VITIS}/gnu/microblaze/lin/bin:${XILINX_VITIS}/gnu/arm/lin/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:${XILINX_VITIS}/gnu/aarch32/lin/gcc-arm-none-eabi/bin:${XILINX_VITIS}/gnu/aarch64/lin/aarch64-none/bin:${XILINX_VITIS}/gnu/armr5/lin/gcc-arm-none-eabi/bin:${XBUILDS_PYTHON_PATH}/bin:${XBUILDS_CMAKE_PATH}/bin:$PATH 20 | 21 | # VALIDATE_ARGS flag is needed to enable the validation of inputs. Set this flag to "" when 22 | # using the GUI flow. 23 | export VALIDATE_ARGS="True" 24 | # OSF Flag is needed to be enabled for Open Source Flow. 25 | export OSF="False" 26 | 27 | # Below is a fallback mechanism to set an esw repo when no user repo is set 28 | # export ESW_REPO="${XILINX_VITIS}/data/embeddedsw-sdt" 29 | 30 | # LOPPER_DTC_FLAGS is needed to generate device tree with symbols in it. 31 | export LOPPER_DTC_FLAGS="-b 0 -@" 32 | 33 | source ${XILINX_VITIS}/tps/lnx64/lopper-1.1.0/env/bin/activate 34 | 35 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | CWD = $(shell readlink -f .) 7 | TOP_DIR = $(CWD)/../../ 8 | include $(TOP_DIR)/platform.mk 9 | 10 | SYSTEM_USER_DTSI = $(CWD)/user_dts/system-user.dtsi 11 | #SYSTEM_CONF_DTS = $(CWD)/user_dts/system-conf.dtsi 12 | PDI_FILE = $(SW_DIR)/hw.pdi 13 | DTB_PATH = $(CWD)/dtb_gen 14 | 15 | 16 | .PHONY: check-vitis check-prebuilt all sw_comp dtb bootimage clean 17 | 18 | $(XSA): 19 | $(MAKE) -C $(TOP_DIR) xsa 20 | 21 | dtb: $(DTB_FILE) 22 | 23 | $(DTB_FILE): check-vitis $(XSA) 24 | $(info "Generating SW Artifacts...") 25 | @if [ ! -d $(BOOT_DIR) ]; then mkdir -p $(BOOT_DIR); fi 26 | $(info "DTB generation started using stdgen+lopper") 27 | 28 | $(MAKE) -C dtb_gen all 29 | 30 | @if [ ! -f $(DTB_PATH)/system.dtb ]; then echo -e "ERROR: Device tree generation failed\n"; exit 1; fi 31 | cp $(DTB_PATH)/system.dtb $(DTB_FILE) -v 32 | 33 | sw_comp: $(SW_FILES) 34 | 35 | $(SW_FILES): $(DTB_FILE) 36 | mkdir -p $(IMAGE_DIR) 37 | cp -f $(PREBUILT_LINUX_PATH)/boot.scr ${IMAGE_DIR}/boot.scr 38 | $(foreach BOOT_FILE,$(BOOT_FILES),cp -f $(PREBUILT_LINUX_PATH)/$(BOOT_FILE) $(BOOT_DIR) ;) 39 | 40 | all: check-vitis check-prebuilt $(SW_FILES) 41 | 42 | $(PDI_FILE): $(XSA) 43 | mkdir -p $(SW_DIR) 44 | cp -f $(XSA) $(SW_DIR)/system.xsa 45 | @echo "openhw $(SW_DIR)/system.xsa" >> $(SW_DIR)/extract 46 | $(XSCT) $(SW_DIR)/extract 47 | 48 | bootimage: $(BOOT_IMAGE) 49 | 50 | $(BOOT_IMAGE): $(PDI_FILE) $(SW_FILES) 51 | $(info "BOOT image for platforms") 52 | $(BOOTGEN) -arch versal -image $(CWD)/bootgen.bif -o $(BOOT_IMAGE) -w; 53 | 54 | clean: 55 | ${RM} -r $(SW_DIR) 56 | ${RM} -r $(PLATFORM_DIR) 57 | $(MAKE) -C dtb_gen clean ; 58 | 59 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/sw/prebuilt_linux/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #******************************************************************************* 6 | 7 | CWD = $(shell readlink -f .) 8 | TOP_DIR = $(CWD)/../../ 9 | include $(TOP_DIR)/platform.mk 10 | 11 | SYSTEM_USER_DTSI = $(CWD)/user_dts/system-user.dtsi 12 | #SYSTEM_CONF_DTS = $(CWD)/user_dts/system-conf.dtsi 13 | PDI_FILE = $(SW_DIR)/hw.pdi 14 | DTB_PATH = $(CWD)/dtb_gen 15 | 16 | .PHONY: check-vitis check-prebuilt all sw_comp dtb bootimage clean 17 | 18 | $(XSA): 19 | $(MAKE) -C $(TOP_DIR) xsa 20 | 21 | dtb: $(DTB_FILE) 22 | 23 | $(DTB_FILE): check-vitis $(XSA) 24 | $(info "Generating SW Artifacts...") 25 | @if [ ! -d $(BOOT_DIR) ]; then mkdir -p $(BOOT_DIR); fi 26 | $(info "DTB generation started using stdgen+lopper") 27 | 28 | $(MAKE) -C dtb_gen all 29 | 30 | @if [ ! -f $(DTB_PATH)/system.dtb ]; then echo -e "ERROR: Device tree generation failed\n"; exit 1; fi 31 | cp $(DTB_PATH)/system.dtb $(DTB_FILE) -v 32 | 33 | sw_comp: $(SW_FILES) 34 | 35 | $(SW_FILES): $(DTB_FILE) 36 | mkdir -p $(IMAGE_DIR) 37 | cp -f $(PREBUILT_LINUX_PATH)/boot.scr ${IMAGE_DIR}/boot.scr 38 | $(foreach BOOT_FILE,$(BOOT_FILES),cp -f $(PREBUILT_LINUX_PATH)/$(BOOT_FILE) $(BOOT_DIR) ;) 39 | 40 | all: check-vitis check-prebuilt $(SW_FILES) 41 | 42 | $(PDI_FILE): $(XSA) 43 | mkdir -p $(SW_DIR) 44 | cp -f $(XSA) $(SW_DIR)/system.xsa 45 | @echo "openhw $(SW_DIR)/system.xsa" >> $(SW_DIR)/extract 46 | $(XSCT) $(SW_DIR)/extract 47 | 48 | bootimage: $(BOOT_IMAGE) 49 | 50 | $(BOOT_IMAGE): $(PDI_FILE) $(SW_FILES) 51 | $(info "BOOT image for platforms") 52 | $(BOOTGEN) -arch versal -image $(CWD)/bootgen.bif -o $(BOOT_IMAGE) -w; 53 | 54 | clean: 55 | ${RM} -r $(SW_DIR) 56 | ${RM} -r $(PLATFORM_DIR) 57 | $(MAKE) -C dtb_gen clean ; 58 | 59 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/sw/prebuilt_linux/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | CWD = $(shell readlink -f .) 7 | TOP_DIR = $(CWD)/../../ 8 | include $(TOP_DIR)/platform.mk 9 | 10 | SYSTEM_USER_DTSI = $(CWD)/user_dts/system-user.dtsi 11 | #SYSTEM_CONF_DTS = $(CWD)/user_dts/system-conf.dtsi 12 | PDI_FILE = $(SW_DIR)/hw.pdi 13 | DTB_PATH = $(CWD)/dtb_gen 14 | 15 | 16 | .PHONY: check-vitis check-prebuilt all sw_comp dtb bootimage clean 17 | 18 | $(XSA): 19 | $(MAKE) -C $(TOP_DIR) xsa 20 | 21 | dtb: $(DTB_FILE) 22 | 23 | $(DTB_FILE): check-vitis $(XSA) 24 | $(info "Generating SW Artifacts...") 25 | @if [ ! -d $(BOOT_DIR) ]; then mkdir -p $(BOOT_DIR); fi 26 | $(info "DTB generation started using stdgen+lopper") 27 | 28 | $(MAKE) -C dtb_gen all 29 | 30 | @if [ ! -f $(DTB_PATH)/system.dtb ]; then echo -e "ERROR: Device tree generation failed\n"; exit 1; fi 31 | cp $(DTB_PATH)/system.dtb $(DTB_FILE) -v 32 | 33 | sw_comp: $(SW_FILES) 34 | 35 | $(SW_FILES): $(DTB_FILE) 36 | mkdir -p $(IMAGE_DIR) 37 | cp -f $(PREBUILT_LINUX_PATH)/boot.scr ${IMAGE_DIR}/boot.scr 38 | $(foreach BOOT_FILE,$(BOOT_FILES),cp -f $(PREBUILT_LINUX_PATH)/$(BOOT_FILE) $(BOOT_DIR) ;) 39 | 40 | all: check-vitis check-prebuilt $(SW_FILES) 41 | 42 | $(PDI_FILE): $(XSA) 43 | mkdir -p $(SW_DIR) 44 | cp -f $(XSA) $(SW_DIR)/system.xsa 45 | @echo "openhw $(SW_DIR)/system.xsa" >> $(SW_DIR)/extract 46 | $(XSCT) $(SW_DIR)/extract 47 | 48 | bootimage: $(BOOT_IMAGE) 49 | 50 | $(BOOT_IMAGE): $(PDI_FILE) $(SW_FILES) 51 | $(info "BOOT image for platforms") 52 | $(BOOTGEN) -arch versal -image $(CWD)/bootgen.bif -o $(BOOT_IMAGE) -w; 53 | 54 | clean: 55 | ${RM} -r $(SW_DIR) 56 | ${RM} -r $(PLATFORM_DIR) 57 | $(MAKE) -C dtb_gen clean ; 58 | 59 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/platform/build_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--static_xsa_path", type=str, dest="static_xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--rp_xsa_path", type=str, dest="rp_xsa_path") 19 | parser.add_argument("--user_dtsi", type=str, dest="user_dtsi") 20 | parser.add_argument("--boot_image", type=str, dest="boot_image") 21 | 22 | #parser.add_argument("--dtb", type=str, dest="dtb") 23 | 24 | args = parser.parse_args() 25 | static_xsa_path=args.static_xsa_path 26 | platform_name=args.platform_name 27 | emu_xsa_path=args.emu_xsa_path 28 | platform_out=args.platform_out 29 | boot_dir_path=args.boot_dir_path 30 | img_dir_path=args.img_dir_path 31 | #dtb=args.dtb 32 | rp_xsa_path=args.rp_xsa_path 33 | user_dtsi=args.user_dtsi 34 | boot_image=args.boot_image 35 | print('args',args) 36 | client = vitis.create_client() 37 | #client.update_workspace(path=os.getcwd()/test) 38 | 39 | 40 | client.update_workspace(path=platform_out) 41 | 42 | platform = client.get_component(name = platform_name) 43 | 44 | #update boot_dir_path with boot.bin path 45 | domain = platform.get_domain(name="xrt") 46 | status = domain.update_hw_boot_bin(boot_image) 47 | 48 | status = platform.build() 49 | 50 | #domain.report() 51 | #platform.report() 52 | 53 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/sw/prebuilt_linux/user_dts/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | /* 8 | * /include/ "system-conf.dtsi" 9 | * Adding directly contents of system-conf file until CR-1139794 is fixed 10 | */ 11 | / { 12 | chosen { 13 | bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=1536M"; 14 | stdout-path = "serial0:115200n8"; 15 | }; 16 | }; 17 | 18 | &gem3 { 19 | local-mac-address = [00 0a 35 00 22 01]; 20 | }; 21 | 22 | &qspi { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | flash0: flash@0 { 26 | spi-tx-bus-width=<1>; 27 | spi-rx-bus-width=<4>; 28 | spi-max-frequency = <108000000>; 29 | /delete-node/ partition@0; 30 | /delete-node/ partition@100000; 31 | /delete-node/ partition@600000; 32 | /delete-node/ partition@620000; 33 | partition@0 { 34 | label = "boot"; 35 | reg = <0x00000000 0x01e00000>; 36 | }; 37 | partition@1 { 38 | label = "bootenv"; 39 | reg = <0x01e00000 0x00040000>; 40 | }; 41 | partition@2 { 42 | label = "kernel"; 43 | reg = <0x01e40000 0x02400000>; 44 | }; 45 | }; 46 | }; 47 | 48 | /{ 49 | reserved-memory { 50 | #address-cells = <2>; 51 | #size-cells = <2>; 52 | ranges; 53 | pl_ddr: buffer@0 { 54 | no-map; 55 | reg = <0x08 0x00 0x00 0x80000000>; 56 | }; 57 | }; 58 | }; 59 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/xsa_scripts/bd.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | ################################################################ 7 | # This is a generated script based on design: vitis_design 8 | # 9 | # Though there are limitations about the generated script, 10 | # the main purpose of this utility is to make learning 11 | # IP Integrator Tcl commands easier. 12 | ################################################################ 13 | 14 | set_property board_part xilinx.com:vck190:part0:* [current_project] 15 | 16 | # Instatiate CED design with configurable properties 17 | 18 | proc assign_bdc_apertures {rm_bd top_bd bdc_cell} { 19 | set old_bd [current_bd_design] 20 | open_bd_design ${rm_bd} 21 | set aps [dict create] 22 | foreach x [get_bd_intf_ports] { 23 | set apertures [get_property -quiet APERTURES ${x}] 24 | if {[string length ${apertures}] > 0} { 25 | dict set aps [::bd::utils::get_short_name ${x}] ${apertures} 26 | } 27 | } 28 | open_bd_design ${top_bd} 29 | foreach {intf apertures} ${aps} { 30 | set_property APERTURES ${apertures} [get_bd_intf_pins [get_bd_cells ${bdc_cell}]/${intf}] 31 | } 32 | current_bd_design ${old_bd} 33 | } 34 | 35 | instantiate_example_design -template xilinx.com:design:versal_dfx_platform:1.0 -design vitis_design -options { Clock_Options.VALUE {clk_out1 104.167 0 false clk_out2 156.250 1 false clk_out3 312.500 2 true clk_out4 78.125 3 false clk_out5 208.330 4 false clk_out6 416.670 5 false clk_out7 625.000 6 false} Include_AIE.VALUE true Include_DDR.VALUE true IRQS.VALUE 63 Include_LPDDR.VALUE true} 36 | 37 | assign_bdc_apertures [get_files VitisRegion.bd] [get_files vitis_design.bd] VitisRegion 38 | 39 | validate_bd_design 40 | save_bd_design 41 | 42 | #write_bd_tcl -f ../xsa_scripts/reference_bd.tcl 43 | 44 | update_compile_order -fileset sim_1 45 | update_compile_order -fileset sources_1 46 | 47 | -------------------------------------------------------------------------------- /changelog.md: -------------------------------------------------------------------------------- 1 | # Change Logs 2 | ## 2025.2 3 | - New Platform: `vek385_base`. The new platforms naming convention is updated. Please refer to [UG1701](https://docs.amd.com/r/en-US/ug1701-vitis-accelerated-embedded/Pre-built-Base-Platforms) for details. 4 | - `xilinx_vck190_base_dfx` platform source CED updated to use MBUFGCE to generate clock for AI Engine, aligning with other Versal base platforms. 5 | - Remove `xilinx_zcu104_base` from Xilinx_Official_Platforms after the [deprecation announcement](https://adaptivesupport.amd.com/s/article/000037352?language=en_US). `xilinx_kv260_base` will continue to be supported. 6 | 7 | ## 2025.1 8 | - `xilinx_vck190_base_dfx` platform updated to use CED to generate hardware platform source. 9 | 10 | ## 2024.2 11 | - VCK190 base platform updated to use Vivado CED (Customizable Example Design) to generate hardware platform source code. TCL based source code is also provided under HW folder for reference. 12 | - Removed BDC platforms 13 | - All Versal platforms updated the dtb generation scripts to make use of newly introduced system device tree flow. 14 | 15 | ## 2023.1 16 | 17 | - Removed PetaLinux directory from source code. 18 | 19 | ## 2022.2 20 | 21 | - Removed Petalinux based sw components generation from platform creation. 22 | 23 | ## 2022.1 24 | 25 | - VCK190 Base Platform clock frequencies updated to match the fraction of AI Engine clock frequency. 26 | - Added VCK190 Base DFX Platform 27 | - All platforms updated the dtb generation scripts to make use of newly introduced `createdts` command. 28 | - Updated top makefile to use pre-built common image by default. 29 | 30 | ## 2021.1 31 | 32 | - VCK190 Base Platform enables ECC on DDR and LPDDR; constraints become concise. 33 | - MPSoC base platforms increased CMA size to 1536M. All Vitis-AI models can run with this CMA size. 34 | - Embedded platform creation flow gets simplified: Device Tree Generator can automatically generate a ZOCL node; XSCT can generate BIF files. Base platform source files are reduced. 35 | 36 |

Copyright © 2020–2025 Advanced Micro Devices, Inc.

37 | 38 |

Terms and Conditions

-------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/sw/prebuilt_linux/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | CWD = $(shell readlink -f .) 7 | TOP_DIR = $(CWD)/../../ 8 | include $(TOP_DIR)/platform.mk 9 | 10 | SYSTEM_USER_DTSI = $(CWD)/user_dts/system-user.dtsi 11 | #SYSTEM_CONF_DTS = $(CWD)/user_dts/system-conf.dtsi 12 | PDI_FILE = $(SW_DIR)/hw.pdi 13 | DTB_PATH = $(CWD)/dtb_gen 14 | 15 | 16 | .PHONY: check-vitis check-prebuilt all sw_comp dtb bootimage clean 17 | 18 | $(XSA): 19 | $(MAKE) -C $(TOP_DIR) xsa 20 | 21 | dtb: $(DTB_FILE) 22 | 23 | $(DTB_FILE): check-vitis $(XSA) 24 | $(info "Generating SW Artifacts...") 25 | @if [ ! -d $(BOOT_DIR) ]; then mkdir -p $(BOOT_DIR); fi 26 | # $(info "DTB generation started using stdgen+lopper") 27 | # 28 | # $(MAKE) -C dtb_gen all 29 | # 30 | # @if [ ! -f $(DTB_PATH)/system.dtb ]; then echo -e "ERROR: Device tree generation failed\n"; exit 1; fi 31 | # cp $(DTB_PATH)/system.dtb $(DTB_FILE) -v 32 | 33 | sw_comp: $(SW_FILES) 34 | 35 | $(SW_FILES): $(DTB_FILE) 36 | mkdir -p $(IMAGE_DIR) 37 | cp -f $(PREBUILT_LINUX_PATH)/boot.scr ${IMAGE_DIR}/boot.scr 38 | $(foreach BOOT_FILE,$(BOOT_FILES),cp -f $(PREBUILT_LINUX_PATH)/$(BOOT_FILE) $(BOOT_DIR) ;) 39 | # cp -f $(CWD)/bootgen.bif $(BOOT_DIR) 40 | # cp -f $(PLATFORM_DIR)/xilinx_vck190_base_dfx_202520_1/hw/linux_dt/system.dtb $(BOOT_DIR) 41 | 42 | all: check-vitis check-prebuilt $(SW_FILES) $(PDI_FILE) 43 | 44 | $(PDI_FILE): $(XSA) 45 | mkdir -p $(SW_DIR) 46 | cp -f $(STATIC_XSA) $(SW_DIR)/system.xsa 47 | $(info "Extracting pdi from xsa") 48 | # @echo "openhw $(SW_DIR)/system.xsa" >> $(SW_DIR)/extract 49 | # hsi open_hw_design $(SW_DIR)/system.xsa 50 | xsdb -eval "hsi open_hw_design $(SW_DIR)/system.xsa" 51 | # $(XILINX_VITIS)/bin/xsdb $(SW_DIR)/extract 52 | 53 | #bootimage: $(BOOT_IMAGE) 54 | 55 | #$(BOOT_IMAGE): $(PDI_FILE) $(SW_FILES) 56 | # $(info "BOOT image for platforms") 57 | # $(BOOTGEN) -arch versal -image $(CWD)/bootgen.bif -o $(BOOT_IMAGE) -w; 58 | 59 | clean: 60 | ${RM} -r $(SW_DIR) 61 | ${RM} -r $(PLATFORM_DIR) 62 | # $(MAKE) -C dtb_gen clean ; 63 | 64 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/sw/prebuilt_linux/user_dts/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | /* 7 | * /include/ "system-conf.dtsi" 8 | * Adding directly contents of system-conf file until CR-1139794 is fixed 9 | */ 10 | / { 11 | chosen { 12 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 13 | stdout-path = "serial0:115200n8"; 14 | }; 15 | }; 16 | 17 | / { 18 | chosen { 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | reserved-memory { 23 | #address-cells = <2>; 24 | #size-cells = <2>; 25 | ranges; 26 | pl_ddr: buffer@0 { 27 | no-map; 28 | reg = <0x08 0x00 0x01 0x80000000>; 29 | }; 30 | lpddr_memory: buffer@1 { 31 | no-map; 32 | reg = <0x500 0x0 0x2 0x0>; 33 | }; 34 | }; 35 | }; 36 | 37 | 38 | &amba_pl { ai_engine@20000000000 { 39 | #address-cells = <0x02>; 40 | #size-cells = <0x02>; 41 | clock-names = "aclk0"; 42 | clocks = <0x13>; 43 | compatible = "xlnx,ai-engine-2.0\0xlnx,ai-engine-v2.0"; 44 | power-domains = <0x8d 0x18800000>; 45 | ranges; 46 | reg = <0x200 0x00 0x01 0x00>; 47 | xlnx,aie-gen = [01]; 48 | xlnx,core-rows = [01 08]; 49 | xlnx,mem-rows = [00 00]; 50 | xlnx,shim-rows = [00 01]; 51 | 52 | aie_aperture@20000000000 { 53 | #address-cells = <0x02>; 54 | #size-cells = <0x02>; 55 | interrupt-names = "interrupt1\0interrupt2\0interrupt3"; 56 | interrupt-parent = <0x05>; 57 | interrupts = <0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04>; 58 | power-domains = <0x8d 0x18800000>; 59 | reg = <0x200 0x00 0x01 0x00>; 60 | xlnx,columns = <0x00 0x32>; 61 | xlnx,node-id = <0x18800000>; 62 | }; 63 | }; 64 | aie_core_ref_clk_0 { 65 | #clock-cells = <0x00>; 66 | clock-frequency = <0x4a817c80>; 67 | compatible = "fixed-clock"; 68 | phandle = <0x13>; 69 | }; 70 | }; 71 | 72 | 73 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/sw/prebuilt_linux/user_dts/system-user.dtsi: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | /* 7 | * /include/ "system-conf.dtsi" 8 | * Adding directly contents of system-conf file until CR-1139794 is fixed 9 | */ 10 | / { 11 | chosen { 12 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait cma=512M"; 13 | stdout-path = "serial0:115200n8"; 14 | }; 15 | }; 16 | 17 | / { 18 | chosen { 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | reserved-memory { 23 | #address-cells = <2>; 24 | #size-cells = <2>; 25 | ranges; 26 | pl_ddr: buffer@0 { 27 | no-map; 28 | reg = <0x08 0x00 0x01 0x80000000>; 29 | }; 30 | lpddr_memory: buffer@1 { 31 | no-map; 32 | reg = <0x500 0x0 0x2 0x0>; 33 | }; 34 | }; 35 | }; 36 | 37 | &amba_pl { 38 | /delete-node/ interrupt-controller@a4040000; 39 | /delete-node/ interrupt-controller@a4050000; 40 | }; 41 | 42 | &amba { 43 | axi_intc_cascaded_1: interrupt-controller@a4040000 { 44 | #interrupt-cells = <2>; 45 | clock-names = "s_axi_aclk"; 46 | clocks = <&misc_clk_0>; 47 | compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; 48 | interrupt-controller ; 49 | interrupt-names = "irq"; 50 | interrupt-parent = <&axi_intc_parent>; 51 | interrupts = <31 2>; 52 | reg = <0x0 0xa4040000 0x0 0x10000>; 53 | xlnx,kind-of-intr = <0x00>; 54 | xlnx,num-intr-inputs = <0x20>; 55 | }; 56 | axi_intc_parent: interrupt-controller@a4050000 { 57 | #interrupt-cells = <2>; 58 | clock-names = "s_axi_aclk"; 59 | clocks = <&misc_clk_0>; 60 | compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; 61 | interrupt-controller ; 62 | interrupt-names = "irq"; 63 | interrupt-parent = <&gic_a72>; 64 | interrupts = <0 84 4>; 65 | reg = <0x0 0xa4050000 0x0 0x10000>; 66 | xlnx,kind-of-intr = <0x0>; 67 | xlnx,num-intr-inputs = <0x20>; 68 | }; 69 | }; 70 | 71 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--dtb", type=str, dest="dtb") 19 | 20 | args = parser.parse_args() 21 | xsa_path=args.xsa_path 22 | platform_name=args.platform_name 23 | emu_xsa_path=args.emu_xsa_path 24 | platform_out=args.platform_out 25 | boot_dir_path=args.boot_dir_path 26 | img_dir_path=args.img_dir_path 27 | dtb=args.dtb 28 | print('args',args) 29 | client = vitis.create_client() 30 | #client.update_workspace(path=os.getcwd()/test) 31 | 32 | client.update_workspace(path=platform_out) 33 | #client.update_workspace("/proj/xhdhdstaff3/swbhardw/platform/2025.2/sysgen_vck190_base_bdc/xilinx_vck190_base_bdc_python_cli/temp") 34 | 35 | platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, no_boot_bsp = True, emu_design = emu_xsa_path, generate_dtb = False, 36 | desc = " A base platform targeting VMK180 .This board includes 8GB of DDR4 UDIMM, 8GB LPDDR4 component, 1968 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vmk180.html" ) 37 | 38 | 39 | platform = client.get_component(name = platform_name) 40 | 41 | # linux domain only since vm180 is non-aie platforms 42 | domain = platform.add_domain(cpu = "psv_cortexa72",os = "linux",name = "xrt",display_name = "xrt") 43 | domain.set_sd_dir(path = img_dir_path) 44 | domain = platform.get_domain(name="xrt") 45 | status = domain.set_boot_dir(path=boot_dir_path) 46 | status = domain.generate_bif() 47 | 48 | status = domain.set_dtb(path=dtb) # used to bypass sdtgen from generate platform 49 | 50 | status = platform.build() 51 | 52 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #******************************************************************************* 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #******************************************************************************* 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--dtb", type=str, dest="dtb") 19 | 20 | args = parser.parse_args() 21 | xsa_path=args.xsa_path 22 | platform_name=args.platform_name 23 | emu_xsa_path=args.emu_xsa_path 24 | platform_out=args.platform_out 25 | boot_dir_path=args.boot_dir_path 26 | img_dir_path=args.img_dir_path 27 | dtb=args.dtb 28 | print('args',args) 29 | 30 | 31 | 32 | client = vitis.create_client() 33 | client.update_workspace(path=platform_out) 34 | 35 | advanced_options = client.create_advanced_options_dict(dt_overlay="1",dt_zocl="1") 36 | 37 | platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, emu_design = emu_xsa_path, no_boot_bsp = True, generate_dtb = False, 38 | desc = " The VEK385 Vitis base platform is designed for the VEK385 evaluation kit, enabling developers to create high-performance applications using AI and DSP engines that deliver over 10× the scalar compute performance of current server-class CPUs. This platform features a powerful heterogeneous architecture with 8 Arm® Cortex®-A78 application processors, 10 Arm® Cortex®-R5 real-time processors, and 20GB of high-speed LPDDR5X memory. It offers a robust foundation for building advanced solutions in AI, signal processing, and compute-intensive domains using AMD Versal™ adaptive SoCs." ) 39 | 40 | 41 | platform = client.get_component(name=platform_name) 42 | 43 | #aie domain 44 | domain = platform.add_domain(cpu = "ai_engine",os = "aie_runtime",name = "aiengine",display_name = "aiengine") 45 | domain = platform.get_domain(name="aiengine") 46 | #linux domain 47 | domain = platform.add_domain(os = "linux",cpu = "cortexa78",name = "xrt",display_name = "xrt") 48 | 49 | status = platform.build() 50 | 51 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #******************************************************************************* 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #******************************************************************************* 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--dtb", type=str, dest="dtb") 19 | 20 | args = parser.parse_args() 21 | xsa_path=args.xsa_path 22 | platform_name=args.platform_name 23 | emu_xsa_path=args.emu_xsa_path 24 | platform_out=args.platform_out 25 | boot_dir_path=args.boot_dir_path 26 | img_dir_path=args.img_dir_path 27 | dtb=args.dtb 28 | print('args',args) 29 | 30 | 31 | 32 | client = vitis.create_client() 33 | client.update_workspace(path=platform_out) 34 | 35 | advanced_options = client.create_advanced_options_dict(dt_overlay="1",dt_zocl="1") 36 | 37 | platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, emu_design = emu_xsa_path, no_boot_bsp = True, generate_dtb = False, 38 | desc = " The VEK385 Vitis base platform is designed for the VEK385 evaluation kit, enabling developers to create high-performance applications using AI and DSP engines that deliver over 10× the scalar compute performance of current server-class CPUs. This platform features a powerful heterogeneous architecture with 8 Arm® Cortex®-A78 application processors, 10 Arm® Cortex®-R5 real-time processors, and 10GB of high-speed LPDDR5X memory. It offers a robust foundation for building advanced solutions in AI, signal processing, and compute-intensive domains using AMD Versal™ adaptive SoCs." ) 39 | 40 | 41 | platform = client.get_component(name=platform_name) 42 | 43 | #aie domain 44 | domain = platform.add_domain(cpu = "ai_engine",os = "aie_runtime",name = "aiengine",display_name = "aiengine") 45 | domain = platform.get_domain(name="aiengine") 46 | #linux domain 47 | domain = platform.add_domain(os = "linux",cpu = "cortexa78",name = "xrt",display_name = "xrt") 48 | 49 | status = platform.build() 50 | 51 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/README.hw: -------------------------------------------------------------------------------- 1 | ########################################################################## 2 | This is a brief document containing design specific details for : xilinx_kv260_base_202520_1 3 | This is auto-generated by Petalinux ref-design builder created @ Fri Nov 15 11:44:39 IST 2024 4 | ########################################################################## 5 | BOARD: xilinx.com:kv260_som_som240_1_connector_kv260_carrier_som240_1_connector:part0:1.4 6 | BLOCK DESIGN: MPSoC_ext_platform 7 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 8 | MODULE INSTANCE NAME IP TYPE IP VERSION IP 9 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 10 | MPSoC_ext_platform_axi_intc_0_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 11 | MPSoC_ext_platform_axi_interconnect_lpd_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 12 | MPSoC_ext_platform_axi_register_slice_0_0 axi_register_slice 2.1 xilinx.com:ip:axi_register_slice:2.1 13 | MPSoC_ext_platform_axi_vip_0_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 14 | MPSoC_ext_platform_axi_vip_1_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 15 | MPSoC_ext_platform_clk_wiz_0_0 clk_wiz 6.0 xilinx.com:ip:clk_wiz:6.0 16 | MPSoC_ext_platform_interconnect_axifull_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 17 | MPSoC_ext_platform_interconnect_axihpm0fpd_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 18 | MPSoC_ext_platform_interconnect_axilite_0 axi_interconnect 2.1 xilinx.com:ip:axi_interconnect:2.1 19 | MPSoC_ext_platform_proc_sys_reset_0_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 20 | MPSoC_ext_platform_proc_sys_reset_1_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 21 | MPSoC_ext_platform_proc_sys_reset_2_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 22 | MPSoC_ext_platform_ps_e_0 zynq_ultra_ps_e 3.5 xilinx.com:ip:zynq_ultra_ps_e:3.5 23 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | #parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | #parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | #parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | #parser.add_argument("--dtb", type=str, dest="dtb") 19 | parser.add_argument("--dtsi", type=str, dest="dtsi") 20 | 21 | args = parser.parse_args() 22 | xsa_path=args.xsa_path 23 | platform_name=args.platform_name 24 | #emu_xsa_path=args.emu_xsa_path 25 | platform_out=args.platform_out 26 | #boot_dir_path=args.boot_dir_path 27 | #img_dir_path=args.img_dir_path 28 | #dtb=args.dtb 29 | dtsi=args.dtsi 30 | print('args',args) 31 | import vitis 32 | client = vitis.create_client() 33 | client.update_workspace(path=platform_out) 34 | 35 | #platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, no_boot_bsp = True, 36 | # desc = " A base platform targeting kv260 kria SOM" ) 37 | #platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, no_boot_bsp = True, 38 | # desc = " A base platform targeting kv260 kria SOM" ) 39 | 40 | #client.set_workspace(path="test") 41 | 42 | advanced_options = client.create_advanced_options_dict(user_dtsi=dtsi,dt_overlay="1",dt_zocl="1") 43 | 44 | platform = client.create_platform_component(name = platform_name,hw_design = xsa_path, no_boot_bsp = True,generate_dtb = True, advanced_options = advanced_options,architecture = "64-bit",desc = " A base platform targeting kv260 kria SOM" ) 45 | 46 | platform = client.get_component(name = platform_name) 47 | 48 | # linux domain only since kv260 is non-aie platforms 49 | domain = platform.add_domain(cpu = "psu_cortexa53",os = "linux",name = "xrt",display_name = "xrt", dt_overlay=True ) 50 | #domain.set_sd_dir(path = img_dir_path) 51 | domain = platform.get_domain(name="xrt") 52 | #status = domain.set_boot_dir(path=boot_dir_path) 53 | status = domain.generate_bif() 54 | 55 | #status = domain.set_dtb(path=dtb) # used to bypass sdtgen from generate platform 56 | 57 | status = platform.build() 58 | 59 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--dtb", type=str, dest="dtb") 19 | 20 | args = parser.parse_args() 21 | xsa_path=args.xsa_path 22 | platform_name=args.platform_name 23 | emu_xsa_path=args.emu_xsa_path 24 | platform_out=args.platform_out 25 | boot_dir_path=args.boot_dir_path 26 | img_dir_path=args.img_dir_path 27 | dtb=args.dtb 28 | print('args',args) 29 | client = vitis.create_client() 30 | #client.update_workspace(path=os.getcwd()/test) 31 | 32 | client.update_workspace(path=platform_out) 33 | #client.update_workspace("/proj/xhdhdstaff3/swbhardw/platform/2025.2/sysgen_vck190_base_bdc/xilinx_vck190_base_bdc_python_cli/temp") 34 | 35 | platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, no_boot_bsp = True, emu_design = emu_xsa_path, generate_dtb = False, 36 | desc = " A base platform targeting VCK190 which is the first Versal AI Core series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. This board includes 8GB of DDR4 UDIMM, 8GB LPDDR4 component, 400 AI engines, 1968 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vck190.html" ) 37 | 38 | 39 | platform = client.get_component(name = platform_name) 40 | 41 | #aie domain 42 | domain = platform.add_domain(cpu = "ai_engine",os = "aie_runtime",name = "aiengine",display_name = "aiengine") 43 | domain = platform.get_domain(name="aiengine") 44 | #linux domain 45 | domain = platform.add_domain(cpu = "psv_cortexa72",os = "linux",name = "xrt",display_name = "xrt") 46 | domain.set_sd_dir(path = img_dir_path) 47 | domain = platform.get_domain(name="xrt") 48 | status = domain.set_boot_dir(path=boot_dir_path) 49 | status = domain.generate_bif() 50 | 51 | status = domain.set_dtb(path=dtb) # used to bypass sdtgen from generate platform 52 | 53 | status = platform.build() 54 | 55 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--xsa_path", type=str, dest="xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--dtb", type=str, dest="dtb") 19 | 20 | args = parser.parse_args() 21 | xsa_path=args.xsa_path 22 | platform_name=args.platform_name 23 | emu_xsa_path=args.emu_xsa_path 24 | platform_out=args.platform_out 25 | boot_dir_path=args.boot_dir_path 26 | img_dir_path=args.img_dir_path 27 | dtb=args.dtb 28 | print('args',args) 29 | client = vitis.create_client() 30 | #client.update_workspace(path=os.getcwd()/test) 31 | 32 | client.update_workspace(path=platform_out) 33 | #client.update_workspace("/proj/xhdhdstaff3/swbhardw/platform/2025.2/sysgen_vck190_base_bdc/xilinx_vck190_base_bdc_python_cli/temp") 34 | 35 | platform = client.create_platform_component(name = platform_name, hw_design = xsa_path, no_boot_bsp = True, emu_design = emu_xsa_path, generate_dtb = False, 36 | desc = " A base platform targeting VEK280 which is the first Versal AI Edge series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. This board includes 12GB LPDDR4 component, 304 AI engines, 1312 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vek280.html" ) 37 | 38 | 39 | platform = client.get_component(name = platform_name) 40 | 41 | #aie domain 42 | domain = platform.add_domain(cpu = "ai_engine",os = "aie_runtime",name = "aiengine",display_name = "aiengine") 43 | domain = platform.get_domain(name="aiengine") 44 | #linux domain 45 | domain = platform.add_domain(cpu = "psv_cortexa72",os = "linux",name = "xrt",display_name = "xrt") 46 | domain.set_sd_dir(path = img_dir_path) 47 | domain = platform.get_domain(name="xrt") 48 | status = domain.set_boot_dir(path=boot_dir_path) 49 | status = domain.generate_bif() 50 | 51 | status = domain.set_dtb(path=dtb) # used to bypass sdtgen from generate platform 52 | 53 | status = platform.build() 54 | 55 | 56 | status = platform.build() 57 | 58 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base_reva/hw/xsa_scripts/xsa.tcl: -------------------------------------------------------------------------------- 1 | file mkdir build 2 | cd build 3 | source ../xsa_scripts/project.tcl 4 | source ../xsa_scripts/bd.tcl 5 | 6 | #custom_platform.tcl to be used to update bd over top of CED based bd for custom platform flow 7 | ##For creating a non-CED based custom platform, user can comment "source ../xsa_scripts/create_bd.tcl" and update custom_platform.tcl 8 | source ../xsa_scripts/custom_platform.tcl 9 | 10 | #Generating Target 11 | generate_target all [get_files ./my_project/my_project.srcs/sources_1/bd/vitis_design/vitis_design.bd] 12 | update_compile_order -fileset sources_1 13 | update_compile_order -fileset sim_1 14 | 15 | # Ensure that your top of synthesis module is also set as top for simulation 16 | 17 | #Generate the final simulation script which will compile 18 | # the _sim_wrapper and xlnoc.bd modules also 19 | launch_simulation -scripts_only 20 | launch_simulation -step compile 21 | launch_simulation -step elaborate 22 | 23 | #Generating Emulation XSA 24 | file mkdir hw_emu 25 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 26 | set pre_synth "" 27 | if { $argc > 1} { 28 | set pre_synth [lindex $argv 2] 29 | } 30 | 31 | #Pre_synth Platform Flow 32 | if {$pre_synth} { 33 | set_property platform.platform_state "pre_synth" [current_project] 34 | write_hw_platform -hw -force -file hw.xsa 35 | 36 | } else { 37 | 38 | #Post_implememtation Platform 39 | # Synthesis Run 40 | launch_runs synth_1 -jobs 20 41 | wait_on_run synth_1 42 | 43 | set_param noc.enableNOCClockGating false 44 | 45 | #Implementation Run 46 | launch_runs impl_1 -to_step write_device_image 47 | wait_on_run impl_1 48 | 49 | open_run impl_1 50 | 51 | 52 | # Generating dynamic reload extensible XSA as default hardware platform 53 | write_hw_platform -hw -force -include_bit -file hw.xsa 54 | 55 | } 56 | 57 | #generate README.hw 58 | set board vek385 59 | 60 | set fd [open README.hw w] 61 | 62 | set board [lindex $argv 0] 63 | 64 | puts $fd "##########################################################################" 65 | puts $fd "This is a brief document containing design specific details for : ${board}" 66 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 67 | puts $fd "##########################################################################" 68 | 69 | set board_part [get_board_parts [current_board_part -quiet]] 70 | if { $board_part != ""} { 71 | puts $fd "BOARD: $board_part" 72 | } 73 | 74 | set design_name [get_property NAME [get_bd_designs]] 75 | puts $fd "BLOCK DESIGN: $design_name" 76 | 77 | set columns {%40s%30s%15s%50s} 78 | puts $fd [string repeat - 150] 79 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 80 | puts $fd [string repeat - 150] 81 | foreach ip [get_ips] { 82 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 83 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 84 | } 85 | close $fd 86 | 87 | 88 | cd .. 89 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/hw/xsa_scripts/xsa.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | file mkdir build 7 | cd build 8 | source ../xsa_scripts/project.tcl 9 | source ../xsa_scripts/bd.tcl 10 | 11 | #For Questa Simulator 12 | source ../data/questa_sim.tcl 13 | 14 | #Generating Target 15 | generate_target all [get_files ./my_project/my_project.srcs/sources_1/bd/vitis_design/vitis_design.bd] 16 | update_compile_order -fileset sources_1 17 | update_compile_order -fileset sim_1 18 | 19 | #generate_switch_network_for_noc 20 | update_compile_order -fileset sim_1 21 | 22 | #Generate the final simulation script which will compile 23 | # the _sim_wrapper and xlnoc.bd modules also 24 | launch_simulation -scripts_only 25 | launch_simulation -step compile 26 | launch_simulation -step elaborate 27 | 28 | #Generating Emulation XSA 29 | #file mkdir hw_emu 30 | #write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 31 | 32 | set pre_synth "" 33 | if { $argc > 1} { 34 | set pre_synth [lindex $argv 2] 35 | } 36 | 37 | #Pre_synth Platform Flow 38 | if {$pre_synth} { 39 | set_property platform.platform_state "pre_synth" [current_project] 40 | write_hw_platform -hw -force -file hw.xsa 41 | } else { 42 | 43 | #Post_implememtation Platform 44 | # Synthesis Run 45 | launch_runs synth_1 -jobs 20 46 | wait_on_run synth_1 47 | 48 | #Implementation Run 49 | launch_runs impl_1 -to_step write_device_image 50 | wait_on_run impl_1 51 | 52 | open_run impl_1 53 | 54 | # Generating XSA 55 | write_hw_platform -hw -force -include_bit -file hw.xsa 56 | } 57 | 58 | #generate README.hw 59 | set board vck190 60 | 61 | set fd [open README.hw w] 62 | 63 | set board [lindex $argv 0] 64 | 65 | puts $fd "##########################################################################" 66 | puts $fd "This is a brief document containing design specific details for : ${board}" 67 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 68 | puts $fd "##########################################################################" 69 | 70 | set board_part [get_board_parts [current_board_part -quiet]] 71 | if { $board_part != ""} { 72 | puts $fd "BOARD: $board_part" 73 | } 74 | 75 | set design_name [get_property NAME [get_bd_designs]] 76 | puts $fd "BLOCK DESIGN: $design_name" 77 | 78 | set columns {%40s%30s%15s%50s} 79 | puts $fd [string repeat - 150] 80 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 81 | puts $fd [string repeat - 150] 82 | foreach ip [get_ips] { 83 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 84 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 85 | } 86 | close $fd 87 | 88 | cd .. 89 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/sw/prebuilt_linux/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | CWD = $(shell readlink -f .) 8 | TOP_DIR = $(CWD)/../../ 9 | include $(TOP_DIR)/platform.mk 10 | 11 | SYSTEM_USER_DTSI = $(CWD)/user_dts/system-user.dtsi 12 | #SYSTEM_CONF_DTS = $(CWD)/user_dts/system-conf.dtsi 13 | BIT_FILE = $(SW_DIR)/hw.bit 14 | 15 | .PHONY: check-vitis check-prebuilt all sw_comp dtb bootimage clean 16 | 17 | $(XSA): 18 | $(MAKE) -C $(TOP_DIR) xsa 19 | 20 | #dtb: $(DTB_FILE) 21 | 22 | #$(DTB_FILE): check-vitis $(XSA) 23 | # $(info "Generating SW Artifacts...") 24 | # @if [ ! -d $(BOOT_DIR) ]; then mkdir -p $(BOOT_DIR); fi 25 | # @mkdir -p $(SW_DIR)/tmp 26 | # $(info "DTB generation started using XSCT") 27 | # $(info $(XSCT) -eval "createdts -hw $(XSA) -git-url https://gitenterprise.xilinx.com/Linux/device-tree-xlnx.git -git-branch master -platform $(PLATFORM) -zocl -out $(SW_DIR)/tmp -dtsi $(SYSTEM_USER_DTSI) -overlay -compile") 28 | # @$(XSCT) -eval "createdts -hw $(XSA) -git-url https://gitenterprise.xilinx.com/Linux/device-tree-xlnx.git -git-branch master -board $(BOARD) -platform $(PLATFORM) -zocl -out $(SW_DIR)/tmp -dtsi $(SYSTEM_USER_DTSI) -overlay -compile" 29 | # $(eval BSP_PATH = $(SW_DIR)/tmp/$(PLATFORM)/$(CORE)/device_tree_domain/bsp/) 30 | # dtc -@ -O dtb -o $(BSP_PATH)/pl.dtbo $(BSP_PATH)/pl.dtsi; \ 31 | cp $(BSP_PATH)/pl.dtbo $(DTBO_FILE) -v 32 | 33 | # @if [ ! -f $(BSP_PATH)/system.dtb ]; then echo -e "ERROR: Device tree generation failed\n"; exit 1; fi 34 | # cp $(BSP_PATH)/system.dtb $(DTB_FILE) -v 35 | 36 | # @rm -rf $(SW_DIR)/tmp 37 | 38 | #sw_comp: $(SW_FILES) 39 | 40 | #$(SW_FILES): $(DTB_FILE) 41 | # mkdir -p $(IMAGE_DIR) 42 | # cp -f $(PREBUILT_LINUX_PATH)/boot.scr ${IMAGE_DIR}/boot.scr 43 | # $(foreach BOOT_FILE,$(BOOT_FILES),cp -f $(PREBUILT_LINUX_PATH)/$(BOOT_FILE) $(BOOT_DIR) ;) 44 | 45 | # # Generate fsbl, pmufw elf files 46 | # $(XSCT) -nodisp -sdx $(PLATFORM_SW_SRC)/generate_platform.tcl platform_name "${PLATFORM_NAME}" \ 47 | xsa_path "${XSA}" emu_xsa_path "${HW_EMU_XSA}" platform_out "${PLATFORM_DIR}" \ 48 | boot_dir_path "${BOOT_DIR}" img_dir_path "${IMAGE_DIR}" generate_sw true 49 | # $(eval BOOT_ARTIFACTS = ${PLATFORM_DIR}/${PLATFORM_NAME}/export/${PLATFORM_NAME}/sw/${PLATFORM_NAME}/boot) 50 | # cp -rf ${BOOT_ARTIFACTS}/*.elf ${BOOT_DIR} 2>/dev/null || : 51 | # ${RM} -r ${PLATFORM_DIR} 52 | 53 | 54 | #all: check-vitis check-prebuilt $(SW_FILES) 55 | 56 | all: check-vitis check-prebuilt 57 | 58 | #$(BIT_FILE): $(XSA) 59 | # mkdir -p $(SW_DIR) 60 | # cp -f $(XSA) $(SW_DIR)/system.xsa 61 | # @echo "openhw $(SW_DIR)/system.xsa" >> $(SW_DIR)/extract 62 | # $(XSCT) $(SW_DIR)/extract 63 | 64 | #bootimage: $(BOOT_IMAGE) 65 | 66 | #$(BOOT_IMAGE): $(BIT_FILE) $(SW_FILES) 67 | # $(info "BOOT image for platforms") 68 | # $(BOOTGEN) -arch zynqmp -image $(CWD)/bootgen.bif -o $(BOOT_IMAGE) -w; 69 | 70 | clean: 71 | ${RM} -r $(SW_DIR) 72 | ${RM} -r $(PLATFORM_DIR) 73 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/platform.mk: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | .EXPORT_ALL_VARIABLES: 7 | 8 | #tools 9 | VIVADO = $(XILINX_VIVADO)/bin/vivado 10 | DTC = $(XILINX_VITIS)/bin/dtc 11 | BOOTGEN = $(XILINX_VITIS)/bin/bootgen 12 | XSCT = $(XILINX_VITIS)/bin/xsct 13 | 14 | #platform specific 15 | PLATFORM = xilinx_vek280_base 16 | CPU_ARCH = a72 17 | BOARD = versal-vek280-revb 18 | CORE = psv_cortexa72_0 19 | 20 | #versioning 21 | VERSION ?= 202520_1 22 | VER ?= 202520.1 23 | 24 | #common 25 | TOP_DIR ?= $(shell readlink -f .) 26 | 27 | #hw related 28 | XSA_DIR ?= $(TOP_DIR)/hw/build 29 | XSA ?= $(XSA_DIR)/hw.xsa 30 | RP_XSA ?= $(XSA_DIR)/rp/rp.xsa 31 | STATIC_XSA ?= $(XSA_DIR)/static.xsa 32 | HW_EMU_XSA ?= $(XSA_DIR)/hw_emu/hw_emu.xsa 33 | PRE_SYNTH ?= TRUE 34 | 35 | #sw related 36 | SW_DIR = $(TOP_DIR)/sw/build 37 | BOOT_DIR = $(SW_DIR)/platform/boot 38 | IMAGE_DIR = $(SW_DIR)/platform/image 39 | DTB_FILE = $(BOOT_DIR)/system.dtb 40 | BOOT_IMAGE = $(BOOT_DIR)/BOOT.BIN 41 | SW_FILES = $(IMAGE_DIR)/boot.scr $(BOOT_DIR)/u-boot.elf $(BOOT_DIR)/bl31.elf 42 | BOOT_FILES = u-boot.elf bl31.elf 43 | 44 | #platform related 45 | PLATFORM_NAME = $(PLATFORM)_$(VERSION) 46 | PLATFORM_SW_SRC = $(TOP_DIR)/platform 47 | PLATFORM_DIR = $(TOP_DIR)/platform_repo 48 | 49 | #flow related 50 | PREBUILT_LINUX_PATH ?= /opt/xilinx/platform/xilinx-versal-common-v2025.2 51 | ifneq ($(wildcard $(TOP_DIR)/xilinx-versal-common-v2025.2),) 52 | PREBUILT_LINUX_PATH ?= $(TOP_DIR)/xilinx-versal-common-v2025.2 53 | endif 54 | # Getting Absolute paths 55 | ifneq ("$(wildcard $(XSA))","") 56 | XSA_ABS ?= $(realpath $(XSA)) 57 | override XSA := $(realpath $(XSA_ABS)) 58 | endif 59 | ifneq ("$(wildcard $(PREBUILT_LINUX_PATH_ABS))","") 60 | PREBUILT_LINUX_PATH_ABS ?= $(realpath $(PREBUILT_LINUX_PATH)) 61 | override PREBUILT_LINUX_PATH := $(realpath $(PREBUILT_LINUX_PATH_ABS)) 62 | endif 63 | 64 | #common targets 65 | check-vitis: 66 | ifeq ($(XILINX_VITIS),) 67 | $(error ERROR: 'XILINX_VITIS' variable not set, please set correctly and rerun) 68 | endif 69 | 70 | check-prebuilt: 71 | ifeq (,$(wildcard $(PREBUILT_LINUX_PATH))) 72 | $(info ) 73 | $(info PREBUILT common images cannot be found at $(PREBUILT_LINUX_PATH)) 74 | $(info If PREBUILT common images are present in another directory, Please specify the path to images as follows :) 75 | $(info make all PREBUILT_LINUX_PATH=/path/to/boot_files/dir) 76 | $(info else) 77 | $(info Please download PREBUILT common images from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html and extract them to /opt/xilinx/platform) 78 | $(error ) 79 | else 80 | $(info Found Platform Images at $(PREBUILT_LINUX_PATH)) 81 | endif 82 | ifeq ($(PREBUILT_LINUX_PATH),) 83 | $(error ERROR: 'PREBUILT_LINUX_PATH' is not accesible, please set this flag to path containing common software) 84 | endif 85 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/vek385_base/hw/xsa_scripts/xsa.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | file mkdir build 7 | cd build 8 | source ../xsa_scripts/project.tcl 9 | source ../xsa_scripts/bd.tcl 10 | 11 | #custom_platform.tcl to be used to update bd over top of CED based bd for custom platform flow 12 | ##For creating a non-CED based custom platform, user can comment "source ../xsa_scripts/create_bd.tcl" and update custom_platform.tcl 13 | source ../xsa_scripts/custom_platform.tcl 14 | 15 | #Generating Target 16 | generate_target all [get_files ./my_project/my_project.srcs/sources_1/bd/vitis_design/vitis_design.bd] 17 | update_compile_order -fileset sources_1 18 | update_compile_order -fileset sim_1 19 | 20 | # Ensure that your top of synthesis module is also set as top for simulation 21 | 22 | #Generate the final simulation script which will compile 23 | # the _sim_wrapper and xlnoc.bd modules also 24 | launch_simulation -scripts_only 25 | launch_simulation -step compile 26 | launch_simulation -step elaborate 27 | 28 | #Generating Emulation XSA 29 | file mkdir hw_emu 30 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 31 | set pre_synth "" 32 | if { $argc > 1} { 33 | set pre_synth [lindex $argv 2] 34 | } 35 | 36 | #Pre_synth Platform Flow 37 | if {$pre_synth} { 38 | set_property platform.platform_state "pre_synth" [current_project] 39 | write_hw_platform -hw -force -file hw.xsa 40 | 41 | } else { 42 | 43 | #Post_implememtation Platform 44 | # Synthesis Run 45 | launch_runs synth_1 -jobs 20 46 | wait_on_run synth_1 47 | 48 | set_param noc.enableNOCClockGating false 49 | 50 | #Implementation Run 51 | launch_runs impl_1 -to_step write_device_image 52 | wait_on_run impl_1 53 | 54 | open_run impl_1 55 | 56 | 57 | # Generating dynamic reload extensible XSA as default hardware platform 58 | write_hw_platform -hw -force -include_bit -file hw.xsa 59 | 60 | } 61 | 62 | #generate README.hw 63 | set board vek385 64 | 65 | set fd [open README.hw w] 66 | 67 | set board [lindex $argv 0] 68 | 69 | puts $fd "##########################################################################" 70 | puts $fd "This is a brief document containing design specific details for : ${board}" 71 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 72 | puts $fd "##########################################################################" 73 | 74 | set board_part [get_board_parts [current_board_part -quiet]] 75 | if { $board_part != ""} { 76 | puts $fd "BOARD: $board_part" 77 | } 78 | 79 | set design_name [get_property NAME [get_bd_designs]] 80 | puts $fd "BLOCK DESIGN: $design_name" 81 | 82 | set columns {%40s%30s%15s%50s} 83 | puts $fd [string repeat - 150] 84 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 85 | puts $fd [string repeat - 150] 86 | foreach ip [get_ips] { 87 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 88 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 89 | } 90 | close $fd 91 | 92 | 93 | cd .. 94 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | include platform.mk 7 | 8 | ############################## Help Section ############################## 9 | .PHONY: help 10 | 11 | help:: 12 | @echo 'Makefile Usage:' 13 | @echo '' 14 | @echo ' All the make commands install platform to "platform_repo/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)"' 15 | @echo '' 16 | @echo ' make all' 17 | @echo ' Command used to generate platform with pre-built software components.' 18 | @echo '' 19 | @echo ' make all PREBUILT_LINUX_PATH=_sim_wrapper as the sim top 23 | #set_property top vitis_design_wrapper_sim_wrapper [get_filesets sim_1] 24 | #import_files -fileset sim_1 -norecurse ./my_project/my_project.srcs/sources_1/common/hdl/vitis_design_wrapper_sim_wrapper.v 25 | #update_compile_order -fileset sim_1 26 | 27 | #Generate the final simulation script which will compile 28 | # the _sim_wrapper and xlnoc.bd modules also 29 | launch_simulation -scripts_only 30 | launch_simulation -step compile 31 | launch_simulation -step elaborate 32 | 33 | #Generating Emulation XSA 34 | file mkdir hw_emu 35 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 36 | 37 | set pre_synth "" 38 | if { $argc > 1} { 39 | set pre_synth [lindex $argv 2] 40 | } 41 | 42 | #Pre_synth Platform Flow 43 | if {$pre_synth} { 44 | set_property platform.platform_state "pre_synth" [current_project] 45 | write_hw_platform -hw -force -file hw.xsa 46 | } else { 47 | 48 | #Post_implememtation Platform 49 | # Synthesis Run 50 | launch_runs synth_1 -jobs 20 51 | wait_on_run synth_1 52 | 53 | #Implementation Run 54 | launch_runs impl_1 -to_step write_device_image 55 | wait_on_run impl_1 56 | 57 | open_run impl_1 58 | 59 | # Generating XSA 60 | write_hw_platform -hw -force -include_bit -file hw.xsa 61 | } 62 | 63 | #generate README.hw 64 | set board vmk180 65 | 66 | set fd [open README.hw w] 67 | 68 | set board [lindex $argv 0] 69 | 70 | puts $fd "##########################################################################" 71 | puts $fd "This is a brief document containing design specific details for : ${board}" 72 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 73 | puts $fd "##########################################################################" 74 | 75 | set board_part [get_board_parts [current_board_part -quiet]] 76 | if { $board_part != ""} { 77 | puts $fd "BOARD: $board_part" 78 | } 79 | 80 | set design_name [get_property NAME [get_bd_designs]] 81 | puts $fd "BLOCK DESIGN: $design_name" 82 | 83 | set columns {%40s%30s%15s%50s} 84 | puts $fd [string repeat - 150] 85 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 86 | puts $fd [string repeat - 150] 87 | foreach ip [get_ips] { 88 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 89 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 90 | } 91 | close $fd 92 | 93 | cd .. 94 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/data/pblock.xdc: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | ######################################## 8 | # 9 | #This file works only with our platform. There will be need to review this xdc as per your resource requirements in static region. 10 | # Creating pblock for Vitis Region 11 | 12 | create_pblock pblock_VitisRegion 13 | add_cells_to_pblock [get_pblocks pblock_VitisRegion] [get_cells -quiet [list vitis_design_i/VitisRegion]] 14 | 15 | #Resizing the pblock as per clock regions 16 | resize_pblock [get_pblocks pblock_VitisRegion] -add {CLOCKREGION_X0Y3:CLOCKREGION_X11Y5 CLOCKREGION_X3Y2:CLOCKREGION_X9Y2 CLOCKREGION_X4Y1:CLOCKREGION_X9Y1 CLOCKREGION_X7Y0:CLOCKREGION_X8Y0} 17 | 18 | # Resizing the pblock and adding maximum resources to Vitis Region that is not required in static region 19 | resize_pblock [get_pblocks pblock_VitisRegion] -add {SLICE_X116Y0:SLICE_X147Y91 SLICE_X76Y0:SLICE_X115Y187 SLICE_X60Y140:SLICE_X75Y185 SLICE_X60Y0:SLICE_X75Y138 SLICE_X50Y0:SLICE_X59Y187 SLICE_X0Y140:SLICE_X49Y187} 20 | resize_pblock [get_pblocks pblock_VitisRegion] -add {BUFG_GT_X0Y24:BUFG_GT_X0Y47} 21 | resize_pblock [get_pblocks pblock_VitisRegion] -add {BUFG_GT_SYNC_X0Y41:BUFG_GT_SYNC_X0Y81} 22 | resize_pblock [get_pblocks pblock_VitisRegion] -add {DSP58_CPLX_X0Y46:DSP58_CPLX_X0Y93 DSP58_CPLX_X0Y0:DSP58_CPLX_X1Y45} 23 | resize_pblock [get_pblocks pblock_VitisRegion] -add {DSP_X0Y46:DSP_X1Y93 DSP_X0Y0:DSP_X3Y45} 24 | resize_pblock [get_pblocks pblock_VitisRegion] -add {GTY_QUAD_X0Y3:GTY_QUAD_X0Y3} 25 | resize_pblock [get_pblocks pblock_VitisRegion] -add {IRI_QUAD_X47Y772:IRI_QUAD_X70Y779 IRI_QUAD_X0Y772:IRI_QUAD_X36Y779 IRI_QUAD_X0Y588:IRI_QUAD_X70Y771 IRI_QUAD_X47Y584:IRI_QUAD_X70Y587 IRI_QUAD_X36Y584:IRI_QUAD_X36Y587 IRI_QUAD_X36Y396:IRI_QUAD_X70Y583 IRI_QUAD_X36Y16:IRI_QUAD_X92Y395 IRI_QUAD_X31Y4:IRI_QUAD_X91Y15 IRI_QUAD_X31Y0:IRI_QUAD_X92Y3} 26 | resize_pblock [get_pblocks pblock_VitisRegion] -add {NOC_NMU512_X0Y2:NOC_NMU512_X0Y3 NOC_NMU512_X0Y0:NOC_NMU512_X1Y1} 27 | resize_pblock [get_pblocks pblock_VitisRegion] -add {NOC_NSU512_X0Y2:NOC_NSU512_X0Y3 NOC_NSU512_X0Y0:NOC_NSU512_X1Y1} 28 | resize_pblock [get_pblocks pblock_VitisRegion] -add {RAMB18_X3Y0:RAMB18_X4Y47 RAMB18_X2Y0:RAMB18_X2Y95 RAMB18_X1Y72:RAMB18_X1Y93 RAMB18_X1Y0:RAMB18_X1Y69 RAMB18_X0Y72:RAMB18_X0Y95} 29 | resize_pblock [get_pblocks pblock_VitisRegion] -add {RAMB36_X3Y0:RAMB36_X4Y23 RAMB36_X2Y0:RAMB36_X2Y47 RAMB36_X1Y36:RAMB36_X1Y46 RAMB36_X1Y0:RAMB36_X1Y34 RAMB36_X0Y36:RAMB36_X0Y47} 30 | resize_pblock [get_pblocks pblock_VitisRegion] -add {URAM288_X2Y0:URAM288_X2Y23 URAM288_X1Y36:URAM288_X1Y46 URAM288_X1Y0:URAM288_X1Y34 URAM288_X0Y36:URAM288_X0Y47} 31 | resize_pblock [get_pblocks pblock_VitisRegion] -add {URAM_CAS_DLY_X1Y0:URAM_CAS_DLY_X2Y0 URAM_CAS_DLY_X0Y1:URAM_CAS_DLY_X0Y1} 32 | 33 | # Removing some sites from Vitis Region as they are in above clock regions but required by static region 34 | resize_pblock pblock_VitisRegion -remove [get_sites -of [get_tiles DDRMC_RIU_CORE_X90Y0]] 35 | resize_pblock pblock_VitisRegion -remove [get_sites -of_objects [get_tiles CLK_VNOC_PSS_CCA_TILE_X23Y47]] 36 | 37 | set_property SNAPPING_MODE ON [get_pblocks pblock_VitisRegion] 38 | set_property IS_SOFT FALSE [get_pblocks pblock_VitisRegion] 39 | 40 | 41 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/platform.mk: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | .EXPORT_ALL_VARIABLES: 7 | 8 | #tools 9 | VIVADO = $(XILINX_VIVADO)/bin/vivado 10 | DTC = $(XILINX_VITIS)/bin/dtc 11 | BOOTGEN = $(XILINX_VITIS)/bin/bootgen 12 | XSCT = $(XILINX_VITIS)/bin/xsct 13 | 14 | #platform specific 15 | PLATFORM = xilinx_kv260_base 16 | CPU_ARCH = a53 17 | BOARD = zynqmp-smk-k26-reva 18 | CORE = psu_cortexa53_0 19 | 20 | #versioning 21 | VERSION ?= 202520_1 22 | VER ?= 202520.1 23 | 24 | #common 25 | TOP_DIR ?= $(shell readlink -f .) 26 | 27 | #hw related 28 | XSA_DIR ?= $(TOP_DIR)/hw/build 29 | XSA ?= $(XSA_DIR)/hw.xsa 30 | RP_XSA ?= $(XSA_DIR)/rp/rp.xsa 31 | STATIC_XSA ?= $(XSA_DIR)/static.xsa 32 | HW_EMU_XSA ?= $(XSA_DIR)/hw_emu/hw_emu.xsa 33 | PRE_SYNTH ?= TRUE 34 | 35 | #sw related 36 | SW_DIR = $(TOP_DIR)/sw/build 37 | BOOT_DIR = $(SW_DIR)/platform/boot 38 | IMAGE_DIR = $(SW_DIR)/platform/image 39 | DTB_FILE = $(BOOT_DIR)/system.dtb 40 | DTBO_FILE = $(BOOT_DIR)/pl.dtbo 41 | BOOT_IMAGE = $(BOOT_DIR)/BOOT.BIN 42 | SW_FILES = $(IMAGE_DIR)/boot.scr $(BOOT_DIR)/u-boot.elf $(BOOT_DIR)/bl31.elf 43 | BOOT_FILES = u-boot.elf bl31.elf 44 | DTSI_FILES = $(TOP_DIR)/sw/prebuilt_linux/user_dts/system-user.dtsi 45 | 46 | #platform related 47 | PLATFORM_NAME = $(PLATFORM)_$(VERSION) 48 | PLATFORM_SW_SRC = $(TOP_DIR)/platform 49 | PLATFORM_DIR = $(TOP_DIR)/platform_repo 50 | 51 | #flow related 52 | PREBUILT_LINUX_PATH ?= /opt/xilinx/platform/xilinx-zynqmp-common-v2025.2 53 | ifneq ($(wildcard $(TOP_DIR)/xilinx-zynqmp-common-v2025.2),) 54 | PREBUILT_LINUX_PATH ?= $(TOP_DIR)/xilinx-zynqmp-common-v2025.2 55 | endif 56 | # Getting Absolute paths 57 | ifneq ("$(wildcard $(XSA))","") 58 | XSA_ABS ?= $(realpath $(XSA)) 59 | override XSA := $(realpath $(XSA_ABS)) 60 | endif 61 | ifneq ("$(wildcard $(HW_EMU_XSA_ABS))","") 62 | HW_EMU_XSA_ABS ?= $(realpath $(HW_EMU_XSA)) 63 | override HW_EMU_XSA := $(realpath $(HW_EMU_XSA_ABS)) 64 | endif 65 | ifneq ("$(wildcard $(PREBUILT_LINUX_PATH_ABS))","") 66 | PREBUILT_LINUX_PATH_ABS ?= $(realpath $(PREBUILT_LINUX_PATH)) 67 | override PREBUILT_LINUX_PATH := $(realpath $(PREBUILT_LINUX_PATH_ABS)) 68 | endif 69 | 70 | #common targets 71 | check-vitis: 72 | ifeq ($(XILINX_VITIS),) 73 | $(error ERROR: 'XILINX_VITIS' variable not set, please set correctly and rerun) 74 | endif 75 | 76 | check-prebuilt: 77 | ifeq (,$(wildcard $(PREBUILT_LINUX_PATH))) 78 | $(info ) 79 | $(info PREBUILT common images cannot be found at $(PREBUILT_LINUX_PATH)) 80 | $(info If PREBUILT common images are present in another directory, Please specify the path to images as follows :) 81 | $(info make all PREBUILT_LINUX_PATH=/path/to/boot_files/dir) 82 | $(info else) 83 | $(info Please download PREBUILT common images from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html and extract them to /opt/xilinx/platform) 84 | $(error ) 85 | else 86 | $(info Found Platform Images at $(PREBUILT_LINUX_PATH)) 87 | endif 88 | ifeq ($(PREBUILT_LINUX_PATH),) 89 | $(error ERROR: 'PREBUILT_LINUX_PATH' is not accesible, please set this flag to path containing common software) 90 | endif 91 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vek280_base/hw/xsa_scripts/xsa.tcl: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | file mkdir build 7 | cd build 8 | source ../xsa_scripts/project.tcl 9 | source ../xsa_scripts/bd.tcl 10 | 11 | #For Questa Simulator 12 | source ../data/questa_sim.tcl 13 | 14 | #Generating Wrapper 15 | #make_wrapper -files [get_files ./my_project/my_project.srcs/sources_1/bd/vitis_design/vitis_design.bd] -top 16 | #add_files -norecurse ./my_project/my_project.srcs/sources_1/bd/vitis_design/hdl/vitis_design_wrapper.v 17 | 18 | #Generating Target 19 | generate_target all [get_files ./my_project/my_project.srcs/sources_1/bd/vitis_design/vitis_design.bd] 20 | update_compile_order -fileset sources_1 21 | update_compile_order -fileset sim_1 22 | #set_property top vitis_design_wrapper [current_fileset] 23 | 24 | # Generate simulation top for your entire design which would include 25 | # aggregated NOC in the form of xlnoc.bd 26 | # # uncomment below if noc switch network is not generated verify 27 | 28 | #generate_switch_network_for_noc 29 | update_compile_order -fileset sim_1 30 | 31 | #Generate the final simulation script which will compile the _sim_wrapper and xlnoc.bd modules also 32 | launch_simulation -scripts_only 33 | launch_simulation -step compile 34 | launch_simulation -step elaborate 35 | 36 | #Generating Emulation XSA 37 | file mkdir hw_emu 38 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 39 | 40 | set pre_synth "" 41 | if { $argc > 1} { 42 | set pre_synth [lindex $argv 2] 43 | } 44 | 45 | #Pre_synth Platform Flow 46 | if {$pre_synth} { 47 | set_property platform.platform_state "pre_synth" [current_project] 48 | write_hw_platform -hw -force -file hw.xsa 49 | } else { 50 | 51 | #Post_implememtation Platform 52 | # Synthesis Run 53 | launch_runs synth_1 -jobs 20 54 | wait_on_run synth_1 55 | 56 | #Implementation Run 57 | launch_runs impl_1 -to_step write_device_image 58 | wait_on_run impl_1 59 | 60 | open_run impl_1 61 | 62 | # Generating XSA 63 | write_hw_platform -hw -force -include_bit -file hw.xsa 64 | } 65 | 66 | #generate README.hw 67 | set board vek280 68 | set fd [open README.hw w] 69 | 70 | set board [lindex $argv 0] 71 | 72 | puts $fd "##########################################################################" 73 | puts $fd "This is a brief document containing design specific details for : ${board}" 74 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 75 | puts $fd "##########################################################################" 76 | 77 | set board_part [get_board_parts [current_board_part -quiet]] 78 | if { $board_part != ""} { 79 | puts $fd "BOARD: $board_part" 80 | } 81 | 82 | set design_name [get_property NAME [get_bd_designs]] 83 | puts $fd "BLOCK DESIGN: $design_name" 84 | 85 | set columns {%40s%30s%15s%50s} 86 | puts $fd [string repeat - 150] 87 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 88 | puts $fd [string repeat - 150] 89 | foreach ip [get_ips] { 90 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 91 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 92 | } 93 | close $fd 94 | 95 | cd .. 96 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include platform.mk 8 | 9 | ############################## Help Section ############################## 10 | .PHONY: help 11 | 12 | help:: 13 | @echo 'Makefile Usage:' 14 | @echo '' 15 | @echo ' All the make commands install platform to "platform_repo/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)"' 16 | @echo '' 17 | @echo ' make all' 18 | @echo ' Command used to generate platform with pre-built software components.' 19 | @echo '' 20 | @echo ' make all PREBUILT_LINUX_PATH= # uncomment below if noc switch network is not generated verify 27 | 28 | #generate_switch_network_for_noc 29 | update_compile_order -fileset sim_1 30 | 31 | #Generate the final simulation script which will compile the _sim_wrapper and xlnoc.bd modules also 32 | launch_simulation -scripts_only 33 | launch_simulation -step compile 34 | launch_simulation -step elaborate 35 | 36 | #Generating Emulation XSA 37 | file mkdir hw_emu 38 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 39 | 40 | #Calling Implementation for HW XSA 41 | set_property platform.platform_state "impl" [current_project] 42 | create_pr_configuration -name config_1 -partitions [list vitis_design_i/VitisRegion:VitisRegion_inst_0 ] 43 | set_property PR_CONFIGURATION config_1 [get_runs impl_1] 44 | 45 | set_property -name STEPS.PLACE_DESIGN.TCL.PRE -value [get_files -of_object [get_filesets utils_1] prohibit_select_bli_bels_for_hold.tcl] -objects [get_runs impl_1] 46 | launch_runs synth_1 -jobs 20 47 | wait_on_run synth_1 48 | 49 | launch_runs impl_1 -to_step write_device_image -jobs 10 50 | wait_on_run impl_1 51 | open_run impl_1 52 | write_hw_platform -force -fixed -static -file static.xsa 53 | file mkdir rp 54 | write_hw_platform -rp vitis_design_i/VitisRegion rp/rp.xsa 55 | 56 | #generate README.hw 57 | set board vck190 58 | 59 | set fd [open README.hw w] 60 | 61 | set board [lindex $argv 0] 62 | 63 | puts $fd "##########################################################################" 64 | puts $fd "This is a brief document containing design specific details for : ${board}" 65 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 66 | puts $fd "##########################################################################" 67 | 68 | set board_part [get_board_parts [current_board_part -quiet]] 69 | if { $board_part != ""} { 70 | puts $fd "BOARD: $board_part" 71 | } 72 | 73 | set design_name [get_property NAME [get_bd_designs]] 74 | puts $fd "BLOCK DESIGN: $design_name" 75 | 76 | set columns {%40s%30s%15s%50s} 77 | puts $fd [string repeat - 150] 78 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 79 | puts $fd [string repeat - 150] 80 | foreach ip [get_ips] { 81 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 82 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 83 | } 84 | close $fd 85 | 86 | cd .. 87 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/platform.mk: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | .EXPORT_ALL_VARIABLES: 8 | 9 | #tools 10 | VIVADO = $(XILINX_VIVADO)/bin/vivado 11 | DTC = $(XILINX_VITIS)/bin/dtc 12 | BOOTGEN = $(XILINX_VITIS)/bin/bootgen 13 | XSCT = $(XILINX_VITIS)/bin/xsct 14 | 15 | #platform specific 16 | PLATFORM = xilinx_vck190_base_dfx 17 | CPU_ARCH = a72 18 | BOARD = versal-vck190-reva-x-ebm-01-reva 19 | CORE = psv_cortexa72_0 20 | 21 | #versioning 22 | VERSION ?= 202520_1 23 | VER ?= 202520.1 24 | 25 | #common 26 | TOP_DIR ?= $(shell readlink -f .) 27 | 28 | #hw related 29 | XSA_DIR ?= $(TOP_DIR)/hw/build 30 | XSA ?= $(XSA_DIR)/hw.xsa 31 | RP_XSA ?= $(XSA_DIR)/rp/rp.xsa 32 | STATIC_XSA ?= $(XSA_DIR)/static.xsa 33 | HW_EMU_XSA ?= $(XSA_DIR)/hw_emu/hw_emu.xsa 34 | PRE_SYNTH ?= FALSE 35 | 36 | #sw related 37 | SW_DIR = $(TOP_DIR)/sw/build 38 | BOOT_DIR = $(SW_DIR)/platform/boot 39 | IMAGE_DIR = $(SW_DIR)/platform/image 40 | DTB_FILE = $(BOOT_DIR)/system.dtb 41 | BOOT_IMAGE = $(BOOT_DIR)/BOOT.BIN 42 | SW_FILES = $(IMAGE_DIR)/boot.scr $(BOOT_DIR)/u-boot.elf $(BOOT_DIR)/bl31.elf 43 | BOOT_FILES = u-boot.elf bl31.elf 44 | USER_DTSI = $(TOP_DIR)/sw/prebuilt_linux/user_dts/system-user.dtsi 45 | 46 | #platform related 47 | PLATFORM_NAME = $(PLATFORM)_$(VERSION) 48 | PLATFORM_SW_SRC = $(TOP_DIR)/platform 49 | PLATFORM_DIR = $(TOP_DIR)/platform_repo 50 | 51 | #flow related 52 | PREBUILT_LINUX_PATH ?= /opt/xilinx/platform/xilinx-versal-common-v2025.2 53 | ifneq ($(wildcard $(TOP_DIR)/xilinx-versal-common-v2025.2),) 54 | PREBUILT_LINUX_PATH ?= $(TOP_DIR)/xilinx-versal-common-v2025.2 55 | endif 56 | # Getting Absolute paths 57 | ifneq ("$(wildcard $(STATIC_XSA))","") 58 | STATIC_XSA_ABS ?= $(realpath $(STATIC_XSA)) 59 | override STATIC_XSA := $(realpath $(STATIC_XSA_ABS)) 60 | endif 61 | ifneq ("$(wildcard $(RP_XSA))","") 62 | RP_XSA_ABS ?= $(realpath $(RP_XSA)) 63 | override RP_XSA := $(realpath $(RP_XSA_ABS)) 64 | endif 65 | ifneq ("$(wildcard $(HW_EMU_XSA_ABS))","") 66 | HW_EMU_XSA_ABS ?= $(realpath $(HW_EMU_XSA)) 67 | override HW_EMU_XSA := $(realpath $(HW_EMU_XSA_ABS)) 68 | endif 69 | ifneq ("$(wildcard $(PREBUILT_LINUX_PATH_ABS))","") 70 | PREBUILT_LINUX_PATH_ABS ?= $(realpath $(PREBUILT_LINUX_PATH)) 71 | override PREBUILT_LINUX_PATH := $(realpath $(PREBUILT_LINUX_PATH_ABS)) 72 | endif 73 | 74 | #common targets 75 | check-vitis: 76 | ifeq ($(XILINX_VITIS),) 77 | $(error ERROR: 'XILINX_VITIS' variable not set, please set correctly and rerun) 78 | endif 79 | 80 | check-prebuilt: 81 | ifeq (,$(wildcard $(PREBUILT_LINUX_PATH))) 82 | $(info ) 83 | $(info PREBUILT common images cannot be found at $(PREBUILT_LINUX_PATH)) 84 | $(info If PREBUILT common images are present in another directory, Please specify the path to images as follows :) 85 | $(info make all PREBUILT_LINUX_PATH=/path/to/boot_files/dir) 86 | $(info else) 87 | $(info Please download PREBUILT common images from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html and extract them to /opt/xilinx/platform) 88 | $(error ) 89 | else 90 | $(info Found Platform Images at $(PREBUILT_LINUX_PATH)) 91 | endif 92 | ifeq ($(PREBUILT_LINUX_PATH),) 93 | $(error ERROR: 'PREBUILT_LINUX_PATH' is not accesible, please set this flag to path containing common software) 94 | endif 95 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/Makefile: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | 7 | include platform.mk 8 | 9 | ############################## Help Section ############################## 10 | .PHONY: help 11 | 12 | help:: 13 | @echo 'Makefile Usage:' 14 | @echo '' 15 | @echo ' All the make commands install platform to "platform_repo/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)"' 16 | @echo '' 17 | @echo ' make all' 18 | @echo ' Command used to generate platform with pre-built software components.' 19 | @echo '' 20 | @echo ' make all PREBUILT_LINUX_PATH= # uncomment below if noc switch network is not generated verify 30 | 31 | #generate_switch_network_for_noc 32 | update_compile_order -fileset sim_1 33 | 34 | #Generate the simulation script which will compile the _sim_wrapper and xlnoc.bd modules also 35 | launch_simulation -scripts_only 36 | launch_simulation -step compile 37 | launch_simulation -step elaborate 38 | 39 | #Generating Emulation XSA 40 | file mkdir hw_emu 41 | write_hw_platform -hw_emu -file hw_emu/hw_emu.xsa 42 | 43 | set pre_synth "" 44 | if { $argc > 1} { 45 | set pre_synth [lindex $argv 2] 46 | } 47 | 48 | #Pre_synth Platform Flow 49 | if {$pre_synth} { 50 | set_property platform.platform_state "pre_synth" [current_project] 51 | write_hw_platform -hw -force -file hw.xsa 52 | } else { 53 | 54 | #Post_implememtation Platform 55 | # Synthesis Run 56 | launch_runs synth_1 -jobs 20 57 | wait_on_run synth_1 58 | 59 | #Implementation Run 60 | launch_runs impl_1 -to_step write_device_image 61 | wait_on_run impl_1 62 | 63 | open_run impl_1 64 | 65 | # Generating XSA 66 | write_hw_platform -hw -force -include_bit -file hw.xsa 67 | } 68 | 69 | #generate README.hw 70 | set board vck190 71 | 72 | set fd [open README.hw w] 73 | 74 | set board [lindex $argv 0] 75 | 76 | puts $fd "##########################################################################" 77 | puts $fd "This is a brief document containing design specific details for : ${board}" 78 | puts $fd "This is auto-generated by Petalinux ref-design builder created @ [clock format [clock seconds] -format {%a %b %d %H:%M:%S %Z %Y}]" 79 | puts $fd "##########################################################################" 80 | 81 | set board_part [get_board_parts [current_board_part -quiet]] 82 | if { $board_part != ""} { 83 | puts $fd "BOARD: $board_part" 84 | } 85 | 86 | set design_name [get_property NAME [get_bd_designs]] 87 | puts $fd "BLOCK DESIGN: $design_name" 88 | 89 | set columns {%40s%30s%15s%50s} 90 | puts $fd [string repeat - 150] 91 | puts $fd [format $columns "MODULE INSTANCE NAME" "IP TYPE" "IP VERSION" "IP"] 92 | puts $fd [string repeat - 150] 93 | foreach ip [get_ips] { 94 | set catlg_ip [get_ipdefs -all [get_property IPDEF $ip]] 95 | puts $fd [format $columns [get_property NAME $ip] [get_property NAME $catlg_ip] [get_property VERSION $catlg_ip] [get_property VLNV $catlg_ip]] 96 | } 97 | close $fd 98 | 99 | cd .. 100 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_kv260_base/README.md: -------------------------------------------------------------------------------- 1 | # Vitis Base Platform for the kv260 Board 2 | 3 | ***Version: 2025.2*** 4 | 5 | This platform comes with common hardware features on the kv260 board like GEM and PS DDR4. The platform software includes OpenCV in PetaLinux. It is useful as a base platform for exercising Vitis capabilities and topologies on the kv260 board. 6 | 7 | ## Platform Specification 8 | 9 | The hardware configurations are sourced from [MPSoC Extensible Embedded Platform](https://github.com/Xilinx/XilinxCEDStore/tree/2025.2/ced/Xilinx/IPI/MPSoC_Ext_Platform) Vivado Customizable Example Design (CED). 10 | 11 | ### General Information 12 | 13 | | Type | Value | 14 | | ----------------- | --------------------------- | 15 | | Release Version | xilinx_kv260_base_202520_1 | 16 | | Vitis version | 2025.2 | 17 | | XRT Tag version | [202520.2.20.0_PetaLinux](https://github.com/Xilinx/XRT/tree/202520.2.20.0_Petalinux) | 18 | | Target board | kv260 | 19 | 20 | ### Interfaces 21 | 22 | | Interface | Region | Details | 23 | | --------- | ------ | ------------------ | 24 | | UART | PS | | 25 | | GEM | PS | | 26 | | USB | PS | USB driver enabled | 27 | | SDIO | PS | | 28 | 29 | ### Hardware Configurations 30 | 31 | | Configuration | Values | Details | 32 | | ----------------------------- | ----------------------------------------------------- | ------------------------------------| 33 | | PS DDR Size | 2GB | | 34 | | Clocks for Kernels | 150.000 MHz, 300.000 MHz, 75.000 MHz, 100.000 MHz, 200.000 MHz, 400.000 MHz, 600.000 MHz | Clocks are synchronous to each other| 35 | | SP Tags supported | DDR, LPDDR | All kernels share same DDR4 and LPDDR4 | 36 | | PS DDR Interfaces for Kernels | HP0, HP1, HP2, HP3, HPC0, HPC1, LPD | They share the same PS DDR. | 37 | | Interrupts | 32 Interrupts are enabled from PL Kernel to PS | | 38 | 39 | >Note: The 625MHz clock is generated by clock generator with MBUGCE driver, designed to deliver a high clock frequency with minimal clock skew for AIE-related designs. For more details about platform clock settings, please refer to the [Adding Clocks and Resets](https://docs.amd.com/r/en-US/ug1701-vitis-accelerated-embedded/Adding-Hardware-Interfaces) in UG1701. 40 | 41 | >Note: This platform is based on CED platform, to get the tcl commands equavalent to platform, please refer to hw/xsa/reference_bd.tcl 42 | 43 | ### Software Configurations 44 | 45 | Users can download [Ubuntu](https://ubuntu.com/download/amd) for KV260 to develop applications based on Ubuntu. Additionally, [Embedded Linux (Yocto)](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+SOMs+Starter+Kits#KV260-Starter-Kit) is available for embedded development. 46 | 47 | ## Build Instructions 48 | 49 | Please refer to the [build instructions](../../README.md#build-instructions) in the top README. 50 | 51 | ## Test the Platform 52 | 53 | Once the Vitis platform build completes, you can use the [Vitis Template](https://github.com/Xilinx/vitis_templates/) to build the Vadd application to test this platform. You can refer to [Vitis Tutorial](https://github.com/Xilinx/Vitis-Tutorials) for detailed guidance on platform validation. 54 | 55 |

Copyright © 2020–2025 Advanced Micro Devices, Inc.

56 | 57 |

Terms and Conditions

-------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/platform/generate_platform.py: -------------------------------------------------------------------------------- 1 | #****************************************************************************** 2 | # Copyright (C) 2020-2022 Xilinx, Inc. All rights reserved. 3 | # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights reserved. 4 | # SPDX-License-Identifier: MIT 5 | #****************************************************************************** 6 | import vitis 7 | import argparse 8 | import os 9 | 10 | print("Platform generation") 11 | parser = argparse.ArgumentParser() 12 | parser.add_argument("--static_xsa_path", type=str, dest="static_xsa_path") 13 | parser.add_argument("--platform_name", type=str, dest="platform_name") 14 | parser.add_argument("--emu_xsa_path", type=str, dest="emu_xsa_path") 15 | parser.add_argument("--platform_out", type=str, dest="platform_out") 16 | parser.add_argument("--boot_dir_path", type=str, dest="boot_dir_path") 17 | parser.add_argument("--img_dir_path", type=str, dest="img_dir_path") 18 | parser.add_argument("--rp_xsa_path", type=str, dest="rp_xsa_path") 19 | parser.add_argument("--user_dtsi", type=str, dest="user_dtsi") 20 | #parser.add_argument("--dtb", type=str, dest="dtb") 21 | 22 | args = parser.parse_args() 23 | static_xsa_path=args.static_xsa_path 24 | platform_name=args.platform_name 25 | emu_xsa_path=args.emu_xsa_path 26 | platform_out=args.platform_out 27 | boot_dir_path=args.boot_dir_path 28 | img_dir_path=args.img_dir_path 29 | #dtb=args.dtb 30 | rp_xsa_path=args.rp_xsa_path 31 | user_dtsi=args.user_dtsi 32 | print('args',args) 33 | client = vitis.create_client() 34 | #client.update_workspace(path=os.getcwd()/test) 35 | 36 | 37 | client.update_workspace(path=platform_out) 38 | #rp_info_args = client.add_rp_info_args(rp_xsa_path=rp_xsa_path) 39 | 40 | #platform = client.create_platform_component(name = platform_name, hw_design = static_xsa_path,os = "linux",cpu = "psv_cortexa72",domain_name = "linux_psv_cortexa72",generate_dtb = True,rp_info_args = rp_info_args) 41 | 42 | #platform = client.get_component(name=platform_name) 43 | 44 | #client.delete_component(name=platform_name) 45 | 46 | #advanced_options = client.create_advanced_options_dict(board_dtsi="versal-vck190-reva-x-ebm-01-reva",user_dtsi=$user_dtsi",dt_overlay="0",dt_zocl="1") 47 | advanced_options = client.create_advanced_options_dict(board_dtsi="versal-vck190-reva-x-ebm-01-reva",user_dtsi=user_dtsi,dt_overlay="0",dt_zocl="1") 48 | 49 | rp_info_args = client.add_rp_info_args(rp_xsa_path=rp_xsa_path) 50 | 51 | #advanced_options = client.create_advanced_options_dict(board_dtsi="versal-vck190-reva-x-ebm-01-reva",user_dtsi=$user_dtsi",dt_overlay="0") 52 | #rp_info_args = client.add_rp_info_args(rp_xsa_path=rp_xsa_path) 53 | 54 | platform = client.create_platform_component(name = platform_name,hw_design = static_xsa_path,os = "linux",cpu = "psv_cortexa72",domain_name = "xrt",emu_design = emu_xsa_path,generate_dtb = True, advanced_options = advanced_options, rp_info_args = rp_info_args, desc = " update for vck190_base_dfx latest : A base platform targeting VCK190_BASE_DFX which is the first Versal AI Core series evaluation kit, enabling designers to develop solutions using AI and DSP engines capable of delivering over 100X greater compute performance compared to current server class CPUs. This board includes 8GB of DDR4 UDIMM, 8GB LPDDR4 component, 400 AI engines, 1968 DSP engines, Dual-Core Arm® Cortex®-A72 and Dual-Core Cortex-R5. More information at https://www.xilinx.com/products/boards-and-kits/vck190.html" ) 55 | 56 | platform = client.get_component(name = platform_name) 57 | 58 | #aie domain 59 | domain = platform.add_domain(cpu = "ai_engine",os = "aie_runtime",name = "aiengine",display_name = "aiengine") 60 | #linux domain 61 | domain = platform.get_domain(name = "xrt") 62 | domain.set_sd_dir(path = img_dir_path) 63 | status = domain.set_boot_dir(path=boot_dir_path) 64 | status = domain.generate_bif() 65 | 66 | #status = domain.set_dtb(path=dtb) # used to bypass sdtgen from generate platform 67 | 68 | #status = platform.build() 69 | 70 | 71 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/README.md: -------------------------------------------------------------------------------- 1 | # Vitis Base Platform for the VMK180 Board 2 | 3 | ***Version: 2025.2**** 4 | 5 | This platform comes with common hardware features on the VMK180 board like GEM and PS DDR4. The platform software includes OpenCV in PetaLinux. It is useful as a base platform for exercising Vitis capabilities and topologies on the VMK180 board. 6 | 7 | ## Platform Specification 8 | 9 | The hardware configurations are sourced from [Versal_Extensible_Embedded_Platform](https://github.com/Xilinx/XilinxCEDStore/tree/2025.2/ced/Xilinx/IPI/Versal_Extensible_Embedded_Platform) Vivado Customizable Example Design (CED). 10 | 11 | ### General Information 12 | 13 | | Type | Value | 14 | | ----------------- | --------------------------- | 15 | | Release Version | xilinx_vmk180_base_202520_1 | 16 | | Vitis version | 2025.2 | 17 | | XRT Tag version | [202520.2.20.0_PetaLinux](https://github.com/Xilinx/XRT/tree/202520.2.20.0_Petalinux) | 18 | | Target board | VMK180 | 19 | 20 | ### Interfaces 21 | 22 | | Interface | Region | Details | 23 | | --------- | ------ | ------------------ | 24 | | UART | PS | | 25 | | GEM | PS | | 26 | | USB | PS | USB driver enabled | 27 | | SDIO | PS | | 28 | 29 | ### Hardware Configurations 30 | 31 | | Configuration | Values | Details | 32 | | ----------------------------- | ----------------------------------------------------- | ------------------------------------| 33 | | CIPS DDR Size | 8GB | | 34 | | LPDDR Size | 8GB | | 35 | | Clocks for Kernels | 156.25MHz, 100.00MHz, 312.5MHz, 78.125MHz, 625MHz | Clocks are synchronous to each other| 36 | | SP Tags supported | DDR, LPDDR | All kernels share same DDR4 and LPDDR4 | 37 | | Interrupts | 63 interrupts are enabled from PL Kernel to PS | | 38 | | AXI Interfaces for Kernel Control | 28 M_AXI_GP AXI interfaces are enabled | | 39 | 40 | >Note: The 625MHz clock is generated by clock generator with MBUGCE driver, designed to deliver a high clock frequency with minimal clock skew for AIE-related designs. For more details about platform clock settings, please refer to the [Adding Clocks and Resets](https://docs.amd.com/r/en-US/ug1701-vitis-accelerated-embedded/Adding-Hardware-Interfaces) in UG1701. 41 | 42 | >Note: This platform is based on CED platform, to get the tcl commands equavalent to platform, please refer to hw/xsa/reference_bd.tcl 43 | 44 | 45 | ### Software Configurations 46 | 47 | The software configurations are based on [VCK190 BSP](https://www.author.xilinx.com/member/vck190-ea.html#tools). Here is the list of additional configurations. 48 | 49 | | Configuration | Values | Details | 50 | | -------------------------------- | ------------------------------------------------------------ | ------- | 51 | | Additional Kernel Configurations | CONFIG_CONSOLE_LOGLEVEL_DEFAULT=1 | | 52 | | Additional RootFS Components | DNF
e2fsprogs-resize2fs
parted
xrt, xrt-dev and zocl
opencl-clhpp
opencl-headers
packagegroup-petalinux-opencv
>imagefeature-package-management
auto-login | | 53 | | Device Tree Modifications | Add zocl node for XRT | | 54 | 55 | ## Build Instructions 56 | 57 | Please refer to the [build instructions](../../README.md#build-instructions) in the top README. 58 | 59 |

Copyright © 2020–2025 Advanced Micro Devices, Inc.

60 | 61 |

Terms and Conditions

62 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vmk180_base/hw/README.hw: -------------------------------------------------------------------------------- 1 | ########################################################################## 2 | This is a brief document containing design specific details for : xilinx_vmk180_base_202520_1 3 | This is auto-generated by Petalinux ref-design builder created @ Mon Nov 30 14:27:54 IST 2020 4 | ########################################################################## 5 | BOARD: xilinx.com:vmk180:part0:2.0 6 | BLOCK DESIGN: bd_2487 bd_2567 bd_5e62 bd_660e bd_d133 bd_e4d6 bd_e536 bd_e5c6 xilinx_vmk180_base 7 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 8 | MODULE INSTANCE NAME IP TYPE IP VERSION IP 9 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 10 | xilinx_vmk180_base_CIPS_0_0 versal_cips 2.1 xilinx.com:ip:versal_cips:2.1 11 | xilinx_vmk180_base_axi_intc_cascaded_1_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 12 | xilinx_vmk180_base_axi_intc_parent_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 13 | xilinx_vmk180_base_cips_noc_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 14 | xilinx_vmk180_base_clk_wizard_0_0 clk_wizard 1.0 xilinx.com:ip:clk_wizard:1.0 15 | xilinx_vmk180_base_icn_ctrl_1_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 16 | xilinx_vmk180_base_icn_ctrl_2_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 17 | xilinx_vmk180_base_icn_ctrl_3_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 18 | xilinx_vmk180_base_icn_ctrl_4_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 19 | xilinx_vmk180_base_icn_ctrl_5_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 20 | xilinx_vmk180_base_noc_ddr4_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 21 | xilinx_vmk180_base_noc_lpddr4_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 22 | xilinx_vmk180_base_psr_100mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 23 | xilinx_vmk180_base_psr_150mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 24 | xilinx_vmk180_base_psr_200mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 25 | xilinx_vmk180_base_psr_300mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 26 | xilinx_vmk180_base_psr_400mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 27 | xilinx_vmk180_base_psr_600mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 28 | xilinx_vmk180_base_psr_75mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 29 | xilinx_vmk180_base_to_delete_kernel_ctrl_0_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 30 | xilinx_vmk180_base_to_delete_kernel_ctrl_1_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 31 | xilinx_vmk180_base_to_delete_kernel_ctrl_2_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 32 | xilinx_vmk180_base_to_delete_kernel_ctrl_3_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 33 | xilinx_vmk180_base_xlconcat_0_0 xlconcat 2.1 xilinx.com:ip:xlconcat:2.1 34 | -------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/README.md: -------------------------------------------------------------------------------- 1 | # Vitis Base DFX Platform for the vck190 Board 2 | 3 | ***Version: 2025.2*** 4 | 5 | This platform comes with common hardware features on the VCK190 board like AI Engine, GEM, DDR and LPDDR. The platform software includes OpenCV in PetaLinux. It is useful as a base platform for exercising Vitis capabilities and topologies on the VCK190 board. 6 | 7 | This platform supports Dynamic Function eXchange feature. Users can switch xclbin (acceleration kernel container for AI Engine and PL) without rebooting the system. 8 | 9 | ## Platform Specification 10 | 11 | The hardware configurations are sourced from [Versal DFX Extensible Embedded Platform](https://github.com/Xilinx/XilinxCEDStore/tree/2025.2/ced/Xilinx/IPI/versal_dfx) Vivado Customizable Example Design (CED). 12 | 13 | ### General Information 14 | 15 | | Type | Value | 16 | | ----------------- | --------------------------- | 17 | | Release Version | xilinx_vck190_base_dfx_202520_1 | 18 | | Vitis version | 2025.2 | 19 | | XRT Tag version | [202520.2.20.0_PetaLinux](https://github.com/Xilinx/XRT/tree/202520.2.20.0_Petalinux) | 20 | | Target board | VCK190 | 21 | 22 | ### Interfaces 23 | 24 | | Interface | Region | Details | 25 | | --------- | ------ | ------------------ | 26 | | UART | PS | | 27 | | GEM | PS | | 28 | | USB | PS | USB driver enabled | 29 | | SDIO | PS | | 30 | 31 | ### Hardware Configurations 32 | 33 | | Configuration | Values | Details | 34 | | ----------------------------- | ----------------------------------------------------- | ------------------------------------| 35 | | CIPS DDR Size | 8GB | | 36 | | LPDDR Size | 8GB | | 37 | | Clocks for Kernels | 156.25MHz, 104.166MHz, 312.5MHz, 78.125MHz, 208.33MHz, 416.66MHz, 625MHz | Clocks are synchronous to each other| 38 | | SP Tags supported | DDR, LPDDR | All kernels share same DDR4 and LPDDR4 | 39 | | Interrupts | 32 interrupts are enabled from PL Kernel to PS | | 40 | | AXI Interfaces for Kernel Control | 28 M_AXI_GP AXI interfaces are enabled | | 41 | | AI Engine | Enabled | | 42 | 43 | ### Software Configurations 44 | 45 | The software configurations are based on [VCK190 BSP](https://www.author.xilinx.com/member/vck190-ea.html#tools). Here is the list of additional configurations. 46 | 47 | | Configuration | Values | Details | 48 | | -------------------------------- | ------------------------------------------------------------ | ------- | 49 | | Additional Kernel Configurations | CONFIG_CONSOLE_LOGLEVEL_DEFAULT=1 | | 50 | | Additional RootFS Components | DNF
e2fsprogs-resize2fs
parted
xrt, xrt-dev and zocl
opencl-clhpp
opencl-headers
packagegroup-petalinux-opencv
>imagefeature-package-management
auto-login | | 51 | | Device Tree Modifications | Add zocl node for XRT | | 52 | 53 | ## Build Instructions 54 | 55 | Please refer to the [build instructions](../../README.md#build-instructions) in the top README. 56 | 57 | ## Test the Platform 58 | 59 | Once the Vitis platform build completes, you can use the [Vitis Acceleration examples](https://github.com/Xilinx/Vitis_Accel_Examples) to build with these platforms to test this platform. 60 | 61 |

Copyright © 2020–2025 Advanced Micro Devices, Inc.

62 | 63 |

Terms and Conditions

-------------------------------------------------------------------------------- /Xilinx_Official_Platforms/xilinx_vck190_base_dfx/hw/README.hw: -------------------------------------------------------------------------------- 1 | ########################################################################## 2 | This is a brief document containing design specific details for : xilinx_vck190_base_202520_1 3 | This is auto-generated by Petalinux ref-design builder created @ Fri Oct 23 10:50:48 IST 2020 4 | ########################################################################## 5 | BOARD: xilinx.com:vck190:part0:2.0 6 | BLOCK DESIGN: bd_038d bd_1837 bd_18c7 bd_1927 bd_a393 bd_b4b0 bd_d896 bd_d976 bd_dbef xilinx_vck190_base 7 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 8 | MODULE INSTANCE NAME IP TYPE IP VERSION IP 9 | ------------------------------------------------------------------------------------------------------------------------------------------------------ 10 | xilinx_vck190_base_CIPS_0_0 versal_cips 2.1 xilinx.com:ip:versal_cips:2.1 11 | xilinx_vck190_base_ai_engine_0_0 ai_engine 2.0 xilinx.com:ip:ai_engine:2.0 12 | xilinx_vck190_base_axi_intc_cascaded_1_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 13 | xilinx_vck190_base_axi_intc_parent_0 axi_intc 4.1 xilinx.com:ip:axi_intc:4.1 14 | xilinx_vck190_base_cips_noc_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 15 | xilinx_vck190_base_clk_wizard_0_0 clk_wizard 1.0 xilinx.com:ip:clk_wizard:1.0 16 | xilinx_vck190_base_icn_ctrl_1_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 17 | xilinx_vck190_base_icn_ctrl_2_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 18 | xilinx_vck190_base_icn_ctrl_3_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 19 | xilinx_vck190_base_icn_ctrl_4_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 20 | xilinx_vck190_base_icn_ctrl_5_0 smartconnect 1.0 xilinx.com:ip:smartconnect:1.0 21 | xilinx_vck190_base_noc_ddr4_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 22 | xilinx_vck190_base_noc_lpddr4_0 axi_noc 1.0 xilinx.com:ip:axi_noc:1.1 23 | xilinx_vck190_base_psr_100mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 24 | xilinx_vck190_base_psr_150mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 25 | xilinx_vck190_base_psr_200mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 26 | xilinx_vck190_base_psr_300mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 27 | xilinx_vck190_base_psr_400mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 28 | xilinx_vck190_base_psr_600mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 29 | xilinx_vck190_base_psr_75mhz_0 proc_sys_reset 5.0 xilinx.com:ip:proc_sys_reset:5.0 30 | xilinx_vck190_base_to_delete_kernel_ctrl_0_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 31 | xilinx_vck190_base_to_delete_kernel_ctrl_1_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 32 | xilinx_vck190_base_to_delete_kernel_ctrl_2_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 33 | xilinx_vck190_base_to_delete_kernel_ctrl_3_0 axi_vip 1.1 xilinx.com:ip:axi_vip:1.1 34 | xilinx_vck190_base_xlconcat_0_0 xlconcat 2.1 xilinx.com:ip:xlconcat:2.1 35 | --------------------------------------------------------------------------------