├── driver ├── tests │ ├── utest │ │ ├── elf_files │ │ │ ├── emptyFile │ │ │ ├── aie_elfs │ │ │ │ ├── mmul │ │ │ │ ├── large_elf │ │ │ │ ├── overlap_elf │ │ │ │ └── passthrough │ │ │ └── aieml_elfs │ │ │ │ └── passthrough │ │ ├── test.cpp │ │ ├── aie_hw_config.h │ │ ├── test_timer_aie.cpp │ │ ├── test_events_aieml.cpp │ │ ├── test_timer_aieml.cpp │ │ ├── test_events_aie.cpp │ │ ├── test_locks_aieml.cpp │ │ ├── CMakeLists.txt │ │ ├── test_multi_part.cpp │ │ ├── test_locks_aie.cpp │ │ ├── test_locks.cpp │ │ ├── test_btree4.cpp │ │ ├── utest.c │ │ ├── common │ │ │ └── hw_config.h │ │ ├── test_pm.cpp │ │ └── test_dma_aie.cpp │ ├── CMakeLists.txt │ └── stest │ │ ├── aiert_tests.h │ │ └── hw_config.h ├── docs │ ├── xlogo_bg.gif │ └── html_footer.html ├── src │ ├── global │ │ ├── xaie_version.h │ │ └── xaiegbl_defs.h │ ├── pm │ │ ├── xaie_reset_aieml.h │ │ ├── xaie_reset.h │ │ ├── xaie_reset_aie.h │ │ ├── xaie_clock.h │ │ ├── xaie_ecc.h │ │ ├── xaie_tilectrl.h │ │ ├── xaie_reset_aieml.c │ │ ├── xaie_tilectrl.c │ │ └── xaie_reset_aie.c │ ├── interrupt │ │ ├── xaie_interrupt_aie.h │ │ ├── xaie_interrupt_aieml.h │ │ ├── xaie_interrupt_aie2ps.h │ │ ├── xaie_interrupt_aie2ps.c │ │ ├── xaie_interrupt_aie.c │ │ ├── xaie_interrupt_aieml.c │ │ └── xaie_interrupt.h │ ├── xaiengine.h │ ├── io_backend │ │ ├── ext │ │ │ ├── xaie_io_common.h │ │ │ └── xaie_io_common.c │ │ ├── privilege │ │ │ └── xaie_io_privilege.h │ │ └── xaie_io_internal.h │ ├── device │ │ ├── xaie_device_aie2ps.h │ │ ├── xaie_device_aie.h │ │ └── xaie_device_aieml.h │ ├── stream_switch │ │ ├── xaie_ss_aie.h │ │ ├── xaie_ss_aie2ps.h │ │ ├── xaie_ss_aieml.h │ │ ├── xaie_ss_aie.c │ │ └── xaie_ss.h │ ├── util │ │ ├── xaie_util_events.h │ │ ├── btree4.h │ │ └── xaie_util_events.c │ ├── Makefile.rsc │ ├── core │ │ ├── xaie_uc.h │ │ ├── xaie_core_aie.h │ │ ├── xaie_core_aieml.h │ │ └── xaie_elfloader.h │ ├── locks │ │ ├── xaie_locks.h │ │ ├── xaie_locks_aie.h │ │ └── xaie_locks_aieml.h │ ├── Makefile │ ├── common │ │ ├── xaie_txn.h │ │ └── xaie_helper_internal.h │ ├── timer │ │ └── xaie_timer.h │ ├── npi │ │ ├── xaie_npi.h │ │ └── xaie_npi_aie.c │ ├── lite │ │ ├── xaie_lite.c │ │ ├── xaie_lite.h │ │ ├── xaie_lite_util.h │ │ ├── xaie_lite_hwcfg.h │ │ └── xaie_lite_internal.h │ ├── dma │ │ ├── xaie_dma_aie2ps.h │ │ ├── xaie_dma_aie.h │ │ └── xaie_dma_aieml.h │ ├── memory │ │ └── xaie_mem.h │ ├── pl │ │ └── xaie_plif.h │ ├── trace │ │ └── xaie_trace.h │ ├── CMakeLists.txt │ ├── perfcnt │ │ └── xaie_perfcnt.h │ └── Makefile.Linux ├── data │ ├── aienginev2.yaml │ ├── aienginev2.mdd │ └── aienginev2.tcl ├── cmake │ ├── platforms │ │ ├── versal-linux.cmake │ │ ├── cross-linux-g++.cmake │ │ └── cross-genric-g++.cmake │ ├── modules │ │ └── FindLibxaiengine.cmake │ ├── collect.cmake │ └── options.cmake ├── README.md ├── examples │ └── Makefile └── CMakeLists.txt ├── .gitignore ├── fal ├── data │ ├── aiefal.yaml │ └── aiefal.mdd ├── tests │ ├── CMakeLists.txt │ └── utests │ │ └── tc │ │ ├── test.cpp │ │ └── common │ │ └── tc_config.h ├── cmake │ ├── platforms │ │ ├── versal-linux.cmake │ │ ├── cross-linux-g++.cmake │ │ └── cross-genric-g++.cmake │ ├── depends.cmake │ ├── modules │ │ └── FindLibxaiengine.cmake │ └── collect.cmake ├── doc │ ├── aiefal-state.txt │ ├── aiefal-state-prereserved.txt │ └── CMakeLists.txt ├── src │ ├── common │ │ ├── xaiefal-common.hpp │ │ └── xaiefal-log.hpp │ ├── xaiefal.hpp │ ├── Makefile │ └── CMakeLists.txt ├── examples │ └── CMakeLists.txt ├── CMakeLists.txt └── README.md ├── README.md ├── cmake └── Findcommon.cmake └── .githooks └── pre-commit /driver/tests/utest/elf_files/emptyFile: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /driver/docs/xlogo_bg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/docs/xlogo_bg.gif -------------------------------------------------------------------------------- /driver/tests/utest/elf_files/aie_elfs/mmul: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/tests/utest/elf_files/aie_elfs/mmul -------------------------------------------------------------------------------- /driver/tests/utest/elf_files/aie_elfs/large_elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/tests/utest/elf_files/aie_elfs/large_elf -------------------------------------------------------------------------------- /driver/tests/utest/elf_files/aie_elfs/overlap_elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/tests/utest/elf_files/aie_elfs/overlap_elf -------------------------------------------------------------------------------- /driver/tests/utest/elf_files/aie_elfs/passthrough: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/tests/utest/elf_files/aie_elfs/passthrough -------------------------------------------------------------------------------- /driver/tests/utest/elf_files/aieml_elfs/passthrough: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/HEAD/driver/tests/utest/elf_files/aieml_elfs/passthrough -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | #Ignore these file extensions 2 | *.a 3 | *.o 4 | *.so 5 | *.so.* 6 | 7 | #Ignore these directories 8 | /driver/include 9 | /driver/internal 10 | -------------------------------------------------------------------------------- /driver/src/global/xaie_version.h: -------------------------------------------------------------------------------- 1 | #ifndef VERSION_H 2 | #define VERSION_H 3 | 4 | #define GIT_PARENT_HASH "84f2fd31aa5ed202c83ed2d10c9e8a20f9afa4db" 5 | #define GIT_BRANCH "main-aie" 6 | 7 | #endif // VERSION_H 8 | -------------------------------------------------------------------------------- /driver/tests/utest/test.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/CommandLineTestRunner.h" 2 | #include "CppUTest/TestHarness.h" 3 | #include 4 | 5 | int main(int argc, char**argv) 6 | { 7 | return CommandLineTestRunner::RunAllTests(argc, argv); 8 | } 9 | -------------------------------------------------------------------------------- /driver/docs/html_footer.html: -------------------------------------------------------------------------------- 1 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /fal/data/aiefal.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 2 | #SPDX-License-Identifier: MIT 3 | %YAML 1.2 4 | --- 5 | title: Bindings for AIE FAL Driver 6 | 7 | maintainers: 8 | - Jaydip Patel 9 | 10 | type: driver 11 | 12 | ... 13 | -------------------------------------------------------------------------------- /fal/tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | add_subdirectory(utests) 8 | -------------------------------------------------------------------------------- /driver/tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | add_subdirectory(utest) 7 | -------------------------------------------------------------------------------- /fal/tests/utests/tc/test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include "xaiefal/xaiefal.hpp" 5 | 6 | #include "CppUTest/CommandLineTestRunner.h" 7 | 8 | using namespace xaiefal; 9 | 10 | int main(int ac, char** av) 11 | { 12 | 13 | Logger::log(LogLevel::FAL_INFO) << "xaiefal cpputests." << std::endl; 14 | return CommandLineTestRunner::RunAllTests(ac, av); 15 | } 16 | -------------------------------------------------------------------------------- /driver/tests/utest/aie_hw_config.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2020 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | #define XAIE_FEATURE_LITE 7 | 8 | #define XAIE_DEV_SINGLE_GEN XAIE_DEV_GEN_AIE 9 | 10 | #include "xaiengine/xaie_lite_hwcfg.h" 11 | #include "xaiengine.h" 12 | -------------------------------------------------------------------------------- /driver/data/aienginev2.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 2 | #SPDX-License-Identifier: MIT 3 | %YAML 1.2 4 | --- 5 | title: Bindings for AIE Engine Driver 6 | 7 | maintainers: 8 | - Gregory Williams 9 | 10 | type: driver 11 | device_type: aie 12 | 13 | properties: 14 | compatible: 15 | items: 16 | - const: xlnx,ai-engine-2.0 17 | 18 | depends: 19 | aiefal: [] 20 | ... 21 | -------------------------------------------------------------------------------- /driver/cmake/platforms/versal-linux.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | set (CMAKE_SYSTEM_PROCESSOR "aarch64" CACHE STRING "") 7 | set (CROSS_PREFIX "aarch64-linux-gnu-" CACHE STRING "") 8 | include (cross-linux-g++) 9 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AI Engine Run Time 2 | 3 | AI Engine runtime(aie-rt) is a combination of two components. 4 | * driver 5 | * fal 6 | 7 | ## AIE Driver(driver) 8 | AIE Driver is a userspace library that provides hardware access to applications. 9 | 10 | ## AIE FAL(fal) 11 | AIE FAL is functional abstraction layer that provides common userspace APIs for 12 | runtime AIE resource management. 13 | 14 | ## License 15 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 16 | SPDX-License-Identifier: MIT 17 | -------------------------------------------------------------------------------- /fal/data/aiefal.mdd: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | OPTION psf_version = 2.1; 8 | 9 | BEGIN driver aiefal 10 | OPTION supported_peripherals = (); 11 | OPTION copyfiles = all; 12 | OPTION VERSION = 1.9; 13 | OPTION NAME = aiefal; 14 | END driver 15 | -------------------------------------------------------------------------------- /fal/cmake/platforms/versal-linux.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_PROCESSOR "aarch64" CACHE STRING "") 8 | set (CROSS_PREFIX "aarch64-linux-gnu-" CACHE STRING "") 9 | include (cross-linux-g++) 10 | 11 | # vim: expandtab:ts=2:sw=2:smartindent 12 | -------------------------------------------------------------------------------- /fal/doc/aiefal-state.txt: -------------------------------------------------------------------------------- 1 | @startuml 2 | title "Resource Allocated At Runtime" 3 | skinparam linetype ortho 4 | skinparam classAttributeIconSize 0 5 | [*] --> Initialized 6 | Initialized --> Reserved : reserve() 7 | Initialized --> Configured : config_parameters 8 | Reserved --> Reserved_and_Configured : config_parameters 9 | Configured --> Reserved_and_Configured : reserve() 10 | Reserved_and_Configured --> Configured : release() 11 | Reserved_and_Configured --> Running : start() 12 | Running --> Reserved_and_Configured : stop() 13 | 14 | @enduml 15 | -------------------------------------------------------------------------------- /driver/README.md: -------------------------------------------------------------------------------- 1 | # AI Engine Driver 2 | 3 | The userspace library for ai-engine provides APIs to configure AIE registers. 4 | 5 | ## Hardware support 6 | 7 | The user space library is supports both AIE, AIEML. 8 | 9 | ## Compilation 10 | ### Compile library 11 | `make -f Makefile.Linux` 12 | ### Generate Documentation 13 | `make -f Makefile.Linux doc-generate` 14 | 15 | HTML docs are populated in ./tmp/api/ 16 | 17 | PDF doc will be available at ./tmp/latex/refman.pdf 18 | 19 | ## License 20 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 21 | SPDX-License-Identifier: MIT 22 | -------------------------------------------------------------------------------- /driver/data/aienginev2.mdd: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | OPTION psf_version = 2.1; 8 | 9 | BEGIN driver aienginev2 10 | 11 | OPTION supported_peripherals = (aie aiengine ai_engine); 12 | OPTION driver_state = ACTIVE; 13 | OPTION copyfiles = all; 14 | OPTION VERSION = 3.8; 15 | OPTION DEPENDS = (aiefal); 16 | OPTION NAME = aienginev2; 17 | 18 | END driver 19 | -------------------------------------------------------------------------------- /driver/cmake/platforms/cross-linux-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | set (CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") 7 | set (CMAKE_C_COMPILER "${CROSS_PREFIX}gcc" CACHE STRING "") 8 | set (CMAKE_CXX_COMPILER "${CROSS_PREFIX}g++" CACHE STRING "") 9 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 10 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 11 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 12 | -------------------------------------------------------------------------------- /driver/cmake/platforms/cross-genric-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | set (CMAKE_SYSTEM_NAME "Generic" CACHE STRING "") 7 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 8 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 9 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 10 | 11 | include (CMakeForceCompiler) 12 | CMAKE_FORCE_C_COMPILER ("${CROSS_PREFIX}gcc" GNU) 13 | CMAKE_FORCE_CXX_COMPILER ("${CROSS_PREFIX}g++" GNU) 14 | -------------------------------------------------------------------------------- /fal/cmake/platforms/cross-linux-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") 8 | set (CMAKE_C_COMPILER "${CROSS_PREFIX}gcc" CACHE STRING "") 9 | set (CMAKE_CXX_COMPILER "${CROSS_PREFIX}g++" CACHE STRING "") 10 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 11 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 12 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 13 | 14 | # vim: expandtab:ts=2:sw=2:smartindent 15 | -------------------------------------------------------------------------------- /fal/cmake/depends.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | if (WITH_XAIEDRV_FIND) 8 | find_package (Libxaiengine REQUIRED) 9 | collect (PROJECT_INC_DIRS "${LIBXAIENGINE_INCLUDE_DIR}") 10 | collect (PROJECT_LIB_DIRS "${LIBXAIENGINE_LIB_DIR}") 11 | collect (PROJECT_LIB_DEPS "${LIBXAIENGINE_LIB}") 12 | else() 13 | collect (PROJECT_INC_DIRS "${CMAKE_BINARY_DIR}/driver-src/include") 14 | collect (PROJECT_LIB_DIRS "${CMAKE_BINARY_DIR}/driver-src/src") 15 | collect (PROJECT_LIB_DEPS "xaiengine") 16 | endif (WITH_XAIEDRV_FIND) 17 | -------------------------------------------------------------------------------- /fal/doc/aiefal-state-prereserved.txt: -------------------------------------------------------------------------------- 1 | @startuml 2 | title "Use Resource Allocated During Compilation" 3 | skinparam linetype ortho 4 | skinparam classAttributeIconSize 0 5 | [*] --> Initialized_and_Prereserved 6 | Initialized_and_Prereserved --> Reserved : reserve() 7 | Initialized_and_Prereserved --> Configured_and_Preserved : config_parameters 8 | Configured_and_Preserved -d-> Reserved_and_Configured : reserve() 9 | Reserved -u-> Reserved_and_Configured: config_parameters 10 | Reserved_and_Configured -u-> Configured_and_Preserved : free() 11 | Reserved_and_Configured -d-> Running : start() 12 | Running -u-> Reserved_and_Configured : stop() 13 | Reserved_and_Configured -l-> Configured : release() 14 | Configured_and_Preserved -l-> Configured: release() 15 | 16 | @enduml 17 | -------------------------------------------------------------------------------- /fal/cmake/platforms/cross-genric-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_NAME "Generic" CACHE STRING "") 8 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 9 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 10 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 11 | 12 | include (CMakeForceCompiler) 13 | CMAKE_FORCE_C_COMPILER ("${CROSS_PREFIX}gcc" GNU) 14 | CMAKE_FORCE_CXX_COMPILER ("${CROSS_PREFIX}g++" GNU) 15 | 16 | # vim: expandtab:ts=2:sw=2:smartindent 17 | -------------------------------------------------------------------------------- /driver/data/aienginev2.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | proc copy_files {dir} { 8 | foreach sub_dir [glob -nocomplain -directory $dir -type d *] { 9 | copy_files $sub_dir 10 | } 11 | foreach fn [glob -nocomplain [file join $dir * -type f *]] { 12 | file copy -force $fn "./src" 13 | } 14 | } 15 | 16 | proc copy_sub_files {dir} { 17 | foreach sub_dir [glob -nocomplain -directory $dir -type d *] { 18 | copy_files $sub_dir 19 | } 20 | } 21 | 22 | proc generate {libhandle} { 23 | copy_sub_files "./src" 24 | file mkdir "../../include/xaiengine" 25 | } 26 | -------------------------------------------------------------------------------- /fal/src/common/xaiefal-common.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #pragma once 5 | 6 | namespace xaiefal { 7 | #define XAIE_RSC_ID_ANY (-1U) 8 | #define XAIE_RSC_TYPE_ANY (-1U) 9 | #define XAIE_MOD_ANY (-1U) 10 | #define XAIE_LOC_ANY 0xFFU 11 | } 12 | 13 | #ifdef __linux__ 14 | #define __COMPILER_SUPPORTS_LOCKS__ 15 | #endif 16 | 17 | #include 18 | #include 19 | #ifdef __COMPILER_SUPPORTS_LOCKS__ 20 | #include 21 | #endif 22 | 23 | #ifdef __COMPILER_SUPPORTS_LOCKS__ 24 | #define _XAIEFAL_MUTEX_ACQUIRE(L) const std::lock_guard lock(L) 25 | #define _XAIEFAL_MUTEX_DECLARE(L) std::mutex L 26 | #else 27 | #define _XAIEFAL_MUTEX_ACQUIRE(...) 28 | #define _XAIEFAL_MUTEX_DECLARE(...) 29 | #endif 30 | -------------------------------------------------------------------------------- /driver/examples/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | CC ?= gcc 8 | 9 | CFLAGS += -Wall -Wextra 10 | INCLUDEDIR = ../include 11 | LIBDIR = ../src 12 | 13 | SRCS = $(wildcard *.c) 14 | SRCS := $(filter-out xaie_error_interrupt_test.c, $(SRCS)) 15 | APPS = $(patsubst %.c, %, $(SRCS)) 16 | APPSTMPS = $(patsubst %.c, %.out, $(SRCS)) 17 | 18 | all: build 19 | 20 | build: $(APPSTMPS) 21 | 22 | %.out: %.o 23 | $(CC) -o $(patsubst %.out, %, $@) $< -L$(LIBDIR) -lxaiengine 24 | 25 | %.o: %.c 26 | $(CC) -I$(INCLUDEDIR) $(CFLAGS) -c $< -o $@ 27 | 28 | clean: 29 | rm -f $(APPS) *.o 30 | -------------------------------------------------------------------------------- /fal/src/xaiefal.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | -------------------------------------------------------------------------------- /driver/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | cmake_minimum_required (VERSION 3.1) 7 | 8 | list (APPEND CMAKE_MODULE_PATH 9 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake" 10 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules" 11 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake/platforms") 12 | 13 | project (xaiengine VERSION 3.8) 14 | 15 | include (CheckIncludeFiles) 16 | include (CheckCSourceCompiles) 17 | include (collect) 18 | include (options) 19 | 20 | enable_testing () 21 | 22 | set(ENV{UTEST_BUILD} "ON") 23 | add_subdirectory (src ${CMAKE_CURRENT_BINARY_DIR}/driver-src) 24 | 25 | if (WITH_TESTS) 26 | add_subdirectory (tests) 27 | endif (WITH_TESTS) 28 | -------------------------------------------------------------------------------- /fal/doc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | find_package(Doxygen) 8 | if (DOXYGEN_FOUND) 9 | 10 | configure_file (Doxyfile.in Doxyfile @ONLY) 11 | 12 | add_custom_target (doc ALL 13 | ${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile 14 | WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} 15 | ) 16 | 17 | install (DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/html 18 | DESTINATION share/doc/${PROJECT_NAME}) 19 | install (FILES ${PROJECT_SOURCE_DIR}/README.md 20 | DESTINATION share/doc/${PROJECT_NAME}) 21 | install (FILES ${PROJECT_SOURCE_DIR}/license.txt 22 | DESTINATION share/doc/${PROJECT_NAME}) 23 | 24 | endif (DOXYGEN_FOUND) 25 | 26 | # vim: expandtab:ts=2:sw=2:smartindent 27 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aieml.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML reset controls. This header file is not 13 | * exposed to the user. 14 | * 15 | ******************************************************************************/ 16 | 17 | #ifndef XAIE_RESET_AIEML_H 18 | #define XAIE_RESET_AIEML_H 19 | 20 | /***************************** Include Files *********************************/ 21 | #include "xaiegbl.h" 22 | 23 | /************************** Function Prototypes *****************************/ 24 | AieRC _XAieMl_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols); 25 | 26 | #endif /* XAIE_RESET_AIEML_H */ 27 | /** @} */ 28 | -------------------------------------------------------------------------------- /fal/cmake/modules/FindLibxaiengine.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | # FindLibxaiengine 8 | # -------- 9 | # 10 | # Find libxaiengine 11 | # 12 | # Find the native libxaiengine includes and library this module defines 13 | # 14 | # :: 15 | # 16 | # LIBXAIENGINE_INCLUDE_DIR, where to find xaiengine.h, etc. 17 | 18 | find_path(LIBXAIENGINE_INCLUDE_DIR NAMES xaiengine.h PATHS ${CMAKE_FIND_ROOT_PATH}) 19 | find_library(LIBXAIENGINE_LIB NAMES xaiengine PATHS ${CMAKE_FIND_ROOT_PATH}) 20 | get_filename_component(LIBXAIENGINE_LIB_DIR ${LIBXAIENGINE_LIB} DIRECTORY) 21 | 22 | include (FindPackageHandleStandardArgs) 23 | FIND_PACKAGE_HANDLE_STANDARD_ARGS (LIBXAIENGINE DEFAULT_MSG LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR) 24 | 25 | mark_as_advanced (LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR LIBXAIENGINE_LIB_DIR) 26 | -------------------------------------------------------------------------------- /driver/cmake/modules/FindLibxaiengine.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | # FindLibxaiengine 7 | # -------- 8 | # 9 | # Find libxaiengine 10 | # 11 | # Find the native libxaiengine includes and library this module defines 12 | # 13 | # :: 14 | # 15 | # LIBXAIENGINE_INCLUDE_DIR, where to find xaiengine.h, etc. 16 | 17 | find_path(LIBXAIENGINE_INCLUDE_DIR NAMES xaiengine.h PATHS ${CMAKE_FIND_ROOT_PATH}) 18 | find_library(LIBXAIENGINE_LIB NAMES xaiengine PATHS ${CMAKE_FIND_ROOT_PATH}) 19 | get_filename_component(LIBXAIENGINE_LIB_DIR ${LIBXAIENGINE_LIB} DIRECTORY) 20 | 21 | include (FindPackageHandleStandardArgs) 22 | FIND_PACKAGE_HANDLE_STANDARD_ARGS (LIBXAIENGINE DEFAULT_MSG LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR) 23 | 24 | mark_as_advanced (LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR LIBXAIENGINE_LIB_DIR) 25 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific AIE. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIE_H 16 | #define XAIE_INTERRUPT_AIE_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAie_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset.h 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_RESET_H 16 | #define XAIE_RESET_H 17 | 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | /**************************** Type Definitions *******************************/ 21 | /************************** Function Prototypes *****************************/ 22 | AieRC XAie_ResetPartition(XAie_DevInst *DevInst); 23 | AieRC XAie_ClearPartitionMems(XAie_DevInst *DevInst); 24 | #endif /* end of protection macro */ 25 | 26 | /** @} */ 27 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aieml.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific to AIE ML. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIEML_H 16 | #define XAIE_INTERRUPT_AIEML_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAieMl_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie2ps.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific AIE2PS. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIE2PS_H 16 | #define XAIE_INTERRUPT_AIE2PS_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAie2ps_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | /** @} */ 26 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aie.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE reset controls. This header file is not 13 | * exposed to the user. 14 | * 15 | ******************************************************************************/ 16 | #ifndef XAIE_RESET_AIE_H 17 | #define XAIE_RESET_AIE_H 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | 21 | /************************** Function Prototypes *****************************/ 22 | AieRC _XAie_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols); 23 | AieRC _XAie_PmSetPartitionClock(XAie_DevInst *DevInst, u8 Enable); 24 | u8 _XAie_PmIsTileRequested(XAie_DevInst *DevInst, XAie_LocType Loc); 25 | 26 | #endif /* XAIE_RESET_AIE_H */ 27 | /** @} */ 28 | -------------------------------------------------------------------------------- /driver/tests/stest/aiert_tests.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file aiert_tests.h 10 | * @{ 11 | * 12 | * Header file for declaring AIE-RT simulator tests (AIEML-Tests) 13 | * 14 | ******************************************************************************/ 15 | 16 | /* List of simulator test APIs 17 | * Description: Add an external reference to your test-api/s here 18 | * 19 | */ 20 | extern int test_lock(XAie_DevInst *DevInst); 21 | extern int test_aie_auto_routing(XAie_DevInst *DevInst); 22 | /* 23 | * Description: Add function pointers to the above test-api/s here 24 | */ 25 | int (*tests_aiert[])(XAie_DevInst *DevInst) = 26 | { 27 | test_lock 28 | }; 29 | 30 | /* 31 | * Description: Add the name of the test-api/s 32 | */ 33 | const char *test_names_aiert[] = 34 | { 35 | "test_lock", 36 | "test_aie_auto_routing" 37 | }; 38 | /** @} */ 39 | -------------------------------------------------------------------------------- /driver/src/xaiengine.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | -------------------------------------------------------------------------------- /fal/src/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | INCLUDEDIR_ROOT=../../../include 8 | INCLUDEDIR=$(INCLUDEDIR_ROOT)/xaiefal 9 | INCLUDES=$(wildcard *.hpp) $(wildcard */*.hpp) 10 | TDIRS=$(addsuffix /,$(addprefix $(INCLUDEDIR)/,$(dir $(wildcard */*.hpp)))) 11 | TINCLUDES=$(addprefix $(INCLUDEDIR)/,$(INCLUDES)) 12 | 13 | ifneq (,$(findstring Windows,$(OS))) 14 | IS_WIN=1 15 | else 16 | IS_WIN=0 17 | endif 18 | 19 | libs: print_msg_xaiefal 20 | 21 | print_msg_xaiefal: 22 | @echo "Compiling xaiefal" 23 | 24 | .PHONY: include 25 | include: xaiefal_includes 26 | 27 | xaiefal_includes: $(INCLUDEDIR) $(TDIRS) $(TINCLUDES) 28 | 29 | ifeq (0,$(IS_WIN)) 30 | $(INCLUDEDIR): 31 | mkdir $@ 32 | $(INCLUDEDIR)/%/: $(INCLUDEDIR) 33 | mkdir $@ 34 | else 35 | $(INCLUDEDIR): 36 | "mkdir" -p $(subst /,\,$@) 37 | $(INCLUDEDIR)/%/: $(INCLUDEDIR) 38 | "mkdir" -p $(subst /,\,$@) 39 | endif 40 | 41 | $(INCLUDEDIR)/%.hpp: %.hpp $(INCLUDEDIR) $(TDIRS) 42 | cp $< $@ 43 | 44 | clean: 45 | -------------------------------------------------------------------------------- /fal/tests/utests/tc/common/tc_config.h: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #ifndef HW_CONFIG_H 5 | #define HW_CONFIG_H 6 | 7 | #include 8 | 9 | #if AIE_GEN == 2 10 | 11 | #define HW_GEN XAIE_DEV_GEN_AIEML 12 | #define XAIE_NUM_ROWS 8 13 | #define XAIE_NUM_COLS 50 14 | #define XAIE_ADDR_ARRAY_OFF 0x800 15 | 16 | #define XAIE_BASE_ADDR 0x20000000000 17 | #define XAIE_COL_SHIFT 25 18 | #define XAIE_ROW_SHIFT 20 19 | #define XAIE_SHIM_ROW 0 20 | #define XAIE_MEM_TILE_ROW_START 1 21 | #define XAIE_MEM_TILE_NUM_ROWS 2 22 | #define XAIE_AIE_TILE_ROW_START 3 23 | #define XAIE_AIE_TILE_NUM_ROWS 8 24 | 25 | #elif AIE_GEN == 1 26 | 27 | #define HW_GEN XAIE_DEV_GEN_AIE 28 | #define XAIE_NUM_ROWS 9 29 | #define XAIE_NUM_COLS 50 30 | #define XAIE_ADDR_ARRAY_OFF 0x800 31 | 32 | #define XAIE_BASE_ADDR 0x20000000000 33 | #define XAIE_COL_SHIFT 23 34 | #define XAIE_ROW_SHIFT 18 35 | #define XAIE_SHIM_ROW 0 36 | #define XAIE_MEM_TILE_ROW_START 0 37 | #define XAIE_MEM_TILE_NUM_ROWS 0 38 | #define XAIE_AIE_TILE_ROW_START 1 39 | #define XAIE_AIE_TILE_NUM_ROWS 8 40 | 41 | #endif 42 | 43 | #endif /* HW_CONFIG_H */ 44 | -------------------------------------------------------------------------------- /driver/src/io_backend/ext/xaie_io_common.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_common.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations that are common accross multiple backends. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   01/20/2021 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_COMMON_H 25 | #define XAIE_IO_COMMON_H 26 | 27 | static inline u64 XAie_IODummyGetTid(void) 28 | { 29 | return 0; 30 | } 31 | 32 | static inline int XAie_IODummyGetPartFd(void *IOInst) 33 | { 34 | (void)IOInst; 35 | return -1; 36 | } 37 | 38 | 39 | void _XAie_IOCommon_MarkTilesInUse(XAie_DevInst *DevInst, 40 | XAie_BackendTilesArray *Args); 41 | 42 | #endif /* XAIE_IO_COMMON_H */ 43 | 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/tests/utest/test_timer_aie.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN == 1 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(TimerApis_Aie) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(TimerApis_Aie, InvalidArgs) 37 | { 38 | AieRC RC; 39 | 40 | RC = XAie_SetTimerResetEvent(&DevInst, XAie_TileLoc(8, 3), XAIE_MEM_MOD, 41 | XAIE_EVENT_GROUP_0_CORE, XAIE_RESETENABLE); 42 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 43 | 44 | RC = XAie_SetTimerResetEvent(&DevInst, XAie_TileLoc(5, 4), 45 | XAIE_CORE_MOD, XAIE_EVENT_GROUP_0_MEM, 46 | XAIE_RESETENABLE); 47 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 48 | } 49 | 50 | #endif /* AIE_GEN == 1 */ 51 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aie2p.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aie. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Keerthanna   01/25/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIE2PS_H 24 | #define XAIE_DEVICE_AIE2PS_H 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAie2PS_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAie2PS_SetAxiMMIsolation(XAie_DevInst* DevInst, u8 IsolationFlags); 30 | AieRC _XAie2PS_SetColumnClk(XAie_DevInst *DevInst, XAie_BackendColumnReq *Args); 31 | 32 | #endif /* XAIE_DEVICE_AIE2P */ 33 | /** @} */ 34 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_clock.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_clock.h 10 | * @{ 11 | * 12 | * Header file for timer implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date        Changes
18 | * ----- ------   --------    --------------------------------------------------
19 | * 1.0   Dishita  06/26/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_CLOCK_H 24 | #define XAIE_CLOCK_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Enum *********************************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | AieRC XAie_PmRequestTiles(XAie_DevInst *DevInst, XAie_LocType *Loc, 33 | u32 NumTiles); 34 | AieRC XAie_PmSetColumnClk(XAie_DevInst *DevInst, u32 StartCol, 35 | u32 NumCols, u8 Enable); 36 | #endif /* end of protection macro */ 37 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_ecc.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ecc.h 10 | * @{ 11 | * 12 | * Header file for ecc implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date        Changes
18 | * ----- ------   --------    --------------------------------------------------
19 | * 1.0   Dishita  08/10/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_ECC_H 24 | #define XAIE_ECC_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Enum *********************************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | void _XAie_EccEvntResetPM(XAie_DevInst *DevInst, XAie_LocType Loc); 33 | AieRC _XAie_EccOnPM(XAie_DevInst *DevInst, XAie_LocType Loc); 34 | AieRC _XAie_EccOnDM(XAie_DevInst *DevInst, XAie_LocType Loc); 35 | #endif /* end of protection macro */ 36 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie.h: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_ss_aie.h 11 | * @{ 12 | * 13 | * This file contains internal api implementations for AIE stream switch. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who         Date        Changes
19 | * ----- ---------   ----------  -----------------------------------------------
20 | * 1.0   Siddharth   12/09/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_SS_AIE_H 25 | #define XAIE_SS_AIE_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaie_helper.h" 29 | 30 | /************************** Constant Definitions *****************************/ 31 | 32 | /************************** Function Prototypes ******************************/ 33 | 34 | AieRC _XAie_StrmSwCheckPortValidity(StrmSwPortType Slave, u8 SlvPortNum, 35 | StrmSwPortType Master, u8 MstrPortNum); 36 | 37 | #endif /* XAIE_SS_AIE_H */ 38 | /** @} */ 39 | -------------------------------------------------------------------------------- /driver/src/util/xaie_util_events.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. * 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_util_events.h 11 | * @{ 12 | * 13 | * Header to include function prototypes for AIE utilities 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Gregory 03/31/2022  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_UTIL_EVENTS_H 25 | #define XAIE_UTIL_EVENTS_H 26 | 27 | #include "xaie_feature_config.h" 28 | #ifdef XAIE_FEATURE_UTIL_ENABLE 29 | 30 | /***************************** Include Files *********************************/ 31 | #include "xaie_events.h" 32 | 33 | /**************************** Function Prototypes *******************************/ 34 | const char* XAie_EventGetString(XAie_Events Event); 35 | #endif /* XAIE_FEATURE_UTIL_ENABLE */ 36 | 37 | #endif /* end of protection macro */ 38 | 39 | /** @} */ 40 | -------------------------------------------------------------------------------- /driver/src/Makefile.rsc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | CROSSCOMPILE ?= 8 | RSCMETA ?= aie_rsc_meta.bin 9 | GEN_RSCMETA ?= gen_aie_rsc_meta.bin 10 | 11 | # use objcopy instead of ld is to make sure the AI engine resource meta data 12 | # is linked as read only data 13 | OBJCOPY = $(CROSSCOMPILE)objcopy 14 | OBJ = $(subst .bin,.o,$(GEN_RSCMETA)) 15 | 16 | OUTFMT=elf64-x86-64 17 | OUTARCH=i386 18 | ifneq (,$(findstring aarch64,$(CROSSCOMPILE))) 19 | OUTFMT=elf64-littleaarch64 20 | OUTARCH=aarch64 21 | endif 22 | ifneq (,$(findstring armr5,$(CROSSCOMPILE))) 23 | OUTFMT=elf32-littlearm 24 | OUTARCH=arm 25 | endif 26 | ifneq (,$(findstring mb-,$(CROSSCOMPILE))) 27 | OUTFMT=elf32-microblazeel 28 | OUTARCH=microblazeel 29 | endif 30 | ifneq (,$(findstring microblaze,$(CROSSCOMPILE))) 31 | OUTFMT=elf32-microblazeel 32 | OUTARCH=microblazeel 33 | endif 34 | 35 | all: addrsc 36 | 37 | addrsc: $(OBJ) 38 | 39 | $(OBJ): $(GEN_RSCMETA) 40 | $(OBJCOPY) -I binary -O $(OUTFMT) -B $(OUTARCH) --rename-section .data=.rodata,alloc,load,readonly,data,contents $< $@ 41 | 42 | $(GEN_RSCMETA): $(RSCMETA) 43 | cp $< $@ 44 | 45 | clean: 46 | rm -f $(OBJ) $(GEN_RSCMETA) 47 | 48 | .PHONY: all addrsc 49 | -------------------------------------------------------------------------------- /driver/src/util/btree4.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2024 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | #ifndef _BTREE4_H_ 7 | #define _BTREE4_H_ 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | /* [data0, data1, data2] 15 | * / | | \ 16 | * c0 c1 c2 c3 17 | * 18 | * c0-c3: child nodes child[0] to child[3]. 19 | */ 20 | 21 | #define BTREE4_DATA_NUM 3 22 | #define BTREE4_CHILD_NUM (BTREE4_DATA_NUM + 1) 23 | 24 | struct btree4_node { 25 | void *data[BTREE4_DATA_NUM]; 26 | struct btree4_node *child[BTREE4_CHILD_NUM]; 27 | struct btree4_node *parent; 28 | }; 29 | 30 | struct btree4 { 31 | struct btree4_node *root; 32 | int (*cmp)(void *a, void *b); 33 | }; 34 | 35 | #define BTREE4_DECLARE(name, cmp) struct btree4 name = {.root = NULL, .cmp = cmp} 36 | #define BTREE4_INIT(ptr, compare) {(ptr)->root = NULL; (ptr)->cmp = compare;} 37 | 38 | void btree4_inorder_visit(struct btree4 *tree, 39 | void (*visit)(void *data, void *priv), 40 | void *priv); 41 | 42 | int btree4_insert(struct btree4 *tree, void *data); 43 | 44 | void *btree4_search(struct btree4 *tree, void *data); 45 | void *btree4_delete(struct btree4 *tree, void *data); 46 | 47 | #endif /* _BTREE4_H_ */ 48 | -------------------------------------------------------------------------------- /driver/tests/utest/test_events_aieml.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN >= 2 5 | 6 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 7 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 8 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 9 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 10 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 11 | 12 | static XAie_InstDeclare(DevInst, &ConfigPtr); 13 | 14 | TEST_GROUP(EventApis_AieMl) 15 | { 16 | void setup() 17 | { 18 | AieRC RC; 19 | 20 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 21 | CHECK_EQUAL(XAIE_OK, RC); 22 | 23 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 24 | CHECK_EQUAL(XAIE_OK, RC); 25 | } 26 | void teardown() 27 | { 28 | AieRC RC; 29 | 30 | RC = XAie_PartitionTeardown(&(DevInst)); 31 | CHECK_EQUAL(XAIE_OK, RC); 32 | 33 | XAie_Finish(&DevInst); 34 | } 35 | }; 36 | 37 | TEST(EventApis_AieMl, Errors) 38 | { 39 | AieRC RC; 40 | 41 | XAie_LocType TileLoc = XAie_TileLoc(5, 4); 42 | 43 | RC = XAie_EventGenerate(&DevInst, TileLoc, XAIE_CORE_MOD, 44 | XAIE_EVENT_EDGE_DETECTION_EVENT_0_CORE); 45 | CHECK_EQUAL(XAIE_OK, RC); 46 | 47 | RC = XAie_EventComboConfig(&DevInst, TileLoc, XAIE_CORE_MOD, 48 | XAIE_EVENT_COMBO0, XAIE_EVENT_COMBO_E1_AND_E2, 49 | XAIE_EVENT_EDGE_DETECTION_EVENT_0_CORE, 50 | XAIE_EVENT_FP_OVERFLOW_CORE); 51 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 52 | } 53 | 54 | #endif /* AIE_GEN >= 2 */ 55 | -------------------------------------------------------------------------------- /cmake/Findcommon.cmake: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. 2 | # SPDX-License-Identifier: MIT 3 | 4 | option(YOCTO "Yocto based embeddedsw FLOW" OFF) 5 | set(CMAKE_POLICY_DEFAULT_CMP0140 OLD) 6 | 7 | if (YOCTO) 8 | find_package(commonmeta QUIET) 9 | endif() 10 | 11 | set (CMAKE_INSTALL_LIBDIR "lib") 12 | function (collector_create name base) 13 | set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST") 14 | set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}") 15 | endfunction (collector_create) 16 | 17 | function (collector_list var name) 18 | get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST") 19 | set (${var} "${_list}" PARENT_SCOPE) 20 | endfunction (collector_list) 21 | 22 | function (collector_base var name) 23 | get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE") 24 | set (${var} "${_base}" PARENT_SCOPE) 25 | endfunction (collector_base) 26 | 27 | function (collect name) 28 | collector_base (_base ${name}) 29 | string(COMPARE NOTEQUAL "${_base}" "" _is_rel) 30 | set (_list) 31 | foreach (s IN LISTS ARGN) 32 | if (_is_rel) 33 | get_filename_component (s "${s}" ABSOLUTE) 34 | file (RELATIVE_PATH s "${_base}" "${s}") 35 | endif (_is_rel) 36 | list (APPEND _list "${s}") 37 | endforeach () 38 | set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}") 39 | endfunction (collect) 40 | 41 | string(ASCII 27 Esc) 42 | set(ColourReset "${Esc}[m") 43 | set(BoldRed "${Esc}[1;31m") 44 | set(BoldYellow "${Esc}[1;33m") 45 | -------------------------------------------------------------------------------- /driver/cmake/collect.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | function (collector_create name base) 7 | set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST") 8 | set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}") 9 | endfunction (collector_create) 10 | 11 | function (collector_list var name) 12 | get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST") 13 | set (${var} "${_list}" PARENT_SCOPE) 14 | endfunction (collector_list) 15 | 16 | function (collector_base var name) 17 | get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE") 18 | set (${var} "${_base}" PARENT_SCOPE) 19 | endfunction (collector_base) 20 | 21 | function (collect name) 22 | collector_base (_base ${name}) 23 | string(COMPARE NOTEQUAL "${_base}" "" _is_rel) 24 | set (_list) 25 | foreach (s IN LISTS ARGN) 26 | if (_is_rel) 27 | get_filename_component (s "${s}" ABSOLUTE) 28 | file (RELATIVE_PATH s "${_base}" "${s}") 29 | endif (_is_rel) 30 | list (APPEND _list "${s}") 31 | endforeach () 32 | set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}") 33 | endfunction (collect) 34 | 35 | # Create global collectors 36 | collector_create (PROJECT_INC_DIRS "") 37 | collector_create (PROJECT_LIB_DIRS "") 38 | collector_create (PROJECT_LIB_DEPS "") 39 | -------------------------------------------------------------------------------- /fal/cmake/collect.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | function (collector_create name base) 8 | set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST") 9 | set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}") 10 | endfunction (collector_create) 11 | 12 | function (collector_list var name) 13 | get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST") 14 | set (${var} "${_list}" PARENT_SCOPE) 15 | endfunction (collector_list) 16 | 17 | function (collector_base var name) 18 | get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE") 19 | set (${var} "${_base}" PARENT_SCOPE) 20 | endfunction (collector_base) 21 | 22 | function (collect name) 23 | collector_base (_base ${name}) 24 | string(COMPARE NOTEQUAL "${_base}" "" _is_rel) 25 | set (_list) 26 | foreach (s IN LISTS ARGN) 27 | if (_is_rel) 28 | get_filename_component (s "${s}" ABSOLUTE) 29 | file (RELATIVE_PATH s "${_base}" "${s}") 30 | endif (_is_rel) 31 | list (APPEND _list "${s}") 32 | endforeach () 33 | set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}") 34 | endfunction (collect) 35 | 36 | # Create global collectors 37 | collector_create (PROJECT_INC_DIRS "") 38 | collector_create (PROJECT_LIB_DIRS "") 39 | collector_create (PROJECT_LIB_DEPS "") 40 | 41 | # vim: expandtab:ts=2:sw=2:smartindent 42 | -------------------------------------------------------------------------------- /driver/src/core/xaie_uc.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_uc.h 10 | * @{ 11 | * 12 | * Header file for core uc loader functions 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Kishan  12/23/2022  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIEUCLOADER_H 24 | #define XAIEUCLOADER_H 25 | 26 | #include "xaie_feature_config.h" 27 | #ifdef XAIE_FEATURE_UC_ENABLE 28 | 29 | /***************************** Include Files *********************************/ 30 | #include "xaiegbl.h" 31 | #include "xaiegbl_regdef.h" 32 | 33 | /************************** Function Prototypes *****************************/ 34 | 35 | AieRC _XAie_UcCoreWakeup(XAie_DevInst *DevInst, XAie_LocType Loc, 36 | const struct XAie_UcMod *UcMod); 37 | AieRC _XAie_UcCoreSleep(XAie_DevInst *DevInst, XAie_LocType Loc, 38 | const struct XAie_UcMod *UcMod); 39 | AieRC _XAie_UcCoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 40 | u32 *CoreStatus, const struct XAie_UcMod *UcMod); 41 | 42 | #endif /* XAIE_FEATURE_UC_ENABLE */ 43 | 44 | #endif /* end of protection macro */ 45 | /** @} */ 46 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_tilectrl.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_tilectrl.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Wendy   05/27/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_TILECTRL_H 24 | #define XAIE_TILECTRL_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | /**************************** Type Definitions *******************************/ 29 | /***************************** Macro Definitions *****************************/ 30 | 31 | #define XAIE_ISOLATE_EAST_MASK (1U << 3) 32 | #define XAIE_ISOLATE_NORTH_MASK (1U << 2) 33 | #define XAIE_ISOLATE_WEST_MASK (1U << 1) 34 | #define XAIE_ISOLATE_SOUTH_MASK (1U << 0) 35 | #define XAIE_ISOLATE_ALL_MASK ((1U << 4) - 1) 36 | 37 | /************************** Function Prototypes *****************************/ 38 | AieRC _XAie_TileCtrlSetIsolation(XAie_DevInst *DevInst, XAie_LocType Loc, 39 | u8 Dir); 40 | 41 | #endif /* end of protection macro */ 42 | -------------------------------------------------------------------------------- /driver/tests/utest/test_timer_aieml.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN >= 2 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(TimerApis_AieMl) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(TimerApis_AieMl, TimerMemTile) 37 | { 38 | AieRC RC; 39 | 40 | RC = XAie_SetTimerResetEvent(&DevInst, XAie_TileLoc(8, 1), XAIE_MEM_MOD, 41 | XAIE_EVENT_TRUE_MEM_TILE, XAIE_RESETENABLE); 42 | CHECK_EQUAL(XAIE_OK, RC); 43 | } 44 | 45 | TEST(TimerApis_AieMl, InvalidArgs) 46 | { 47 | AieRC RC; 48 | 49 | RC = XAie_SetTimerResetEvent(&DevInst, XAie_TileLoc(8, 3), XAIE_MEM_MOD, 50 | XAIE_EVENT_FP_OVERFLOW_CORE, XAIE_RESETENABLE); 51 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 52 | 53 | RC = XAie_SetTimerResetEvent(&DevInst, XAie_TileLoc(5, 4), 54 | XAIE_CORE_MOD, XAIE_EVENT_FP_OVERFLOW_CORE, 55 | XAIE_RESETENABLE); 56 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 57 | } 58 | 59 | #endif /* AIE_GEN >= 2 */ 60 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aie.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aie. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   05/03/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIE 24 | #define XAIE_DEVICE_AIE 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAie_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAie_SetPartColShimReset(XAie_DevInst *DevInst, u8 Enable); 30 | AieRC _XAie_SetPartColClockAfterRst(XAie_DevInst *DevInst, u8 Enable); 31 | AieRC _XAie_SetPartIsolationAfterRst(XAie_DevInst *DevInst, u8 ClearIsolation); 32 | AieRC _XAie_PartMemZeroInit(XAie_DevInst *DevInst); 33 | AieRC _XAie_RequestTiles(XAie_DevInst *DevInst, XAie_BackendTilesArray *Args); 34 | AieRC _XAie_SetColumnClk(XAie_DevInst *DevInst, XAie_BackendColumnReq *Args); 35 | 36 | #endif /* XAIE_DEVICE_AIE */ 37 | /** @} */ 38 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aie2ps.h 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who	 Date	Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Sankarji   06/15/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_SS_AIE2PS_H 24 | #define XAIE_SS_AIE2PS_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_helper.h" 28 | 29 | /************************** Constant Definitions *****************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | 33 | AieRC _XAie2PS_AieTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 34 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 35 | AieRC _XAie2PS_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 36 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 37 | AieRC _XAie2PS_ShimTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 38 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 39 | 40 | #endif /* XAIE_SS_AIE2PS_H */ 41 | /** @} */ 42 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aieml.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aieml. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   05/03/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIEML 24 | #define XAIE_DEVICE_AIEML 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAieMl_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAieMl_SetPartColShimReset(XAie_DevInst *DevInst, u8 Enable); 30 | AieRC _XAieMl_SetPartColClockAfterRst(XAie_DevInst *DevInst, u8 Enable); 31 | AieRC _XAieMl_SetPartIsolationAfterRst(XAie_DevInst *DevInst, u8 ClearIsolation); 32 | AieRC _XAieMl_PartMemZeroInit(XAie_DevInst *DevInst); 33 | AieRC _XAieMl_RequestTiles(XAie_DevInst *DevInst, XAie_BackendTilesArray *Args); 34 | AieRC _XAieMl_SetColumnClk(XAie_DevInst *DevInst, XAie_BackendColumnReq *Args); 35 | 36 | #endif /* XAIE_DEVICE_AIEML */ 37 | /** @} */ 38 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   03/17/2020  Initial creation
20 | * 1.1   Tejus   03/23/2020  Include xaiegbl header file
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_H 25 | #define XAIELOCKS_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | /**************************** Type Definitions *******************************/ 31 | /************************** Function Prototypes *****************************/ 32 | AieRC XAie_LockAcquire(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 33 | u32 TimeOut); 34 | AieRC XAie_LockRelease(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 35 | u32 TimeOut); 36 | AieRC XAie_LockSetValue(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | XAie_Lock Lock); 38 | AieRC XAie_LockGetValue(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 39 | u32 *LockValue); 40 | #endif /* end of protection macro */ 41 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aieml.h 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who         Date        Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Siddharth   12/09/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_SS_AIEML_H 24 | #define XAIE_SS_AIEML_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_helper.h" 28 | 29 | /************************** Constant Definitions *****************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | 33 | AieRC _XAieMl_AieTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 34 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 35 | AieRC _XAieMl_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 36 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 37 | AieRC _XAieMl_ShimTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 38 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 39 | 40 | #endif /* XAIE_SS_AIEML_H */ 41 | /** @} */ 42 | -------------------------------------------------------------------------------- /driver/src/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | COMPILER= 8 | ARCHIVER= 9 | CP=cp 10 | COMPILER_FLAGS = 11 | EXTRA_COMPILER_FLAGS= 12 | EXTRA_ARCHIVE_FLAGS=rc 13 | LIB=libxil.a 14 | 15 | RELEASEDIR=../../../lib 16 | INCLUDEDIR=../../../include 17 | INCLUDES=-I./. -I${INCLUDEDIR} -I${INCLUDEDIR}/xaiengine 18 | EXTRA_CFLAGS= 19 | 20 | AIEBACKEND ?= BAREMETAL 21 | EXTRA_CFLAGS += -D__AIE$(AIEBACKEND)__ 22 | ifdef XAIE_DEV_SINGLE_GEN 23 | EXTRA_CFLAGS += -DXAIE_DEV_SINGLE_GEN=$(XAIE_DEV_SINGLE_GEN) 24 | endif 25 | 26 | XAIE_DIR = . 27 | OUTS = *.o 28 | OBJECTS = $(addsuffix .o, $(basename $(wildcard ./*/*.c) $(wildcard ./*/*/*.c))) 29 | XAIE_SRCS := $(filter-out $(XAIE_SRCS_EXCLUDE), $(wildcard ./*/*.c) $(wildcard ./*/*/*.c)) 30 | XAIE_OBJS = $(addprefix $(XAIE_DIR)/, $(XAIE_SRCS:%.c=%.o)) 31 | 32 | INCLUDEFILES= $(wildcard ./*/*.h) $(wildcard ./*/*/*.h) 33 | 34 | libs: xaie 35 | 36 | xaie: print_msg_xaie $(XAIE_OBJS) 37 | $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${XAIE_OBJS} 38 | 39 | print_msg_xaie: 40 | @echo "Compiling xaie" 41 | 42 | .PHONY: include 43 | include: xaie_includes 44 | 45 | xaie_includes: 46 | ${CP} xaiengine.h ${INCLUDEDIR} 47 | ${CP} ${INCLUDEFILES} ${INCLUDEDIR}/xaiengine 48 | 49 | clean: 50 | rm -rf $(XAIE_DIR)/${OBJECTS} 51 | rm -rf ${RELEASEDIR}/${LIB} 52 | 53 | $(XAIE_DIR)/%.o: $(XAIE_DIR)/%.c $(INCLUDEFILES) 54 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_CFLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@ 55 | -------------------------------------------------------------------------------- /fal/src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | if(NOT ${YOCTO}) 8 | add_library(aiefal INTERFACE) 9 | 10 | include_directories(${CMAKE_BINARY_DIR}/include/xaiefal) 11 | 12 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/common DESTINATION 13 | ${CMAKE_BINARY_DIR}/include/xaiefal) 14 | 15 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/profile DESTINATION 16 | ${CMAKE_BINARY_DIR}/include/xaiefal) 17 | 18 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/rsc DESTINATION 19 | ${CMAKE_BINARY_DIR}/include/xaiefal) 20 | 21 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/xaiefal.hpp DESTINATION 22 | ${CMAKE_BINARY_DIR}/include/xaiefal) 23 | else() 24 | file(GLOB_RECURSE _sources *.cpp) 25 | file(GLOB_RECURSE _headers *.hpp) 26 | 27 | set (_dest_inc_dir ${CMAKE_CURRENT_BINARY_DIR}/include) 28 | 29 | foreach (hf ${_headers}) 30 | get_filename_component(f "${hf}" NAME) 31 | get_filename_component(d "${hf}" DIRECTORY) 32 | get_filename_component(d "${d}" NAME) 33 | if ("${d}" STREQUAL "src") 34 | set (d "") 35 | endif() 36 | 37 | configure_file ("./${d}/${f}" include/${PROJECT_NAME}/${d}/${f} @ONLY) 38 | install (FILES ${_dest_inc_dir}/${PROJECT_NAME}/${d}/${f} 39 | DESTINATION include RENAME ${PROJECT_NAME}/${d}/${f}) 40 | endforeach (hf) 41 | 42 | collect (PROJECT_LIB_DIRS "${CMAKE_CURRENT_BINARY_DIR}") 43 | collect (PROJECT_INC_DIRS "${CMAKE_CURRENT_BINARY_DIR}/include") 44 | 45 | endif() 46 | 47 | # vim: expandtab:ts=2:sw=2:smartindent 48 | -------------------------------------------------------------------------------- /driver/src/common/xaie_txn.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_txn.h 10 | * @{ 11 | * 12 | * This file contains data structure for TxN flow 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Keyur   08/25/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIETXN_H 24 | #define XAIETXN_H 25 | 26 | /***************************** Include Files *********************************/ 27 | /* All New custom Ops should be added above XAIE_IO_CUSTOM_OP_NEXT 28 | * To support backward compatibility existing enums should not be 29 | * modified. */ 30 | typedef enum { 31 | XAIE_IO_WRITE, 32 | XAIE_IO_BLOCKWRITE, 33 | XAIE_IO_BLOCKSET, 34 | XAIE_IO_MASKWRITE, 35 | XAIE_IO_MASKPOLL, 36 | XAIE_CONFIG_SHIMDMA_BD, 37 | XAIE_CONFIG_SHIMDMA_DMABUF_BD, 38 | XAIE_IO_CUSTOM_OP_BEGIN = 1U<<7U, 39 | XAIE_IO_CUSTOM_OP_TCT = XAIE_IO_CUSTOM_OP_BEGIN, 40 | XAIE_IO_CUSTOM_OP_DDR_PATCH, 41 | XAIE_IO_CUSTOM_OP_NEXT, 42 | XAIE_IO_CUSTOM_OP_MAX = UCHAR_MAX, 43 | } XAie_TxnOpcode; 44 | 45 | struct XAie_TxnCmd { 46 | XAie_TxnOpcode Opcode; 47 | u32 Mask; 48 | u64 RegOff; 49 | u32 Value; 50 | u64 DataPtr; 51 | u32 Size; 52 | }; 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /fal/examples/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | collector_list (_list PROJECT_INC_DIRS) 8 | include_directories (${_list} ${CMAKE_CURRENT_SOURCE_DIR}) 9 | 10 | collector_list (_list PROJECT_LIB_DIRS) 11 | link_directories (${_list}) 12 | 13 | collector_list (_deps PROJECT_LIB_DEPS) 14 | 15 | get_property (_ec_flags GLOBAL PROPERTY "PROJECT_EC_FLAGS") 16 | message ("_ec_flags = ${_ec_flags}") 17 | 18 | set (_apps profile-aie) 19 | list(APPEND _apps profile-io-aie) 20 | list(APPEND _apps trace-pc-aie) 21 | 22 | foreach (_app ${_apps}) 23 | set (_src ${CMAKE_CURRENT_SOURCE_DIR}/${_app}.cpp) 24 | if (WITH_SHARED_LIB) 25 | add_executable (${_app}-share ${_src}) 26 | set_target_properties(${_app}-share PROPERTIES CXX_STANDARD 11) 27 | target_compile_options (${_app}-share PUBLIC ${_ec_flags}) 28 | target_link_libraries (${_app}-share ${_ec_flags} ${_deps}) 29 | install (TARGETS ${_app}-share RUNTIME DESTINATION bin) 30 | endif (WITH_SHARED_LIB) 31 | 32 | if (WITH_STATIC_LIB) 33 | if (${PROJECT_SYSTEM} STREQUAL "linux") 34 | add_executable (${_app}-static ${_src}) 35 | set_target_properties(${_app}-static PROPERTIES CXX_STANDARD 11) 36 | target_compile_options (${_app}-static PUBLIC ${_ec_flags}) 37 | target_link_libraries (${_app}-static ${_ec_flags} ${_deps}) 38 | install (TARGETS ${_app}-static RUNTIME DESTINATION bin) 39 | endif (${PROJECT_SYSTEM} STREQUAL "linux") 40 | endif (WITH_STATIC_LIB) 41 | endforeach (_app) 42 | -------------------------------------------------------------------------------- /driver/src/core/xaie_core_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_core_aie.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for aie core apis. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/02/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIECORE_AIE_H 24 | #define XAIECORE_AIE_H 25 | /***************************** Include Files *********************************/ 26 | #include "xaie_helper.h" 27 | /************************** Function Prototypes *****************************/ 28 | AieRC _XAie_CoreConfigureDone(XAie_DevInst *DevInst, XAie_LocType Loc, 29 | const struct XAie_CoreMod *CoreMod); 30 | AieRC _XAie_CoreEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 31 | const struct XAie_CoreMod *CoreMod); 32 | AieRC _XAie_CoreWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 33 | u32 TimeOut, const struct XAie_CoreMod *CoreMod); 34 | AieRC _XAie_CoreReadDoneBit(XAie_DevInst *DevInst, XAie_LocType Loc, 35 | u8 *DoneBit, const struct XAie_CoreMod *CoreMod); 36 | AieRC _XAie_CoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | u32 *CoreStatus, const struct XAie_CoreMod *CoreMod); 38 | 39 | #endif /* XAIECORE_AIE_H */ 40 | /** @} */ 41 | -------------------------------------------------------------------------------- /.githooks/pre-commit: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Determine if this is an amend operation 4 | IS_AMEND=$(ps -ocommand= -p $PPID | grep -e '--amend'); 5 | 6 | if [ -n "$IS_AMEND" ]; then 7 | echo "You are ammending patch, version file already updated with parent git hash" 8 | exit 0 9 | fi 10 | 11 | # For regular commits, get the current HEAD 12 | GIT_PARENT_HASH=$(git rev-parse HEAD 2>/dev/null || echo "unknown") 13 | GIT_BRANCH=$(git rev-parse --abbrev-ref HEAD 2>/dev/null || echo "unknown") 14 | 15 | # Define the file to update 16 | FILE_TO_UPDATE="driver/src/global/xaie_version.h" 17 | 18 | # Check if the file exists, create it with a default template if it doesn't 19 | if [ ! -f "$FILE_TO_UPDATE" ]; then 20 | mkdir -p "$(dirname "$FILE_TO_UPDATE")" 21 | cat > "$FILE_TO_UPDATE" << EOL 22 | #ifndef VERSION_H 23 | #define VERSION_H 24 | 25 | #define GIT_PARENT_HASH "unknown" 26 | #define GIT_BRANCH "unknown" 27 | 28 | #endif // VERSION_H 29 | EOL 30 | fi 31 | 32 | # Update the macros in version.h 33 | sed -i 's/#define[[:space:]]\+GIT_PARENT_HASH[[:space:]]\+".*"/#define GIT_PARENT_HASH "'"$GIT_PARENT_HASH"'"/g' "$FILE_TO_UPDATE" 34 | sed -i 's/#define[[:space:]]\+GIT_BRANCH[[:space:]]\+".*"/#define GIT_BRANCH "'"$GIT_BRANCH"'"/g' "$FILE_TO_UPDATE" 35 | 36 | # Verify the file was updated correctly 37 | if grep -q "#define GIT_PARENT_HASH \"$GIT_PARENT_HASH\"" "$FILE_TO_UPDATE" && \ 38 | grep -q "#define GIT_BRANCH \"$GIT_BRANCH\"" "$FILE_TO_UPDATE"; then 39 | # Stage the updated file 40 | git add "$FILE_TO_UPDATE" 41 | echo "Updated $FILE_TO_UPDATE with Git hash $GIT_PARENT_HASH and branch $GIT_BRANCH." 42 | else 43 | echo "Error: Failed to update $FILE_TO_UPDATE with Git metadata." 44 | exit 1 45 | fi 46 | 47 | exit 0 48 | -------------------------------------------------------------------------------- /driver/src/core/xaie_core_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_core_aieml.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for aie-ml core apis. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/02/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIECORE_AIEML_H 24 | #define XAIECORE_AIEML_H 25 | /***************************** Include Files *********************************/ 26 | #include "xaie_helper.h" 27 | /************************** Function Prototypes *****************************/ 28 | AieRC _XAieMl_CoreConfigureDone(XAie_DevInst *DevInst, XAie_LocType Loc, 29 | const struct XAie_CoreMod *CoreMod); 30 | AieRC _XAieMl_CoreEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 31 | const struct XAie_CoreMod *CoreMod); 32 | AieRC _XAieMl_CoreWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 33 | u32 TimeOut, const struct XAie_CoreMod *CoreMod); 34 | AieRC _XAieMl_CoreReadDoneBit(XAie_DevInst *DevInst, XAie_LocType Loc, 35 | u8 *DoneBit, const struct XAie_CoreMod *CoreMod); 36 | AieRC _XAieMl_CoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | u32 *CoreStatus, const struct XAie_CoreMod *CoreMod); 38 | 39 | #endif /* XAIECORE_AIEML_H */ 40 | /** @} */ 41 | -------------------------------------------------------------------------------- /fal/src/common/xaiefal-log.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include 5 | #include 6 | 7 | #pragma once 8 | 9 | namespace xaiefal { 10 | enum class LogLevel { 11 | FAL_DEBUG, 12 | FAL_INFO, 13 | FAL_WARN, 14 | FAL_ERROR, 15 | FAL_MAX, 16 | }; 17 | 18 | class Logger 19 | { 20 | private: 21 | Logger() : Level(LogLevel::FAL_INFO) {} 22 | public: 23 | LogLevel Level; 24 | std::ofstream of; 25 | std::ofstream ofnull; 26 | 27 | ~Logger() {} 28 | 29 | void setLogLevel(LogLevel Lvl) { 30 | Level = Lvl; 31 | } 32 | 33 | LogLevel getLogLevel() { 34 | return Level; 35 | } 36 | 37 | void setLogFile(const std::string& File) { 38 | of.open(File); 39 | } 40 | 41 | Logger(const Logger&) = delete; 42 | Logger& operator=(const Logger &) = delete; 43 | Logger(Logger &&) = delete; 44 | Logger & operator=(Logger &&) = delete; 45 | static Logger &get() { 46 | static Logger logger; 47 | 48 | return logger; 49 | } 50 | static std::ostream &log(LogLevel Lvl=LogLevel::FAL_MAX) { 51 | const char* label; 52 | 53 | switch(Lvl) { 54 | case LogLevel::FAL_DEBUG: label = "XAIEFAL: DEBUG: "; break; 55 | case LogLevel::FAL_INFO: label = "XAIEFAL: INFO: "; break; 56 | case LogLevel::FAL_WARN: label = "XAIEFAL: WARN: "; break; 57 | case LogLevel::FAL_ERROR: label = "XAIEFAL: ERROR: "; break; 58 | default: label = ""; break; 59 | } 60 | 61 | if (get().Level <= Lvl) { 62 | if (get().of.rdbuf()->is_open()) { 63 | get().of << label; 64 | return get().of; 65 | } else { 66 | std::cout << label; 67 | return std::cout; 68 | } 69 | } else { 70 | return get().ofnull; 71 | } 72 | } 73 | 74 | }; 75 | } 76 | -------------------------------------------------------------------------------- /driver/tests/utest/test_events_aie.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN == 1 5 | 6 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 7 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 8 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 9 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 10 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 11 | 12 | static XAie_InstDeclare(DevInst, &ConfigPtr); 13 | 14 | TEST_GROUP(EventApis_Aie) 15 | { 16 | void setup() 17 | { 18 | AieRC RC; 19 | 20 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 21 | CHECK_EQUAL(XAIE_OK, RC); 22 | 23 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 24 | CHECK_EQUAL(XAIE_OK, RC); 25 | } 26 | 27 | void teardown() 28 | { 29 | AieRC RC; 30 | 31 | RC = XAie_PartitionTeardown(&(DevInst)); 32 | CHECK_EQUAL(XAIE_OK, RC); 33 | 34 | XAie_Finish(&DevInst); 35 | } 36 | }; 37 | 38 | TEST(EventApis_Aie, Errors) 39 | { 40 | AieRC RC; 41 | 42 | XAie_LocType TileLoc = XAie_TileLoc(5, 4); 43 | 44 | RC = XAie_EventGenerate(&DevInst, TileLoc, XAIE_CORE_MOD, 45 | XAIE_EVENT_GROUP_0_MEM); 46 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 47 | 48 | RC = XAie_EventComboConfig(&DevInst, TileLoc, XAIE_CORE_MOD, 49 | XAIE_EVENT_COMBO0, XAIE_EVENT_COMBO_E1_AND_E2, 50 | XAIE_EVENT_COMBO_EVENT_0_CORE, 51 | XAIE_EVENT_GROUP_0_MEM); 52 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 53 | 54 | RC = XAie_EventBroadcast(&DevInst, TileLoc, XAIE_CORE_MOD, 1, 55 | XAIE_EVENT_GROUP_0_MEM); 56 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 57 | 58 | RC = XAie_EventComboConfig(&DevInst, TileLoc, XAIE_CORE_MOD, 59 | XAIE_EVENT_COMBO0, XAIE_EVENT_COMBO_E1_AND_E2, 60 | XAIE_EVENT_GROUP_0_MEM, 61 | XAIE_EVENT_FP_OVERFLOW_CORE); 62 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 63 | } 64 | 65 | #endif /* AIE_GEN == 1 */ 66 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks_aie.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for AIE locks. This header file is 13 | * not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/17/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_AIE_H 25 | #define XAIELOCKS_AIE_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_locks.h" 28 | #include "xaiegbl_defs.h" 29 | #include "xaie_helper.h" 30 | 31 | /************************** Constant Definitions *****************************/ 32 | 33 | /************************** Function Prototypes *****************************/ 34 | AieRC _XAie_LockAcquire(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 35 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 36 | AieRC _XAie_LockRelease(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 37 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 38 | AieRC _XAie_LockSetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 39 | XAie_LocType Loc, XAie_Lock Lock); 40 | AieRC _XAie_LockGetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 41 | XAie_LocType Loc, XAie_Lock Lock, u32 *LockVal); 42 | 43 | #endif 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks_aieml.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for AIEML locks. This header file is 13 | * not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/17/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_AIEML_H 25 | #define XAIELOCKS_AIEML_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_locks.h" 28 | #include "xaiegbl_defs.h" 29 | #include "xaie_helper.h" 30 | 31 | /************************** Constant Definitions *****************************/ 32 | 33 | /************************** Function Prototypes *****************************/ 34 | AieRC _XAieMl_LockAcquire(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 35 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 36 | AieRC _XAieMl_LockRelease(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 37 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 38 | AieRC _XAieMl_LockSetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 39 | XAie_LocType Loc, XAie_Lock Lock); 40 | AieRC _XAieMl_LockGetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 41 | XAie_LocType Loc, XAie_Lock Lock, u32 *LockVal); 42 | 43 | #endif 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/cmake/options.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | if (NOT DEFINED CMAKE_BUILD_TYPE) 7 | set (CMAKE_BUILD_TYPE Debug) 8 | endif (NOT DEFINED CMAKE_BUILD_TYPE) 9 | message ("-- Build type: ${CMAKE_BUILD_TYPE}") 10 | 11 | if (NOT CMAKE_INSTALL_LIBDIR) 12 | set (CMAKE_INSTALL_LIBDIR "lib") 13 | endif (NOT CMAKE_INSTALL_LIBDIR) 14 | 15 | if (NOT CMAKE_INSTALL_BINDIR) 16 | set (CMAKE_INSTALL_BINDIR "bin") 17 | endif (NOT CMAKE_INSTALL_BINDIR) 18 | 19 | set (_host "${CMAKE_HOST_SYSTEM_NAME}/${CMAKE_HOST_SYSTEM_PROCESSOR}") 20 | message ("-- Host: ${_host}") 21 | 22 | set (_target "${CMAKE_SYSTEM_NAME}/${CMAKE_SYSTEM_PROCESSOR}") 23 | message ("-- Target: ${_target}") 24 | 25 | if (NOT DEFINED MACHINE) 26 | set (MACHINE "Generic") 27 | endif (NOT DEFINED MACHINE) 28 | message ("-- Machine: ${MACHINE}") 29 | 30 | # handle if '-' in machine name 31 | string (REPLACE "-" "_" MACHINE ${MACHINE}) 32 | 33 | if (NOT DEFINED PROJECT_SYSTEM) 34 | string (TOLOWER ${CMAKE_SYSTEM_NAME} PROJECT_SYSTEM) 35 | string (TOUPPER ${CMAKE_SYSTEM_NAME} PROJECT_SYSTEM_UPPER) 36 | endif (NOT DEFINED PROJECT_SYSTEM) 37 | 38 | string (TOLOWER ${CMAKE_SYSTEM_PROCESSOR} PROJECT_PROCESSOR) 39 | string (TOUPPER ${CMAKE_SYSTEM_PROCESSOR} PROJECT_PROCESSOR_UPPER) 40 | string (TOLOWER ${MACHINE} PROJECT_MACHINE) 41 | string (TOUPPER ${MACHINE} PROJECT_MACHINE_UPPER) 42 | 43 | option (WITH_STATIC_LIB "Build with a static library" ON) 44 | 45 | if ("${PROJECT_SYSTEM}" STREQUAL "linux") 46 | option (WITH_SHARED_LIB "Build with a shared library" ON) 47 | endif ("${PROJECT_SYSTEM}" STREQUAL "linux") 48 | -------------------------------------------------------------------------------- /driver/src/io_backend/privilege/xaie_io_privilege.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_privilege.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations that requires privilege permissions for multiple backends. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Wendy   05/17/2021 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_PRIVILEGE_H 25 | #define XAIE_IO_PRIVILEGE_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaie_dma_aie2ps.h" 29 | #include "xaiegbl.h" 30 | #include "xaie_io_privilege.h" 31 | 32 | AieRC _XAie_PrivilegeInitPart(XAie_DevInst *DevInst, XAie_PartInitOpts *Opts); 33 | AieRC _XAie_PrivilegeTeardownPart(XAie_DevInst *DevInst); 34 | AieRC _XAie_PrivilegeRequestTiles(XAie_DevInst *DevInst, 35 | XAie_BackendTilesArray *Args); 36 | AieRC _XAie_PrivilegeSetColumnClk(XAie_DevInst *DevInst, 37 | XAie_BackendColumnReq *Args); 38 | AieRC XAie_UcDmaPause(XAie_DevInst *DevInst, XAie_LocType *Loc, 39 | UcDmaDir_enum Dir, u8 Pause); 40 | AieRC XAie_NocDmaPause(XAie_DevInst *DevInst, XAie_LocType *Loc, 41 | u8 ChNum, XAie_DmaDirection Dir, u8 Pause); 42 | AieRC XAie_Privi2egeSetAxiMMIsolation(XAie_DevInst *DevInst, u8 IsolationFlags); 43 | #endif /* XAIE_IO_PRIVILEGE_H */ 44 | 45 | /** @} */ 46 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie2ps.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie2ps.c 10 | * @{ 11 | * 12 | * This file contains AIE2PS specific interrupt routines which are not exposed 13 | * to the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aie2ps.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | /************************** Constant Definitions *****************************/ 23 | /************************** Function Definitions *****************************/ 24 | /*****************************************************************************/ 25 | /** 26 | * This API computes first level IRQ broadcast ID. 27 | * 28 | * @param DevInst: Device Instance 29 | * @param Loc: Location of AIE Tile 30 | * @param Switch: Switch in the given module. For a shim tile, value 31 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 32 | * 33 | * @return IrqId: IRQ broadcast ID. 34 | * 35 | * @note AIE2PS has NOC tile in every SHIM tile. Each switch in L1 ctrl 36 | * maps to 0 or 1. 37 | * 38 | * Internal Only. 39 | ******************************************************************************/ 40 | u8 _XAie2ps_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 41 | XAie_BroadcastSw Switch) 42 | { 43 | (void)DevInst; 44 | (void)Loc; 45 | return Switch; 46 | } 47 | 48 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 49 | 50 | /** @} */ 51 | -------------------------------------------------------------------------------- /driver/src/timer/xaie_timer.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_timer.h 10 | * @{ 11 | * 12 | * Header file for timer implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date     Changes
18 | * ----- ------   -------- -----------------------------------------------------
19 | * 1.0   Dishita  04/05/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIETIMER_H 24 | #define XAIETIMER_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | #include "xaiegbl.h" 29 | 30 | /************************** Enum *********************************************/ 31 | 32 | /************************** Function Prototypes *****************************/ 33 | AieRC XAie_SetTimerTrigEventVal(XAie_DevInst *DevInst, XAie_LocType Loc, 34 | XAie_ModuleType Module, u32 LowEventValue, u32 HighEventValue); 35 | AieRC XAie_ResetTimer(XAie_DevInst *DevInst, XAie_LocType Loc, 36 | XAie_ModuleType Module); 37 | AieRC XAie_SetTimerResetEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 38 | XAie_ModuleType Module, XAie_Events Event, 39 | XAie_Reset Reset); 40 | AieRC XAie_ReadTimer(XAie_DevInst *DevInst, XAie_LocType Loc, 41 | XAie_ModuleType Module, u64 *TimerVal); 42 | AieRC XAie_WaitCycles(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | XAie_ModuleType Module, u64 CycleCnt); 44 | AieRC XAie_SyncTimerWithTwoBcstChannel(XAie_DevInst *DevInst, u8 BcastChannelId1, 45 | u8 BcastChannelId2); 46 | AieRC XAie_SyncTimer(XAie_DevInst *DevInst, u8 BcastChannelId); 47 | 48 | #endif /* end of protection macro */ 49 | -------------------------------------------------------------------------------- /driver/tests/utest/test_locks_aieml.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN >= 2 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(LockApisAieml) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(LockApisAieml, AcquireLock) 37 | { 38 | AieRC RC; 39 | 40 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 41 | 42 | RC = XAie_LockSetValue(&DevInst, TileLoc, XAie_LockInit(5, 1)); 43 | CHECK_EQUAL(XAIE_OK, RC); 44 | 45 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 46 | CHECK_EQUAL(XAIE_OK, RC); 47 | 48 | RC = XAie_LockSetValue(&DevInst, TileLoc, XAie_LockInit(5, 2)); 49 | CHECK_EQUAL(XAIE_OK, RC); 50 | 51 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, -1), 0); 52 | CHECK_EQUAL(XAIE_OK, RC); 53 | 54 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 2), 0); 55 | CHECK_EQUAL(XAIE_LOCK_RESULT_FAILED, RC); 56 | 57 | RC = XAie_LockSetValue(&DevInst, TileLoc, XAie_LockInit(5, 3)); 58 | CHECK_EQUAL(XAIE_OK, RC); 59 | 60 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 2), 0); 61 | CHECK_EQUAL(XAIE_LOCK_RESULT_FAILED, RC); 62 | } 63 | 64 | TEST(LockApisAieml, ReleaseLock) 65 | { 66 | AieRC RC; 67 | 68 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 69 | 70 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 71 | CHECK_EQUAL(XAIE_OK, RC); 72 | } 73 | #endif 74 | -------------------------------------------------------------------------------- /fal/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | cmake_minimum_required (VERSION 3.0) 8 | 9 | list (APPEND CMAKE_MODULE_PATH 10 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake" 11 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules" 12 | "${CMAKE_CURRENT_SOURCE_DIR}/cmake/platforms") 13 | 14 | project (xaiefal) 15 | 16 | include (CheckIncludeFiles) 17 | include (CheckCSourceCompiles) 18 | include (ExternalProject) 19 | include (collect) 20 | include (options) 21 | include (depends) 22 | 23 | foreach(_inc_path ${CMAKE_INCLUDE_PATH}) 24 | collect (PROJECT_INC_DIRS "${_inc_path}") 25 | endforeach() 26 | 27 | if (WITH_BUILD_XAIEDRV) 28 | if ("${PROJECT_SYSTEM}" STREQUAL "linux") 29 | set (_makefile Makefile.Linux) 30 | else() 31 | set (_makefile Makefile) 32 | endif ("${PROJECT_SYSTEM}" STREQUAL "linux") 33 | set (CC ${CMAKE_C_COMPILER}) 34 | set (CFLAGS -Wall -Wextra ${AIEDRV_BACKEND}) 35 | find_program(MAKE_EXE NAMES gmake nmake make) 36 | ExternalProject_Add(driver 37 | URL "${CMAKE_CURRENT_SOURCE_DIR}/../driver" 38 | SOURCE_DIR "${CMAKE_BINARY_DIR}/driver-src" 39 | BUILD_IN_SOURCE true 40 | CONFIGURE_COMMAND "" 41 | BUILD_COMMAND ${MAKE_EXE} -C src -f ${_makefile} CC=${CC} "CFLAGS=-std=c99 -Wall -Wextra ${AIEDRV_BACKEND}" 42 | INSTALL_COMMAND "" 43 | ) 44 | collect (PROJECT_INC_DIRS ${CMAKE_BINARY_DIR}/driver-src/include) 45 | collect (PROJECT_LIB_DIRS ${CMAKE_BINARY_DIR}/driver-src/src) 46 | endif (WITH_BUILD_XAIEDRV) 47 | 48 | enable_testing () 49 | 50 | add_subdirectory (src) 51 | 52 | if (WITH_DOC) 53 | add_subdirectory (doc) 54 | endif (WITH_DOC) 55 | 56 | if (WITH_TESTS) 57 | add_subdirectory (tests) 58 | endif (WITH_TESTS) 59 | 60 | if (WITH_EXAMPLES) 61 | add_subdirectory (examples) 62 | endif (WITH_EXAMPLES) 63 | 64 | # vim: expandtab:ts=2:sw=2:smartindent 65 | -------------------------------------------------------------------------------- /driver/src/util/xaie_util_events.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. * 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_util_events.c 11 | * @{ 12 | * 13 | * This file contains function implementations for AIE utilities 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Gregory 03/31/2022  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | 25 | /***************************** Include Files *********************************/ 26 | #include "xaie_feature_config.h" 27 | #include "xaie_util_events.h" 28 | 29 | #ifdef XAIE_FEATURE_UTIL_ENABLE 30 | 31 | /**************************** Variable Definitions *******************************/ 32 | /* Event string lookup table indexed by event number */ 33 | static const char *XAie_EventStrings[] = { 34 | XAIE_EVENT_GENERATE_CORE_MOD(ENUM_STRING) 35 | XAIE_EVENT_GENERATE_MEM_MOD(ENUM_STRING) 36 | XAIE_EVENT_GENERATE_PL_MOD(ENUM_STRING) 37 | XAIE_EVENT_GENERATE_MEM_TILE(ENUM_STRING) 38 | }; 39 | 40 | /**************************** Function Definitions *******************************/ 41 | /*****************************************************************************/ 42 | /** 43 | * 44 | * This API takes input of an Event id and returns a string describing the event 45 | * 46 | * @param Event - Event ID 47 | * 48 | * @return String corresponding to Event ID 49 | * 50 | * @note None 51 | * 52 | ******************************************************************************/ 53 | const char* XAie_EventGetString(XAie_Events Event) { 54 | return XAie_EventStrings[Event]; 55 | } 56 | 57 | #endif /* XAIE_FEATURE_UTIL_ENABLE */ 58 | /** @} */ 59 | -------------------------------------------------------------------------------- /driver/src/npi/xaie_npi.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_npi.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for AI engine NPI access 13 | * operations for. 14 | * 15 | ******************************************************************************/ 16 | #ifndef XAIE_NPI_H 17 | #define XAIE_NPI_H 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | #include "xaiegbl_regdef.h" 21 | 22 | /************************** Constant Definitions *****************************/ 23 | 24 | #ifndef XAIE_NPI_BASEADDR 25 | #define XAIE_NPI_BASEADDR 0xF70A0000U 26 | #endif 27 | 28 | #define XAIE_NPI_TIMEOUT_US 0x00000005U 29 | 30 | /* 31 | * Typedef for structure for NPI protected registers access 32 | */ 33 | typedef struct XAie_NpiProtRegReq { 34 | u32 StartCol; 35 | u32 NumCols; 36 | u8 Enable; 37 | } XAie_NpiProtRegReq; 38 | 39 | /* 40 | * This typedef contains the attributes for AI engine NPI registers 41 | */ 42 | typedef struct XAie_NpiMod { 43 | u32 PcsrMaskOff; 44 | u32 PcsrCntrOff; 45 | u32 PcsrLockOff; 46 | u32 ProtRegOff; 47 | u32 PcsrUnlockCode; 48 | XAie_RegFldAttr ShimReset; 49 | XAie_RegFldAttr ProtRegEnable; 50 | XAie_RegFldAttr ProtRegFirstCol; 51 | XAie_RegFldAttr ProtRegLastCol; 52 | AieRC (*SetProtectedRegField)(XAie_DevInst *DevInst, 53 | XAie_NpiProtRegReq *Req, u32 *RegVal); 54 | } XAie_NpiMod; 55 | 56 | typedef void (*NpiWrite32Func)(void *IOInst, u32 RegOff, u32 RegVal); 57 | 58 | /************************** Function Prototypes *****************************/ 59 | AieRC _XAie_NpiSetShimReset(XAie_DevInst *DevInst, u8 RstEnable); 60 | AieRC _XAie_NpiSetProtectedRegEnable(XAie_DevInst *DevInst, 61 | XAie_NpiProtRegReq *Req); 62 | 63 | #endif /* End of protection macro */ 64 | 65 | /** @} */ 66 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | /*****************************************************************************/ 7 | /** 8 | * @file xaie_lite.c 9 | * @{ 10 | * 11 | * This file contains lite routines. 12 | * 13 | * 
14 | * MODIFICATION HISTORY:
15 | *
16 | * Ver   Who     Date        Changes
17 | * ----- ------  --------    ---------------------------------------------------
18 | * 1.0   Nishad  06/23/2022  Initial creation
19 | *
20 | *
21 | * 22 | ******************************************************************************/ 23 | /***************************** Include Files *********************************/ 24 | 25 | #include "xaie_feature_config.h" 26 | 27 | #if defined(XAIE_FEATURE_PRIVILEGED_ENABLE) && defined(XAIE_FEATURE_LITE) 28 | 29 | #include "xaie_lite.h" 30 | #include "xaie_lite_internal.h" 31 | #include "xaiegbl_defs.h" 32 | #include "xaiegbl.h" 33 | 34 | /***************************** Macro Definitions *****************************/ 35 | /************************** Function Definitions *****************************/ 36 | /*****************************************************************************/ 37 | /** 38 | * 39 | * This API maps given IRQ ID to a range of columns it is programmed to receive 40 | * interrupts from. 41 | * 42 | * @param IrqId: 43 | * @param Range: Pointer to return column range mapping. 44 | * 45 | * @return XAIE_OK on success, error code on failure. 46 | * 47 | * @note None 48 | * 49 | ******************************************************************************/ 50 | AieRC XAie_MapIrqIdToCols(u8 IrqId, XAie_Range *Range) 51 | { 52 | XAIE_ERROR_RETURN(IrqId >= XAIE_MAX_NUM_NOC_INTR, XAIE_INVALID_ARGS, 53 | XAIE_ERROR_MSG("Invalid AIE IRQ ID\n")); 54 | 55 | XAie_Range Temp = _XAie_MapIrqIdToCols(IrqId); 56 | Range->Start = Temp.Start; 57 | Range->Num = Temp.Num; 58 | 59 | return XAIE_OK; 60 | } 61 | 62 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE && XAIE_FEATURE_LITE */ 63 | /** @} */ 64 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aie2ps.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who	Date	Changes
19 | * ----- ------     --------    -----------------------------------------------------
20 | * 1.0   Sanakrji   10/04/2022  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIE2PS_H 25 | #define XAIE_DMA_AIE2PS_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | 30 | typedef enum { XAIE_UC_MODULE__DMA_DIR__DM2MM, 31 | XAIE_UC_MODULE__DMA_DIR__MM2DM, 32 | XAIE_UC_MODULE__DMA_DIR__MAX 33 | } UcDmaDir_enum; 34 | 35 | /************************** Function Prototypes *****************************/ 36 | AieRC _XAie2PS_DmaSetMultiDim(XAie_DmaDesc *DmaDesc, XAie_DmaTensor *Tensor); 37 | AieRC _XAie2PS_MemTileDmaWriteBd(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc, 38 | XAie_LocType Loc, u8 BdNum); 39 | AieRC _XAie2PS_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 40 | XAie_LocType Loc, u8 BdNum); 41 | AieRC _XAie2PS_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 42 | XAie_LocType Loc, u8 BdNum); 43 | 44 | AieRC _XAie2PS_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 45 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 46 | u16 BdNum); 47 | AieRC _XAie2PS_AxiBurstLenCheck(u8 BurstLen, u8 *AxiBurstLen); 48 | AieRC XAie_GetUcDmaAxiMmOutstandingTxn(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | u32 *Status); 50 | AieRC XAie_GetNocDmaAxiMmOutstandingTxn(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | u32 *Status); 52 | #endif /* XAIE_DMA_AIE2PS_H */ 53 | /** @} */ 54 | -------------------------------------------------------------------------------- /driver/tests/utest/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. 3 | # SPDX-License-Identifier: MIT 4 | ############################################################################### 5 | 6 | if (CPPUTEST_DIR) 7 | find_path(CPPUTEST_INC_DIR NAMES "CppUTest/Utest.h" PATHS ${CPPUTEST_DIR}/include) 8 | find_library(CPPUTEST_FOUND_LIB NAMES CppUTest PATHS ${CPPUTEST_DIR}/src/CppUTest) 9 | if (NOT CPPUTEST_FOUND_LIB) 10 | message (FATAL_ERROR "No CppUtest Library is found in ${CPPUTEST_DIR}") 11 | endif (NOT CPPUTEST_FOUND_LIB) 12 | get_filename_component(CPPUTEST_LIB_DIR ${CPPUTEST_FOUND_LIB} DIRECTORY) 13 | message ("CPPUTEST_INC_DIR=${CPPUTEST_INC_DIR}") 14 | else() 15 | message (FATAL_ERROR "No CppUtest directory is found in ${CPPUTEST_DIR}") 16 | endif (CPPUTEST_DIR) 17 | 18 | file(COPY elf_files DESTINATION ${CMAKE_CURRENT_BINARY_DIR}) 19 | 20 | collector_list (_list PROJECT_INCLUDE_DIRS) 21 | list (APPEND _list ${CPPUTEST_INC_DIR}) 22 | list (APPEND _list ${CMAKE_CURRENT_SOURCE_DIR}/common) 23 | list (APPEND _list ${CMAKE_BINARY_DIR}/driver-src/include) 24 | 25 | include_directories (${_list}) 26 | 27 | collector_list (_list PROJECT_LIB_DIRS) 28 | list (APPEND _list ${CPPUTEST_LIB_DIR}) 29 | list (APPEND _list ${CMAKE_BINARY_DIR}/driver-src}) 30 | link_directories (${_list}) 31 | 32 | collector_list (_deps PROJECT_LIB_DEPS) 33 | list (APPEND _deps "CppUTest") 34 | list (APPEND _deps "xaiengine") 35 | 36 | file(GLOB _sources *.cpp) 37 | set (EXEPREX "run-test") 38 | set (EXETEST "${EXEPREX}-aie") 39 | add_executable (${EXETEST} ${_sources}) 40 | set_target_properties(${EXETEST} PROPERTIES CXX_STANDARD 11) 41 | #if(TEST_HARDWARE) 42 | # set (_test_cflag -DTEST_HARDWARE) 43 | #endif (TEST_HARDWARE) 44 | if (AIE_GEN) 45 | set (_test_cflag ${_test_cflag} -DAIE_GEN=${AIE_GEN}) 46 | else(AIE_GEN) 47 | set (_test_cflag ${_test_cflag} -DAIE_GEN=1) 48 | endif(AIE_GEN) 49 | 50 | if (__AIESIM__) 51 | set (_test_cflag ${_test_cflag} -D__AIESIM__=1) 52 | endif(__AIESIM__) 53 | message ("_test_cflags=${_test_cflag}") 54 | target_compile_options (${EXETEST} PUBLIC ${_test_cflag}) 55 | target_link_libraries (${EXETEST} ${_deps}) 56 | -------------------------------------------------------------------------------- /driver/tests/utest/test_multi_part.cpp: -------------------------------------------------------------------------------- 1 | 2 | #include "CppUTest/TestHarness.h" 3 | #include 4 | 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(MultiPartsApis) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(MultiPartsApis, MultiPartsBasic) 37 | { 38 | AieRC RC; 39 | XAie_DmaDesc DmaDesc; 40 | u64 AiePartBaseAddr = 0x40000000; 41 | u8 PartStartCol = 2; 42 | u8 PartNumCols = 3; 43 | 44 | XAie_LocType TileLoc0 = XAie_TileLoc(0, 0); 45 | XAie_LocType TileLoc1 = XAie_TileLoc(2, 0); 46 | 47 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc0); 48 | CHECK_EQUAL(RC, XAIE_INVALID_TILE); 49 | 50 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc1); 51 | CHECK_EQUAL(RC, XAIE_OK); 52 | 53 | RC = XAie_SetupPartitionConfig(&DevInst, AiePartBaseAddr, PartStartCol, 54 | PartNumCols); 55 | CHECK_EQUAL(RC, XAIE_INVALID_DEVICE); 56 | 57 | XAie_Finish(&DevInst); 58 | 59 | RC = XAie_SetupPartitionConfig(&DevInst, AiePartBaseAddr, PartStartCol, 60 | XAIE_NUM_COLS); 61 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 62 | CHECK_EQUAL(RC, XAIE_INVALID_DEVICE); 63 | 64 | RC = XAie_SetupPartitionConfig(&DevInst, AiePartBaseAddr, PartStartCol, 65 | PartNumCols); 66 | CHECK_EQUAL(RC, XAIE_OK); 67 | 68 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 69 | CHECK_EQUAL(RC, XAIE_OK); 70 | 71 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc0); 72 | CHECK_EQUAL(RC, XAIE_OK); 73 | 74 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc1); 75 | #if AIE_GEN == 3 76 | CHECK_EQUAL(RC, XAIE_OK); 77 | #else 78 | CHECK_EQUAL(RC, XAIE_INVALID_TILE); 79 | #endif 80 | 81 | CHECK_EQUAL(DevInst.BaseAddr, AiePartBaseAddr); 82 | } 83 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aie.c 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who         Date        Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Siddharth   12/09/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #include "xaie_feature_config.h" 24 | #include "xaie_helper.h" 25 | 26 | #ifdef XAIE_FEATURE_SS_ENABLE 27 | /************************** Constant Definitions *****************************/ 28 | /************************** Function Definitions *****************************/ 29 | /*****************************************************************************/ 30 | /** 31 | * 32 | * This api is used to verify if a stream switch connection is possible with 33 | * the provided slave and master ports. Within AIE, a full crossbar exists. 34 | * So, every valid slave port and valid master port can connect. 35 | * 36 | * @param Slave: The type of the slave port. 37 | * @param SlvPortNum: The number of the slave port. 38 | * @param Master: The type of the master port. 39 | * @param MstrPortNum: The number of the master port. 40 | * 41 | * @return XAIE_OK if a stream switch connection is possible. 42 | * 43 | * @note Internal API for AIE. This API shouldn't be called directly. 44 | * It is invoked using a function pointer within the Stream 45 | * Module data structure. 46 | * 47 | *****************************************************************************/ 48 | AieRC _XAie_StrmSwCheckPortValidity(StrmSwPortType Slave, u8 SlvPortNum, 49 | StrmSwPortType Master, u8 MstrPortNum) 50 | { 51 | (void)Slave; 52 | (void)SlvPortNum; 53 | (void)Master; 54 | (void)MstrPortNum; 55 | return XAIE_OK; 56 | } 57 | 58 | #endif /* XAIE_FEATURE_SS_ENABLE */ 59 | -------------------------------------------------------------------------------- /driver/tests/utest/test_locks_aie.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN == 1 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(LockApisAie) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(LockApisAie, AcquireLock) 37 | { 38 | AieRC RC; 39 | 40 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 41 | 42 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 43 | CHECK_EQUAL(XAIE_OK, RC); 44 | 45 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 46 | CHECK_EQUAL(XAIE_OK, RC); 47 | 48 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 49 | if (DevInst.Backend->Type == XAIE_IO_BACKEND_DEBUG) { 50 | CHECK_EQUAL(RC, XAIE_OK); 51 | } else { 52 | CHECK_EQUAL(XAIE_LOCK_RESULT_FAILED, RC); 53 | } 54 | 55 | RC = XAie_LockRelease(&DevInst, TileLoc, 56 | XAie_LockInit(5, XAIE_LOCK_WITH_NO_VALUE), 0); 57 | CHECK_EQUAL(XAIE_OK, RC); 58 | 59 | RC = XAie_LockAcquire(&DevInst, TileLoc, 60 | XAie_LockInit(5, XAIE_LOCK_WITH_NO_VALUE), 0); 61 | CHECK_EQUAL(XAIE_OK, RC); 62 | 63 | RC = XAie_LockAcquire(&DevInst, TileLoc, 64 | XAie_LockInit(5, XAIE_LOCK_WITH_NO_VALUE), 0); 65 | if (DevInst.Backend->Type == XAIE_IO_BACKEND_DEBUG) { 66 | CHECK_EQUAL(RC, XAIE_OK); 67 | } else { 68 | CHECK_EQUAL(XAIE_LOCK_RESULT_FAILED, RC); 69 | } 70 | } 71 | 72 | TEST(LockApisAie, ReleaseLock) 73 | { 74 | AieRC RC; 75 | 76 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 77 | 78 | RC = XAie_LockRelease(&DevInst, TileLoc, 79 | XAie_LockInit(5, XAIE_LOCK_WITH_NO_VALUE), 0); 80 | CHECK_EQUAL(XAIE_OK, RC); 81 | 82 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 83 | CHECK_EQUAL(XAIE_OK, RC); 84 | } 85 | #endif 86 | -------------------------------------------------------------------------------- /driver/src/memory/xaie_mem.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_mem.h 10 | * @{ 11 | * 12 | * Header file for data memory implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Nishad  07/30/2020  Add API to read and write block of data from tile
22 | *			    data memory.
23 | *
24 | * 25 | ******************************************************************************/ 26 | #ifndef XAIEMEM_H 27 | #define XAIEMEM_H 28 | 29 | /***************************** Include Files *********************************/ 30 | #include "xaiegbl.h" 31 | 32 | /***************************** Macro Definitions *****************************/ 33 | #define XAIE_MEM_WORD_ALIGN_SHIFT 2U 34 | #define XAIE_MEM_WORD_ALIGN_MASK ((1U << XAIE_MEM_WORD_ALIGN_SHIFT) - 1U) 35 | #define XAIE_MEM_WORD_ALIGN_SIZE (1U << XAIE_MEM_WORD_ALIGN_SHIFT) 36 | #define XAIE_MEM_WORD_ROUND_UP(Addr) (((Addr) + XAIE_MEM_WORD_ALIGN_MASK) & \ 37 | ~XAIE_MEM_WORD_ALIGN_MASK) 38 | #define XAIE_MEM_WORD_ROUND_DOWN(Addr) ((Addr) & (~XAIE_MEM_WORD_ALIGN_MASK)) 39 | 40 | /************************** Function Prototypes *****************************/ 41 | AieRC XAie_DataMemWrWord(XAie_DevInst *DevInst, XAie_LocType Loc, 42 | u32 Addr, u32 Data); 43 | AieRC XAie_DataMemRdWord(XAie_DevInst *DevInst, XAie_LocType Loc, 44 | u32 Addr, u32 *Data); 45 | AieRC XAie_DataMemBlockWrite(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 46 | const void *Src, u32 Size); 47 | AieRC XAie_SharedDataMemBlockWrite(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | u32 Addr, const void *Src, u32 Size); 49 | AieRC XAie_SharedDataMemBlockRead(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 50 | void *Dst, u32 Size); 51 | AieRC XAie_DataMemBlockRead(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 52 | void *Dst, u32 Size); 53 | 54 | #endif /* end of protection macro */ 55 | 56 | /** @} */ 57 | -------------------------------------------------------------------------------- /driver/src/common/xaie_helper_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2024 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_helper_internal.h 10 | * @{ 11 | * 12 | * This file contains inline helper functions for AIE drivers. 13 | ******************************************************************************/ 14 | #ifndef XAIE_HELPER_INTERNAL_H 15 | #define XAIE_HELPER_INTERNAL_H 16 | 17 | /***************************** Include Files *********************************/ 18 | #include "xaiegbl_regdef.h" 19 | /***************************** Macro Definitions *****************************/ 20 | /************************** Function Definitions *****************************/ 21 | AieRC _XAie_GetSlaveIdx(const XAie_StrmMod *StrmMod, StrmSwPortType Slave, 22 | u8 PortNum, u8 *SlaveIdx); 23 | AieRC _XAie_GetMstrIdx(const XAie_StrmMod *StrmMod, StrmSwPortType Master, 24 | u8 PortNum, u8 *MasterIdx); 25 | u32 _XAie_GetFatalGroupErrors(XAie_DevInst *DevInst, XAie_LocType Loc, 26 | XAie_ModuleType Module); 27 | u32 _XAie_GetTileBitPosFromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 28 | void _XAie_SetBitInBitmap(u32 *Bitmap, u32 StartSetBit, u32 NumSetBit); 29 | void _XAie_ClrBitInBitmap(u32 *Bitmap, u32 StartSetBit, u32 NumSetBit); 30 | AieRC _XAie_Txn_Start(XAie_DevInst *DevInst, u32 Flags); 31 | AieRC _XAie_Txn_Submit(XAie_DevInst *DevInst, XAie_TxnInst *TxnInst); 32 | XAie_TxnInst* _XAie_TxnExport(XAie_DevInst *DevInst); 33 | u8* _XAie_TxnExportSerialized(XAie_DevInst *DevInst, u8 NumConsumers, 34 | u32 Flags); 35 | AieRC _XAie_ClearTransaction(XAie_DevInst* DevInst); 36 | AieRC _XAie_TxnFree(XAie_TxnInst *Inst); 37 | void _XAie_TxnResourceCleanup(XAie_DevInst *DevInst); 38 | void _XAie_FreeTxnPtr(void *Ptr); 39 | void _XAie_AppendPartitionToList(XAie_DevInst *DevInst, XAie_PartitionList *PartInst); 40 | AieRC _XAie_DestroyPartitionFdList(XAie_DevInst *DevInst); 41 | AieRC _XAie_PrintPartitionList(XAie_DevInst *DevInst); 42 | int _XAie_MatchPartitionList(XAie_DevInst *DevInst, u32 PartitionId); 43 | AieRC _XAie_IsUcPrivilegedSet(XAie_DevInst *DevInst, XAie_LocType Loc, u8 *Priv); 44 | AieRC _XAie_PmSetPartitionClock(XAie_DevInst *DevInst, u8 Enable); 45 | #endif 46 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie.c 10 | * @{ 11 | * 12 | * This file contains AIE specific interrupt routines which are not exposed to 13 | * the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aie.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | 23 | /************************** Constant Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * This API computes first level IRQ broadcast ID. 28 | * 29 | * @param DevInst: Device Instance 30 | * @param Loc: Location of AIE Tile 31 | * @param Switch: Switch in the given module. For a shim tile, value 32 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 33 | * 34 | * @return IrqId: IRQ broadcast ID. 35 | * 36 | * @note IRQ ID for each switch block starts from 0, every block on the 37 | * left will increase by 1 until it reaches the first Shim NoC 38 | * column. The IRQ ID restarts from 0 on the switch A of the 39 | * second shim NoC column. For the shim PL columns after the 40 | * second Shim NoC, if there is no shim NoC further right, the 41 | * column will use the shim NoC on the left. That is the L1 IRQ 42 | * broadcast ID pattern, 43 | * For column from 0 to 43 is: 0 1 2 3 4 5 0 1 44 | * For column from 44 to 49 is: 0 1 2 3 4 5 0 1 2 3 4 5 45 | * 46 | * Internal Only. 47 | ******************************************************************************/ 48 | u8 _XAie_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | XAie_BroadcastSw Switch) 50 | { 51 | u8 IrqId = (((Loc.Col % 4U) % 3U) * 2U) + (u8)Switch; 52 | 53 | if (Loc.Col + 3U > DevInst->NumCols) { 54 | IrqId += 2U; 55 | } 56 | 57 | return IrqId; 58 | } 59 | 60 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 61 | 62 | /** @} */ 63 | -------------------------------------------------------------------------------- /fal/README.md: -------------------------------------------------------------------------------- 1 | # xaiefal 2 | 3 | ## Overview 4 | 5 | Xilinx AI engine functional abstraction layer (FAL) provides common user APIs 6 | for runtime AI engine tiles resources management. 7 | 8 | ## Build Proejct 9 | We use `cmake` to build the project. 10 | 11 | ### Generate Documentation 12 | The project uses doxygen for documentation. Follow these instructions to 13 | generate documentation. 14 | ``` 15 | mkdir build 16 | cd build 17 | cmake ../ -DWITH_DOC=on 18 | make 19 | ``` 20 | 21 | ### Includes to build `libxaiengine` library 22 | Use the following cmake commands to configure the build: 23 | For Linux to run on target: 24 | ``` 25 | mkdir build 26 | cd build 27 | cmake ../ -DCMAKE_TOOLCHAIN_FILE=versal-linux -DWITH_BUILD_XAIEDRV=on 28 | ``` 29 | 30 | After running `cmake` to configure the build, can go to the build directory to 31 | compile: 32 | ``` 33 | cd build 34 | make VERBOSE=1 35 | ``` 36 | 37 | ### Not build `libxaiengine` library 38 | If excludes building `libxaiengine` library, user will need to provide where 39 | `libxaiengine` is as this library depends on the AI engine driver library. 40 | For Linux to run on target: 41 | ``` 42 | mkdir build 43 | cd build 44 | cmake ../ -DCMAKE_TOOLCHAIN_FILE=versal-linux -DCMAKE_LIBRARY_PATH= -DCMAKE_INCLUDE_PATH= 45 | ``` 46 | 47 | After running `cmake` to configure the build, can go to the build directory to 48 | compile: 49 | ``` 50 | cd build 51 | make VERBOSE=1 52 | ``` 53 | 54 | ### Build Unit Tests 55 | We use `CppUTest` for unit testing. Use CMake option `-DWITH_TESTS=ON` to turn 56 | on building the unit testing. 57 | 58 | You can specify to use your external cpputest directory with the following 59 | option `-DWITH_TESTS=ON -DCPPUTEST_DIR=` 60 | 61 | Here is the repo for cpputest: 62 | `https://github.com/cpputest/cpputest.git` 63 | 64 | The testing executable will be in `/tests/`. 65 | It will not run the tests by default during build. If you want to run the tests 66 | in the end of the build, you can use CMake option `-DWITH_TESTS_EXEC=ON`. 67 | 68 | #### Build with Coverage Enable 69 | Add the following cmake options along with `-DWITH_TESTS=ON -DWITH_TESTS_EXEC=ON`: 70 | `-DCMAKE_BUILD_TYPE=Debug -DCODE_COVERAGE=on` to enable coverage. 71 | 72 | The generated coverage information file will be in: 73 | `/tests/utests/`. 74 | 75 | ## License 76 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 77 | SPDX-License-Identifier: MIT 78 | -------------------------------------------------------------------------------- /driver/src/io_backend/ext/xaie_io_common.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_common.c 10 | * @{ 11 | * 12 | * This file contains routines for common io backend. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date        Changes
18 | * ----- ------  --------    ---------------------------------------------------
19 | * 1.0   Dishita 03/08/2021  Initial creation
20 | *
21 | *
22 | * 23 | ******************************************************************************/ 24 | /***************************** Include Files *********************************/ 25 | #include 26 | #include 27 | 28 | #include "xaie_feature_config.h" 29 | #include "xaie_io.h" 30 | #include "xaie_helper.h" 31 | #include "xaie_helper_internal.h" 32 | /*****************************************************************************/ 33 | /************************** Function Definitions *****************************/ 34 | /*****************************************************************************/ 35 | /** 36 | * This API marks the bitmap with for the tiles which are clock enabled. 37 | * 38 | * @param DevInst: AI engine partition device instance pointer 39 | * @param Args: Backend tile args 40 | * 41 | * @return XAIE_OK on success, error code on failure 42 | * 43 | * @note Internal only. 44 | * 45 | *******************************************************************************/ 46 | void _XAie_IOCommon_MarkTilesInUse(XAie_DevInst *DevInst, 47 | XAie_BackendTilesArray *Args) 48 | { 49 | /* Setup the requested tiles bitmap locally */ 50 | if (Args->Locs == NULL) { 51 | u32 StartBit, NumTiles; 52 | 53 | NumTiles = (u32)(DevInst->NumCols * (DevInst->NumRows - 1U)); 54 | /* Loc is NULL, it suggests all tiles are requested */ 55 | StartBit = _XAie_GetTileBitPosFromLoc(DevInst, 56 | XAie_TileLoc(0, 1)); 57 | _XAie_SetBitInBitmap(DevInst->DevOps->TilesInUse, StartBit, 58 | NumTiles); 59 | } else { 60 | for(u32 i = 0; i < Args->NumTiles; i++) { 61 | u32 Bit; 62 | 63 | if(Args->Locs[i].Row == 0U) { 64 | continue; 65 | } 66 | 67 | /* 68 | * If a tile is ungated, the rows below it are 69 | * ungated. 70 | */ 71 | Bit = _XAie_GetTileBitPosFromLoc(DevInst, 72 | XAie_TileLoc(Args->Locs[i].Col, 1)); 73 | _XAie_SetBitInBitmap(DevInst->DevOps->TilesInUse, 74 | Bit, Args->Locs[i].Row); 75 | } 76 | } 77 | } 78 | 79 | /** @} */ 80 | -------------------------------------------------------------------------------- /driver/src/core/xaie_elfloader.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_elfloader.h 10 | * @{ 11 | * 12 | * Header file for core elf loader functions 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Tejus   05/26/2020  Add API to load elf from memory.
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIELOADER_H 26 | #define XAIELOADER_H 27 | 28 | #include "xaie_feature_config.h" 29 | #ifdef XAIE_FEATURE_ELF_ENABLE 30 | 31 | /***************************** Include Files *********************************/ 32 | #include 33 | #include 34 | #include 35 | #include "xaie_helper.h" 36 | #include "xaiegbl.h" 37 | #include "xaiegbl_defs.h" 38 | #include "xaiegbl_defs.h" 39 | 40 | /************************** Constant Definitions *****************************/ 41 | #define XAIE_LOAD_ELF_TXT (1U << 0U) 42 | #define XAIE_LOAD_ELF_BSS (1U << 1U) 43 | #define XAIE_LOAD_ELF_DATA (1U << 2U) 44 | #define XAIE_LOAD_ELF_ALL (XAIE_LOAD_ELF_TXT | XAIE_LOAD_ELF_BSS | \ 45 | XAIE_LOAD_ELF_DATA) 46 | 47 | /************************** Variable Definitions *****************************/ 48 | typedef struct { 49 | u32 start; /**< Stack start address */ 50 | u32 end; /**< Stack end address */ 51 | } XAieSim_StackSz; 52 | /************************** Function Prototypes *****************************/ 53 | 54 | AieRC XAie_LoadElf(XAie_DevInst *DevInst, XAie_LocType Loc, const char *ElfPtr, 55 | u8 LoadSym); 56 | AieRC XAie_LoadElfMem(XAie_DevInst *DevInst, XAie_LocType Loc, 57 | const unsigned char* ElfMem); 58 | AieRC XAie_LoadElfSection(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | const unsigned char *SectionPtr, const Elf32_Phdr *Phdr); 60 | AieRC XAie_LoadElfSectionBlock(XAie_DevInst *DevInst, XAie_LocType Loc, 61 | const unsigned char* SectionPtr, u64 TgtAddr, u32 Size); 62 | AieRC XAie_LoadElfPartial(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | const char* ElfPtr, u8 Sections, u8 LoadSym); 64 | 65 | void _XAie_PrintElfHdr(const Elf32_Ehdr *Ehdr); 66 | void _XAie_PrintProgSectHdr(const Elf32_Phdr *Phdr); 67 | #endif /* XAIE_FEATURE_ELF_ENABLE */ 68 | #endif /* end of protection macro */ 69 | /** @} */ 70 | -------------------------------------------------------------------------------- /driver/src/io_backend/xaie_io_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | *****************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_internal.c 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Ssatpute   27/06/2020 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_INTERNAL_H 25 | #define XAIE_IO_INTERNAL_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | #include "xaie_io.h" 30 | 31 | /****************************** Type Definitions *****************************/ 32 | /************************** Function Prototypes *****************************/ 33 | const XAie_Backend* _XAie_GetBackendPtr(XAie_BackendType Backend); 34 | 35 | /*****************************************************************************/ 36 | /** 37 | * 38 | * Set the NPI write request arguments 39 | * 40 | * @param RegOff : NPI register offset 41 | * @param RegVal : Register Value 42 | * @return NPI write request 43 | * 44 | * @note Internal API only. 45 | * 46 | ******************************************************************************/ 47 | static inline XAie_BackendNpiWrReq 48 | _XAie_SetBackendNpiWrReq(u32 RegOff, u32 RegVal) 49 | { 50 | XAie_BackendNpiWrReq Req; 51 | 52 | Req.NpiRegOff = RegOff; 53 | Req.Val = RegVal; 54 | 55 | return Req; 56 | } 57 | 58 | /*****************************************************************************/ 59 | /** 60 | * 61 | * Set the NPI mask poll request arguments 62 | * 63 | * @param RegOff : NPI register offset 64 | * @param Mask : Mask Value 65 | * @param RegVal : Register Value 66 | * @param TimeOutUs : Time Out Value in us. 67 | * @return NPI mask poll request 68 | * 69 | * @note Internal API only. 70 | * 71 | ******************************************************************************/ 72 | static inline XAie_BackendNpiMaskPollReq 73 | _XAie_SetBackendNpiMaskPollReq(u32 RegOff, u32 Mask, u32 RegVal, u32 TimeOutUs) 74 | { 75 | XAie_BackendNpiMaskPollReq Req; 76 | 77 | Req.NpiRegOff = RegOff; 78 | Req.Val = RegVal; 79 | Req.Mask = Mask; 80 | Req.TimeOutUs = TimeOutUs; 81 | 82 | return Req; 83 | } 84 | 85 | #endif /* End of protection macro */ 86 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aieml.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aieml.c 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets for AIEML 13 | * 14 | ******************************************************************************/ 15 | /***************************** Include Files *********************************/ 16 | #include "xaie_feature_config.h" 17 | #include "xaie_helper.h" 18 | #include "xaie_npi.h" 19 | #include "xaiegbl.h" 20 | 21 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 22 | 23 | /*****************************************************************************/ 24 | /***************************** Macro Definitions *****************************/ 25 | /************************** Function Definitions *****************************/ 26 | /*****************************************************************************/ 27 | /** 28 | * 29 | * This API reset the SHIM for the specified columns 30 | * 31 | * @param DevInst: Device Instance 32 | * @param StartCol: Start column 33 | * @param NumCols: Number of columns 34 | * 35 | * @return XAIE_OK for success, and error value for failure 36 | * 37 | * @note It is not required to check the DevInst as the caller function 38 | * should provide the correct value. As we only supports full 39 | * partition SHIMs reset, if the @StartCol and @NumCols are not 40 | * aligned with the full partition, it will return error. 41 | * This function does the following steps: 42 | * * Enable protect registers 43 | * * Assert SHIM reset 44 | * * Deassert SHIM reset 45 | * * Disable protect registers 46 | * 47 | ******************************************************************************/ 48 | AieRC _XAieMl_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols) 49 | { 50 | XAie_NpiProtRegReq ProtRegReq; 51 | 52 | if(StartCol > 0U || NumCols != DevInst->NumCols) { 53 | XAIE_ERROR("AIE shim reset, not supported columns.\n"); 54 | return XAIE_INVALID_ARGS; 55 | } 56 | 57 | ProtRegReq.StartCol = StartCol; 58 | ProtRegReq.NumCols = NumCols; 59 | ProtRegReq.Enable = XAIE_ENABLE; 60 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_SET_PROTREG, (void *)&ProtRegReq); 61 | 62 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 63 | (void *)(uintptr_t)XAIE_ENABLE); 64 | 65 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 66 | (void *)(uintptr_t)XAIE_DISABLE); 67 | 68 | ProtRegReq.Enable = XAIE_DISABLE; 69 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_SET_PROTREG, (void *)&ProtRegReq); 70 | 71 | return XAIE_OK; 72 | } 73 | 74 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 75 | /** @} */ 76 | -------------------------------------------------------------------------------- /driver/src/global/xaiegbl_defs.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaiegbl_defs.h 10 | * @{ 11 | * 12 | * This file contains the generic definitions for the AIE drivers. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0  Naresh  03/23/2018  Initial creation
20 | * 1.1  Naresh  07/11/2018  Updated copyright info
21 | * 1.2  Hyun    10/10/2018  Added the mask write API
22 | * 1.3  Nishad  12/05/2018  Renamed ME attributes to AIE
23 | * 1.4  Hyun    01/08/2019  Add the mask poll function
24 | * 1.5  Tejus   08/01/2019  Restructure code for AIE
25 | * 1.6  Dishita 04/17/2020  Fix compiler warning
26 | * 1.7  Dishita 05/07/2020  Removed Reset related macros
27 | * 1.8  Tejus   06/09/2020  Remove NPI apis.
28 | *
29 | * 30 | ******************************************************************************/ 31 | #ifndef XAIEGBL_DEFS_H 32 | #define XAIEGBL_DEFS_H 33 | 34 | /***************************** Include Files *********************************/ 35 | #include 36 | #include 37 | 38 | /************************** Constant Definitions *****************************/ 39 | typedef int8_t s8; 40 | typedef uint8_t u8; 41 | typedef uint16_t u16; 42 | typedef int32_t s32; 43 | typedef uint32_t u32; 44 | typedef uint64_t u64; 45 | 46 | #define XAIE_DEV_GENERIC_DEVICE 0U 47 | #define XAIE_DEV_GEN_AIE 1U 48 | #define XAIE_DEV_GEN_AIEML 2U 49 | #define XAIE_DEV_GEN_AIE2IPU 3U 50 | #define XAIE_DEV_GEN_AIE2P 4U 51 | #define XAIE_DEV_GEN_AIE2PS 5U 52 | #define XAIE_DEV_GEN_S100 6U 53 | #define XAIE_DEV_GEN_S200 7U 54 | #define XAIE_DEV_GEN_AIE2P_STRIX_A0 8U 55 | #define XAIE_DEV_GEN_AIE2P_STRIX_B0 9U 56 | 57 | #define XAIE_COMPONENT_IS_READY 1U 58 | 59 | #define XAIE_NULL (void *)0U 60 | #define XAIE_ENABLE 1U 61 | #define XAIE_DISABLE 0U 62 | 63 | #define XAIEGBL_TILE_TYPE_AIETILE 0U 64 | #define XAIEGBL_TILE_TYPE_SHIMNOC 1U 65 | #define XAIEGBL_TILE_TYPE_SHIMPL 2U 66 | #define XAIEGBL_TILE_TYPE_MEMTILE 3U 67 | #define XAIEGBL_TILE_TYPE_MAX 4U 68 | 69 | #define XAie_SetField(Val, Lsb, Mask) (((u32)(Val) << (Lsb)) & (Mask)) 70 | #define XAie_GetField(Val, Lsb, Mask) (((u32)(Val) & (Mask)) >> (Lsb)) 71 | 72 | #define __FORCE_INLINE__ __attribute__((always_inline)) 73 | 74 | /************************** Variable Definitions *****************************/ 75 | /************************** Function Prototypes *****************************/ 76 | #endif /* end of protection macro */ 77 | /** @} */ 78 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aieml.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aieml.c 10 | * @{ 11 | * 12 | * This file contains AIE ML specific interrupt routines which are not exposed 13 | * to the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aieml.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | 23 | /************************** Constant Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * This API computes first level IRQ broadcast ID. 28 | * 29 | * @param DevInst: Device Instance 30 | * @param Loc: Location of AIE Tile 31 | * @param Switch: Switch in the given module. For a shim tile, value 32 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 33 | * 34 | * @return IrqId: IRQ broadcast ID. 35 | * 36 | * @note IRQ ID for each switch block starts from 0, every block on the 37 | * left will increase by 1 until it reaches the first Shim NoC 38 | * column. The IRQ ID restarts from 0 on the switch A of the 39 | * second shim NoC column. For the shim PL columns after the 40 | * second Shim NoC, if there is no shim NoC further right, the 41 | * column will use the shim NoC on the left. That is the L1 IRQ 42 | * broadcast ID pattern, 43 | * For column from 0 to 43 is: 0 1 2 3 4 5 0 1 44 | * For column from 44 to 49 is: 0 1 2 3 4 5 0 1 2 3 4 5 45 | * 46 | * Internal Only. 47 | ******************************************************************************/ 48 | u8 _XAieMl_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | XAie_BroadcastSw Switch) 50 | { 51 | u8 TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 52 | 53 | if (TileType != XAIEGBL_TILE_TYPE_SHIMNOC) { 54 | if (((Loc.Col / 4U) * 4U + 2U) < DevInst->NumCols) { 55 | /* There is SHIM NOC on the right */ 56 | return (Loc.Col % 4U) * 2U + (u8)Switch; 57 | } else { 58 | /* 59 | * if there is no SHIM NOC on the right, use the 60 | * SHIM NoC on the left. 61 | */ 62 | return (Loc.Col % 4U) * 2U + (u8)Switch + 2U; 63 | } 64 | } else { 65 | if ((Loc.Col % 4U) == 2U) { 66 | /* SHIM NoC on the left */ 67 | return 4U + (u8)Switch; 68 | } else { 69 | /* SHIM NoC on the right */ 70 | return (u8)Switch; 71 | } 72 | } 73 | } 74 | 75 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 76 | 77 | /** @} */ 78 | -------------------------------------------------------------------------------- /driver/src/pl/xaie_plif.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_plif.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/28/2019  Initial creation
20 | * 1.1   Tejus   03/16/2020  Implementation of apis for Mux/Demux configuration
21 | * 1.2   Tejus   03/20/2020  Remove range apis
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIEPLIF_H 26 | #define XAIEPLIF_H 27 | 28 | /***************************** Include Files *********************************/ 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | /**************************** Type Definitions *******************************/ 32 | /* 33 | * This enum captures the AIE-PL interface bit widths available in the hardware. 34 | */ 35 | typedef enum { 36 | PLIF_WIDTH_32 = 32, 37 | PLIF_WIDTH_64 = 64, 38 | PLIF_WIDTH_128 = 128 39 | } XAie_PlIfWidth; 40 | 41 | /************************** Function Prototypes *****************************/ 42 | AieRC XAie_PlIfBliBypassEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | u8 PortNum); 44 | AieRC XAie_PlIfBliBypassDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 45 | u8 PortNum); 46 | AieRC XAie_PlIfDownSzrEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 47 | u8 PortNum); 48 | AieRC XAie_PlIfDownSzrDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | u8 PortNum); 50 | AieRC XAie_PlToAieIntfEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | u8 PortNum, XAie_PlIfWidth Width); 52 | AieRC XAie_PlToAieIntfDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 53 | u8 PortNum, XAie_PlIfWidth Width); 54 | AieRC XAie_AieToPlIntfEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 55 | u8 PortNum, XAie_PlIfWidth Width); 56 | AieRC XAie_AieToPlIntfDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 57 | u8 PortNum, XAie_PlIfWidth Width); 58 | AieRC XAie_EnableShimDmaToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | u8 PortNum); 60 | AieRC XAie_EnableAieToShimDmaStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 61 | u8 PortNum); 62 | AieRC XAie_EnableNoCToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | u8 PortNum); 64 | AieRC XAie_EnableAieToNoCStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 65 | u8 PortNum); 66 | AieRC XAie_EnablePlToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 67 | u8 PortNum); 68 | AieRC XAie_EnableAieToPlStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 69 | u8 PortNum); 70 | #endif /* end of protection macro */ 71 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite.h 10 | * @{ 11 | * 12 | * This header file defines a lightweight version of AIE driver APIs. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0  Nishad  08/30/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_LITE_H 24 | #define XAIE_LITE_H 25 | 26 | #ifdef XAIE_FEATURE_LITE 27 | 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | #include "xaie_helper.h" 31 | 32 | #define XAie_LDeclareDevInst(DevInst, _BaseAddr, _StartCol, _NumCols) \ 33 | XAie_DevInst DevInst = { \ 34 | .BaseAddr = (_BaseAddr), \ 35 | .StartCol = (_StartCol), \ 36 | .NumCols = (_NumCols), \ 37 | .NumRows = (XAIE_NUM_ROWS), \ 38 | } 39 | 40 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 41 | #include "xaie_lite_aie.h" 42 | #include "xaie_lite_shim_aie.h" 43 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 44 | #include "xaie_lite_aieml.h" 45 | #include "xaie_lite_shim_aie.h" 46 | #else 47 | #include 48 | #endif 49 | 50 | #define XAIE_ERROR_MSG(...) \ 51 | "[AIE ERROR] %s():%d: %s", __func__, __LINE__, __VA_ARGS__ 52 | 53 | #ifdef XAIE_ENABLE_INPUT_CHECK 54 | #define XAIE_ERROR_RETURN(ERRCON, RET, ...) { \ 55 | if (ERRCON) { \ 56 | printf(__VA_ARGS__); \ 57 | return (RET); \ 58 | } \ 59 | } 60 | #else 61 | #define XAIE_ERROR_RETURN(...) 62 | #endif 63 | 64 | /************************** Variable Definitions *****************************/ 65 | /************************** Function Prototypes *****************************/ 66 | AieRC XAie_IsPartitionIdle(XAie_DevInst *DevInst); 67 | AieRC XAie_ClearPartitionContext(XAie_DevInst *DevInst); 68 | 69 | /************************** Function Definitions *****************************/ 70 | /*****************************************************************************/ 71 | /** 72 | * 73 | * This is API returns the location next NoC tile. 74 | * 75 | * @param DevInst: Device Instance 76 | * @param Loc: Location of the AIE tile. 77 | * 78 | * @note Internal only. 79 | * 80 | ******************************************************************************/ 81 | __FORCE_INLINE__ 82 | static inline XAie_LocType XAie_LPartGetNextNocTile(XAie_DevInst *DevInst, 83 | XAie_LocType Loc) 84 | { 85 | XAie_LocType lLoc = XAie_TileLoc((Loc.Col + DevInst->StartCol), 86 | Loc.Row); 87 | 88 | UPDT_NEXT_NOC_TILE_LOC(lLoc); 89 | return lLoc; 90 | } 91 | 92 | #endif /* XAIE_FEATURE_LITE */ 93 | 94 | #endif /* XAIE_LITE_H */ 95 | 96 | /** @} */ 97 | -------------------------------------------------------------------------------- /driver/src/trace/xaie_trace.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_trace.h 10 | * @{ 11 | * 12 | * Header file for AIE trace module. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Nishad  06/16/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_TRACE_H 24 | #define XAIE_TRACE_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | 29 | /**************************** Type Definitions *******************************/ 30 | /* This enum captures various states of a trace module */ 31 | typedef enum { 32 | XAIE_TRACE_IDLE, 33 | XAIE_TRACE_RUNNING, 34 | XAIE_TRACE_OVERRUN, 35 | } XAie_TraceState; 36 | 37 | /* This enum captures various trace modes */ 38 | typedef enum { 39 | XAIE_TRACE_EVENT_TIME, 40 | XAIE_TRACE_EVENT_PC, 41 | XAIE_TRACE_INST_EXEC, 42 | } XAie_TraceMode; 43 | 44 | /************************** Function Prototypes *****************************/ 45 | AieRC XAie_TraceEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 46 | XAie_ModuleType Module, XAie_Events Event, u8 SlotId); 47 | AieRC XAie_TraceStartEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | XAie_ModuleType Module, XAie_Events StartEvent); 49 | AieRC XAie_TraceStopEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | XAie_ModuleType Module, XAie_Events StopEvent); 51 | AieRC XAie_TracePktConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | XAie_ModuleType Module, XAie_Packet Pkt); 53 | AieRC XAie_TraceModeConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 54 | XAie_ModuleType Module, XAie_TraceMode Mode); 55 | AieRC XAie_TraceGetState(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | XAie_ModuleType Module, XAie_TraceState *State); 57 | AieRC XAie_TraceGetMode(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | XAie_ModuleType Module, XAie_TraceMode *Mode); 59 | AieRC XAie_TraceControlConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 60 | XAie_ModuleType Module, XAie_Events StartEvent, 61 | XAie_Events StopEvent, XAie_TraceMode Mode); 62 | AieRC XAie_TraceControlConfigReset(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | XAie_ModuleType Module); 64 | AieRC XAie_TracePktConfigReset(XAie_DevInst *DevInst, XAie_LocType Loc, 65 | XAie_ModuleType Module); 66 | AieRC XAie_TraceEventList(XAie_DevInst *DevInst, XAie_LocType Loc, 67 | XAie_ModuleType Module, XAie_Events *Events, u8 *SlotId, 68 | u8 NumEvents); 69 | AieRC XAie_TraceEventReset(XAie_DevInst *DevInst, XAie_LocType Loc, 70 | XAie_ModuleType Module, u8 SlotId); 71 | 72 | #endif /* end of protection macro */ 73 | -------------------------------------------------------------------------------- /driver/tests/utest/test_locks.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 5 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 6 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 7 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 8 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 9 | 10 | static XAie_InstDeclare(DevInst, &ConfigPtr); 11 | 12 | TEST_GROUP(LockApis) 13 | { 14 | void setup() 15 | { 16 | AieRC RC; 17 | 18 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 19 | CHECK_EQUAL(XAIE_OK, RC); 20 | 21 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 22 | CHECK_EQUAL(XAIE_OK, RC); 23 | } 24 | void teardown() 25 | { 26 | AieRC RC; 27 | 28 | RC = XAie_PartitionTeardown(&(DevInst)); 29 | CHECK_EQUAL(XAIE_OK, RC); 30 | 31 | XAie_Finish(&DevInst); 32 | } 33 | }; 34 | 35 | #if AIE_GEN != 3 36 | TEST(LockApis, ReleaseLockShimPlTile) 37 | { 38 | AieRC RC; 39 | 40 | RC = XAie_LockRelease(&DevInst, XAie_TileLoc(1, 0), XAie_LockInit(5, 1), 41 | 0); 42 | CHECK_EQUAL(XAIE_INVALID_TILE, RC); 43 | } 44 | #endif 45 | 46 | #if AIE_GEN >= 2 47 | TEST(LockApis, LockSetValue) 48 | { 49 | AieRC RC; 50 | 51 | RC = XAie_LockSetValue(&DevInst, XAie_TileLoc(8, 4), 52 | XAie_LockInit(5, 1)); 53 | CHECK_EQUAL(RC, XAIE_OK); 54 | 55 | RC = XAie_LockSetValue(&DevInst, XAie_TileLoc(8, 1), 56 | XAie_LockInit(11, 5)); 57 | CHECK_EQUAL(RC, XAIE_OK); 58 | 59 | RC = XAie_LockSetValue(&DevInst, XAie_TileLoc(2, 0), 60 | XAie_LockInit(3, 0)); 61 | CHECK_EQUAL(RC, XAIE_OK); 62 | 63 | } 64 | #endif 65 | 66 | TEST(LockApis, Negatives) 67 | { 68 | AieRC RC; 69 | 70 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 71 | 72 | RC = XAie_LockAcquire(NULL, TileLoc, XAie_LockInit(5, 1), 0); 73 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 74 | 75 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(25, 1), 0); 76 | CHECK_EQUAL(XAIE_INVALID_LOCK_ID, RC); 77 | 78 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 150), 0); 79 | CHECK_EQUAL(XAIE_INVALID_LOCK_VALUE, RC); 80 | 81 | RC = XAie_LockRelease(NULL, TileLoc, XAie_LockInit(5, 1), 0); 82 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 83 | 84 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(25, 1), 0); 85 | CHECK_EQUAL(XAIE_INVALID_LOCK_ID, RC); 86 | 87 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 150), 0); 88 | CHECK_EQUAL(XAIE_INVALID_LOCK_VALUE, RC); 89 | 90 | #if AIE_GEN != 3 91 | TileLoc = XAie_TileLoc(8,0); 92 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 93 | CHECK_EQUAL(XAIE_INVALID_TILE, RC); 94 | 95 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 96 | CHECK_EQUAL(XAIE_INVALID_TILE, RC); 97 | #endif 98 | 99 | DevInst.IsReady = 0; 100 | RC = XAie_LockAcquire(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 101 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 102 | 103 | RC = XAie_LockRelease(&DevInst, TileLoc, XAie_LockInit(5, 1), 0); 104 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 105 | 106 | DevInst.IsReady = 1; 107 | } 108 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_util.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 AMD. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_util.h 10 | * @{ 11 | * 12 | * This header file defines lightweight utility helpers for the AIE lite 13 | * driver. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who       Date        Changes
19 | * ----- --------  --------    ------------------------------------------------
20 | * 1.0  dsteger    07/10/2022  Initial creation
21 | * 1.1  avasi	  11/16/2022  Additions for Status Dump of Core Tile, Mem Tile
22 | *                             and Shim Tile registers.
23 | *
24 | * 25 | ******************************************************************************/ 26 | 27 | #ifndef XAIE_LITE_UTIL_H 28 | #define XAIE_LITE_UTIL_H 29 | 30 | #include "xaiegbl_defs.h" 31 | #include "xaie_lite_hwcfg.h" 32 | 33 | #if defined(XAIE_FEATURE_LITE_UTIL) 34 | /************************** Macro Definitions *****************************/ 35 | // To update these version numbers based on the changes made. 36 | #define VERSION_MAJOR 1 37 | #define VERSION_MINOR 1 38 | 39 | #define XAie_LGetColRangeBufSize(NumCols) { \ 40 | sizeof(XAie_Col_Status) * NumCols \ 41 | } 42 | 43 | /************************** Variable Definitions *****************************/ 44 | 45 | /* Data structure to capture the dma status */ 46 | typedef struct { 47 | u32 S2MMStatus; 48 | u32 MM2SStatus; 49 | } XAie_DmaStatus; 50 | 51 | /* Data structure to capture the core tile status */ 52 | typedef struct { 53 | XAie_DmaStatus dma[XAIE_TILE_DMA_NUM_CH]; 54 | u32 EventStatus[XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS]; 55 | u32 CoreStatus; 56 | u32 ProgramCounter; 57 | u32 StackPtr; 58 | u32 LinkReg; 59 | u8 LockValue[XAIE_TILE_NUM_LOCKS]; 60 | } XAie_Core_Tile_Status; 61 | 62 | /* Data structure to capture the mem tile status */ 63 | #if (XAIE_DEV_SINGLE_GEN != XAIE_DEV_GEN_AIE) 64 | typedef struct { 65 | XAie_DmaStatus dma[XAIE_MEM_TILE_DMA_NUM_CH]; 66 | u32 EventStatus[XAIE_MEM_TILE_NUM_EVENT_STATUS_REGS]; 67 | u8 LockValue[XAIE_MEM_TILE_NUM_LOCKS]; 68 | } XAie_Mem_Tile_Status; 69 | #endif 70 | 71 | /* Data structure to capture the shim tile status */ 72 | typedef struct { 73 | XAie_DmaStatus dma[XAIE_SHIM_DMA_NUM_CH]; 74 | u32 EventStatus[XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS]; 75 | u8 LockValue[XAIE_SHIM_NUM_LOCKS]; 76 | } XAie_Shim_Tile_Status; 77 | 78 | /* Data structure to capture column status */ 79 | typedef struct { 80 | XAie_Core_Tile_Status CoreTile[XAIE_AIE_TILE_NUM_ROWS]; 81 | #if (XAIE_DEV_SINGLE_GEN != XAIE_DEV_GEN_AIE) 82 | XAie_Mem_Tile_Status MemTile[XAIE_MEM_TILE_NUM_ROWS]; 83 | #endif 84 | XAie_Shim_Tile_Status ShimTile[XAIE_SHIM_NUM_ROWS]; 85 | } XAie_Col_Status; 86 | 87 | /************************** Function Prototypes *****************************/ 88 | #endif /* XAIE_FEATURE_LITE_UTIL */ 89 | 90 | #endif /* end of protection macro */ 91 | 92 | /** @} */ 93 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aie.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/23/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIE_H 25 | #define XAIE_DMA_AIE_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Function Prototypes *****************************/ 30 | void _XAie_TileDmaInit(XAie_DmaDesc *Desc); 31 | void _XAie_ShimDmaInit(XAie_DmaDesc *Desc); 32 | AieRC _XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock Acq, XAie_Lock Rel, 33 | u8 AcqEn, u8 RelEn); 34 | AieRC _XAie_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 35 | XAie_LocType Loc, u8 BdNum); 36 | AieRC _XAie_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 37 | XAie_LocType Loc, u8 BdNum); 38 | AieRC _XAie_TileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 39 | XAie_LocType Loc, u8 BdNum); 40 | AieRC _XAie_TileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 41 | XAie_LocType Loc, u8 BdNum); 42 | AieRC _XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, 43 | u8 IntrleaveCount, u16 IntrleaveCurr); 44 | AieRC _XAie_DmaSetMultiDim(XAie_DmaDesc *DmaDesc, XAie_DmaTensor *Tensor); 45 | AieRC _XAie_DmaGetPendingBdCount(XAie_DevInst *DevInst, XAie_LocType Loc, 46 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 47 | u8 *PendingBd); 48 | AieRC _XAie_DmaWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 50 | u32 TimeOutUs); 51 | AieRC _XAie_DmaGetChannelStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 53 | u32 *Status); 54 | AieRC _XAie_DmaCheckBdChValidity(u8 BdNum, u8 ChNum); 55 | AieRC _XAie_DmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 56 | XAie_LocType Loc, u32 Len, u16 BdNum); 57 | AieRC _XAie_ShimDmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 58 | XAie_LocType Loc, u32 Len, u16 BdNum); 59 | AieRC _XAie_DmaUpdateBdAddr(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 60 | XAie_LocType Loc, u64 Addr, u16 BdNum); 61 | AieRC _XAie_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 62 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 63 | u16 BdNum); 64 | AieRC _XAie_DmaSetBdIteration(XAie_DmaDesc *DmaDesc, u32 StepSize, u16 Wrap, 65 | u8 IterCurr); 66 | AieRC _XAie_AxiBurstLenCheck(u8 BurstLen, u8 *AxiBurstLen); 67 | #endif /* XAIE_DMA_AIE_H */ 68 | /** @} */ 69 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_tilectrl.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_tilectrl.c 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile controls. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Wendy   05/27/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | /***************************** Include Files *********************************/ 24 | 25 | #include "xaie_feature_config.h" 26 | #include "xaie_helper.h" 27 | #include "xaie_tilectrl.h" 28 | #include "xaiegbl_defs.h" 29 | 30 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 31 | 32 | /************************** Constant Definitions *****************************/ 33 | /************************** Function Definitions *****************************/ 34 | /*****************************************************************************/ 35 | /** 36 | * 37 | * This API sets isolation of a tile 38 | * 39 | * @param DevInst: Device Instance 40 | * @param Loc: tile location 41 | * @param Dir: directions to block, the direction input as: 42 | * XAIE_ISOLATE_EAST_MASK, 43 | * XAIE_ISOLATE_NORTH_MASK, 44 | * XAIE_ISOLATE_WEST_MASK, 45 | * XAIE_ISOLATE_SOUTH_MASK, 46 | * or "OR" operation of more than one of the above masks, 47 | * or XAIE_ISOLATE_ALL_MASK to block all directions. 48 | * 49 | * @return XAIE_OK on success, error code on failure 50 | * 51 | * @note It is not required to check the DevInst as the caller function 52 | * should provide the correct value. As this is internal function, 53 | * it will not verify the Dir input. 54 | * This is INTERNAL function. 55 | * 56 | ******************************************************************************/ 57 | AieRC _XAie_TileCtrlSetIsolation(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | u8 Dir) 59 | { 60 | const XAie_TileCtrlMod *TCtrlMod; 61 | u32 FldVal, Mask; 62 | u64 RegAddr; 63 | u8 TileType; 64 | 65 | TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 66 | if(TileType == XAIEGBL_TILE_TYPE_MAX) { 67 | XAIE_ERROR("Failed to set tile isolation, invalid tile type Col:%u Row:%u TileType:%u\n", Loc.Col, Loc.Row, TileType); 68 | return XAIE_ERR; 69 | } 70 | 71 | TCtrlMod = DevInst->DevProp.DevMod[TileType].TileCtrlMod; 72 | RegAddr = TCtrlMod->TileCtrlRegOff + 73 | XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col); 74 | Mask = TCtrlMod->IsolateEast.Mask | TCtrlMod->IsolateNorth.Mask | 75 | TCtrlMod->IsolateWest.Mask | TCtrlMod->IsolateSouth.Mask; 76 | /* 77 | * This is internal function, the Dir input masks matches the register 78 | * isolation mask, there is no need to calculate each direction bit. 79 | */ 80 | FldVal = XAie_SetField(Dir, 81 | TCtrlMod->IsolateSouth.Lsb, Mask); 82 | 83 | return XAie_Write32(DevInst, RegAddr, FldVal); 84 | } 85 | 86 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 87 | /** @} */ 88 | -------------------------------------------------------------------------------- /driver/tests/utest/test_btree4.cpp: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2024 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | #ifndef FILES_MISSING 6 | 7 | #include 8 | #include 9 | #include "CppUTest/TestHarness.h" 10 | 11 | extern "C" { 12 | #include "xaiengine/btree4.h" 13 | } 14 | 15 | #define TEST_BTREE4_SIZE 20000 16 | 17 | static uint64_t tmp; 18 | 19 | int cmp(void *a, void *b) 20 | { 21 | uint64_t x = (uint64_t)a; 22 | uint64_t y = (uint64_t)b; 23 | 24 | if (x < y) 25 | return -1; 26 | else if (x > y) 27 | return 1; 28 | return 0; 29 | } 30 | 31 | void visit(void *data, void *priv) 32 | { 33 | uint64_t v = (uint64_t)data; 34 | int *order_result = (int *)priv; 35 | 36 | if (*order_result) 37 | return; 38 | if (tmp > v) { 39 | *order_result = 1; 40 | return; 41 | } 42 | tmp = v; 43 | } 44 | 45 | int check_order(struct btree4 *tree) 46 | { 47 | int order_result = 0; 48 | tmp = 0; 49 | btree4_inorder_visit(tree, visit, (void *)&order_result); 50 | 51 | return order_result; 52 | } 53 | 54 | TEST_GROUP(BTree4) 55 | { 56 | void setup() 57 | { 58 | } 59 | void teardown() 60 | { 61 | } 62 | }; 63 | 64 | TEST(BTree4, BTree4_test) 65 | { 66 | uint64_t *data; 67 | uint64_t *random_index; 68 | ssize_t size = TEST_BTREE4_SIZE; 69 | BTREE4_DECLARE(tree, cmp); 70 | uint64_t i; 71 | uint64_t res; 72 | 73 | data = (uint64_t *)malloc(size * sizeof(*data)); 74 | CHECK(data != NULL); 75 | random_index = (uint64_t *)malloc(size * sizeof(*random_index)); 76 | CHECK(random_index != NULL); 77 | 78 | getrandom(data, size * sizeof(*data), GRND_NONBLOCK); 79 | getrandom(random_index, size * sizeof(*random_index), GRND_NONBLOCK); 80 | 81 | /* Insert */ 82 | for (i = 0; i < size; i++) { 83 | printf("\rInsert test: %ld%%", (i * 100) / size); 84 | fflush(stdout); 85 | if (data[i] == 0) 86 | continue; 87 | 88 | btree4_insert(&tree, (void *)data[i]); 89 | 90 | res = (uint64_t)btree4_search(&tree, (void *)data[i]); 91 | CHECK_EQUAL(res, data[i]); 92 | 93 | res = check_order(&tree); 94 | CHECK_EQUAL(res, 0); 95 | } 96 | printf("\n"); 97 | 98 | /* Search */ 99 | for (i = 0; i < size; i++) { 100 | printf("\rSearch test: %ld%%", (i * 100) / size); 101 | if (data[i] == 0) 102 | continue; 103 | res = (uint64_t)btree4_search(&tree, (void *)data[i]); 104 | CHECK_EQUAL(res, data[i]); 105 | } 106 | printf("\n"); 107 | 108 | /* Random Delete */ 109 | for (i = 0; i < size; i++) { 110 | printf("\rDelete test: %ld%%", (i * 100) / size); 111 | uint64_t index = random_index[i]; 112 | 113 | index %= size; 114 | if (data[index] == 0) 115 | continue; 116 | 117 | res = (uint64_t)btree4_delete(&tree, (void *)data[index]); 118 | CHECK_EQUAL(res, data[index]); 119 | 120 | res = check_order(&tree); 121 | CHECK_EQUAL(res, 0); 122 | 123 | res = (uint64_t)btree4_search(&tree, (void *)data[index]); 124 | CHECK_EQUAL(res, 0); 125 | 126 | for (uint64_t j = 0; j < size; j++) { 127 | if (data[index] == data[j]) 128 | data[j] = 0; 129 | } 130 | } 131 | printf("\n"); 132 | } 133 | #endif /*#ifndef FILES_MISSING*/ 134 | -------------------------------------------------------------------------------- /driver/src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2023 Advanced Micro Devices, Inc.. All rights reserved. 2 | # SPDX-License-Identifier: MIT 3 | cmake_minimum_required(VERSION 3.15) 4 | 5 | file(GLOB_RECURSE SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/*/*.c" "${CMAKE_CURRENT_SOURCE_DIR}/*/*/*.c") 6 | 7 | file(GLOB_RECURSE HEADERS "${CMAKE_CURRENT_SOURCE_DIR}/*/*.h" "${CMAKE_CURRENT_SOURCE_DIR}/*/*/*.h") 8 | 9 | if (NOT "$ENV{UTEST_BUILD}" STREQUAL "ON") 10 | project(aienginev2) 11 | 12 | find_package(common) 13 | include_directories(${CMAKE_BINARY_DIR}/include/xaiengine) 14 | 15 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/xaiengine.h DESTINATION ${CMAKE_BINARY_DIR}/include/) 16 | 17 | file(COPY ${HEADERS} DESTINATION ${CMAKE_BINARY_DIR}/include/xaiengine) 18 | 19 | add_library(aienginev2 STATIC ${SOURCES}) 20 | 21 | set_target_properties(aienginev2 PROPERTIES LINKER_LANGUAGE C) 22 | target_compile_options(aienginev2 PRIVATE -Wall -Wextra -D__AIEBAREMETAL__) 23 | 24 | else () 25 | project(xaiengine LANGUAGES C VERSION 3.8) 26 | 27 | set(CMAKE_C_STANDARD 11) 28 | 29 | set(CMAKE_POSITION_INDEPENDENT_CODE ON) 30 | 31 | set(CMAKE_WINDOWS_EXPORT_ALL_SYMBOLS TRUE) 32 | 33 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/xaiengine.h DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/include/) 34 | 35 | file(COPY ${HEADERS} DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/include/${PROJECT_NAME}) 36 | 37 | add_library( 38 | ${PROJECT_NAME} 39 | SHARED 40 | ${SOURCES} 41 | ) 42 | target_include_directories( 43 | ${PROJECT_NAME} 44 | PRIVATE 45 | ${CMAKE_CURRENT_BINARY_DIR}/include 46 | ${CMAKE_CURRENT_BINARY_DIR}/include/${PROJECT_NAME} 47 | ) 48 | set_target_properties( 49 | ${PROJECT_NAME} 50 | PROPERTIES 51 | VERSION 52 | ${PROJECT_VERSION} 53 | SOVERSION 54 | ${PROJECT_VERSION_MAJOR} 55 | ) 56 | 57 | if (LINUX_BACKEND) 58 | list(APPEND IO_BACKEND -D__AIELINUX__) 59 | endif (LINUX_BACKEND) 60 | if (METAL_BACKEND) 61 | list(APPEND IO_BACKEND -D__AIEMETAL__) 62 | endif (METAL_BACKEND) 63 | if (SOCKET_BACKEND) 64 | list(APPEND IO_BACKEND -D__AIESOCKET__) 65 | endif (SOCKET_BACKEND) 66 | if (DEBUG_BACKEND) 67 | list(APPEND IO_BACKEND -D__AIEDEBUG__) 68 | endif (DEBUG_BACKEND) 69 | if (SIM_BACKEND) 70 | list(APPEND IO_BACKEND -D__AIESIM__) 71 | endif (SIM_BACKEND) 72 | 73 | if(MSVC) 74 | target_compile_options(${PROJECT_NAME} PRIVATE /Wall -DXAIE_FEATURE_MSVC ${IO_BACKEND}) 75 | else() 76 | target_compile_options(${PROJECT_NAME} PRIVATE -Wall -Wextra ${IO_BACKEND}) 77 | endif() 78 | 79 | include(GNUInstallDirs) 80 | 81 | install( 82 | FILES 83 | ${HEADERS} 84 | DESTINATION 85 | ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} 86 | ) 87 | 88 | install( 89 | FILES 90 | ${CMAKE_CURRENT_SOURCE_DIR}/xaiengine.h 91 | DESTINATION 92 | ${CMAKE_INSTALL_INCLUDEDIR} 93 | ) 94 | 95 | install( 96 | TARGETS 97 | ${PROJECT_NAME} 98 | EXPORT ${PROJECT_NAME}-targets 99 | INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} 100 | RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} 101 | ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} 102 | LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} 103 | ) 104 | 105 | install( 106 | EXPORT ${PROJECT_NAME}-targets 107 | NAMESPACE ${PROJECT_NAME}:: 108 | COMPONENT runtime 109 | DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PROJECT_NAME} 110 | ) 111 | endif () 112 | -------------------------------------------------------------------------------- /driver/tests/utest/utest.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file utest.c 10 | * @{ 11 | * 12 | * This file contains unit test driver for . 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who           Date     Changes
 18 | * ----- ----------   -------- -----------------------------------------------------
 19 | * 1.0   siyuan sun   09/24/2019  Initial creation
 20 | 
 21 | *
22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | #define XAIE_DEBUG 27 | 28 | #include "aie_hw_config.h" 29 | 30 | 31 | 32 | #define XAIE_RES_TILE_ROW_START 0x20 33 | #define XAIE_RES_TILE_NUM_ROWS 3 34 | /* 35 | * Example op to send ifm, ofm. 36 | */ 37 | typedef struct { 38 | u64 ifm[6]; 39 | u64 ofm[6]; 40 | u32 flags; 41 | } __attribute__((packed, aligned(4))) dpu_op_1; 42 | 43 | /* 44 | * Example op for register poll; 45 | */ 46 | typedef struct { 47 | u32 addr; 48 | u32 timeout; 49 | } __attribute__((packed, aligned(4))) dpu_op_2; 50 | 51 | 52 | int main() { 53 | 54 | /* Initialize aie driver. */ 55 | XAie_SetupConfig(ConfigPtr, XAIE_DEV_GEN_AIE, XAIE_BASE_ADDR, 56 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 57 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 58 | XAIE_RES_TILE_ROW_START, XAIE_RES_TILE_NUM_ROWS, 59 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 60 | 61 | XAie_InstDeclare(DevInst, &ConfigPtr); 62 | 63 | XAie_CfgInitialize(&DevInst, &ConfigPtr); 64 | 65 | XAie_StartTransaction(&DevInst,XAIE_TRANSACTION_DISABLE_AUTO_FLUSH); 66 | 67 | int Op1 = XAie_RequestCustomTxnOp(&DevInst); 68 | int Op2 = XAie_RequestCustomTxnOp(&DevInst); 69 | 70 | if( -1 != Op1) { 71 | 72 | dpu_op_1 dpu_op1; 73 | dpu_op1.ifm[0] = 0xDEADBEEF; 74 | dpu_op1.ofm[0] = 0xBEEFDEAD; 75 | dpu_op1.flags = 1 << 5; 76 | 77 | /*test hexdump with the same function*/ 78 | printf("UNIT TEST LOG BEGIN>>>"); 79 | BuffHexDump(&dpu_op1,sizeof(dpu_op_1)); 80 | printf("\n<<>>"); 94 | BuffHexDump(&dpu_op2,sizeof(dpu_op_2)); 95 | printf("\n<<Enable, _XAieNpiMod.ProtRegEnable.Lsb, 84 | _XAieNpiMod.ProtRegEnable.Mask); 85 | 86 | return XAIE_OK; 87 | } 88 | 89 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 90 | /** @} */ 91 | -------------------------------------------------------------------------------- /driver/tests/utest/common/hw_config.h: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #ifndef HW_CONFIG_H 5 | #define HW_CONFIG_H 6 | 7 | #include 8 | 9 | #if AIE_GEN == XAIE_DEV_GEN_AIEML 10 | #define HW_GEN XAIE_DEV_GEN_AIEML 11 | #define XAIE_NUM_ROWS 11 12 | #define XAIE_NUM_COLS 38 13 | #define XAIE_BASE_ADDR 0x20000000000 14 | #define XAIE_COL_SHIFT 25 15 | #define XAIE_ROW_SHIFT 20 16 | #define XAIE_SHIM_ROW 0 17 | #define XAIE_MEM_TILE_ROW_START 1 18 | #define XAIE_MEM_TILE_NUM_ROWS 2 19 | #define XAIE_AIE_TILE_ROW_START 3 20 | #define XAIE_AIE_TILE_NUM_ROWS 8 21 | 22 | #elif AIE_GEN == XAIE_DEV_GEN_AIE 23 | #define HW_GEN XAIE_DEV_GEN_AIE 24 | #define XAIE_NUM_ROWS 9 25 | #define XAIE_NUM_COLS 50 26 | #define XAIE_BASE_ADDR 0x20000000000 27 | #define XAIE_COL_SHIFT 23 28 | #define XAIE_ROW_SHIFT 18 29 | #define XAIE_SHIM_ROW 0 30 | #define XAIE_MEM_TILE_ROW_START 0 31 | #define XAIE_MEM_TILE_NUM_ROWS 0 32 | #define XAIE_AIE_TILE_ROW_START 1 33 | #define XAIE_AIE_TILE_NUM_ROWS 8 34 | 35 | #elif AIE_GEN == XAIE_DEV_GEN_AIE2IPU 36 | #define HW_GEN XAIE_DEV_GEN_AIE2IPU 37 | #define XAIE_NUM_ROWS 6 38 | #define XAIE_NUM_COLS 5 39 | #define XAIE_BASE_ADDR 0x00000000000 40 | #define XAIE_COL_SHIFT 25 41 | #define XAIE_ROW_SHIFT 20 42 | #define XAIE_SHIM_ROW 0 43 | #define XAIE_MEM_TILE_ROW_START 1 44 | #define XAIE_MEM_TILE_NUM_ROWS 1 45 | #define XAIE_AIE_TILE_ROW_START 2 46 | #define XAIE_AIE_TILE_NUM_ROWS 4 47 | 48 | #elif AIE_GEN == XAIE_DEV_GEN_AIE2P 49 | #define HW_GEN XAIE_DEV_GEN_AIE2P 50 | #define XAIE_NUM_ROWS 6 51 | #define XAIE_NUM_COLS 4 52 | #define XAIE_BASE_ADDR 0x00000000000 53 | #define XAIE_COL_SHIFT 25 54 | #define XAIE_ROW_SHIFT 20 55 | #define XAIE_SHIM_ROW 0 56 | #define XAIE_MEM_TILE_ROW_START 1 57 | #define XAIE_MEM_TILE_NUM_ROWS 1 58 | #define XAIE_AIE_TILE_ROW_START 2 59 | #define XAIE_AIE_TILE_NUM_ROWS 4 60 | 61 | #elif AIE_GEN == XAIE_DEV_GEN_AIE2PS 62 | #define HW_GEN XAIE_DEV_GEN_AIE2PS 63 | #define XAIE_NUM_ROWS 8 64 | #define XAIE_NUM_COLS 20 65 | #define XAIE_BASE_ADDR 0x22000000000 66 | #define XAIE_COL_SHIFT 25 67 | #define XAIE_ROW_SHIFT 20 68 | #define XAIE_SHIM_ROW 0 69 | #define XAIE_MEM_TILE_ROW_START 1 70 | #define XAIE_MEM_TILE_NUM_ROWS 2 71 | #define XAIE_AIE_TILE_ROW_START 3 72 | #define XAIE_AIE_TILE_NUM_ROWS 5 73 | 74 | #elif AIE_GEN == XAIE_DEV_GEN_AIE2P_STRIX_A0 75 | #define HW_GEN XAIE_DEV_GEN_AIE2P_STRIX_A0 76 | #define XAIE_NUM_ROWS 6 77 | #define XAIE_NUM_COLS 4 78 | #define XAIE_BASE_ADDR 0x00000000000 79 | #define XAIE_COL_SHIFT 25 80 | #define XAIE_ROW_SHIFT 20 81 | #define XAIE_SHIM_ROW 0 82 | #define XAIE_MEM_TILE_ROW_START 1 83 | #define XAIE_MEM_TILE_NUM_ROWS 1 84 | #define XAIE_AIE_TILE_ROW_START 2 85 | #define XAIE_AIE_TILE_NUM_ROWS 4 86 | 87 | #elif AIE_GEN == XAIE_DEV_GEN_AIE2P_STRIX_B0 88 | #define HW_GEN XAIE_DEV_GEN_AIE2P_STRIX_B0 89 | #define XAIE_NUM_ROWS 6 90 | #define XAIE_NUM_COLS 8 91 | #define XAIE_BASE_ADDR 0x00000000000 92 | #define XAIE_COL_SHIFT 25 93 | #define XAIE_ROW_SHIFT 20 94 | #define XAIE_SHIM_ROW 0 95 | #define XAIE_MEM_TILE_ROW_START 1 96 | #define XAIE_MEM_TILE_NUM_ROWS 1 97 | #define XAIE_AIE_TILE_ROW_START 2 98 | #define XAIE_AIE_TILE_NUM_ROWS 4 99 | 100 | #endif 101 | 102 | #endif /* HW_CONFIG_H */ 103 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss.h 10 | * @{ 11 | * 12 | * Header file for stream switch implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Tejus   03/21/2020  Add stream switch packet switch mode apis
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIESS_H 26 | #define XAIESS_H 27 | 28 | /***************************** Include Files *********************************/ 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | #include "xaiegbl_defs.h" 32 | #include "xaie_helper.h" 33 | 34 | /**************************** Type Definitions *******************************/ 35 | /* Typedef to capture Packet drop header */ 36 | typedef enum { 37 | XAIE_SS_PKT_DONOT_DROP_HEADER, 38 | XAIE_SS_PKT_DROP_HEADER 39 | } XAie_StrmSwPktHeader; 40 | 41 | /************************** Function Prototypes *****************************/ 42 | AieRC XAie_StrmConnCctEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | StrmSwPortType Slave, u8 SlvPortNum, StrmSwPortType Master, 44 | u8 MstrPortNum); 45 | 46 | AieRC XAie_StrmConnCctDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 47 | StrmSwPortType Slave, u8 SlvPortNum, StrmSwPortType Master, 48 | u8 MstrPortNum); 49 | 50 | AieRC XAie_StrmPktSwMstrPortEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | StrmSwPortType Master, u8 MstrPortNum, 52 | XAie_StrmSwPktHeader DropHeader, u8 Arbitor, u8 MSelEn); 53 | 54 | AieRC XAie_StrmPktSwMstrPortDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 55 | StrmSwPortType Master, u8 MstrPortNum); 56 | 57 | AieRC XAie_StrmPktSwSlavePortEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | StrmSwPortType Slave, u8 SlvPortNum); 59 | 60 | AieRC XAie_StrmPktSwSlavePortDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 61 | StrmSwPortType Slave, u8 SlvPortNum); 62 | 63 | AieRC XAie_StrmPktSwSlaveSlotEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 64 | StrmSwPortType Slave, u8 SlvPortNum, u8 SlotNum, 65 | XAie_Packet Pkt, u8 Mask, u8 MSel, u8 Arbitor); 66 | 67 | AieRC XAie_StrmPktSwSlaveSlotDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 68 | StrmSwPortType Slave, u8 SlvPortNum, u8 SlotNum); 69 | AieRC XAie_StrmSwLogicalToPhysicalPort(XAie_DevInst *DevInst, XAie_LocType Loc, 70 | XAie_StrmPortIntf Port, StrmSwPortType PortType, u8 PortNum, 71 | u8 *PhyPortId); 72 | AieRC XAie_StrmSwPhysicalToLogicalPort(XAie_DevInst *DevInst, XAie_LocType Loc, 73 | XAie_StrmPortIntf Port, u8 PhyPortId, StrmSwPortType *PortType, 74 | u8 *PortNum); 75 | AieRC XAie_StrmSwDeterministicMergeConfig(XAie_DevInst *DevInst, 76 | XAie_LocType Loc, u8 Arbitor, StrmSwPortType Slave, u8 PortNum, 77 | u8 PktCount, u8 Position); 78 | AieRC XAie_StrmSwDeterministicMergeEnable(XAie_DevInst *DevInst, 79 | XAie_LocType Loc, u8 Arbitor); 80 | AieRC XAie_StrmSwDeterministicMergeDisable(XAie_DevInst *DevInst, 81 | XAie_LocType Loc, u8 Arbitor); 82 | 83 | #endif /* end of protection macro */ 84 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_hwcfg.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_hwcfg.h 10 | * @{ 11 | * 12 | * This header file capture hardware configurations for all supported devices. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who       Date        Changes
 18 | * ----- --------  --------    ------------------------------------------------
 19 | * 1.0  Nishad     06/23/2022  Initial creation
 20 | * 1.1  avasi      11/16/2022  Additions for Status Dump of Core Tile, Mem Tile
 21 | *                             and Shim Tile registers.
 22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIE_LITE_HWCFG_H 26 | #define XAIE_LITE_HWCFG_H 27 | 28 | #ifdef XAIE_FEATURE_LITE 29 | 30 | /***************************** Include Files *********************************/ 31 | /************************** Constant Definitions *****************************/ 32 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 33 | 34 | #ifndef XAIE_BASE_ADDR 35 | #define XAIE_BASE_ADDR 0x20000000000 36 | #endif 37 | 38 | #ifndef XAIE_NPI_BASEADDR 39 | #define XAIE_NPI_BASEADDR 0xF70A0000 40 | #endif 41 | 42 | #ifndef XAIE_NUM_ROWS 43 | #define XAIE_NUM_ROWS 9 44 | #endif 45 | 46 | #ifndef XAIE_NUM_COLS 47 | #define XAIE_NUM_COLS 50 48 | #endif 49 | 50 | #define XAIE_TILE_NUM_LOCKS 16 51 | #define XAIE_SHIM_NUM_LOCKS 16 52 | 53 | #define XAIE_TILE_DMA_NUM_CH 2U 54 | #define XAIE_SHIM_DMA_NUM_CH 2U 55 | 56 | #define XAIE_COL_SHIFT 23 57 | #define XAIE_ROW_SHIFT 18 58 | #define XAIE_SHIM_ROW 0 59 | #define XAIE_SHIM_NUM_ROWS 1 60 | #define XAIE_MEM_TILE_ROW_START 0 61 | #define XAIE_MEM_TILE_NUM_ROWS 0 62 | #define XAIE_AIE_TILE_ROW_START 1 63 | #define XAIE_AIE_TILE_NUM_ROWS 8 64 | #define XAIE_NUM_NOC_INTR_OFFSET 1 65 | 66 | #define XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS 4 67 | #define XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS 4 68 | 69 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 70 | 71 | #ifndef XAIE_BASE_ADDR 72 | #define XAIE_BASE_ADDR 0x20000000000 73 | #endif 74 | 75 | #ifndef XAIE_NPI_BASEADDR 76 | #define XAIE_NPI_BASEADDR 0xF6D10000 77 | #endif 78 | 79 | #ifndef XAIE_NUM_ROWS 80 | #define XAIE_NUM_ROWS 11 81 | #endif 82 | 83 | #ifndef XAIE_NUM_COLS 84 | #define XAIE_NUM_COLS 38 85 | #endif 86 | 87 | #define XAIE_TILE_NUM_LOCKS 16 88 | #define XAIE_MEM_TILE_NUM_LOCKS 64 89 | #define XAIE_SHIM_NUM_LOCKS 16 90 | 91 | #define XAIE_TILE_DMA_NUM_CH 2U 92 | #define XAIE_MEM_TILE_DMA_NUM_CH 6U 93 | #define XAIE_SHIM_DMA_NUM_CH 2U 94 | 95 | #define XAIE_COL_SHIFT 25 96 | #define XAIE_ROW_SHIFT 20 97 | #define XAIE_SHIM_ROW 0 98 | #define XAIE_SHIM_NUM_ROWS 1 99 | #define XAIE_MEM_TILE_ROW_START 1 100 | #define XAIE_MEM_TILE_NUM_ROWS 2 101 | #define XAIE_AIE_TILE_ROW_START 3 102 | #define XAIE_AIE_TILE_NUM_ROWS 8 103 | #define XAIE_NUM_NOC_INTR_OFFSET 1 104 | 105 | #define XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS 4 106 | #define XAIE_MEM_TILE_NUM_EVENT_STATUS_REGS 6 107 | #define XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS 4 108 | 109 | #else 110 | #include 111 | #endif 112 | 113 | #endif /* XAIE_FEATURE_LITE */ 114 | #endif /* end of protection macro */ 115 | 116 | /** @} */ 117 | -------------------------------------------------------------------------------- /driver/tests/stest/hw_config.h: -------------------------------------------------------------------------------- 1 | #ifndef HW_CONFIG_H 2 | #define HW_CONFIG_H 3 | 4 | #if AIE_GEN == 1 5 | 6 | #define HW_GEN XAIE_DEV_GEN_AIE 7 | #define XAIE_BASE_ADDR 0x20000000000 8 | #define XAIE_COL_SHIFT 23 9 | #define XAIE_ROW_SHIFT 18 10 | 11 | #if DEVICE == 80 12 | #define XAIE_NUM_ROWS 9 13 | #define XAIE_NUM_COLS 50 14 | #define XAIE_SHIM_ROW 0 15 | #define XAIE_MEM_TILE_ROW_START 0 16 | #define XAIE_MEM_TILE_NUM_ROWS 0 17 | #define XAIE_AIE_TILE_ROW_START 1 18 | #define XAIE_AIE_TILE_NUM_ROWS 8 19 | 20 | #elif DEVICE == 0 /* SystemC Config */ 21 | #define XAIE_NUM_ROWS 4 22 | #define XAIE_NUM_COLS 5 23 | #define XAIE_SHIM_ROW 0 24 | #define XAIE_MEM_TILE_ROW_START 0 25 | #define XAIE_MEM_TILE_NUM_ROWS 0 26 | #define XAIE_AIE_TILE_ROW_START 1 27 | #define XAIE_AIE_TILE_NUM_ROWS 3 28 | #endif /* DEVICE */ 29 | 30 | /* AIE_GEN = 2 by default for now. */ 31 | #elif AIE_GEN == 2 32 | 33 | #define HW_GEN XAIE_DEV_GEN_AIEML 34 | #define XAIE_BASE_ADDR 0x20000000000 35 | #define XAIE_COL_SHIFT 25 36 | #define XAIE_ROW_SHIFT 20 37 | 38 | #if DEVICE == 60 39 | #define XAIE_NUM_ROWS 11 40 | #define XAIE_NUM_COLS 38 41 | #define XAIE_SHIM_ROW 0 42 | #define XAIE_MEM_TILE_ROW_START 1 43 | #define XAIE_MEM_TILE_NUM_ROWS 2 44 | #define XAIE_AIE_TILE_ROW_START 3 45 | #define XAIE_AIE_TILE_NUM_ROWS 8 46 | 47 | #elif DEVICE == 0 /* SystemC Config */ 48 | #define XAIE_NUM_ROWS 6 49 | #define XAIE_NUM_COLS 5 50 | #define XAIE_SHIM_ROW 0 51 | #define XAIE_MEM_TILE_ROW_START 1 52 | #define XAIE_MEM_TILE_NUM_ROWS 1 53 | #define XAIE_AIE_TILE_ROW_START 2 54 | #define XAIE_AIE_TILE_NUM_ROWS 4 55 | #endif /* DEVICE */ 56 | 57 | #elif AIE_GEN == 3 58 | 59 | #define HW_GEN XAIE_DEV_GEN_AIE2IPU 60 | #define XAIE_BASE_ADDR 0x20000000000 61 | #define XAIE_COL_SHIFT 25 62 | #define XAIE_ROW_SHIFT 20 63 | 64 | /* SystemC Config */ 65 | #define XAIE_NUM_ROWS 6 66 | #define XAIE_NUM_COLS 5 67 | #define XAIE_SHIM_ROW 0 68 | #define XAIE_MEM_TILE_ROW_START 1 69 | #define XAIE_MEM_TILE_NUM_ROWS 1 70 | #define XAIE_AIE_TILE_ROW_START 2 71 | #define XAIE_AIE_TILE_NUM_ROWS 4 72 | 73 | #elif AIE_GEN == 4 74 | 75 | #define HW_GEN XAIE_DEV_GEN_AIE2P 76 | #define XAIE_BASE_ADDR 0x20000000000 77 | #define XAIE_COL_SHIFT 25 78 | #define XAIE_ROW_SHIFT 20 79 | 80 | /* SystemC Config */ 81 | #define XAIE_NUM_ROWS 6 82 | #define XAIE_NUM_COLS 5 83 | #define XAIE_SHIM_ROW 0 84 | #define XAIE_MEM_TILE_ROW_START 1 85 | #define XAIE_MEM_TILE_NUM_ROWS 1 86 | #define XAIE_AIE_TILE_ROW_START 2 87 | #define XAIE_AIE_TILE_NUM_ROWS 4 88 | 89 | #elif AIE_GEN == 5 90 | 91 | #define HW_GEN XAIE_DEV_GEN_AIE2PS 92 | #define XAIE_COL_SHIFT 25 93 | #define XAIE_ROW_SHIFT 20 94 | 95 | #if DEVICE == 80 /* IPP Config */ 96 | #define XAIE_BASE_ADDR 0x22000000000 97 | #define XAIE_NUM_ROWS 7 98 | #define XAIE_NUM_COLS 4 99 | #define XAIE_SHIM_ROW 0 100 | #define XAIE_MEM_TILE_ROW_START 1 101 | #define XAIE_MEM_TILE_NUM_ROWS 2 102 | #define XAIE_AIE_TILE_ROW_START 3 103 | #define XAIE_AIE_TILE_NUM_ROWS 4 104 | 105 | #elif DEVICE == 0 /* systemc Config */ 106 | #define XAIE_BASE_ADDR 0x20000000000 107 | #define XAIE_NUM_ROWS 4 108 | #define XAIE_NUM_COLS 5 109 | #define XAIE_SHIM_ROW 0 110 | #define XAIE_MEM_TILE_ROW_START 1 111 | #define XAIE_MEM_TILE_NUM_ROWS 1 112 | #define XAIE_AIE_TILE_ROW_START 2 113 | #define XAIE_AIE_TILE_NUM_ROWS 2 114 | 115 | #endif /* DEVICE */ 116 | #endif /* AIE_GEN */ 117 | #endif /* HW_CONFIG_H */ 118 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aieml.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/23/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIEML_H 25 | #define XAIE_DMA_AIEML_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | 30 | /************************** Function Prototypes *****************************/ 31 | void _XAieMl_ShimDmaInit(XAie_DmaDesc *Desc); 32 | void _XAieMl_TileDmaInit(XAie_DmaDesc *Desc); 33 | void _XAieMl_MemTileDmaInit(XAie_DmaDesc *Desc); 34 | AieRC _XAieMl_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock Acq, XAie_Lock Rel, 35 | u8 AcqEn, u8 RelEn); 36 | AieRC _XAieMl_MemTileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 37 | XAie_LocType Loc, u8 BdNum); 38 | AieRC _XAieMl_MemTileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 39 | XAie_LocType Loc, u8 BdNum); 40 | AieRC _XAieMl_TileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 41 | XAie_LocType Loc, u8 BdNum); 42 | AieRC _XAieMl_TileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 43 | XAie_LocType Loc, u8 BdNum); 44 | AieRC _XAieMl_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 45 | XAie_LocType Loc, u8 BdNum); 46 | AieRC _XAieMl_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 47 | XAie_LocType Loc, u8 BdNum); 48 | AieRC _XAieMl_DmaSetMultiDim(XAie_DmaDesc *DmaDesc, XAie_DmaTensor *Tensor); 49 | AieRC _XAieMl_DmaGetPendingBdCount(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 51 | u8 *PendingBd); 52 | AieRC _XAieMl_DmaWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 53 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 54 | u32 TimeOutUs); 55 | AieRC _XAieMl_DmaWaitForBdTaskQueue(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 57 | u32 TimeOutUs); 58 | AieRC _XAieMl_DmaGetChannelStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 60 | u32 *Status); 61 | AieRC _XAieMl_DmaCheckBdChValidity(u8 BdNum, u8 ChNum); 62 | AieRC _XAieMl_MemTileDmaCheckBdChValidity(u8 BdNum, u8 ChNum); 63 | AieRC _XAieMl_DmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 64 | XAie_LocType Loc, u32 Len, u16 BdNum); 65 | AieRC _XAieMl_ShimDmaUpdateBdLen(XAie_DevInst *DevInst, 66 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u32 Len, u16 BdNum); 67 | AieRC _XAieMl_DmaUpdateBdAddr(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 68 | XAie_LocType Loc, u64 Addr, u16 BdNum); 69 | AieRC _XAieMl_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 70 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 71 | u16 BdNum); 72 | AieRC _XAieMl_DmaSetBdIteration(XAie_DmaDesc *DmaDesc, u32 StepSize, u16 Wrap, 73 | u8 IterCurr); 74 | AieRC _XAie_AxiBurstLenCheck(u8 BurstLen, u8 *AxiBurstLen); 75 | 76 | #endif /* XAIE_DMA_AIEML_H */ 77 | /** @} */ 78 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt.h 10 | * @{ 11 | * 12 | * Header file for AIE interrupt module. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Nishad  07/21/2020  Initial creation
20 | * 1.1   Nishad  07/23/2020  Add APIs to configure second level interrupt
21 | *			    controller.
22 | * 1.2   Nishad  07/23/2020  Add API to initialize error broadcast network.
23 | * 1.3   Nishad  08/13/2020  Add macro for error broadcast mask.
24 | *
25 | * 26 | ******************************************************************************/ 27 | #ifndef XAIE_INTERRUPT_H 28 | #define XAIE_INTERRUPT_H 29 | 30 | /***************************** Include Files *********************************/ 31 | #include "xaie_events.h" 32 | #include "xaie_core.h" 33 | 34 | /**************************** Type Definitions *******************************/ 35 | #define XAIE_ERROR_BROADCAST_ID 0x0U 36 | #define XAIE_ERROR_BROADCAST_MASK 0x1U 37 | 38 | #define XAIE_ERROR_BROADCAST_ID_UC_EVENT 0x1U 39 | #define XAIE_ERROR_BROADCAST_ID_USER_EVENT1 0x2U 40 | 41 | #define XAIE_ERROR_SHIM_INTR_ID 0x10U 42 | #define XAIE_ERROR_SHIM_INTR_MASK 0x10000U 43 | #define XAIE_ERROR_NPI_INTR_ID 0x1U 44 | #define XAIE_ERROR_L2_ENABLE 0x3FU 45 | 46 | /************************** Function Prototypes *****************************/ 47 | AieRC XAie_IntrCtrlL1Enable(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | XAie_BroadcastSw Switch, u8 IntrId); 49 | AieRC XAie_IntrCtrlL1Disable(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | XAie_BroadcastSw Switch, u8 IntrId); 51 | AieRC XAie_IntrCtrlL1IrqSet(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | XAie_BroadcastSw Switch, u8 BroadcastId); 53 | AieRC XAie_IntrCtrlL1Event(XAie_DevInst *DevInst, XAie_LocType Loc, 54 | XAie_BroadcastSw Switch, u8 IrqEventId, XAie_Events Event); 55 | AieRC XAie_IntrCtrlL1BroadcastBlock(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | XAie_BroadcastSw Switch, u32 ChannelBitMap); 57 | AieRC XAie_IntrCtrlL1BroadcastUnblock(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | XAie_BroadcastSw Switch, u32 ChannelBitMap); 59 | u32 XAie_IntrCtrlL1Status(XAie_DevInst *DevInst, 60 | XAie_LocType Loc, XAie_BroadcastSw Switch); 61 | u32 XAie_IntrCtrlL2Mask(XAie_DevInst *DevInst, XAie_LocType Loc); 62 | AieRC XAie_IntrCtrlL2Enable(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | u32 ChannelBitMap); 64 | u32 XAie_IntrCtrlL2Status(XAie_DevInst *DevInst, XAie_LocType Loc); 65 | AieRC XAie_IntrCtrlL2Disable(XAie_DevInst *DevInst, XAie_LocType Loc, 66 | u32 ChannelBitMap); 67 | AieRC XAie_ErrorHandlingInit(XAie_DevInst *DevInst); 68 | void XAie_DisableErrorInterrupts(u8 IrqId); 69 | AieRC XAie_IntrCtrlL2Ack(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Status); 70 | 71 | AieRC XAie_BacktrackErrorInterrupts(XAie_DevInst *DevInst, 72 | XAie_ErrorMetaData *MData); 73 | void XAie_IntrCtrlL1Ack(XAie_DevInst *DevInst, 74 | XAie_LocType Loc, XAie_BroadcastSw Switch, 75 | u32 ChannelBitMap); 76 | u8 XAie_EventReadStatusHw(XAie_DevInst *DevInst, 77 | XAie_LocType Loc, XAie_ModuleType Module, u8 Event); 78 | void XAie_EventClearStatus(XAie_DevInst *DevInst, 79 | XAie_LocType Loc, XAie_ModuleType Module, u8 Event); 80 | 81 | #endif /* end of protection macro */ 82 | /** @} */ 83 | -------------------------------------------------------------------------------- /driver/src/perfcnt/xaie_perfcnt.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_perfcnt.h 10 | * @{ 11 | * 12 | * Header file for performance counter implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date     Changes
18 | * ----- ------   -------- -----------------------------------------------------
19 | * 1.0   Dishita  11/21/2019  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIEPERFCNT_H 24 | #define XAIEPERFCNT_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | #include "xaie_helper.h" 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | 32 | /************************** Function Prototypes *****************************/ 33 | AieRC XAie_PerfCounterGet(XAie_DevInst *DevInst, XAie_LocType Loc, 34 | XAie_ModuleType Module, u8 Counter, u32 *CounterVal); 35 | AieRC XAie_PerfCounterGetOffset(XAie_DevInst *DevInst, XAie_LocType Loc, 36 | XAie_ModuleType Module, u8 Counter, u64 *Offset); 37 | AieRC XAie_PerfCounterControlSet(XAie_DevInst *DevInst, XAie_LocType Loc, 38 | XAie_ModuleType Module, u8 Counter, XAie_Events StartEvent, 39 | XAie_Events StopEvent); 40 | AieRC XAie_PerfCounterResetControlSet(XAie_DevInst *DevInst, XAie_LocType Loc, 41 | XAie_ModuleType Module, u8 Counter, XAie_Events ResetEvent); 42 | AieRC XAie_PerfCounterSet(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | XAie_ModuleType Module, u8 Counter, u32 CounterVal); 44 | AieRC XAie_PerfCounterEventValueSet(XAie_DevInst *DevInst, XAie_LocType Loc, 45 | XAie_ModuleType Module, u8 Counter, u32 EventVal); 46 | AieRC XAie_PerfCounterControlReset(XAie_DevInst *DevInst, XAie_LocType Loc, 47 | XAie_ModuleType Module, u8 Counter); 48 | AieRC XAie_PerfCounterResetControlReset(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | XAie_ModuleType Module, u8 Counter); 50 | AieRC XAie_PerfCounterReset(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | XAie_ModuleType Module, u8 Counter); 52 | AieRC XAie_PerfCounterEventValueReset(XAie_DevInst *DevInst, XAie_LocType Loc, 53 | XAie_ModuleType Module, u8 Counter); 54 | AieRC XAie_PerfCounterGetControlConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 55 | XAie_ModuleType Module, u8 Counter, XAie_Events *StartEvent, 56 | XAie_Events *StopEvent, XAie_Events *ResetEvent); 57 | AieRC XAie_PerfCounterGetEventBase(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | XAie_ModuleType Module, XAie_Events *Event); 59 | AieRC XAie_MdmPerfCounterGet(XAie_DevInst *DevInst, XAie_LocType Loc, 60 | u32 *CounterVal); 61 | AieRC XAie_MdmPerfCounterGetConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 62 | u8 *NumEvntCounter, u8 *NumLatCounter, u8 *CounterWidth); 63 | AieRC XAie_MdmPerfCounterGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 64 | u8 *CounterStatus); 65 | AieRC XAie_MdmPerfCounterControlSet(XAie_DevInst *DevInst, XAie_LocType Loc, 66 | u8 *UcEvents); 67 | AieRC XAie_MdmPerfCounterControlReset(XAie_DevInst *DevInst, XAie_LocType Loc); 68 | AieRC XAie_MdmPerfCounterSet(XAie_DevInst *DevInst, XAie_LocType Loc, 69 | u32 *CounterVal); 70 | AieRC XAie_MdmPerfCounterReset(XAie_DevInst *DevInst, XAie_LocType Loc); 71 | AieRC XAie_MdmPerfCounterGetControlConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 72 | u8 *UcEvents); 73 | AieRC XAie_MdmPerfCounterStart(XAie_DevInst *DevInst, XAie_LocType Loc); 74 | AieRC XAie_MdmPerfCounterStop(XAie_DevInst *DevInst, XAie_LocType Loc, 75 | u8 SampleEnable); 76 | AieRC XAie_MdmPerfCounterSample(XAie_DevInst *DevInst, XAie_LocType Loc); 77 | #endif /* end of protection macro */ 78 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aie.c 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets for AIE 13 | * 14 | ******************************************************************************/ 15 | /***************************** Include Files *********************************/ 16 | #include "xaie_feature_config.h" 17 | #include "xaie_helper.h" 18 | #include "xaiegbl.h" 19 | 20 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 21 | 22 | /*****************************************************************************/ 23 | /***************************** Macro Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * 28 | * This API set the SHIM tile reset 29 | * 30 | * @param DevInst: Device Instance 31 | * @param Loc: Location of AIE SHIM tile 32 | * @param RstEnable: XAIE_ENABLE to enable reset, XAIE_DISABLE to 33 | * disable reset. 34 | * 35 | * @return none 36 | * 37 | * @note It is not required to check the DevInst and the Loc tile type 38 | * as the caller function should provide the correct value. 39 | * 40 | ******************************************************************************/ 41 | static void _XAie_RstSetShimReset(XAie_DevInst *DevInst, XAie_LocType Loc, 42 | u8 RstEnable) 43 | { 44 | u8 TileType; 45 | u32 FldVal; 46 | u64 RegAddr; 47 | const XAie_PlIfMod *PlIfMod; 48 | const XAie_ShimRstMod *ShimTileRst; 49 | 50 | TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 51 | PlIfMod = DevInst->DevProp.DevMod[TileType].PlIfMod; 52 | ShimTileRst = PlIfMod->ShimTileRst; 53 | 54 | RegAddr = ShimTileRst->RegOff + 55 | XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col); 56 | FldVal = XAie_SetField(RstEnable, 57 | ShimTileRst->RstCntr.Lsb, 58 | ShimTileRst->RstCntr.Mask); 59 | 60 | XAie_Write32(DevInst, RegAddr, FldVal); 61 | } 62 | 63 | /*****************************************************************************/ 64 | /** 65 | * 66 | * This API reset the SHIM for the specified columns 67 | * 68 | * @param DevInst: Device Instance 69 | * @param StartCol: Start column 70 | * @param NumCols: Number of columns 71 | * 72 | * @return XAIE_OK 73 | * 74 | * @note It is not required to check the DevInst as the caller function 75 | * should provide the correct value. Also it will not check the 76 | * @StartCol nor the @NumCols, the caller function should do the 77 | * validation and provide the correct values. This function does 78 | * the following steps: 79 | * * Set reset bit for every SHIM 80 | * * Assert SHIM reset 81 | * * Deassert SHIM reset 82 | * * Unset reset bit for every SHIM 83 | * 84 | ******************************************************************************/ 85 | AieRC _XAie_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols) 86 | { 87 | for (u8 C = StartCol; C < (StartCol + NumCols); C++) { 88 | XAie_LocType Loc = XAie_TileLoc(C, 0); 89 | 90 | _XAie_RstSetShimReset(DevInst, Loc, XAIE_ENABLE); 91 | } 92 | 93 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 94 | (void *)(uintptr_t)XAIE_ENABLE); 95 | 96 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 97 | (void *)(uintptr_t)XAIE_DISABLE); 98 | 99 | for (u8 C = StartCol; C < (StartCol + NumCols); C++) { 100 | XAie_LocType Loc = XAie_TileLoc(C, 0); 101 | 102 | _XAie_RstSetShimReset(DevInst, Loc, XAIE_DISABLE); 103 | } 104 | 105 | return XAIE_OK; 106 | } 107 | 108 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 109 | /** @} */ 110 | -------------------------------------------------------------------------------- /driver/tests/utest/test_pm.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN != 4 5 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 6 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 7 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 8 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 9 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 10 | 11 | static XAie_InstDeclare(DevInst, &ConfigPtr); 12 | 13 | TEST_GROUP(PmApis) 14 | { 15 | void setup() 16 | { 17 | AieRC RC; 18 | 19 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 20 | CHECK_EQUAL(XAIE_OK, RC); 21 | 22 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 23 | CHECK_EQUAL(XAIE_OK, RC); 24 | } 25 | void teardown() 26 | { 27 | AieRC RC; 28 | 29 | RC = XAie_PartitionTeardown(&(DevInst)); 30 | CHECK_EQUAL(XAIE_OK, RC); 31 | 32 | XAie_Finish(&DevInst); 33 | } 34 | }; 35 | 36 | TEST(PmApis, PmAllTiles) 37 | { 38 | AieRC RC; 39 | 40 | XAie_LocType TileLoc = XAie_TileLoc(1, 0); 41 | 42 | XAie_LocType TilesToRequest[4]; 43 | TilesToRequest[0].Col = 3; 44 | TilesToRequest[0].Row = 5; 45 | TilesToRequest[1].Col = 5; 46 | TilesToRequest[1].Row = 3; 47 | 48 | RC = XAie_PmRequestTiles(&DevInst, TilesToRequest, 2); 49 | CHECK_EQUAL(XAIE_OK, RC); 50 | 51 | if(DevInst.Backend->Type != XAIE_IO_BACKEND_LINUX) { 52 | RC = XAie_ResetPartition(&DevInst); 53 | CHECK_EQUAL(XAIE_OK, RC); 54 | } 55 | 56 | RC = XAie_ClearPartitionMems(&DevInst); 57 | CHECK_EQUAL(XAIE_OK, RC); 58 | 59 | RC = XAie_PmRequestTiles(&DevInst, &TileLoc, 1); 60 | CHECK_EQUAL(XAIE_OK, RC); 61 | 62 | RC = XAie_PmRequestTiles(&DevInst, NULL, 0); 63 | CHECK_EQUAL(XAIE_OK, RC); 64 | 65 | XAie_LocType Tiles[4]; 66 | Tiles[0].Col = 3; 67 | Tiles[0].Row = 3; 68 | Tiles[1].Col = 3; 69 | Tiles[1].Row = 4; 70 | Tiles[2].Col = 2; 71 | Tiles[2].Row = 4; 72 | Tiles[3].Col = 2; 73 | Tiles[3].Row = 3; 74 | 75 | RC = XAie_PmRequestTiles(&DevInst, Tiles, 4); 76 | CHECK_EQUAL(XAIE_OK, RC); 77 | 78 | RC = XAie_ClearPartitionMems(&DevInst); 79 | CHECK_EQUAL(XAIE_OK, RC); 80 | } 81 | 82 | TEST_GROUP(PmNegs) 83 | { 84 | void setup() 85 | { 86 | AieRC RC; 87 | 88 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 89 | CHECK_EQUAL(XAIE_OK, RC); 90 | 91 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 92 | CHECK_EQUAL(XAIE_OK, RC); 93 | } 94 | void teardown() 95 | { 96 | AieRC RC; 97 | 98 | RC = XAie_PartitionTeardown(&(DevInst)); 99 | CHECK_EQUAL(XAIE_OK, RC); 100 | 101 | XAie_Finish(&DevInst); 102 | } 103 | }; 104 | 105 | TEST(PmNegs, InvalidArgs) 106 | { 107 | AieRC RC; 108 | 109 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 110 | 111 | RC = XAie_PmRequestTiles(NULL, NULL, 2); 112 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 113 | 114 | RC = XAie_PmRequestTiles(&DevInst, &TileLoc, 100022); 115 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 116 | 117 | XAie_LocType Tiles[4]; 118 | Tiles[0].Col = 3; 119 | Tiles[0].Row = 3; 120 | Tiles[1].Col = 3; 121 | Tiles[1].Row = XAIE_NUM_ROWS+3; 122 | Tiles[2].Col = XAIE_NUM_COLS+2; 123 | Tiles[2].Row = 4; 124 | Tiles[3].Col = 2; 125 | Tiles[3].Row = 3; 126 | 127 | RC = XAie_PmRequestTiles(&DevInst, Tiles, 4); 128 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 129 | 130 | Tiles[1].Row = 3; 131 | Tiles[1].Col = XAIE_NUM_COLS + 2; 132 | 133 | RC = XAie_PmRequestTiles(&DevInst, Tiles, 4); 134 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 135 | 136 | RC = XAie_ClearPartitionMems(NULL); 137 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 138 | 139 | RC = XAie_ResetPartition(NULL); 140 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 141 | 142 | DevInst.IsReady = 0; 143 | 144 | RC = XAie_ClearPartitionMems(&DevInst); 145 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 146 | 147 | RC = XAie_ResetPartition(&DevInst); 148 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 149 | 150 | RC = XAie_PmRequestTiles(&DevInst, Tiles, 4); 151 | CHECK_EQUAL(XAIE_INVALID_ARGS, RC); 152 | 153 | DevInst.IsReady = 1; 154 | } 155 | 156 | #endif 157 | -------------------------------------------------------------------------------- /driver/tests/utest/test_dma_aie.cpp: -------------------------------------------------------------------------------- 1 | #include "CppUTest/TestHarness.h" 2 | #include 3 | 4 | #if AIE_GEN == 1 5 | 6 | static XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 7 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 8 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 9 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 10 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 11 | 12 | static XAie_InstDeclare(DevInst, &ConfigPtr); 13 | 14 | TEST_GROUP(DmaApis_Aie) 15 | { 16 | void setup() 17 | { 18 | AieRC RC; 19 | 20 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 21 | CHECK_EQUAL(XAIE_OK, RC); 22 | 23 | RC = XAie_PartitionInitialize(&(DevInst), NULL); 24 | CHECK_EQUAL(XAIE_OK, RC); 25 | } 26 | void teardown() 27 | { 28 | AieRC RC; 29 | 30 | RC = XAie_PartitionTeardown(&(DevInst)); 31 | CHECK_EQUAL(XAIE_OK, RC); 32 | 33 | XAie_Finish(&DevInst); 34 | } 35 | }; 36 | 37 | TEST(DmaApis_Aie, BdApis) 38 | { 39 | AieRC RC; 40 | XAie_DmaDesc DmaDesc; 41 | 42 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 43 | 44 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc); 45 | CHECK_EQUAL(RC, XAIE_OK); 46 | 47 | RC = XAie_DmaSetLock(&DmaDesc, XAie_LockInit(5, 1), 48 | XAie_LockInit(5, 0)); 49 | CHECK_EQUAL(RC, XAIE_OK); 50 | 51 | RC = XAie_DmaSetPkt(&DmaDesc, XAie_PacketInit(10, 5)); 52 | CHECK_EQUAL(RC, XAIE_OK); 53 | 54 | RC = XAie_DmaSetDoubleBuffer(&DmaDesc, 0x6000, XAie_LockInit(5, 1), 55 | XAie_LockInit(5, 0)); 56 | CHECK_EQUAL(RC, XAIE_OK); 57 | 58 | RC = XAie_DmaConfigFifoMode(&DmaDesc, XAIE_DMA_FIFO_COUNTER_1); 59 | CHECK_EQUAL(RC, XAIE_OK); 60 | } 61 | 62 | TEST(DmaApis_Aie, MultiDimApis) 63 | { 64 | AieRC RC; 65 | XAie_DmaDesc DmaDesc; 66 | 67 | XAie_LocType TileLoc = XAie_TileLoc(5, 4); 68 | 69 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc); 70 | CHECK_EQUAL(RC, XAIE_OK); 71 | 72 | XAie_DmaTensor Tensor; 73 | XAie_DmaDimDesc Dimensions[2]; 74 | 75 | Dimensions[0].AieDimDesc.Offset = 1; 76 | Dimensions[0].AieDimDesc.Incr = 1; 77 | Dimensions[0].AieDimDesc.Wrap = 32; 78 | Dimensions[1].AieDimDesc.Offset = 2; 79 | Dimensions[1].AieDimDesc.Incr = 2; 80 | Dimensions[1].AieDimDesc.Wrap = 20; 81 | 82 | Tensor.NumDim = 2U; 83 | Tensor.Dim = Dimensions; 84 | 85 | RC = XAie_DmaSetMultiDimAddr(&DmaDesc, &Tensor, 0x1800, 40); 86 | CHECK_EQUAL(RC, XAIE_OK); 87 | 88 | RC = XAie_DmaWriteBd(&DevInst, &DmaDesc, TileLoc, 8); 89 | CHECK_EQUAL(RC, XAIE_OK); 90 | } 91 | 92 | TEST(DmaApis_Aie, ShimDmaApis) 93 | { 94 | AieRC RC = XAIE_OK; 95 | XAie_DmaDesc DmaDesc; 96 | 97 | XAie_LocType TileLoc = XAie_TileLoc(2, 0); 98 | 99 | RC = XAie_DmaDescInit(&DevInst, &DmaDesc, TileLoc); 100 | CHECK_EQUAL(RC, XAIE_OK); 101 | 102 | RC = XAie_DmaSetLock(&DmaDesc, XAie_LockInit(5, 1), 103 | XAie_LockInit(5, 0)); 104 | CHECK_EQUAL(RC, XAIE_OK); 105 | 106 | RC = XAie_DmaSetPkt(&DmaDesc, XAie_PacketInit(10, 5)); 107 | CHECK_EQUAL(RC, XAIE_OK); 108 | 109 | RC = XAie_DmaConfigFifoMode(&DmaDesc, XAIE_DMA_FIFO_COUNTER_1); 110 | CHECK_EQUAL(RC, XAIE_FEATURE_NOT_SUPPORTED); 111 | 112 | RC = XAie_DmaWriteBd(&DevInst, &DmaDesc, TileLoc, 7); 113 | CHECK_EQUAL(RC, XAIE_OK); 114 | 115 | RC = XAie_DmaChannelPauseStream(&DevInst, TileLoc, 1, DMA_S2MM, 116 | XAIE_ENABLE); 117 | CHECK_EQUAL(RC, XAIE_OK); 118 | 119 | RC = XAie_DmaChannelPauseMem(&DevInst, TileLoc, 1, DMA_S2MM, 120 | XAIE_ENABLE); 121 | CHECK_EQUAL(RC, XAIE_OK); 122 | } 123 | 124 | TEST(DmaApis_Aie, InvalidArgs) 125 | { 126 | AieRC RC; 127 | XAie_DmaDesc DmaDesc; 128 | 129 | XAie_LocType TileLoc = XAie_TileLoc(8, 3); 130 | 131 | RC = XAie_DmaDescInit(NULL, &DmaDesc, TileLoc); 132 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 133 | 134 | RC = XAie_DmaSetDoubleBuffer(NULL, 0x6000, XAie_LockInit(5, 1), 135 | XAie_LockInit(5, 0)); 136 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 137 | 138 | RC = XAie_DmaConfigFifoMode(NULL, XAIE_DMA_FIFO_COUNTER_1); 139 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 140 | } 141 | #endif /* AIE_GEN == 1 */ 142 | -------------------------------------------------------------------------------- /driver/src/Makefile.Linux: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | APP = aiengine 8 | 9 | CC ?= gcc 10 | CP = cp 11 | LIBSOURCES = $(wildcard ./*/*.c) $(wildcard ./*/*/*.c) 12 | CFLAGS += -Wall -Wextra --std=c11 13 | EXTRA_CFLAGS += -D_POSIX_C_SOURCE=200809 -D_DEFAULT_SOURCE 14 | DOCS_DIR = ../tmp 15 | DOXYGEN_CONFIG_FILE = ../docs/aie_driver_docs_config.dox 16 | 17 | OUTS = $(LIBSOURCES:.c=.o) 18 | INCLUDEFILES = ./*/xaie_clock.h ./*/xaie_reset.h ./*/xaie_core.h ./*/xaie_dma.h ./*/xaie_elfloader.h ./*/xaie_events.h ./*/xaie_events_aie.h ./*/xaie_events_aieml.h ./*/xaie_interrupt.h ./*/xaie_lite.h ./*/xaie_lite_util.h ./*/xaie_locks.h ./*/xaie_mem.h ./*/xaie_perfcnt.h ./*/xaie_plif.h ./*/xaie_ss.h ./*/xaie_timer.h ./*/xaie_trace.h ./*/xaie_util_events.h ./*/xaiegbl.h ./*/xaiegbl_defs.h ./*/xaiegbl_regdef.h ./*/xaie_io.h ./*/xaie_feature_config.h ./*/xaie_helper.h ./*/xaie_lite_hwcfg.h ./*/xaiegbl_params.h ./*/*/xlnx-ai-engine.h ./*/xaie_txn.h ./*/xaie_routing.h 19 | INTERNALFILES = ./*/*.h ./*/*/*.h 20 | INCLUDEDIR = ../include 21 | INTERNALDIR = ../internal 22 | NAME := xaiengine 23 | MAJOR = 3 24 | MINOR = 8 25 | VERSION = $(MAJOR).$(MINOR) 26 | 27 | all: include lib$(NAME).so 28 | 29 | include: 30 | mkdir $(INCLUDEDIR)/xaiengine -p 31 | mkdir $(INTERNALDIR)/xaiengine -p 32 | $(CP) xaiengine.h $(INCLUDEDIR) 33 | $(CP) $(INCLUDEFILES) $(INCLUDEDIR)/xaiengine 34 | $(CP) xaiengine.h $(INTERNALDIR) 35 | $(CP) $(INTERNALFILES) $(INTERNALDIR)/xaiengine 36 | 37 | lib$(NAME).so.$(VERSION): $(OUTS) 38 | $(CC) $(LDFLAGS) $^ -shared -Wl,-soname,lib$(NAME).so.$(MAJOR) -o lib$(NAME).so.$(VERSION) 39 | 40 | lib$(NAME).so: lib$(NAME).so.$(VERSION) 41 | rm -f lib$(NAME).so.$(MAJOR) lib$(NAME).so 42 | ln -s lib$(NAME).so.$(VERSION) lib$(NAME).so.$(MAJOR) 43 | ln -s lib$(NAME).so.$(MAJOR) lib$(NAME).so 44 | 45 | %.o: %.c include 46 | $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 47 | 48 | baremetal: include lib$(NAME).so 49 | CFLAGS_bare += -Wall -Wextra --std=c11 -D_AIEBAREMETAL__ 50 | ifeq ($(MAKECMDGOALS) ,baremetal) 51 | %.o: %.c include 52 | $(CC) $(CFLAGS_bare) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 53 | endif 54 | 55 | linux: include lib$(NAME).so 56 | CFLAGS_linux += -Wall -Wextra --std=c11 -D__AIELINUX__ -D_POSIX_C_SOURCE=200809 -D_DEFAULT_SOURCE 57 | ifeq ($(MAKECMDGOALS),linux) 58 | %.o: %.c include 59 | $(CC) $(CFLAGS_linux) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 60 | endif 61 | 62 | simulation: include lib$(NAME).so 63 | CFLAGS_simulation += -Wall -Wextra --std=c11 -D__AIESIM__ 64 | ifeq ($(MAKECMDGOALS),simulation) 65 | %.o: %.c include 66 | $(CC) $(CFLAGS_simulation) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 67 | endif 68 | 69 | cdo: include lib$(NAME).so 70 | CFLAGS_cdo += -Wall -Wextra --std=c11 -D__AIECDO__ 71 | ifeq ($(MAKECMDGOALS) ,cdo) 72 | %.o: %.c include 73 | $(CC) $(CFLAGS_cdo) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 74 | endif 75 | 76 | libmetal: include lib$(NAME).so 77 | CFLAGS_libmetal += -Wall -Wextra --std=c11 -D__AIEMETAL__ 78 | ifeq ($(MAKECMDGOALS), libmetal) 79 | %.o: %.c include 80 | $(CC) $(CFLAGS_libmetal) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 81 | endif 82 | 83 | controlcode: include lib$(NAME).so 84 | CFLAGS_controlcode += -Wall -Wextra --std=c11 -D__AIECONTROLCODE__ 85 | ifeq ($(MAKECMDGOALS) ,controlcode) 86 | %.o: %.c include 87 | $(CC) $(CFLAGS_controlcode) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 88 | endif 89 | 90 | doc-generate: 91 | mkdir -p $(DOCS_DIR) 92 | doxygen $(DOXYGEN_CONFIG_FILE) 93 | cd $(DOCS_DIR)/latex; make; cd .. 94 | 95 | doc-clean: 96 | rm -rf $(DOCS_DIR) 97 | 98 | clean: 99 | rm -rf $(OUTS) *.so *.so.* 100 | rm -rf $(INCLUDEDIR) 101 | rm -rf $(INTERNALDIR) 102 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 - 2023 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_io_internal.h 10 | * @{ 11 | * 12 | * This header file defines a lightweight version of AIE driver APIs. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who     Date     Changes
 18 | * ----- ------  -------- -----------------------------------------------------
 19 | * 1.0  Ssatpute  06/27/2021  Initial creation
 20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_LITE_IO_INTERNAL_H 24 | #define XAIE_LITE_IO_INTERNAL_H 25 | 26 | #ifdef XAIE_FEATURE_LITE 27 | 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | #include "xaie_helper.h" 31 | 32 | 33 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 34 | #include "xaie_lite_aie.h" 35 | #include "xaie_lite_shim_aie.h" 36 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 37 | #include "xaie_lite_aieml.h" 38 | #include "xaie_lite_shim_aie.h" 39 | #else 40 | #include 41 | #endif 42 | 43 | #define XAIE_ERROR_MSG(...) \ 44 | "[AIE ERROR] %s():%d: %s", __func__, __LINE__, __VA_ARGS__ 45 | 46 | #ifdef XAIE_ENABLE_INPUT_CHECK 47 | #ifdef _ENABLE_IPU_LX6_ 48 | #include 49 | #endif 50 | #define XAIE_ERROR_RETURN(ERRCON, RET, ...) { \ 51 | if (ERRCON) { \ 52 | printf(__VA_ARGS__); \ 53 | return (RET); \ 54 | } \ 55 | } 56 | #else 57 | #define XAIE_ERROR_RETURN(...) 58 | #endif 59 | 60 | /************************** Function Definitions *****************************/ 61 | /*****************************************************************************/ 62 | /** 63 | * 64 | * This is API returns the tile type for a given device instance and tile 65 | * location. 66 | * 67 | * @param DevInst: Device Instance 68 | * @param Loc: Location of the AIE tile. 69 | * @return TileType (AIETILE/MEMTILE/SHIMPL/SHIMNOC on success and MAX on 70 | * error) 71 | * 72 | * @note Internal only. 73 | * 74 | ******************************************************************************/ 75 | static inline u8 _XAie_LGetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc) 76 | { 77 | XAIE_ERROR_RETURN((Loc.Col >= XAIE_NUM_COLS), XAIEGBL_TILE_TYPE_MAX, 78 | XAIE_ERROR_MSG("Invalid column: %d\n", Loc.Col)); 79 | 80 | if(Loc.Row == 0U) { 81 | return _XAie_LGetShimTTypefromLoc(DevInst, Loc); 82 | } else if(Loc.Row >= XAIE_MEM_TILE_ROW_START && 83 | (Loc.Row < (XAIE_MEM_TILE_ROW_START + 84 | XAIE_MEM_TILE_NUM_ROWS))) { 85 | return XAIEGBL_TILE_TYPE_MEMTILE; 86 | } else if (Loc.Row >= XAIE_AIE_TILE_ROW_START && 87 | (Loc.Row < (XAIE_AIE_TILE_ROW_START + 88 | XAIE_AIE_TILE_NUM_ROWS))) { 89 | return XAIEGBL_TILE_TYPE_AIETILE; 90 | } 91 | 92 | XAIE_ERROR_RETURN(1U, XAIEGBL_TILE_TYPE_MAX, 93 | XAIE_ERROR_MSG("Cannot find Tile Type\n")); 94 | 95 | return XAIEGBL_TILE_TYPE_MAX; 96 | } 97 | 98 | /** 99 | * 100 | * This API checks if an AI engine tile is in use. 101 | * 102 | * @param DevInst: Device Instance. 103 | * @param Loc: Tile location. 104 | * 105 | * @return XAIE_ENABLE if a tile is in use, otherwise XAIE_DISABLE. 106 | * 107 | * @note Internal only. 108 | * 109 | ******************************************************************************/ 110 | static inline u8 _XAie_LPmIsTileRequested(XAie_DevInst *DevInst, 111 | XAie_LocType Loc) 112 | { 113 | u8 TileType; 114 | TileType = _XAie_LGetTTypefromLoc(DevInst, Loc); 115 | 116 | if (TileType == XAIEGBL_TILE_TYPE_MAX) { 117 | return XAIE_DISABLE; 118 | } 119 | if (TileType == XAIEGBL_TILE_TYPE_SHIMNOC || TileType == XAIEGBL_TILE_TYPE_SHIMPL) { 120 | return XAIE_ENABLE; 121 | } 122 | 123 | return _XAie_LPmIsArrayTileRequested(DevInst, Loc); 124 | } 125 | 126 | #endif /* XAIE_FEATURE_LITE */ 127 | 128 | #endif /* XAIE_LITE_H */ 129 | --------------------------------------------------------------------------------