├── .github └── workflows │ └── send-email.yml ├── .gitignore ├── README.md ├── cmake └── Findcommon.cmake ├── driver ├── README.md ├── data │ ├── aienginev2.mdd │ ├── aienginev2.tcl │ └── aienginev2.yaml ├── docs │ ├── aie_driver_docs_config.dox │ ├── driver_layout.xml │ ├── html_footer.html │ └── xlogo_bg.gif ├── examples │ ├── Makefile │ ├── xaie_error_interrupt_test.c │ ├── xaie_partition_list_query.c │ └── xaie_tile_dma_loopback.c ├── src │ ├── CMakeLists.txt │ ├── Makefile │ ├── Makefile.Linux │ ├── Makefile.rsc │ ├── common │ │ ├── xaie_helper.c │ │ ├── xaie_helper.h │ │ ├── xaie_helper_internal.h │ │ └── xaie_txn.h │ ├── core │ │ ├── xaie_core.c │ │ ├── xaie_core.h │ │ ├── xaie_core_aie.c │ │ ├── xaie_core_aie.h │ │ ├── xaie_core_aieml.c │ │ ├── xaie_core_aieml.h │ │ ├── xaie_elfloader.c │ │ ├── xaie_elfloader.h │ │ ├── xaie_uc.c │ │ └── xaie_uc.h │ ├── device │ │ ├── xaie_device_aie.c │ │ ├── xaie_device_aie.h │ │ ├── xaie_device_aie2ps.c │ │ ├── xaie_device_aie2ps.h │ │ ├── xaie_device_aieml.c │ │ └── xaie_device_aieml.h │ ├── dma │ │ ├── xaie_dma.c │ │ ├── xaie_dma.h │ │ ├── xaie_dma_aie.c │ │ ├── xaie_dma_aie.h │ │ ├── xaie_dma_aie2ps.c │ │ ├── xaie_dma_aie2ps.h │ │ ├── xaie_dma_aieml.c │ │ └── xaie_dma_aieml.h │ ├── events │ │ ├── xaie_events.c │ │ ├── xaie_events.h │ │ ├── xaie_events_aie.h │ │ ├── xaie_events_aie2ps.h │ │ └── xaie_events_aieml.h │ ├── global │ │ ├── xaie2psgbl_params.h │ │ ├── xaie2psgbl_reginit.c │ │ ├── xaie_feature_config.h │ │ ├── xaiegbl.c │ │ ├── xaiegbl.h │ │ ├── xaiegbl_defs.h │ │ ├── xaiegbl_params.h │ │ ├── xaiegbl_regdef.h │ │ ├── xaiegbl_reginit.c │ │ ├── xaiemlgbl_params.h │ │ └── xaiemlgbl_reginit.c │ ├── interrupt │ │ ├── xaie_interrupt.h │ │ ├── xaie_interrupt_aie.c │ │ ├── xaie_interrupt_aie.h │ │ ├── xaie_interrupt_aie2ps.c │ │ ├── xaie_interrupt_aie2ps.h │ │ ├── xaie_interrupt_aieml.c │ │ ├── xaie_interrupt_aieml.h │ │ ├── xaie_interrupt_backtrack.c │ │ ├── xaie_interrupt_control.c │ │ └── xaie_interrupt_init.c │ ├── io_backend │ │ ├── ext │ │ │ ├── xaie_baremetal.c │ │ │ ├── xaie_cdo.c │ │ │ ├── xaie_debug.c │ │ │ ├── xaie_io_common.c │ │ │ ├── xaie_io_common.h │ │ │ ├── xaie_linux.c │ │ │ ├── xaie_metal.c │ │ │ ├── xaie_sim.c │ │ │ ├── xaie_socket.c │ │ │ └── xlnx-ai-engine.h │ │ ├── privilege │ │ │ ├── xaie_io_privilege.c │ │ │ └── xaie_io_privilege.h │ │ ├── xaie_io.c │ │ ├── xaie_io.h │ │ └── xaie_io_internal.h │ ├── lite │ │ ├── xaie_lite.c │ │ ├── xaie_lite.h │ │ ├── xaie_lite_aie.h │ │ ├── xaie_lite_aieml.h │ │ ├── xaie_lite_hwcfg.h │ │ ├── xaie_lite_internal.h │ │ ├── xaie_lite_io.h │ │ ├── xaie_lite_npi.h │ │ ├── xaie_lite_privilege.c │ │ ├── xaie_lite_regdef_aie.h │ │ ├── xaie_lite_regdef_aieml.h │ │ ├── xaie_lite_shim_aie.h │ │ └── xaie_lite_util.h │ ├── locks │ │ ├── xaie_locks.c │ │ ├── xaie_locks.h │ │ ├── xaie_locks_aie.c │ │ ├── xaie_locks_aie.h │ │ ├── xaie_locks_aieml.c │ │ └── xaie_locks_aieml.h │ ├── memory │ │ ├── xaie_mem.c │ │ └── xaie_mem.h │ ├── npi │ │ ├── xaie_npi.c │ │ ├── xaie_npi.h │ │ ├── xaie_npi_aie.c │ │ └── xaie_npi_aieml.c │ ├── perfcnt │ │ ├── xaie_perfcnt.c │ │ └── xaie_perfcnt.h │ ├── pl │ │ ├── xaie_plif.c │ │ └── xaie_plif.h │ ├── pm │ │ ├── xaie_clock.c │ │ ├── xaie_clock.h │ │ ├── xaie_ecc.c │ │ ├── xaie_ecc.h │ │ ├── xaie_reset.c │ │ ├── xaie_reset.h │ │ ├── xaie_reset_aie.c │ │ ├── xaie_reset_aie.h │ │ ├── xaie_reset_aieml.c │ │ ├── xaie_reset_aieml.h │ │ ├── xaie_tilectrl.c │ │ └── xaie_tilectrl.h │ ├── routing │ │ ├── xaie_routing.c │ │ ├── xaie_routing.h │ │ └── xaie_routing_internal.h │ ├── stream_switch │ │ ├── xaie_ss.c │ │ ├── xaie_ss.h │ │ ├── xaie_ss_aie.c │ │ ├── xaie_ss_aie.h │ │ ├── xaie_ss_aie2ps.c │ │ ├── xaie_ss_aie2ps.h │ │ ├── xaie_ss_aieml.c │ │ └── xaie_ss_aieml.h │ ├── timer │ │ ├── xaie_timer.c │ │ └── xaie_timer.h │ ├── trace │ │ ├── xaie_trace.c │ │ └── xaie_trace.h │ ├── util │ │ ├── xaie_util_events.c │ │ ├── xaie_util_events.h │ │ ├── xaie_util_status.c │ │ └── xaie_util_status.h │ └── xaiengine.h └── test │ ├── stest │ ├── aiert_tests.h │ ├── hw_config.h │ ├── xaie_auto_routing.c │ └── xaie_test_lock.c │ └── utest │ ├── aie_hw_config.h │ └── utest.c ├── fal ├── CMakeLists.txt ├── README.md ├── cmake │ ├── collect.cmake │ ├── depends.cmake │ ├── modules │ │ └── FindLibxaiengine.cmake │ ├── options.cmake │ └── platforms │ │ ├── cross-genric-g++.cmake │ │ ├── cross-linux-g++.cmake │ │ └── versal-linux.cmake ├── data │ ├── aiefal.mdd │ └── aiefal.yaml ├── doc │ ├── CMakeLists.txt │ ├── Doxyfile.in │ ├── aiefal-class.txt │ ├── aiefal-state-prereserved.txt │ └── aiefal-state.txt ├── examples │ ├── CMakeLists.txt │ ├── profile-aie.cpp │ ├── profile-io-aie.cpp │ └── trace-pc-aie.cpp ├── src │ ├── CMakeLists.txt │ ├── Makefile │ ├── common │ │ ├── xaiefal-base.hpp │ │ ├── xaiefal-common.hpp │ │ └── xaiefal-log.hpp │ ├── profile │ │ └── xaiefal-profile.hpp │ ├── rsc │ │ ├── xaiefal-bc.hpp │ │ ├── xaiefal-events.hpp │ │ ├── xaiefal-groupevent.hpp │ │ ├── xaiefal-pc.hpp │ │ ├── xaiefal-perf.hpp │ │ ├── xaiefal-rsc-base.hpp │ │ ├── xaiefal-rsc-group-impl.hpp │ │ ├── xaiefal-rsc-group.hpp │ │ ├── xaiefal-rscmgr-backend-base.hpp │ │ ├── xaiefal-rscmgr-generic.hpp │ │ ├── xaiefal-rscmgr-linux.hpp │ │ ├── xaiefal-rscmgr.hpp │ │ ├── xaiefal-ss.hpp │ │ └── xaiefal-trace.hpp │ └── xaiefal.hpp └── tests │ ├── CMakeLists.txt │ └── utests │ ├── CMakeLists.txt │ └── tc │ ├── common │ └── tc_config.h │ ├── test.cpp │ ├── test_bc.cpp │ ├── test_combo.cpp │ ├── test_groupevent.cpp │ ├── test_pc.cpp │ ├── test_perf.cpp │ ├── test_rsc_base.cpp │ ├── test_rscs_stat.cpp │ ├── test_ss.cpp │ ├── test_trace.cpp │ └── test_userevent.cpp └── license.txt /.gitignore: -------------------------------------------------------------------------------- 1 | #Ignore these file extensions 2 | *.a 3 | *.o 4 | *.so 5 | *.so.* 6 | 7 | #Ignore these directories 8 | /driver/include 9 | /driver/internal 10 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AI Engine Run Time 2 | 3 | AI Engine runtime(aie-rt) is a combination of two components. 4 | * driver 5 | * fal 6 | 7 | ## AIE Driver(driver) 8 | AIE Driver is a userspace library that provides hardware access to applications. 9 | 10 | ## AIE FAL(fal) 11 | AIE FAL is functional abstraction layer that provides common userspace APIs for 12 | runtime AIE resource management. 13 | 14 | ## License 15 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 16 | SPDX-License-Identifier: MIT 17 | -------------------------------------------------------------------------------- /cmake/Findcommon.cmake: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. 2 | # SPDX-License-Identifier: MIT 3 | 4 | option(YOCTO "Yocto based embeddedsw FLOW" OFF) 5 | set(CMAKE_POLICY_DEFAULT_CMP0140 OLD) 6 | 7 | if (YOCTO) 8 | find_package(commonmeta QUIET) 9 | endif() 10 | 11 | set (CMAKE_INSTALL_LIBDIR "lib") 12 | function (collector_create name base) 13 | set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST") 14 | set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}") 15 | endfunction (collector_create) 16 | 17 | function (collector_list var name) 18 | get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST") 19 | set (${var} "${_list}" PARENT_SCOPE) 20 | endfunction (collector_list) 21 | 22 | function (collector_base var name) 23 | get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE") 24 | set (${var} "${_base}" PARENT_SCOPE) 25 | endfunction (collector_base) 26 | 27 | function (collect name) 28 | collector_base (_base ${name}) 29 | string(COMPARE NOTEQUAL "${_base}" "" _is_rel) 30 | set (_list) 31 | foreach (s IN LISTS ARGN) 32 | if (_is_rel) 33 | get_filename_component (s "${s}" ABSOLUTE) 34 | file (RELATIVE_PATH s "${_base}" "${s}") 35 | endif (_is_rel) 36 | list (APPEND _list "${s}") 37 | endforeach () 38 | set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}") 39 | endfunction (collect) 40 | 41 | string(ASCII 27 Esc) 42 | set(ColourReset "${Esc}[m") 43 | set(BoldRed "${Esc}[1;31m") 44 | set(BoldYellow "${Esc}[1;33m") 45 | -------------------------------------------------------------------------------- /driver/README.md: -------------------------------------------------------------------------------- 1 | # AI Engine Driver 2 | 3 | The userspace library for ai-engine provides APIs to configure AIE registers. 4 | 5 | ## Hardware support 6 | 7 | The user space library is supports both AIE, AIEML. 8 | 9 | ## Compilation 10 | ### Compile library 11 | `make -f Makefile.Linux` 12 | ### Generate Documentation 13 | `make -f Makefile.Linux doc-generate` 14 | 15 | HTML docs are populated in ./tmp/api/ 16 | 17 | PDF doc will be available at ./tmp/latex/refman.pdf 18 | 19 | ## License 20 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 21 | SPDX-License-Identifier: MIT 22 | -------------------------------------------------------------------------------- /driver/data/aienginev2.mdd: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | OPTION psf_version = 2.1; 8 | 9 | BEGIN driver aienginev2 10 | 11 | OPTION supported_peripherals = (aie aiengine ai_engine); 12 | OPTION driver_state = ACTIVE; 13 | OPTION copyfiles = all; 14 | OPTION VERSION = 3.6; 15 | OPTION DEPENDS = (aiefal); 16 | OPTION NAME = aienginev2; 17 | 18 | END driver 19 | -------------------------------------------------------------------------------- /driver/data/aienginev2.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | proc copy_files {dir} { 8 | foreach sub_dir [glob -nocomplain -directory $dir -type d *] { 9 | copy_files $sub_dir 10 | } 11 | foreach fn [glob -nocomplain [file join $dir * -type f *]] { 12 | file copy -force $fn "./src" 13 | } 14 | } 15 | 16 | proc copy_sub_files {dir} { 17 | foreach sub_dir [glob -nocomplain -directory $dir -type d *] { 18 | copy_files $sub_dir 19 | } 20 | } 21 | 22 | proc generate {libhandle} { 23 | copy_sub_files "./src" 24 | file mkdir "../../include/xaiengine" 25 | } 26 | -------------------------------------------------------------------------------- /driver/data/aienginev2.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 2 | #SPDX-License-Identifier: MIT 3 | %YAML 1.2 4 | --- 5 | title: Bindings for AIE Engine Driver 6 | 7 | maintainers: 8 | - Gregory Williams 9 | 10 | type: driver 11 | 12 | properties: 13 | compatible: 14 | items: 15 | - const: xlnx,ai-engine-2.0 16 | 17 | depends: 18 | aiefal: [] 19 | ... 20 | -------------------------------------------------------------------------------- /driver/docs/html_footer.html: -------------------------------------------------------------------------------- 1 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /driver/docs/xlogo_bg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/aie-rt/5364a69cbce5129465977a6348364c627c575d76/driver/docs/xlogo_bg.gif -------------------------------------------------------------------------------- /driver/examples/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | CC ?= gcc 8 | 9 | CFLAGS += -Wall -Wextra 10 | INCLUDEDIR = ../include 11 | LIBDIR = ../src 12 | 13 | SRCS = $(wildcard *.c) 14 | SRCS := $(filter-out xaie_error_interrupt_test.c, $(SRCS)) 15 | APPS = $(patsubst %.c, %, $(SRCS)) 16 | APPSTMPS = $(patsubst %.c, %.out, $(SRCS)) 17 | 18 | all: build 19 | 20 | build: $(APPSTMPS) 21 | 22 | %.out: %.o 23 | $(CC) -o $(patsubst %.out, %, $@) $< -L$(LIBDIR) -lxaiengine 24 | 25 | %.o: %.c 26 | $(CC) -I$(INCLUDEDIR) $(CFLAGS) -c $< -o $@ 27 | 28 | clean: 29 | rm -f $(APPS) *.o 30 | -------------------------------------------------------------------------------- /driver/src/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | COMPILER= 8 | ARCHIVER= 9 | CP=cp 10 | COMPILER_FLAGS = 11 | EXTRA_COMPILER_FLAGS= 12 | EXTRA_ARCHIVE_FLAGS=rc 13 | LIB=libxil.a 14 | 15 | RELEASEDIR=../../../lib 16 | INCLUDEDIR=../../../include 17 | INCLUDES=-I./. -I${INCLUDEDIR} -I${INCLUDEDIR}/xaiengine 18 | EXTRA_CFLAGS= 19 | 20 | AIEBACKEND ?= BAREMETAL 21 | EXTRA_CFLAGS += -D__AIE$(AIEBACKEND)__ 22 | ifdef XAIE_DEV_SINGLE_GEN 23 | EXTRA_CFLAGS += -DXAIE_DEV_SINGLE_GEN=$(XAIE_DEV_SINGLE_GEN) 24 | endif 25 | 26 | XAIE_DIR = . 27 | OUTS = *.o 28 | OBJECTS = $(addsuffix .o, $(basename $(wildcard ./*/*.c) $(wildcard ./*/*/*.c))) 29 | XAIE_SRCS := $(filter-out $(XAIE_SRCS_EXCLUDE), $(wildcard ./*/*.c) $(wildcard ./*/*/*.c)) 30 | XAIE_OBJS = $(addprefix $(XAIE_DIR)/, $(XAIE_SRCS:%.c=%.o)) 31 | 32 | INCLUDEFILES= $(wildcard ./*/*.h) $(wildcard ./*/*/*.h) 33 | 34 | libs: xaie 35 | 36 | xaie: print_msg_xaie $(XAIE_OBJS) 37 | $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${XAIE_OBJS} 38 | 39 | print_msg_xaie: 40 | @echo "Compiling xaie" 41 | 42 | .PHONY: include 43 | include: xaie_includes 44 | 45 | xaie_includes: 46 | ${CP} xaiengine.h ${INCLUDEDIR} 47 | ${CP} ${INCLUDEFILES} ${INCLUDEDIR}/xaiengine 48 | 49 | clean: 50 | rm -rf $(XAIE_DIR)/${OBJECTS} 51 | rm -rf ${RELEASEDIR}/${LIB} 52 | 53 | $(XAIE_DIR)/%.o: $(XAIE_DIR)/%.c $(INCLUDEFILES) 54 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_CFLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o $@ 55 | -------------------------------------------------------------------------------- /driver/src/Makefile.Linux: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | APP = aiengine 8 | 9 | CC ?= gcc 10 | CP = cp 11 | LIBSOURCES = $(wildcard ./*/*.c) $(wildcard ./*/*/*.c) 12 | CFLAGS += -Wall -Wextra --std=c11 13 | EXTRA_CFLAGS += -D_POSIX_C_SOURCE=200809 -D_DEFAULT_SOURCE 14 | DOCS_DIR = ../tmp 15 | DOXYGEN_CONFIG_FILE = ../docs/aie_driver_docs_config.dox 16 | 17 | OUTS = $(LIBSOURCES:.c=.o) 18 | INCLUDEFILES = ./*/xaie_clock.h ./*/xaie_reset.h ./*/xaie_core.h ./*/xaie_dma.h ./*/xaie_elfloader.h ./*/xaie_events.h ./*/xaie_events_aie.h ./*/xaie_events_aieml.h ./*/xaie_interrupt.h ./*/xaie_lite.h ./*/xaie_lite_util.h ./*/xaie_locks.h ./*/xaie_mem.h ./*/xaie_perfcnt.h ./*/xaie_plif.h ./*/xaie_ss.h ./*/xaie_timer.h ./*/xaie_trace.h ./*/xaie_util_events.h ./*/xaiegbl.h ./*/xaiegbl_defs.h ./*/xaiegbl_regdef.h ./*/xaie_io.h ./*/xaie_feature_config.h ./*/xaie_helper.h ./*/xaie_lite_hwcfg.h ./*/xaiegbl_params.h ./*/*/xlnx-ai-engine.h ./*/xaie_txn.h ./*/xaie_routing.h 19 | INTERNALFILES = ./*/*.h ./*/*/*.h 20 | INCLUDEDIR = ../include 21 | INTERNALDIR = ../internal 22 | NAME := xaiengine 23 | MAJOR = 3 24 | MINOR = 6 25 | VERSION = $(MAJOR).$(MINOR) 26 | 27 | all: include lib$(NAME).so 28 | 29 | include: 30 | mkdir $(INCLUDEDIR)/xaiengine -p 31 | mkdir $(INTERNALDIR)/xaiengine -p 32 | $(CP) xaiengine.h $(INCLUDEDIR) 33 | $(CP) $(INCLUDEFILES) $(INCLUDEDIR)/xaiengine 34 | $(CP) xaiengine.h $(INTERNALDIR) 35 | $(CP) $(INTERNALFILES) $(INTERNALDIR)/xaiengine 36 | 37 | lib$(NAME).so.$(VERSION): $(OUTS) 38 | $(CC) $(LDFLAGS) $^ -shared -Wl,-soname,lib$(NAME).so.$(MAJOR) -o lib$(NAME).so.$(VERSION) 39 | 40 | lib$(NAME).so: lib$(NAME).so.$(VERSION) 41 | rm -f lib$(NAME).so.$(MAJOR) lib$(NAME).so 42 | ln -s lib$(NAME).so.$(VERSION) lib$(NAME).so.$(MAJOR) 43 | ln -s lib$(NAME).so.$(MAJOR) lib$(NAME).so 44 | 45 | %.o: %.c include 46 | $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 47 | 48 | baremetal: include lib$(NAME).so 49 | CFLAGS_bare += -Wall -Wextra --std=c11 -D_AIEBAREMETAL__ 50 | ifeq ($(MAKECMDGOALS) ,baremetal) 51 | %.o: %.c include 52 | $(CC) $(CFLAGS_bare) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 53 | endif 54 | 55 | linux: include lib$(NAME).so 56 | CFLAGS_linux += -Wall -Wextra --std=c11 -D__AIELINUX__ -D_POSIX_C_SOURCE=200809 -D_DEFAULT_SOURCE 57 | ifeq ($(MAKECMDGOALS),linux) 58 | %.o: %.c include 59 | $(CC) $(CFLAGS_linux) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 60 | endif 61 | 62 | simulation: include lib$(NAME).so 63 | CFLAGS_simulation += -Wall -Wextra --std=c11 -D__AIESIM__ 64 | ifeq ($(MAKECMDGOALS),simulation) 65 | %.o: %.c include 66 | $(CC) $(CFLAGS_simulation) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 67 | endif 68 | 69 | cdo: include lib$(NAME).so 70 | CFLAGS_cdo += -Wall -Wextra --std=c11 -D__AIECDO__ 71 | ifeq ($(MAKECMDGOALS) ,cdo) 72 | %.o: %.c include 73 | $(CC) $(CFLAGS_cdo) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 74 | endif 75 | 76 | libmetal: include lib$(NAME).so 77 | CFLAGS_libmetal += -Wall -Wextra --std=c11 -D__AIEMETAL__ 78 | ifeq ($(MAKECMDGOALS), libmetal) 79 | %.o: %.c include 80 | $(CC) $(CFLAGS_libmetal) -I$(INTERNALDIR) -I$(INTERNALDIR)/xaiengine -c -fPIC $< -o $@ 81 | endif 82 | 83 | doc-generate: 84 | mkdir -p $(DOCS_DIR) 85 | doxygen $(DOXYGEN_CONFIG_FILE) 86 | cd $(DOCS_DIR)/latex; make; cd .. 87 | 88 | doc-clean: 89 | rm -rf $(DOCS_DIR) 90 | 91 | clean: 92 | rm -rf $(OUTS) *.so *.so.* 93 | rm -rf $(INCLUDEDIR) 94 | rm -rf $(INTERNALDIR) 95 | -------------------------------------------------------------------------------- /driver/src/Makefile.rsc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | CROSSCOMPILE ?= 8 | RSCMETA ?= aie_rsc_meta.bin 9 | GEN_RSCMETA ?= gen_aie_rsc_meta.bin 10 | 11 | # use objcopy instead of ld is to make sure the AI engine resource meta data 12 | # is linked as read only data 13 | OBJCOPY = $(CROSSCOMPILE)objcopy 14 | OBJ = $(subst .bin,.o,$(GEN_RSCMETA)) 15 | 16 | OUTFMT=elf64-x86-64 17 | OUTARCH=i386 18 | ifneq (,$(findstring aarch64,$(CROSSCOMPILE))) 19 | OUTFMT=elf64-littleaarch64 20 | OUTARCH=aarch64 21 | endif 22 | ifneq (,$(findstring armr5,$(CROSSCOMPILE))) 23 | OUTFMT=elf32-littlearm 24 | OUTARCH=arm 25 | endif 26 | ifneq (,$(findstring mb-,$(CROSSCOMPILE))) 27 | OUTFMT=elf32-microblazeel 28 | OUTARCH=microblazeel 29 | endif 30 | ifneq (,$(findstring microblaze,$(CROSSCOMPILE))) 31 | OUTFMT=elf32-microblazeel 32 | OUTARCH=microblazeel 33 | endif 34 | 35 | all: addrsc 36 | 37 | addrsc: $(OBJ) 38 | 39 | $(OBJ): $(GEN_RSCMETA) 40 | $(OBJCOPY) -I binary -O $(OUTFMT) -B $(OUTARCH) --rename-section .data=.rodata,alloc,load,readonly,data,contents $< $@ 41 | 42 | $(GEN_RSCMETA): $(RSCMETA) 43 | cp $< $@ 44 | 45 | clean: 46 | rm -f $(OBJ) $(GEN_RSCMETA) 47 | 48 | .PHONY: all addrsc 49 | -------------------------------------------------------------------------------- /driver/src/common/xaie_helper_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2024 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_helper_internal.h 10 | * @{ 11 | * 12 | * This file contains inline helper functions for AIE drivers. 13 | ******************************************************************************/ 14 | #ifndef XAIE_HELPER_INTERNAL_H 15 | #define XAIE_HELPER_INTERNAL_H 16 | 17 | /***************************** Include Files *********************************/ 18 | /***************************** Macro Definitions *****************************/ 19 | /************************** Function Definitions *****************************/ 20 | AieRC _XAie_GetSlaveIdx(const XAie_StrmMod *StrmMod, StrmSwPortType Slave, 21 | u8 PortNum, u8 *SlaveIdx); 22 | AieRC _XAie_GetMstrIdx(const XAie_StrmMod *StrmMod, StrmSwPortType Master, 23 | u8 PortNum, u8 *MasterIdx); 24 | u32 _XAie_GetFatalGroupErrors(XAie_DevInst *DevInst, XAie_LocType Loc, 25 | XAie_ModuleType Module); 26 | u32 _XAie_GetTileBitPosFromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 27 | void _XAie_SetBitInBitmap(u32 *Bitmap, u32 StartSetBit, u32 NumSetBit); 28 | void _XAie_ClrBitInBitmap(u32 *Bitmap, u32 StartSetBit, u32 NumSetBit); 29 | AieRC _XAie_Txn_Start(XAie_DevInst *DevInst, u32 Flags); 30 | AieRC _XAie_Txn_Submit(XAie_DevInst *DevInst, XAie_TxnInst *TxnInst); 31 | XAie_TxnInst* _XAie_TxnExport(XAie_DevInst *DevInst); 32 | u8* _XAie_TxnExportSerialized(XAie_DevInst *DevInst, u8 NumConsumers, 33 | u32 Flags); 34 | AieRC _XAie_ClearTransaction(XAie_DevInst* DevInst); 35 | AieRC _XAie_TxnFree(XAie_TxnInst *Inst); 36 | void _XAie_TxnResourceCleanup(XAie_DevInst *DevInst); 37 | void _XAie_FreeTxnPtr(void *Ptr); 38 | u8 _XAie_IsUcModulePresent(XAie_DevInst* DevInst, u8 TileType); 39 | void _XAie_AppendPartitionToList(XAie_DevInst *DevInst, XAie_PartitionList *PartInst); 40 | AieRC _XAie_DestroyPartitionFdList(XAie_DevInst *DevInst); 41 | AieRC _XAie_PrintPartitionList(XAie_DevInst *DevInst); 42 | int _XAie_MatchPartitionList(XAie_DevInst *DevInst, u32 PartitionId); 43 | #endif 44 | -------------------------------------------------------------------------------- /driver/src/common/xaie_txn.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_txn.h 10 | * @{ 11 | * 12 | * This file contains data structure for TxN flow 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Keyur   08/25/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIETXN_H 24 | #define XAIETXN_H 25 | 26 | /***************************** Include Files *********************************/ 27 | /* All New custom Ops should be added above XAIE_IO_CUSTOM_OP_NEXT 28 | * To support backward compatibility existing enums should not be 29 | * modified. */ 30 | typedef enum { 31 | XAIE_IO_WRITE, 32 | XAIE_IO_BLOCKWRITE, 33 | XAIE_IO_BLOCKSET, 34 | XAIE_IO_MASKWRITE, 35 | XAIE_IO_MASKPOLL, 36 | XAIE_CONFIG_SHIMDMA_BD, 37 | XAIE_CONFIG_SHIMDMA_DMABUF_BD, 38 | XAIE_IO_CUSTOM_OP_BEGIN = 1U<<7U, 39 | XAIE_IO_CUSTOM_OP_TCT = XAIE_IO_CUSTOM_OP_BEGIN, 40 | XAIE_IO_CUSTOM_OP_DDR_PATCH, 41 | XAIE_IO_CUSTOM_OP_NEXT, 42 | XAIE_IO_CUSTOM_OP_MAX = UCHAR_MAX, 43 | } XAie_TxnOpcode; 44 | 45 | struct XAie_TxnCmd { 46 | XAie_TxnOpcode Opcode; 47 | u32 Mask; 48 | u64 RegOff; 49 | u32 Value; 50 | u64 DataPtr; 51 | u32 Size; 52 | }; 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /driver/src/core/xaie_core_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_core_aie.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for aie core apis. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/02/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIECORE_AIE_H 24 | #define XAIECORE_AIE_H 25 | /***************************** Include Files *********************************/ 26 | #include "xaie_helper.h" 27 | /************************** Function Prototypes *****************************/ 28 | AieRC _XAie_CoreConfigureDone(XAie_DevInst *DevInst, XAie_LocType Loc, 29 | const struct XAie_CoreMod *CoreMod); 30 | AieRC _XAie_CoreEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 31 | const struct XAie_CoreMod *CoreMod); 32 | AieRC _XAie_CoreWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 33 | u32 TimeOut, const struct XAie_CoreMod *CoreMod); 34 | AieRC _XAie_CoreReadDoneBit(XAie_DevInst *DevInst, XAie_LocType Loc, 35 | u8 *DoneBit, const struct XAie_CoreMod *CoreMod); 36 | AieRC _XAie_CoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | u32 *CoreStatus, const struct XAie_CoreMod *CoreMod); 38 | 39 | #endif /* XAIECORE_AIE_H */ 40 | /** @} */ 41 | -------------------------------------------------------------------------------- /driver/src/core/xaie_core_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_core_aieml.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for aie-ml core apis. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/02/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIECORE_AIEML_H 24 | #define XAIECORE_AIEML_H 25 | /***************************** Include Files *********************************/ 26 | #include "xaie_helper.h" 27 | /************************** Function Prototypes *****************************/ 28 | AieRC _XAieMl_CoreConfigureDone(XAie_DevInst *DevInst, XAie_LocType Loc, 29 | const struct XAie_CoreMod *CoreMod); 30 | AieRC _XAieMl_CoreEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 31 | const struct XAie_CoreMod *CoreMod); 32 | AieRC _XAieMl_CoreWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 33 | u32 TimeOut, const struct XAie_CoreMod *CoreMod); 34 | AieRC _XAieMl_CoreReadDoneBit(XAie_DevInst *DevInst, XAie_LocType Loc, 35 | u8 *DoneBit, const struct XAie_CoreMod *CoreMod); 36 | AieRC _XAieMl_CoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | u32 *CoreStatus, const struct XAie_CoreMod *CoreMod); 38 | 39 | #endif /* XAIECORE_AIEML_H */ 40 | /** @} */ 41 | -------------------------------------------------------------------------------- /driver/src/core/xaie_elfloader.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_elfloader.h 10 | * @{ 11 | * 12 | * Header file for core elf loader functions 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Tejus   05/26/2020  Add API to load elf from memory.
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIELOADER_H 26 | #define XAIELOADER_H 27 | 28 | #include "xaie_feature_config.h" 29 | #ifdef XAIE_FEATURE_ELF_ENABLE 30 | 31 | /***************************** Include Files *********************************/ 32 | #include 33 | #include 34 | #include 35 | #include "xaie_helper.h" 36 | #include "xaiegbl.h" 37 | #include "xaiegbl_defs.h" 38 | #include "xaiegbl_defs.h" 39 | 40 | /************************** Constant Definitions *****************************/ 41 | #define XAIE_LOAD_ELF_TXT (1U << 0U) 42 | #define XAIE_LOAD_ELF_BSS (1U << 1U) 43 | #define XAIE_LOAD_ELF_DATA (1U << 2U) 44 | #define XAIE_LOAD_ELF_ALL (XAIE_LOAD_ELF_TXT | XAIE_LOAD_ELF_BSS | \ 45 | XAIE_LOAD_ELF_DATA) 46 | 47 | /************************** Variable Definitions *****************************/ 48 | typedef struct { 49 | u32 start; /**< Stack start address */ 50 | u32 end; /**< Stack end address */ 51 | } XAieSim_StackSz; 52 | /************************** Function Prototypes *****************************/ 53 | 54 | AieRC XAie_LoadElf(XAie_DevInst *DevInst, XAie_LocType Loc, const char *ElfPtr, 55 | u8 LoadSym); 56 | AieRC XAie_LoadElfMem(XAie_DevInst *DevInst, XAie_LocType Loc, 57 | const unsigned char* ElfMem); 58 | AieRC XAie_LoadElfSection(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | const unsigned char *SectionPtr, const Elf32_Phdr *Phdr); 60 | AieRC XAie_LoadElfSectionBlock(XAie_DevInst *DevInst, XAie_LocType Loc, 61 | const unsigned char* SectionPtr, u64 TgtAddr, u32 Size); 62 | AieRC XAie_LoadElfPartial(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | const char* ElfPtr, u8 Sections, u8 LoadSym); 64 | 65 | void _XAie_PrintElfHdr(const Elf32_Ehdr *Ehdr); 66 | void _XAie_PrintProgSectHdr(const Elf32_Phdr *Phdr); 67 | #endif /* XAIE_FEATURE_ELF_ENABLE */ 68 | #endif /* end of protection macro */ 69 | /** @} */ 70 | -------------------------------------------------------------------------------- /driver/src/core/xaie_uc.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_uc.h 10 | * @{ 11 | * 12 | * Header file for core uc loader functions 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Kishan  12/23/2022  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIEUCLOADER_H 24 | #define XAIEUCLOADER_H 25 | 26 | #include "xaie_feature_config.h" 27 | #ifdef XAIE_FEATURE_UC_ENABLE 28 | 29 | /***************************** Include Files *********************************/ 30 | #include "xaiegbl.h" 31 | #include "xaiegbl_regdef.h" 32 | 33 | /************************** Function Prototypes *****************************/ 34 | 35 | AieRC _XAie_UcCoreWakeup(XAie_DevInst *DevInst, XAie_LocType Loc, 36 | const struct XAie_UcMod *UcMod); 37 | AieRC _XAie_UcCoreSleep(XAie_DevInst *DevInst, XAie_LocType Loc, 38 | const struct XAie_UcMod *UcMod); 39 | AieRC _XAie_UcCoreGetStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 40 | u32 *CoreStatus, const struct XAie_UcMod *UcMod); 41 | 42 | #endif /* XAIE_FEATURE_UC_ENABLE */ 43 | 44 | #endif /* end of protection macro */ 45 | /** @} */ 46 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aie.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aie. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   05/03/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIE 24 | #define XAIE_DEVICE_AIE 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAie_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAie_SetPartColShimReset(XAie_DevInst *DevInst, u8 Enable); 30 | AieRC _XAie_SetPartColClockAfterRst(XAie_DevInst *DevInst, u8 Enable); 31 | AieRC _XAie_SetPartIsolationAfterRst(XAie_DevInst *DevInst, u8 ClearIsolation); 32 | AieRC _XAie_PartMemZeroInit(XAie_DevInst *DevInst); 33 | AieRC _XAie_RequestTiles(XAie_DevInst *DevInst, XAie_BackendTilesArray *Args); 34 | AieRC _XAie_SetColumnClk(XAie_DevInst *DevInst, XAie_BackendColumnReq *Args); 35 | 36 | #endif /* XAIE_DEVICE_AIE */ 37 | /** @} */ 38 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aie2ps.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aie2p.c 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aie2p ipu. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who     Date     Changes
 18 | * ----- ------  -------- -----------------------------------------------------
 19 | * 1.0   Keerthanna   01/25/2023  Initial creation
 20 | *
21 | * 22 | ******************************************************************************/ 23 | /***************************** Include Files *********************************/ 24 | #include "xaie_helper.h" 25 | 26 | /************************** Function Definitions *****************************/ 27 | /*****************************************************************************/ 28 | /** 29 | * 30 | * This is the function used to get the tile type for a given device instance 31 | * and tile location. 32 | * 33 | * @param DevInst: Device Instance 34 | * @param Loc: Location of the AIE tile. 35 | * @return TileType (AIETILE/MEMTILE/SHIMPL/SHIMNOC on success and MAX on 36 | * error) 37 | * 38 | * @note Internal API only. This API returns tile type based on all 39 | * tiles on row 0 being shim noc tiles. 40 | * 41 | ******************************************************************************/ 42 | u8 _XAie2PS_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc) 43 | { 44 | 45 | if(Loc.Col >= DevInst->NumCols) { 46 | XAIE_ERROR("Invalid column: %d\n", Loc.Col); 47 | return XAIEGBL_TILE_TYPE_MAX; 48 | } 49 | 50 | if(Loc.Row == 0U) { 51 | return XAIEGBL_TILE_TYPE_SHIMNOC; 52 | } else if(Loc.Row >= DevInst->MemTileRowStart && 53 | (Loc.Row < (DevInst->MemTileRowStart + 54 | DevInst->MemTileNumRows))) { 55 | return XAIEGBL_TILE_TYPE_MEMTILE; 56 | } else if (Loc.Row >= DevInst->AieTileRowStart && 57 | (Loc.Row < (DevInst->AieTileRowStart + 58 | DevInst->AieTileNumRows))) { 59 | return XAIEGBL_TILE_TYPE_AIETILE; 60 | } 61 | 62 | XAIE_ERROR("Cannot find Tile Type\n"); 63 | 64 | return XAIEGBL_TILE_TYPE_MAX; 65 | } 66 | 67 | AieRC _XAie2PS_SetAxiMMIsolation(XAie_DevInst* DevInst, u8 IsolationFlags) 68 | { 69 | AieRC RC = XAIE_OK; 70 | u64 RegAddr; 71 | u32 RegVal; 72 | u8 TileType; 73 | static const XAie_AxiMMTileCtrlMod *AxiMMTileCtrlMod; 74 | 75 | for(u8 Col = 0; Col < DevInst->NumCols; Col++) { 76 | TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, 77 | XAie_TileLoc(Col, 0U)); 78 | if(TileType != XAIEGBL_TILE_TYPE_SHIMNOC && 79 | TileType != XAIEGBL_TILE_TYPE_SHIMPL) { 80 | continue; 81 | } 82 | AxiMMTileCtrlMod = DevInst->DevProp.DevMod[TileType].AxiMMTileCtrlMod; 83 | RegVal = 0U; 84 | 85 | if(IsolationFlags == XAIE_INIT_ISOLATION) { 86 | if(Col == 0U) { 87 | RegVal |= AxiMMTileCtrlMod->AxiMMIsolateWest.Mask; 88 | } 89 | if(Col == (u8)(DevInst->NumCols - 1U)) { 90 | RegVal |= AxiMMTileCtrlMod->AxiMMIsolateEast.Mask; 91 | } 92 | } 93 | 94 | if(Col == 0U && (IsolationFlags & XAIE_INIT_WEST_ISOLATION)) { 95 | RegVal |= AxiMMTileCtrlMod->AxiMMIsolateWest.Mask; 96 | } 97 | if(Col == (u8)(DevInst->NumCols - 1U) && (IsolationFlags & XAIE_INIT_EAST_ISOLATION)) { 98 | RegVal |= AxiMMTileCtrlMod->AxiMMIsolateEast.Mask; 99 | } 100 | 101 | RegAddr = XAie_GetTileAddr(DevInst, 0U, Col) + 102 | AxiMMTileCtrlMod->TileCtrlAxiMMRegOff; 103 | RC = XAie_Write32(DevInst, RegAddr, RegVal); 104 | } 105 | return RC; 106 | } 107 | 108 | /** @} */ 109 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aie2p.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aie. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Keerthanna   01/25/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIE2PS_H 24 | #define XAIE_DEVICE_AIE2PS_H 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAie2PS_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAie2PS_SetAxiMMIsolation(XAie_DevInst* DevInst, u8 IsolationFlags); 30 | 31 | #endif /* XAIE_DEVICE_AIE2P */ 32 | /** @} */ 33 | -------------------------------------------------------------------------------- /driver/src/device/xaie_device_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_device_aieml.h 10 | * @{ 11 | * 12 | * This file contains the apis for device specific operations of aieml. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   05/03/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_DEVICE_AIEML 24 | #define XAIE_DEVICE_AIEML 25 | 26 | /***************************** Include Files *********************************/ 27 | /************************** Function Prototypes *****************************/ 28 | u8 _XAieMl_GetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc); 29 | AieRC _XAieMl_SetPartColShimReset(XAie_DevInst *DevInst, u8 Enable); 30 | AieRC _XAieMl_SetPartColClockAfterRst(XAie_DevInst *DevInst, u8 Enable); 31 | AieRC _XAieMl_SetPartIsolationAfterRst(XAie_DevInst *DevInst, u8 ClearIsolation); 32 | AieRC _XAieMl_PartMemZeroInit(XAie_DevInst *DevInst); 33 | AieRC _XAieMl_RequestTiles(XAie_DevInst *DevInst, XAie_BackendTilesArray *Args); 34 | AieRC _XAieMl_SetColumnClk(XAie_DevInst *DevInst, XAie_BackendColumnReq *Args); 35 | 36 | #endif /* XAIE_DEVICE_AIEML */ 37 | /** @} */ 38 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aie.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/23/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIE_H 25 | #define XAIE_DMA_AIE_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Function Prototypes *****************************/ 30 | void _XAie_TileDmaInit(XAie_DmaDesc *Desc); 31 | void _XAie_ShimDmaInit(XAie_DmaDesc *Desc); 32 | AieRC _XAie_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock Acq, XAie_Lock Rel, 33 | u8 AcqEn, u8 RelEn); 34 | AieRC _XAie_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 35 | XAie_LocType Loc, u8 BdNum); 36 | AieRC _XAie_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 37 | XAie_LocType Loc, u8 BdNum); 38 | AieRC _XAie_TileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 39 | XAie_LocType Loc, u8 BdNum); 40 | AieRC _XAie_TileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 41 | XAie_LocType Loc, u8 BdNum); 42 | AieRC _XAie_DmaSetInterleaveEnable(XAie_DmaDesc *DmaDesc, u8 DoubleBuff, 43 | u8 IntrleaveCount, u16 IntrleaveCurr); 44 | AieRC _XAie_DmaSetMultiDim(XAie_DmaDesc *DmaDesc, XAie_DmaTensor *Tensor); 45 | AieRC _XAie_DmaGetPendingBdCount(XAie_DevInst *DevInst, XAie_LocType Loc, 46 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 47 | u8 *PendingBd); 48 | AieRC _XAie_DmaWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 50 | u32 TimeOutUs); 51 | AieRC _XAie_DmaGetChannelStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 53 | u32 *Status); 54 | AieRC _XAie_DmaCheckBdChValidity(u8 BdNum, u8 ChNum); 55 | AieRC _XAie_DmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 56 | XAie_LocType Loc, u32 Len, u16 BdNum); 57 | AieRC _XAie_ShimDmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 58 | XAie_LocType Loc, u32 Len, u16 BdNum); 59 | AieRC _XAie_DmaUpdateBdAddr(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 60 | XAie_LocType Loc, u64 Addr, u16 BdNum); 61 | AieRC _XAie_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 62 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 63 | u16 BdNum); 64 | AieRC _XAie_DmaSetBdIteration(XAie_DmaDesc *DmaDesc, u32 StepSize, u16 Wrap, 65 | u8 IterCurr); 66 | 67 | #endif /* XAIE_DMA_AIE_H */ 68 | /** @} */ 69 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aie2ps.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who	Date	Changes
19 | * ----- ------     --------    -----------------------------------------------------
20 | * 1.0   Sanakrji   10/04/2022  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIE2PS_H 25 | #define XAIE_DMA_AIE2PS_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | 30 | typedef enum { XAIE_UC_MODULE__DMA_DIR__DM2MM, 31 | XAIE_UC_MODULE__DMA_DIR__MM2DM, 32 | XAIE_UC_MODULE__DMA_DIR__MAX 33 | } UcDmaDir_enum; 34 | 35 | /************************** Function Prototypes *****************************/ 36 | AieRC _XAie2PS_MemTileDmaWriteBd(XAie_DevInst *DevInst, XAie_DmaDesc *DmaDesc, 37 | XAie_LocType Loc, u8 BdNum); 38 | AieRC _XAie2PS_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 39 | XAie_LocType Loc, u8 BdNum); 40 | AieRC _XAie2PS_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 41 | XAie_LocType Loc, u8 BdNum); 42 | 43 | AieRC _XAie2PS_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 44 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 45 | u16 BdNum); 46 | AieRC _XAie2PS_AxiBurstLenCheck(u8 BurstLen, u8 *AxiBurstLen); 47 | AieRC XAie_GetUcDmaAxiMmOutstandingTxn(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | u32 *Status); 49 | AieRC XAie_GetNocDmaAxiMmOutstandingTxn(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | u32 *Status); 51 | #endif /* XAIE_DMA_AIE2PS_H */ 52 | /** @} */ 53 | -------------------------------------------------------------------------------- /driver/src/dma/xaie_dma_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_dma_aieml.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML DMA configuration and controls. This 13 | * header file is not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/23/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_DMA_AIEML_H 25 | #define XAIE_DMA_AIEML_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | 30 | /************************** Function Prototypes *****************************/ 31 | void _XAieMl_ShimDmaInit(XAie_DmaDesc *Desc); 32 | void _XAieMl_TileDmaInit(XAie_DmaDesc *Desc); 33 | void _XAieMl_MemTileDmaInit(XAie_DmaDesc *Desc); 34 | AieRC _XAieMl_DmaSetLock(XAie_DmaDesc *DmaDesc, XAie_Lock Acq, XAie_Lock Rel, 35 | u8 AcqEn, u8 RelEn); 36 | AieRC _XAieMl_MemTileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 37 | XAie_LocType Loc, u8 BdNum); 38 | AieRC _XAieMl_MemTileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 39 | XAie_LocType Loc, u8 BdNum); 40 | AieRC _XAieMl_TileDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 41 | XAie_LocType Loc, u8 BdNum); 42 | AieRC _XAieMl_TileDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 43 | XAie_LocType Loc, u8 BdNum); 44 | AieRC _XAieMl_ShimDmaWriteBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 45 | XAie_LocType Loc, u8 BdNum); 46 | AieRC _XAieMl_ShimDmaReadBd(XAie_DevInst *DevInst , XAie_DmaDesc *DmaDesc, 47 | XAie_LocType Loc, u8 BdNum); 48 | AieRC _XAieMl_DmaSetMultiDim(XAie_DmaDesc *DmaDesc, XAie_DmaTensor *Tensor); 49 | AieRC _XAieMl_DmaGetPendingBdCount(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 51 | u8 *PendingBd); 52 | AieRC _XAieMl_DmaWaitForDone(XAie_DevInst *DevInst, XAie_LocType Loc, 53 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 54 | u32 TimeOutUs); 55 | AieRC _XAieMl_DmaGetChannelStatus(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | const XAie_DmaMod *DmaMod, u8 ChNum, XAie_DmaDirection Dir, 57 | u32 *Status); 58 | AieRC _XAieMl_DmaCheckBdChValidity(u8 BdNum, u8 ChNum); 59 | AieRC _XAieMl_MemTileDmaCheckBdChValidity(u8 BdNum, u8 ChNum); 60 | AieRC _XAieMl_DmaUpdateBdLen(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 61 | XAie_LocType Loc, u32 Len, u16 BdNum); 62 | AieRC _XAieMl_ShimDmaUpdateBdLen(XAie_DevInst *DevInst, 63 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u32 Len, u16 BdNum); 64 | AieRC _XAieMl_DmaUpdateBdAddr(XAie_DevInst *DevInst, const XAie_DmaMod *DmaMod, 65 | XAie_LocType Loc, u64 Addr, u16 BdNum); 66 | AieRC _XAieMl_ShimDmaUpdateBdAddr(XAie_DevInst *DevInst, 67 | const XAie_DmaMod *DmaMod, XAie_LocType Loc, u64 Addr, 68 | u16 BdNum); 69 | AieRC _XAieMl_DmaSetBdIteration(XAie_DmaDesc *DmaDesc, u32 StepSize, u16 Wrap, 70 | u8 IterCurr); 71 | 72 | #endif /* XAIE_DMA_AIEML_H */ 73 | /** @} */ 74 | -------------------------------------------------------------------------------- /driver/src/global/xaie_feature_config.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | /*****************************************************************************/ 7 | /** 8 | * @file xaie_feature_config.h 9 | * @{ 10 | * 11 | * This file contains macros to optionally enable AI engine feaures during 12 | * compilation to reduce binary size. 13 | * We have one macro per feature, and for easier to use, we have feature groups 14 | * macros. Here are the groups macros: 15 | * * XAIE_FEATURE_APP_BASIC: basic features commonly needed for runtime on 16 | * target application. It includes the following features: 17 | * * XAIE_FEATURE_CORE_ENABLE: AIE tile core module APIs 18 | * * XAIE_FEATURE_DMA_ENABLE: AIE DMA APIs 19 | * * XAIE_FEATURE_LOCK_ENABLE: AIE lock APIs 20 | * * XAIE_FEATURE_DATAMEM_ENABLE: AIE data memory APIs 21 | * * XAIE_FEATURE_PRIVILEGED: features commonly needed for the library which 22 | * needs privileged permission for platform management 23 | * * XAIE_FEATURE_PRIVILEGED_ENABLE: AIE APIs which needs to access 24 | * privileged registers. As such operations are column reset, 25 | * shim reset, AXI bus error events setting, NPI interrupt 26 | * setting, and memory clearing. It will enable the following 27 | * features: 28 | * * XAIE_FEATURE_PL_ENABLE: AIE SHIM PL APIs 29 | * * XAIE_FEATURE_DATAMEM_ENABLE 30 | * * XAIE_FEATURE_INTR_CTRL_ENABLE: AIE interrupt enable/disable APIs 31 | * * XAIE_FEATURE_INTR_BTRK_ENABLE: AIE interrupt back tracking 32 | * * XAIE_FEATURE_ALL: all AIE APIs 33 | * * XAIE_FEATURE_CORE_ENABLE 34 | * * XAIE_FEATURE_DMA_ENABLE 35 | * * XAIE_FEATURE_LOCK_ENABLE 36 | * * XAIE_FEATURE_PRIVILEGED_ENABLE 37 | * * XAIE_FEATURE_DATAMEM_ENABLE 38 | * * XAIE_FEATURE_PERFCOUNT_ENABLE: AIE performance counter APIs 39 | * * XAIE_FEATURE_TIMER_ENABLE: AIE timer APIs 40 | * * XAIE_FEATURE_TRACE_ENABLE: AIE tracing APIs 41 | * * XAIE_FEATURE_SS_ENABLE: AIE stream switch APIs 42 | * * XAIE_FEATURE_EVENTS_ENABLE: AIE events APIs 43 | * * XAIE_FEATURE_ELF_ENABLE: AIE ELF loader APIs 44 | * * XAIE_FEATURE_UC_ENABLE: AIE SHIM microcontroller APIs 45 | * * XAIE_FEATURE_INTR_INIT_ENABLE: AIE interrupt network initialization APIs 46 | * * XAIE_FEATURE_UTIL_ENABLE: AIE Utility APIs 47 | * 48 | * 
 49 | * MODIFICATION HISTORY:
 50 | *
 51 | * Ver   Who     Date     Changes
 52 | * ----- ------  -------- -----------------------------------------------------
 53 | * 1.0   Wendy   07/27/2021  Initial creation
 54 | *
55 | * 56 | ******************************************************************************/ 57 | #ifndef XAIE_FEATURE_CONFIG_H 58 | #define XAIE_FEATURE_CONFIG_H 59 | 60 | #ifndef XAIE_FEATURE_APP_BASIC 61 | #ifndef XAIE_FEATURE_PRIVILEGED 62 | #ifndef XAIE_FEATURE_ALL 63 | /* Define is all features */ 64 | #define XAIE_FEATURE_ALL 65 | #endif 66 | #endif 67 | #endif 68 | 69 | #ifdef XAIE_FEATURE_APP_BASIC 70 | #define XAIE_FEATURE_CORE_ENABLE 71 | #define XAIE_FEATURE_DMA_ENABLE 72 | #define XAIE_FEATURE_LOCK_ENABLE 73 | #define XAIE_FEATURE_DATAMEM_ENABLE 74 | #endif /* XAIE_FEATURE_APP_BASIC */ 75 | 76 | #ifdef XAIE_FEATURE_PRIVILEGED 77 | #define XAIE_FEATURE_PRIVILEGED_ENABLE 78 | #define XAIE_FEATURE_INTR_BTRK_ENABLE 79 | #endif 80 | 81 | #ifdef XAIE_FEATURE_ALL 82 | #define XAIE_FEATURE_PRIVILEGED_ENABLE 83 | #define XAIE_FEATURE_PL_ENABLE 84 | #define XAIE_FEATURE_DMA_ENABLE 85 | #define XAIE_FEATURE_LOCK_ENABLE 86 | #define XAIE_FEATURE_DATAMEM_ENABLE 87 | #define XAIE_FEATURE_PERFCOUNT_ENABLE 88 | #define XAIE_FEATURE_TIMER_ENABLE 89 | #define XAIE_FEATURE_TRACE_ENABLE 90 | #define XAIE_FEATURE_SS_ENABLE 91 | #define XAIE_FEATURE_EVENTS_ENABLE 92 | #define XAIE_FEATURE_CORE_ENABLE 93 | #define XAIE_FEATURE_ELF_ENABLE 94 | #define XAIE_FEATURE_UC_ENABLE 95 | #define XAIE_FEATURE_INTR_INIT_ENABLE 96 | #define XAIE_FEATURE_INTR_BTRK_ENABLE 97 | #define XAIE_FEATURE_UTIL_ENABLE 98 | #define XAIE_FEATURE_UTIL_STATUS_ENABLE 99 | #define XAIE_FEATURE_ROUTING_ENABLE 100 | #endif /* XAIE_FEATURE_FULL */ 101 | 102 | #if defined(XAIE_FEATURE_INTR_INIT_ENABLE) || \ 103 | defined(XAIE_FEATURE_INTR_CTRL_ENABLE) || \ 104 | defined(XAIE_FEATURE_INTR_BTRK_ENABLE) 105 | #ifndef XAIE_FEATURE_INTR_L1_ENABLE 106 | #define XAIE_FEATURE_INTR_L1_ENABLE 107 | #endif 108 | #ifndef XAIE_FEATURE_INTR_L2_ENABLE 109 | #define XAIE_FEATURE_INTR_L2_ENABLE 110 | #endif 111 | #endif 112 | 113 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 114 | #ifndef XAIE_FEATURE_PL_ENABLE 115 | #define XAIE_FEATURE_PL_ENABLE 116 | #endif 117 | #ifndef XAIE_FEATURE_INTR_CTRL_ENABLE 118 | #define XAIE_FEATURE_INTR_CTRL_ENABLE 119 | #endif 120 | #ifndef XAIE_FEATURE_DATAMEM_ENABLE 121 | #define XAIE_FEATURE_DATAMEM_ENABLE 122 | #endif 123 | #endif 124 | 125 | #endif /* XAIE_FEATURE_CONFIG_H */ 126 | /** @} */ 127 | -------------------------------------------------------------------------------- /driver/src/global/xaiegbl_defs.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaiegbl_defs.h 10 | * @{ 11 | * 12 | * This file contains the generic definitions for the AIE drivers. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0  Naresh  03/23/2018  Initial creation
20 | * 1.1  Naresh  07/11/2018  Updated copyright info
21 | * 1.2  Hyun    10/10/2018  Added the mask write API
22 | * 1.3  Nishad  12/05/2018  Renamed ME attributes to AIE
23 | * 1.4  Hyun    01/08/2019  Add the mask poll function
24 | * 1.5  Tejus   08/01/2019  Restructure code for AIE
25 | * 1.6  Dishita 04/17/2020  Fix compiler warning
26 | * 1.7  Dishita 05/07/2020  Removed Reset related macros
27 | * 1.8  Tejus   06/09/2020  Remove NPI apis.
28 | *
29 | * 30 | ******************************************************************************/ 31 | #ifndef XAIEGBL_DEFS_H 32 | #define XAIEGBL_DEFS_H 33 | 34 | /***************************** Include Files *********************************/ 35 | #include 36 | #include 37 | 38 | /************************** Constant Definitions *****************************/ 39 | typedef int8_t s8; 40 | typedef uint8_t u8; 41 | typedef uint16_t u16; 42 | typedef int32_t s32; 43 | typedef uint32_t u32; 44 | typedef uint64_t u64; 45 | 46 | #define XAIE_DEV_GENERIC_DEVICE 0U 47 | #define XAIE_DEV_GEN_AIE 1U 48 | #define XAIE_DEV_GEN_AIEML 2U 49 | #define XAIE_DEV_GEN_AIE2PS 5U 50 | #define XAIE_DEV_GEN_S100 6U 51 | #define XAIE_DEV_GEN_S200 7U 52 | 53 | #define XAIE_COMPONENT_IS_READY 1U 54 | 55 | #define XAIE_NULL (void *)0U 56 | #define XAIE_ENABLE 1U 57 | #define XAIE_DISABLE 0U 58 | 59 | #define XAIEGBL_TILE_TYPE_AIETILE 0U 60 | #define XAIEGBL_TILE_TYPE_SHIMNOC 1U 61 | #define XAIEGBL_TILE_TYPE_SHIMPL 2U 62 | #define XAIEGBL_TILE_TYPE_MEMTILE 3U 63 | #define XAIEGBL_TILE_TYPE_MAX 4U 64 | 65 | #define XAie_SetField(Val, Lsb, Mask) (((u32)(Val) << (Lsb)) & (Mask)) 66 | #define XAie_GetField(Val, Lsb, Mask) (((u32)(Val) & (Mask)) >> (Lsb)) 67 | 68 | #define __FORCE_INLINE__ __attribute__((always_inline)) 69 | 70 | /************************** Variable Definitions *****************************/ 71 | /************************** Function Prototypes *****************************/ 72 | #endif /* end of protection macro */ 73 | /** @} */ 74 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt.h 10 | * @{ 11 | * 12 | * Header file for AIE interrupt module. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Nishad  07/21/2020  Initial creation
20 | * 1.1   Nishad  07/23/2020  Add APIs to configure second level interrupt
21 | *			    controller.
22 | * 1.2   Nishad  07/23/2020  Add API to initialize error broadcast network.
23 | * 1.3   Nishad  08/13/2020  Add macro for error broadcast mask.
24 | *
25 | * 26 | ******************************************************************************/ 27 | #ifndef XAIE_INTERRUPT_H 28 | #define XAIE_INTERRUPT_H 29 | 30 | /***************************** Include Files *********************************/ 31 | #include "xaie_events.h" 32 | #include "xaie_core.h" 33 | 34 | /**************************** Type Definitions *******************************/ 35 | #define XAIE_ERROR_BROADCAST_ID 0x0U 36 | #define XAIE_ERROR_BROADCAST_MASK 0x1U 37 | 38 | #define XAIE_ERROR_BROADCAST_ID_UC_EVENT 0x1U 39 | #define XAIE_ERROR_BROADCAST_ID_USER_EVENT1 0x2U 40 | 41 | #define XAIE_ERROR_SHIM_INTR_ID 0x10U 42 | #define XAIE_ERROR_SHIM_INTR_MASK 0x10000U 43 | #define XAIE_ERROR_NPI_INTR_ID 0x1U 44 | #define XAIE_ERROR_L2_ENABLE 0x3FU 45 | 46 | /************************** Function Prototypes *****************************/ 47 | AieRC XAie_IntrCtrlL1Enable(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | XAie_BroadcastSw Switch, u8 IntrId); 49 | AieRC XAie_IntrCtrlL1Disable(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | XAie_BroadcastSw Switch, u8 IntrId); 51 | AieRC XAie_IntrCtrlL1IrqSet(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | XAie_BroadcastSw Switch, u8 BroadcastId); 53 | AieRC XAie_IntrCtrlL1Event(XAie_DevInst *DevInst, XAie_LocType Loc, 54 | XAie_BroadcastSw Switch, u8 IrqEventId, XAie_Events Event); 55 | AieRC XAie_IntrCtrlL1BroadcastBlock(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | XAie_BroadcastSw Switch, u32 ChannelBitMap); 57 | AieRC XAie_IntrCtrlL1BroadcastUnblock(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | XAie_BroadcastSw Switch, u32 ChannelBitMap); 59 | AieRC XAie_IntrCtrlL2Enable(XAie_DevInst *DevInst, XAie_LocType Loc, 60 | u32 ChannelBitMap); 61 | AieRC XAie_IntrCtrlL2Disable(XAie_DevInst *DevInst, XAie_LocType Loc, 62 | u32 ChannelBitMap); 63 | AieRC XAie_ErrorHandlingInit(XAie_DevInst *DevInst); 64 | void XAie_DisableErrorInterrupts(u8 IrqId); 65 | 66 | AieRC XAie_BacktrackErrorInterrupts(XAie_DevInst *DevInst, 67 | XAie_ErrorMetaData *MData); 68 | 69 | #endif /* end of protection macro */ 70 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie.c 10 | * @{ 11 | * 12 | * This file contains AIE specific interrupt routines which are not exposed to 13 | * the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aie.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | 23 | /************************** Constant Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * This API computes first level IRQ broadcast ID. 28 | * 29 | * @param DevInst: Device Instance 30 | * @param Loc: Location of AIE Tile 31 | * @param Switch: Switch in the given module. For a shim tile, value 32 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 33 | * 34 | * @return IrqId: IRQ broadcast ID. 35 | * 36 | * @note IRQ ID for each switch block starts from 0, every block on the 37 | * left will increase by 1 until it reaches the first Shim NoC 38 | * column. The IRQ ID restarts from 0 on the switch A of the 39 | * second shim NoC column. For the shim PL columns after the 40 | * second Shim NoC, if there is no shim NoC further right, the 41 | * column will use the shim NoC on the left. That is the L1 IRQ 42 | * broadcast ID pattern, 43 | * For column from 0 to 43 is: 0 1 2 3 4 5 0 1 44 | * For column from 44 to 49 is: 0 1 2 3 4 5 0 1 2 3 4 5 45 | * 46 | * Internal Only. 47 | ******************************************************************************/ 48 | u8 _XAie_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | XAie_BroadcastSw Switch) 50 | { 51 | u8 IrqId = (((Loc.Col % 4U) % 3U) * 2U) + (u8)Switch; 52 | 53 | if (Loc.Col + 3U > DevInst->NumCols) { 54 | IrqId += 2U; 55 | } 56 | 57 | return IrqId; 58 | } 59 | 60 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 61 | 62 | /** @} */ 63 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific AIE. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIE_H 16 | #define XAIE_INTERRUPT_AIE_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAie_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie2ps.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie2ps.c 10 | * @{ 11 | * 12 | * This file contains AIE2PS specific interrupt routines which are not exposed 13 | * to the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aie2ps.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | /************************** Constant Definitions *****************************/ 23 | /************************** Function Definitions *****************************/ 24 | /*****************************************************************************/ 25 | /** 26 | * This API computes first level IRQ broadcast ID. 27 | * 28 | * @param DevInst: Device Instance 29 | * @param Loc: Location of AIE Tile 30 | * @param Switch: Switch in the given module. For a shim tile, value 31 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 32 | * 33 | * @return IrqId: IRQ broadcast ID. 34 | * 35 | * @note AIE2PS has NOC tile in every SHIM tile. Each switch in L1 ctrl 36 | * maps to 0 or 1. 37 | * 38 | * Internal Only. 39 | ******************************************************************************/ 40 | u8 _XAie2ps_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 41 | XAie_BroadcastSw Switch) 42 | { 43 | (void)DevInst; 44 | (void)Loc; 45 | return Switch; 46 | } 47 | 48 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 49 | 50 | /** @} */ 51 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aie2ps.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific AIE2PS. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIE2PS_H 16 | #define XAIE_INTERRUPT_AIE2PS_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAie2ps_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | /** @} */ 26 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aieml.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aieml.c 10 | * @{ 11 | * 12 | * This file contains AIE ML specific interrupt routines which are not exposed 13 | * to the user. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_interrupt_aieml.h" 20 | 21 | #ifdef XAIE_FEATURE_INTR_INIT_ENABLE 22 | 23 | /************************** Constant Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * This API computes first level IRQ broadcast ID. 28 | * 29 | * @param DevInst: Device Instance 30 | * @param Loc: Location of AIE Tile 31 | * @param Switch: Switch in the given module. For a shim tile, value 32 | * could be XAIE_EVENT_SWITCH_A or XAIE_EVENT_SWITCH_B. 33 | * 34 | * @return IrqId: IRQ broadcast ID. 35 | * 36 | * @note IRQ ID for each switch block starts from 0, every block on the 37 | * left will increase by 1 until it reaches the first Shim NoC 38 | * column. The IRQ ID restarts from 0 on the switch A of the 39 | * second shim NoC column. For the shim PL columns after the 40 | * second Shim NoC, if there is no shim NoC further right, the 41 | * column will use the shim NoC on the left. That is the L1 IRQ 42 | * broadcast ID pattern, 43 | * For column from 0 to 43 is: 0 1 2 3 4 5 0 1 44 | * For column from 44 to 49 is: 0 1 2 3 4 5 0 1 2 3 4 5 45 | * 46 | * Internal Only. 47 | ******************************************************************************/ 48 | u8 _XAieMl_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | XAie_BroadcastSw Switch) 50 | { 51 | u8 TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 52 | 53 | if (TileType != XAIEGBL_TILE_TYPE_SHIMNOC) { 54 | if (((Loc.Col / 4U) * 4U + 2U) < DevInst->NumCols) { 55 | /* There is SHIM NOC on the right */ 56 | return (Loc.Col % 4U) * 2U + (u8)Switch; 57 | } else { 58 | /* 59 | * if there is no SHIM NOC on the right, use the 60 | * SHIM NoC on the left. 61 | */ 62 | return (Loc.Col % 4U) * 2U + (u8)Switch + 2U; 63 | } 64 | } else { 65 | if ((Loc.Col % 4U) == 2U) { 66 | /* SHIM NoC on the left */ 67 | return 4U + (u8)Switch; 68 | } else { 69 | /* SHIM NoC on the right */ 70 | return (u8)Switch; 71 | } 72 | } 73 | } 74 | 75 | #endif /* XAIE_FEATURE_INTR_INIT_ENABLE */ 76 | 77 | /** @} */ 78 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_aieml.h 10 | * @{ 11 | * 12 | * Internal header file to capture interrupt APIs specific to AIE ML. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_INTERRUPT_AIEML_H 16 | #define XAIE_INTERRUPT_AIEML_H 17 | 18 | /***************************** Include Files *********************************/ 19 | /**************************** Type Definitions *******************************/ 20 | /************************** Function Prototypes *****************************/ 21 | u8 _XAieMl_IntrCtrlL1IrqId(XAie_DevInst *DevInst, XAie_LocType Loc, 22 | XAie_BroadcastSw Switch); 23 | 24 | #endif /* end of protection macro */ 25 | -------------------------------------------------------------------------------- /driver/src/interrupt/xaie_interrupt_control.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_interrupt_control.c 10 | * @{ 11 | * 12 | * This file implements routine for disabling AIE interrupts. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who     Date     Changes
 18 | * ----- ------  -------- -----------------------------------------------------
 19 | * 1.0   Nishad  08/20/2021  Initial creation
 20 | *
21 | * 22 | ******************************************************************************/ 23 | 24 | /***************************** Include Files *********************************/ 25 | #include "xaie_feature_config.h" 26 | #include "xaie_interrupt.h" 27 | #include "xaie_lite.h" 28 | #include "xaie_lite_io.h" 29 | 30 | #if defined(XAIE_FEATURE_INTR_CTRL_ENABLE) && defined(XAIE_FEATURE_LITE) 31 | 32 | /************************** Constant Definitions *****************************/ 33 | /************************** Function Definitions *****************************/ 34 | /*****************************************************************************/ 35 | /** 36 | * 37 | * This API returns the status of second-level interrupt controller. 38 | * 39 | * @param Loc: Location of AIE tile. 40 | * 41 | * @return Status: Status second-level interrupt controller. 42 | * 43 | * @note Internal only. 44 | * 45 | ******************************************************************************/ 46 | static inline u32 _XAie_LIntrCtrlL2Status(XAie_LocType Loc) 47 | { 48 | u64 RegAddr = _XAie_LGetTileAddr(Loc.Row, Loc.Col) + 49 | XAIE_NOC_MOD_INTR_L2_STATUS; 50 | return _XAie_LRead32(RegAddr); 51 | } 52 | 53 | /*****************************************************************************/ 54 | /** 55 | * 56 | * This API clears the status of interrupts in the second-level interrupt 57 | * controller. 58 | * 59 | * @param Loc: Location of AIE tile. 60 | * @param ChannelBitMap: Bitmap of channels to be acknowledged. Writing a 61 | * value of 1 to the register field clears the 62 | * corresponding interrupt channel. 63 | * 64 | * @return None. 65 | * 66 | * @note Internal only. 67 | * 68 | ******************************************************************************/ 69 | static inline void _XAie_LIntrCtrlL2Ack(XAie_LocType Loc, u32 ChannelBitMap) 70 | { 71 | u64 RegAddr = _XAie_LGetTileAddr(Loc.Row, Loc.Col) + 72 | XAIE_NOC_MOD_INTR_L2_STATUS; 73 | _XAie_LWrite32(RegAddr, ChannelBitMap); 74 | } 75 | 76 | /*****************************************************************************/ 77 | /** 78 | * 79 | * This API disables interrupts to second level interrupt controller. 80 | * 81 | * @param Loc: Location of AIE Tile 82 | * @param ChannelBitMap: Interrupt Bitmap. 83 | * 84 | * @return None. 85 | * 86 | * @note Internal Only. 87 | * 88 | ******************************************************************************/ 89 | static inline void _XAie_LIntrCtrlL2Disable(XAie_LocType Loc, u32 ChannelBitMap) 90 | { 91 | u64 RegAddr = _XAie_LGetTileAddr(Loc.Row, Loc.Col) + 92 | XAIE_NOC_MOD_INTR_L2_DISABLE; 93 | _XAie_LWrite32(RegAddr, ChannelBitMap); 94 | } 95 | 96 | /*****************************************************************************/ 97 | /** 98 | * 99 | * This API disables all second-level interrupt controllers reporting errors. 100 | * 101 | * @param IrqId: Zero indexed IRQ ID. Valid values corresponds to the 102 | * number of AIE IRQs mapped to the processor. 103 | * 104 | * @return None. 105 | * 106 | * @note None. 107 | * 108 | ******************************************************************************/ 109 | void XAie_DisableErrorInterrupts(u8 IrqId) 110 | { 111 | XAie_Range Cols; 112 | 113 | XAie_MapIrqIdToCols(IrqId, &Cols); 114 | 115 | XAie_LocType Loc = XAie_TileLoc(Cols.Start, XAIE_SHIM_ROW); 116 | 117 | if (!IS_TILE_NOC_TILE(Loc)) { 118 | UPDT_NEXT_NOC_TILE_LOC(Loc); 119 | } 120 | 121 | while (Loc.Col < Cols.Start + Cols.Num) { 122 | u32 Status; 123 | 124 | Status = _XAie_LIntrCtrlL2Status(Loc); 125 | 126 | /* Only disable L2s that are reporting errors. */ 127 | if (Status) { 128 | _XAie_LIntrCtrlL2Disable(Loc, Status); 129 | _XAie_LIntrCtrlL2Ack(Loc, Status); 130 | } 131 | 132 | UPDT_NEXT_NOC_TILE_LOC(Loc); 133 | } 134 | } 135 | 136 | #endif /* XAIE_FEATURE_INTR_CTRL_ENABLE */ 137 | 138 | /** @} */ 139 | -------------------------------------------------------------------------------- /driver/src/io_backend/ext/xaie_io_common.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_common.c 10 | * @{ 11 | * 12 | * This file contains routines for common io backend. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date        Changes
18 | * ----- ------  --------    ---------------------------------------------------
19 | * 1.0   Dishita 03/08/2021  Initial creation
20 | *
21 | *
22 | * 23 | ******************************************************************************/ 24 | /***************************** Include Files *********************************/ 25 | #include 26 | #include 27 | 28 | #include "xaie_feature_config.h" 29 | #include "xaie_io.h" 30 | #include "xaie_helper.h" 31 | #include "xaie_helper_internal.h" 32 | /*****************************************************************************/ 33 | /************************** Function Definitions *****************************/ 34 | /*****************************************************************************/ 35 | /** 36 | * This API marks the bitmap with for the tiles which are clock enabled. 37 | * 38 | * @param DevInst: AI engine partition device instance pointer 39 | * @param Args: Backend tile args 40 | * 41 | * @return XAIE_OK on success, error code on failure 42 | * 43 | * @note Internal only. 44 | * 45 | *******************************************************************************/ 46 | void _XAie_IOCommon_MarkTilesInUse(XAie_DevInst *DevInst, 47 | XAie_BackendTilesArray *Args) 48 | { 49 | /* Setup the requested tiles bitmap locally */ 50 | if (Args->Locs == NULL) { 51 | u32 StartBit, NumTiles; 52 | 53 | NumTiles = (u32)(DevInst->NumCols * (DevInst->NumRows - 1U)); 54 | /* Loc is NULL, it suggests all tiles are requested */ 55 | StartBit = _XAie_GetTileBitPosFromLoc(DevInst, 56 | XAie_TileLoc(0, 1)); 57 | _XAie_SetBitInBitmap(DevInst->DevOps->TilesInUse, StartBit, 58 | NumTiles); 59 | } else { 60 | for(u32 i = 0; i < Args->NumTiles; i++) { 61 | u32 Bit; 62 | 63 | if(Args->Locs[i].Row == 0U) { 64 | continue; 65 | } 66 | 67 | /* 68 | * If a tile is ungated, the rows below it are 69 | * ungated. 70 | */ 71 | Bit = _XAie_GetTileBitPosFromLoc(DevInst, 72 | XAie_TileLoc(Args->Locs[i].Col, 1)); 73 | _XAie_SetBitInBitmap(DevInst->DevOps->TilesInUse, 74 | Bit, Args->Locs[i].Row); 75 | } 76 | } 77 | } 78 | 79 | /** @} */ 80 | -------------------------------------------------------------------------------- /driver/src/io_backend/ext/xaie_io_common.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_common.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations that are common accross multiple backends. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   01/20/2021 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_COMMON_H 25 | #define XAIE_IO_COMMON_H 26 | 27 | static inline u64 XAie_IODummyGetTid(void) 28 | { 29 | return 0; 30 | } 31 | 32 | static inline int XAie_IODummyGetPartFd(void *IOInst) 33 | { 34 | (void)IOInst; 35 | return -1; 36 | } 37 | 38 | 39 | void _XAie_IOCommon_MarkTilesInUse(XAie_DevInst *DevInst, 40 | XAie_BackendTilesArray *Args); 41 | 42 | #endif /* XAIE_IO_COMMON_H */ 43 | 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/src/io_backend/privilege/xaie_io_privilege.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_privilege.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations that requires privilege permissions for multiple backends. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Wendy   05/17/2021 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_PRIVILEGE_H 25 | #define XAIE_IO_PRIVILEGE_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaie_dma_aie2ps.h" 29 | #include "xaiegbl.h" 30 | #include "xaie_io_privilege.h" 31 | 32 | AieRC _XAie_PrivilegeInitPart(XAie_DevInst *DevInst, XAie_PartInitOpts *Opts); 33 | AieRC _XAie_PrivilegeTeardownPart(XAie_DevInst *DevInst); 34 | AieRC _XAie_PrivilegeRequestTiles(XAie_DevInst *DevInst, 35 | XAie_BackendTilesArray *Args); 36 | AieRC _XAie_PrivilegeSetColumnClk(XAie_DevInst *DevInst, 37 | XAie_BackendColumnReq *Args); 38 | AieRC XAie_UcDmaPause(XAie_DevInst *DevInst, XAie_LocType *Loc, 39 | UcDmaDir_enum Dir, u8 Pause); 40 | AieRC XAie_NocDmaPause(XAie_DevInst *DevInst, XAie_LocType *Loc, 41 | u8 ChNum, XAie_DmaDirection Dir, u8 Pause); 42 | AieRC XAie_Privi2egeSetAxiMMIsolation(XAie_DevInst *DevInst, u8 IsolationFlags); 43 | #endif /* XAIE_IO_PRIVILEGE_H */ 44 | 45 | /** @} */ 46 | -------------------------------------------------------------------------------- /driver/src/io_backend/xaie_io_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | *****************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_io_internal.c 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for low level IO 13 | * operations. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Ssatpute   27/06/2020 Initial creation.
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_IO_INTERNAL_H 25 | #define XAIE_IO_INTERNAL_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | #include "xaie_io.h" 30 | 31 | /****************************** Type Definitions *****************************/ 32 | /************************** Function Prototypes *****************************/ 33 | const XAie_Backend* _XAie_GetBackendPtr(XAie_BackendType Backend); 34 | 35 | /*****************************************************************************/ 36 | /** 37 | * 38 | * Set the NPI write request arguments 39 | * 40 | * @param RegOff : NPI register offset 41 | * @param RegVal : Register Value 42 | * @return NPI write request 43 | * 44 | * @note Internal API only. 45 | * 46 | ******************************************************************************/ 47 | static inline XAie_BackendNpiWrReq 48 | _XAie_SetBackendNpiWrReq(u32 RegOff, u32 RegVal) 49 | { 50 | XAie_BackendNpiWrReq Req; 51 | 52 | Req.NpiRegOff = RegOff; 53 | Req.Val = RegVal; 54 | 55 | return Req; 56 | } 57 | 58 | /*****************************************************************************/ 59 | /** 60 | * 61 | * Set the NPI mask poll request arguments 62 | * 63 | * @param RegOff : NPI register offset 64 | * @param Mask : Mask Value 65 | * @param RegVal : Register Value 66 | * @param TimeOutUs : Time Out Value in us. 67 | * @return NPI mask poll request 68 | * 69 | * @note Internal API only. 70 | * 71 | ******************************************************************************/ 72 | static inline XAie_BackendNpiMaskPollReq 73 | _XAie_SetBackendNpiMaskPollReq(u32 RegOff, u32 Mask, u32 RegVal, u32 TimeOutUs) 74 | { 75 | XAie_BackendNpiMaskPollReq Req; 76 | 77 | Req.NpiRegOff = RegOff; 78 | Req.Val = RegVal; 79 | Req.Mask = Mask; 80 | Req.TimeOutUs = TimeOutUs; 81 | 82 | return Req; 83 | } 84 | 85 | #endif /* End of protection macro */ 86 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | /*****************************************************************************/ 7 | /** 8 | * @file xaie_lite.c 9 | * @{ 10 | * 11 | * This file contains lite routines. 12 | * 13 | * 
14 | * MODIFICATION HISTORY:
15 | *
16 | * Ver   Who     Date        Changes
17 | * ----- ------  --------    ---------------------------------------------------
18 | * 1.0   Nishad  06/23/2022  Initial creation
19 | *
20 | *
21 | * 22 | ******************************************************************************/ 23 | /***************************** Include Files *********************************/ 24 | 25 | #include "xaie_feature_config.h" 26 | 27 | #if defined(XAIE_FEATURE_PRIVILEGED_ENABLE) && defined(XAIE_FEATURE_LITE) 28 | 29 | #include "xaie_lite.h" 30 | #include "xaie_lite_internal.h" 31 | #include "xaiegbl_defs.h" 32 | #include "xaiegbl.h" 33 | 34 | /***************************** Macro Definitions *****************************/ 35 | /************************** Function Definitions *****************************/ 36 | /*****************************************************************************/ 37 | /** 38 | * 39 | * This API maps given IRQ ID to a range of columns it is programmed to receive 40 | * interrupts from. 41 | * 42 | * @param IrqId: 43 | * @param Range: Pointer to return column range mapping. 44 | * 45 | * @return XAIE_OK on success, error code on failure. 46 | * 47 | * @note None 48 | * 49 | ******************************************************************************/ 50 | AieRC XAie_MapIrqIdToCols(u8 IrqId, XAie_Range *Range) 51 | { 52 | XAIE_ERROR_RETURN(IrqId >= XAIE_MAX_NUM_NOC_INTR, XAIE_INVALID_ARGS, 53 | XAIE_ERROR_MSG("Invalid AIE IRQ ID\n")); 54 | 55 | XAie_Range Temp = _XAie_MapIrqIdToCols(IrqId); 56 | Range->Start = Temp.Start; 57 | Range->Num = Temp.Num; 58 | 59 | return XAIE_OK; 60 | } 61 | 62 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE && XAIE_FEATURE_LITE */ 63 | /** @} */ 64 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite.h 10 | * @{ 11 | * 12 | * This header file defines a lightweight version of AIE driver APIs. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0  Nishad  08/30/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_LITE_H 24 | #define XAIE_LITE_H 25 | 26 | #ifdef XAIE_FEATURE_LITE 27 | 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | #include "xaie_helper.h" 31 | 32 | #define XAie_LDeclareDevInst(DevInst, _BaseAddr, _StartCol, _NumCols) \ 33 | XAie_DevInst DevInst = { \ 34 | .BaseAddr = (_BaseAddr), \ 35 | .StartCol = (_StartCol), \ 36 | .NumCols = (_NumCols), \ 37 | .NumRows = (XAIE_NUM_ROWS), \ 38 | } 39 | 40 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 41 | #include "xaie_lite_aie.h" 42 | #include "xaie_lite_shim_aie.h" 43 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 44 | #include "xaie_lite_aieml.h" 45 | #include "xaie_lite_shim_aie.h" 46 | #else 47 | #include 48 | #endif 49 | 50 | #define XAIE_ERROR_MSG(...) \ 51 | "[AIE ERROR] %s():%d: %s", __func__, __LINE__, __VA_ARGS__ 52 | 53 | #ifdef XAIE_ENABLE_INPUT_CHECK 54 | #define XAIE_ERROR_RETURN(ERRCON, RET, ...) { \ 55 | if (ERRCON) { \ 56 | printf(__VA_ARGS__); \ 57 | return (RET); \ 58 | } \ 59 | } 60 | #else 61 | #define XAIE_ERROR_RETURN(...) 62 | #endif 63 | 64 | /************************** Variable Definitions *****************************/ 65 | /************************** Function Prototypes *****************************/ 66 | AieRC XAie_IsPartitionIdle(XAie_DevInst *DevInst); 67 | AieRC XAie_ClearPartitionContext(XAie_DevInst *DevInst); 68 | 69 | /************************** Function Definitions *****************************/ 70 | /*****************************************************************************/ 71 | /** 72 | * 73 | * This is API returns the location next NoC tile. 74 | * 75 | * @param DevInst: Device Instance 76 | * @param Loc: Location of the AIE tile. 77 | * 78 | * @note Internal only. 79 | * 80 | ******************************************************************************/ 81 | __FORCE_INLINE__ 82 | static inline XAie_LocType XAie_LPartGetNextNocTile(XAie_DevInst *DevInst, 83 | XAie_LocType Loc) 84 | { 85 | XAie_LocType lLoc = XAie_TileLoc((Loc.Col + DevInst->StartCol), 86 | Loc.Row); 87 | 88 | UPDT_NEXT_NOC_TILE_LOC(lLoc); 89 | return lLoc; 90 | } 91 | 92 | #endif /* XAIE_FEATURE_LITE */ 93 | 94 | #endif /* XAIE_LITE_H */ 95 | 96 | /** @} */ 97 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_hwcfg.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_hwcfg.h 10 | * @{ 11 | * 12 | * This header file capture hardware configurations for all supported devices. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who       Date        Changes
 18 | * ----- --------  --------    ------------------------------------------------
 19 | * 1.0  Nishad     06/23/2022  Initial creation
 20 | * 1.1  avasi      11/16/2022  Additions for Status Dump of Core Tile, Mem Tile
 21 | *                             and Shim Tile registers.
 22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIE_LITE_HWCFG_H 26 | #define XAIE_LITE_HWCFG_H 27 | 28 | #ifdef XAIE_FEATURE_LITE 29 | 30 | /***************************** Include Files *********************************/ 31 | /************************** Constant Definitions *****************************/ 32 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 33 | 34 | #ifndef XAIE_BASE_ADDR 35 | #define XAIE_BASE_ADDR 0x20000000000 36 | #endif 37 | 38 | #ifndef XAIE_NPI_BASEADDR 39 | #define XAIE_NPI_BASEADDR 0xF70A0000 40 | #endif 41 | 42 | #ifndef XAIE_NUM_ROWS 43 | #define XAIE_NUM_ROWS 9 44 | #endif 45 | 46 | #ifndef XAIE_NUM_COLS 47 | #define XAIE_NUM_COLS 50 48 | #endif 49 | 50 | #define XAIE_TILE_NUM_LOCKS 16 51 | #define XAIE_SHIM_NUM_LOCKS 16 52 | 53 | #define XAIE_TILE_DMA_NUM_CH 2U 54 | #define XAIE_SHIM_DMA_NUM_CH 2U 55 | 56 | #define XAIE_COL_SHIFT 23 57 | #define XAIE_ROW_SHIFT 18 58 | #define XAIE_SHIM_ROW 0 59 | #define XAIE_SHIM_NUM_ROWS 1 60 | #define XAIE_MEM_TILE_ROW_START 0 61 | #define XAIE_MEM_TILE_NUM_ROWS 0 62 | #define XAIE_AIE_TILE_ROW_START 1 63 | #define XAIE_AIE_TILE_NUM_ROWS 8 64 | #define XAIE_NUM_NOC_INTR_OFFSET 1 65 | 66 | #define XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS 4 67 | #define XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS 4 68 | 69 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 70 | 71 | #ifndef XAIE_BASE_ADDR 72 | #define XAIE_BASE_ADDR 0x20000000000 73 | #endif 74 | 75 | #ifndef XAIE_NPI_BASEADDR 76 | #define XAIE_NPI_BASEADDR 0xF6D10000 77 | #endif 78 | 79 | #ifndef XAIE_NUM_ROWS 80 | #define XAIE_NUM_ROWS 11 81 | #endif 82 | 83 | #ifndef XAIE_NUM_COLS 84 | #define XAIE_NUM_COLS 38 85 | #endif 86 | 87 | #define XAIE_TILE_NUM_LOCKS 16 88 | #define XAIE_MEM_TILE_NUM_LOCKS 64 89 | #define XAIE_SHIM_NUM_LOCKS 16 90 | 91 | #define XAIE_TILE_DMA_NUM_CH 2U 92 | #define XAIE_MEM_TILE_DMA_NUM_CH 6U 93 | #define XAIE_SHIM_DMA_NUM_CH 2U 94 | 95 | #define XAIE_COL_SHIFT 25 96 | #define XAIE_ROW_SHIFT 20 97 | #define XAIE_SHIM_ROW 0 98 | #define XAIE_SHIM_NUM_ROWS 1 99 | #define XAIE_MEM_TILE_ROW_START 1 100 | #define XAIE_MEM_TILE_NUM_ROWS 2 101 | #define XAIE_AIE_TILE_ROW_START 3 102 | #define XAIE_AIE_TILE_NUM_ROWS 8 103 | #define XAIE_NUM_NOC_INTR_OFFSET 1 104 | 105 | #define XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS 4 106 | #define XAIE_MEM_TILE_NUM_EVENT_STATUS_REGS 6 107 | #define XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS 4 108 | 109 | #else 110 | #include 111 | #endif 112 | 113 | #endif /* XAIE_FEATURE_LITE */ 114 | #endif /* end of protection macro */ 115 | 116 | /** @} */ 117 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 - 2023 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_io_internal.h 10 | * @{ 11 | * 12 | * This header file defines a lightweight version of AIE driver APIs. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who     Date     Changes
 18 | * ----- ------  -------- -----------------------------------------------------
 19 | * 1.0  Ssatpute  06/27/2021  Initial creation
 20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_LITE_IO_INTERNAL_H 24 | #define XAIE_LITE_IO_INTERNAL_H 25 | 26 | #ifdef XAIE_FEATURE_LITE 27 | 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | #include "xaie_helper.h" 31 | 32 | 33 | #if XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIE 34 | #include "xaie_lite_aie.h" 35 | #include "xaie_lite_shim_aie.h" 36 | #elif XAIE_DEV_SINGLE_GEN == XAIE_DEV_GEN_AIEML 37 | #include "xaie_lite_aieml.h" 38 | #include "xaie_lite_shim_aie.h" 39 | #else 40 | #include 41 | #endif 42 | 43 | #define XAIE_ERROR_MSG(...) \ 44 | "[AIE ERROR] %s():%d: %s", __func__, __LINE__, __VA_ARGS__ 45 | 46 | #ifdef XAIE_ENABLE_INPUT_CHECK 47 | #ifdef _ENABLE_IPU_LX6_ 48 | #include 49 | #endif 50 | #define XAIE_ERROR_RETURN(ERRCON, RET, ...) { \ 51 | if (ERRCON) { \ 52 | printf(__VA_ARGS__); \ 53 | return (RET); \ 54 | } \ 55 | } 56 | #else 57 | #define XAIE_ERROR_RETURN(...) 58 | #endif 59 | 60 | /************************** Function Definitions *****************************/ 61 | /*****************************************************************************/ 62 | /** 63 | * 64 | * This is API returns the tile type for a given device instance and tile 65 | * location. 66 | * 67 | * @param DevInst: Device Instance 68 | * @param Loc: Location of the AIE tile. 69 | * @return TileType (AIETILE/MEMTILE/SHIMPL/SHIMNOC on success and MAX on 70 | * error) 71 | * 72 | * @note Internal only. 73 | * 74 | ******************************************************************************/ 75 | static inline u8 _XAie_LGetTTypefromLoc(XAie_DevInst *DevInst, XAie_LocType Loc) 76 | { 77 | XAIE_ERROR_RETURN((Loc.Col >= XAIE_NUM_COLS), XAIEGBL_TILE_TYPE_MAX, 78 | XAIE_ERROR_MSG("Invalid column: %d\n", Loc.Col)); 79 | 80 | if(Loc.Row == 0U) { 81 | return _XAie_LGetShimTTypefromLoc(DevInst, Loc); 82 | } else if(Loc.Row >= XAIE_MEM_TILE_ROW_START && 83 | (Loc.Row < (XAIE_MEM_TILE_ROW_START + 84 | XAIE_MEM_TILE_NUM_ROWS))) { 85 | return XAIEGBL_TILE_TYPE_MEMTILE; 86 | } else if (Loc.Row >= XAIE_AIE_TILE_ROW_START && 87 | (Loc.Row < (XAIE_AIE_TILE_ROW_START + 88 | XAIE_AIE_TILE_NUM_ROWS))) { 89 | return XAIEGBL_TILE_TYPE_AIETILE; 90 | } 91 | 92 | XAIE_ERROR_RETURN(1U, XAIEGBL_TILE_TYPE_MAX, 93 | XAIE_ERROR_MSG("Cannot find Tile Type\n")); 94 | 95 | return XAIEGBL_TILE_TYPE_MAX; 96 | } 97 | 98 | /** 99 | * 100 | * This API checks if an AI engine tile is in use. 101 | * 102 | * @param DevInst: Device Instance. 103 | * @param Loc: Tile location. 104 | * 105 | * @return XAIE_ENABLE if a tile is in use, otherwise XAIE_DISABLE. 106 | * 107 | * @note Internal only. 108 | * 109 | ******************************************************************************/ 110 | static inline u8 _XAie_LPmIsTileRequested(XAie_DevInst *DevInst, 111 | XAie_LocType Loc) 112 | { 113 | u8 TileType; 114 | TileType = _XAie_LGetTTypefromLoc(DevInst, Loc); 115 | 116 | if (TileType == XAIEGBL_TILE_TYPE_MAX) { 117 | return XAIE_DISABLE; 118 | } 119 | if (TileType == XAIEGBL_TILE_TYPE_SHIMNOC || TileType == XAIEGBL_TILE_TYPE_SHIMPL) { 120 | return XAIE_ENABLE; 121 | } 122 | 123 | return _XAie_LPmIsArrayTileRequested(DevInst, Loc); 124 | } 125 | 126 | #endif /* XAIE_FEATURE_LITE */ 127 | 128 | #endif /* XAIE_LITE_H */ 129 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_shim_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_shim_aie.h 10 | * @{ 11 | * 12 | * This header file defines a lite shim interface for AIE type devices. 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who     Date     Changes
 18 | * ----- ------  -------- -----------------------------------------------------
 19 | * 1.0   Nishad   06/23/2022  Initial creation
 20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_LITE_SHIM_AIE_H 24 | #define XAIE_LITE_SHIM_AIE_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_lite_hwcfg.h" 28 | #include "xaiegbl_defs.h" 29 | #include "xaiegbl.h" 30 | 31 | /************************** Constant Definitions *****************************/ 32 | #define UPDT_NEXT_NOC_TILE_LOC(Loc) \ 33 | ({ \ 34 | if ((Loc).Col <= 1) \ 35 | (Loc).Col = 2; \ 36 | else if ((((Loc).Col + 1) % 4) / 2) \ 37 | (Loc).Col += 1; \ 38 | else if ((((Loc).Col + 2) % 4) / 2) \ 39 | (Loc).Col += 2; \ 40 | else \ 41 | (Loc).Col += 3; \ 42 | }) 43 | 44 | #define IS_TILE_NOC_TILE(Loc) \ 45 | ({ \ 46 | ((Loc).Col % 4) / 2 ? 1: 0; \ 47 | }) 48 | 49 | #define XAIE_MAX_NUM_NOC_INTR 3U 50 | 51 | /************************** Function Prototypes *****************************/ 52 | /*****************************************************************************/ 53 | /** 54 | * 55 | * This is API returns the shim tile type for a given device instance and tile 56 | * location. 57 | * 58 | * @param DevInst: Device Instance 59 | * @param Loc: Location of the AIE tile. 60 | * 61 | * @return TileType SHIMPL/SHIMNOC on success. 62 | * 63 | * @note Internal only. 64 | * 65 | ******************************************************************************/ 66 | static inline u8 _XAie_LGetShimTTypefromLoc(XAie_DevInst *DevInst, 67 | XAie_LocType Loc) 68 | { 69 | u8 ColType = (DevInst->StartCol + Loc.Col) % 4U; 70 | 71 | if((ColType == 0U) || (ColType == 1U)) 72 | return XAIEGBL_TILE_TYPE_SHIMPL; 73 | 74 | return XAIEGBL_TILE_TYPE_SHIMNOC; 75 | } 76 | 77 | /*****************************************************************************/ 78 | /** 79 | * 80 | * This API maps L2 status bit to its L1 switch. 81 | * 82 | * @param DevInst: Device Instance. 83 | * @param Index: Set bit position in L2 status. 84 | * @param L2Col: Location of L2 column. 85 | * @param L1Col: Mapped value of L1 column. 86 | * @param Switch: Broadcast switch. 87 | * 88 | * @return None. 89 | * 90 | * @note Internal only. 91 | * 92 | ******************************************************************************/ 93 | static inline void _XAie_MapL2MaskToL1(XAie_DevInst *DevInst, u32 Index, 94 | u8 L2Col, u8 *L1Col, XAie_BroadcastSw *Switch) 95 | { 96 | if (L2Col + 3 >= DevInst->NumCols) { 97 | *L1Col = L2Col + (Index % 6) / 2; 98 | *Switch = (Index % 6) % 2; 99 | } else if ((L2Col) % 2 == 0) { 100 | /* Set bit position could be 0 - 5 */ 101 | *L1Col = L2Col - (2 - (Index % 6) / 2); 102 | *Switch = (Index % 6) % 2; 103 | } else { 104 | /* Set bit position could be 0 - 1 */ 105 | *L1Col = L2Col; 106 | *Switch= Index; 107 | } 108 | } 109 | 110 | /*****************************************************************************/ 111 | /** 112 | * 113 | * This is API returns the range of columns programmed to generate interrupt on 114 | * the given IRQ channel. 115 | * 116 | * @param IrqId: L2 IRQ ID. 117 | * 118 | * @return Range of columns. 119 | * 120 | * @note Internal only. 121 | * 122 | ******************************************************************************/ 123 | static inline XAie_Range _XAie_MapIrqIdToCols(u8 IrqId) 124 | { 125 | XAie_Range _MapIrqIdToCols[] = { 126 | {.Start = 0, .Num = 16}, 127 | {.Start = 16, .Num = 16}, 128 | {.Start = 32, .Num = 18}, 129 | }; 130 | 131 | return _MapIrqIdToCols[IrqId]; 132 | } 133 | 134 | /*****************************************************************************/ 135 | /** 136 | * 137 | * This is API returns the L2 IRQ ID for a given column. 138 | * 139 | * @param DevInst: Device Instance 140 | * @param Loc: Location of the AIE tile. 141 | * 142 | * @return L2 IRQ ID. 143 | * 144 | * @note Internal only. 145 | * 146 | ******************************************************************************/ 147 | static inline u8 _XAie_MapColToIrqId(XAie_DevInst *DevInst, XAie_LocType Loc) 148 | { 149 | u8 IrqId, AbsCol; 150 | 151 | AbsCol = DevInst->StartCol + Loc.Col; 152 | IrqId = AbsCol / (XAIE_NUM_COLS / XAIE_MAX_NUM_NOC_INTR) + 153 | XAIE_NUM_NOC_INTR_OFFSET; 154 | 155 | if (AbsCol + 3 > XAIE_NUM_COLS) { 156 | IrqId -= 1; 157 | } 158 | 159 | return IrqId; 160 | } 161 | 162 | #endif /* end of protection macro */ 163 | /** @} */ 164 | -------------------------------------------------------------------------------- /driver/src/lite/xaie_lite_util.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 AMD. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_lite_util.h 10 | * @{ 11 | * 12 | * This header file defines lightweight utility helpers for the AIE lite 13 | * driver. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who       Date        Changes
19 | * ----- --------  --------    ------------------------------------------------
20 | * 1.0  dsteger    07/10/2022  Initial creation
21 | * 1.1  avasi	  11/16/2022  Additions for Status Dump of Core Tile, Mem Tile
22 | *                             and Shim Tile registers.
23 | *
24 | * 25 | ******************************************************************************/ 26 | 27 | #ifndef XAIE_LITE_UTIL_H 28 | #define XAIE_LITE_UTIL_H 29 | 30 | #include "xaiegbl_defs.h" 31 | #include "xaie_lite_hwcfg.h" 32 | 33 | #if defined(XAIE_FEATURE_LITE_UTIL) 34 | /************************** Macro Definitions *****************************/ 35 | // To update these version numbers based on the changes made. 36 | #define VERSION_MAJOR 1 37 | #define VERSION_MINOR 1 38 | 39 | #define XAie_LGetColRangeBufSize(NumCols) { \ 40 | sizeof(XAie_Col_Status) * NumCols \ 41 | } 42 | 43 | /************************** Variable Definitions *****************************/ 44 | 45 | /* Data structure to capture the dma status */ 46 | typedef struct { 47 | u32 S2MMStatus; 48 | u32 MM2SStatus; 49 | } XAie_DmaStatus; 50 | 51 | /* Data structure to capture the core tile status */ 52 | typedef struct { 53 | XAie_DmaStatus dma[XAIE_TILE_DMA_NUM_CH]; 54 | u32 EventStatus[XAIE_CORE_TILE_NUM_EVENT_STATUS_REGS]; 55 | u32 CoreStatus; 56 | u32 ProgramCounter; 57 | u32 StackPtr; 58 | u32 LinkReg; 59 | u8 LockValue[XAIE_TILE_NUM_LOCKS]; 60 | } XAie_Core_Tile_Status; 61 | 62 | /* Data structure to capture the mem tile status */ 63 | #if (XAIE_DEV_SINGLE_GEN != XAIE_DEV_GEN_AIE) 64 | typedef struct { 65 | XAie_DmaStatus dma[XAIE_MEM_TILE_DMA_NUM_CH]; 66 | u32 EventStatus[XAIE_MEM_TILE_NUM_EVENT_STATUS_REGS]; 67 | u8 LockValue[XAIE_MEM_TILE_NUM_LOCKS]; 68 | } XAie_Mem_Tile_Status; 69 | #endif 70 | 71 | /* Data structure to capture the shim tile status */ 72 | typedef struct { 73 | XAie_DmaStatus dma[XAIE_SHIM_DMA_NUM_CH]; 74 | u32 EventStatus[XAIE_SHIM_TILE_NUM_EVENT_STATUS_REGS]; 75 | u8 LockValue[XAIE_SHIM_NUM_LOCKS]; 76 | } XAie_Shim_Tile_Status; 77 | 78 | /* Data structure to capture column status */ 79 | typedef struct { 80 | XAie_Core_Tile_Status CoreTile[XAIE_AIE_TILE_NUM_ROWS]; 81 | #if (XAIE_DEV_SINGLE_GEN != XAIE_DEV_GEN_AIE) 82 | XAie_Mem_Tile_Status MemTile[XAIE_MEM_TILE_NUM_ROWS]; 83 | #endif 84 | XAie_Shim_Tile_Status ShimTile[XAIE_SHIM_NUM_ROWS]; 85 | } XAie_Col_Status; 86 | 87 | /************************** Function Prototypes *****************************/ 88 | #endif /* XAIE_FEATURE_LITE_UTIL */ 89 | 90 | #endif /* end of protection macro */ 91 | 92 | /** @} */ 93 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   03/17/2020  Initial creation
20 | * 1.1   Tejus   03/23/2020  Include xaiegbl header file
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_H 25 | #define XAIELOCKS_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaiegbl.h" 29 | #include "xaiegbl_defs.h" 30 | /**************************** Type Definitions *******************************/ 31 | /************************** Function Prototypes *****************************/ 32 | AieRC XAie_LockAcquire(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 33 | u32 TimeOut); 34 | AieRC XAie_LockRelease(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 35 | u32 TimeOut); 36 | AieRC XAie_LockSetValue(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | XAie_Lock Lock); 38 | AieRC XAie_LockGetValue(XAie_DevInst *DevInst, XAie_LocType Loc, XAie_Lock Lock, 39 | u32 *LockValue); 40 | #endif /* end of protection macro */ 41 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks_aie.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for AIE locks. This header file is 13 | * not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/17/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_AIE_H 25 | #define XAIELOCKS_AIE_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_locks.h" 28 | #include "xaiegbl_defs.h" 29 | #include "xaie_helper.h" 30 | 31 | /************************** Constant Definitions *****************************/ 32 | 33 | /************************** Function Prototypes *****************************/ 34 | AieRC _XAie_LockAcquire(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 35 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 36 | AieRC _XAie_LockRelease(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 37 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 38 | AieRC _XAie_LockSetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 39 | XAie_LocType Loc, XAie_Lock Lock); 40 | AieRC _XAie_LockGetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 41 | XAie_LocType Loc, XAie_Lock Lock, u32 *LockVal); 42 | 43 | #endif 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/src/locks/xaie_locks_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_locks_aieml.h 10 | * @{ 11 | * 12 | * This file contains function prototypes for AIEML locks. This header file is 13 | * not exposed to the user. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Tejus   03/17/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIELOCKS_AIEML_H 25 | #define XAIELOCKS_AIEML_H 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_locks.h" 28 | #include "xaiegbl_defs.h" 29 | #include "xaie_helper.h" 30 | 31 | /************************** Constant Definitions *****************************/ 32 | 33 | /************************** Function Prototypes *****************************/ 34 | AieRC _XAieMl_LockAcquire(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 35 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 36 | AieRC _XAieMl_LockRelease(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 37 | XAie_LocType Loc, XAie_Lock Lock, u32 TimeOut); 38 | AieRC _XAieMl_LockSetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 39 | XAie_LocType Loc, XAie_Lock Lock); 40 | AieRC _XAieMl_LockGetValue(XAie_DevInst *DevInst, const XAie_LockMod *LockMod, 41 | XAie_LocType Loc, XAie_Lock Lock, u32 *LockVal); 42 | 43 | #endif 44 | /** @} */ 45 | -------------------------------------------------------------------------------- /driver/src/memory/xaie_mem.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_mem.h 10 | * @{ 11 | * 12 | * Header file for data memory implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Nishad  07/30/2020  Add API to read and write block of data from tile
22 | *			    data memory.
23 | *
24 | * 25 | ******************************************************************************/ 26 | #ifndef XAIEMEM_H 27 | #define XAIEMEM_H 28 | 29 | /***************************** Include Files *********************************/ 30 | #include "xaiegbl.h" 31 | 32 | /***************************** Macro Definitions *****************************/ 33 | #define XAIE_MEM_WORD_ALIGN_SHIFT 2U 34 | #define XAIE_MEM_WORD_ALIGN_MASK ((1U << XAIE_MEM_WORD_ALIGN_SHIFT) - 1U) 35 | #define XAIE_MEM_WORD_ALIGN_SIZE (1U << XAIE_MEM_WORD_ALIGN_SHIFT) 36 | #define XAIE_MEM_WORD_ROUND_UP(Addr) (((Addr) + XAIE_MEM_WORD_ALIGN_MASK) & \ 37 | ~XAIE_MEM_WORD_ALIGN_MASK) 38 | #define XAIE_MEM_WORD_ROUND_DOWN(Addr) ((Addr) & (~XAIE_MEM_WORD_ALIGN_MASK)) 39 | 40 | /************************** Function Prototypes *****************************/ 41 | AieRC XAie_DataMemWrWord(XAie_DevInst *DevInst, XAie_LocType Loc, 42 | u32 Addr, u32 Data); 43 | AieRC XAie_DataMemRdWord(XAie_DevInst *DevInst, XAie_LocType Loc, 44 | u32 Addr, u32 *Data); 45 | AieRC XAie_DataMemBlockWrite(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 46 | const void *Src, u32 Size); 47 | AieRC XAie_SharedDataMemBlockWrite(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | u32 Addr, const void *Src, u32 Size); 49 | AieRC XAie_SharedDataMemBlockRead(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 50 | void *Dst, u32 Size); 51 | AieRC XAie_DataMemBlockRead(XAie_DevInst *DevInst, XAie_LocType Loc, u32 Addr, 52 | void *Dst, u32 Size); 53 | 54 | #endif /* end of protection macro */ 55 | 56 | /** @} */ 57 | -------------------------------------------------------------------------------- /driver/src/npi/xaie_npi.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_npi.h 10 | * @{ 11 | * 12 | * This file contains the data structures and routines for AI engine NPI access 13 | * operations for. 14 | * 15 | ******************************************************************************/ 16 | #ifndef XAIE_NPI_H 17 | #define XAIE_NPI_H 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | #include "xaiegbl_regdef.h" 21 | 22 | /************************** Constant Definitions *****************************/ 23 | 24 | #ifndef XAIE_NPI_BASEADDR 25 | #define XAIE_NPI_BASEADDR 0xF70A0000U 26 | #endif 27 | 28 | #define XAIE_NPI_TIMEOUT_US 0x00000005U 29 | 30 | /* 31 | * Typedef for structure for NPI protected registers access 32 | */ 33 | typedef struct XAie_NpiProtRegReq { 34 | u32 StartCol; 35 | u32 NumCols; 36 | u8 Enable; 37 | } XAie_NpiProtRegReq; 38 | 39 | /* 40 | * This typedef contains the attributes for AI engine NPI registers 41 | */ 42 | typedef struct XAie_NpiMod { 43 | u32 PcsrMaskOff; 44 | u32 PcsrCntrOff; 45 | u32 PcsrLockOff; 46 | u32 ProtRegOff; 47 | u32 PcsrUnlockCode; 48 | XAie_RegFldAttr ShimReset; 49 | XAie_RegFldAttr ProtRegEnable; 50 | XAie_RegFldAttr ProtRegFirstCol; 51 | XAie_RegFldAttr ProtRegLastCol; 52 | AieRC (*SetProtectedRegField)(XAie_DevInst *DevInst, 53 | XAie_NpiProtRegReq *Req, u32 *RegVal); 54 | } XAie_NpiMod; 55 | 56 | typedef void (*NpiWrite32Func)(void *IOInst, u32 RegOff, u32 RegVal); 57 | 58 | /************************** Function Prototypes *****************************/ 59 | AieRC _XAie_NpiSetShimReset(XAie_DevInst *DevInst, u8 RstEnable); 60 | AieRC _XAie_NpiSetProtectedRegEnable(XAie_DevInst *DevInst, 61 | XAie_NpiProtRegReq *Req); 62 | 63 | #endif /* End of protection macro */ 64 | 65 | /** @} */ 66 | -------------------------------------------------------------------------------- /driver/src/npi/xaie_npi_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_npi_aie.c 10 | * @{ 11 | * 12 | * This file contains routines for operations for accessing AI engine 13 | * specific NPI. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_npi.h" 20 | #include "xaiegbl.h" 21 | 22 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 23 | 24 | /************************** Constant Definitions *****************************/ 25 | #define XAIE_NPI_PCSR_MASK 0x00000000U 26 | #define XAIE_NPI_PCSR_MASK_SHIM_RESET_MSK 0x08000000U 27 | #define XAIE_NPI_PCSR_MASK_SHIM_RESET_LSB 27U 28 | 29 | #define XAIE_NPI_PCSR_CONTROL 0X00000004U 30 | #define XAIE_NPI_PCSR_CONTROL_SHIM_RESET_MSK 0x08000000U 31 | #define XAIE_NPI_PCSR_CONTROL_SHIM_RESET_LSB 27U 32 | 33 | #define XAIE_NPI_PCSR_LOCK 0X0000000CU 34 | #define XAIE_NPI_PCSR_UNLOCK_CODE 0xF9E8D7C6U 35 | 36 | #define XAIE_NPI_SPARE_REG 0x00000200U 37 | #define XAIE_NPI_PROT_REG_EN_MSK 0x00000001U 38 | #define XAIE_NPI_PROT_REG_EN_LSB 0U 39 | 40 | #define XAIE_NPI_IRQ_REG 0x00000030U 41 | 42 | /****************************** Type Definitions *****************************/ 43 | 44 | /************************** Variable Definitions *****************************/ 45 | static AieRC _XAie_NpiSetProtectedRegField(XAie_DevInst *DevInst, 46 | XAie_NpiProtRegReq *Req, u32 *RegVal); 47 | 48 | XAie_NpiMod _XAieNpiMod = 49 | { 50 | .PcsrMaskOff = XAIE_NPI_PCSR_MASK, 51 | .PcsrCntrOff = XAIE_NPI_PCSR_CONTROL, 52 | .PcsrLockOff = XAIE_NPI_PCSR_LOCK, 53 | .ProtRegOff = XAIE_NPI_SPARE_REG, 54 | .PcsrUnlockCode = XAIE_NPI_PCSR_UNLOCK_CODE, 55 | .ShimReset = {XAIE_NPI_PCSR_CONTROL_SHIM_RESET_LSB, XAIE_NPI_PCSR_CONTROL_SHIM_RESET_MSK}, 56 | .ProtRegEnable = {XAIE_NPI_PROT_REG_EN_LSB, XAIE_NPI_PROT_REG_EN_MSK}, 57 | .ProtRegFirstCol = {0, 0}, 58 | .ProtRegLastCol = {0, 0}, 59 | .SetProtectedRegField = _XAie_NpiSetProtectedRegField, 60 | }; 61 | 62 | /************************** Function Definitions *****************************/ 63 | /*****************************************************************************/ 64 | /** 65 | * 66 | * This is function to setup the protected register configuration value. 67 | * 68 | * @param DevInst : AI engine partition device pointer 69 | * @param Req: Protect Register Request 70 | * @param RegVal: pointer to return calculated register value 71 | * 72 | * @return XAIE_OK 73 | * 74 | * @note For AIE, the StartCol and NumCols in the @Req will not be 75 | * used as it is not supported in hardware. 76 | * 77 | *******************************************************************************/ 78 | static AieRC _XAie_NpiSetProtectedRegField(XAie_DevInst *DevInst, 79 | XAie_NpiProtRegReq *Req, u32 *RegVal) 80 | { 81 | (void) DevInst; 82 | 83 | *RegVal = XAie_SetField(Req->Enable, _XAieNpiMod.ProtRegEnable.Lsb, 84 | _XAieNpiMod.ProtRegEnable.Mask); 85 | 86 | return XAIE_OK; 87 | } 88 | 89 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 90 | /** @} */ 91 | -------------------------------------------------------------------------------- /driver/src/npi/xaie_npi_aieml.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_npi_aieml.c 10 | * @{ 11 | * 12 | * This file contains routines for operations for accessing AI engine v2 13 | * specific NPI. 14 | * 15 | ******************************************************************************/ 16 | /***************************** Include Files *********************************/ 17 | #include "xaie_feature_config.h" 18 | #include "xaie_helper.h" 19 | #include "xaie_npi.h" 20 | #include "xaiegbl.h" 21 | 22 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 23 | 24 | /************************** Constant Definitions *****************************/ 25 | #define XAIEML_NPI_PCSR_UNLOCK_CODE 0xF9E8D7C6U 26 | #define XAIEML_NPI_PCSR_MASK 0x00000000U 27 | #define XAIEML_NPI_PCSR_MASK_SHIM_RESET_MSK 0x08000000U 28 | #define XAIEML_NPI_PCSR_MASK_SHIM_RESET_LSB 27U 29 | 30 | #define XAIEML_NPI_PCSR_CONTROL 0X00000004U 31 | #define XAIEML_NPI_PCSR_CONTROL_SHIM_RESET_MSK 0x08000000U 32 | #define XAIEML_NPI_PCSR_CONTROL_SHIM_RESET_LSB 27U 33 | 34 | #define XAIEML_NPI_PCSR_LOCK 0X0000000CU 35 | #define XAIEML_NPI_PCSR_LOCK_STATE_UNLOCK_CODE 0xF9E8D7C6U 36 | 37 | #define XAIEML_NPI_PROT_REG_CNTR 0x00000200U 38 | #define XAIEML_NPI_PROT_REG_CNTR_EN_MSK 0x00000001U 39 | #define XAIEML_NPI_PROT_REG_CNTR_EN_LSB 0U 40 | #define XAIEML_NPI_PROT_REG_CNTR_FIRSTCOL_MSK 0x000000FEU 41 | #define XAIEML_NPI_PROT_REG_CNTR_FIRSTCOL_LSB 1U 42 | #define XAIEML_NPI_PROT_REG_CNTR_LASTCOL_MSK 0x00007F00U 43 | #define XAIEML_NPI_PROT_REG_CNTR_LASTCOL_LSB 8U 44 | 45 | #define XAIEML_COL_MASK (0x7FU << 25) 46 | /****************************** Type Definitions *****************************/ 47 | 48 | /************************** Variable Definitions *****************************/ 49 | static AieRC _XAieMl_NpiSetProtectedRegField(XAie_DevInst *DevInst, 50 | XAie_NpiProtRegReq *Req, u32 *RegVal); 51 | 52 | const XAie_NpiMod _XAieMlNpiMod = 53 | { 54 | .PcsrMaskOff = XAIEML_NPI_PCSR_MASK, 55 | .PcsrCntrOff = XAIEML_NPI_PCSR_CONTROL, 56 | .PcsrLockOff = XAIEML_NPI_PCSR_LOCK, 57 | .ProtRegOff = XAIEML_NPI_PROT_REG_CNTR, 58 | .PcsrUnlockCode = XAIEML_NPI_PCSR_UNLOCK_CODE, 59 | .ShimReset = {XAIEML_NPI_PCSR_CONTROL_SHIM_RESET_LSB, XAIEML_NPI_PCSR_CONTROL_SHIM_RESET_MSK}, 60 | .ProtRegEnable = {XAIEML_NPI_PROT_REG_CNTR_EN_LSB, XAIEML_NPI_PROT_REG_CNTR_EN_MSK}, 61 | .ProtRegFirstCol = {XAIEML_NPI_PROT_REG_CNTR_FIRSTCOL_LSB, XAIEML_NPI_PROT_REG_CNTR_FIRSTCOL_MSK}, 62 | .ProtRegLastCol = {XAIEML_NPI_PROT_REG_CNTR_LASTCOL_LSB, XAIEML_NPI_PROT_REG_CNTR_LASTCOL_MSK}, 63 | .SetProtectedRegField = _XAieMl_NpiSetProtectedRegField, 64 | }; 65 | 66 | /************************** Function Definitions *****************************/ 67 | /*****************************************************************************/ 68 | /** 69 | * 70 | * This is function to setup the protected register configuration value. 71 | * 72 | * @param DevInst : AI engine partition device pointer 73 | * @param Req: Protect Register Request 74 | * @param RegVal: pointer to return calculated register value 75 | * 76 | * @return XAIE_OK for success, and negative value for failure 77 | * 78 | * @note None 79 | * 80 | *******************************************************************************/ 81 | static AieRC _XAieMl_NpiSetProtectedRegField(XAie_DevInst *DevInst, 82 | XAie_NpiProtRegReq *Req, u32 *RegVal) 83 | { 84 | u32 CFirst, CLast, NumCols; 85 | 86 | if ((Req->StartCol + Req->NumCols) > DevInst->NumCols || 87 | (Req->StartCol != 0U && Req->NumCols == 0U)) { 88 | XAIE_ERROR("Invalid columns (%u, %u) for protected regs.\n", 89 | Req->StartCol, Req->NumCols); 90 | return XAIE_INVALID_ARGS; 91 | } 92 | 93 | *RegVal = XAie_SetField(Req->Enable, _XAieMlNpiMod.ProtRegEnable.Lsb, 94 | _XAieMlNpiMod.ProtRegEnable.Mask); 95 | 96 | NumCols = Req->NumCols; 97 | if (NumCols == 0U) { 98 | /* It is for the whole partition instance */ 99 | NumCols = DevInst->NumCols; 100 | CFirst = 0; 101 | } else { 102 | CFirst = Req->StartCol; 103 | } 104 | 105 | CLast = CFirst + NumCols - 1U; 106 | 107 | *RegVal |= XAie_SetField(CFirst, _XAieMlNpiMod.ProtRegFirstCol.Lsb, 108 | _XAieMlNpiMod.ProtRegFirstCol.Mask); 109 | *RegVal |= XAie_SetField(CLast, _XAieMlNpiMod.ProtRegLastCol.Lsb, 110 | _XAieMlNpiMod.ProtRegLastCol.Mask); 111 | 112 | return XAIE_OK; 113 | } 114 | 115 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 116 | /** @} */ 117 | -------------------------------------------------------------------------------- /driver/src/perfcnt/xaie_perfcnt.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_perfcnt.h 10 | * @{ 11 | * 12 | * Header file for performance counter implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date     Changes
18 | * ----- ------   -------- -----------------------------------------------------
19 | * 1.0   Dishita  11/21/2019  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIEPERFCNT_H 24 | #define XAIEPERFCNT_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | #include "xaie_helper.h" 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | #include "xaiegbl_defs.h" 32 | 33 | /************************** Function Prototypes *****************************/ 34 | AieRC XAie_PerfCounterGet(XAie_DevInst *DevInst, XAie_LocType Loc, 35 | XAie_ModuleType Module, u8 Counter, u32 *CounterVal); 36 | AieRC XAie_PerfCounterGetOffset(XAie_DevInst *DevInst, XAie_LocType Loc, 37 | XAie_ModuleType Module, u8 Counter, u64 *Offset); 38 | AieRC XAie_PerfCounterControlSet(XAie_DevInst *DevInst, XAie_LocType Loc, 39 | XAie_ModuleType Module, u8 Counter, XAie_Events StartEvent, 40 | XAie_Events StopEvent); 41 | AieRC XAie_PerfCounterResetControlSet(XAie_DevInst *DevInst, XAie_LocType Loc, 42 | XAie_ModuleType Module, u8 Counter, XAie_Events ResetEvent); 43 | AieRC XAie_PerfCounterSet(XAie_DevInst *DevInst, XAie_LocType Loc, 44 | XAie_ModuleType Module, u8 Counter, u32 CounterVal); 45 | AieRC XAie_PerfCounterEventValueSet(XAie_DevInst *DevInst, XAie_LocType Loc, 46 | XAie_ModuleType Module, u8 Counter, u32 EventVal); 47 | AieRC XAie_PerfCounterControlReset(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | XAie_ModuleType Module, u8 Counter); 49 | AieRC XAie_PerfCounterResetControlReset(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | XAie_ModuleType Module, u8 Counter); 51 | AieRC XAie_PerfCounterReset(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | XAie_ModuleType Module, u8 Counter); 53 | AieRC XAie_PerfCounterEventValueReset(XAie_DevInst *DevInst, XAie_LocType Loc, 54 | XAie_ModuleType Module, u8 Counter); 55 | AieRC XAie_PerfCounterGetControlConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | XAie_ModuleType Module, u8 Counter, XAie_Events *StartEvent, 57 | XAie_Events *StopEvent, XAie_Events *ResetEvent); 58 | AieRC XAie_PerfCounterGetEventBase(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | XAie_ModuleType Module, XAie_Events *Event); 60 | #endif /* end of protection macro */ 61 | -------------------------------------------------------------------------------- /driver/src/pl/xaie_plif.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_plif.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   10/28/2019  Initial creation
20 | * 1.1   Tejus   03/16/2020  Implementation of apis for Mux/Demux configuration
21 | * 1.2   Tejus   03/20/2020  Remove range apis
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIEPLIF_H 26 | #define XAIEPLIF_H 27 | 28 | /***************************** Include Files *********************************/ 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | /**************************** Type Definitions *******************************/ 32 | /* 33 | * This enum captures the AIE-PL interface bit widths available in the hardware. 34 | */ 35 | typedef enum { 36 | PLIF_WIDTH_32 = 32, 37 | PLIF_WIDTH_64 = 64, 38 | PLIF_WIDTH_128 = 128 39 | } XAie_PlIfWidth; 40 | 41 | /************************** Function Prototypes *****************************/ 42 | AieRC XAie_PlIfBliBypassEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | u8 PortNum); 44 | AieRC XAie_PlIfBliBypassDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 45 | u8 PortNum); 46 | AieRC XAie_PlIfDownSzrEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 47 | u8 PortNum); 48 | AieRC XAie_PlIfDownSzrDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 49 | u8 PortNum); 50 | AieRC XAie_PlToAieIntfEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | u8 PortNum, XAie_PlIfWidth Width); 52 | AieRC XAie_PlToAieIntfDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 53 | u8 PortNum, XAie_PlIfWidth Width); 54 | AieRC XAie_AieToPlIntfEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 55 | u8 PortNum, XAie_PlIfWidth Width); 56 | AieRC XAie_AieToPlIntfDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 57 | u8 PortNum, XAie_PlIfWidth Width); 58 | AieRC XAie_EnableShimDmaToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | u8 PortNum); 60 | AieRC XAie_EnableAieToShimDmaStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 61 | u8 PortNum); 62 | AieRC XAie_EnableNoCToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | u8 PortNum); 64 | AieRC XAie_EnableAieToNoCStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 65 | u8 PortNum); 66 | AieRC XAie_EnablePlToAieStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 67 | u8 PortNum); 68 | AieRC XAie_EnableAieToPlStrmPort(XAie_DevInst *DevInst, XAie_LocType Loc, 69 | u8 PortNum); 70 | #endif /* end of protection macro */ 71 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_clock.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_clock.h 10 | * @{ 11 | * 12 | * Header file for timer implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date        Changes
18 | * ----- ------   --------    --------------------------------------------------
19 | * 1.0   Dishita  06/26/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_CLOCK_H 24 | #define XAIE_CLOCK_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Enum *********************************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | AieRC XAie_PmRequestTiles(XAie_DevInst *DevInst, XAie_LocType *Loc, 33 | u32 NumTiles); 34 | AieRC XAie_PmSetColumnClk(XAie_DevInst *DevInst, u32 StartCol, 35 | u32 NumCols, u8 Enable); 36 | #endif /* end of protection macro */ 37 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_ecc.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ecc.h 10 | * @{ 11 | * 12 | * Header file for ecc implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date        Changes
18 | * ----- ------   --------    --------------------------------------------------
19 | * 1.0   Dishita  08/10/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_ECC_H 24 | #define XAIE_ECC_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | 29 | /************************** Enum *********************************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | void _XAie_EccEvntResetPM(XAie_DevInst *DevInst, XAie_LocType Loc); 33 | AieRC _XAie_EccOnPM(XAie_DevInst *DevInst, XAie_LocType Loc); 34 | AieRC _XAie_EccOnDM(XAie_DevInst *DevInst, XAie_LocType Loc); 35 | #endif /* end of protection macro */ 36 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset.h 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_RESET_H 16 | #define XAIE_RESET_H 17 | 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | /**************************** Type Definitions *******************************/ 21 | /************************** Function Prototypes *****************************/ 22 | AieRC XAie_ResetPartition(XAie_DevInst *DevInst); 23 | AieRC XAie_ClearPartitionMems(XAie_DevInst *DevInst); 24 | #endif /* end of protection macro */ 25 | 26 | /** @} */ 27 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aie.c 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets for AIE 13 | * 14 | ******************************************************************************/ 15 | /***************************** Include Files *********************************/ 16 | #include "xaie_feature_config.h" 17 | #include "xaie_helper.h" 18 | #include "xaiegbl.h" 19 | 20 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 21 | 22 | /*****************************************************************************/ 23 | /***************************** Macro Definitions *****************************/ 24 | /************************** Function Definitions *****************************/ 25 | /*****************************************************************************/ 26 | /** 27 | * 28 | * This API set the SHIM tile reset 29 | * 30 | * @param DevInst: Device Instance 31 | * @param Loc: Location of AIE SHIM tile 32 | * @param RstEnable: XAIE_ENABLE to enable reset, XAIE_DISABLE to 33 | * disable reset. 34 | * 35 | * @return none 36 | * 37 | * @note It is not required to check the DevInst and the Loc tile type 38 | * as the caller function should provide the correct value. 39 | * 40 | ******************************************************************************/ 41 | static void _XAie_RstSetShimReset(XAie_DevInst *DevInst, XAie_LocType Loc, 42 | u8 RstEnable) 43 | { 44 | u8 TileType; 45 | u32 FldVal; 46 | u64 RegAddr; 47 | const XAie_PlIfMod *PlIfMod; 48 | const XAie_ShimRstMod *ShimTileRst; 49 | 50 | TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 51 | PlIfMod = DevInst->DevProp.DevMod[TileType].PlIfMod; 52 | ShimTileRst = PlIfMod->ShimTileRst; 53 | 54 | RegAddr = ShimTileRst->RegOff + 55 | XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col); 56 | FldVal = XAie_SetField(RstEnable, 57 | ShimTileRst->RstCntr.Lsb, 58 | ShimTileRst->RstCntr.Mask); 59 | 60 | XAie_Write32(DevInst, RegAddr, FldVal); 61 | } 62 | 63 | /*****************************************************************************/ 64 | /** 65 | * 66 | * This API reset the SHIM for the specified columns 67 | * 68 | * @param DevInst: Device Instance 69 | * @param StartCol: Start column 70 | * @param NumCols: Number of columns 71 | * 72 | * @return XAIE_OK 73 | * 74 | * @note It is not required to check the DevInst as the caller function 75 | * should provide the correct value. Also it will not check the 76 | * @StartCol nor the @NumCols, the caller function should do the 77 | * validation and provide the correct values. This function does 78 | * the following steps: 79 | * * Set reset bit for every SHIM 80 | * * Assert SHIM reset 81 | * * Deassert SHIM reset 82 | * * Unset reset bit for every SHIM 83 | * 84 | ******************************************************************************/ 85 | AieRC _XAie_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols) 86 | { 87 | for (u8 C = StartCol; C < (StartCol + NumCols); C++) { 88 | XAie_LocType Loc = XAie_TileLoc(C, 0); 89 | 90 | _XAie_RstSetShimReset(DevInst, Loc, XAIE_ENABLE); 91 | } 92 | 93 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 94 | (void *)(uintptr_t)XAIE_ENABLE); 95 | 96 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 97 | (void *)(uintptr_t)XAIE_DISABLE); 98 | 99 | for (u8 C = StartCol; C < (StartCol + NumCols); C++) { 100 | XAie_LocType Loc = XAie_TileLoc(C, 0); 101 | 102 | _XAie_RstSetShimReset(DevInst, Loc, XAIE_DISABLE); 103 | } 104 | 105 | return XAIE_OK; 106 | } 107 | 108 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 109 | /** @} */ 110 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aie.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aie.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE reset controls. This header file is not 13 | * exposed to the user. 14 | * 15 | ******************************************************************************/ 16 | #ifndef XAIE_RESET_AIE_H 17 | #define XAIE_RESET_AIE_H 18 | /***************************** Include Files *********************************/ 19 | #include "xaiegbl.h" 20 | 21 | /************************** Function Prototypes *****************************/ 22 | AieRC _XAie_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols); 23 | AieRC _XAie_PmSetPartitionClock(XAie_DevInst *DevInst, u8 Enable); 24 | u8 _XAie_PmIsTileRequested(XAie_DevInst *DevInst, XAie_LocType Loc); 25 | 26 | #endif /* XAIE_RESET_AIE_H */ 27 | /** @} */ 28 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aieml.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aieml.c 10 | * @{ 11 | * 12 | * This file contains routines for AI engine resets for AIEML 13 | * 14 | ******************************************************************************/ 15 | /***************************** Include Files *********************************/ 16 | #include "xaie_feature_config.h" 17 | #include "xaie_helper.h" 18 | #include "xaie_npi.h" 19 | #include "xaiegbl.h" 20 | 21 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 22 | 23 | /*****************************************************************************/ 24 | /***************************** Macro Definitions *****************************/ 25 | /************************** Function Definitions *****************************/ 26 | /*****************************************************************************/ 27 | /** 28 | * 29 | * This API reset the SHIM for the specified columns 30 | * 31 | * @param DevInst: Device Instance 32 | * @param StartCol: Start column 33 | * @param NumCols: Number of columns 34 | * 35 | * @return XAIE_OK for success, and error value for failure 36 | * 37 | * @note It is not required to check the DevInst as the caller function 38 | * should provide the correct value. As we only supports full 39 | * partition SHIMs reset, if the @StartCol and @NumCols are not 40 | * aligned with the full partition, it will return error. 41 | * This function does the following steps: 42 | * * Enable protect registers 43 | * * Assert SHIM reset 44 | * * Deassert SHIM reset 45 | * * Disable protect registers 46 | * 47 | ******************************************************************************/ 48 | AieRC _XAieMl_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols) 49 | { 50 | XAie_NpiProtRegReq ProtRegReq; 51 | 52 | if(StartCol > 0U || NumCols != DevInst->NumCols) { 53 | XAIE_ERROR("AIE shim reset, not supported columns.\n"); 54 | return XAIE_INVALID_ARGS; 55 | } 56 | 57 | ProtRegReq.StartCol = StartCol; 58 | ProtRegReq.NumCols = NumCols; 59 | ProtRegReq.Enable = XAIE_ENABLE; 60 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_SET_PROTREG, (void *)&ProtRegReq); 61 | 62 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 63 | (void *)(uintptr_t)XAIE_ENABLE); 64 | 65 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_ASSERT_SHIMRST, 66 | (void *)(uintptr_t)XAIE_DISABLE); 67 | 68 | ProtRegReq.Enable = XAIE_DISABLE; 69 | XAie_RunOp(DevInst, XAIE_BACKEND_OP_SET_PROTREG, (void *)&ProtRegReq); 70 | 71 | return XAIE_OK; 72 | } 73 | 74 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 75 | /** @} */ 76 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_reset_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_reset_aieml.h 10 | * @{ 11 | * 12 | * This file contains routines for AIEML reset controls. This header file is not 13 | * exposed to the user. 14 | * 15 | ******************************************************************************/ 16 | 17 | #ifndef XAIE_RESET_AIEML_H 18 | #define XAIE_RESET_AIEML_H 19 | 20 | /***************************** Include Files *********************************/ 21 | #include "xaiegbl.h" 22 | 23 | /************************** Function Prototypes *****************************/ 24 | AieRC _XAieMl_RstShims(XAie_DevInst *DevInst, u32 StartCol, u32 NumCols); 25 | 26 | #endif /* XAIE_RESET_AIEML_H */ 27 | /** @} */ 28 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_tilectrl.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_tilectrl.c 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile controls. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Wendy   05/27/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | /***************************** Include Files *********************************/ 24 | 25 | #include "xaie_feature_config.h" 26 | #include "xaie_helper.h" 27 | #include "xaie_tilectrl.h" 28 | #include "xaiegbl_defs.h" 29 | 30 | #ifdef XAIE_FEATURE_PRIVILEGED_ENABLE 31 | 32 | /************************** Constant Definitions *****************************/ 33 | /************************** Function Definitions *****************************/ 34 | /*****************************************************************************/ 35 | /** 36 | * 37 | * This API sets isolation of a tile 38 | * 39 | * @param DevInst: Device Instance 40 | * @param Loc: tile location 41 | * @param Dir: directions to block, the direction input as: 42 | * XAIE_ISOLATE_EAST_MASK, 43 | * XAIE_ISOLATE_NORTH_MASK, 44 | * XAIE_ISOLATE_WEST_MASK, 45 | * XAIE_ISOLATE_SOUTH_MASK, 46 | * or "OR" operation of more than one of the above masks, 47 | * or XAIE_ISOLATE_ALL_MASK to block all directions. 48 | * 49 | * @return XAIE_OK on success, error code on failure 50 | * 51 | * @note It is not required to check the DevInst as the caller function 52 | * should provide the correct value. As this is internal function, 53 | * it will not verify the Dir input. 54 | * This is INTERNAL function. 55 | * 56 | ******************************************************************************/ 57 | AieRC _XAie_TileCtrlSetIsolation(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | u8 Dir) 59 | { 60 | const XAie_TileCtrlMod *TCtrlMod; 61 | u32 FldVal, Mask; 62 | u64 RegAddr; 63 | u8 TileType; 64 | 65 | TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc); 66 | if(TileType == XAIEGBL_TILE_TYPE_MAX) { 67 | XAIE_ERROR("Failed to set tile isolation, invalid tile type\n"); 68 | return XAIE_ERR; 69 | } 70 | 71 | TCtrlMod = DevInst->DevProp.DevMod[TileType].TileCtrlMod; 72 | RegAddr = TCtrlMod->TileCtrlRegOff + 73 | XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col); 74 | Mask = TCtrlMod->IsolateEast.Mask | TCtrlMod->IsolateNorth.Mask | 75 | TCtrlMod->IsolateWest.Mask | TCtrlMod->IsolateSouth.Mask; 76 | /* 77 | * This is internal function, the Dir input masks matches the register 78 | * isolation mask, there is no need to calculate each direction bit. 79 | */ 80 | FldVal = XAie_SetField(Dir, 81 | TCtrlMod->IsolateSouth.Lsb, Mask); 82 | 83 | return XAie_Write32(DevInst, RegAddr, FldVal); 84 | } 85 | 86 | #endif /* XAIE_FEATURE_PRIVILEGED_ENABLE */ 87 | /** @} */ 88 | -------------------------------------------------------------------------------- /driver/src/pm/xaie_tilectrl.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_tilectrl.h 10 | * @{ 11 | * 12 | * This file contains routines for AIE tile control. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Wendy   05/27/2021  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_TILECTRL_H 24 | #define XAIE_TILECTRL_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaiegbl.h" 28 | /**************************** Type Definitions *******************************/ 29 | /***************************** Macro Definitions *****************************/ 30 | 31 | #define XAIE_ISOLATE_EAST_MASK (1U << 3) 32 | #define XAIE_ISOLATE_NORTH_MASK (1U << 2) 33 | #define XAIE_ISOLATE_WEST_MASK (1U << 1) 34 | #define XAIE_ISOLATE_SOUTH_MASK (1U << 0) 35 | #define XAIE_ISOLATE_ALL_MASK ((1U << 4) - 1) 36 | 37 | /************************** Function Prototypes *****************************/ 38 | AieRC _XAie_TileCtrlSetIsolation(XAie_DevInst *DevInst, XAie_LocType Loc, 39 | u8 Dir); 40 | 41 | #endif /* end of protection macro */ 42 | -------------------------------------------------------------------------------- /driver/src/routing/xaie_routing_internal.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2024 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_routing.h 10 | * @{ 11 | * 12 | * This file contains the internal high level APIs for AI-Engines. 13 | * 14 | ******************************************************************************/ 15 | #ifndef XAIE_ROUTING_INTERNAL_H 16 | #define XAIE_ROUTING_INTERNAL_H 17 | 18 | /***************************** Include Files *********************************/ 19 | #include 20 | #include 21 | #include 22 | #include 23 | 24 | //internal functions 25 | static void _XAie_printBitfield(int value, int bits); 26 | static const char* _XAie_StrmSwPortTypeToString(StrmSwPortType type); 27 | static void _XAie_drawRoute(XAie_RoutingInstance *routingInstance, XAie_LocType *path, int pathLength, 28 | XAie_LocType source, XAie_LocType destination); 29 | static void _XAie_enqueue(Queue* queue, XAie_LocType item); 30 | static XAie_LocType _XAie_dequeue(Queue* queue); 31 | static bool _XAie_isShimTile(XAie_RoutingInstance* RoutingInstance, XAie_LocType tile); 32 | static AieRC _XAie_updatePortAvailabilityForShimDmaToAie(XAie_RoutingInstance *routingInstance, XAie_LocType tile, int stream, bool SetOrUnset /*True for set*/); 33 | static AieRC _XAie_updatePortAvailabilityForAieToShimDma(XAie_RoutingInstance *routingInstance, XAie_LocType tile, int stream, bool SetOrUnset /*True for set*/); 34 | static void _XAie_updatePortAvailabilityForStrmConn(XAie_RoutingInstance *routingInstance, XAie_LocType tile, StrmSwPortType portSource, int sourceStream, StrmSwPortType portDest, int destStream); 35 | static int _XAie_findFirstMatchingStream(XAie_RoutingInstance* RoutingInstance, XAie_LocType tile, 36 | StrmSwPortType direction, bool isEndTile); 37 | static void _XAie_resetBDAvailability(XAie_RoutingInstance *routingInstance, XAie_LocType tile, u8 bdID); 38 | static int _XAie_findAvailableBufferID(XAie_RoutingInstance *routingInstance, XAie_LocType tile); 39 | static bool _XAie_isAdjTileValidForCurrTile(XAie_RoutingInstance* RoutingInstance, XAie_RouteConstraints* RouteConstraints, 40 | XAie_LocType currentTile, XAie_LocType adjTile, StrmSwPortType direction, bool** visited); 41 | static AieRC _XAie_performRoutingOnPath(XAie_RoutingInstance *routingInstance, XAie_LocType source, XAie_LocType destination, XAie_LocType *path, int pathLength); 42 | static AieRC _XAie_programBufferDescriptors(XAie_RoutingInstance *routingInstance, XAie_LocType source, void* SourceObject, u32 data_size, void* DestinationObject, 43 | XAie_LocType destination, XAie_BDs* BDs); 44 | static bool _XAie_findShortestPath(XAie_RoutingInstance *routingInstance, XAie_RouteConstraints* RouteConstraints, XAie_LocType source, XAie_LocType destination, XAie_LocType *path, int *pathLength); 45 | static bool _XAie_isTileBlackListed(XAie_LocType CurrTile, XAie_RouteConstraints* RouteConstraints); 46 | static bool _XAie_isTileWhitelisted(XAie_LocType CurrTile, XAie_LocType *whitelist, u16 whitelistCount); 47 | static bool _XAie_isMemTile(XAie_RoutingInstance* RoutingInstance, XAie_LocType tile); 48 | static void _XAie_updatePortAvailabilityForStrmConnInverse(XAie_RoutingInstance *routingInstance, XAie_LocType tile, 49 | StrmSwPortType portSource, int sourceStream, StrmSwPortType portDest, int destStream); 50 | static void _XAie_freeXAieProgrammedRoutes(XAie_ProgrammedRoutes* headRoute); 51 | static void _XAie_FreeRouteFromRoutesDB(XAie_ProgrammedRoutes** head, XAie_LocType source, XAie_LocType destination); 52 | static void _XAie_FreeRoutingSteps(XAie_RoutingStep* step); 53 | static XAie_RoutingPath* _XAie_findRouteInRouteDB(XAie_ProgrammedRoutes* routesDB, XAie_LocType source, XAie_LocType destination); 54 | static void _XAie_addRouteInRoutesDB(XAie_ProgrammedRoutes** head, XAie_RoutingPath* routePath); 55 | 56 | #endif /* End of protection macro */ 57 | 58 | /** @} */ 59 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss.h 10 | * @{ 11 | * 12 | * Header file for stream switch implementations. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Tejus   09/24/2019  Initial creation
20 | * 1.1   Tejus   03/20/2020  Remove range apis
21 | * 1.2   Tejus   03/21/2020  Add stream switch packet switch mode apis
22 | *
23 | * 24 | ******************************************************************************/ 25 | #ifndef XAIESS_H 26 | #define XAIESS_H 27 | 28 | /***************************** Include Files *********************************/ 29 | #include "xaiegbl.h" 30 | #include "xaiegbl_defs.h" 31 | #include "xaiegbl_defs.h" 32 | #include "xaie_helper.h" 33 | 34 | /**************************** Type Definitions *******************************/ 35 | /* Typedef to capture Packet drop header */ 36 | typedef enum { 37 | XAIE_SS_PKT_DONOT_DROP_HEADER, 38 | XAIE_SS_PKT_DROP_HEADER 39 | } XAie_StrmSwPktHeader; 40 | 41 | /************************** Function Prototypes *****************************/ 42 | AieRC XAie_StrmConnCctEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | StrmSwPortType Slave, u8 SlvPortNum, StrmSwPortType Master, 44 | u8 MstrPortNum); 45 | 46 | AieRC XAie_StrmConnCctDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 47 | StrmSwPortType Slave, u8 SlvPortNum, StrmSwPortType Master, 48 | u8 MstrPortNum); 49 | 50 | AieRC XAie_SStrmConnCctDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 51 | StrmSwPortType Slave, u8 SlvPortNum, StrmSwPortType Master, 52 | u8 MstrPortNum); 53 | 54 | AieRC XAie_StrmPktSwMstrPortEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 55 | StrmSwPortType Master, u8 MstrPortNum, 56 | XAie_StrmSwPktHeader DropHeader, u8 Arbitor, u8 MSelEn); 57 | 58 | AieRC XAie_StrmPktSwMstrPortDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 59 | StrmSwPortType Master, u8 MstrPortNum); 60 | 61 | AieRC XAie_StrmPktSwSlavePortEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 62 | StrmSwPortType Slave, u8 SlvPortNum); 63 | 64 | AieRC XAie_StrmPktSwSlavePortDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 65 | StrmSwPortType Slave, u8 SlvPortNum); 66 | 67 | AieRC XAie_StrmPktSwSlaveSlotEnable(XAie_DevInst *DevInst, XAie_LocType Loc, 68 | StrmSwPortType Slave, u8 SlvPortNum, u8 SlotNum, 69 | XAie_Packet Pkt, u8 Mask, u8 MSel, u8 Arbitor); 70 | 71 | AieRC XAie_StrmPktSwSlaveSlotDisable(XAie_DevInst *DevInst, XAie_LocType Loc, 72 | StrmSwPortType Slave, u8 SlvPortNum, u8 SlotNum); 73 | AieRC XAie_StrmSwLogicalToPhysicalPort(XAie_DevInst *DevInst, XAie_LocType Loc, 74 | XAie_StrmPortIntf Port, StrmSwPortType PortType, u8 PortNum, 75 | u8 *PhyPortId); 76 | AieRC XAie_StrmSwPhysicalToLogicalPort(XAie_DevInst *DevInst, XAie_LocType Loc, 77 | XAie_StrmPortIntf Port, u8 PhyPortId, StrmSwPortType *PortType, 78 | u8 *PortNum); 79 | AieRC XAie_StrmSwDeterministicMergeConfig(XAie_DevInst *DevInst, 80 | XAie_LocType Loc, u8 Arbitor, StrmSwPortType Slave, u8 PortNum, 81 | u8 PktCount, u8 Position); 82 | AieRC XAie_StrmSwDeterministicMergeEnable(XAie_DevInst *DevInst, 83 | XAie_LocType Loc, u8 Arbitor); 84 | AieRC XAie_StrmSwDeterministicMergeDisable(XAie_DevInst *DevInst, 85 | XAie_LocType Loc, u8 Arbitor); 86 | 87 | #endif /* end of protection macro */ 88 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aie.c 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who         Date        Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Siddharth   12/09/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #include "xaie_feature_config.h" 24 | #include "xaie_helper.h" 25 | 26 | #ifdef XAIE_FEATURE_SS_ENABLE 27 | /************************** Constant Definitions *****************************/ 28 | /************************** Function Definitions *****************************/ 29 | /*****************************************************************************/ 30 | /** 31 | * 32 | * This api is used to verify if a stream switch connection is possible with 33 | * the provided slave and master ports. Within AIE, a full crossbar exists. 34 | * So, every valid slave port and valid master port can connect. 35 | * 36 | * @param Slave: The type of the slave port. 37 | * @param SlvPortNum: The number of the slave port. 38 | * @param Master: The type of the master port. 39 | * @param MstrPortNum: The number of the master port. 40 | * 41 | * @return XAIE_OK if a stream switch connection is possible. 42 | * 43 | * @note Internal API for AIE. This API shouldn't be called directly. 44 | * It is invoked using a function pointer within the Stream 45 | * Module data structure. 46 | * 47 | *****************************************************************************/ 48 | AieRC _XAie_StrmSwCheckPortValidity(StrmSwPortType Slave, u8 SlvPortNum, 49 | StrmSwPortType Master, u8 MstrPortNum) 50 | { 51 | (void)Slave; 52 | (void)SlvPortNum; 53 | (void)Master; 54 | (void)MstrPortNum; 55 | return XAIE_OK; 56 | } 57 | 58 | #endif /* XAIE_FEATURE_SS_ENABLE */ 59 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie.h: -------------------------------------------------------------------------------- 1 | 2 | /****************************************************************************** 3 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_ss_aie.h 11 | * @{ 12 | * 13 | * This file contains internal api implementations for AIE stream switch. 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who         Date        Changes
19 | * ----- ---------   ----------  -----------------------------------------------
20 | * 1.0   Siddharth   12/09/2020  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_SS_AIE_H 25 | #define XAIE_SS_AIE_H 26 | 27 | /***************************** Include Files *********************************/ 28 | #include "xaie_helper.h" 29 | 30 | /************************** Constant Definitions *****************************/ 31 | 32 | /************************** Function Prototypes ******************************/ 33 | 34 | AieRC _XAie_StrmSwCheckPortValidity(StrmSwPortType Slave, u8 SlvPortNum, 35 | StrmSwPortType Master, u8 MstrPortNum); 36 | 37 | #endif /* XAIE_SS_AIE_H */ 38 | /** @} */ 39 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aie2ps.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aie2ps.h 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who	 Date	Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Sankarji   06/15/2023  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_SS_AIE2PS_H 24 | #define XAIE_SS_AIE2PS_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_helper.h" 28 | 29 | /************************** Constant Definitions *****************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | 33 | AieRC _XAie2PS_AieTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 34 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 35 | AieRC _XAie2PS_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 36 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 37 | AieRC _XAie2PS_ShimTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 38 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 39 | 40 | #endif /* XAIE_SS_AIE2PS_H */ 41 | /** @} */ 42 | -------------------------------------------------------------------------------- /driver/src/stream_switch/xaie_ss_aieml.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_ss_aieml.h 10 | * @{ 11 | * 12 | * This file contains internal api implementations for AIE stream switch. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who         Date        Changes
18 | * ----- ---------   ----------  -----------------------------------------------
19 | * 1.0   Siddharth   12/09/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_SS_AIEML_H 24 | #define XAIE_SS_AIEML_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_helper.h" 28 | 29 | /************************** Constant Definitions *****************************/ 30 | 31 | /************************** Function Prototypes *****************************/ 32 | 33 | AieRC _XAieMl_AieTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 34 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 35 | AieRC _XAieMl_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 36 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 37 | AieRC _XAieMl_ShimTile_StrmSwCheckPortValidity(StrmSwPortType Slave, 38 | u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum); 39 | 40 | #endif /* XAIE_SS_AIEML_H */ 41 | /** @} */ 42 | -------------------------------------------------------------------------------- /driver/src/timer/xaie_timer.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_timer.h 10 | * @{ 11 | * 12 | * Header file for timer implementation. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who      Date     Changes
18 | * ----- ------   -------- -----------------------------------------------------
19 | * 1.0   Dishita  04/05/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIETIMER_H 24 | #define XAIETIMER_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | #include "xaiegbl.h" 29 | 30 | /************************** Enum *********************************************/ 31 | 32 | /************************** Function Prototypes *****************************/ 33 | AieRC XAie_SetTimerTrigEventVal(XAie_DevInst *DevInst, XAie_LocType Loc, 34 | XAie_ModuleType Module, u32 LowEventValue, u32 HighEventValue); 35 | AieRC XAie_ResetTimer(XAie_DevInst *DevInst, XAie_LocType Loc, 36 | XAie_ModuleType Module); 37 | AieRC XAie_SetTimerResetEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 38 | XAie_ModuleType Module, XAie_Events Event, 39 | XAie_Reset Reset); 40 | AieRC XAie_ReadTimer(XAie_DevInst *DevInst, XAie_LocType Loc, 41 | XAie_ModuleType Module, u64 *TimerVal); 42 | AieRC XAie_WaitCycles(XAie_DevInst *DevInst, XAie_LocType Loc, 43 | XAie_ModuleType Module, u64 CycleCnt); 44 | AieRC XAie_SyncTimerWithTwoBcstChannel(XAie_DevInst *DevInst, u8 BcastChannelId1, 45 | u8 BcastChannelId2); 46 | AieRC XAie_SyncTimer(XAie_DevInst *DevInst, u8 BcastChannelId); 47 | 48 | #endif /* end of protection macro */ 49 | -------------------------------------------------------------------------------- /driver/src/trace/xaie_trace.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2020 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file xaie_trace.h 10 | * @{ 11 | * 12 | * Header file for AIE trace module. 13 | * 14 | * 
15 | * MODIFICATION HISTORY:
16 | *
17 | * Ver   Who     Date     Changes
18 | * ----- ------  -------- -----------------------------------------------------
19 | * 1.0   Nishad  06/16/2020  Initial creation
20 | *
21 | * 22 | ******************************************************************************/ 23 | #ifndef XAIE_TRACE_H 24 | #define XAIE_TRACE_H 25 | 26 | /***************************** Include Files *********************************/ 27 | #include "xaie_events.h" 28 | 29 | /**************************** Type Definitions *******************************/ 30 | /* This enum captures various states of a trace module */ 31 | typedef enum { 32 | XAIE_TRACE_IDLE, 33 | XAIE_TRACE_RUNNING, 34 | XAIE_TRACE_OVERRUN, 35 | } XAie_TraceState; 36 | 37 | /* This enum captures various trace modes */ 38 | typedef enum { 39 | XAIE_TRACE_EVENT_TIME, 40 | XAIE_TRACE_EVENT_PC, 41 | XAIE_TRACE_INST_EXEC, 42 | } XAie_TraceMode; 43 | 44 | /************************** Function Prototypes *****************************/ 45 | AieRC XAie_TraceEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 46 | XAie_ModuleType Module, XAie_Events Event, u8 SlotId); 47 | AieRC XAie_TraceStartEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 48 | XAie_ModuleType Module, XAie_Events StartEvent); 49 | AieRC XAie_TraceStopEvent(XAie_DevInst *DevInst, XAie_LocType Loc, 50 | XAie_ModuleType Module, XAie_Events StopEvent); 51 | AieRC XAie_TracePktConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 52 | XAie_ModuleType Module, XAie_Packet Pkt); 53 | AieRC XAie_TraceModeConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 54 | XAie_ModuleType Module, XAie_TraceMode Mode); 55 | AieRC XAie_TraceGetState(XAie_DevInst *DevInst, XAie_LocType Loc, 56 | XAie_ModuleType Module, XAie_TraceState *State); 57 | AieRC XAie_TraceGetMode(XAie_DevInst *DevInst, XAie_LocType Loc, 58 | XAie_ModuleType Module, XAie_TraceMode *Mode); 59 | AieRC XAie_TraceControlConfig(XAie_DevInst *DevInst, XAie_LocType Loc, 60 | XAie_ModuleType Module, XAie_Events StartEvent, 61 | XAie_Events StopEvent, XAie_TraceMode Mode); 62 | AieRC XAie_TraceControlConfigReset(XAie_DevInst *DevInst, XAie_LocType Loc, 63 | XAie_ModuleType Module); 64 | AieRC XAie_TracePktConfigReset(XAie_DevInst *DevInst, XAie_LocType Loc, 65 | XAie_ModuleType Module); 66 | AieRC XAie_TraceEventList(XAie_DevInst *DevInst, XAie_LocType Loc, 67 | XAie_ModuleType Module, XAie_Events *Events, u8 *SlotId, 68 | u8 NumEvents); 69 | AieRC XAie_TraceEventReset(XAie_DevInst *DevInst, XAie_LocType Loc, 70 | XAie_ModuleType Module, u8 SlotId); 71 | 72 | #endif /* end of protection macro */ 73 | -------------------------------------------------------------------------------- /driver/src/util/xaie_util_events.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 Xilinx, Inc. All rights reserved. 3 | * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. * 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_util_events.h 11 | * @{ 12 | * 13 | * Header to include function prototypes for AIE utilities 14 | * 15 | * 
16 | * MODIFICATION HISTORY:
17 | *
18 | * Ver   Who     Date     Changes
19 | * ----- ------  -------- -----------------------------------------------------
20 | * 1.0   Gregory 03/31/2022  Initial creation
21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_UTIL_EVENTS_H 25 | #define XAIE_UTIL_EVENTS_H 26 | 27 | #include "xaie_feature_config.h" 28 | #ifdef XAIE_FEATURE_UTIL_ENABLE 29 | 30 | /***************************** Include Files *********************************/ 31 | #include "xaie_events.h" 32 | 33 | /**************************** Function Prototypes *******************************/ 34 | const char* XAie_EventGetString(XAie_Events Event); 35 | #endif /* XAIE_FEATURE_UTIL_ENABLE */ 36 | 37 | #endif /* end of protection macro */ 38 | 39 | /** @} */ 40 | -------------------------------------------------------------------------------- /driver/src/util/xaie_util_status.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2022 AMD. All rights reserved. 3 | * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All Rights Reserved. * 4 | * SPDX-License-Identifier: MIT 5 | ******************************************************************************/ 6 | 7 | 8 | /*****************************************************************************/ 9 | /** 10 | * @file xaie_util_status.h 11 | * @{ 12 | * 13 | * Header to include function prototypes for AIE status utilities 14 | * 15 | * 
 16 | * MODIFICATION HISTORY:
 17 | *
 18 | * Ver   Who     Date     Changes
 19 | * ----- ------  -------- -----------------------------------------------------
 20 | * 1.0   dsteger 07/25/2022  Initial creation
 21 | *
22 | * 23 | ******************************************************************************/ 24 | #ifndef XAIE_UTIL_STATUS_H 25 | #define XAIE_UTIL_STATUS_H 26 | 27 | /***************************** Include Files *********************************/ 28 | 29 | #include "xaie_feature_config.h" 30 | #include "xaiegbl_defs.h" 31 | #include "xaiegbl.h" 32 | 33 | #ifdef XAIE_FEATURE_UTIL_STATUS_ENABLE 34 | 35 | /**************************** Variable Definitions *******************************/ 36 | 37 | enum { 38 | XAIE_CORE_STATUS_ENABLE_BIT = 0U, 39 | XAIE_CORE_STATUS_RESET_BIT, 40 | XAIE_CORE_STATUS_MEM_STALL_S_BIT, 41 | XAIE_CORE_STATUS_MEM_STALL_W_BIT, 42 | XAIE_CORE_STATUS_MEM_STALL_N_BIT, 43 | XAIE_CORE_STATUS_MEM_STALL_E_BIT, 44 | XAIE_CORE_STATUS_LOCK_STALL_S_BIT, 45 | XAIE_CORE_STATUS_LOCK_STALL_W_BIT, 46 | XAIE_CORE_STATUS_LOCK_STALL_N_BIT, 47 | XAIE_CORE_STATUS_LOCK_STALL_E_BIT, 48 | XAIE_CORE_STATUS_STREAM_STALL_SS0_BIT, 49 | XAIE_CORE_STATUS_STREAM_STALL_MS0_BIT = 12, 50 | XAIE_CORE_STATUS_CASCADE_STALL_SCD_BIT = 14, 51 | XAIE_CORE_STATUS_CASCADE_STALL_MCD_BIT, 52 | XAIE_CORE_STATUS_DEBUG_HALT_BIT, 53 | XAIE_CORE_STATUS_ECC_ERROR_STALL_BIT, 54 | XAIE_CORE_STATUS_ECC_SCRUBBING_STALL_BIT, 55 | XAIE_CORE_STATUS_ERROR_HALT_BIT, 56 | XAIE_CORE_STATUS_DONE_BIT, 57 | XAIE_CORE_STATUS_PROCESSOR_BUS_STALL_BIT, 58 | XAIE_CORE_STATUS_MAX_BIT 59 | }; 60 | 61 | enum DmaStatus_S2MM_enum{ 62 | XAIE_DMA_STATUS_S2MM_STATUS = 0U, 63 | XAIE_DMA_STATUS_S2MM_STALLED_LOCK_ACK = 2U, 64 | XAIE_DMA_STATUS_S2MM_STALLED_LOCK_REL, 65 | XAIE_DMA_STATUS_S2MM_STALLED_STREAM_STARVATION, 66 | XAIE_DMA_STATUS_S2MM_STALLED_TCT_OR_COUNT_FIFO_FULL, 67 | XAIE_DMA_STATUS_S2MM_ERROR_LOCK_ACCESS_TO_UNAVAIL = 8U, // Specific only to MEM Tile 68 | XAIE_DMA_STATUS_S2MM_ERROR_DM_ACCESS_TO_UNAVAIL, // Specific only to MEM Tile 69 | XAIE_DMA_STATUS_S2MM_ERROR_BD_UNAVAIL = 10U, 70 | XAIE_DMA_STATUS_S2MM_ERROR_BD_INVALID, 71 | XAIE_DMA_STATUS_S2MM_ERROR_FOT_LENGTH, 72 | XAIE_DMA_STATUS_S2MM_ERROR_FOT_BDS_PER_TASK, 73 | XAIE_DMA_STATUS_S2MM_AXI_MM_DECODE_ERROR = 16U, 74 | XAIE_DMA_STATUS_S2MM_AXI_MM_SLAVE_ERROR = 17U, 75 | XAIE_DMA_STATUS_S2MM_TASK_QUEUE_OVERFLOW = 18U, 76 | XAIE_DMA_STATUS_S2MM_CHANNEL_RUNNING, 77 | XAIE_DMA_STATUS_S2MM_TASK_QUEUE_SIZE, 78 | XAIE_DMA_STATUS_S2MM_CURRENT_BD = 24U, 79 | XAIE_DMA_STATUS_S2MM_MAX 80 | }; 81 | 82 | enum DmaStatus_MM2S_enum{ 83 | XAIE_DMA_STATUS_MM2S_STATUS = 0U, 84 | XAIE_DMA_STATUS_MM2S_STALLED_LOCK_ACK = 2U, 85 | XAIE_DMA_STATUS_MM2S_STALLED_LOCK_REL, 86 | XAIE_DMA_STATUS_MM2S_STALLED_STREAM_BACKPRESSURE, 87 | XAIE_DMA_STATUS_MM2S_STALLED_TCT, 88 | XAIE_DMA_STATUS_MM2S_ERROR_LOCK_ACCESS_TO_UNAVAIL = 8U, // Specific only to MEM Tile 89 | XAIE_DMA_STATUS_MM2S_ERROR_DM_ACCESS_TO_UNAVAIL, // Specific only to MEM Tile 90 | XAIE_DMA_STATUS_MM2S_ERROR_BD_UNAVAIL, 91 | XAIE_DMA_STATUS_MM2S_ERROR_BD_INVALID = 11U, 92 | XAIE_DMA_STATUS_MM2S_AXI_MM_DECODE_ERROR = 16U, 93 | XAIE_DMA_STATUS_MM2S_AXI_MM_SLAVE_ERROR = 17U, 94 | XAIE_DMA_STATUS_MM2S_TASK_QUEUE_OVERFLOW = 18U, 95 | XAIE_DMA_STATUS_MM2S_CHANNEL_RUNNING, 96 | XAIE_DMA_STATUS_MM2S_TASK_QUEUE_SIZE, 97 | XAIE_DMA_STATUS_MM2S_CURRENT_BD = 24U, 98 | XAIE_DMA_STATUS_MM2S_MAX 99 | }; 100 | 101 | /**************************** Function Prototypes *******************************/ 102 | #define TRUE 1u 103 | #define FALSE 0u 104 | 105 | int XAie_CoreStatus_CSV(u32 Reg, char *Buf); 106 | int XAie_DmaS2MMStatus_CSV(u32 Reg, char *Buf, u8 ); 107 | int XAie_DmaMM2SStatus_CSV(u32 Reg, char *Buf, u8 ); 108 | 109 | #define MAX_CHAR_ARRAY_SIZE 400 110 | #endif /* XAIE_FEATURE_UTIL_STATUS_ENABLE */ 111 | 112 | #endif /* end of protection macro */ 113 | 114 | /** @} */ 115 | -------------------------------------------------------------------------------- /driver/src/xaiengine.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | #ifdef __cplusplus 34 | } 35 | #endif 36 | -------------------------------------------------------------------------------- /driver/test/stest/aiert_tests.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file aiert_tests.h 10 | * @{ 11 | * 12 | * Header file for declaring AIE-RT simulator tests (AIEML-Tests) 13 | * 14 | ******************************************************************************/ 15 | 16 | /* List of simulator test APIs 17 | * Description: Add an external reference to your test-api/s here 18 | * 19 | */ 20 | extern int test_lock(XAie_DevInst *DevInst); 21 | extern int test_aie_auto_routing(XAie_DevInst *DevInst); 22 | /* 23 | * Description: Add function pointers to the above test-api/s here 24 | */ 25 | int (*tests_aiert[])(XAie_DevInst *DevInst) = 26 | { 27 | test_lock 28 | }; 29 | 30 | /* 31 | * Description: Add the name of the test-api/s 32 | */ 33 | const char *test_names_aiert[] = 34 | { 35 | "test_lock", 36 | "test_aie_auto_routing" 37 | }; 38 | /** @} */ 39 | -------------------------------------------------------------------------------- /driver/test/stest/hw_config.h: -------------------------------------------------------------------------------- 1 | #ifndef HW_CONFIG_H 2 | #define HW_CONFIG_H 3 | 4 | #if AIE_GEN == 1 5 | 6 | #define HW_GEN XAIE_DEV_GEN_AIE 7 | #define XAIE_BASE_ADDR 0x20000000000 8 | #define XAIE_COL_SHIFT 23 9 | #define XAIE_ROW_SHIFT 18 10 | 11 | #if DEVICE == 80 /* s80 Config */ 12 | #define XAIE_NUM_ROWS 9 13 | #define XAIE_NUM_COLS 50 14 | #define XAIE_SHIM_ROW 0 15 | #define XAIE_MEM_TILE_ROW_START 0 16 | #define XAIE_MEM_TILE_NUM_ROWS 0 17 | #define XAIE_AIE_TILE_ROW_START 1 18 | #define XAIE_AIE_TILE_NUM_ROWS 8 19 | 20 | #elif DEVICE == 0 /* SystemC Config */ 21 | #define XAIE_NUM_ROWS 4 22 | #define XAIE_NUM_COLS 5 23 | #define XAIE_SHIM_ROW 0 24 | #define XAIE_MEM_TILE_ROW_START 0 25 | #define XAIE_MEM_TILE_NUM_ROWS 0 26 | #define XAIE_AIE_TILE_ROW_START 1 27 | #define XAIE_AIE_TILE_NUM_ROWS 3 28 | #endif /* DEVICE */ 29 | 30 | /* AIE_GEN = 2 by default for now. */ 31 | #elif AIE_GEN == 2 32 | 33 | #define HW_GEN XAIE_DEV_GEN_AIEML 34 | #define XAIE_BASE_ADDR 0x20000000000 35 | #define XAIE_COL_SHIFT 25 36 | #define XAIE_ROW_SHIFT 20 37 | 38 | #if DEVICE == 60 /* sv60 Config */ 39 | #define XAIE_NUM_ROWS 11 40 | #define XAIE_NUM_COLS 38 41 | #define XAIE_SHIM_ROW 0 42 | #define XAIE_MEM_TILE_ROW_START 1 43 | #define XAIE_MEM_TILE_NUM_ROWS 2 44 | #define XAIE_AIE_TILE_ROW_START 3 45 | #define XAIE_AIE_TILE_NUM_ROWS 8 46 | 47 | #elif DEVICE == 0 /* SystemC Config */ 48 | #define XAIE_NUM_ROWS 6 49 | #define XAIE_NUM_COLS 5 50 | #define XAIE_SHIM_ROW 0 51 | #define XAIE_MEM_TILE_ROW_START 1 52 | #define XAIE_MEM_TILE_NUM_ROWS 1 53 | #define XAIE_AIE_TILE_ROW_START 2 54 | #define XAIE_AIE_TILE_NUM_ROWS 4 55 | #endif /* DEVICE */ 56 | 57 | #elif AIE_GEN == 3 58 | 59 | #define HW_GEN XAIE_DEV_GEN_AIE2IPU 60 | #define XAIE_BASE_ADDR 0x20000000000 61 | #define XAIE_COL_SHIFT 25 62 | #define XAIE_ROW_SHIFT 20 63 | 64 | /* SystemC Config */ 65 | #define XAIE_NUM_ROWS 6 66 | #define XAIE_NUM_COLS 5 67 | #define XAIE_SHIM_ROW 0 68 | #define XAIE_MEM_TILE_ROW_START 1 69 | #define XAIE_MEM_TILE_NUM_ROWS 1 70 | #define XAIE_AIE_TILE_ROW_START 2 71 | #define XAIE_AIE_TILE_NUM_ROWS 4 72 | 73 | #elif AIE_GEN == 4 74 | 75 | #define HW_GEN XAIE_DEV_GEN_AIE2P 76 | #define XAIE_BASE_ADDR 0x20000000000 77 | #define XAIE_COL_SHIFT 25 78 | #define XAIE_ROW_SHIFT 20 79 | 80 | /* SystemC Config */ 81 | #define XAIE_NUM_ROWS 6 82 | #define XAIE_NUM_COLS 5 83 | #define XAIE_SHIM_ROW 0 84 | #define XAIE_MEM_TILE_ROW_START 1 85 | #define XAIE_MEM_TILE_NUM_ROWS 1 86 | #define XAIE_AIE_TILE_ROW_START 2 87 | #define XAIE_AIE_TILE_NUM_ROWS 4 88 | 89 | #elif AIE_GEN == 5 90 | 91 | #define HW_GEN XAIE_DEV_GEN_AIE2PS 92 | #define XAIE_COL_SHIFT 25 93 | #define XAIE_ROW_SHIFT 20 94 | 95 | #if DEVICE == 80 /* IPP Config */ 96 | #define XAIE_BASE_ADDR 0x22000000000 97 | #define XAIE_NUM_ROWS 7 98 | #define XAIE_NUM_COLS 4 99 | #define XAIE_SHIM_ROW 0 100 | #define XAIE_MEM_TILE_ROW_START 1 101 | #define XAIE_MEM_TILE_NUM_ROWS 2 102 | #define XAIE_AIE_TILE_ROW_START 3 103 | #define XAIE_AIE_TILE_NUM_ROWS 4 104 | 105 | #elif DEVICE == 0 /* systemc Config */ 106 | #define XAIE_BASE_ADDR 0x20000000000 107 | #define XAIE_NUM_ROWS 4 108 | #define XAIE_NUM_COLS 5 109 | #define XAIE_SHIM_ROW 0 110 | #define XAIE_MEM_TILE_ROW_START 1 111 | #define XAIE_MEM_TILE_NUM_ROWS 1 112 | #define XAIE_AIE_TILE_ROW_START 2 113 | #define XAIE_AIE_TILE_NUM_ROWS 2 114 | 115 | #endif /* DEVICE */ 116 | #endif /* AIE_GEN */ 117 | #endif /* HW_CONFIG_H */ 118 | -------------------------------------------------------------------------------- /driver/test/stest/xaie_test_lock.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2023 AMD, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | /***************************** Include Files *********************************/ 7 | #include 8 | #include 9 | 10 | /************************** Constant Definitions *****************************/ 11 | /************************** Function Definitions *****************************/ 12 | /*****************************************************************************/ 13 | /** 14 | * 15 | * This function tests AIE Locks 16 | * 17 | * @param None. 18 | * 19 | * @return 0 on success and error code on failure. 20 | * 21 | * @note None. 22 | * 23 | *******************************************************************************/ 24 | int test_lock(XAie_DevInst *DevInst) 25 | { 26 | XAie_LocType t = XAie_TileLoc(1,3); 27 | XAie_LockSetValue(DevInst, t, XAie_LockInit(5,1)); 28 | u32 var; 29 | AieRC RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,1),&var); 30 | if(RC != XAIE_OK) { 31 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 32 | return -1; 33 | } 34 | 35 | printf("after set lock value = %x\n",var); 36 | RC = XAie_LockAcquire(DevInst, t, XAie_LockInit(5, 1),0); 37 | if(RC != XAIE_OK) { 38 | printf("[stest/test_lock] XAie_LockAcquire failed.\n"); 39 | return -1; 40 | } 41 | 42 | printf("RC = 0x%x \n",RC); 43 | RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,1),&var); 44 | if(RC != XAIE_OK) { 45 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 46 | return -1; 47 | } 48 | 49 | printf("after aquire lock value = %x\n",var); 50 | //RC = XAie_LockRelease(DevInst, t, XAie_LockInit(5,1),0); 51 | //printf("-Release RC = 0x%x\n",RC); 52 | RC = XAie_LockAcquire(DevInst, t, XAie_LockInit(5,1),0); 53 | if(RC != XAIE_OK) { 54 | printf("[stest/test_lock] XAie_LockAcquire failed.\n"); 55 | return -1; 56 | } 57 | 58 | printf("after first second aquire RC = 0x%x\n",RC); 59 | RC = XAie_LockRelease(DevInst, t, XAie_LockInit(5,-1),0); 60 | if(RC != XAIE_OK) { 61 | printf("[stest/test_lock] XAie_LockRelease failed.\n"); 62 | return -1; 63 | } 64 | 65 | printf("-Release -1 RC = 0x%x\n",RC); 66 | RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,1),&var); 67 | if(RC != XAIE_OK) { 68 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 69 | return -1; 70 | } 71 | 72 | printf("after release lock value = %x\n",var); 73 | RC = XAie_LockAcquire(DevInst, t, XAie_LockInit(5,0),0); 74 | 75 | if(RC != XAIE_OK) { 76 | printf("[stest/test_lock] XAie_LockAcquire failed.\n"); 77 | return -1; 78 | } 79 | 80 | printf("after releasea aquire 0x0 RC = 0x%x\n",RC); 81 | RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,2),&var); 82 | if(RC != XAIE_OK) { 83 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 84 | return -1; 85 | } 86 | 87 | printf("after second aqc lock value = %x\n",var); 88 | 89 | 90 | RC = XAie_LockRelease(DevInst, t, XAie_LockInit(5,1),0); 91 | if(RC != XAIE_OK) { 92 | printf("[stest/test_lock] XAie_LockRelease failed.\n"); 93 | return -1; 94 | } 95 | 96 | printf("-Release 5,1 RC = 0x%x\n",RC); 97 | RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,1),&var); 98 | if(RC != XAIE_OK) { 99 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 100 | return -1; 101 | } 102 | 103 | printf("after release 5,1 get lock value = %x\n",var); 104 | 105 | RC = XAie_LockRelease(DevInst, t, XAie_LockInit(5,2),0); 106 | if(RC != XAIE_OK) { 107 | printf("[stest/test_lock] XAie_LockRelease failed.\n"); 108 | return -1; 109 | } 110 | 111 | printf("-Release 5,2 RC = 0x%x\n",RC); 112 | RC = XAie_LockGetValue(DevInst, t, XAie_LockInit(5,2),&var); 113 | if(RC != XAIE_OK) { 114 | printf("[stest/test_lock] XAie_LockGetValue failed.\n"); 115 | return -1; 116 | } 117 | 118 | printf("after second release get lock value = %x\n",var); 119 | 120 | XAie_LockSetValue(DevInst, t, XAie_LockInit(5,1)); 121 | RC = XAie_LockAcquire(DevInst, t, XAie_LockInit(5,1),0); 122 | if(RC != XAIE_OK) { 123 | printf("[stest/test_lock] XAie_LockAcquire failed.\n"); 124 | return -1; 125 | } 126 | 127 | printf("after set lock RC = 0x%x\n",RC); 128 | printf("[stest/test_lock] test_lock Passed!\n"); 129 | return 0; 130 | } 131 | -------------------------------------------------------------------------------- /driver/test/utest/aie_hw_config.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2020 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | #define XAIE_FEATURE_LITE 7 | 8 | #define XAIE_DEV_SINGLE_GEN XAIE_DEV_GEN_AIE 9 | 10 | #include "xaiengine/xaie_lite_hwcfg.h" 11 | #include "xaiengine.h" 12 | -------------------------------------------------------------------------------- /driver/test/utest/utest.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved. 3 | * SPDX-License-Identifier: MIT 4 | ******************************************************************************/ 5 | 6 | 7 | /*****************************************************************************/ 8 | /** 9 | * @file utest.c 10 | * @{ 11 | * 12 | * This file contains unit test driver for . 13 | * 14 | * 
 15 | * MODIFICATION HISTORY:
 16 | *
 17 | * Ver   Who           Date     Changes
 18 | * ----- ----------   -------- -----------------------------------------------------
 19 | * 1.0   siyuan sun   09/24/2019  Initial creation
 20 | 
 21 | *
22 | * 23 | ******************************************************************************/ 24 | 25 | 26 | #define XAIE_DEBUG 27 | 28 | #include "aie_hw_config.h" 29 | 30 | 31 | 32 | #define XAIE_RES_TILE_ROW_START 0x20 33 | #define XAIE_RES_TILE_NUM_ROWS 3 34 | /* 35 | * Example op to send ifm, ofm. 36 | */ 37 | typedef struct { 38 | u64 ifm[6]; 39 | u64 ofm[6]; 40 | u32 flags; 41 | } __attribute__((packed, aligned(4))) dpu_op_1; 42 | 43 | /* 44 | * Example op for register poll; 45 | */ 46 | typedef struct { 47 | u32 addr; 48 | u32 timeout; 49 | } __attribute__((packed, aligned(4))) dpu_op_2; 50 | 51 | 52 | int main() { 53 | 54 | /* Initialize aie driver. */ 55 | XAie_SetupConfig(ConfigPtr, XAIE_DEV_GEN_AIE, XAIE_BASE_ADDR, 56 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 57 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 58 | XAIE_RES_TILE_ROW_START, XAIE_RES_TILE_NUM_ROWS, 59 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 60 | 61 | XAie_InstDeclare(DevInst, &ConfigPtr); 62 | 63 | XAie_CfgInitialize(&DevInst, &ConfigPtr); 64 | 65 | XAie_StartTransaction(&DevInst,XAIE_TRANSACTION_DISABLE_AUTO_FLUSH); 66 | 67 | int Op1 = XAie_RequestCustomTxnOp(&DevInst); 68 | int Op2 = XAie_RequestCustomTxnOp(&DevInst); 69 | 70 | if( -1 != Op1) { 71 | 72 | dpu_op_1 dpu_op1; 73 | dpu_op1.ifm[0] = 0xDEADBEEF; 74 | dpu_op1.ofm[0] = 0xBEEFDEAD; 75 | dpu_op1.flags = 1 << 5; 76 | 77 | /*test hexdump with the same function*/ 78 | printf("UNIT TEST LOG BEGIN>>>"); 79 | BuffHexDump(&dpu_op1,sizeof(dpu_op_1)); 80 | printf("\n<<>>"); 94 | BuffHexDump(&dpu_op2,sizeof(dpu_op_2)); 95 | printf("\n<< -DCMAKE_INCLUDE_PATH= 45 | ``` 46 | 47 | After running `cmake` to configure the build, can go to the build directory to 48 | compile: 49 | ``` 50 | cd build 51 | make VERBOSE=1 52 | ``` 53 | 54 | ### Build Unit Tests 55 | We use `CppUTest` for unit testing. Use CMake option `-DWITH_TESTS=ON` to turn 56 | on building the unit testing. 57 | 58 | You can specify to use your external cpputest directory with the following 59 | option `-DWITH_TESTS=ON -DCPPUTEST_DIR=` 60 | 61 | Here is the repo for cpputest: 62 | `https://github.com/cpputest/cpputest.git` 63 | 64 | The testing executable will be in `/tests/`. 65 | It will not run the tests by default during build. If you want to run the tests 66 | in the end of the build, you can use CMake option `-DWITH_TESTS_EXEC=ON`. 67 | 68 | #### Build with Coverage Enable 69 | Add the following cmake options along with `-DWITH_TESTS=ON -DWITH_TESTS_EXEC=ON`: 70 | `-DCMAKE_BUILD_TYPE=Debug -DCODE_COVERAGE=on` to enable coverage. 71 | 72 | The generated coverage information file will be in: 73 | `/tests/utests/`. 74 | 75 | ## License 76 | Copyright (C) 2022 Xilinx, Inc. All rights reserved. 77 | SPDX-License-Identifier: MIT 78 | -------------------------------------------------------------------------------- /fal/cmake/collect.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | function (collector_create name base) 8 | set_property (GLOBAL PROPERTY "COLLECT_${name}_LIST") 9 | set_property (GLOBAL PROPERTY "COLLECT_${name}_BASE" "${base}") 10 | endfunction (collector_create) 11 | 12 | function (collector_list var name) 13 | get_property (_list GLOBAL PROPERTY "COLLECT_${name}_LIST") 14 | set (${var} "${_list}" PARENT_SCOPE) 15 | endfunction (collector_list) 16 | 17 | function (collector_base var name) 18 | get_property (_base GLOBAL PROPERTY "COLLECT_${name}_BASE") 19 | set (${var} "${_base}" PARENT_SCOPE) 20 | endfunction (collector_base) 21 | 22 | function (collect name) 23 | collector_base (_base ${name}) 24 | string(COMPARE NOTEQUAL "${_base}" "" _is_rel) 25 | set (_list) 26 | foreach (s IN LISTS ARGN) 27 | if (_is_rel) 28 | get_filename_component (s "${s}" ABSOLUTE) 29 | file (RELATIVE_PATH s "${_base}" "${s}") 30 | endif (_is_rel) 31 | list (APPEND _list "${s}") 32 | endforeach () 33 | set_property (GLOBAL APPEND PROPERTY "COLLECT_${name}_LIST" "${_list}") 34 | endfunction (collect) 35 | 36 | # Create global collectors 37 | collector_create (PROJECT_INC_DIRS "") 38 | collector_create (PROJECT_LIB_DIRS "") 39 | collector_create (PROJECT_LIB_DEPS "") 40 | 41 | # vim: expandtab:ts=2:sw=2:smartindent 42 | -------------------------------------------------------------------------------- /fal/cmake/depends.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | if (WITH_XAIEDRV_FIND) 8 | find_package (Libxaiengine REQUIRED) 9 | collect (PROJECT_INC_DIRS "${LIBXAIENGINE_INCLUDE_DIR}") 10 | collect (PROJECT_LIB_DIRS "${LIBXAIENGINE_LIB_DIR}") 11 | collect (PROJECT_LIB_DEPS "${LIBXAIENGINE_LIB}") 12 | else() 13 | collect (PROJECT_INC_DIRS "${CMAKE_BINARY_DIR}/driver-src/include") 14 | collect (PROJECT_LIB_DIRS "${CMAKE_BINARY_DIR}/driver-src/src") 15 | collect (PROJECT_LIB_DEPS "xaiengine") 16 | endif (WITH_XAIEDRV_FIND) 17 | -------------------------------------------------------------------------------- /fal/cmake/modules/FindLibxaiengine.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | # FindLibxaiengine 8 | # -------- 9 | # 10 | # Find libxaiengine 11 | # 12 | # Find the native libxaiengine includes and library this module defines 13 | # 14 | # :: 15 | # 16 | # LIBXAIENGINE_INCLUDE_DIR, where to find xaiengine.h, etc. 17 | 18 | find_path(LIBXAIENGINE_INCLUDE_DIR NAMES xaiengine.h PATHS ${CMAKE_FIND_ROOT_PATH}) 19 | find_library(LIBXAIENGINE_LIB NAMES xaiengine PATHS ${CMAKE_FIND_ROOT_PATH}) 20 | get_filename_component(LIBXAIENGINE_LIB_DIR ${LIBXAIENGINE_LIB} DIRECTORY) 21 | 22 | include (FindPackageHandleStandardArgs) 23 | FIND_PACKAGE_HANDLE_STANDARD_ARGS (LIBXAIENGINE DEFAULT_MSG LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR) 24 | 25 | mark_as_advanced (LIBXAIENGINE_LIB LIBXAIENGINE_INCLUDE_DIR LIBXAIENGINE_LIB_DIR) 26 | -------------------------------------------------------------------------------- /fal/cmake/options.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (PROJECT_VER_MAJOR 0) 8 | set (PROJECT_VER_MINOR 1) 9 | set (PROJECT_VER_PATCH 0) 10 | set (PROJECT_VER 0.1.0) 11 | 12 | if (NOT DEFINED CMAKE_BUILD_TYPE) 13 | set (CMAKE_BUILD_TYPE Debug) 14 | endif (NOT DEFINED CMAKE_BUILD_TYPE) 15 | message ("-- Build type: ${CMAKE_BUILD_TYPE}") 16 | 17 | if (NOT CMAKE_INSTALL_LIBDIR) 18 | set (CMAKE_INSTALL_LIBDIR "lib") 19 | endif (NOT CMAKE_INSTALL_LIBDIR) 20 | 21 | if (NOT CMAKE_INSTALL_BINDIR) 22 | set (CMAKE_INSTALL_BINDIR "bin") 23 | endif (NOT CMAKE_INSTALL_BINDIR) 24 | 25 | set (_host "${CMAKE_HOST_SYSTEM_NAME}/${CMAKE_HOST_SYSTEM_PROCESSOR}") 26 | message ("-- Host: ${_host}") 27 | 28 | set (_target "${CMAKE_SYSTEM_NAME}/${CMAKE_SYSTEM_PROCESSOR}") 29 | message ("-- Target: ${_target}") 30 | 31 | if (NOT DEFINED MACHINE) 32 | set (MACHINE "Generic") 33 | endif (NOT DEFINED MACHINE) 34 | message ("-- Machine: ${MACHINE}") 35 | 36 | # handle if '-' in machine name 37 | string (REPLACE "-" "_" MACHINE ${MACHINE}) 38 | 39 | if (NOT DEFINED PROJECT_SYSTEM) 40 | string (TOLOWER ${CMAKE_SYSTEM_NAME} PROJECT_SYSTEM) 41 | string (TOUPPER ${CMAKE_SYSTEM_NAME} PROJECT_SYSTEM_UPPER) 42 | endif (NOT DEFINED PROJECT_SYSTEM) 43 | 44 | string (TOLOWER ${CMAKE_SYSTEM_PROCESSOR} PROJECT_PROCESSOR) 45 | string (TOUPPER ${CMAKE_SYSTEM_PROCESSOR} PROJECT_PROCESSOR_UPPER) 46 | string (TOLOWER ${MACHINE} PROJECT_MACHINE) 47 | string (TOUPPER ${MACHINE} PROJECT_MACHINE_UPPER) 48 | 49 | option (WITH_STATIC_LIB "Build with a static library" ON) 50 | 51 | if ("${PROJECT_SYSTEM}" STREQUAL "linux") 52 | option (WITH_SHARED_LIB "Build with a shared library" ON) 53 | option (WITH_TESTS "Install test applications" ON) 54 | endif ("${PROJECT_SYSTEM}" STREQUAL "linux") 55 | 56 | if (WITH_TESTS AND (${_host} STREQUAL ${_target})) 57 | option (WITH_TESTS_EXEC "Run test applications during build" OFF) 58 | option(TEST_HARDWARE "Run tests on hardware" OFF) 59 | endif (WITH_TESTS AND (${_host} STREQUAL ${_target})) 60 | 61 | option (WITH_DOC "Build with documentation" ON) 62 | 63 | option (WITH_BUILD_XAIEDRV "Build libxaiengine" OFF) 64 | if (NOT WITH_BUILD_XAIEDRV) 65 | message ("Will not build libxaiengine, please make sure libxaiengine is in lib/include path") 66 | option (WITH_XAIEDRV_FIND "Find libxaiegnine depends" ON) 67 | else() 68 | if ("${PROJECT_SYSTEM}" STREQUAL "linux") 69 | if (NOT ${_host} STREQUAL ${_target}) 70 | option (WITH_AIEDRV_LINUX "Build with cross compile linux backend" ON) 71 | option (WITH_AIEDRV_LIBMETAL "Build with libmetal backend" OFF) 72 | if (WITH_AIEDRV_LIBMETAL) 73 | set (AIEDRV_BACKEND -D__AIEMETAL__) 74 | elseif (WITH_AIEDRV_LINUX) 75 | set (AIEDRV_BACKEND -D__AIELINUX__) 76 | endif (WITH_AIEDRV_LIBMETAL) 77 | endif(NOT ${_host} STREQUAL ${_target}) 78 | else() 79 | option (WITH_AIEDRV_BAREMETAL "Build with baremetal backend" ON) 80 | if (WITH_AIEDRV_BAREMETAL) 81 | set (AIEDRV_BACKEND -D__AIEBAREMETAL__) 82 | endif (WITH_AIEDRV_BAREMETAL) 83 | endif ("${PROJECT_SYSTEM}" STREQUAL "linux") 84 | message ("Will build libxaiengine") 85 | endif (NOT WITH_BUILD_XAIEDRV) 86 | 87 | 88 | set_property (GLOBAL PROPERTY "PROJECT_EC_FLAGS" -Wall -Wextra) 89 | if(CMAKE_BUILD_TYPE STREQUAL "coverage" OR CODE_COVERAGE) 90 | if("${CMAKE_CXX_COMPILER_ID}" MATCHES "(Apple)?[Cc]lang") 91 | message("Building with llvm Code Coverage Tools") 92 | 93 | # Warning/Error messages 94 | find_program (LLVM_COV_PATH llvm-cov) 95 | if(NOT LLVM_COV_PATH) 96 | message(FATAL_ERROR "llvm-cov not found! Aborting.") 97 | endif() 98 | 99 | # set Flags 100 | get_property(_ec_flags GLOBAL PROPERTY "PROJECT_EC_FLAGS") 101 | set_property (GLOBAL PROPERTY "PROJECT_EC_FLAGS" ${_ec_flags} -fprofile-instr-generate -fcoverage-mapping) 102 | 103 | elseif(CMAKE_COMPILER_IS_GNUCXX) 104 | message("Building with lcov Code Coverage Tools") 105 | 106 | # Warning/Error messages 107 | if(NOT (CMAKE_BUILD_TYPE STREQUAL "Debug")) 108 | message(WARNING "Code coverage results with an optimized (non-Debug) build may be misleading") 109 | endif() 110 | find_program (LCOV_PATH lcov) 111 | if(NOT LCOV_PATH) 112 | message(FATAL_ERROR "lcov not found! Aborting...") 113 | endif() 114 | 115 | get_property(_ec_flags GLOBAL PROPERTY "PROJECT_EC_FLAGS") 116 | set_property (GLOBAL PROPERTY "PROJECT_EC_FLAGS" ${_ec_flags} -fprofile-arcs -ftest-coverage) 117 | else() 118 | message(FATAL_ERROR "Code coverage requires Clang or GCC. Aborting.") 119 | endif() 120 | endif() 121 | # vim: expandtab:ts=2:sw=2:smartindent 122 | -------------------------------------------------------------------------------- /fal/cmake/platforms/cross-genric-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_NAME "Generic" CACHE STRING "") 8 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 9 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 10 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 11 | 12 | include (CMakeForceCompiler) 13 | CMAKE_FORCE_C_COMPILER ("${CROSS_PREFIX}gcc" GNU) 14 | CMAKE_FORCE_CXX_COMPILER ("${CROSS_PREFIX}g++" GNU) 15 | 16 | # vim: expandtab:ts=2:sw=2:smartindent 17 | -------------------------------------------------------------------------------- /fal/cmake/platforms/cross-linux-g++.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") 8 | set (CMAKE_C_COMPILER "${CROSS_PREFIX}gcc" CACHE STRING "") 9 | set (CMAKE_CXX_COMPILER "${CROSS_PREFIX}g++" CACHE STRING "") 10 | set (CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER CACHE STRING "") 11 | set (CMAKE_FIND_ROOT_PATH_MODE_LIBRARY NEVER CACHE STRING "") 12 | set (CMAKE_FIND_ROOT_PATH_MODE_INCLUDE NEVER CACHE STRING "") 13 | 14 | # vim: expandtab:ts=2:sw=2:smartindent 15 | -------------------------------------------------------------------------------- /fal/cmake/platforms/versal-linux.cmake: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | set (CMAKE_SYSTEM_PROCESSOR "aarch64" CACHE STRING "") 8 | set (CROSS_PREFIX "aarch64-linux-gnu-" CACHE STRING "") 9 | include (cross-linux-g++) 10 | 11 | # vim: expandtab:ts=2:sw=2:smartindent 12 | -------------------------------------------------------------------------------- /fal/data/aiefal.mdd: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | OPTION psf_version = 2.1; 8 | 9 | BEGIN driver aiefal 10 | OPTION supported_peripherals = (); 11 | OPTION copyfiles = all; 12 | OPTION VERSION = 1.7; 13 | OPTION NAME = aiefal; 14 | END driver 15 | -------------------------------------------------------------------------------- /fal/data/aiefal.yaml: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 2 | #SPDX-License-Identifier: MIT 3 | %YAML 1.2 4 | --- 5 | title: Bindings for AIE FAL Driver 6 | 7 | maintainers: 8 | - Jaydip Patel 9 | 10 | type: driver 11 | 12 | ... 13 | -------------------------------------------------------------------------------- /fal/doc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | find_package(Doxygen) 8 | if (DOXYGEN_FOUND) 9 | 10 | configure_file (Doxyfile.in Doxyfile @ONLY) 11 | 12 | add_custom_target (doc ALL 13 | ${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile 14 | WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} 15 | ) 16 | 17 | install (DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/html 18 | DESTINATION share/doc/${PROJECT_NAME}) 19 | install (FILES ${PROJECT_SOURCE_DIR}/README.md 20 | DESTINATION share/doc/${PROJECT_NAME}) 21 | install (FILES ${PROJECT_SOURCE_DIR}/license.txt 22 | DESTINATION share/doc/${PROJECT_NAME}) 23 | 24 | endif (DOXYGEN_FOUND) 25 | 26 | # vim: expandtab:ts=2:sw=2:smartindent 27 | -------------------------------------------------------------------------------- /fal/doc/aiefal-state-prereserved.txt: -------------------------------------------------------------------------------- 1 | @startuml 2 | title "Use Resource Allocated During Compilation" 3 | skinparam linetype ortho 4 | skinparam classAttributeIconSize 0 5 | [*] --> Initialized_and_Prereserved 6 | Initialized_and_Prereserved --> Reserved : reserve() 7 | Initialized_and_Prereserved --> Configured_and_Preserved : config_parameters 8 | Configured_and_Preserved -d-> Reserved_and_Configured : reserve() 9 | Reserved -u-> Reserved_and_Configured: config_parameters 10 | Reserved_and_Configured -u-> Configured_and_Preserved : free() 11 | Reserved_and_Configured -d-> Running : start() 12 | Running -u-> Reserved_and_Configured : stop() 13 | Reserved_and_Configured -l-> Configured : release() 14 | Configured_and_Preserved -l-> Configured: release() 15 | 16 | @enduml 17 | -------------------------------------------------------------------------------- /fal/doc/aiefal-state.txt: -------------------------------------------------------------------------------- 1 | @startuml 2 | title "Resource Allocated At Runtime" 3 | skinparam linetype ortho 4 | skinparam classAttributeIconSize 0 5 | [*] --> Initialized 6 | Initialized --> Reserved : reserve() 7 | Initialized --> Configured : config_parameters 8 | Reserved --> Reserved_and_Configured : config_parameters 9 | Configured --> Reserved_and_Configured : reserve() 10 | Reserved_and_Configured --> Configured : release() 11 | Reserved_and_Configured --> Running : start() 12 | Running --> Reserved_and_Configured : stop() 13 | 14 | @enduml 15 | -------------------------------------------------------------------------------- /fal/examples/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | collector_list (_list PROJECT_INC_DIRS) 8 | include_directories (${_list} ${CMAKE_CURRENT_SOURCE_DIR}) 9 | 10 | collector_list (_list PROJECT_LIB_DIRS) 11 | link_directories (${_list}) 12 | 13 | collector_list (_deps PROJECT_LIB_DEPS) 14 | 15 | get_property (_ec_flags GLOBAL PROPERTY "PROJECT_EC_FLAGS") 16 | message ("_ec_flags = ${_ec_flags}") 17 | 18 | set (_apps profile-aie) 19 | list(APPEND _apps profile-io-aie) 20 | list(APPEND _apps trace-pc-aie) 21 | 22 | foreach (_app ${_apps}) 23 | set (_src ${CMAKE_CURRENT_SOURCE_DIR}/${_app}.cpp) 24 | if (WITH_SHARED_LIB) 25 | add_executable (${_app}-share ${_src}) 26 | set_target_properties(${_app}-share PROPERTIES CXX_STANDARD 11) 27 | target_compile_options (${_app}-share PUBLIC ${_ec_flags}) 28 | target_link_libraries (${_app}-share ${_ec_flags} ${_deps}) 29 | install (TARGETS ${_app}-share RUNTIME DESTINATION bin) 30 | endif (WITH_SHARED_LIB) 31 | 32 | if (WITH_STATIC_LIB) 33 | if (${PROJECT_SYSTEM} STREQUAL "linux") 34 | add_executable (${_app}-static ${_src}) 35 | set_target_properties(${_app}-static PROPERTIES CXX_STANDARD 11) 36 | target_compile_options (${_app}-static PUBLIC ${_ec_flags}) 37 | target_link_libraries (${_app}-static ${_ec_flags} ${_deps}) 38 | install (TARGETS ${_app}-static RUNTIME DESTINATION bin) 39 | endif (${PROJECT_SYSTEM} STREQUAL "linux") 40 | endif (WITH_STATIC_LIB) 41 | endforeach (_app) 42 | -------------------------------------------------------------------------------- /fal/examples/profile-aie.cpp: -------------------------------------------------------------------------------- 1 | // (c) Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include 5 | #include 6 | 7 | #include "xaiefal/xaiefal.hpp" 8 | 9 | #define HW_GEN XAIE_DEV_GEN_AIE 10 | #define XAIE_NUM_ROWS 9 11 | #define XAIE_NUM_COLS 50 12 | #define XAIE_ADDR_ARRAY_OFF 0x800 13 | 14 | #define XAIE_BASE_ADDR 0x20000000000 15 | #define XAIE_COL_SHIFT 23 16 | #define XAIE_ROW_SHIFT 18 17 | #define XAIE_SHIM_ROW 0 18 | #define XAIE_MEM_TILE_ROW_START 0 19 | #define XAIE_MEM_TILE_NUM_ROWS 0 20 | #define XAIE_AIE_TILE_ROW_START 1 21 | #define XAIE_AIE_TILE_NUM_ROWS 8 22 | 23 | using namespace std; 24 | using namespace xaiefal; 25 | 26 | class XAieHeatMap { 27 | public: 28 | XAieHeatMap() = delete; 29 | XAieHeatMap(std::shared_ptr Dev): 30 | AieDev(Dev) {} 31 | AieRC addTiles(const std::vector &vL) { 32 | for (auto L: vL) { 33 | auto PerfCounterActive = AieDev->tile(L).core().activeCycles(); 34 | vActive.push_back(PerfCounterActive); 35 | auto PerfCounterStall = AieDev->tile(L).core().stallCycles(); 36 | vStall.push_back(PerfCounterStall); 37 | } 38 | return XAIE_OK; 39 | } 40 | AieRC reserve() { 41 | AieRC RC = XAIE_OK; 42 | for (auto R: vActive) { 43 | RC = R->reserve(); 44 | if (RC != XAIE_OK) { 45 | return RC; 46 | } 47 | } 48 | for (auto R: vStall) { 49 | RC = R->reserve(); 50 | if (RC != XAIE_OK) { 51 | return RC; 52 | } 53 | } 54 | 55 | return RC; 56 | } 57 | AieRC release() { 58 | for (auto R: vActive) { 59 | R->release(); 60 | } 61 | for (auto R: vStall) { 62 | R->release(); 63 | } 64 | return XAIE_OK; 65 | } 66 | AieRC start() { 67 | AieRC RC = XAIE_OK; 68 | for (auto R: vActive) { 69 | RC = R->start(); 70 | if (RC != XAIE_OK) { 71 | return RC; 72 | } 73 | } 74 | for (auto R: vStall) { 75 | RC = R->start(); 76 | if (RC != XAIE_OK) { 77 | return RC; 78 | } 79 | } 80 | 81 | return RC; 82 | } 83 | AieRC stop() { 84 | for (auto R: vActive) { 85 | R->stop(); 86 | } 87 | for (auto R: vStall) { 88 | R->stop(); 89 | } 90 | return XAIE_OK; 91 | } 92 | void printResult() { 93 | Logger::log(LogLevel::INFO) << " === Profile results. ==== " << std::endl; 94 | for (auto R: vActive) { 95 | uint32_t Result; 96 | 97 | if (R->isRunning()) { 98 | R->readResult(Result); 99 | Logger::log() << "\t(" << static_cast(R->loc().Col) << 100 | "," << static_cast(R->loc().Row) << "):" << 101 | "Active=" << Result << endl; 102 | } 103 | } 104 | for (auto R: vStall) { 105 | uint32_t Result; 106 | 107 | if (R->isRunning()) { 108 | R->readResult(Result); 109 | Logger::log() << "\t(" << static_cast(R->loc().Col) << 110 | "," << static_cast(R->loc().Row) << "):" << 111 | "Stall=" << Result << endl; 112 | } 113 | } 114 | } 115 | private: 116 | std::shared_ptr AieDev; 117 | std::vector> vActive; 118 | std::vector> vStall; 119 | }; 120 | 121 | int main(void) 122 | { 123 | AieRC RC; 124 | std::vector vL; 125 | std::shared_ptr AiePtr; 126 | 127 | XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 128 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 129 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 130 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 131 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 132 | 133 | XAie_InstDeclare(DevInst, &ConfigPtr); 134 | 135 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 136 | if (RC != XAIE_OK) { 137 | std::cout << "Failed to intialize AI engine partition" << std::endl; 138 | return -1; 139 | } 140 | 141 | 142 | //Request tiles 143 | u8 NumTiles = 2; 144 | XAie_LocType Loc[NumTiles]; 145 | Loc[0] = XAie_TileLoc(1, 1); 146 | Loc[1] = XAie_TileLoc(1, 2); 147 | 148 | RC = XAie_PmRequestTiles(&(DevInst), Loc, NumTiles); 149 | 150 | vL.push_back(XAie_TileLoc(1,1)); 151 | vL.push_back(XAie_TileLoc(1,2)); 152 | 153 | AiePtr = std::make_shared(&DevInst, true); 154 | XAieHeatMap HeatMap(AiePtr); 155 | HeatMap.addTiles(vL); 156 | HeatMap.reserve(); 157 | HeatMap.start(); 158 | HeatMap.printResult(); 159 | HeatMap.stop(); 160 | HeatMap.release(); 161 | 162 | return 0; 163 | } 164 | -------------------------------------------------------------------------------- /fal/src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | if(NOT ${YOCTO}) 8 | add_library(aiefal INTERFACE) 9 | 10 | include_directories(${CMAKE_BINARY_DIR}/include/xaiefal) 11 | 12 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/common DESTINATION 13 | ${CMAKE_BINARY_DIR}/include/xaiefal) 14 | 15 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/profile DESTINATION 16 | ${CMAKE_BINARY_DIR}/include/xaiefal) 17 | 18 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/rsc DESTINATION 19 | ${CMAKE_BINARY_DIR}/include/xaiefal) 20 | 21 | file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/xaiefal.hpp DESTINATION 22 | ${CMAKE_BINARY_DIR}/include/xaiefal) 23 | else() 24 | file(GLOB_RECURSE _sources *.cpp) 25 | file(GLOB_RECURSE _headers *.hpp) 26 | 27 | set (_dest_inc_dir ${CMAKE_CURRENT_BINARY_DIR}/include) 28 | 29 | foreach (hf ${_headers}) 30 | get_filename_component(f "${hf}" NAME) 31 | get_filename_component(d "${hf}" DIRECTORY) 32 | get_filename_component(d "${d}" NAME) 33 | if ("${d}" STREQUAL "src") 34 | set (d "") 35 | endif() 36 | 37 | configure_file ("./${d}/${f}" include/${PROJECT_NAME}/${d}/${f} @ONLY) 38 | install (FILES ${_dest_inc_dir}/${PROJECT_NAME}/${d}/${f} 39 | DESTINATION include RENAME ${PROJECT_NAME}/${d}/${f}) 40 | endforeach (hf) 41 | 42 | collect (PROJECT_LIB_DIRS "${CMAKE_CURRENT_BINARY_DIR}") 43 | collect (PROJECT_INC_DIRS "${CMAKE_CURRENT_BINARY_DIR}/include") 44 | 45 | endif() 46 | 47 | # vim: expandtab:ts=2:sw=2:smartindent 48 | -------------------------------------------------------------------------------- /fal/src/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2018 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | INCLUDEDIR_ROOT=../../../include 8 | INCLUDEDIR=$(INCLUDEDIR_ROOT)/xaiefal 9 | INCLUDES=$(wildcard *.hpp) $(wildcard */*.hpp) 10 | TDIRS=$(addsuffix /,$(addprefix $(INCLUDEDIR)/,$(dir $(wildcard */*.hpp)))) 11 | TINCLUDES=$(addprefix $(INCLUDEDIR)/,$(INCLUDES)) 12 | 13 | ifneq (,$(findstring Windows,$(OS))) 14 | IS_WIN=1 15 | else 16 | IS_WIN=0 17 | endif 18 | 19 | libs: print_msg_xaiefal 20 | 21 | print_msg_xaiefal: 22 | @echo "Compiling xaiefal" 23 | 24 | .PHONY: include 25 | include: xaiefal_includes 26 | 27 | xaiefal_includes: $(INCLUDEDIR) $(TDIRS) $(TINCLUDES) 28 | 29 | ifeq (0,$(IS_WIN)) 30 | $(INCLUDEDIR): 31 | mkdir $@ 32 | $(INCLUDEDIR)/%/: $(INCLUDEDIR) 33 | mkdir $@ 34 | else 35 | $(INCLUDEDIR): 36 | "mkdir" -p $(subst /,\,$@) 37 | $(INCLUDEDIR)/%/: $(INCLUDEDIR) 38 | "mkdir" -p $(subst /,\,$@) 39 | endif 40 | 41 | $(INCLUDEDIR)/%.hpp: %.hpp $(INCLUDEDIR) $(TDIRS) 42 | cp $< $@ 43 | 44 | clean: 45 | -------------------------------------------------------------------------------- /fal/src/common/xaiefal-common.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #pragma once 5 | 6 | namespace xaiefal { 7 | #define XAIE_RSC_ID_ANY (-1U) 8 | #define XAIE_RSC_TYPE_ANY (-1U) 9 | #define XAIE_MOD_ANY (-1U) 10 | #define XAIE_LOC_ANY 0xFFU 11 | } 12 | 13 | #ifdef __linux__ 14 | #define __COMPILER_SUPPORTS_LOCKS__ 15 | #endif 16 | 17 | #include 18 | #include 19 | #ifdef __COMPILER_SUPPORTS_LOCKS__ 20 | #include 21 | #endif 22 | 23 | #ifdef __COMPILER_SUPPORTS_LOCKS__ 24 | #define _XAIEFAL_MUTEX_ACQUIRE(L) const std::lock_guard lock(L) 25 | #define _XAIEFAL_MUTEX_DECLARE(L) std::mutex L 26 | #else 27 | #define _XAIEFAL_MUTEX_ACQUIRE(...) 28 | #define _XAIEFAL_MUTEX_DECLARE(...) 29 | #endif 30 | -------------------------------------------------------------------------------- /fal/src/common/xaiefal-log.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include 5 | #include 6 | 7 | #pragma once 8 | 9 | namespace xaiefal { 10 | enum class LogLevel { 11 | DEBUG, 12 | INFO, 13 | WARN, 14 | ERROR, 15 | MAX, 16 | }; 17 | 18 | class Logger 19 | { 20 | private: 21 | Logger() : Level(LogLevel::INFO) {} 22 | public: 23 | LogLevel Level; 24 | std::ofstream of; 25 | std::ofstream ofnull; 26 | 27 | ~Logger() {} 28 | 29 | void setLogLevel(LogLevel Lvl) { 30 | Level = Lvl; 31 | } 32 | 33 | LogLevel getLogLevel() { 34 | return Level; 35 | } 36 | 37 | void setLogFile(const std::string& File) { 38 | of.open(File); 39 | } 40 | 41 | Logger(const Logger&) = delete; 42 | Logger& operator=(const Logger &) = delete; 43 | Logger(Logger &&) = delete; 44 | Logger & operator=(Logger &&) = delete; 45 | static Logger &get() { 46 | static Logger logger; 47 | 48 | return logger; 49 | } 50 | static std::ostream &log(LogLevel Lvl=LogLevel::MAX) { 51 | const char* label; 52 | 53 | switch(Lvl) { 54 | case LogLevel::DEBUG: label = "XAIEFAL: DEBUG: "; break; 55 | case LogLevel::INFO: label = "XAIEFAL: INFO: "; break; 56 | case LogLevel::WARN: label = "XAIEFAL: WARN: "; break; 57 | case LogLevel::ERROR: label = "XAIEFAL: ERROR: "; break; 58 | default: label = ""; break; 59 | } 60 | 61 | if (get().Level <= Lvl) { 62 | if (get().of.rdbuf()->is_open()) { 63 | get().of << label; 64 | return get().of; 65 | } else { 66 | std::cout << label; 67 | return std::cout; 68 | } 69 | } else { 70 | return get().ofnull; 71 | } 72 | } 73 | 74 | }; 75 | } 76 | -------------------------------------------------------------------------------- /fal/src/xaiefal.hpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | -------------------------------------------------------------------------------- /fal/tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | add_subdirectory(utests) 8 | -------------------------------------------------------------------------------- /fal/tests/utests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved. 3 | # SPDX-License-Identifier: MIT 4 | # 5 | ############################################################################### 6 | 7 | if (CPPUTEST_DIR) 8 | find_path(CPPUTEST_INC_DIR NAMES "CppUTest/Utest.h" PATHS ${CPPUTEST_DIR}/include) 9 | find_library(CPPUTEST_FOUND_LIB NAMES CppUTest PATHS ${CPPUTEST_DIR}/src/CppUTest) 10 | if (NOT CPPUTEST_FOUND_LIB) 11 | message (FATAL_ERROR "No CppUtest Library is found in ${CPPUTEST_DIR}") 12 | endif (NOT CPPUTEST_FOUND_LIB) 13 | get_filename_component(CPPUTEST_LIB_DIR ${CPPUTEST_FOUND_LIB} DIRECTORY) 14 | message ("CPPUTEST_INC_DIR=${CPPUTEST_INC_DIR}") 15 | else() 16 | ExternalProject_Add(cpputest 17 | SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/cpputest" 18 | CMAKE_ARGS -DTESTS=OFF -DEXAMPLES=OFF 19 | INSTALL_COMMAND "" 20 | ) 21 | set (CPPUTEST_INC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/cpputest/include") 22 | set (CPPUTEST_LIB_DIR "${CMAKE_CURRENT_BINARY_DIR}/cpputest-prefix/src/cpputest-build/src/CppUTest") 23 | endif (CPPUTEST_DIR) 24 | 25 | get_property (_ec_flags GLOBAL PROPERTY "PROJECT_EC_FLAGS") 26 | 27 | collector_list (_list PROJECT_INC_DIRS) 28 | list (APPEND _list ${CPPUTEST_INC_DIR}) 29 | list (APPEND _list ${CMAKE_CURRENT_SOURCE_DIR}/tc) 30 | include_directories (${_list}) 31 | 32 | collector_list (_list PROJECT_LIB_DIRS) 33 | list (APPEND _list ${CPPUTEST_LIB_DIR}) 34 | link_directories (${_list}) 35 | 36 | collector_list (_deps PROJECT_LIB_DEPS) 37 | list (APPEND _deps "CppUTest") 38 | 39 | file(GLOB _sources tc/*.cpp) 40 | set (EXEPREX "run-test") 41 | set (EXETEST "${EXEPREX}-aie") 42 | add_executable (${EXETEST} ${_sources}) 43 | set_target_properties(${EXETEST} PROPERTIES CXX_STANDARD 11) 44 | if (NOT CPPUTEST_FOUND_LIB) 45 | add_dependencies (${EXETEST} cpputest) 46 | endif (NOT CPPUTEST_FOUND_LIB) 47 | if(TEST_HARDWARE) 48 | set (_test_cflag -DTEST_HARDWARE) 49 | endif (TEST_HARDWARE) 50 | if (AIE_GEN) 51 | set (_test_cflag ${_test_cflag} -DAIE_GEN=${AIE_GEN}) 52 | else(AIE_GEN) 53 | set (_test_cflag ${_test_cflag} -DAIE_GEN=1) 54 | endif(AIE_GEN) 55 | if (FAL_LINUX) 56 | set (_test_cflag ${_test_cflag} -DFAL_LINUX) 57 | endif(FAL_LINUX) 58 | target_compile_options (${EXETEST} PUBLIC ${_ec_flags} ${_test_cflag}) 59 | target_link_libraries (${EXETEST} ${_ec_flags} ${_deps}) 60 | install (TARGETS ${EXETEST} RUNTIME DESTINATION bin) 61 | 62 | #set library search PATH 63 | if (WITH_TESTS_EXEC) 64 | collector_list (_list PROJECT_LIB_DIRS) 65 | string(REPLACE " " ":" _libs_paths "${_list}") 66 | if (APPLE) 67 | set (_env "DYLD_LIBRARY_PATH=${_libs_paths}") 68 | else() 69 | set (_env "LD_LIBRARY_PATH=${_libs_paths}") 70 | endif(APPLE) 71 | 72 | set (_tests ${EXEPREX}-aie) 73 | foreach (_test ${_tests}) 74 | add_test(${_test} ${_test}) 75 | set_property(TEST ${_test} PROPERTY ENVIRONMENT "${_env}") 76 | add_custom_target(run_unit_test_${_test} ALL 77 | COMMENT "Run Tests" 78 | COMMAND ${CMAKE_CTEST_COMMAND} --output-on-failure 79 | POST_BUILD 80 | DEPENDS ${_test}) 81 | 82 | if(CMAKE_BUILD_TYPE STREQUAL "coverage" OR CODE_COVERAGE) 83 | if("${CMAKE_CXX_COMPILER_ID}" MATCHES "(Apple)?[Cc]lang") 84 | add_custom_target(coverage_report_${_test} ALL 85 | COMMENT "Generate coverage report" 86 | POST_BUILD 87 | DEPENDS run_unit_test_${_test} 88 | COMMAND llvm-profdata merge -sparse default.profraw -o ${_test}.profdata 89 | COMMAND llvm-cov report ${_test} -instr-profile=${_test}.profdata 90 | ) 91 | else() 92 | add_custom_target(coverage_report_${_test} ALL 93 | COMMENT "Generate coverage report" 94 | POST_BUILD 95 | DEPENDS run_unit_test_${_test} 96 | COMMAND lcov -c --rc lcov_branch_coverage=1 -d . -o coverage.info 97 | COMMAND lcov -l --rc lcov_branch_coverage=1 coverage.info 98 | ) 99 | endif("${CMAKE_CXX_COMPILER_ID}" MATCHES "(Apple)?[Cc]lang") 100 | endif(CMAKE_BUILD_TYPE STREQUAL "coverage" OR CODE_COVERAGE) 101 | endforeach(_test) 102 | endif (WITH_TESTS_EXEC) 103 | -------------------------------------------------------------------------------- /fal/tests/utests/tc/common/tc_config.h: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #ifndef HW_CONFIG_H 5 | #define HW_CONFIG_H 6 | 7 | #include 8 | 9 | #if AIE_GEN == 2 10 | 11 | #define HW_GEN XAIE_DEV_GEN_AIEML 12 | #define XAIE_NUM_ROWS 8 13 | #define XAIE_NUM_COLS 50 14 | #define XAIE_ADDR_ARRAY_OFF 0x800 15 | 16 | #define XAIE_BASE_ADDR 0x20000000000 17 | #define XAIE_COL_SHIFT 25 18 | #define XAIE_ROW_SHIFT 20 19 | #define XAIE_SHIM_ROW 0 20 | #define XAIE_MEM_TILE_ROW_START 1 21 | #define XAIE_MEM_TILE_NUM_ROWS 2 22 | #define XAIE_AIE_TILE_ROW_START 3 23 | #define XAIE_AIE_TILE_NUM_ROWS 8 24 | 25 | #elif AIE_GEN == 1 26 | 27 | #define HW_GEN XAIE_DEV_GEN_AIE 28 | #define XAIE_NUM_ROWS 9 29 | #define XAIE_NUM_COLS 50 30 | #define XAIE_ADDR_ARRAY_OFF 0x800 31 | 32 | #define XAIE_BASE_ADDR 0x20000000000 33 | #define XAIE_COL_SHIFT 23 34 | #define XAIE_ROW_SHIFT 18 35 | #define XAIE_SHIM_ROW 0 36 | #define XAIE_MEM_TILE_ROW_START 0 37 | #define XAIE_MEM_TILE_NUM_ROWS 0 38 | #define XAIE_AIE_TILE_ROW_START 1 39 | #define XAIE_AIE_TILE_NUM_ROWS 8 40 | 41 | #endif 42 | 43 | #endif /* HW_CONFIG_H */ 44 | -------------------------------------------------------------------------------- /fal/tests/utests/tc/test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include "xaiefal/xaiefal.hpp" 5 | 6 | #include "CppUTest/CommandLineTestRunner.h" 7 | 8 | using namespace xaiefal; 9 | 10 | int main(int ac, char** av) 11 | { 12 | 13 | Logger::log(LogLevel::INFO) << "xaiefal cpputests." << std::endl; 14 | return CommandLineTestRunner::RunAllTests(ac, av); 15 | } 16 | -------------------------------------------------------------------------------- /fal/tests/utests/tc/test_userevent.cpp: -------------------------------------------------------------------------------- 1 | // Copyright(C) 2020 - 2021 by Xilinx, Inc. All rights reserved. 2 | // SPDX-License-Identifier: MIT 3 | 4 | #include "xaiefal/xaiefal.hpp" 5 | 6 | #include "CppUTest/CommandLineTestRunner.h" 7 | #include "CppUTest/TestHarness.h" 8 | #include "CppUTest/TestRegistry.h" 9 | 10 | #include "common/tc_config.h" 11 | 12 | using namespace xaiefal; 13 | 14 | TEST_GROUP(UserEvent) 15 | { 16 | }; 17 | 18 | TEST(UserEvent, UserEventBasic) 19 | { 20 | AieRC RC; 21 | XAie_Events E; 22 | 23 | XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 24 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 25 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 26 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 27 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 28 | 29 | XAie_InstDeclare(DevInst, &ConfigPtr); 30 | 31 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 32 | CHECK_EQUAL(RC, XAIE_OK); 33 | XAieDev Aie(&DevInst, true); 34 | 35 | auto UserEvent = Aie.tile(1,3).core().userEvent(); 36 | RC = UserEvent->getEvent(E); 37 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 38 | RC = UserEvent->reserve(); 39 | CHECK_EQUAL(RC, XAIE_OK); 40 | RC = UserEvent->getEvent(E); 41 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_CORE); 42 | RC = UserEvent->start(); 43 | CHECK_EQUAL(RC, XAIE_OK); 44 | RC = UserEvent->stop(); 45 | CHECK_EQUAL(RC, XAIE_OK); 46 | RC = UserEvent->release(); 47 | CHECK_EQUAL(RC, XAIE_OK); 48 | 49 | auto UserEvent0 = Aie.tile(1,3).core().userEvent(); 50 | RC = UserEvent0->reserve(); 51 | CHECK_EQUAL(RC, XAIE_OK); 52 | RC = UserEvent0->getEvent(E); 53 | CHECK_EQUAL(RC, XAIE_OK); 54 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_CORE); 55 | auto UserEvent1 = Aie.tile(1,3).core().userEvent(); 56 | RC = UserEvent1->reserve(); 57 | CHECK_EQUAL(RC, XAIE_OK); 58 | RC = UserEvent1->getEvent(E); 59 | CHECK_EQUAL(RC, XAIE_OK); 60 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_1_CORE); 61 | auto UserEvent2 = Aie.tile(1,3).core().userEvent(); 62 | RC = UserEvent2->reserve(); 63 | CHECK_EQUAL(RC, XAIE_OK); 64 | RC = UserEvent2->getEvent(E); 65 | CHECK_EQUAL(RC, XAIE_OK); 66 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_2_CORE); 67 | auto UserEvent3 = Aie.tile(1,3).core().userEvent(); 68 | RC = UserEvent3->reserve(); 69 | CHECK_EQUAL(RC, XAIE_OK); 70 | RC = UserEvent3->getEvent(E); 71 | CHECK_EQUAL(RC, XAIE_OK); 72 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_3_CORE); 73 | auto UserEvent4 = Aie.tile(1,3).core().userEvent(); 74 | RC = UserEvent4->reserve(); 75 | CHECK_EQUAL(RC, XAIE_ERR); 76 | 77 | UserEvent = Aie.tile(1,3).mem().userEvent(); 78 | RC = UserEvent->reserve(); 79 | CHECK_EQUAL(RC, XAIE_OK); 80 | RC = UserEvent->getEvent(E); 81 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_MEM); 82 | RC = UserEvent->start(); 83 | CHECK_EQUAL(RC, XAIE_OK); 84 | RC = UserEvent->stop(); 85 | CHECK_EQUAL(RC, XAIE_OK); 86 | RC = UserEvent->release(); 87 | CHECK_EQUAL(RC, XAIE_OK); 88 | 89 | UserEvent = Aie.tile(1,0).pl().userEvent(); 90 | RC = UserEvent->reserve(); 91 | CHECK_EQUAL(RC, XAIE_OK); 92 | RC = UserEvent->getEvent(E); 93 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_PL); 94 | RC = UserEvent->start(); 95 | CHECK_EQUAL(RC, XAIE_OK); 96 | RC = UserEvent->stop(); 97 | CHECK_EQUAL(RC, XAIE_OK); 98 | RC = UserEvent->release(); 99 | CHECK_EQUAL(RC, XAIE_OK); 100 | } 101 | 102 | #if AIE_GEN != 1 103 | TEST(UserEvent, UserEventMemTileBasic) 104 | { 105 | AieRC RC; 106 | XAie_Events E; 107 | 108 | XAie_SetupConfig(ConfigPtr, HW_GEN, XAIE_BASE_ADDR, 109 | XAIE_COL_SHIFT, XAIE_ROW_SHIFT, 110 | XAIE_NUM_COLS, XAIE_NUM_ROWS, XAIE_SHIM_ROW, 111 | XAIE_MEM_TILE_ROW_START, XAIE_MEM_TILE_NUM_ROWS, 112 | XAIE_AIE_TILE_ROW_START, XAIE_AIE_TILE_NUM_ROWS); 113 | 114 | XAie_InstDeclare(DevInst, &ConfigPtr); 115 | 116 | RC = XAie_CfgInitialize(&(DevInst), &ConfigPtr); 117 | CHECK_EQUAL(RC, XAIE_OK); 118 | XAieDev Aie(&DevInst, true); 119 | 120 | //Error resource not resesrved 121 | auto UserEvent = Aie.tile(1,1).mem().userEvent(); 122 | RC = UserEvent->getEvent(E); 123 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 124 | RC = UserEvent->reserve(); 125 | CHECK_EQUAL(RC, XAIE_OK); 126 | RC = UserEvent->getEvent(E); 127 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_MEM_TILE); 128 | RC = UserEvent->start(); 129 | CHECK_EQUAL(RC, XAIE_OK); 130 | RC = UserEvent->stop(); 131 | CHECK_EQUAL(RC, XAIE_OK); 132 | RC = UserEvent->release(); 133 | CHECK_EQUAL(RC, XAIE_OK); 134 | 135 | auto UserEvent0 = Aie.tile(1,1).mem().userEvent(); 136 | RC = UserEvent0->reserve(); 137 | CHECK_EQUAL(RC, XAIE_OK); 138 | RC = UserEvent0->getEvent(E); 139 | CHECK_EQUAL(RC, XAIE_OK); 140 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_0_MEM_TILE); 141 | auto UserEvent1 = Aie.tile(1,1).mem().userEvent(); 142 | RC = UserEvent1->reserve(); 143 | CHECK_EQUAL(RC, XAIE_OK); 144 | RC = UserEvent1->getEvent(E); 145 | CHECK_EQUAL(RC, XAIE_OK); 146 | CHECK_EQUAL(E, XAIE_EVENT_USER_EVENT_1_MEM_TILE); 147 | auto UserEvent4 = Aie.tile(1,1).mem().userEvent(); 148 | RC = UserEvent4->reserve(); 149 | CHECK_EQUAL(RC, XAIE_INVALID_ARGS); 150 | } 151 | #endif 152 | --------------------------------------------------------------------------------