├── .github └── workflows │ ├── make.yml │ ├── net_printer.yml │ ├── package_and_test-container.yml │ ├── scoring_criteria.yml │ └── wirelength_analyzer.yml ├── .gitignore ├── .gitmodules ├── LICENSE.MIT ├── Makefile ├── README.md ├── alpha_submission ├── README.md ├── nxroute-poc_container.def ├── opencl_example │ └── opencl_example_container.def └── rwroute_container.def ├── compute-score.py ├── docs ├── AMD_E_Wh_RGB.jpg ├── FAQ.md ├── _config.yml ├── _layouts │ └── default.html ├── advanced.md ├── alpha_submission.md ├── benchmarks.md ├── contact.md ├── details.md ├── final_submission.md ├── flow-detailed.png ├── flow-simple.png ├── fpga24-contest-slides.pdf ├── index.md ├── results.md ├── score.md ├── start.md └── vivado-conflict.png ├── final_submission ├── README.md ├── nxroute-poc_container.def ├── opencl_example └── rwroute_container.def ├── gradle └── wrapper │ ├── gradle-wrapper.jar │ └── gradle-wrapper.properties ├── gradlew ├── net_printer ├── README.md └── np.py ├── networkx-proof-of-concept-router └── nxroute-poc.py ├── requirements.txt ├── scoring_formula ├── README.md ├── scoring_formula.py └── test_scoring_formula.py ├── settings.gradle ├── src └── com │ └── xilinx │ └── fpga24_routing_contest │ ├── CheckPhysNetlist.java │ ├── DcpToFPGAIF.java │ ├── DiffPhysNetlist.java │ └── PartialRouterPhysNetlist.java └── wirelength_analyzer ├── Makefile ├── README.md ├── __init__.py ├── test ├── __init__.py ├── find_vivado_critical_path_in_wirelength_graph.py ├── parse_vivado_route_tree.py └── test_wa.py ├── wa.py └── xcvup_device_data.py /.github/workflows/make.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/fpga24_routing_contest/HEAD/.github/workflows/make.yml -------------------------------------------------------------------------------- /.github/workflows/net_printer.yml: -------------------------------------------------------------------------------- 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