├── README.md ├── RM └── data │ └── RM.tcl ├── ai_engine └── data │ └── ai_engine.tcl ├── ams └── data │ └── ams.tcl ├── apmps └── data │ └── apmps.tcl ├── audio_embed └── data │ └── audio_embed.tcl ├── audio_formatter └── data │ └── audio_formatter.tcl ├── audio_spdif └── data │ └── audio_spdif.tcl ├── axi_bram └── data │ └── axi_bram.tcl ├── axi_can └── data │ └── axi_can.tcl ├── axi_cdma └── data │ └── axi_cdma.tcl ├── axi_clk_wiz └── data │ └── axi_clk_wiz.tcl ├── axi_dma └── data │ └── axi_dma.tcl ├── axi_emc └── data │ └── axi_emc.tcl ├── axi_ethernet └── data │ └── axi_ethernet.tcl ├── axi_gpio └── data │ └── axi_gpio.tcl ├── axi_iic └── data │ └── axi_iic.tcl ├── axi_mcdma └── data │ └── axi_mcdma.tcl ├── axi_pcie └── data │ └── axi_pcie.tcl ├── axi_perf_mon └── data │ └── axi_perf_mon.tcl ├── axi_qspi └── data │ └── axi_qspi.tcl ├── axi_sysace └── data │ └── axi_sysace.tcl ├── axi_tft └── data │ └── axi_tft.tcl ├── axi_timebase_wdt └── data │ └── axi_timebase_wdt.tcl ├── axi_traffic_gen └── data │ └── axi_traffic_gen.tcl ├── axi_usb2_device └── data │ └── axi_usb2_device.tcl ├── axi_vcu └── data │ └── axi_vcu.tcl ├── axi_vdma └── data │ └── axi_vdma.tcl ├── axi_vdu └── data │ └── axi_vdu.tcl ├── axi_xadc └── data │ └── axi_xadc.tcl ├── axis_switch └── data │ └── axis_switch.tcl ├── canfdps └── data │ └── canfdps.tcl ├── canps └── data │ └── canps.tcl ├── cpu └── data │ └── cpu.tcl ├── cpu_cortexa53 └── data │ └── cpu_cortexa53.tcl ├── cpu_cortexa72 └── data │ └── cpu_cortexa72.tcl ├── cpu_cortexa78 └── data │ └── cpu_cortexa78.tcl ├── cpu_cortexa9 └── data │ └── cpu_cortexa9.tcl ├── cpu_cortexr5 └── data │ └── cpu_cortexr5.tcl ├── crl_apb └── data │ └── crl_apb.tcl ├── ddrcps └── data │ └── ddrcps.tcl ├── ddrps └── data │ └── ddrps.tcl ├── ddrpsv └── data │ └── ddrpsv.tcl ├── debug_bridge └── data │ └── debug_bridge.tcl ├── demosaic └── data │ └── demosaic.tcl ├── devcfg └── data │ └── devcfg.tcl ├── device_tree └── data │ ├── common_proc.tcl │ ├── config.yaml │ ├── device_tree.tcl │ ├── kernel_dtsi │ ├── 2022.2 │ │ ├── BOARD │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include │ │ │ └── dt-bindings │ │ │ │ ├── clock │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ │ ├── dma │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ │ ├── gpio │ │ │ │ └── gpio.h │ │ │ │ ├── input │ │ │ │ └── input.h │ │ │ │ ├── interrupt-controller │ │ │ │ └── irq.h │ │ │ │ ├── net │ │ │ │ └── ti-dp83867.h │ │ │ │ ├── phy │ │ │ │ └── phy.h │ │ │ │ ├── pinctrl │ │ │ │ └── pinctrl-zynqmp.h │ │ │ │ ├── power │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ │ └── reset │ │ │ │ ├── xlnx-versal-resets.h │ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal-net │ │ │ └── versal-net-ipp-rev1.9.dtsi │ │ ├── versal │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp │ │ │ ├── zynqmp-clk-ccf.dtsi │ │ │ └── zynqmp.dtsi │ ├── 2023.2 │ │ ├── BOARD │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vek280-revb.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynq-zc770-xm010.dtsi │ │ │ ├── zynq-zc770-xm011-x16.dtsi │ │ │ ├── zynq-zc770-xm011.dtsi │ │ │ ├── zynq-zc770-xm012.dtsi │ │ │ ├── zynq-zc770-xm013.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include │ │ │ └── dt-bindings │ │ │ │ ├── clock │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ ├── xlnx-versal-net-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ │ ├── dma │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ │ ├── gpio │ │ │ │ └── gpio.h │ │ │ │ ├── input │ │ │ │ └── input.h │ │ │ │ ├── interrupt-controller │ │ │ │ └── irq.h │ │ │ │ ├── net │ │ │ │ ├── mscc-phy-vsc8531.h │ │ │ │ └── ti-dp83867.h │ │ │ │ ├── phy │ │ │ │ └── phy.h │ │ │ │ ├── pinctrl │ │ │ │ └── pinctrl-zynqmp.h │ │ │ │ ├── power │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ │ └── reset │ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ │ ├── xlnx-versal-resets.h │ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal-net │ │ │ ├── versal-net-clk-ccf.dtsi │ │ │ ├── versal-net-clk.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ └── versal-net.dtsi │ │ ├── versal │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp │ │ │ ├── zynqmp-clk-ccf.dtsi │ │ │ └── zynqmp.dtsi │ └── 2024.1 │ │ ├── BOARD │ │ ├── ac701-full.dtsi │ │ ├── ac701-lite.dtsi │ │ ├── avnet-ultra96-rev1.dtsi │ │ ├── kc705-full.dtsi │ │ ├── kc705-lite.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── kcu105.dtsi │ │ ├── sp701-rev1.0.dtsi │ │ ├── vcu118-rev2.0.dtsi │ │ ├── versal-a2197-sc-reva.dtsi │ │ ├── versal-emb-plus-ve2302-reva.dtsi │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ ├── versal-net-emu-rev1.9.dtsi │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ ├── versal-v350-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck5000-reva.dtsi │ │ ├── versal-vek280-reva.dtsi │ │ ├── versal-vek280-revb.dtsi │ │ ├── versal-vhk158-reva.dtsi │ │ ├── versal-virt.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva.dtsi │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ ├── versal-vpk120-reva.dtsi │ │ ├── versal-vpk120-revb.dtsi │ │ ├── versal-vpk180-reva.dtsi │ │ ├── versal-x-ebm-01-reva.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── versal-x-ebm-03-reva.dtsi │ │ ├── zc1232-reva.dtsi │ │ ├── zc1254-reva.dtsi │ │ ├── zc1751-dc1.dtsi │ │ ├── zc1751-dc2.dtsi │ │ ├── zc702.dtsi │ │ ├── zc706.dtsi │ │ ├── zcu100-reva.dtsi │ │ ├── zcu100-revb.dtsi │ │ ├── zcu100-revc.dtsi │ │ ├── zcu102-rev1.0.dtsi │ │ ├── zcu102-reva.dtsi │ │ ├── zcu102-revb.dtsi │ │ ├── zcu104-reva.dtsi │ │ ├── zcu104-revc.dtsi │ │ ├── zcu106-reva.dtsi │ │ ├── zcu111-reva.dtsi │ │ ├── zcu1275-reva.dtsi │ │ ├── zcu1275-revb.dtsi │ │ ├── zcu1285-reva.dtsi │ │ ├── zcu208-reva.dtsi │ │ ├── zcu216-reva.dtsi │ │ ├── zcu670-reva.dtsi │ │ ├── zcu670-revb.dtsi │ │ ├── zedboard.dtsi │ │ ├── zynq-zc770-xm010.dtsi │ │ ├── zynq-zc770-xm011-x16.dtsi │ │ ├── zynq-zc770-xm011.dtsi │ │ ├── zynq-zc770-xm012.dtsi │ │ ├── zynq-zc770-xm013.dtsi │ │ ├── zynqmp-a2197-reva.dtsi │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ ├── zynqmp-sc-revb.dtsi │ │ ├── zynqmp-sc-revc.dtsi │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include │ │ └── dt-bindings │ │ │ ├── clock │ │ │ ├── xlnx-versal-clk.h │ │ │ ├── xlnx-versal-net-clk.h │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio │ │ │ └── gpio.h │ │ │ ├── input │ │ │ └── input.h │ │ │ ├── interrupt-controller │ │ │ └── irq.h │ │ │ ├── net │ │ │ ├── mscc-phy-vsc8531.h │ │ │ └── ti-dp83867.h │ │ │ ├── phy │ │ │ └── phy.h │ │ │ ├── pinctrl │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power │ │ │ ├── xlnx-versal-net-power.h │ │ │ ├── xlnx-versal-power.h │ │ │ ├── xlnx-versal-regnode.h │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal-net │ │ ├── versal-net-clk-ccf.dtsi │ │ ├── versal-net-clk.dtsi │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ └── versal-net.dtsi │ │ ├── versal │ │ ├── versal-clk.dtsi │ │ ├── versal-spp-pm.dtsi │ │ └── versal.dtsi │ │ ├── zynq │ │ ├── skeleton.dtsi │ │ └── zynq-7000.dtsi │ │ └── zynqmp │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── partial_proc.tcl │ ├── video_utils.tcl │ ├── xillib_common.tcl │ ├── xillib_hw.tcl │ ├── xillib_internal.tcl │ └── xillib_sw.tcl ├── dfeccf └── data │ └── dfeccf.tcl ├── dfemix └── data │ └── dfemix.tcl ├── dfeprach └── data │ └── dfeprach.tcl ├── dmaps └── data │ └── dmaps.tcl ├── dp └── data │ └── dp.tcl ├── dp12_14_core └── data │ └── dp12_14_core.tcl ├── dp_hdcp22_rx └── data │ └── dp_hdcp22_rx.tcl ├── dp_hdcp22_tx └── data │ └── dp_hdcp22_tx.tcl ├── dp_rx └── data │ └── dp_rx.tcl ├── dp_rxss12 └── data │ └── dp_rxss12.tcl ├── dp_rxss14 └── data │ └── dp_rxss14.tcl ├── dp_rxss21 └── data │ └── dp_rxss21.tcl ├── dp_tx └── data │ └── dp_tx.tcl ├── dp_txss12 └── data │ └── dp_txss12.tcl ├── dp_txss14 └── data │ └── dp_txss14.tcl ├── dp_txss21 └── data │ └── dp_txss21.tcl ├── dprx21_core └── data │ └── dprx21_core.tcl ├── dptx21_core └── data │ └── dptx21_core.tcl ├── dpu_eu └── data │ └── dpu_eu.tcl ├── emaclite └── data │ └── emaclite.tcl ├── emacps └── data │ └── emacps.tcl ├── ernic └── data │ └── ernic.tcl ├── framebuf_rd └── data │ └── framebuf_rd.tcl ├── framebuf_wr └── data │ └── framebuf_wr.tcl ├── gamma_lut └── data │ └── gamma_lut.tcl ├── generic └── data │ └── generic.tcl ├── globaltimerps └── data │ └── globaltimerps.tcl ├── gpiops └── data │ └── gpiops.tcl ├── hdmi_ctrl └── data │ └── hdmi_ctrl.tcl ├── hdmi_gt_ctrl └── data │ └── hdmi_gt_ctrl.tcl ├── hdmi_hdcp22_rx └── data │ └── hdmi_hdcp22_rx.tcl ├── hdmi_hdcp22_tx └── data │ └── hdmi_hdcp22_tx.tcl ├── hdmi_phy1 └── data │ └── hdmi_phy1.tcl ├── hdmi_rx └── data │ └── hdmi_rx.tcl ├── hdmi_rx1 └── data │ └── hdmi_rx1.tcl ├── hdmi_rx_ss └── data │ └── hdmi_rx_ss.tcl ├── hdmi_rxss1 └── data │ └── hdmi_rxss1.tcl ├── hdmi_tx └── data │ └── hdmi_tx.tcl ├── hdmi_tx1 └── data │ └── hdmi_tx1.tcl ├── hdmi_tx_ss └── data │ └── hdmi_tx_ss.tcl ├── hdmi_txss1 └── data │ └── hdmi_txss1.tcl ├── i2s_receiver └── data │ └── i2s_receiver.tcl ├── i2s_transmitter └── data │ └── i2s_transmitter.tcl ├── i3cpsx └── data │ └── i3cpsx.tcl ├── iicps └── data │ └── iicps.tcl ├── intc └── data │ └── intc.tcl ├── iomodule └── data │ └── iomodule.tcl ├── ipipsu └── data │ └── ipipsu.tcl ├── license.txt ├── linear_spi └── data │ └── linear_spi.tcl ├── mig_7series └── data │ └── mig_7series.tcl ├── mipi_csi2_rx └── data │ └── mipi_csi2_rx.tcl ├── mipi_csi2_rx_core └── data │ └── mipi_csi2_rx_core.tcl ├── mipi_csi2_rx_ss └── data │ └── mipi_csi2_rx_ss.tcl ├── mipi_csi2_tx_core └── data │ └── mipi_csi2_tx_core.tcl ├── mipi_csi2_tx_ss └── data │ └── mipi_csi2_tx_ss.tcl ├── mipi_dphy └── data │ └── mipi_dphy.tcl ├── mipi_dsi2_rx └── data │ └── mipi_dsi2_rx.tcl ├── mipi_dsi2_rx_core └── data │ └── mipi_dsi2_rx_core.tcl ├── mipi_dsi2_rx_ss └── data │ └── mipi_dsi2_rx_ss.tcl ├── mipi_dsi_rx └── data │ └── mipi_dsi_rx.tcl ├── mipi_dsi_rx_core └── data │ └── mipi_dsi_rx_core.tcl ├── mipi_dsi_rx_ss └── data │ └── mipi_dsi_rx_ss.tcl ├── mipi_dsi_tx └── data │ └── mipi_dsi_tx.tcl ├── mipi_dsi_tx_core └── data │ └── mipi_dsi_tx_core.tcl ├── mipi_dsi_tx_ss └── data │ └── mipi_dsi_tx_ss.tcl ├── mipi_rx_phy └── data │ └── mipi_rx_phy.tcl ├── mipi_tx_phy └── data │ └── mipi_tx_phy.tcl ├── mixer └── data │ └── mixer.tcl ├── mrmac └── data │ └── mrmac.tcl ├── multi_scaler └── data │ └── multi_scaler.tcl ├── nandps └── data │ └── nandps.tcl ├── norps └── data │ └── norps.tcl ├── nvme_aggr └── data │ └── nvme_aggr.tcl ├── ocmcps └── data │ └── ocmcps.tcl ├── ospips └── data │ └── ospips.tcl ├── pl310ps └── data │ └── pl310ps.tcl ├── pmups └── data │ └── pmups.tcl ├── pr_decoupler └── data │ └── pr_decoupler.tcl ├── prc └── data │ ├── api.tcl │ └── prc.tcl ├── psu_ocm └── data │ └── psu_ocm.tcl ├── ptp_1588_timer_syncer └── data │ └── ptp_1588_timer_syncer.tcl ├── qspips └── data │ └── qspips.tcl ├── ramps └── data │ └── ramps.tcl ├── rfdc └── data │ └── rfdc.tcl ├── scene_change_detector └── data │ └── scene_change_detector.tcl ├── scugic └── data │ └── scugic.tcl ├── scutimer └── data │ └── scutimer.tcl ├── scuwdt └── data │ └── scuwdt.tcl ├── sdfec └── data │ └── sdfec.tcl ├── sdi_rx └── data │ └── sdi_rx.tcl ├── sdi_rxss └── data │ └── sdi_rxss.tcl ├── sdi_tx └── data │ └── sdi_tx.tcl ├── sdi_txss └── data │ └── sdi_txss.tcl ├── sdps └── data │ └── sdps.tcl ├── slcrps └── data │ └── slcrps.tcl ├── smccps └── data │ └── smccps.tcl ├── spips └── data │ └── spips.tcl ├── sync_ip └── data │ └── sync_ip.tcl ├── sysmon └── data │ └── sysmon.tcl ├── sysmonpsv └── data │ └── sysmonpsv.tcl ├── tmrctr └── data │ └── tmrctr.tcl ├── tpg └── data │ └── tpg.tcl ├── trngpsx └── data │ └── trngpsx.tcl ├── tsn └── data │ └── tsn.tcl ├── ttcps └── data │ └── ttcps.tcl ├── uartlite └── data │ └── uartlite.tcl ├── uartns └── data │ └── uartns.tcl ├── uartps └── data │ └── uartps.tcl ├── usbps └── data │ └── usbps.tcl ├── vid_phy_ctrl └── data │ └── vid_phy_ctrl.tcl ├── vproc_ss └── data │ └── vproc_ss.tcl ├── vtc └── data │ └── vtc.tcl ├── wdtps └── data │ └── wdtps.tcl ├── wdttb └── data │ └── wdttb.tcl ├── xadcps └── data │ └── xadcps.tcl └── xdmapcie └── data └── xdmapcie.tcl /RM/data/RM.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc RM_generate {drv_handle} { 17 | set val [hsi get_property FAMILY [hsi::get_hw_designs]] 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts] 20 | switch -glob $val { 21 | "zynq" { 22 | add_prop $node "fpga-mgr" "<&devcfg>" string $dts_file 23 | } 24 | } 25 | } 26 | 27 | -------------------------------------------------------------------------------- /apmps/data/apmps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc apmps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /audio_formatter/data/audio_formatter.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc audio_formatter_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | set node [get_node $drv_handle] 26 | if {$node == 0} { 27 | return 28 | } 29 | pldt append $node compatible "\ \, \"xlnx,audio-formatter-1.0\"" 30 | 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /axi_iic/data/axi_iic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_iic_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | 26 | pldt append $node compatible "\ \, \"xlnx,xps-iic-2.00.a\"" 27 | set proctype [get_hw_family] 28 | if {[regexp "microblaze" $proctype match]} { 29 | gen_dev_ccf_binding $drv_handle "s_axi_aclk" 30 | } 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /axi_perf_mon/data/axi_perf_mon.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_perf_mon_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | 26 | pldt append $node compatible "\ \, \"xlnx,axi-perf-monitor\"" 27 | set check_list "enable-profile enable-trace num-monitor-slots enable-event-count enable-event-log have-sampled-metric-cnt num-of-counters metric-count-width metrics-sample-count-width global-count-width metric-count-scale" 28 | foreach p ${check_list} { 29 | set ip_conf [string toupper "c_${p}"] 30 | regsub -all {\-} $ip_conf {_} ip_conf 31 | set_drv_conf_prop $drv_handle ${ip_conf} xlnx,${p} $node hexint 32 | } 33 | } 34 | 35 | 36 | -------------------------------------------------------------------------------- /axi_sysace/data/axi_sysace.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_sysace_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /axi_tft/data/axi_tft.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_tft_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /axi_usb2_device/data/axi_usb2_device.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_usb2_device_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | pldt append $node compatible "\ \, \"xlnx,usb2-device-4.00.a\"" 26 | set ip [hsi::get_cells -hier $drv_handle] 27 | set include_dma [hsi get_property CONFIG.C_INCLUDE_DMA $ip] 28 | if { $include_dma eq "1"} { 29 | set_drv_conf_prop $drv_handle C_INCLUDE_DMA xlnx,has-builtin-dma $node boolean 30 | } 31 | 32 | } 33 | 34 | 35 | -------------------------------------------------------------------------------- /canfdps/data/canfdps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc canfdps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /canps/data/canps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc canps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /cpu_cortexa9/data/cpu_cortexa9.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc cpu_cortexa9_generate {drv_handle} { 17 | global dtsi_fname 18 | set dtsi_fname "zynq/zynq-7000.dtsi" 19 | update_system_dts_include [file tail ${dtsi_fname}] 20 | set bus_name "amba" 21 | set fields [split [get_ip_property $drv_handle NAME] "_"] 22 | set cpu_nr [lindex $fields end] 23 | set ip_name [get_ip_property $drv_handle IP_NAME] 24 | set cpu_node [create_node -n "&ps7_cortexa9_${cpu_nr}" -d "pcw.dtsi" -p root -h $drv_handle] 25 | add_prop $cpu_node "xlnx,ip-name" $ip_name string "pcw.dtsi" 26 | add_prop $cpu_node "bus-handle" $bus_name reference "pcw.dtsi" 27 | gen_drv_prop_from_ip $drv_handle 28 | set amba_node [create_node -n "&${bus_name}" -d "pcw.dtsi" -p root] 29 | } 30 | 31 | -------------------------------------------------------------------------------- /crl_apb/data/crl_apb.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2020-2021 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc crl_apb_generate {drv_handle} { 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | } 19 | 20 | 21 | -------------------------------------------------------------------------------- /debug_bridge/data/debug_bridge.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2020-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc debug_bridge_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"generic-uio\"" 22 | } 23 | 24 | 25 | -------------------------------------------------------------------------------- /devcfg/data/devcfg.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc devcfg_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /device_tree/data/config.yaml: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | --- 16 | dict_devicetree: 17 | kernel_ver: 2024.1 18 | mainline_kernel: none 19 | board_dts: versal-vck190-reva 20 | dt_overlay: false 21 | output_dir: output_dts 22 | dt_zocl: false 23 | --- 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/vcu118-rev2.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-property/ pcs-handle; 4 | /delete-property/ managed; 5 | /delete-property/ xlnx,switch-x-sgmii; 6 | /delete-node/ mdio; 7 | axi_ethernet_mdio: mdio { 8 | #address-cells = <1>; 9 | #size-cells = <0>; 10 | phy0: phy@3 { 11 | device_type = "ethernet-phy"; 12 | ti,sgmii-ref-clock-output-enable; 13 | ti,dp83867-rxctrl-strap-quirk; 14 | ti,rx-internal-delay = <0x8>; 15 | ti,tx-internal-delay = <0xa>; 16 | ti,fifo-depth = <0x1>; 17 | reg = <3>; 18 | }; 19 | }; 20 | }; 21 | 22 | &axi_iic_0 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | i2c-mux@75 { 26 | compatible = "nxp,pca9548"; 27 | #address-cells = <1>; 28 | #size-cells = <0>; 29 | reg = <0x75>; 30 | i2c@3 { 31 | #address-cells = <1>; 32 | #size-cells = <0>; 33 | reg = <3>; 34 | eeprom@54 { 35 | compatible = "atmel,24c08"; 36 | reg = <0x54>; 37 | }; 38 | }; 39 | }; 40 | i2c-mux@74 { 41 | compatible = "nxp,pca9548"; 42 | #address-cells = <1>; 43 | #size-cells = <0>; 44 | reg = <0x74>; 45 | i2c@0 { 46 | #address-cells = <1>; 47 | #size-cells = <0>; 48 | reg = <0>; 49 | si570: clock-generator@5d { 50 | #clock-cells = <0>; 51 | compatible = "silabs,si570"; 52 | temperature-stability = <50>; 53 | reg = <0x5d>; 54 | factory-fout = <156250000>; 55 | clock-frequency = <148500000>; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021 - 2022, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-net-ipp-rev1.9.dtsi" 11 | 12 | / { 13 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 14 | }; 15 | 16 | &ospi { 17 | status = "okay"; 18 | }; 19 | 20 | &qspi { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal v350 revA 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "include/dt-bindings/gpio/gpio.h" 11 | 12 | / { 13 | compatible = "xlnx,versal-v350-revA", "xlnx,versal"; 14 | model = "Xilinx Versal v350 board revA"; 15 | 16 | chosen { 17 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; 18 | stdout-path = "serial0:115200"; 19 | }; 20 | 21 | aliases { 22 | serial0 = &serial0; 23 | serial1 = &serial1; 24 | spi0 = &ospi; 25 | }; 26 | }; 27 | 28 | &dcc { 29 | status = "okay"; 30 | }; 31 | 32 | &ospi { 33 | bus-num = <2>; 34 | num-cs = <1>; 35 | #address-cells = <1>; 36 | #size-cells = <0>; 37 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 38 | 39 | flash@0 { 40 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 41 | reg = <0>; 42 | #address-cells = <0x1>; 43 | #size-cells = <0x1>; 44 | cdns,read-delay = <0x0>; 45 | cdns,tshsl-ns = <0x0>; 46 | cdns,tsd2d-ns = <0x0>; 47 | cdns,tchsh-ns = <0x1>; 48 | cdns,tslch-ns = <0x1>; 49 | spi-tx-bus-width = <8>; 50 | spi-rx-bus-width = <8>; 51 | spi-max-frequency = <20000000>; 52 | partition@0 { 53 | label = "spi0-flash0"; 54 | reg = <0x0 0x8000000>; 55 | }; 56 | }; 57 | }; 58 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-01 revA (SE1) 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | 14 | / { 15 | compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", 16 | "xlnx,versal-vc-p-a2197-00-revA", 17 | "xlnx,versal-vc-p-a2197-00", 18 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 19 | model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; 20 | 21 | aliases { 22 | spi0 = &ospi; 23 | }; 24 | }; 25 | 26 | /* Mutually exclusive */ 27 | &ospi { 28 | bus-num = <2>; 29 | num-cs = <1>; 30 | #address-cells = <1>; 31 | #size-cells = <0>; 32 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 33 | reset-names = "qspi"; 34 | resets = <&versal_reset VERSAL_RST_OSPI>; 35 | 36 | flash@0 { 37 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 38 | reg = <0>; 39 | #address-cells = <0x1>; 40 | #size-cells = <0x1>; 41 | cdns,read-delay = <0x0>; 42 | cdns,tshsl-ns = <0x0>; 43 | cdns,tsd2d-ns = <0x0>; 44 | cdns,tchsh-ns = <0x1>; 45 | cdns,tslch-ns = <0x1>; 46 | spi-tx-bus-width = <8>; 47 | spi-rx-bus-width = <8>; 48 | spi-max-frequency = <20000000>; 49 | partition@0 { 50 | label = "spi0-flash0"; 51 | reg = <0x0 0x8000000>; 52 | }; 53 | }; 54 | }; 55 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | / { 11 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 12 | "xlnx,versal-vc-p-a2197-00", 13 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 14 | model = "Xilinx Versal A2197 Processor board revA"; 15 | 16 | }; 17 | 18 | &dcc { 19 | status = "okay"; 20 | }; 21 | 22 | &sdhci0 { 23 | no-1-8-v; 24 | }; 25 | 26 | &sdhci1 { 27 | no-1-8-v; 28 | }; 29 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 14 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 14 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 14 | model = "Xilinx Versal vck190 Eval board rev1.1"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 10 | 11 | / { 12 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 13 | "xlnx,versal-vck190-revA", "xlnx,versal"; 14 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 14 | model = "Xilinx Versal vck190 Eval board revA"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck5000 revA 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "include/dt-bindings/gpio/gpio.h" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; 14 | model = "Xilinx Versal vck5000 board revA"; 15 | 16 | chosen { 17 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 18 | stdout-path = "serial0:115200"; 19 | }; 20 | 21 | aliases { 22 | serial0 = &serial0; 23 | serial1 = &serial1; 24 | spi0 = &ospi; 25 | }; 26 | 27 | }; 28 | 29 | &ospi { 30 | bus-num = <2>; 31 | num-cs = <1>; 32 | #address-cells = <1>; 33 | #size-cells = <0>; 34 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 35 | 36 | flash@0 { 37 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 38 | reg = <0>; 39 | #address-cells = <0x1>; 40 | #size-cells = <0x1>; 41 | cdns,read-delay = <0x0>; 42 | cdns,tshsl-ns = <0x0>; 43 | cdns,tsd2d-ns = <0x0>; 44 | cdns,tchsh-ns = <0x1>; 45 | cdns,tslch-ns = <0x1>; 46 | spi-tx-bus-width = <8>; 47 | spi-rx-bus-width = <8>; 48 | spi-max-frequency = <20000000>; 49 | partition@0 { 50 | label = "spi0-flash0"; 51 | reg = <0x0 0x10000000>; 52 | }; 53 | }; 54 | }; 55 | 56 | &dcc { 57 | status = "okay"; 58 | }; 59 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019 - 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 16 | }; 17 | 18 | &sdhci1 { 19 | #include "versal-x-ebm-02-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | #include "versal-vmk180-rev1.1.dtsi" 10 | 11 | / { 12 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 13 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 14 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 15 | }; 16 | 17 | &ospi { 18 | #include "versal-x-ebm-03-reva.dtsi" 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019 - 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 14 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 15 | }; 16 | 17 | &sdhci1 { /* PMC_MIO26-36/51 */ 18 | clk-phase-sd-hs = <111>, <48>; 19 | clk-phase-uhs-sdr25 = <114>, <48>; 20 | clk-phase-uhs-ddr50 = <126>, <36>; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | #include "versal-vmk180-reva.dtsi" 10 | 11 | / { 12 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 13 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 14 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 15 | }; 16 | 17 | &qspi { 18 | #include "versal-x-ebm-01-reva.dtsi" 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 16 | }; 17 | 18 | &sdhci1 { 19 | #include "versal-x-ebm-02-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | #include "versal-vmk180-reva.dtsi" 10 | 11 | / { 12 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 13 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 14 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 15 | 16 | aliases { 17 | spi0 = &ospi; 18 | }; 19 | }; 20 | 21 | &ospi { 22 | #include "versal-x-ebm-03-reva.dtsi" 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | num-cs = <2>; 11 | spi-tx-bus-width = <4>; 12 | spi-rx-bus-width = <4>; 13 | #address-cells = <1>; 14 | #size-cells = <0>; 15 | is-dual = <1>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 11 | non-removable; 12 | disable-wp; 13 | bus-width = <8>; 14 | xlnx,mio-bank = <0>; 15 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "include/dt-bindings/gpio/gpio.h" 11 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 12 | /* U97 MT35XU02G */ 13 | compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; 14 | bus-num = <2>; 15 | num-cs = <1>; 16 | #address-cells = <1>; 17 | #size-cells = <0>; 18 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 19 | reset-names = "qspi"; 20 | resets = <&versal_reset VERSAL_RST_OSPI>; 21 | 22 | flash@0 { 23 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 24 | reg = <0>; 25 | #address-cells = <1>; 26 | #size-cells = <1>; 27 | cdns,read-delay = <0x0>; 28 | cdns,tshsl-ns = <0x0>; 29 | cdns,tsd2d-ns = <0x0>; 30 | cdns,tchsh-ns = <0x1>; 31 | cdns,tslch-ns = <0x1>; 32 | spi-tx-bus-width = <8>; 33 | spi-rx-bus-width = <8>; 34 | spi-max-frequency = <20000000>; 35 | partition@0 { 36 | label = "spi0-flash0"; 37 | reg = <0x0 0x8000000>; 38 | }; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015 - 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | * Siva Durga Prasad Paladugu 9 | */ 10 | 11 | / { 12 | model = "ZynqMP ZC1254 RevA"; 13 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 14 | }; 15 | 16 | &qspi { 17 | flash@0 { 18 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 19 | #address-cells = <1>; 20 | #size-cells = <1>; 21 | reg = <0x0>; 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 24 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 25 | partition@0 { /* for testing purpose */ 26 | label = "qspi-fsbl-uboot"; 27 | reg = <0x0 0x100000>; 28 | }; 29 | partition@100000 { /* for testing purpose */ 30 | label = "qspi-linux"; 31 | reg = <0x100000 0x500000>; 32 | }; 33 | partition@600000 { /* for testing purpose */ 34 | label = "qspi-device-tree"; 35 | reg = <0x600000 0x20000>; 36 | }; 37 | partition@620000 { /* for testing purpose */ 38 | label = "qspi-rootfs"; 39 | reg = <0x620000 0x5E0000>; 40 | }; 41 | }; 42 | }; 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * (C) Copyright 2016 - 2020, Xilinx, Inc. 5 | * 6 | * Michal Simek 7 | */ 8 | 9 | #include "zcu102-revb.dtsi" 10 | 11 | / { 12 | model = "ZynqMP ZCU102 Rev1.0"; 13 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 14 | }; 15 | 16 | &eeprom { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | 20 | board_sn: board-sn@0 { 21 | reg = <0x0 0x14>; 22 | }; 23 | 24 | eth_mac: eth-mac@20 { 25 | reg = <0x20 0x6>; 26 | }; 27 | 28 | board_name: board-name@d0 { 29 | reg = <0xd0 0x6>; 30 | }; 31 | 32 | board_revision: board-revision@e0 { 33 | reg = <0xe0 0x3>; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016 - 2020, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zcu102-reva.dtsi" 11 | 12 | / { 13 | model = "ZynqMP ZCU102 RevB"; 14 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15 | }; 16 | 17 | &gem3 { 18 | phy-handle = <&phyc>; 19 | phyc: ethernet-phy@c { 20 | reg = <0xc>; 21 | ti,rx-internal-delay = <0x8>; 22 | ti,tx-internal-delay = <0xa>; 23 | ti,fifo-depth = <0x1>; 24 | ti,dp83867-rxctrl-strap-quirk; 25 | /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ 26 | }; 27 | /* Cleanup from RevA */ 28 | /delete-node/ ethernet-phy@21; 29 | }; 30 | 31 | /* Fix collision with u61 */ 32 | &i2c0 { 33 | i2c-mux@75 { 34 | i2c@2 { 35 | max15303@1b { /* u8 */ 36 | compatible = "maxim,max15303"; 37 | reg = <0x1b>; 38 | }; 39 | /delete-node/ max15303@20; 40 | }; 41 | }; 42 | }; 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU1275 4 | * 5 | * (C) Copyright 2017 - 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | * Siva Durga Prasad Paladugu 9 | */ 10 | 11 | / { 12 | model = "ZynqMP ZCU1275 RevA"; 13 | compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", 14 | "xlnx,zynqmp"; 15 | }; 16 | 17 | &qspi { 18 | flash@0 { 19 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 20 | #address-cells = <1>; 21 | #size-cells = <1>; 22 | reg = <0x0>; 23 | spi-tx-bus-width = <1>; 24 | spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ 25 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 26 | partition@0 { /* for testing purpose */ 27 | label = "qspi-fsbl-uboot"; 28 | reg = <0x0 0x100000>; 29 | }; 30 | partition@100000 { /* for testing purpose */ 31 | label = "qspi-linux"; 32 | reg = <0x100000 0x500000>; 33 | }; 34 | partition@600000 { /* for testing purpose */ 35 | label = "qspi-device-tree"; 36 | reg = <0x600000 0x20000>; 37 | }; 38 | partition@620000 { /* for testing purpose */ 39 | label = "qspi-rootfs"; 40 | reg = <0x620000 0x5E0000>; 41 | }; 42 | }; 43 | }; 44 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zedboard.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | model = "Zynq Zed Development Board"; 3 | compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 4 | 5 | usb_phy0: phy0@e0002000 { 6 | compatible = "ulpi-phy"; 7 | #phy-cells = <0>; 8 | reg = <0xe0002000 0x1000>; 9 | view-port = <0x0170>; 10 | drv-vbus; 11 | }; 12 | }; 13 | 14 | &clkc { 15 | ps-clk-frequency = <33333333>; 16 | }; 17 | 18 | &gem0 { 19 | phy-handle = <ðernet_phy>; 20 | ethernet_phy: ethernet-phy@0 { 21 | reg = <0>; 22 | device_type = "ethernet-phy"; 23 | }; 24 | }; 25 | 26 | &qspi { 27 | u-boot,dm-pre-reloc; 28 | is-dual = <0>; 29 | num-cs = <1>; 30 | flash@0 { 31 | compatible = "n25q128a11", "jedec,spi-nor"; 32 | reg = <0x0>; 33 | spi-tx-bus-width = <1>; 34 | spi-rx-bus-width = <4>; 35 | spi-max-frequency = <50000000>; 36 | #address-cells = <1>; 37 | #size-cells = <1>; 38 | partition@qspi-fsbl-uboot { 39 | label = "qspi-fsbl-uboot"; 40 | reg = <0x0 0x100000>; 41 | }; 42 | partition@qspi-linux { 43 | label = "qspi-linux"; 44 | reg = <0x100000 0x500000>; 45 | }; 46 | partition@qspi-device-tree { 47 | label = "qspi-device-tree"; 48 | reg = <0x600000 0x20000>; 49 | }; 50 | partition@qspi-rootfs { 51 | label = "qspi-rootfs"; 52 | reg = <0x620000 0x5E0000>; 53 | }; 54 | partition@qspi-bitstream { 55 | label = "qspi-bitstream"; 56 | reg = <0xC00000 0x400000>; 57 | }; 58 | }; 59 | }; 60 | 61 | &sdhci0 { 62 | u-boot,dm-pre-reloc; 63 | }; 64 | 65 | &uart1 { 66 | u-boot,dm-pre-reloc; 67 | }; 68 | 69 | &usb0 { 70 | dr_mode = "host"; 71 | usb-phy = <&usb_phy0>; 72 | }; 73 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019 - 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-e-a2197-00-reva.dtsi" 11 | 12 | / { 13 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 14 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 15 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 16 | 17 | /delete-node/ ina226-vcco-500; 18 | /delete-node/ ina226-vcco-501; 19 | /delete-node/ ina226-vcco-502; 20 | }; 21 | 22 | &i2c0 { 23 | i2c-mux@74 { /* u33 */ 24 | i2c@2 { /* PCIE_CLK */ 25 | /delete-node/ clock-generator@6c; 26 | }; 27 | i2c@3 { /* PMBUS2_INA226 */ 28 | /delete-node/ ina226@42; 29 | /delete-node/ ina226@43; 30 | /delete-node/ ina226@44; 31 | }; 32 | }; 33 | }; 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021, Xilinx, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sm-k26-reva.dtsi" 11 | 12 | / { 13 | model = "ZynqMP SMK-K26 Rev1/B/A"; 14 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 15 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 16 | "xlnx,zynqmp"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020 Xilinx, Inc. 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 9 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | 11 | /* Bit value for different voltage levels */ 12 | #define IO_STANDARD_LVCMOS33 0 13 | #define IO_STANDARD_LVCMOS18 1 14 | 15 | /* Bit values for Slew Rates */ 16 | #define SLEW_RATE_FAST 0 17 | #define SLEW_RATE_SLOW 1 18 | 19 | /* Bit values for Pin drive strength */ 20 | #define DRIVE_STRENGTH_2MA 2 21 | #define DRIVE_STRENGTH_4MA 4 22 | #define DRIVE_STRENGTH_8MA 8 23 | #define DRIVE_STRENGTH_12MA 12 24 | 25 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 26 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022 Xilinx, Inc. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 7 | #define _DT_BINDINGS_VERSAL_REGNODE_H 8 | 9 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 10 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 11 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 12 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 13 | 14 | #endif 15 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018 Xilinx, Inc. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 7 | #define _DT_BINDINGS_ZYNQMP_POWER_H 8 | 9 | #define PD_RPU 6 10 | #define PD_RPU_0 7 11 | #define PD_RPU_1 8 12 | #define PD_OCM_0 11 13 | #define PD_OCM_1 12 14 | #define PD_OCM_2 13 15 | #define PD_OCM_3 14 16 | #define PD_TCM_0_A 15 17 | #define PD_TCM_0_B 16 18 | #define PD_TCM_1_A 17 19 | #define PD_TCM_1_B 18 20 | #define PD_USB_0 22 21 | #define PD_USB_1 23 22 | #define PD_TTC_0 24 23 | #define PD_TTC_1 25 24 | #define PD_TTC_2 26 25 | #define PD_TTC_3 27 26 | #define PD_SATA 28 27 | #define PD_ETH_0 29 28 | #define PD_ETH_1 30 29 | #define PD_ETH_2 31 30 | #define PD_ETH_3 32 31 | #define PD_UART_0 33 32 | #define PD_UART_1 34 33 | #define PD_SPI_0 35 34 | #define PD_SPI_1 36 35 | #define PD_I2C_0 37 36 | #define PD_I2C_1 38 37 | #define PD_SD_0 39 38 | #define PD_SD_1 40 39 | #define PD_DP 41 40 | #define PD_GDMA 42 41 | #define PD_ADMA 43 42 | #define PD_NAND 44 43 | #define PD_QSPI 45 44 | #define PD_GPIO 46 45 | #define PD_CAN_0 47 46 | #define PD_CAN_1 48 47 | #define PD_GPU 58 48 | #define PD_PCIE 59 49 | #define PD_PL 69 50 | 51 | #endif 52 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2022.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/vcu118-rev2.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-property/ pcs-handle ; 4 | /delete-property/ managed ; 5 | /delete-property/ xlnx,switch-x-sgmii ; 6 | /delete-node/ mdio; 7 | axi_ethernet_mdio: mdio { 8 | #address-cells = <1>; 9 | #size-cells = <0>; 10 | phy0: phy@3 { 11 | device_type = "ethernet-phy"; 12 | ti,sgmii-ref-clock-output-enable; 13 | ti,dp83867-rxctrl-strap-quirk; 14 | ti,rx-internal-delay = <0x8>; 15 | ti,tx-internal-delay = <0xa>; 16 | ti,fifo-depth = <0x1>; 17 | reg = <3>; 18 | }; 19 | }; 20 | }; 21 | 22 | &axi_iic_0 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | i2c-mux@75 { 26 | compatible = "nxp,pca9548"; 27 | #address-cells = <1>; 28 | #size-cells = <0>; 29 | reg = <0x75>; 30 | i2c@3 { 31 | #address-cells = <1>; 32 | #size-cells = <0>; 33 | reg = <3>; 34 | eeprom@54 { 35 | compatible = "atmel,24c08"; 36 | reg = <0x54>; 37 | }; 38 | }; 39 | }; 40 | i2c-mux@74 { 41 | compatible = "nxp,pca9548"; 42 | #address-cells = <1>; 43 | #size-cells = <0>; 44 | reg = <0x74>; 45 | i2c@0 { 46 | #address-cells = <1>; 47 | #size-cells = <0>; 48 | reg = <0>; 49 | si570: clock-generator@5d { 50 | #clock-cells = <0>; 51 | compatible = "silabs,si570"; 52 | temperature-stability = <50>; 53 | reg = <0x5d>; 54 | factory-fout = <156250000>; 55 | clock-frequency = <148500000>; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | }; 15 | 16 | &i2c0 { 17 | /* Access via J70/J71 or J82/J83 */ 18 | clock-frequency = <100000>; 19 | }; 20 | 21 | &i2c1 { 22 | /* Access via J70/J71 or J82/J83 */ 23 | /* By default this bus should have eeprom for board identification at 0x54 */ 24 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 25 | clock-frequency = <100000>; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-v350-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal v350 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | 13 | / { 14 | compatible = "xlnx,versal-v350-revA", "xlnx,versal"; 15 | model = "Xilinx Versal v350 board revA"; 16 | 17 | chosen { 18 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | aliases { 23 | serial0 = &serial0; 24 | serial1 = &serial1; 25 | spi0 = &ospi; 26 | }; 27 | }; 28 | 29 | &dcc { 30 | status = "okay"; 31 | }; 32 | 33 | &ospi { 34 | bus-num = <2>; 35 | num-cs = <1>; 36 | #address-cells = <1>; 37 | #size-cells = <0>; 38 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 39 | 40 | flash@0 { 41 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 42 | reg = <0>; 43 | #address-cells = <0x1>; 44 | #size-cells = <0x1>; 45 | cdns,read-delay = <0x0>; 46 | cdns,tshsl-ns = <0x0>; 47 | cdns,tsd2d-ns = <0x0>; 48 | cdns,tchsh-ns = <0x1>; 49 | cdns,tslch-ns = <0x1>; 50 | spi-tx-bus-width = <8>; 51 | spi-rx-bus-width = <8>; 52 | spi-max-frequency = <20000000>; 53 | partition@0 { 54 | label = "spi0-flash0"; 55 | reg = <0x0 0x8000000>; 56 | }; 57 | }; 58 | }; 59 | 60 | &serial1 { 61 | status = "disabled"; 62 | }; 63 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | }; 18 | 19 | &dcc { 20 | status = "okay"; 21 | }; 22 | 23 | &sdhci0 { 24 | no-1-8-v; 25 | }; 26 | 27 | &sdhci1 { 28 | no-1-8-v; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck5000-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck5000 revA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck5000 board revA"; 16 | 17 | chosen { 18 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | aliases { 23 | serial0 = &serial0; 24 | serial1 = &serial1; 25 | spi0 = &ospi; 26 | }; 27 | 28 | }; 29 | 30 | &ospi { 31 | bus-num = <2>; 32 | num-cs = <1>; 33 | #address-cells = <1>; 34 | #size-cells = <0>; 35 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 36 | 37 | flash@0 { 38 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 39 | reg = <0>; 40 | #address-cells = <0x1>; 41 | #size-cells = <0x1>; 42 | cdns,read-delay = <0x0>; 43 | cdns,tshsl-ns = <0x0>; 44 | cdns,tsd2d-ns = <0x0>; 45 | cdns,tchsh-ns = <0x1>; 46 | cdns,tslch-ns = <0x1>; 47 | spi-tx-bus-width = <8>; 48 | spi-rx-bus-width = <8>; 49 | spi-max-frequency = <20000000>; 50 | partition@0 { 51 | label = "spi0-flash0"; 52 | reg = <0x0 0x10000000>; 53 | }; 54 | }; 55 | }; 56 | 57 | &dcc { 58 | status = "okay"; 59 | }; 60 | 61 | &serial1 { 62 | status = "disabled"; 63 | }; 64 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | is-dual = <1>; 17 | flash@0 { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 21 | reg = <0>, <1>; 22 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 23 | spi-tx-bus-width = <4>; 24 | spi-rx-bus-width = <4>; 25 | spi-max-frequency = <150000000>; 26 | partition@0 { 27 | label = "spi0-flash0"; 28 | reg = <0x0 0x10000000>; 29 | }; 30 | }; 31 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | /* U97 MT35XU02G */ 14 | compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; 15 | bus-num = <2>; 16 | num-cs = <1>; 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; 20 | 21 | flash@0 { 22 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 23 | reg = <0>; 24 | #address-cells = <1>; 25 | #size-cells = <1>; 26 | cdns,read-delay = <0x0>; 27 | cdns,tshsl-ns = <0x0>; 28 | cdns,tsd2d-ns = <0x0>; 29 | cdns,tchsh-ns = <0x1>; 30 | cdns,tslch-ns = <0x1>; 31 | spi-tx-bus-width = <8>; 32 | spi-rx-bus-width = <8>; 33 | spi-max-frequency = <20000000>; 34 | partition@0 { 35 | label = "spi0-flash0"; 36 | reg = <0x0 0x8000000>; 37 | }; 38 | }; 39 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | / { 13 | model = "ZynqMP ZC1254 RevA"; 14 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | serial0 = &uart0; 18 | serial1 = &dcc; 19 | spi0 = &qspi; 20 | }; 21 | }; 22 | 23 | &qspi { 24 | flash@0 { 25 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 26 | #address-cells = <1>; 27 | #size-cells = <1>; 28 | reg = <0x0>; 29 | spi-tx-bus-width = <4>; 30 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 31 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 32 | partition@0 { /* for testing purpose */ 33 | label = "qspi-fsbl-uboot"; 34 | reg = <0x0 0x100000>; 35 | }; 36 | partition@100000 { /* for testing purpose */ 37 | label = "qspi-linux"; 38 | reg = <0x100000 0x500000>; 39 | }; 40 | partition@600000 { /* for testing purpose */ 41 | label = "qspi-device-tree"; 42 | reg = <0x600000 0x20000>; 43 | }; 44 | partition@620000 { /* for testing purpose */ 45 | label = "qspi-rootfs"; 46 | reg = <0x620000 0x5E0000>; 47 | }; 48 | }; 49 | }; 50 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * (C) Copyright 2016-2022 Xilinx, Inc. 5 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zcu102-revb.dtsi" 11 | 12 | / { 13 | model = "ZynqMP ZCU102 Rev1.0"; 14 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15 | }; 16 | 17 | &eeprom { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | 21 | board_sn: board-sn@0 { 22 | reg = <0x0 0x14>; 23 | }; 24 | 25 | eth_mac: eth-mac@20 { 26 | reg = <0x20 0x6>; 27 | }; 28 | 29 | board_name: board-name@d0 { 30 | reg = <0xd0 0x6>; 31 | }; 32 | 33 | board_revision: board-revision@e0 { 34 | reg = <0xe0 0x3>; 35 | }; 36 | }; 37 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 RevB"; 15 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem3 { 19 | phy-handle = <&phyc>; 20 | mdio: mdio { 21 | phyc: ethernet-phy@c { 22 | #phy-cells = <0x1>; 23 | compatible = "ethernet-phy-id2000.a231"; 24 | reg = <0xc>; 25 | ti,rx-internal-delay = <0x8>; 26 | ti,tx-internal-delay = <0xa>; 27 | ti,fifo-depth = <0x1>; 28 | ti,dp83867-rxctrl-strap-quirk; 29 | reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30 | }; 31 | /* Cleanup from RevA */ 32 | /delete-node/ ethernet-phy@21; 33 | }; 34 | }; 35 | 36 | /* Fix collision with u61 */ 37 | &i2c0 { 38 | i2c-mux@75 { 39 | i2c@2 { 40 | max15303@1b { /* u8 */ 41 | compatible = "maxim,max15303"; 42 | reg = <0x1b>; 43 | }; 44 | /delete-node/ max15303@20; 45 | }; 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | / { 13 | model = "ZynqMP ZCU1275 RevA"; 14 | compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", 15 | "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | spi0 = &qspi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | flash@0 { 26 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 27 | #address-cells = <1>; 28 | #size-cells = <1>; 29 | reg = <0x0>; 30 | spi-tx-bus-width = <1>; 31 | spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ 32 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 33 | partition@0 { /* for testing purpose */ 34 | label = "qspi-fsbl-uboot"; 35 | reg = <0x0 0x100000>; 36 | }; 37 | partition@100000 { /* for testing purpose */ 38 | label = "qspi-linux"; 39 | reg = <0x100000 0x500000>; 40 | }; 41 | partition@600000 { /* for testing purpose */ 42 | label = "qspi-device-tree"; 43 | reg = <0x600000 0x20000>; 44 | }; 45 | partition@620000 { /* for testing purpose */ 46 | label = "qspi-rootfs"; 47 | reg = <0x620000 0x5E0000>; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zedboard.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | model = "Zynq Zed Development Board"; 3 | compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 4 | 5 | usb_phy0: phy0@e0002000 { 6 | compatible = "ulpi-phy"; 7 | #phy-cells = <0>; 8 | reg = <0xe0002000 0x1000>; 9 | view-port = <0x0170>; 10 | drv-vbus; 11 | }; 12 | }; 13 | 14 | &clkc { 15 | ps-clk-frequency = <33333333>; 16 | }; 17 | 18 | &gem0 { 19 | phy-handle = <ðernet_phy>; 20 | ethernet_phy: ethernet-phy@0 { 21 | reg = <0>; 22 | device_type = "ethernet-phy"; 23 | }; 24 | }; 25 | 26 | &qspi { 27 | u-boot,dm-pre-reloc; 28 | is-dual = <0>; 29 | num-cs = <1>; 30 | flash@0 { 31 | compatible = "n25q128a11", "jedec,spi-nor"; 32 | reg = <0x0>; 33 | spi-tx-bus-width = <1>; 34 | spi-rx-bus-width = <4>; 35 | spi-max-frequency = <50000000>; 36 | #address-cells = <1>; 37 | #size-cells = <1>; 38 | partition@qspi-fsbl-uboot { 39 | label = "qspi-fsbl-uboot"; 40 | reg = <0x0 0x100000>; 41 | }; 42 | partition@qspi-linux { 43 | label = "qspi-linux"; 44 | reg = <0x100000 0x500000>; 45 | }; 46 | partition@qspi-device-tree { 47 | label = "qspi-device-tree"; 48 | reg = <0x600000 0x20000>; 49 | }; 50 | partition@qspi-rootfs { 51 | label = "qspi-rootfs"; 52 | reg = <0x620000 0x5E0000>; 53 | }; 54 | partition@qspi-bitstream { 55 | label = "qspi-bitstream"; 56 | reg = <0xC00000 0x400000>; 57 | }; 58 | }; 59 | }; 60 | 61 | &sdhci0 { 62 | u-boot,dm-pre-reloc; 63 | }; 64 | 65 | &uart1 { 66 | u-boot,dm-pre-reloc; 67 | }; 68 | 69 | &usb0 { 70 | dr_mode = "host"; 71 | usb-phy = <&usb_phy0>; 72 | }; 73 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynq-zc770-xm011-x16.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * Xilinx ZC770 XM011 board DTS with NAND x16 4 | * 5 | * (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | #include "zynq-zc770-xm011.dtsi" 9 | 10 | / { 11 | model = "Xilinx ZC770 XM011 board (NAND x16)"; 12 | }; 13 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-e-a2197-00-reva.dtsi" 12 | 13 | / { 14 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 15 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 16 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 17 | 18 | /delete-node/ ina226-vcco-500; 19 | /delete-node/ ina226-vcco-501; 20 | /delete-node/ ina226-vcco-502; 21 | }; 22 | 23 | &i2c0 { 24 | i2c-mux@74 { /* u33 */ 25 | i2c@2 { /* PCIE_CLK */ 26 | /delete-node/ clock-generator@6c; 27 | }; 28 | i2c@3 { /* PMBUS2_INA226 */ 29 | /delete-node/ ina226@42; 30 | /delete-node/ ina226@43; 31 | /delete-node/ ina226@44; 32 | }; 33 | }; 34 | }; 35 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-revc.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP Generic System Controller 4 | * 5 | * Copyright (C) 2021-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sc-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP Generic System Controller"; 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ 19 | /delete-node/ mdio; 20 | 21 | mdio: mdio { 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | 25 | phy0: ethernet-phy@1 { /* ADI1300 */ 26 | #phy-cells = <1>; 27 | compatible = "ethernet-phy-id0283.bc30"; 28 | reg = <1>; 29 | adi,rx-internal-delay-ps = <2400>; 30 | adi,tx-internal-delay-ps = <2400>; 31 | adi,fifo-depth-bits = <8>; 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 33 | reset-assert-us = <10>; 34 | reset-deassert-us = <5000>; 35 | }; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA"; 15 | compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/net/mscc-phy-vsc8531.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Device Tree constants for Microsemi VSC8531 PHY 4 | * 5 | * Author: Nagaraju Lakkaraju 6 | * 7 | * Copyright (c) 2017 Microsemi Corporation 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_MSCC_VSC8531_H 11 | #define _DT_BINDINGS_MSCC_VSC8531_H 12 | 13 | /* PHY LED Modes */ 14 | #define VSC8531_LINK_ACTIVITY 0 15 | #define VSC8531_LINK_1000_ACTIVITY 1 16 | #define VSC8531_LINK_100_ACTIVITY 2 17 | #define VSC8531_LINK_10_ACTIVITY 3 18 | #define VSC8531_LINK_100_1000_ACTIVITY 4 19 | #define VSC8531_LINK_10_1000_ACTIVITY 5 20 | #define VSC8531_LINK_10_100_ACTIVITY 6 21 | #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 22 | #define VSC8531_DUPLEX_COLLISION 8 23 | #define VSC8531_COLLISION 9 24 | #define VSC8531_ACTIVITY 10 25 | #define VSC8584_100FX_1000X_ACTIVITY 11 26 | #define VSC8531_AUTONEG_FAULT 12 27 | #define VSC8531_SERIAL_MODE 13 28 | #define VSC8531_FORCE_LED_OFF 14 29 | #define VSC8531_FORCE_LED_ON 15 30 | 31 | #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 32 | #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 33 | #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 34 | #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 35 | #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 36 | #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 37 | #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 38 | #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 8 | #define _DT_BINDINGS_ZYNQMP_POWER_H 9 | 10 | #define PD_RPU 6 11 | #define PD_RPU_0 7 12 | #define PD_RPU_1 8 13 | #define PD_OCM_0 11 14 | #define PD_OCM_1 12 15 | #define PD_OCM_2 13 16 | #define PD_OCM_3 14 17 | #define PD_TCM_0_A 15 18 | #define PD_TCM_0_B 16 19 | #define PD_TCM_1_A 17 20 | #define PD_TCM_1_B 18 21 | #define PD_USB_0 22 22 | #define PD_USB_1 23 23 | #define PD_TTC_0 24 24 | #define PD_TTC_1 25 25 | #define PD_TTC_2 26 26 | #define PD_TTC_3 27 27 | #define PD_SATA 28 28 | #define PD_ETH_0 29 29 | #define PD_ETH_1 30 30 | #define PD_ETH_2 31 31 | #define PD_ETH_3 32 32 | #define PD_UART_0 33 33 | #define PD_UART_1 34 34 | #define PD_SPI_0 35 35 | #define PD_SPI_1 36 36 | #define PD_I2C_0 37 37 | #define PD_I2C_1 38 38 | #define PD_SD_0 39 39 | #define PD_SD_1 40 40 | #define PD_DP 41 41 | #define PD_GDMA 42 42 | #define PD_ADMA 43 43 | #define PD_NAND 44 44 | #define PD_QSPI 45 45 | #define PD_GPIO 46 46 | #define PD_CAN_0 47 47 | #define PD_CAN_1 48 48 | #define PD_GPU 58 49 | #define PD_PCIE 59 50 | #define PD_PL 69 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-versal-net-resets.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2020-2022 Xilinx, Inc. 4 | * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H 8 | #define _DT_BINDINGS_VERSAL_NET_RESETS_H 9 | 10 | #include "xlnx-versal-resets.h" 11 | 12 | #define VERSAL_RST_USB_1 (0xC1040C6U) 13 | 14 | /* Remove Versal specific reset IDs */ 15 | #undef VERSAL_RST_ACPU_0_POR 16 | #undef VERSAL_RST_ACPU_1_POR 17 | #undef VERSAL_RST_OCM2_POR 18 | #undef VERSAL_RST_APU 19 | #undef VERSAL_RST_ACPU_0 20 | #undef VERSAL_RST_ACPU_1 21 | #undef VERSAL_RST_ACPU_L2 22 | #undef VERSAL_RST_RPU_ISLAND 23 | #undef VERSAL_RST_RPU_AMBA 24 | #undef VERSAL_RST_R5_0 25 | #undef VERSAL_RST_R5_1 26 | #undef VERSAL_RST_OCM2_RST 27 | #undef VERSAL_RST_I2C_PMC 28 | #undef VERSAL_RST_I2C_0 29 | #undef VERSAL_RST_I2C_1 30 | #undef VERSAL_RST_SWDT_FPD 31 | #undef VERSAL_RST_SWDT_LPD 32 | #undef VERSAL_RST_USB 33 | #undef VERSAL_RST_DPC 34 | #undef VERSAL_RST_DBG_TRACE 35 | #undef VERSAL_RST_DBG_TSTMP 36 | #undef VERSAL_RST_RPU0_DBG 37 | #undef VERSAL_RST_RPU1_DBG 38 | #undef VERSAL_RST_HSDP 39 | #undef VERSAL_RST_CPMDBG 40 | #undef VERSAL_RST_PCIE_CFG 41 | #undef VERSAL_RST_PCIE_CORE0 42 | #undef VERSAL_RST_PCIE_CORE1 43 | #undef VERSAL_RST_PCIE_DMA 44 | #undef VERSAL_RST_L2_0 45 | #undef VERSAL_RST_L2_1 46 | #undef VERSAL_RST_ADDR_REMAP 47 | #undef VERSAL_RST_CPI0 48 | #undef VERSAL_RST_CPI1 49 | #undef VERSAL_RST_XRAM 50 | #undef VERSAL_RST_AIE_ARRAY 51 | #undef VERSAL_RST_AIE_SHIM 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2023.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/vcu118-rev2.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-property/ pcs-handle ; 4 | /delete-property/ managed ; 5 | /delete-property/ xlnx,switch-x-sgmii ; 6 | /delete-node/ mdio; 7 | axi_ethernet_mdio: mdio { 8 | #address-cells = <1>; 9 | #size-cells = <0>; 10 | phy0: phy@3 { 11 | device_type = "ethernet-phy"; 12 | ti,sgmii-ref-clock-output-enable; 13 | ti,dp83867-rxctrl-strap-quirk; 14 | ti,rx-internal-delay = <0x8>; 15 | ti,tx-internal-delay = <0xa>; 16 | ti,fifo-depth = <0x1>; 17 | reg = <3>; 18 | }; 19 | }; 20 | }; 21 | 22 | &axi_iic_0 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | i2c-mux@75 { 26 | compatible = "nxp,pca9548"; 27 | #address-cells = <1>; 28 | #size-cells = <0>; 29 | reg = <0x75>; 30 | i2c@3 { 31 | #address-cells = <1>; 32 | #size-cells = <0>; 33 | reg = <3>; 34 | eeprom@54 { 35 | compatible = "atmel,24c08"; 36 | reg = <0x54>; 37 | }; 38 | }; 39 | }; 40 | i2c-mux@74 { 41 | compatible = "nxp,pca9548"; 42 | #address-cells = <1>; 43 | #size-cells = <0>; 44 | reg = <0x74>; 45 | i2c@0 { 46 | #address-cells = <1>; 47 | #size-cells = <0>; 48 | reg = <0>; 49 | si570: clock-generator@5d { 50 | #clock-cells = <0>; 51 | compatible = "silabs,si570"; 52 | temperature-stability = <50>; 53 | reg = <0x5d>; 54 | factory-fout = <156250000>; 55 | clock-frequency = <148500000>; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-emb-plus-ve2302-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal Embedded+ VE2302 revA 4 | * 5 | * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "include/dt-bindings/gpio/gpio.h" 11 | 12 | / { 13 | compatible = "xlnx,versal-emb-plus-ve2302-revA", 14 | "xlnx,versal-emb-plus-ve2302", 15 | "xlnx,versal"; 16 | model = "Xilinx Versal Embedded+ VE2302 revA"; 17 | 18 | chosen { 19 | bootargs = "earlycon clk_ignore_unused"; 20 | stdout-path = "serial0:115200"; 21 | }; 22 | 23 | aliases { 24 | serial0 = &serial0; 25 | serial1 = &serial1; 26 | i2c0 = &i2c0; 27 | }; 28 | 29 | /* For extension board */ 30 | onewire { 31 | compatible = "w1-gpio"; 32 | gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; 33 | }; 34 | }; 35 | 36 | &gpio0 { 37 | gpio-line-names = "GPIO_LED2", "GPIO_LED3", "GPIO_LED4", "", "1WIRE", /* 0 - 4 */ 38 | "", "FUSA", "", "EGPIO", "AGPIO", /* 5 - 9 */ 39 | "I2C0_SCL", "I2C0_SDA", "", "", "", /* 10 - 14 */ 40 | "", "", "", "", "", /* 15 - 19 */ 41 | "", "", "", "", "3V3_MON_N", /* 20 - 24 */ 42 | "3V3_MON_P", /* 25, MIO end and EMIO start */ 43 | "", "", "", /* 26 - 29 */ 44 | "", "", "", "", "", /* 30 - 34 */ 45 | "", "", "", "", "", /* 35 - 39 */ 46 | "", "", "", "", "", /* 40 - 44 */ 47 | "", "", "", "", "", /* 45 - 49 */ 48 | "", "", "", "", "", /* 50 - 54 */ 49 | "", "", ""; /* 55 - 57 */ 50 | }; 51 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal NET IPP/SPP OSPI 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-net-ipp-rev1.9.dtsi" 12 | 13 | / { 14 | model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; 15 | }; 16 | 17 | &ospi { 18 | status = "okay"; 19 | }; 20 | 21 | &qspi { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | }; 15 | 16 | &i2c0 { 17 | /* Access via J70/J71 or J82/J83 */ 18 | clock-frequency = <100000>; 19 | }; 20 | 21 | &i2c1 { 22 | /* Access via J70/J71 or J82/J83 */ 23 | /* By default this bus should have eeprom for board identification at 0x54 */ 24 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 25 | clock-frequency = <100000>; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-v350-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal v350 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | 13 | / { 14 | compatible = "xlnx,versal-v350-revA", "xlnx,versal"; 15 | model = "Xilinx Versal v350 board revA"; 16 | 17 | chosen { 18 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | aliases { 23 | serial0 = &serial0; 24 | serial1 = &serial1; 25 | serial2 = &dcc; 26 | spi0 = &ospi; 27 | }; 28 | }; 29 | 30 | &dcc { 31 | status = "okay"; 32 | }; 33 | 34 | &ospi { 35 | bus-num = <2>; 36 | num-cs = <1>; 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | 40 | flash@0 { 41 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 42 | reg = <0>; 43 | #address-cells = <0x1>; 44 | #size-cells = <0x1>; 45 | cdns,read-delay = <0x0>; 46 | cdns,tshsl-ns = <0x0>; 47 | cdns,tsd2d-ns = <0x0>; 48 | cdns,tchsh-ns = <0x1>; 49 | cdns,tslch-ns = <0x1>; 50 | spi-tx-bus-width = <8>; 51 | spi-rx-bus-width = <8>; 52 | spi-max-frequency = <20000000>; 53 | no-wp; 54 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 55 | partition@0 { 56 | label = "spi0-flash0"; 57 | reg = <0x0 0x8000000>; 58 | }; 59 | }; 60 | }; 61 | 62 | &serial1 { 63 | status = "disabled"; 64 | }; 65 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | status = "disabled"; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | / { 12 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 13 | "xlnx,versal-vc-p-a2197-00", 14 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 15 | model = "Xilinx Versal A2197 Processor board revA"; 16 | 17 | aliases { 18 | serial2 = &dcc; 19 | }; 20 | }; 21 | 22 | &dcc { 23 | status = "okay"; 24 | }; 25 | 26 | &sdhci0 { 27 | no-1-8-v; 28 | }; 29 | 30 | &sdhci1 { 31 | no-1-8-v; 32 | }; 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 14 | "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VCK190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck5000-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck5000 revA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck5000 board revA"; 16 | 17 | chosen { 18 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 19 | stdout-path = "serial0:115200"; 20 | }; 21 | 22 | aliases { 23 | serial0 = &serial0; 24 | serial1 = &serial1; 25 | serial2 = &dcc; 26 | spi0 = &ospi; 27 | }; 28 | 29 | }; 30 | 31 | &ospi { 32 | bus-num = <2>; 33 | num-cs = <1>; 34 | #address-cells = <1>; 35 | #size-cells = <0>; 36 | 37 | flash@0 { 38 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 39 | reg = <0>; 40 | #address-cells = <0x1>; 41 | #size-cells = <0x1>; 42 | cdns,read-delay = <0x0>; 43 | cdns,tshsl-ns = <0x0>; 44 | cdns,tsd2d-ns = <0x0>; 45 | cdns,tchsh-ns = <0x1>; 46 | cdns,tslch-ns = <0x1>; 47 | spi-tx-bus-width = <8>; 48 | spi-rx-bus-width = <8>; 49 | spi-max-frequency = <20000000>; 50 | no-wp; 51 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 52 | partition@0 { 53 | label = "spi0-flash0"; 54 | reg = <0x0 0x10000000>; 55 | }; 56 | }; 57 | }; 58 | 59 | &dcc { 60 | status = "okay"; 61 | }; 62 | 63 | &serial1 { 64 | status = "disabled"; 65 | }; 66 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-rev1.1.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 16 | }; 17 | 18 | &ospi { 19 | #include "versal-x-ebm-03-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 16 | }; 17 | 18 | &qspi { 19 | #include "versal-x-ebm-01-reva.dtsi" 20 | }; 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | #include "versal-vmk180-reva.dtsi" 11 | 12 | / { 13 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 14 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 16 | 17 | aliases { 18 | spi0 = &ospi; 19 | }; 20 | }; 21 | 22 | &ospi { 23 | #include "versal-x-ebm-03-reva.dtsi" 24 | }; 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | bus-width = <8>; 15 | xlnx,mio-bank = <0>; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | /* U97 MT35XU02G */ 14 | compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; 15 | bus-num = <2>; 16 | num-cs = <1>; 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | 20 | flash@0 { 21 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 22 | reg = <0>; 23 | #address-cells = <1>; 24 | #size-cells = <1>; 25 | cdns,read-delay = <0x0>; 26 | cdns,tshsl-ns = <0x0>; 27 | cdns,tsd2d-ns = <0x0>; 28 | cdns,tchsh-ns = <0x1>; 29 | cdns,tslch-ns = <0x1>; 30 | spi-tx-bus-width = <8>; 31 | spi-rx-bus-width = <8>; 32 | spi-max-frequency = <20000000>; 33 | no-wp; 34 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 35 | partition@0 { 36 | label = "spi0-flash0"; 37 | reg = <0x0 0x8000000>; 38 | }; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | / { 13 | model = "ZynqMP ZC1254 RevA"; 14 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 15 | 16 | aliases { 17 | serial0 = &uart0; 18 | serial1 = &dcc; 19 | spi0 = &qspi; 20 | }; 21 | }; 22 | 23 | &qspi { 24 | flash@0 { 25 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 26 | #address-cells = <1>; 27 | #size-cells = <1>; 28 | reg = <0x0>; 29 | spi-tx-bus-width = <4>; 30 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 31 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 32 | partition@0 { /* for testing purpose */ 33 | label = "qspi-fsbl-uboot"; 34 | reg = <0x0 0x100000>; 35 | }; 36 | partition@100000 { /* for testing purpose */ 37 | label = "qspi-linux"; 38 | reg = <0x100000 0x500000>; 39 | }; 40 | partition@600000 { /* for testing purpose */ 41 | label = "qspi-device-tree"; 42 | reg = <0x600000 0x20000>; 43 | }; 44 | partition@620000 { /* for testing purpose */ 45 | label = "qspi-rootfs"; 46 | reg = <0x620000 0x5E0000>; 47 | }; 48 | }; 49 | }; 50 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * (C) Copyright 2016-2022 Xilinx, Inc. 5 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zcu102-revb.dtsi" 11 | 12 | / { 13 | model = "ZynqMP ZCU102 Rev1.0"; 14 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15 | }; 16 | 17 | &eeprom { 18 | #address-cells = <1>; 19 | #size-cells = <1>; 20 | 21 | board_sn: board-sn@0 { 22 | reg = <0x0 0x14>; 23 | }; 24 | 25 | eth_mac: eth-mac@20 { 26 | reg = <0x20 0x6>; 27 | }; 28 | 29 | board_name: board-name@d0 { 30 | reg = <0xd0 0x6>; 31 | }; 32 | 33 | board_revision: board-revision@e0 { 34 | reg = <0xe0 0x3>; 35 | }; 36 | }; 37 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 RevB"; 15 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem3 { 19 | phy-handle = <&phyc>; 20 | mdio: mdio { 21 | phyc: ethernet-phy@c { 22 | #phy-cells = <0x1>; 23 | compatible = "ethernet-phy-id2000.a231"; 24 | reg = <0xc>; 25 | ti,rx-internal-delay = <0x8>; 26 | ti,tx-internal-delay = <0xa>; 27 | ti,fifo-depth = <0x1>; 28 | ti,dp83867-rxctrl-strap-quirk; 29 | reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30 | }; 31 | /* Cleanup from RevA */ 32 | /delete-node/ ethernet-phy@21; 33 | }; 34 | }; 35 | 36 | /* Fix collision with u61 */ 37 | &i2c0 { 38 | i2c-mux@75 { 39 | i2c@2 { 40 | max15303@1b { /* u8 */ 41 | compatible = "maxim,max15303"; 42 | reg = <0x1b>; 43 | }; 44 | /delete-node/ max15303@20; 45 | }; 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1275-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU1275 4 | * 5 | * (C) Copyright 2017-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | / { 13 | model = "ZynqMP ZCU1275 RevA"; 14 | compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", 15 | "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | spi0 = &qspi; 21 | }; 22 | }; 23 | 24 | &qspi { 25 | flash@0 { 26 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 27 | #address-cells = <1>; 28 | #size-cells = <1>; 29 | reg = <0x0>; 30 | spi-tx-bus-width = <1>; 31 | spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ 32 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 33 | partition@0 { /* for testing purpose */ 34 | label = "qspi-fsbl-uboot"; 35 | reg = <0x0 0x100000>; 36 | }; 37 | partition@100000 { /* for testing purpose */ 38 | label = "qspi-linux"; 39 | reg = <0x100000 0x500000>; 40 | }; 41 | partition@600000 { /* for testing purpose */ 42 | label = "qspi-device-tree"; 43 | reg = <0x600000 0x20000>; 44 | }; 45 | partition@620000 { /* for testing purpose */ 46 | label = "qspi-rootfs"; 47 | reg = <0x620000 0x5E0000>; 48 | }; 49 | }; 50 | }; 51 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zedboard.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | model = "Zynq Zed Development Board"; 3 | compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; 4 | 5 | usb_phy0: phy0@e0002000 { 6 | compatible = "ulpi-phy"; 7 | #phy-cells = <0>; 8 | reg = <0xe0002000 0x1000>; 9 | view-port = <0x0170>; 10 | drv-vbus; 11 | }; 12 | }; 13 | 14 | &clkc { 15 | ps-clk-frequency = <33333333>; 16 | }; 17 | 18 | &gem0 { 19 | phy-handle = <ðernet_phy>; 20 | ethernet_phy: ethernet-phy@0 { 21 | reg = <0>; 22 | device_type = "ethernet-phy"; 23 | }; 24 | }; 25 | 26 | &qspi { 27 | bootph-all; 28 | num-cs = <1>; 29 | flash@0 { 30 | compatible = "n25q128a11", "jedec,spi-nor"; 31 | reg = <0x0>; 32 | spi-tx-bus-width = <1>; 33 | spi-rx-bus-width = <4>; 34 | spi-max-frequency = <50000000>; 35 | #address-cells = <1>; 36 | #size-cells = <1>; 37 | partition@qspi-fsbl-uboot { 38 | label = "qspi-fsbl-uboot"; 39 | reg = <0x0 0x100000>; 40 | }; 41 | partition@qspi-linux { 42 | label = "qspi-linux"; 43 | reg = <0x100000 0x500000>; 44 | }; 45 | partition@qspi-device-tree { 46 | label = "qspi-device-tree"; 47 | reg = <0x600000 0x20000>; 48 | }; 49 | partition@qspi-rootfs { 50 | label = "qspi-rootfs"; 51 | reg = <0x620000 0x5E0000>; 52 | }; 53 | partition@qspi-bitstream { 54 | label = "qspi-bitstream"; 55 | reg = <0xC00000 0x400000>; 56 | }; 57 | }; 58 | }; 59 | 60 | &sdhci0 { 61 | bootph-all; 62 | }; 63 | 64 | &uart1 { 65 | bootph-all; 66 | }; 67 | 68 | &usb0 { 69 | dr_mode = "host"; 70 | usb-phy = <&usb_phy0>; 71 | }; 72 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynq-zc770-xm011-x16.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * Xilinx ZC770 XM011 board DTS with NAND x16 4 | * 5 | * (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | #include "zynq-zc770-xm011.dtsi" 9 | 10 | / { 11 | model = "Xilinx ZC770 XM011 board (NAND x16)"; 12 | }; 13 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-e-a2197-00-reva.dtsi" 12 | 13 | / { 14 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 15 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 16 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 17 | 18 | /delete-node/ ina226-vcco-500; 19 | /delete-node/ ina226-vcco-501; 20 | /delete-node/ ina226-vcco-502; 21 | }; 22 | 23 | &i2c0 { 24 | i2c-mux@74 { /* u33 */ 25 | i2c@2 { /* PCIE_CLK */ 26 | /delete-node/ clock-generator@6c; 27 | }; 28 | i2c@3 { /* PMBUS2_INA226 */ 29 | /delete-node/ ina226@42; 30 | /delete-node/ ina226@43; 31 | /delete-node/ ina226@44; 32 | }; 33 | }; 34 | }; 35 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-revc.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP Generic System Controller 4 | * 5 | * Copyright (C) 2021-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sc-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP Generic System Controller"; 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ 19 | /delete-node/ mdio; 20 | 21 | mdio: mdio { 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | 25 | phy0: ethernet-phy@1 { /* ADI1300 */ 26 | #phy-cells = <1>; 27 | compatible = "ethernet-phy-id0283.bc30"; 28 | reg = <1>; 29 | adi,rx-internal-delay-ps = <2400>; 30 | adi,tx-internal-delay-ps = <2400>; 31 | adi,fifo-depth-bits = <8>; 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 33 | reset-assert-us = <10>; 34 | reset-deassert-us = <5000>; 35 | }; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | }; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A 4 | * 5 | * (C) Copyright 2021-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 16 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 17 | "xlnx,zynqmp"; 18 | }; 19 | 20 | &sdhci0 { 21 | status = "disabled"; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/net/mscc-phy-vsc8531.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Device Tree constants for Microsemi VSC8531 PHY 4 | * 5 | * Author: Nagaraju Lakkaraju 6 | * 7 | * Copyright (c) 2017 Microsemi Corporation 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_MSCC_VSC8531_H 11 | #define _DT_BINDINGS_MSCC_VSC8531_H 12 | 13 | /* PHY LED Modes */ 14 | #define VSC8531_LINK_ACTIVITY 0 15 | #define VSC8531_LINK_1000_ACTIVITY 1 16 | #define VSC8531_LINK_100_ACTIVITY 2 17 | #define VSC8531_LINK_10_ACTIVITY 3 18 | #define VSC8531_LINK_100_1000_ACTIVITY 4 19 | #define VSC8531_LINK_10_1000_ACTIVITY 5 20 | #define VSC8531_LINK_10_100_ACTIVITY 6 21 | #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 22 | #define VSC8531_DUPLEX_COLLISION 8 23 | #define VSC8531_COLLISION 9 24 | #define VSC8531_ACTIVITY 10 25 | #define VSC8584_100FX_1000X_ACTIVITY 11 26 | #define VSC8531_AUTONEG_FAULT 12 27 | #define VSC8531_SERIAL_MODE 13 28 | #define VSC8531_FORCE_LED_OFF 14 29 | #define VSC8531_FORCE_LED_ON 15 30 | 31 | #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 32 | #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 33 | #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 34 | #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 35 | #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 36 | #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 37 | #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 38 | #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This header provides constants for the phy framework 4 | * 5 | * Copyright (C) 2014 STMicroelectronics 6 | * Author: Gabriel Fernandez 7 | * License terms: GNU General Public License (GPL), version 2 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PHY 11 | #define _DT_BINDINGS_PHY 12 | 13 | #define PHY_NONE 0 14 | #define PHY_TYPE_SATA 1 15 | #define PHY_TYPE_PCIE 2 16 | #define PHY_TYPE_USB2 3 17 | #define PHY_TYPE_USB3 4 18 | #define PHY_TYPE_UFS 5 19 | #define PHY_TYPE_DP 6 20 | #define PHY_TYPE_XPCS 7 21 | #define PHY_TYPE_SGMII 8 22 | #define PHY_TYPE_QSGMII 9 23 | 24 | #endif /* _DT_BINDINGS_PHY */ 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | /* Bit values for Pin drive strength */ 21 | #define DRIVE_STRENGTH_2MA 2 22 | #define DRIVE_STRENGTH_4MA 4 23 | #define DRIVE_STRENGTH_8MA 8 24 | #define DRIVE_STRENGTH_12MA 12 25 | 26 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022-2022 Xilinx, Inc. 4 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018-2022 Xilinx, Inc. 4 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 8 | #define _DT_BINDINGS_ZYNQMP_POWER_H 9 | 10 | #define PD_RPU 6 11 | #define PD_RPU_0 7 12 | #define PD_RPU_1 8 13 | #define PD_OCM_0 11 14 | #define PD_OCM_1 12 15 | #define PD_OCM_2 13 16 | #define PD_OCM_3 14 17 | #define PD_TCM_0_A 15 18 | #define PD_TCM_0_B 16 19 | #define PD_TCM_1_A 17 20 | #define PD_TCM_1_B 18 21 | #define PD_USB_0 22 22 | #define PD_USB_1 23 23 | #define PD_TTC_0 24 24 | #define PD_TTC_1 25 25 | #define PD_TTC_2 26 26 | #define PD_TTC_3 27 27 | #define PD_SATA 28 28 | #define PD_ETH_0 29 29 | #define PD_ETH_1 30 30 | #define PD_ETH_2 31 31 | #define PD_ETH_3 32 32 | #define PD_UART_0 33 33 | #define PD_UART_1 34 34 | #define PD_SPI_0 35 35 | #define PD_SPI_1 36 36 | #define PD_I2C_0 37 37 | #define PD_I2C_1 38 38 | #define PD_SD_0 39 39 | #define PD_SD_1 40 40 | #define PD_DP 41 41 | #define PD_GDMA 42 42 | #define PD_ADMA 43 43 | #define PD_NAND 44 44 | #define PD_QSPI 45 45 | #define PD_GPIO 46 46 | #define PD_CAN_0 47 47 | #define PD_CAN_1 48 48 | #define PD_GPU 58 49 | #define PD_PCIE 59 50 | #define PD_PL 69 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-versal-net-resets.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2020-2022 Xilinx, Inc. 4 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H 8 | #define _DT_BINDINGS_VERSAL_NET_RESETS_H 9 | 10 | #include "xlnx-versal-resets.h" 11 | 12 | #define VERSAL_RST_USB_1 (0xC1040C6U) 13 | 14 | /* Remove Versal specific reset IDs */ 15 | #undef VERSAL_RST_ACPU_0_POR 16 | #undef VERSAL_RST_ACPU_1_POR 17 | #undef VERSAL_RST_OCM2_POR 18 | #undef VERSAL_RST_APU 19 | #undef VERSAL_RST_ACPU_0 20 | #undef VERSAL_RST_ACPU_1 21 | #undef VERSAL_RST_ACPU_L2 22 | #undef VERSAL_RST_RPU_ISLAND 23 | #undef VERSAL_RST_RPU_AMBA 24 | #undef VERSAL_RST_R5_0 25 | #undef VERSAL_RST_R5_1 26 | #undef VERSAL_RST_OCM2_RST 27 | #undef VERSAL_RST_I2C_PMC 28 | #undef VERSAL_RST_I2C_0 29 | #undef VERSAL_RST_I2C_1 30 | #undef VERSAL_RST_SWDT_FPD 31 | #undef VERSAL_RST_SWDT_LPD 32 | #undef VERSAL_RST_USB 33 | #undef VERSAL_RST_DPC 34 | #undef VERSAL_RST_DBG_TRACE 35 | #undef VERSAL_RST_DBG_TSTMP 36 | #undef VERSAL_RST_RPU0_DBG 37 | #undef VERSAL_RST_RPU1_DBG 38 | #undef VERSAL_RST_HSDP 39 | #undef VERSAL_RST_CPMDBG 40 | #undef VERSAL_RST_PCIE_CFG 41 | #undef VERSAL_RST_PCIE_CORE0 42 | #undef VERSAL_RST_PCIE_CORE1 43 | #undef VERSAL_RST_PCIE_DMA 44 | #undef VERSAL_RST_L2_0 45 | #undef VERSAL_RST_L2_1 46 | #undef VERSAL_RST_ADDR_REMAP 47 | #undef VERSAL_RST_CPI0 48 | #undef VERSAL_RST_CPI1 49 | #undef VERSAL_RST_XRAM 50 | #undef VERSAL_RST_AIE_ARRAY 51 | #undef VERSAL_RST_AIE_SHIM 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.1/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /dfeccf/data/dfeccf.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfeccf_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set count 0 19 | foreach handle [hsi::get_cells -hier] { 20 | set ip_name [hsi get_property IP_NAME $handle] 21 | if {[string match -nocase $ip_name "xdfe_cc_filter"] } { 22 | set count [expr $count + 1] 23 | } 24 | } 25 | add_prop $node "num-insts" $count hexlist $dts_file 26 | 27 | set value [hsi get_property "CONFIG.C_SWITCHABLE" $drv_handle] 28 | add_prop $node "xlnx,switchable" $value string $dts_file 1 29 | } 30 | -------------------------------------------------------------------------------- /dfemix/data/dfemix.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfemix_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set count 0 19 | foreach handle [hsi::get_cells -hier] { 20 | set ip_name [hsi get_property IP_NAME $handle] 21 | if {[string match -nocase $ip_name "xdfe_cc_mixer"] } { 22 | set count [expr $count + 1] 23 | } 24 | } 25 | add_prop $node "num-insts" $count hexlist $dts_file 26 | 27 | set value [hsi get_property "CONFIG.C_MODE" $drv_handle] 28 | if {[string compare -nocase "downlink" $value] == 0} { 29 | set value 0 30 | } elseif {[string compare -nocase "uplink" $value] == 0} { 31 | set value 1 32 | } elseif {[string compare -nocase "switchable" $value] == 0} { 33 | set value 2 34 | } 35 | add_prop $node "xlnx,modeint" $value hexint $dts_file 36 | } -------------------------------------------------------------------------------- /dmaps/data/dmaps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc dmaps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | set ip [hsi::get_cells -hier $drv_handle] 20 | 21 | set ip_name [get_ip_property $drv_handle IP_NAME] 22 | set req_dma_list "psu_gdma psu_adma psu_csudma" 23 | if {[lsearch -nocase $req_dma_list $ip_name] >= 0} { 24 | set_drv_conf_prop $drv_handle C_DMA_MODE xlnx,dma-type $node int 25 | if {[string match -nocase $ip_name "psu_csudma"]} { 26 | add_prop $node "xlnx,dma-type" 0 int $dts_file 27 | } 28 | } 29 | } 30 | 31 | 32 | -------------------------------------------------------------------------------- /dprx21_core/data/dprx21_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | 17 | proc dprx21_core_generate {drv_handle} { 18 | set node [get_node $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set dts_file [set_drv_def_dts $drv_handle] 23 | set freq [get_clk_pin_freq $drv_handle "S_AXI_ACLK"] 24 | if {[llength $freq] == 0} { 25 | set freq "100000000" 26 | puts "WARNING: Clock frequency information is not available in the design, \ 27 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 28 | If this is incorrect, the peripheral $drv_handle will be non-functional" 29 | } 30 | add_prop "${node}" "xlnx,axi-aclk-freq-mhz" $freq hexint $dts_file 1 31 | 32 | } 33 | -------------------------------------------------------------------------------- /dptx21_core/data/dptx21_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | 17 | proc dptx21_core_generate {drv_handle} { 18 | set node [get_node $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set dts_file [set_drv_def_dts $drv_handle] 23 | set freq [get_clk_pin_freq $drv_handle "S_AXI_ACLK"] 24 | if {[llength $freq] == 0} { 25 | set freq "100000000" 26 | puts "WARNING: Clock frequency information is not available in the design, \ 27 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 28 | If this is incorrect, the peripheral $drv_handle will be non-functional" 29 | } 30 | add_prop "${node}" "xlnx,axi-aclk-freq-mhz" $freq hexint $dts_file 1 31 | 32 | } 33 | -------------------------------------------------------------------------------- /dpu_eu/data/dpu_eu.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc dpu_eu_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"deephi,dpu\"" 22 | } 23 | 24 | 25 | -------------------------------------------------------------------------------- /emaclite/data/emaclite.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc emaclite_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | pldt append $node compatible "\ \, \"xlnx,axi-ethernetlite-3.0\" , \"xlnx,xps-ethernetlite-1.00.a\"" 19 | update_eth_mac_addr $drv_handle 20 | gen_mdio_node $drv_handle $node 21 | } 22 | 23 | -------------------------------------------------------------------------------- /generic/data/generic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generic_generate {drv_handle} { 17 | set hsi_version [get_hsi_version] 18 | set ver [split $hsi_version "."] 19 | set value [lindex $ver 0] 20 | set dts_file [set_drv_def_dts $drv_handle] 21 | if {$value >= 2018} { 22 | set generic_node [get_node $drv_handle] 23 | } 24 | } 25 | 26 | 27 | -------------------------------------------------------------------------------- /globaltimerps/data/globaltimerps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc globaltimerps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /gpiops/data/gpiops.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 3 | # Based on original code: 4 | # (C) Copyright 2007-2014 Michal Simek 5 | # (C) Copyright 2014-2022 Xilinx, Inc. 6 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | # 8 | # Michal SIMEK 9 | # 10 | # This program is free software; you can redistribute it and/or 11 | # modify it under the terms of the GNU General Public License as 12 | # published by the Free Software Foundation; either version 2 of 13 | # the License, or (at your option) any later version. 14 | # 15 | # This program is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | 21 | 22 | proc gpiops_generate {drv_handle} { 23 | set count 32 24 | set dts_file [set_drv_def_dts $drv_handle] 25 | set node [get_node $drv_handle] 26 | set ip [hsi::get_cells -hier $drv_handle] 27 | add_prop $node "emio-gpio-width" [get_ip_param_value $ip C_EMIO_GPIO_WIDTH] hexint $dts_file 28 | set gpiomask [get_ip_param_value $ip "C_MIO_GPIO_MASK"] 29 | 30 | if {[llength $gpiomask]} { 31 | set mask [expr {$gpiomask & 0xffffffff}] 32 | add_prop $node "gpio-mask-low" $mask int $dts_file 33 | set mask [expr {$gpiomask>>$count}] 34 | set mask [expr {$mask & 0xffffffff}] 35 | add_prop $node "gpio-mask-high" "$mask" int $dts_file 36 | } 37 | } 38 | 39 | 40 | -------------------------------------------------------------------------------- /hdmi_ctrl/data/hdmi_ctrl.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_ctrl_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | pldt append $node compatible "\ \, \"xlnx,hdmi_act_ctrl\"" 23 | } 24 | 25 | 26 | -------------------------------------------------------------------------------- /hdmi_rx/data/hdmi_rx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_rx_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /hdmi_rx1/data/hdmi_rx1.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_rx1_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /hdmi_tx/data/hdmi_tx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_tx_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /hdmi_tx1/data/hdmi_tx1.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_tx1_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /i3cpsx/data/i3cpsx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc i3cpsx_generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /iicps/data/iicps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc iicps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | ps7_reset_handle $drv_handle CONFIG.C_I2C_RESET CONFIG.i2c-reset 22 | set_drv_conf_prop $drv_handle C_I2C_CLK_FREQ_HZ xlnx,clock-freq $node int 23 | 24 | } 25 | 26 | 27 | -------------------------------------------------------------------------------- /license.txt: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021 Xilinx, Inc. 3 | # Based on original code: 4 | # (C) Copyright 2007-2014 Michal Simek 5 | # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 6 | # 7 | # Michal SIMEK 8 | # 9 | # This program is free software; you can redistribute it and/or 10 | # modify it under the terms of the GNU General Public License as 11 | # published by the Free Software Foundation; either version 2 of 12 | # the License, or (at your option) any later version. 13 | # 14 | # This program is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | -------------------------------------------------------------------------------- /linear_spi/data/linear_spi.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc linear_spi_generate {drv_handle} { 16 | set baseaddr [get_baseaddr $drv_handle no_prefix] 17 | set memory_node [create_node -n "memory" -l "${drv_handle}_memory" -u $baseaddr -p root -d "system-top.dts"] 18 | add_prop "${memory_node}" "device_type" "memory" string "system-top.dts" 1 19 | set mem_compatible_string [gen_compatible_string $drv_handle] 20 | if {![string_is_empty $mem_compatible_string]} { 21 | add_prop ${memory_node} "compatible" "${mem_compatible_string}-memory" string "system-top.dts" 22 | } 23 | set reg [gen_reg_property $drv_handle "skip_ps_check" 0] 24 | if {![string_is_empty $reg]} { 25 | add_prop "${memory_node}" "reg" $reg hexlist "system-top.dts" 1 26 | } 27 | add_prop "${memory_node}" "xlnx,ip-name" [get_ip_property $drv_handle IP_NAME] string "system-top.dts" 28 | add_prop "${memory_node}" "memory_type" "linear_flash" string "system-top.dts" 29 | } 30 | -------------------------------------------------------------------------------- /mipi_csi2_rx_core/data/mipi_csi2_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_csi2_rx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | #currently nothing is missing 24 | 25 | } 26 | -------------------------------------------------------------------------------- /mipi_csi2_tx_core/data/mipi_csi2_tx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_csi2_tx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | #currently nothing is missing 24 | 25 | } 26 | -------------------------------------------------------------------------------- /mipi_dphy/data/mipi_dphy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_dphy_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set iclk_period [hsi get_property CONFIG.C_TXPLL_CLKIN_PERIOD [hsi::get_cells -hier $drv_handle]] 24 | #add_prop "${node}" "xlnx,txpll-clkin-period" $iclk_period stringlist $dts_file 1 25 | 26 | set dphymode [hsi get_property CONFIG.C_DPHY_MODE [hsi::get_cells -hier $drv_handle]] 27 | if {[string match -nocase "master" $dphymode]} { 28 | add_prop "${node}" "xlnx,dphy-mode" 1 int $dts_file 1 29 | } elseif {[string match -nocase "slave" $dphymode]} { 30 | add_prop "${node}" "xlnx,dphy-mode" 0 int $dts_file 1 31 | } 32 | set highaddr [hsi get_property CONFIG.C_HIGHADDR [hsi get_cells -hier $drv_handle]] 33 | add_prop "${node}" "xlnx,highaddr" $highaddr hexint $dts_file 1 34 | } 35 | -------------------------------------------------------------------------------- /mipi_dsi2_rx_core/data/mipi_dsi2_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc mipi_dsi2_rx_core_generate {drv_handle} { 16 | 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /mipi_dsi_rx_core/data/mipi_dsi_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc mipi_dsi_rx_core_generate {drv_handle} { 16 | 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /mipi_dsi_tx_core/data/mipi_dsi_tx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_dsi_tx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | 24 | } 25 | -------------------------------------------------------------------------------- /mipi_rx_phy/data/mipi_rx_phy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_rx_phy_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | pldt append $node compatible "\ \, \"xlnx,dsi\"" 23 | set phy_mode [hsi get_property CONFIG.C_PHY_MODE [hsi::get_cells -hier $drv_handle]] 24 | puts "phy_mode = $phy_mode" 25 | if {[string match -nocase $phy_mode "dphy"]} { 26 | add_prop "$node" "xlnx,phy-mode" 1 int $dts_file 1 27 | } else { 28 | add_prop "$node" "xlnx,phy-mode" 0 int $dts_file 1 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /mipi_tx_phy/data/mipi_tx_phy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_tx_phy_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | pldt append $node compatible "\ \, \"xlnx,dsi\"" 23 | set phy_mode [hsi get_property CONFIG.C_PHY_MODE [hsi::get_cells -hier $drv_handle]] 24 | puts "phy_mode = $phy_mode" 25 | if {[string match -nocase $phy_mode "dphy"]} { 26 | add_prop "$node" "xlnx,phy-mode" 1 int $dts_file 1 27 | } else { 28 | add_prop "$node" "xlnx,phy-mode" 0 int $dts_file 1 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /norps/data/norps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc norps_generate {drv_handle} { 17 | 18 | # TODO: if addr25 is used, should we consider set the reg size to 64MB? 19 | # enable reg generation for ps ip 20 | gen_reg_property $drv_handle "enable_ps_ip" 21 | } 22 | 23 | 24 | -------------------------------------------------------------------------------- /ocmcps/data/ocmcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ocmcps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /ospips/data/ospips.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ospips_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set_drv_conf_prop $drv_handle C_OSPI_CLK_FREQ_HZ xlnx,clock-freq $node int 19 | set ospi_handle [hsi::get_cells -hier $drv_handle] 20 | set ospi_mode [get_ip_param_value $ospi_handle "C_OSPI_MODE"] 21 | set is_stacked 0 22 | set is_dual 0 23 | if {$ospi_mode == 1} { 24 | set is_stacked 1 25 | } 26 | add_prop $node "is-dual" $is_dual int "pcw.dtsi" 27 | add_prop $node "is-stacked" $is_stacked int "pcw.dtsi" 28 | } 29 | 30 | 31 | -------------------------------------------------------------------------------- /pl310ps/data/pl310ps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc pl310ps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /pr_decoupler/data/pr_decoupler.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc pr_decoupler_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /prc/data/api.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/system-device-tree-xlnx/257621551996a3d51248fd8aa6e9af07f55e01d0/prc/data/api.tcl -------------------------------------------------------------------------------- /ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ptp_1588_timer_syncer_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | set dts_file [set_drv_def_dts $drv_handle] 22 | set compatible [get_comp_str $drv_handle] 23 | set ip_ver [get_comp_ver $drv_handle] 24 | if {[string match -nocase $ip_ver "3.0"] || [string match -nocase $ip_ver "2.0"]} { 25 | set keyval [pldt append $node compatible "\ \, \"xlnx,timer-syncer-1588-3.0\""] 26 | } elseif {[string match -nocase $ip_ver "1.0"]} { 27 | set keyval [pldt append $node compatible "\ \, \"xlnx,timer-syncer-1588-1.0\""] 28 | } 29 | set_drv_prop $drv_handle compatible "$compatible" $node noformating 30 | } 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /scugic/data/scugic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scugic_generate {drv_handle} { 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set proctype [get_hw_family] 19 | set cpm_ip [hsi::get_cells -hier -filter IP_NAME==psv_cpm] 20 | 21 | if {[string match -nocase $proctype "versal"] && \ 22 | [string match -nocase [hsi get_property CONFIG.APU_GIC_ITS_CTL [hsi get_cells -hier $drv_handle]] "0xF9020000"] && \ 23 | [llength $cpm_ip]} { 24 | set node [create_node -n "&gic_its" -d $dts_file -p root] 25 | add_prop $node "status" "okay" string $dts_file 26 | set reg "0x0 0xf9020000 0x0 0x20000" 27 | set_memmap "gic_its" a53 $reg 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /scutimer/data/scutimer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scutimer_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /scuwdt/data/scuwdt.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scuwdt_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /smccps/data/smccps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc smccps_generate {drv_handle} { 17 | set handle [hsi::get_cells -hier -filter {IP_NAME==ps7_smcc}] 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | set reg [get_baseaddr [hsi::get_cells -hier $handle]] 21 | add_prop $node "flashbase" $reg int $dts_file 22 | set bus_width [hsi get_property CONFIG.C_NAND_WIDTH [hsi::get_cells -hier $handle]] 23 | add_prop $node "nand-bus-width" $bus_width int $dts_file 24 | } 25 | 26 | 27 | -------------------------------------------------------------------------------- /spips/data/spips.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc spips_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | set ip [hsi::get_cells -hier $drv_handle] 20 | set cs-num 0 21 | # SPI PS only have chip select range 0 - 2 22 | foreach n {0 1 2} { 23 | set cs_en [hsi get_property CONFIG.C_HAS_SS${n} $ip] 24 | if {[string equal "1" $cs_en]} { 25 | incr cs-num 26 | } 27 | } 28 | if {${cs-num} != 0} { 29 | add_prop $node "num-cs" ${cs-num} int $dts_file 30 | } 31 | 32 | # the is-decoded-cs property is hard coded as we do not know if the 33 | # board has external decoder connected or not 34 | # Once we had the board level information, is-decoded-cs need to be 35 | # generated based on it. 36 | } 37 | 38 | 39 | -------------------------------------------------------------------------------- /sysmon/data/sysmon.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc sysmon_generate {drv_handle} { 16 | set dts_file [set_drv_def_dts $drv_handle] 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | add_prop $node "xlnx,ip-type" 1 hexint $dts_file 22 | } -------------------------------------------------------------------------------- /tmrctr/data/tmrctr.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc tmrctr_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | pldt append $node compatible "\ \, \"xlnx,xps-timer-1.00.a\"" 20 | set proctype [get_hw_family] 21 | if {[regexp "microblaze" $proctype match]} { 22 | gen_dev_ccf_binding $drv_handle "s_axi_aclk" 23 | } else { 24 | set ip [hsi::get_cells -hier $drv_handle] 25 | set clk [hsi::get_pins -of_objects $ip "S_AXI_ACLK"] 26 | if {[llength $clk] } { 27 | set freq [hsi get_property CLK_FREQ $clk] 28 | add_prop $node "clock-frequency" $freq hexint $dts_file 29 | } 30 | } 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /trngpsx/data/trngpsx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc trngpsx_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set pki_trng_baseaddress "0x20400051000" 18 | set pki_trng_offset "0x200" 19 | set pki_num_insts 8 20 | 21 | if {$node == 0} { 22 | return 23 | } 24 | for {set instance 0} {$instance < $pki_num_insts} {incr instance} { 25 | set instance_base_addr [format %lx [expr $pki_trng_baseaddress + [expr {$instance * $pki_trng_offset}]]] 26 | set instance_node_label "psx_pki_trng${instance}" 27 | set trng_node [create_node -l $instance_node_label -n "psx_pki_trng" -u $instance_base_addr -d "pcw.dtsi" -p "&amba"] 28 | add_prop $trng_node "compatible" "xlnx,psx-pmc-trng-11.0" string "pcw.dtsi" 29 | add_prop $trng_node "status" "okay" string "pcw.dtsi" 30 | set reg "0x[string range $instance_base_addr 0 end-8] 0x[string range $instance_base_addr end-7 end] 0x0 0x200" 31 | add_prop $trng_node "reg" $reg hexlist "pcw.dtsi" 32 | set_memmap $instance_node_label a53 $reg 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /ttcps/data/ttcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ttcps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set_drv_conf_prop $drv_handle C_TTC_CLK0_FREQ_HZ xlnx,clock-freq $node int 19 | } 20 | 21 | 22 | -------------------------------------------------------------------------------- /uartns/data/uartns.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 3 | # Based on original code: 4 | # (C) Copyright 2007-2014 Michal Simek 5 | # (C) Copyright 2014-2022 Xilinx, Inc. 6 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 7 | # 8 | # Michal SIMEK 9 | # 10 | # This program is free software; you can redistribute it and/or 11 | # modify it under the terms of the GNU General Public License as 12 | # published by the Free Software Foundation; either version 2 of 13 | # the License, or (at your option) any later version. 14 | # 15 | # This program is distributed in the hope that it will be useful, 16 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | # GNU General Public License for more details. 19 | # 20 | 21 | proc uartns_generate {drv_handle} { 22 | set node [get_node $drv_handle] 23 | set dts_file [set_drv_def_dts $drv_handle] 24 | set ip [hsi::get_cells -hier $drv_handle] 25 | set has_xin [get_ip_param_value $ip C_HAS_EXTERNAL_XIN] 26 | set clock_port "S_AXI_ACLK" 27 | 28 | set freq [get_clk_pin_freq $ip "$clock_port"] 29 | add_prop $node "xlnx,clock-freq" $freq int $dts_file 30 | 31 | set proctype [get_hw_family] 32 | if {[regexp "microblaze" $proctype match]} { 33 | gen_dev_ccf_binding $drv_handle "s_axi_aclk" 34 | } 35 | pldt unset $node "clock-frequency" 36 | } 37 | 38 | 39 | -------------------------------------------------------------------------------- /vtc/data/vtc.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc vtc_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | set dts_file [set_drv_def_dts $drv_handle] 22 | pldt append $node compatible "\ \, \"xlnx,v-tc-6.1\"" 23 | set generate_en [hsi get_property CONFIG.C_GENERATE_EN [hsi::get_cells -hier $drv_handle]] 24 | if {$generate_en == 1} { 25 | add_prop "${node}" "xlnx,generator" boolean $dts_file 26 | } 27 | set detect_en [hsi get_property CONFIG.C_DETECT_EN [hsi::get_cells -hier $drv_handle]] 28 | if {$detect_en == 1} { 29 | add_prop "${node}" "xlnx,detector" boolean $dts_file 30 | } 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /wdtps/data/wdtps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc wdtps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /wdttb/data/wdttb.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc wdttb_generate {drv_handle} { 16 | set dts_file [set_drv_def_dts $drv_handle] 17 | set node [get_node $drv_handle] 18 | #Add a node to enable winwdt examples in PS and PL 19 | add_prop $node "xlnx,winwdt-example" 1 int $dts_file 20 | 21 | if {[string match -nocase $dts_file "pcw.dtsi"]} { 22 | add_prop $node compatible "xlnx,versal-wwdt-1.0 xlnx,versal-wwdt" stringlist $dts_file 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /xadcps/data/xadcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc xadcps_generate {drv_handle} { 17 | } 18 | 19 | --------------------------------------------------------------------------------