├── prc └── data │ └── api.tcl ├── device_tree └── data │ ├── kernel_dtsi │ ├── 2025.1 │ │ ├── zynqmp │ │ │ └── zynqmp-u-boot.dtsi │ │ ├── BOARD │ │ │ ├── zynq-zc770-xm011-x16.dtsi │ │ │ ├── xilinx-versal-net-virt.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-zcu102-rev1.1.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── zynqmp-zcu106-rev1.0.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal2-ve-p-a2112-00-revA-eemi.dtsi │ │ │ ├── versal2-ve-p-a2112-00-reva-eemi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vm-p-m1369-00-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── ac701-full.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── versal2-ve-p-a2112-00-reva.dtsi │ │ │ ├── versal2-ve-p-a2112-00-revA.dtsi │ │ │ └── vcu118-rev2.0.dtsi │ │ ├── include │ │ │ └── dt-bindings │ │ │ │ ├── thermal │ │ │ │ └── thermal.h │ │ │ │ ├── power │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ │ ├── dma │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ │ ├── input │ │ │ │ └── input.h │ │ │ │ ├── interrupt-controller │ │ │ │ ├── arm-gic.h │ │ │ │ └── irq.h │ │ │ │ ├── pinctrl │ │ │ │ └── pinctrl-zynqmp.h │ │ │ │ ├── reset │ │ │ │ └── xlnx-versal2-resets.h │ │ │ │ ├── phy │ │ │ │ └── phy.h │ │ │ │ ├── clock │ │ │ │ └── xlnx-versal2-clk.h │ │ │ │ ├── net │ │ │ │ └── mscc-phy-vsc8531.h │ │ │ │ └── gpio │ │ │ │ └── gpio.h │ │ └── zynq │ │ │ └── skeleton.dtsi │ ├── 2025.2 │ │ ├── zynqmp │ │ │ └── zynqmp-u-boot.dtsi │ │ ├── BOARD │ │ │ ├── zynq-zc770-xm011-x16.dtsi │ │ │ ├── xilinx-versal-net-virt.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-zcu102-rev1.1.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── zynqmp-zcu106-rev1.0.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal2-ve-p-a2112-00-reva-eemi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vm-p-m1369-00-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── ac701-full.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ └── versal2-ve-p-a2112-00-reva.dtsi │ │ ├── include │ │ │ └── dt-bindings │ │ │ │ ├── thermal │ │ │ │ └── thermal.h │ │ │ │ ├── power │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ │ ├── dma │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ │ ├── input │ │ │ │ └── input.h │ │ │ │ ├── interrupt-controller │ │ │ │ ├── arm-gic.h │ │ │ │ └── irq.h │ │ │ │ ├── pinctrl │ │ │ │ └── pinctrl-zynqmp.h │ │ │ │ ├── phy │ │ │ │ └── phy.h │ │ │ │ ├── reset │ │ │ │ └── xlnx-versal2-resets.h │ │ │ │ ├── clock │ │ │ │ └── xlnx-versal2-clk.h │ │ │ │ ├── net │ │ │ │ └── mscc-phy-vsc8531.h │ │ │ │ └── gpio │ │ │ │ └── gpio.h │ │ └── zynq │ │ │ └── skeleton.dtsi │ └── 2024.2 │ │ ├── BOARD │ │ ├── zynq-zc770-xm011-x16.dtsi │ │ ├── xilinx-versal-net-virt.dtsi │ │ ├── kcu105.dtsi │ │ ├── versal-virt.dtsi │ │ ├── kcu105-tmr.dtsi │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ ├── versal-vck190-reva.dtsi │ │ ├── versal-vck190-rev1.1.dtsi │ │ ├── versal-x-ebm-02-reva.dtsi │ │ ├── avnet-ultra96-rev1.dtsi │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ ├── versal-vmk180-rev1.1.dtsi │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ ├── versal-vm-p-m1369-00-reva.dtsi │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ ├── sp701-rev1.0.dtsi │ │ ├── zcu102-rev1.0.dtsi │ │ ├── versal-x-ebm-01-reva.dtsi │ │ ├── ac701-lite.dtsi │ │ ├── ac701-full.dtsi │ │ ├── kc705-full.dtsi │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ ├── kc705-lite.dtsi │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ ├── zynqmp-sc-revc.dtsi │ │ ├── versal-x-ebm-03-reva.dtsi │ │ ├── zcu102-revb.dtsi │ │ ├── vcu118-rev2.0.dtsi │ │ └── zc1254-reva.dtsi │ │ ├── zynq │ │ └── skeleton.dtsi │ │ └── include │ │ └── dt-bindings │ │ ├── power │ │ ├── xlnx-versal-regnode.h │ │ └── xlnx-zynqmp-power.h │ │ ├── dma │ │ └── xlnx-zynqmp-dpdma.h │ │ ├── input │ │ └── input.h │ │ ├── interrupt-controller │ │ ├── arm-gic.h │ │ └── irq.h │ │ ├── pinctrl │ │ └── pinctrl-zynqmp.h │ │ ├── phy │ │ └── phy.h │ │ ├── net │ │ └── mscc-phy-vsc8531.h │ │ └── gpio │ │ └── gpio.h │ ├── config.yaml │ └── parts_spec.tcl ├── i3cpsx └── data │ └── i3cpsx.tcl ├── xadcps └── data │ └── xadcps.tcl ├── apmps └── data │ └── apmps.tcl ├── canps └── data │ └── canps.tcl ├── wdtps └── data │ └── wdtps.tcl ├── devcfg └── data │ └── devcfg.tcl ├── license.txt ├── ocmcps └── data │ └── ocmcps.tcl ├── pl310ps └── data │ └── pl310ps.tcl ├── scuwdt └── data │ └── scuwdt.tcl ├── scutimer └── data │ └── scutimer.tcl ├── axi_sysace └── data │ └── axi_sysace.tcl ├── globaltimerps └── data │ └── globaltimerps.tcl ├── crl_apb └── data │ └── crl_apb.tcl ├── norps └── data │ └── norps.tcl ├── axi_hwicap └── data │ └── axi_hwicap.tcl ├── ttcps └── data │ └── ttcps.tcl ├── axi_i3c └── data │ └── axi_i3c.tcl ├── mipi_dsi2_rx_core └── data │ └── mipi_dsi2_rx_core.tcl ├── mipi_dsi_rx_core └── data │ └── mipi_dsi_rx_core.tcl ├── dfx_axi_shutdown_manager └── data │ └── dfx_axi_shutdown_manager.tcl ├── sysmon └── data │ └── sysmon.tcl ├── dpu_eu └── data │ └── dpu_eu.tcl ├── axi_tft └── data │ └── axi_tft.tcl ├── mipi_dsi_tx_core └── data │ └── mipi_dsi_tx_core.tcl ├── pr_decoupler └── data │ └── pr_decoupler.tcl ├── debug_bridge └── data │ └── debug_bridge.tcl ├── mmi_usb └── data │ └── mmi_usb.tcl ├── axi_fifo_mm_s └── data │ └── axi_fifo_mm_s.tcl ├── mipi_csi2_rx_core └── data │ └── mipi_csi2_rx_core.tcl ├── mipi_csi2_tx_core └── data │ └── mipi_csi2_tx_core.tcl ├── emaclite └── data │ └── emaclite.tcl ├── hdmi_ctrl └── data │ └── hdmi_ctrl.tcl ├── pmcdma └── data │ └── pmcdma.tcl ├── iicps └── data │ └── iicps.tcl ├── generic └── data │ └── generic.tcl ├── wdttb └── data │ └── wdttb.tcl ├── tmr_inject └── data │ └── tmr_inject.tcl ├── tmr_manager └── data │ └── tmr_manager.tcl ├── RM └── data │ └── RM.tcl ├── asu └── data │ └── asu.tcl ├── axi_iic └── data │ └── axi_iic.tcl ├── mipi_rx_phy └── data │ └── mipi_rx_phy.tcl ├── mipi_tx_phy └── data │ └── mipi_tx_phy.tcl ├── smccps └── data │ └── smccps.tcl ├── dmaps └── data │ └── dmaps.tcl ├── axi_usb2_device └── data │ └── axi_usb2_device.tcl ├── dprx21_core └── data │ └── dprx21_core.tcl ├── dptx21_core └── data │ └── dptx21_core.tcl ├── dfeccf └── data │ └── dfeccf.tcl ├── hdmi_rx └── data │ └── hdmi_rx.tcl ├── hdmi_tx └── data │ └── hdmi_tx.tcl ├── dfeofdm └── data │ └── dfeofdm.tcl ├── hdmi_rx1 └── data │ └── hdmi_rx1.tcl ├── hdmi_tx1 └── data │ └── hdmi_tx1.tcl ├── scugic └── data │ └── scugic.tcl ├── dfemix └── data │ └── dfemix.tcl ├── tmrctr └── data │ └── tmrctr.tcl ├── ptp_1588_timer_syncer └── data │ └── ptp_1588_timer_syncer.tcl └── cpu_cortexa9 └── data └── cpu_cortexa9.tcl /prc/data/api.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xilinx/system-device-tree-xlnx/HEAD/prc/data/api.tcl -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/zynqmp/zynqmp-u-boot.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * (C) Copyright 2025, Advanced Micro Devices, Inc. 4 | * 5 | * Michal Simek 6 | */ 7 | 8 | /{ 9 | binman: binman{ 10 | }; 11 | }; 12 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/zynqmp/zynqmp-u-boot.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * (C) Copyright 2025, Advanced Micro Devices, Inc. 4 | * 5 | * Michal Simek 6 | */ 7 | 8 | /{ 9 | binman: binman{ 10 | }; 11 | }; 12 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynq-zc770-xm011-x16.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * Xilinx ZC770 XM011 board DTS with NAND x16 4 | * 5 | * (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | #include "zynq-zc770-xm011.dtsi" 9 | 10 | / { 11 | model = "Xilinx ZC770 XM011 board (NAND x16)"; 12 | }; 13 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynq-zc770-xm011-x16.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * Xilinx ZC770 XM011 board DTS with NAND x16 4 | * 5 | * (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | #include "zynq-zc770-xm011.dtsi" 9 | 10 | / { 11 | model = "Xilinx ZC770 XM011 board (NAND x16)"; 12 | }; 13 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynq-zc770-xm011-x16.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * Xilinx ZC770 XM011 board DTS with NAND x16 4 | * 5 | * (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | #include "zynq-zc770-xm011.dtsi" 9 | 10 | / { 11 | model = "Xilinx ZC770 XM011 board (NAND x16)"; 12 | }; 13 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/xilinx-versal-net-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * Empty device tree for versal-net-virt board 4 | * 5 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | 9 | / { 10 | options { 11 | u-boot { 12 | compatible = "u-boot,config"; 13 | bootscr-address = /bits/ 64 <0x20000000>; 14 | }; 15 | }; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/xilinx-versal-net-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * Empty device tree for versal-net-virt board 4 | * 5 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | 9 | / { 10 | options { 11 | u-boot { 12 | compatible = "u-boot,config"; 13 | bootscr-address = /bits/ 64 <0x20000000>; 14 | }; 15 | }; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/xilinx-versal-net-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * Empty device tree for versal-net-virt board 4 | * 5 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | */ 7 | 8 | 9 | / { 10 | options { 11 | u-boot { 12 | compatible = "u-boot,config"; 13 | bootscr-address = /bits/ 64 <0x20000000>; 14 | }; 15 | }; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 | /* 3 | * Empty device tree for versal-virt board 4 | * 5 | * Copyright 2021 Google LLC 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | 10 | / { 11 | options { 12 | u-boot { 13 | compatible = "u-boot,config"; 14 | bootscr-address = /bits/ 64 <0x20000000>; 15 | }; 16 | }; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 | /* 3 | * Empty device tree for versal-virt board 4 | * 5 | * Copyright 2021 Google LLC 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | 10 | / { 11 | options { 12 | u-boot { 13 | compatible = "u-boot,config"; 14 | bootscr-address = /bits/ 64 <0x20000000>; 15 | }; 16 | }; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/kcu105.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-virt.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 | /* 3 | * Empty device tree for versal-virt board 4 | * 5 | * Copyright 2021 Google LLC 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | 10 | / { 11 | options { 12 | u-boot { 13 | compatible = "u-boot,config"; 14 | bootscr-address = /bits/ 64 <0x20000000>; 15 | }; 16 | }; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/kcu105-tmr.dtsi: -------------------------------------------------------------------------------- 1 | &tmr_0_MB1_axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@75 { 5 | compatible = "nxp,pca9544"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x75>; 9 | i2c@3 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <3>; 13 | eeprom@54 { 14 | compatible = "atmel,24c08"; 15 | reg = <0x54>; 16 | }; 17 | }; 18 | }; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-sc-vek280-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VEK280 revB 4 | * 5 | * (C) Copyright 2022-2024, Advanced Micro Devices, Inc 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | #include "zynqmp-sc-vek280-reva.dtsi" 11 | 12 | &{/} { 13 | compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", 14 | "xlnx,zynqmp-vek280", "xlnx,zynqmp"; 15 | }; 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/thermal/thermal.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for most thermal bindings. 4 | * 5 | * Copyright (C) 2013 Texas Instruments 6 | * Eduardo Valentin 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_THERMAL_THERMAL_H 10 | #define _DT_BINDINGS_THERMAL_THERMAL_H 11 | 12 | /* On cooling devices upper and lower limits */ 13 | #define THERMAL_NO_LIMIT (~0) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/thermal/thermal.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for most thermal bindings. 4 | * 5 | * Copyright (C) 2013 Texas Instruments 6 | * Eduardo Valentin 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_THERMAL_THERMAL_H 10 | #define _DT_BINDINGS_THERMAL_THERMAL_H 11 | 12 | /* On cooling devices upper and lower limits */ 13 | #define THERMAL_NO_LIMIT (~0) 14 | 15 | #endif 16 | 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-zcu102-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.1 4 | * 5 | * (C) Copyright 2016 - 2020, Xilinx, Inc. 6 | * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-rev1.0.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 Rev1.1"; 15 | compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-zcu102-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.1 4 | * 5 | * (C) Copyright 2016 - 2020, Xilinx, Inc. 6 | * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-rev1.0.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 Rev1.1"; 15 | compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board revA"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | no-sd; 15 | no-sdio; 16 | cap-mmc-hw-reset; 17 | bus-width = <8>; 18 | xlnx,mio-bank = <0>; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | no-sd; 15 | no-sdio; 16 | cap-mmc-hw-reset; 17 | bus-width = <8>; 18 | xlnx,mio-bank = <0>; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vck190 Eval board rev1.1"; 16 | }; 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | /* emmc MIO 0-13 - MTFC8GAKAJCN */ 12 | non-removable; 13 | disable-wp; 14 | no-sd; 15 | no-sdio; 16 | cap-mmc-hw-reset; 17 | bus-width = <8>; 18 | xlnx,mio-bank = <0>; 19 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-zcu106-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU106 Rev1.0 4 | * 5 | * (C) Copyright 2016 - 2022, Xilinx, Inc. 6 | * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu106-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU106 Rev1.0"; 15 | compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106-revA", 16 | "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-zcu106-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU106 Rev1.0 4 | * 5 | * (C) Copyright 2016 - 2022, Xilinx, Inc. 6 | * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu106-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU106 Rev1.0"; 15 | compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106-revA", 16 | "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/avnet-ultra96-rev1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Avnet Ultra96 rev1 4 | * 5 | * (C) Copyright 2018-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | #include "zcu100-revc.dtsi" 13 | 14 | / { 15 | model = "Avnet Ultra96 Rev1"; 16 | compatible = "avnet,ultra96-rev1", "avnet,ultra96", 17 | "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", 18 | "xlnx,zynqmp"; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/avnet-ultra96-rev1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Avnet Ultra96 rev1 4 | * 5 | * (C) Copyright 2018-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | #include "zcu100-revc.dtsi" 13 | 14 | / { 15 | model = "Avnet Ultra96 Rev1"; 16 | compatible = "avnet,ultra96-rev1", "avnet,ultra96", 17 | "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", 18 | "xlnx,zynqmp"; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/avnet-ultra96-rev1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Avnet Ultra96 rev1 4 | * 5 | * (C) Copyright 2018-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | #include "zcu100-revc.dtsi" 13 | 14 | / { 15 | model = "Avnet Ultra96 Rev1"; 16 | compatible = "avnet,ultra96-rev1", "avnet,ultra96", 17 | "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", 18 | "xlnx,zynqmp"; 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/power/xlnx-versal-regnode.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL_REGNODE_H 8 | #define _DT_BINDINGS_VERSAL_REGNODE_H 9 | 10 | #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) 11 | #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) 12 | #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) 13 | #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-smk-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k24-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K24 RevA"; 15 | compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 | "xlnx,zynqmp"; 17 | }; 18 | 19 | &sdhci0 { 20 | status = "disabled"; 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 | /* 3 | * Copyright 2019 Laurent Pinchart 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 7 | #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ 8 | 9 | #define ZYNQMP_DPDMA_VIDEO0 0 10 | #define ZYNQMP_DPDMA_VIDEO1 1 11 | #define ZYNQMP_DPDMA_VIDEO2 2 12 | #define ZYNQMP_DPDMA_GRAPHICS 3 13 | #define ZYNQMP_DPDMA_AUDIO0 4 14 | #define ZYNQMP_DPDMA_AUDIO1 5 15 | 16 | #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-sm-k24-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SM-K24 RevA 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SM-K24 RevA/B/1"; 15 | compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 | "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 | "xlnx,zynqmp"; 18 | 19 | }; 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/input/input.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most input bindings. 3 | * 4 | * Most input bindings include key code, matrix key code format. 5 | * In most cases, key code and matrix key code format uses 6 | * the standard values/macro defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INPUT_INPUT_H 10 | #define _DT_BINDINGS_INPUT_INPUT_H 11 | 12 | #include "linux-event-codes.h" 13 | #define MATRIX_KEY(row, col, code) \ 14 | ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) 15 | 16 | #endif /* _DT_BINDINGS_INPUT_INPUT_H */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/input/input.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most input bindings. 3 | * 4 | * Most input bindings include key code, matrix key code format. 5 | * In most cases, key code and matrix key code format uses 6 | * the standard values/macro defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INPUT_INPUT_H 10 | #define _DT_BINDINGS_INPUT_INPUT_H 11 | 12 | #include "linux-event-codes.h" 13 | #define MATRIX_KEY(row, col, code) \ 14 | ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) 15 | 16 | #endif /* _DT_BINDINGS_INPUT_INPUT_H */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/input/input.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most input bindings. 3 | * 4 | * Most input bindings include key code, matrix key code format. 5 | * In most cases, key code and matrix key code format uses 6 | * the standard values/macro defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INPUT_INPUT_H 10 | #define _DT_BINDINGS_INPUT_INPUT_H 11 | 12 | #include "linux-event-codes.h" 13 | #define MATRIX_KEY(row, col, code) \ 14 | ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) 15 | 16 | #endif /* _DT_BINDINGS_INPUT_INPUT_H */ 17 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", 15 | "xlnx,versal-vck190-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board revA (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vck190 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vck190-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; 17 | }; 18 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | 14 | cpu_card { 15 | compatible = "simple-bus"; 16 | #address-cells = <1>; 17 | #size-cells = <1>; 18 | bootph-all; 19 | 20 | timer@0 { 21 | compatible = "snps,arc-timer"; 22 | clocks = <&core_clk>; 23 | reg = <0 1>; 24 | }; 25 | }; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/zynq/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | 14 | cpu_card { 15 | compatible = "simple-bus"; 16 | #address-cells = <1>; 17 | #size-cells = <1>; 18 | bootph-all; 19 | 20 | timer@0 { 21 | compatible = "snps,arc-timer"; 22 | clocks = <&core_clk>; 23 | reg = <0 1>; 24 | }; 25 | }; 26 | }; 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/interrupt-controller/arm-gic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * This header provides constants for the ARM GIC. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8 | 9 | #include "irq.h" 10 | 11 | /* interrupt specifier cell 0 */ 12 | 13 | #define GIC_SPI 0 14 | #define GIC_PPI 1 15 | 16 | /* 17 | * Interrupt specifier cell 2. 18 | * The flags in irq.h are valid, plus those below. 19 | */ 20 | #define GIC_CPU_MASK_RAW(x) ((x) << 8) 21 | #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/interrupt-controller/arm-gic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * This header provides constants for the ARM GIC. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8 | 9 | #include "irq.h" 10 | 11 | /* interrupt specifier cell 0 */ 12 | 13 | #define GIC_SPI 0 14 | #define GIC_PPI 1 15 | 16 | /* 17 | * Interrupt specifier cell 2. 18 | * The flags in irq.h are valid, plus those below. 19 | */ 20 | #define GIC_CPU_MASK_RAW(x) ((x) << 8) 21 | #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/interrupt-controller/arm-gic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * This header provides constants for the ARM GIC. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8 | 9 | #include "irq.h" 10 | 11 | /* interrupt specifier cell 0 */ 12 | 13 | #define GIC_SPI 0 14 | #define GIC_PPI 1 15 | 16 | /* 17 | * Interrupt specifier cell 2. 18 | * The flags in irq.h are valid, plus those below. 19 | */ 20 | #define GIC_CPU_MASK_RAW(x) ((x) << 8) 21 | #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 17 | }; 18 | 19 | &ospi { 20 | #include "versal-x-ebm-03-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020 Xilinx-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 17 | }; 18 | 19 | &ospi { 20 | #include "versal-x-ebm-03-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020 Xilinx-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; 17 | }; 18 | 19 | &qspi { 20 | #include "versal-x-ebm-01-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; 17 | }; 18 | 19 | &ospi { 20 | #include "versal-x-ebm-03-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-rev1.1.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 15 | model = "Xilinx Versal vmk180 Eval board rev1.1"; 16 | }; 17 | 18 | &sdhci1 { /* PMC_MIO26-36/51 */ 19 | clk-phase-sd-hs = <111>, <48>; 20 | clk-phase-uhs-sdr25 = <114>, <48>; 21 | clk-phase-uhs-ddr50 = <126>, <36>; 22 | }; 23 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020 Xilinx-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 11 | 12 | /* Bit value for different voltage levels */ 13 | #define IO_STANDARD_LVCMOS33 0 14 | #define IO_STANDARD_LVCMOS18 1 15 | 16 | /* Bit values for Slew Rates */ 17 | #define SLEW_RATE_FAST 0 18 | #define SLEW_RATE_SLOW 1 19 | 20 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-rev1.1.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", 15 | "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; 17 | }; 18 | 19 | &sdhci1 { 20 | #include "versal-x-ebm-02-reva.dtsi" 21 | }; 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal2-ve-p-a2112-00-revA-eemi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | / { 11 | compatible = "amd,versal2"; 12 | model = "AMD Versal Gen 2 Silicon EL2"; 13 | 14 | chosen { 15 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 16 | stdout-path = "serial0:115200n8"; 17 | }; 18 | }; 19 | 20 | /* GPIO leds/dips/pushPB, SMA to PL */ 21 | &mmi_10gbe { 22 | phy-mode = "10gbase-r"; 23 | fixed-link { 24 | speed = <10000>; 25 | full-duplex; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal2-ve-p-a2112-00-reva-eemi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | / { 11 | compatible = "amd,versal2"; 12 | model = "AMD Versal Gen 2 Silicon EL2"; 13 | 14 | chosen { 15 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 16 | stdout-path = "serial0:115200n8"; 17 | }; 18 | }; 19 | 20 | /* GPIO leds/dips/pushPB, SMA to PL */ 21 | &mmi_10gbe { 22 | phy-mode = "10gbase-r"; 23 | fixed-link { 24 | speed = <10000>; 25 | duplex = "full"; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal2-ve-p-a2112-00-reva-eemi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | / { 11 | compatible = "amd,versal2"; 12 | model = "AMD Versal Gen 2 Silicon EL2"; 13 | 14 | chosen { 15 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 16 | stdout-path = "serial0:115200n8"; 17 | }; 18 | }; 19 | 20 | /* GPIO leds/dips/pushPB, SMA to PL */ 21 | &mmi_10gbe { 22 | phy-mode = "10gbase-r"; 23 | fixed-link { 24 | speed = <10000>; 25 | duplex = "full"; 26 | }; 27 | }; 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 14 | "xlnx,versal-vc-p-a2197-00", 15 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 16 | model = "Xilinx Versal A2197 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vm-p-m1369-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2024-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vm-p-m1369-00-revA", 14 | "xlnx,versal-vm-p-m1369-00", 15 | "xlnx,versal-vm-p-m1369", "xlnx,versal"; 16 | model = "Xilinx Versal m1369 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev2/1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev2", 16 | "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 17 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 18 | "xlnx,zynqmp"; 19 | }; 20 | 21 | &sdhci0 { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most IRQ bindings. 3 | * 4 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 5 | * In most cases, the format of the flags cell uses the standard values 6 | * defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 10 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | 12 | #define IRQ_TYPE_NONE 0 13 | #define IRQ_TYPE_EDGE_RISING 1 14 | #define IRQ_TYPE_EDGE_FALLING 2 15 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 16 | #define IRQ_TYPE_LEVEL_HIGH 4 17 | #define IRQ_TYPE_LEVEL_LOW 8 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 14 | "xlnx,versal-vc-p-a2197-00", 15 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 16 | model = "Xilinx Versal A2197 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vm-p-m1369-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2024-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vm-p-m1369-00-revA", 14 | "xlnx,versal-vm-p-m1369-00", 15 | "xlnx,versal-vm-p-m1369", "xlnx,versal"; 16 | model = "Xilinx Versal m1369 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev2/1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev2", 16 | "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 17 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 18 | "xlnx,zynqmp"; 19 | }; 20 | 21 | &sdhci0 { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most IRQ bindings. 3 | * 4 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 5 | * In most cases, the format of the flags cell uses the standard values 6 | * defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 10 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | 12 | #define IRQ_TYPE_NONE 0 13 | #define IRQ_TYPE_EDGE_RISING 1 14 | #define IRQ_TYPE_EDGE_FALLING 2 15 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 16 | #define IRQ_TYPE_LEVEL_HIGH 4 17 | #define IRQ_TYPE_LEVEL_LOW 8 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vc-p-a2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vc-p-a2197-00-revA", 14 | "xlnx,versal-vc-p-a2197-00", 15 | "xlnx,versal-vc-p-a2197", "xlnx,versal"; 16 | model = "Xilinx Versal A2197 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vm-p-m1369-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal 4 | * 5 | * (C) Copyright 2024-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | 12 | / { 13 | compatible = "xlnx,versal-vm-p-m1369-00-revA", 14 | "xlnx,versal-vm-p-m1369-00", 15 | "xlnx,versal-vm-p-m1369", "xlnx,versal"; 16 | model = "Xilinx Versal m1369 Processor board revA"; 17 | 18 | aliases { 19 | serial2 = &dcc; 20 | }; 21 | 22 | }; 23 | 24 | 25 | &sdhci0 { 26 | no-1-8-v; 27 | }; 28 | 29 | &sdhci1 { 30 | no-1-8-v; 31 | }; 32 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-smk-k26-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sm-k26-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP SMK-K26 Rev2/1/B/A"; 15 | compatible = "xlnx,zynqmp-smk-k26-rev2", 16 | "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", 17 | "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", 18 | "xlnx,zynqmp"; 19 | }; 20 | 21 | &sdhci0 { 22 | status = "disabled"; 23 | }; 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This header provides constants for most IRQ bindings. 3 | * 4 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 5 | * In most cases, the format of the flags cell uses the standard values 6 | * defined in this header. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 10 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | 12 | #define IRQ_TYPE_NONE 0 13 | #define IRQ_TYPE_EDGE_RISING 1 14 | #define IRQ_TYPE_EDGE_FALLING 2 15 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 16 | #define IRQ_TYPE_LEVEL_HIGH 4 17 | #define IRQ_TYPE_LEVEL_LOW 8 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 17 | 18 | aliases { 19 | spi0 = &ospi; 20 | }; 21 | }; 22 | 23 | &ospi { 24 | #include "versal-x-ebm-03-reva.dtsi" 25 | }; 26 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 17 | 18 | aliases { 19 | spi0 = &ospi; 20 | }; 21 | }; 22 | 23 | &ospi { 24 | #include "versal-x-ebm-03-reva.dtsi" 25 | }; 26 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vmk180-reva.dtsi" 12 | 13 | / { 14 | compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", 15 | "xlnx,versal-vmk180-revA", "xlnx,versal"; 16 | model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; 17 | 18 | aliases { 19 | spi0 = &ospi; 20 | }; 21 | }; 22 | 23 | &ospi { 24 | #include "versal-x-ebm-03-reva.dtsi" 25 | }; 26 | -------------------------------------------------------------------------------- /i3cpsx/data/i3cpsx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc i3cpsx_generate {drv_handle} { 17 | } 18 | -------------------------------------------------------------------------------- /xadcps/data/xadcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc xadcps_generate {drv_handle} { 17 | } 18 | 19 | -------------------------------------------------------------------------------- /apmps/data/apmps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc apmps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /canps/data/canps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc canps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /wdtps/data/wdtps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc wdtps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /devcfg/data/devcfg.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc devcfg_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /license.txt: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021 Xilinx, Inc. 3 | # Based on original code: 4 | # (C) Copyright 2007-2014 Michal Simek 5 | # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 6 | # 7 | # Michal SIMEK 8 | # 9 | # This program is free software; you can redistribute it and/or 10 | # modify it under the terms of the GNU General Public License as 11 | # published by the Free Software Foundation; either version 2 of 12 | # the License, or (at your option) any later version. 13 | # 14 | # This program is distributed in the hope that it will be useful, 15 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | # GNU General Public License for more details. 18 | # 19 | -------------------------------------------------------------------------------- /ocmcps/data/ocmcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ocmcps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /pl310ps/data/pl310ps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc pl310ps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /scuwdt/data/scuwdt.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scuwdt_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /scutimer/data/scutimer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scutimer_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /axi_sysace/data/axi_sysace.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_sysace_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | /* Mutually exclusive with qspi */ 25 | 26 | &qspi { 27 | status = "disabled"; 28 | }; 29 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | /* Mutually exclusive with qspi */ 25 | 26 | &qspi { 27 | status = "disabled"; 28 | }; 29 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal X-PRC-04 revA (SE4) 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" 12 | 13 | / { 14 | chosen { 15 | bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; 16 | stdout-path = "serial0:115200"; 17 | }; 18 | 19 | aliases { 20 | spi0 = &ospi; 21 | }; 22 | }; 23 | 24 | /* Mutually exclusive with qspi */ 25 | 26 | &qspi { 27 | status = "disabled"; 28 | }; 29 | -------------------------------------------------------------------------------- /globaltimerps/data/globaltimerps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc globaltimerps_generate {drv_handle} { 17 | } 18 | 19 | 20 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/reset/xlnx-versal2-resets.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022, Xilinx, Inc. 4 | * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL2_RESETS_H 8 | #define _DT_BINDINGS_VERSAL2_RESETS_H 9 | 10 | #include "xlnx-versal-net-resets.h" 11 | 12 | #define VERSAL_RST_UFS (0xC104103U) 13 | #define VERSAL_RST_UFS_PHY (0xC10407CU) 14 | #define VERSAL_RST_DC (0xC104119U) 15 | #define VERSAL_RST_UDH_DRD (0xC10407BU) 16 | #define VERSAL_RST_GPU (0xC10411AU) 17 | #define VERSAL_RST_GPU_RECOV (0xC10411BU) 18 | #define VERSAL_RST_UDH_AUX (0xC10411DU) 19 | #define VERSAL_RST_UDH_DP (0xC10411EU) 20 | #define VERSAL_RST_UDH_HDCPRAM (0xC10411FU) 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /crl_apb/data/crl_apb.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2020-2021 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc crl_apb_generate {drv_handle} { 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | } 19 | 20 | 21 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/sp701-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-node/ mdio; 4 | axi_ethernet_mdio: mdio { 5 | #address-cells = <1>; 6 | #size-cells = <0>; 7 | phy0: phy@1 { 8 | device_type = "ethernet-phy"; 9 | reg = <1>; 10 | ti,rx-internal-delay = <0x3>; 11 | ti,tx-internal-delay = <0x3>; 12 | ti,fifo-depth = <0x1>; 13 | }; 14 | }; 15 | }; 16 | 17 | &axi_iic_0 { 18 | #address-cells = <1>; 19 | #size-cells = <0>; 20 | i2c-mux@75 { 21 | compatible = "nxp,pca9548"; 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | reg = <0x75>; 25 | i2c@0 { 26 | #address-cells = <1>; 27 | #size-cells = <0>; 28 | reg = <0>; 29 | eeprom@50 { 30 | compatible = "atmel,24c08"; 31 | reg = <0x50>; 32 | }; 33 | }; 34 | }; 35 | }; 36 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * 4 | * This header provides constants for the phy framework 5 | * 6 | * Copyright (C) 2014 STMicroelectronics 7 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 8 | * Author: Gabriel Fernandez 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_PHY 12 | #define _DT_BINDINGS_PHY 13 | 14 | #define PHY_NONE 0 15 | #define PHY_TYPE_SATA 1 16 | #define PHY_TYPE_PCIE 2 17 | #define PHY_TYPE_USB2 3 18 | #define PHY_TYPE_USB3 4 19 | #define PHY_TYPE_UFS 5 20 | #define PHY_TYPE_DP 6 21 | #define PHY_TYPE_XPCS 7 22 | #define PHY_TYPE_SGMII 8 23 | #define PHY_TYPE_QSGMII 9 24 | #define PHY_TYPE_DPHY 10 25 | #define PHY_TYPE_CPHY 11 26 | 27 | #endif /* _DT_BINDINGS_PHY */ 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * 4 | * This header provides constants for the phy framework 5 | * 6 | * Copyright (C) 2014 STMicroelectronics 7 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 8 | * Author: Gabriel Fernandez 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_PHY 12 | #define _DT_BINDINGS_PHY 13 | 14 | #define PHY_NONE 0 15 | #define PHY_TYPE_SATA 1 16 | #define PHY_TYPE_PCIE 2 17 | #define PHY_TYPE_USB2 3 18 | #define PHY_TYPE_USB3 4 19 | #define PHY_TYPE_UFS 5 20 | #define PHY_TYPE_DP 6 21 | #define PHY_TYPE_XPCS 7 22 | #define PHY_TYPE_SGMII 8 23 | #define PHY_TYPE_QSGMII 9 24 | #define PHY_TYPE_DPHY 10 25 | #define PHY_TYPE_CPHY 11 26 | 27 | #endif /* _DT_BINDINGS_PHY */ 28 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/phy/phy.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * 4 | * This header provides constants for the phy framework 5 | * 6 | * Copyright (C) 2014 STMicroelectronics 7 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 8 | * Author: Gabriel Fernandez 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_PHY 12 | #define _DT_BINDINGS_PHY 13 | 14 | #define PHY_NONE 0 15 | #define PHY_TYPE_SATA 1 16 | #define PHY_TYPE_PCIE 2 17 | #define PHY_TYPE_USB2 3 18 | #define PHY_TYPE_USB3 4 19 | #define PHY_TYPE_UFS 5 20 | #define PHY_TYPE_DP 6 21 | #define PHY_TYPE_XPCS 7 22 | #define PHY_TYPE_SGMII 8 23 | #define PHY_TYPE_QSGMII 9 24 | #define PHY_TYPE_DPHY 10 25 | #define PHY_TYPE_CPHY 11 26 | 27 | #endif /* _DT_BINDINGS_PHY */ 28 | -------------------------------------------------------------------------------- /norps/data/norps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc norps_generate {drv_handle} { 17 | 18 | # TODO: if addr25 is used, should we consider set the reg size to 64MB? 19 | } 20 | 21 | 22 | -------------------------------------------------------------------------------- /axi_hwicap/data/axi_hwicap.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc axi_hwicap_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | if {$node == 0} { 18 | return 19 | } 20 | 21 | if {[catch {pldt append $node compatible "\ \, \"xlnx,axi-hwicap\""} msg]} {} 22 | } 23 | -------------------------------------------------------------------------------- /device_tree/data/config.yaml: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | --- 16 | dict_devicetree: 17 | kernel_ver: 2025.2 18 | mainline_kernel: none 19 | board_dts: versal-vck190-reva 20 | output_dir: output_dts 21 | zocl: disable 22 | --- 23 | -------------------------------------------------------------------------------- /ttcps/data/ttcps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ttcps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set_drv_conf_prop $drv_handle C_TTC_CLK0_FREQ_HZ xlnx,clock-freq $node int 19 | } 20 | 21 | 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 Rev1.0"; 15 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &eeprom { 19 | #address-cells = <1>; 20 | #size-cells = <1>; 21 | 22 | board_sn: board-sn@0 { 23 | reg = <0x0 0x14>; 24 | }; 25 | 26 | eth_mac: eth-mac@20 { 27 | reg = <0x20 0x6>; 28 | }; 29 | 30 | board_name: board-name@d0 { 31 | reg = <0xd0 0x6>; 32 | }; 33 | 34 | board_revision: board-revision@e0 { 35 | reg = <0xe0 0x3>; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 Rev1.0"; 15 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &eeprom { 19 | #address-cells = <1>; 20 | #size-cells = <1>; 21 | 22 | board_sn: board-sn@0 { 23 | reg = <0x0 0x14>; 24 | }; 25 | 26 | eth_mac: eth-mac@20 { 27 | reg = <0x20 0x6>; 28 | }; 29 | 30 | board_name: board-name@d0 { 31 | reg = <0xd0 0x6>; 32 | }; 33 | 34 | board_revision: board-revision@e0 { 35 | reg = <0xe0 0x3>; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zcu102-rev1.0.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 Rev1.0"; 15 | compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &eeprom { 19 | #address-cells = <1>; 20 | #size-cells = <1>; 21 | 22 | board_sn: board-sn@0 { 23 | reg = <0x0 0x14>; 24 | }; 25 | 26 | eth_mac: eth-mac@20 { 27 | reg = <0x20 0x6>; 28 | }; 29 | 30 | board_name: board-name@d0 { 31 | reg = <0xd0 0x6>; 32 | }; 33 | 34 | board_revision: board-revision@e0 { 35 | reg = <0xe0 0x3>; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /axi_i3c/data/axi_i3c.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc axi_i3c_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | if {$node == 0} { 18 | return 19 | } 20 | set keyval [pldt append $node compatible "\ \, \"xlnx,axi-i3c\""] 21 | } 22 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-x-ebm-01-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | num-cs = <2>; 12 | spi-tx-bus-width = <4>; 13 | spi-rx-bus-width = <4>; 14 | #address-cells = <1>; 15 | #size-cells = <0>; 16 | flash@0 { 17 | #address-cells = <1>; 18 | #size-cells = <1>; 19 | compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ 20 | reg = <0>, <1>; 21 | parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ 22 | spi-tx-bus-width = <4>; 23 | spi-rx-bus-width = <4>; 24 | spi-max-frequency = <150000000>; 25 | partition@0 { 26 | label = "spi0-flash0"; 27 | reg = <0x0 0x10000000>; 28 | }; 29 | }; 30 | -------------------------------------------------------------------------------- /mipi_dsi2_rx_core/data/mipi_dsi2_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc mipi_dsi2_rx_core_generate {drv_handle} { 16 | 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /mipi_dsi_rx_core/data/mipi_dsi_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc mipi_dsi_rx_core_generate {drv_handle} { 16 | 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /dfx_axi_shutdown_manager/data/dfx_axi_shutdown_manager.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfx_axi_shutdown_manager_generate {drv_handle} { 16 | set node [gen_peripheral_nodes $drv_handle] 17 | if {$node == 0} { 18 | return 19 | } 20 | pldt append $node compatible "\ \, \"xlnx,dfx-axi-shutdown-manager\"" 21 | } 22 | -------------------------------------------------------------------------------- /sysmon/data/sysmon.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc sysmon_generate {drv_handle} { 16 | set dts_file [set_drv_def_dts $drv_handle] 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | add_prop $node "xlnx,ip-type" 1 hexint $dts_file 22 | } -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/clock/xlnx-versal2-clk.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022, Xilinx Inc. 4 | * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_CLK_VERSAL2_H 8 | #define _DT_BINDINGS_CLK_VERSAL2_H 9 | 10 | #include "xlnx-versal-net-clk.h" 11 | 12 | #define CAN2_REF_2X 0xC1 13 | #define CAN3_REF_2X 0xC6 14 | #define I3C2_REF 0xBD 15 | #define I3C3_REF 0xBC 16 | #define I3C4_REF 0xBB 17 | #define I3C5_REF 0xC7 18 | #define I3C6_REF 0xC4 19 | #define I3C7_REF 0xC3 20 | #define TTC4 0xCC 21 | #define TTC5 0xCD 22 | #define TTC6 0xCE 23 | #define TTC7 0xCF 24 | #define UFS_REF 0xC8 25 | #define MMI_DRD_REF_CLK 0xD0 26 | #define GPU_PLL 0xD9 27 | #define DC_PIXEL 0xDA 28 | #define GPU_REF 0xDB 29 | #define MMI_AUX0_REF 0xDC 30 | #define PS_AXI_DMA 0xDD 31 | #define AUX1_REF 0xDF 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /dpu_eu/data/dpu_eu.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2019-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc dpu_eu_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"deephi,dpu\"" 22 | } 23 | 24 | 25 | -------------------------------------------------------------------------------- /axi_tft/data/axi_tft.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_tft_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"xlnx,axi-tft\"" 22 | } 23 | 24 | 25 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/reset/xlnx-versal2-resets.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022, Xilinx, Inc. 4 | * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_VERSAL2_RESETS_H 8 | #define _DT_BINDINGS_VERSAL2_RESETS_H 9 | 10 | #include "xlnx-versal-net-resets.h" 11 | 12 | #define VERSAL_RST_UFS (0xC104103U) 13 | #define VERSAL_RST_UFS_PHY (0xC10407CU) 14 | #define VERSAL_RST_DC (0xC104119U) 15 | #define VERSAL_RST_UDH_DRD (0xC10407BU) 16 | #define VERSAL_RST_GPU (0xC10411AU) 17 | #define VERSAL_RST_GPU_RECOV (0xC10411BU) 18 | #define VERSAL_RST_UDH_AUX (0xC10411DU) 19 | #define VERSAL_RST_UDH_DP (0xC10411EU) 20 | #define VERSAL_RST_UDH_HDCPRAM (0xC10411FU) 21 | #define VERSAL_RST_MMI_GEM (0xC104120U) 22 | #define VERSAL_RST_MMI_GEM_CFG (0xC104121U) 23 | #define VERSAL_RST_MMI_GEM_TSU (0xC104122U) 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /mipi_dsi_tx_core/data/mipi_dsi_tx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_dsi_tx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | 24 | } 25 | -------------------------------------------------------------------------------- /pr_decoupler/data/pr_decoupler.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc pr_decoupler_generate {drv_handle} { 17 | set node [gen_peripheral_nodes $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"xlnx,pr-decoupler\"" 22 | } -------------------------------------------------------------------------------- /debug_bridge/data/debug_bridge.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2020-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc debug_bridge_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | pldt append $node compatible "\ \, \"generic-uio\"" 22 | } 23 | 24 | 25 | -------------------------------------------------------------------------------- /mmi_usb/data/mmi_usb.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc mmi_usb_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | if {$node == 0} { 18 | return 19 | } 20 | set mmi_usb_virt_node [create_node -n "&usb_mmi" -d "pcw.dtsi" -p root] 21 | add_prop $mmi_usb_virt_node "status" "okay" string "pcw.dtsi" 22 | } 23 | -------------------------------------------------------------------------------- /axi_fifo_mm_s/data/axi_fifo_mm_s.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc axi_fifo_mm_s_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | if {$node == 0} { 18 | return 19 | } 20 | set compatible [get_comp_str $drv_handle] 21 | set keyval [pldt append $node compatible "\ \, \"xlnx,axi-fifo-mm-s\""] 22 | } 23 | -------------------------------------------------------------------------------- /mipi_csi2_rx_core/data/mipi_csi2_rx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_csi2_rx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | #currently nothing is missing 24 | 25 | } 26 | -------------------------------------------------------------------------------- /mipi_csi2_tx_core/data/mipi_csi2_tx_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_csi2_tx_core_generate {drv_handle} { 17 | 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | if {$node == 0} { 21 | return 22 | } 23 | #currently nothing is missing 24 | 25 | } 26 | -------------------------------------------------------------------------------- /emaclite/data/emaclite.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc emaclite_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | pldt append $node compatible "\ \, \"xlnx,axi-ethernetlite-3.0\" , \"xlnx,xps-ethernetlite-1.00.a\"" 19 | update_eth_mac_addr $drv_handle 20 | gen_mdio_node $drv_handle $node 21 | } 22 | 23 | -------------------------------------------------------------------------------- /hdmi_ctrl/data/hdmi_ctrl.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_ctrl_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | pldt append $node compatible "\ \, \"xlnx,hdmi_act_ctrl\"" 23 | } 24 | 25 | 26 | -------------------------------------------------------------------------------- /pmcdma/data/pmcdma.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc pmcdma_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set pmcbridge [hsi::get_cells -hier -filter IP_NAME==pmcbridge] 19 | if {![string_is_empty $pmcbridge]} { 20 | [return_tree_obj $drv_handle] append $node compatible "\ \, \"xlnx,pmc-dma\"" 21 | add_prop $node "xlnx,dma-type" 1 int $dts_file 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/clock/xlnx-versal2-clk.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2022, Xilinx Inc. 4 | * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_CLK_VERSAL2_H 8 | #define _DT_BINDINGS_CLK_VERSAL2_H 9 | 10 | #include "xlnx-versal-net-clk.h" 11 | 12 | #define CAN2_REF_2X 0xC1 13 | #define CAN3_REF_2X 0xC6 14 | #define I3C2_REF 0xBD 15 | #define I3C3_REF 0xBC 16 | #define I3C4_REF 0xBB 17 | #define I3C5_REF 0xC7 18 | #define I3C6_REF 0xC4 19 | #define I3C7_REF 0xC3 20 | #define TTC4 0xCC 21 | #define TTC5 0xCD 22 | #define TTC6 0xCE 23 | #define TTC7 0xCF 24 | #define UFS_REF 0xC8 25 | #define MMI_DRD_REF_CLK 0xD0 26 | #define MMIPLL 0xD7 27 | #define GPU_PLL 0xD9 28 | #define DC_PIXEL 0xDA 29 | #define GPU_REF 0xDB 30 | #define MMI_AUX0_REF 0xDC 31 | #define PS_AXI_DMA 0xDD 32 | #define MMI_AUX1_REF 0xDF 33 | #define MMI_GEM_HCLK 0xE0 34 | #define DC_REF 0xE2 35 | #define DC_27M 0xE3 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/ac701-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /iicps/data/iicps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc iicps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | ps7_reset_handle $drv_handle CONFIG.C_I2C_RESET CONFIG.i2c-reset 22 | set_drv_conf_prop $drv_handle C_I2C_CLK_FREQ_HZ xlnx,clock-freq $node int 23 | 24 | } 25 | 26 | 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-e-a2197-00-reva.dtsi" 12 | 13 | / { 14 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 15 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 16 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 17 | 18 | /delete-node/ ina226-vcco-500; 19 | /delete-node/ ina226-vcco-501; 20 | /delete-node/ ina226-vcco-502; 21 | }; 22 | 23 | &i2c0 { 24 | i2c-mux@74 { /* u33 */ 25 | i2c@2 { /* PCIE_CLK */ 26 | /delete-node/ clock-generator@6c; 27 | }; 28 | i2c@3 { /* PMBUS2_INA226 */ 29 | /delete-node/ ina226@42; 30 | /delete-node/ ina226@43; 31 | /delete-node/ ina226@44; 32 | }; 33 | }; 34 | }; 35 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-e-a2197-00-reva.dtsi" 12 | 13 | / { 14 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 15 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 16 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 17 | 18 | /delete-node/ ina226-vcco-500; 19 | /delete-node/ ina226-vcco-501; 20 | /delete-node/ ina226-vcco-502; 21 | }; 22 | 23 | &i2c0 { 24 | i2c-mux@74 { /* u33 */ 25 | i2c@2 { /* PCIE_CLK */ 26 | /delete-node/ clock-generator@6c; 27 | }; 28 | i2c@3 { /* PMBUS2_INA226 */ 29 | /delete-node/ ina226@42; 30 | /delete-node/ ina226@43; 31 | /delete-node/ ina226@44; 32 | }; 33 | }; 34 | }; 35 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/ac701-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/kc705-full.dtsi: -------------------------------------------------------------------------------- 1 | &axi_iic_0 { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernet_0 { 35 | phy-handle = <&phy0>; 36 | axi_ethernet_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-e-a2197-00-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx Versal a2197 RevB System Controller 4 | * 5 | * (C) Copyright 2019-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-e-a2197-00-reva.dtsi" 12 | 13 | / { 14 | model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ 15 | compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", 16 | "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 17 | 18 | /delete-node/ ina226-vcco-500; 19 | /delete-node/ ina226-vcco-501; 20 | /delete-node/ ina226-vcco-502; 21 | }; 22 | 23 | &i2c0 { 24 | i2c-mux@74 { /* u33 */ 25 | i2c@2 { /* PCIE_CLK */ 26 | /delete-node/ clock-generator@6c; 27 | }; 28 | i2c@3 { /* PMBUS2_INA226 */ 29 | /delete-node/ ina226@42; 30 | /delete-node/ ina226@43; 31 | /delete-node/ ina226@44; 32 | }; 33 | }; 34 | }; 35 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/kc705-lite.dtsi: -------------------------------------------------------------------------------- 1 | &iic_main { 2 | #address-cells = <1>; 3 | #size-cells = <0>; 4 | i2c-mux@74 { 5 | compatible = "nxp,pca9548"; 6 | #address-cells = <1>; 7 | #size-cells = <0>; 8 | reg = <0x74>; 9 | i2c@0 { 10 | #address-cells = <1>; 11 | #size-cells = <0>; 12 | reg = <0>; 13 | si570: clock-generator@5d { 14 | #clock-cells = <0>; 15 | compatible = "silabs,si570"; 16 | temperature-stability = <50>; 17 | reg = <0x5d>; 18 | factory-fout = <156250000>; 19 | clock-frequency = <148500000>; 20 | }; 21 | }; 22 | i2c@3 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | reg = <3>; 26 | eeprom@54 { 27 | compatible = "atmel,24c08"; 28 | reg = <0x54>; 29 | }; 30 | }; 31 | }; 32 | }; 33 | 34 | &axi_ethernetlite { 35 | phy-handle = <&phy0>; 36 | axi_ethernetlite_mdio: mdio { 37 | #address-cells = <1>; 38 | #size-cells = <0>; 39 | phy0: phy@7 { 40 | device_type = "ethernet-phy"; 41 | reg = <7>; 42 | }; 43 | }; 44 | }; 45 | -------------------------------------------------------------------------------- /generic/data/generic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc generic_generate {drv_handle} { 17 | set hsi_version [get_hsi_version] 18 | set ver [split $hsi_version "."] 19 | set value [lindex $ver 0] 20 | set dts_file [set_drv_def_dts $drv_handle] 21 | if {$value >= 2018} { 22 | set generic_node [get_node $drv_handle] 23 | } 24 | } 25 | 26 | 27 | -------------------------------------------------------------------------------- /wdttb/data/wdttb.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023-2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc wdttb_generate {drv_handle} { 16 | set dts_file [set_drv_def_dts $drv_handle] 17 | set node [get_node $drv_handle] 18 | #Add a node to enable winwdt examples in PS and PL 19 | add_prop $node "xlnx,winwdt-example" 1 int $dts_file 20 | 21 | if {[string match -nocase $dts_file "pcw.dtsi"]} { 22 | add_prop $node compatible "xlnx,versal-wwdt-1.0 xlnx,versal-wwdt" stringlist $dts_file 1 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /tmr_inject/data/tmr_inject.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc tmr_inject_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set tree_obj [return_tree_obj $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | set version [string tolower [hsi get_property VLNV $drv_handle]] 22 | if {![string compare -nocase "xilinx.com:ip:tmr_inject:1.0" $version] == 0} { 23 | $tree_obj append $node compatible "\ \, \"xlnx,tmr-inject-1.0\"" 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /device_tree/data/parts_spec.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | # Placeholder proc to set parts specific IP-tcl file mapping 16 | proc part_specific_init_proclist {} { 17 | 18 | } 19 | 20 | # Placeholder proc to set parts specific PS IP and baseaddress mapping 21 | proc part_specific_ps_mapping {def_ps_mapping} { 22 | return $def_ps_mapping 23 | } 24 | 25 | # Placeholder proc to accomodate parts specific miscellaneous operations 26 | proc gen_part_specific_misc {} { 27 | 28 | } -------------------------------------------------------------------------------- /tmr_manager/data/tmr_manager.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc tmr_manager_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set tree_obj [return_tree_obj $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | set version [string tolower [hsi get_property VLNV $drv_handle]] 22 | if {![string compare -nocase "xilinx.com:ip:tmr_manager:1.0" $version] == 0} { 23 | $tree_obj append $node compatible "\ \, \"xlnx,tmr-manager-1.0\"" 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /RM/data/RM.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2017-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc RM_generate {drv_handle} { 17 | set val [hsi get_property FAMILY [hsi::get_hw_designs]] 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts] 20 | switch -glob $val { 21 | "zynq" { 22 | add_prop $node "fpga-mgr" "<&devcfg>" string $dts_file 23 | } 24 | } 25 | } 26 | 27 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | 15 | 16 | chosen { 17 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200n8 root=/dev/ram0 rw"; 18 | stdout-path = "serial0:115200n8"; 19 | }; 20 | 21 | /* aliases { 22 | nvmem0 = &eeprom0; 23 | nvmem1 = &eeprom1; 24 | }; */ 25 | }; 26 | 27 | &i2c0 { 28 | /* Access via J70/J71 or J82/J83 */ 29 | clock-frequency = <100000>; 30 | }; 31 | 32 | &i2c1 { 33 | /* Access via J70/J71 or J82/J83 */ 34 | /* By default this bus should have eeprom for board identification at 0x54 */ 35 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 36 | clock-frequency = <100000>; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | 15 | 16 | chosen { 17 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200n8 root=/dev/ram0 rw"; 18 | stdout-path = "serial0:115200n8"; 19 | }; 20 | 21 | /* aliases { 22 | nvmem0 = &eeprom0; 23 | nvmem1 = &eeprom1; 24 | }; */ 25 | }; 26 | 27 | &i2c0 { 28 | /* Access via J70/J71 or J82/J83 */ 29 | clock-frequency = <100000>; 30 | }; 31 | 32 | &i2c1 { 33 | /* Access via J70/J71 or J82/J83 */ 34 | /* By default this bus should have eeprom for board identification at 0x54 */ 35 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 36 | clock-frequency = <100000>; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) 4 | * 5 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "xlnx,versal-net-vn-p-b2197-00-revA", 13 | "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; 14 | 15 | 16 | chosen { 17 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200n8 root=/dev/ram0 rw"; 18 | stdout-path = "serial0:115200n8"; 19 | }; 20 | 21 | /* aliases { 22 | nvmem0 = &eeprom0; 23 | nvmem1 = &eeprom1; 24 | }; */ 25 | }; 26 | 27 | &i2c0 { 28 | /* Access via J70/J71 or J82/J83 */ 29 | clock-frequency = <100000>; 30 | }; 31 | 32 | &i2c1 { 33 | /* Access via J70/J71 or J82/J83 */ 34 | /* By default this bus should have eeprom for board identification at 0x54 */ 35 | /* SE/X-PRC card identification is also on this bus at 0x52 */ 36 | clock-frequency = <100000>; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-revc.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP Generic System Controller 4 | * 5 | * Copyright (C) 2021-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sc-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP Generic System Controller"; 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ 19 | /delete-node/ mdio; 20 | 21 | mdio: mdio { 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | 25 | phy0: ethernet-phy@1 { /* ADI1300 */ 26 | #phy-cells = <1>; 27 | compatible = "ethernet-phy-id0283.bc30"; 28 | reg = <1>; 29 | adi,rx-internal-delay-ps = <2400>; 30 | adi,tx-internal-delay-ps = <2400>; 31 | adi,fifo-depth-bits = <8>; 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 33 | reset-assert-us = <10>; 34 | reset-deassert-us = <5000>; 35 | }; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zynqmp-sc-revc.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP Generic System Controller 4 | * 5 | * Copyright (C) 2021-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sc-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP Generic System Controller"; 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ 19 | /delete-node/ mdio; 20 | 21 | mdio: mdio { 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | 25 | phy0: ethernet-phy@1 { /* ADI1300 */ 26 | #phy-cells = <1>; 27 | compatible = "ethernet-phy-id0283.bc30"; 28 | reg = <1>; 29 | adi,rx-internal-delay-ps = <2400>; 30 | adi,tx-internal-delay-ps = <2400>; 31 | adi,fifo-depth-bits = <8>; 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 33 | reset-assert-us = <10>; 34 | reset-deassert-us = <5000>; 35 | }; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zynqmp-sc-revc.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx ZynqMP Generic System Controller 4 | * 5 | * Copyright (C) 2021-2022 Xilinx, Inc. 6 | * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zynqmp-sc-revb.dtsi" 12 | 13 | / { 14 | model = "ZynqMP Generic System Controller"; 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ 19 | /delete-node/ mdio; 20 | 21 | mdio: mdio { 22 | #address-cells = <1>; 23 | #size-cells = <0>; 24 | 25 | phy0: ethernet-phy@1 { /* ADI1300 */ 26 | #phy-cells = <1>; 27 | compatible = "ethernet-phy-id0283.bc30"; 28 | reg = <1>; 29 | adi,rx-internal-delay-ps = <2400>; 30 | adi,tx-internal-delay-ps = <2400>; 31 | adi,fifo-depth-bits = <8>; 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 33 | reset-assert-us = <10>; 34 | reset-deassert-us = <5000>; 35 | }; 36 | }; 37 | }; 38 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | 14 | /* U97 MT35XU02G */ 15 | bus-num = <2>; 16 | num-cs = <1>; 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | 20 | flash@0 { 21 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 22 | reg = <0>; 23 | #address-cells = <1>; 24 | #size-cells = <1>; 25 | cdns,read-delay = <0x0>; 26 | cdns,tshsl-ns = <0x0>; 27 | cdns,tsd2d-ns = <0x0>; 28 | cdns,tchsh-ns = <0x1>; 29 | cdns,tslch-ns = <0x1>; 30 | spi-tx-bus-width = <8>; 31 | spi-rx-bus-width = <8>; 32 | spi-max-frequency = <20000000>; 33 | no-wp; 34 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 35 | partition@0 { 36 | label = "spi0-flash0"; 37 | reg = <0x0 0x8000000>; 38 | }; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | 14 | /* U97 MT35XU02G */ 15 | bus-num = <2>; 16 | num-cs = <1>; 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | 20 | flash@0 { 21 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 22 | reg = <0>; 23 | #address-cells = <1>; 24 | #size-cells = <1>; 25 | cdns,read-delay = <0x0>; 26 | cdns,tshsl-ns = <0x0>; 27 | cdns,tsd2d-ns = <0x0>; 28 | cdns,tchsh-ns = <0x1>; 29 | cdns,tslch-ns = <0x1>; 30 | spi-tx-bus-width = <8>; 31 | spi-rx-bus-width = <8>; 32 | spi-max-frequency = <20000000>; 33 | no-wp; 34 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 35 | partition@0 { 36 | label = "spi0-flash0"; 37 | reg = <0x0 0x8000000>; 38 | }; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal-x-ebm-03-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 4 | * 5 | * (C) Copyright 2020-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "include/dt-bindings/gpio/gpio.h" 12 | #include "include/dt-bindings/reset/xlnx-versal-resets.h" 13 | 14 | /* U97 MT35XU02G */ 15 | bus-num = <2>; 16 | num-cs = <1>; 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | 20 | flash@0 { 21 | compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; 22 | reg = <0>; 23 | #address-cells = <1>; 24 | #size-cells = <1>; 25 | cdns,read-delay = <0x0>; 26 | cdns,tshsl-ns = <0x0>; 27 | cdns,tsd2d-ns = <0x0>; 28 | cdns,tchsh-ns = <0x1>; 29 | cdns,tslch-ns = <0x1>; 30 | spi-tx-bus-width = <8>; 31 | spi-rx-bus-width = <8>; 32 | spi-max-frequency = <20000000>; 33 | no-wp; 34 | reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; 35 | partition@0 { 36 | label = "spi0-flash0"; 37 | reg = <0x0 0x8000000>; 38 | }; 39 | }; 40 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/net/mscc-phy-vsc8531.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Device Tree constants for Microsemi VSC8531 PHY 4 | * 5 | * Author: Nagaraju Lakkaraju 6 | * 7 | * Copyright (c) 2017 Microsemi Corporation 8 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_MSCC_VSC8531_H 12 | #define _DT_BINDINGS_MSCC_VSC8531_H 13 | 14 | /* PHY LED Modes */ 15 | #define VSC8531_LINK_ACTIVITY 0 16 | #define VSC8531_LINK_1000_ACTIVITY 1 17 | #define VSC8531_LINK_100_ACTIVITY 2 18 | #define VSC8531_LINK_10_ACTIVITY 3 19 | #define VSC8531_LINK_100_1000_ACTIVITY 4 20 | #define VSC8531_LINK_10_1000_ACTIVITY 5 21 | #define VSC8531_LINK_10_100_ACTIVITY 6 22 | #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 23 | #define VSC8531_DUPLEX_COLLISION 8 24 | #define VSC8531_COLLISION 9 25 | #define VSC8531_ACTIVITY 10 26 | #define VSC8584_100FX_1000X_ACTIVITY 11 27 | #define VSC8531_AUTONEG_FAULT 12 28 | #define VSC8531_SERIAL_MODE 13 29 | #define VSC8531_FORCE_LED_OFF 14 30 | #define VSC8531_FORCE_LED_ON 15 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/net/mscc-phy-vsc8531.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Device Tree constants for Microsemi VSC8531 PHY 4 | * 5 | * Author: Nagaraju Lakkaraju 6 | * 7 | * Copyright (c) 2017 Microsemi Corporation 8 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_MSCC_VSC8531_H 12 | #define _DT_BINDINGS_MSCC_VSC8531_H 13 | 14 | /* PHY LED Modes */ 15 | #define VSC8531_LINK_ACTIVITY 0 16 | #define VSC8531_LINK_1000_ACTIVITY 1 17 | #define VSC8531_LINK_100_ACTIVITY 2 18 | #define VSC8531_LINK_10_ACTIVITY 3 19 | #define VSC8531_LINK_100_1000_ACTIVITY 4 20 | #define VSC8531_LINK_10_1000_ACTIVITY 5 21 | #define VSC8531_LINK_10_100_ACTIVITY 6 22 | #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 23 | #define VSC8531_DUPLEX_COLLISION 8 24 | #define VSC8531_COLLISION 9 25 | #define VSC8531_ACTIVITY 10 26 | #define VSC8584_100FX_1000X_ACTIVITY 11 27 | #define VSC8531_AUTONEG_FAULT 12 28 | #define VSC8531_SERIAL_MODE 13 29 | #define VSC8531_FORCE_LED_OFF 14 30 | #define VSC8531_FORCE_LED_ON 15 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/net/mscc-phy-vsc8531.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Device Tree constants for Microsemi VSC8531 PHY 4 | * 5 | * Author: Nagaraju Lakkaraju 6 | * 7 | * Copyright (c) 2017 Microsemi Corporation 8 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_MSCC_VSC8531_H 12 | #define _DT_BINDINGS_MSCC_VSC8531_H 13 | 14 | /* PHY LED Modes */ 15 | #define VSC8531_LINK_ACTIVITY 0 16 | #define VSC8531_LINK_1000_ACTIVITY 1 17 | #define VSC8531_LINK_100_ACTIVITY 2 18 | #define VSC8531_LINK_10_ACTIVITY 3 19 | #define VSC8531_LINK_100_1000_ACTIVITY 4 20 | #define VSC8531_LINK_10_1000_ACTIVITY 5 21 | #define VSC8531_LINK_10_100_ACTIVITY 6 22 | #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 23 | #define VSC8531_DUPLEX_COLLISION 8 24 | #define VSC8531_COLLISION 9 25 | #define VSC8531_ACTIVITY 10 26 | #define VSC8584_100FX_1000X_ACTIVITY 11 27 | #define VSC8531_AUTONEG_FAULT 12 28 | #define VSC8531_SERIAL_MODE 13 29 | #define VSC8531_FORCE_LED_OFF 14 30 | #define VSC8531_FORCE_LED_ON 15 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /asu/data/asu.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 - 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc asu_generate {drv_handle} { 16 | set cpu_node [create_node -n "&asu" -d "pcw.dtsi" -p root -h $drv_handle] 17 | set ip_name [get_ip_property $drv_handle IP_NAME] 18 | add_prop $cpu_node "xlnx,ip-name" $ip_name string "pcw.dtsi" 19 | gen_drv_prop_from_ip $drv_handle 20 | set clk_freq [get_ip_property $drv_handle "CONFIG.C_CPU_CLK_FREQ_HZ"] 21 | add_prop $cpu_node "clock-frequency" $clk_freq int "pcw.dtsi" 1 22 | add_prop $cpu_node "timebase-frequency" $clk_freq int "pcw.dtsi" 1 23 | add_prop $cpu_node "xlnx,freq" $clk_freq int "pcw.dtsi" 1 24 | } 25 | -------------------------------------------------------------------------------- /axi_iic/data/axi_iic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_iic_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(CUSTOM_SDT_REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | 26 | pldt append $node compatible "\ \, \"xlnx,xps-iic-2.00.a\"" 27 | set proctype [get_hw_family] 28 | if {[regexp "microblaze" $proctype match]} { 29 | gen_dev_ccf_binding $drv_handle "s_axi_aclk" 30 | } 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 RevB"; 15 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem3 { 19 | phy-handle = <&phyc>; 20 | mdio: mdio { 21 | phyc: ethernet-phy@c { 22 | #phy-cells = <0x1>; 23 | compatible = "ethernet-phy-id2000.a231"; 24 | reg = <0xc>; 25 | ti,rx-internal-delay = <0x8>; 26 | ti,tx-internal-delay = <0xa>; 27 | ti,fifo-depth = <0x1>; 28 | ti,dp83867-rxctrl-strap-quirk; 29 | reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30 | }; 31 | /* Cleanup from RevA */ 32 | /delete-node/ ethernet-phy@21; 33 | }; 34 | }; 35 | 36 | /* Fix collision with u61 */ 37 | &i2c0 { 38 | i2c-mux@75 { 39 | i2c@2 { 40 | max15303@1b { /* u8 */ 41 | compatible = "maxim,max15303"; 42 | reg = <0x1b>; 43 | }; 44 | /delete-node/ max15303@20; 45 | }; 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 RevB"; 15 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem3 { 19 | phy-handle = <&phyc>; 20 | mdio: mdio { 21 | phyc: ethernet-phy@c { 22 | #phy-cells = <0x1>; 23 | compatible = "ethernet-phy-id2000.a231"; 24 | reg = <0xc>; 25 | ti,rx-internal-delay = <0x8>; 26 | ti,tx-internal-delay = <0xa>; 27 | ti,fifo-depth = <0x1>; 28 | ti,dp83867-rxctrl-strap-quirk; 29 | reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30 | }; 31 | /* Cleanup from RevA */ 32 | /delete-node/ ethernet-phy@21; 33 | }; 34 | }; 35 | 36 | /* Fix collision with u61 */ 37 | &i2c0 { 38 | i2c-mux@75 { 39 | i2c@2 { 40 | max15303@1b { /* u8 */ 41 | compatible = "maxim,max15303"; 42 | reg = <0x1b>; 43 | }; 44 | /delete-node/ max15303@20; 45 | }; 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/zcu102-revb.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZCU102 RevB 4 | * 5 | * (C) Copyright 2016-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | */ 10 | 11 | #include "zcu102-reva.dtsi" 12 | 13 | / { 14 | model = "ZynqMP ZCU102 RevB"; 15 | compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 16 | }; 17 | 18 | &gem3 { 19 | phy-handle = <&phyc>; 20 | mdio: mdio { 21 | phyc: ethernet-phy@c { 22 | #phy-cells = <0x1>; 23 | compatible = "ethernet-phy-id2000.a231"; 24 | reg = <0xc>; 25 | ti,rx-internal-delay = <0x8>; 26 | ti,tx-internal-delay = <0xa>; 27 | ti,fifo-depth = <0x1>; 28 | ti,dp83867-rxctrl-strap-quirk; 29 | reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; 30 | }; 31 | /* Cleanup from RevA */ 32 | /delete-node/ ethernet-phy@21; 33 | }; 34 | }; 35 | 36 | /* Fix collision with u61 */ 37 | &i2c0 { 38 | i2c-mux@75 { 39 | i2c@2 { 40 | max15303@1b { /* u8 */ 41 | compatible = "maxim,max15303"; 42 | reg = <0x1b>; 43 | }; 44 | /delete-node/ max15303@20; 45 | }; 46 | }; 47 | }; 48 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal2-ve-p-a2112-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "amd,versal2"; 13 | model = "AMD Versal Gen 2 Silicon EL2"; 14 | 15 | chosen { 16 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 17 | stdout-path = "serial0:115200n8"; 18 | }; 19 | 20 | reserved-memory { 21 | #address-cells = <2>; 22 | #size-cells = <2>; 23 | ranges; 24 | 25 | /* TF-A, TEE, RPUs */ 26 | /* FIXME Uncomment after VNC */ 27 | /*res: memory@0 { 28 | no-map; 29 | reg = <0 0 0 0x20000000>; 30 | }; */ 31 | }; 32 | }; 33 | 34 | &adma0 { 35 | dma-coherent; 36 | }; 37 | 38 | &adma1 { 39 | dma-coherent; 40 | }; 41 | 42 | &adma2 { 43 | dma-coherent; 44 | }; 45 | 46 | &adma3 { 47 | dma-coherent; 48 | }; 49 | 50 | &adma4 { 51 | dma-coherent; 52 | }; 53 | 54 | &adma5 { 55 | dma-coherent; 56 | }; 57 | 58 | &adma6 { 59 | dma-coherent; 60 | }; 61 | 62 | &adma7 { 63 | dma-coherent; 64 | }; 65 | 66 | &gem0 { 67 | dma-coherent; 68 | }; 69 | /* GPIO leds/dips/pushPB, SMA to PL */ 70 | -------------------------------------------------------------------------------- /mipi_rx_phy/data/mipi_rx_phy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_rx_phy_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set phy_mode [hsi get_property CONFIG.C_PHY_MODE [hsi::get_cells -hier $drv_handle]] 23 | puts "phy_mode = $phy_mode" 24 | if {[string match -nocase $phy_mode "dphy"]} { 25 | add_prop "$node" "xlnx,phy-mode" 1 int $dts_file 1 26 | } else { 27 | add_prop "$node" "xlnx,phy-mode" 0 int $dts_file 1 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /mipi_tx_phy/data/mipi_tx_phy.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc mipi_tx_phy_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set phy_mode [hsi get_property CONFIG.C_PHY_MODE [hsi::get_cells -hier $drv_handle]] 23 | puts "phy_mode = $phy_mode" 24 | if {[string match -nocase $phy_mode "dphy"]} { 25 | add_prop "$node" "xlnx,phy-mode" 1 int $dts_file 1 26 | } else { 27 | add_prop "$node" "xlnx,phy-mode" 0 int $dts_file 1 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/versal2-ve-p-a2112-00-revA.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "amd,versal2"; 13 | model = "AMD Versal Gen 2 Silicon EL2"; 14 | 15 | chosen { 16 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 17 | stdout-path = "serial0:115200n8"; 18 | }; 19 | 20 | reserved-memory { 21 | #address-cells = <2>; 22 | #size-cells = <2>; 23 | ranges; 24 | 25 | /* TF-A, TEE, RPUs */ 26 | /* FIXME Uncomment after VNC */ 27 | /*res: memory@0 { 28 | no-map; 29 | reg = <0 0 0 0x20000000>; 30 | }; */ 31 | }; 32 | }; 33 | 34 | &adma0 { 35 | dma-coherent; 36 | }; 37 | 38 | &adma1 { 39 | dma-coherent; 40 | }; 41 | 42 | &adma2 { 43 | dma-coherent; 44 | }; 45 | 46 | &adma3 { 47 | dma-coherent; 48 | }; 49 | 50 | &adma4 { 51 | dma-coherent; 52 | }; 53 | 54 | &adma5 { 55 | dma-coherent; 56 | }; 57 | 58 | &adma6 { 59 | dma-coherent; 60 | }; 61 | 62 | &adma7 { 63 | dma-coherent; 64 | }; 65 | 66 | &gem0 { 67 | dma-coherent; 68 | }; 69 | 70 | /* GPIO leds/dips/pushPB, SMA to PL */ 71 | -------------------------------------------------------------------------------- /smccps/data/smccps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc smccps_generate {drv_handle} { 17 | set handle [hsi::get_cells -hier -filter {IP_NAME==ps7_smcc}] 18 | set node [get_node $drv_handle] 19 | set dts_file [set_drv_def_dts $drv_handle] 20 | set reg [get_baseaddr [hsi::get_cells -hier $handle]] 21 | add_prop $node "flashbase" $reg int $dts_file 22 | set nand_handle [hsi::get_cells -hier -filter {IP_NAME==ps7_nand}] 23 | set bus_width [get_ip_property $nand_handle CONFIG.C_NAND_WIDTH] 24 | add_prop $node "nand-bus-width" $bus_width int $dts_file 25 | } 26 | 27 | 28 | -------------------------------------------------------------------------------- /dmaps/data/dmaps.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc dmaps_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | set ip [hsi::get_cells -hier $drv_handle] 20 | 21 | set ip_name [get_ip_property $drv_handle IP_NAME] 22 | set req_dma_list "psu_gdma psu_adma psu_csudma" 23 | if {[lsearch -nocase $req_dma_list $ip_name] >= 0} { 24 | set_drv_conf_prop $drv_handle C_DMA_MODE xlnx,dma-type $node int 25 | if {[string match -nocase $ip_name "psu_csudma"]} { 26 | add_prop $node "xlnx,dma-type" 0 int $dts_file 27 | } 28 | } 29 | } 30 | 31 | 32 | -------------------------------------------------------------------------------- /axi_usb2_device/data/axi_usb2_device.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc axi_usb2_device_generate {drv_handle} { 17 | global env 18 | global dtsi_fname 19 | set path $env(CUSTOM_SDT_REPO) 20 | 21 | set node [get_node $drv_handle] 22 | if {$node == 0} { 23 | return 24 | } 25 | pldt append $node compatible "\ \, \"xlnx,usb2-device-4.00.a\"" 26 | set ip [hsi::get_cells -hier $drv_handle] 27 | set include_dma [hsi get_property CONFIG.C_INCLUDE_DMA $ip] 28 | if { $include_dma eq "1"} { 29 | set_drv_conf_prop $drv_handle C_INCLUDE_DMA xlnx,has-builtin-dma $node boolean 30 | } 31 | 32 | } 33 | 34 | 35 | -------------------------------------------------------------------------------- /dprx21_core/data/dprx21_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | 17 | proc dprx21_core_generate {drv_handle} { 18 | set node [get_node $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set dts_file [set_drv_def_dts $drv_handle] 23 | set freq [get_clk_pin_freq $drv_handle "S_AXI_ACLK"] 24 | if {[llength $freq] == 0} { 25 | set freq "100000000" 26 | puts "WARNING: Clock frequency information is not available in the design, \ 27 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 28 | If this is incorrect, the peripheral $drv_handle will be non-functional" 29 | } 30 | add_prop "${node}" "xlnx,axi-aclk-freq-mhz" $freq hexint $dts_file 1 31 | 32 | } 33 | -------------------------------------------------------------------------------- /dptx21_core/data/dptx21_core.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | 17 | proc dptx21_core_generate {drv_handle} { 18 | set node [get_node $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | set dts_file [set_drv_def_dts $drv_handle] 23 | set freq [get_clk_pin_freq $drv_handle "S_AXI_ACLK"] 24 | if {[llength $freq] == 0} { 25 | set freq "100000000" 26 | puts "WARNING: Clock frequency information is not available in the design, \ 27 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 28 | If this is incorrect, the peripheral $drv_handle will be non-functional" 29 | } 30 | add_prop "${node}" "xlnx,axi-aclk-freq-mhz" $freq hexint $dts_file 1 31 | 32 | } 33 | -------------------------------------------------------------------------------- /dfeccf/data/dfeccf.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2024 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfeccf_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set count 0 19 | foreach handle [hsi::get_cells -hier] { 20 | set ip_name [hsi get_property IP_NAME $handle] 21 | if {[string match -nocase $ip_name "xdfe_cc_filter"] } { 22 | set count [expr $count + 1] 23 | } 24 | } 25 | add_prop $node "num-insts" $count hexlist $dts_file 26 | 27 | set value [hsi get_property "CONFIG.C_SWITCHABLE" $drv_handle] 28 | add_prop $node "xlnx,switchable" $value string $dts_file 1 29 | if {[string compare -nocase "true" $value] == 0} { 30 | set value 1 31 | } else { 32 | set value 0 33 | } 34 | add_prop $node "xlnx,switchable-int" $value hexint $dts_file 35 | } 36 | -------------------------------------------------------------------------------- /hdmi_rx/data/hdmi_rx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_rx_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /hdmi_tx/data/hdmi_tx.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_tx_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /dfeofdm/data/dfeofdm.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2025 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfeofdm_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set count 0 19 | foreach handle [hsi::get_cells -hier] { 20 | set ip_name [hsi get_property IP_NAME $handle] 21 | if {[string match -nocase $ip_name "xdfe_ofdm"] } { 22 | set count [expr $count + 1] 23 | } 24 | } 25 | add_prop $node "num-insts" $count hexlist $dts_file 26 | 27 | set value [hsi get_property "CONFIG.C_FREQUENCY_RANGE" $drv_handle] 28 | add_prop $node "xlnx,frequency-range" $value string $dts_file 1 29 | if {[string compare -nocase "FR1" $value] == 0} { 30 | set value 0 31 | } else { 32 | set value 1 33 | } 34 | add_prop $node "xlnx,frequency-range-int" $value hexint $dts_file 35 | } -------------------------------------------------------------------------------- /hdmi_rx1/data/hdmi_rx1.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_rx1_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /hdmi_tx1/data/hdmi_tx1.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2018-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc hdmi_tx1_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | if {$node == 0} { 20 | return 21 | } 22 | 23 | set freq 0 24 | set freq [get_clk_pin_freq $drv_handle "s_axi_aclk"] 25 | if {[llength $freq] == 0} { 26 | set freq "100000000" 27 | puts "WARNING: Clock frequency information is not available in the design, \ 28 | for peripheral $drv_handle. Assuming a default frequency of 100MHz. \ 29 | If this is incorrect, the peripheral $drv_handle will be non-functional" 30 | } 31 | add_prop "${node}" "xlnx,axi-lite-freq-hz" $freq hexint $dts_file 1 32 | 33 | } 34 | -------------------------------------------------------------------------------- /scugic/data/scugic.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc scugic_generate {drv_handle} { 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set proctype [get_hw_family] 19 | set cpm_ip [hsi::get_cells -hier -filter IP_NAME==psv_cpm] 20 | 21 | if {[string match -nocase $proctype "versal"] && \ 22 | [string match -nocase [hsi get_property CONFIG.APU_GIC_ITS_CTL [hsi get_cells -hier $drv_handle]] "0xF9020000"] && \ 23 | [llength $cpm_ip]} { 24 | set node [create_node -n "&gic_its" -d $dts_file -p root] 25 | add_prop $node "status" "okay" string $dts_file 26 | set reg "0x0 0xf9020000 0x0 0x20000" 27 | set_memmap "gic_its" a53 $reg 28 | } 29 | } 30 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/BOARD/versal2-ve-p-a2112-00-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0 2 | /* 3 | * dts file for AMD Versal Gen 2 VNC (T50) 4 | * 5 | * Copyright (C) 2024, Advanced Micro Devices, Inc. 6 | * 7 | * Michal Simek 8 | */ 9 | 10 | 11 | / { 12 | compatible = "amd,versal2"; 13 | model = "AMD Versal Gen 2 Silicon EL2"; 14 | 15 | chosen { 16 | bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200"; 17 | stdout-path = "serial0:115200n8"; 18 | }; 19 | 20 | reserved-memory { 21 | #address-cells = <2>; 22 | #size-cells = <2>; 23 | ranges; 24 | 25 | /* TF-A, TEE, RPUs */ 26 | /* FIXME Uncomment after VNC */ 27 | /*res: memory@0 { 28 | no-map; 29 | reg = <0 0 0 0x20000000>; 30 | }; */ 31 | }; 32 | }; 33 | 34 | &adma0 { 35 | dma-coherent; 36 | }; 37 | 38 | &adma1 { 39 | dma-coherent; 40 | }; 41 | 42 | &adma2 { 43 | dma-coherent; 44 | }; 45 | 46 | &adma3 { 47 | dma-coherent; 48 | }; 49 | 50 | &adma4 { 51 | dma-coherent; 52 | }; 53 | 54 | &adma5 { 55 | dma-coherent; 56 | }; 57 | 58 | &adma6 { 59 | dma-coherent; 60 | }; 61 | 62 | &adma7 { 63 | dma-coherent; 64 | }; 65 | 66 | &gem0 { 67 | dma-coherent; 68 | }; 69 | /* GPIO leds/dips/pushPB, SMA to PL */ 70 | &mmi_10gbe { 71 | phy-mode = "10gbase-r"; 72 | fixed-link { 73 | speed = <10000>; 74 | full-duplex; 75 | }; 76 | }; 77 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 8 | #define _DT_BINDINGS_ZYNQMP_POWER_H 9 | 10 | #define PD_RPU 6 11 | #define PD_RPU_0 7 12 | #define PD_RPU_1 8 13 | #define PD_OCM_0 11 14 | #define PD_OCM_1 12 15 | #define PD_OCM_2 13 16 | #define PD_OCM_3 14 17 | #define PD_TCM_0_A 15 18 | #define PD_TCM_0_B 16 19 | #define PD_TCM_1_A 17 20 | #define PD_TCM_1_B 18 21 | #define PD_USB_0 22 22 | #define PD_USB_1 23 23 | #define PD_TTC_0 24 24 | #define PD_TTC_1 25 25 | #define PD_TTC_2 26 26 | #define PD_TTC_3 27 27 | #define PD_SATA 28 28 | #define PD_ETH_0 29 29 | #define PD_ETH_1 30 30 | #define PD_ETH_2 31 31 | #define PD_ETH_3 32 32 | #define PD_UART_0 33 33 | #define PD_UART_1 34 34 | #define PD_SPI_0 35 35 | #define PD_SPI_1 36 36 | #define PD_I2C_0 37 37 | #define PD_I2C_1 38 38 | #define PD_SD_0 39 39 | #define PD_SD_1 40 40 | #define PD_DP 41 41 | #define PD_GDMA 42 42 | #define PD_ADMA 43 43 | #define PD_NAND 44 44 | #define PD_QSPI 45 45 | #define PD_GPIO 46 46 | #define PD_CAN_0 47 47 | #define PD_CAN_1 48 48 | #define PD_GPU 58 49 | #define PD_PCIE 59 50 | #define PD_PL 69 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 8 | #define _DT_BINDINGS_ZYNQMP_POWER_H 9 | 10 | #define PD_RPU 6 11 | #define PD_RPU_0 7 12 | #define PD_RPU_1 8 13 | #define PD_OCM_0 11 14 | #define PD_OCM_1 12 15 | #define PD_OCM_2 13 16 | #define PD_OCM_3 14 17 | #define PD_TCM_0_A 15 18 | #define PD_TCM_0_B 16 19 | #define PD_TCM_1_A 17 20 | #define PD_TCM_1_B 18 21 | #define PD_USB_0 22 22 | #define PD_USB_1 23 23 | #define PD_TTC_0 24 24 | #define PD_TTC_1 25 25 | #define PD_TTC_2 26 26 | #define PD_TTC_3 27 27 | #define PD_SATA 28 28 | #define PD_ETH_0 29 29 | #define PD_ETH_1 30 30 | #define PD_ETH_2 31 31 | #define PD_ETH_3 32 32 | #define PD_UART_0 33 33 | #define PD_UART_1 34 34 | #define PD_SPI_0 35 35 | #define PD_SPI_1 36 36 | #define PD_I2C_0 37 37 | #define PD_I2C_1 38 38 | #define PD_SD_0 39 39 | #define PD_SD_1 40 40 | #define PD_DP 41 41 | #define PD_GDMA 42 42 | #define PD_ADMA 43 43 | #define PD_NAND 44 44 | #define PD_QSPI 45 45 | #define PD_GPIO 46 46 | #define PD_CAN_0 47 47 | #define PD_CAN_1 48 48 | #define PD_GPU 58 49 | #define PD_PCIE 59 50 | #define PD_PL 69 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.2/include/dt-bindings/power/xlnx-zynqmp-power.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Copyright (C) 2018 Xilinx-2022 Xilinx, Inc. 4 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_ZYNQMP_POWER_H 8 | #define _DT_BINDINGS_ZYNQMP_POWER_H 9 | 10 | #define PD_RPU 6 11 | #define PD_RPU_0 7 12 | #define PD_RPU_1 8 13 | #define PD_OCM_0 11 14 | #define PD_OCM_1 12 15 | #define PD_OCM_2 13 16 | #define PD_OCM_3 14 17 | #define PD_TCM_0_A 15 18 | #define PD_TCM_0_B 16 19 | #define PD_TCM_1_A 17 20 | #define PD_TCM_1_B 18 21 | #define PD_USB_0 22 22 | #define PD_USB_1 23 23 | #define PD_TTC_0 24 24 | #define PD_TTC_1 25 25 | #define PD_TTC_2 26 26 | #define PD_TTC_3 27 27 | #define PD_SATA 28 28 | #define PD_ETH_0 29 29 | #define PD_ETH_1 30 30 | #define PD_ETH_2 31 31 | #define PD_ETH_3 32 32 | #define PD_UART_0 33 33 | #define PD_UART_1 34 34 | #define PD_SPI_0 35 35 | #define PD_SPI_1 36 36 | #define PD_I2C_0 37 37 | #define PD_I2C_1 38 38 | #define PD_SD_0 39 39 | #define PD_SD_1 40 40 | #define PD_DP 41 41 | #define PD_GDMA 42 42 | #define PD_ADMA 43 43 | #define PD_NAND 44 44 | #define PD_QSPI 45 45 | #define PD_GPIO 46 46 | #define PD_CAN_0 47 47 | #define PD_CAN_1 48 48 | #define PD_GPU 58 49 | #define PD_PCIE 59 50 | #define PD_PL 69 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /dfemix/data/dfemix.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. 3 | # 4 | # This program is free software; you can redistribute it and/or 5 | # modify it under the terms of the GNU General Public License as 6 | # published by the Free Software Foundation; either version 2 of 7 | # the License, or (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # 14 | 15 | proc dfemix_generate {drv_handle} { 16 | set node [get_node $drv_handle] 17 | set dts_file [set_drv_def_dts $drv_handle] 18 | set count 0 19 | foreach handle [hsi::get_cells -hier] { 20 | set ip_name [hsi get_property IP_NAME $handle] 21 | if {[string match -nocase $ip_name "xdfe_cc_mixer"] } { 22 | set count [expr $count + 1] 23 | } 24 | } 25 | add_prop $node "num-insts" $count hexlist $dts_file 26 | 27 | set value [hsi get_property "CONFIG.C_MODE" $drv_handle] 28 | if {[string compare -nocase "downlink" $value] == 0} { 29 | set value 0 30 | } elseif {[string compare -nocase "uplink" $value] == 0} { 31 | set value 1 32 | } elseif {[string compare -nocase "switchable" $value] == 0} { 33 | set value 2 34 | } 35 | add_prop $node "xlnx,modeint" $value hexint $dts_file 36 | } -------------------------------------------------------------------------------- /tmrctr/data/tmrctr.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc tmrctr_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | set dts_file [set_drv_def_dts $drv_handle] 19 | pldt append $node compatible "\ \, \"xlnx,xps-timer-1.00.a\"" 20 | set proctype [get_hw_family] 21 | if {[regexp "microblaze" $proctype match]} { 22 | gen_dev_ccf_binding $drv_handle "s_axi_aclk" 23 | } else { 24 | set ip [hsi::get_cells -hier $drv_handle] 25 | set clk [hsi::get_pins -of_objects $ip "S_AXI_ACLK"] 26 | if {[llength $clk] } { 27 | set freq [hsi get_property CLK_FREQ $clk] 28 | add_prop $node "clock-frequency" $freq hexint $dts_file 29 | } 30 | } 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2021-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc ptp_1588_timer_syncer_generate {drv_handle} { 17 | set node [get_node $drv_handle] 18 | if {$node == 0} { 19 | return 20 | } 21 | set dts_file [set_drv_def_dts $drv_handle] 22 | set compatible [get_comp_str $drv_handle] 23 | set ip_ver [get_comp_ver $drv_handle] 24 | if {$ip_ver >= "2.0"} { 25 | set keyval [pldt append $node compatible "\ \, \"xlnx,timer-syncer-1588-3.0\""] 26 | } elseif {[string match -nocase $ip_ver "1.0"]} { 27 | set keyval [pldt append $node compatible "\ \, \"xlnx,timer-syncer-1588-1.0\""] 28 | } 29 | set_drv_prop $drv_handle compatible "$compatible" $node noformating 30 | } 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /cpu_cortexa9/data/cpu_cortexa9.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # (C) Copyright 2014-2022 Xilinx, Inc. 3 | # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 4 | # 5 | # This program is free software; you can redistribute it and/or 6 | # modify it under the terms of the GNU General Public License as 7 | # published by the Free Software Foundation; either version 2 of 8 | # the License, or (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | 16 | proc cpu_cortexa9_generate {drv_handle} { 17 | global dtsi_fname 18 | set dtsi_fname "zynq/zynq-7000.dtsi" 19 | update_system_dts_include [file tail ${dtsi_fname}] 20 | set bus_name "amba" 21 | set fields [split [get_ip_property $drv_handle NAME] "_"] 22 | set cpu_nr [lindex $fields end] 23 | set ip_name [get_ip_property $drv_handle IP_NAME] 24 | set cpu_node [create_node -n "&ps7_cortexa9_${cpu_nr}" -d "pcw.dtsi" -p root -h $drv_handle] 25 | add_prop $cpu_node "xlnx,ip-name" $ip_name string "pcw.dtsi" 26 | add_prop $cpu_node "bus-handle" $bus_name reference "pcw.dtsi" 27 | gen_drv_prop_from_ip $drv_handle 28 | set amba_node [create_node -n "&${bus_name}" -d "pcw.dtsi" -p root] 29 | } 30 | 31 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/vcu118-rev2.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-property/ pcs-handle ; 4 | /delete-property/ managed ; 5 | /delete-property/ xlnx,switch-x-sgmii ; 6 | /delete-node/ mdio; 7 | axi_ethernet_mdio: mdio { 8 | #address-cells = <1>; 9 | #size-cells = <0>; 10 | phy0: phy@3 { 11 | device_type = "ethernet-phy"; 12 | ti,sgmii-ref-clock-output-enable; 13 | ti,dp83867-rxctrl-strap-quirk; 14 | ti,rx-internal-delay = <0x8>; 15 | ti,tx-internal-delay = <0xa>; 16 | ti,fifo-depth = <0x1>; 17 | reg = <3>; 18 | }; 19 | }; 20 | }; 21 | 22 | &axi_iic_0 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | i2c-mux@75 { 26 | compatible = "nxp,pca9548"; 27 | #address-cells = <1>; 28 | #size-cells = <0>; 29 | reg = <0x75>; 30 | i2c@3 { 31 | #address-cells = <1>; 32 | #size-cells = <0>; 33 | reg = <3>; 34 | eeprom@54 { 35 | compatible = "atmel,24c08"; 36 | reg = <0x54>; 37 | }; 38 | }; 39 | }; 40 | i2c-mux@74 { 41 | compatible = "nxp,pca9548"; 42 | #address-cells = <1>; 43 | #size-cells = <0>; 44 | reg = <0x74>; 45 | i2c@0 { 46 | #address-cells = <1>; 47 | #size-cells = <0>; 48 | reg = <0>; 49 | si570: clock-generator@5d { 50 | #clock-cells = <0>; 51 | compatible = "silabs,si570"; 52 | temperature-stability = <50>; 53 | reg = <0x5d>; 54 | factory-fout = <156250000>; 55 | clock-frequency = <148500000>; 56 | }; 57 | }; 58 | }; 59 | }; 60 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2024.2/BOARD/zc1254-reva.dtsi: -------------------------------------------------------------------------------- 1 | // SPDX-License-Identifier: GPL-2.0+ 2 | /* 3 | * dts file for Xilinx ZynqMP ZC1254 4 | * 5 | * (C) Copyright 2015-2022 Xilinx, Inc. 6 | * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. 7 | * 8 | * Michal Simek 9 | * Siva Durga Prasad Paladugu 10 | */ 11 | 12 | 13 | / { 14 | model = "ZynqMP ZC1254 RevA"; 15 | compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; 16 | 17 | aliases { 18 | serial0 = &uart0; 19 | serial1 = &dcc; 20 | spi0 = &qspi; 21 | }; 22 | 23 | }; 24 | 25 | 26 | &qspi { 27 | flash@0 { 28 | compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 29 | #address-cells = <1>; 30 | #size-cells = <1>; 31 | reg = <0x0>; 32 | spi-tx-bus-width = <4>; 33 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 34 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ 35 | partition@0 { /* for testing purpose */ 36 | label = "qspi-fsbl-uboot"; 37 | reg = <0x0 0x100000>; 38 | }; 39 | partition@100000 { /* for testing purpose */ 40 | label = "qspi-linux"; 41 | reg = <0x100000 0x500000>; 42 | }; 43 | partition@600000 { /* for testing purpose */ 44 | label = "qspi-device-tree"; 45 | reg = <0x600000 0x20000>; 46 | }; 47 | partition@620000 { /* for testing purpose */ 48 | label = "qspi-rootfs"; 49 | reg = <0x620000 0x5E0000>; 50 | }; 51 | }; 52 | }; 53 | -------------------------------------------------------------------------------- /device_tree/data/kernel_dtsi/2025.1/BOARD/vcu118-rev2.0.dtsi: -------------------------------------------------------------------------------- 1 | &axi_ethernet_0 { 2 | phy-handle = <&phy0>; 3 | /delete-property/ pcs-handle ; 4 | /delete-property/ managed ; 5 | /delete-property/ xlnx,switch-x-sgmii ; 6 | /delete-node/ mdio; 7 | axi_ethernet_mdio: mdio { 8 | #address-cells = <1>; 9 | #size-cells = <0>; 10 | phy0: phy@3 { 11 | device_type = "ethernet-phy"; 12 | ti,sgmii-ref-clock-output-enable; 13 | ti,dp83867-rxctrl-strap-quirk; 14 | ti,rx-internal-delay = <0x8>; 15 | ti,tx-internal-delay = <0xa>; 16 | ti,fifo-depth = <0x1>; 17 | reg = <3>; 18 | }; 19 | }; 20 | }; 21 | 22 | &axi_iic_0 { 23 | #address-cells = <1>; 24 | #size-cells = <0>; 25 | i2c-mux@75 { 26 | compatible = "nxp,pca9548"; 27 | #address-cells = <1>; 28 | #size-cells = <0>; 29 | reg = <0x75>; 30 | i2c@3 { 31 | #address-cells = <1>; 32 | #size-cells = <0>; 33 | reg = <3>; 34 | eeprom@54 { 35 | compatible = "atmel,24c08"; 36 | reg = <0x54>; 37 | }; 38 | }; 39 | }; 40 | i2c-mux@74 { 41 | compatible = "nxp,pca9548"; 42 | #address-cells = <1>; 43 | #size-cells = <0>; 44 | reg = <0x74>; 45 | i2c@0 { 46 | #address-cells = <1>; 47 | #size-cells = <0>; 48 | reg = <0>; 49 | si570: clock-generator@5d { 50 | #clock-cells = <0>; 51 | compatible = "silabs,si570"; 52 | temperature-stability = <50>; 53 | reg = <0x5d>; 54 | factory-fout = <156250000>; 55 | clock-frequency = <148500000>; 56 | }; 57 | }; 58 | }; 59 | }; 60 | --------------------------------------------------------------------------------