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/docs/Creating_AFI.md:
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1 | ---
2 | layout: default
3 | ---
4 |
5 | # Creating an Amazon FPGA Image (AFI)
6 |
7 | This document guides you through the steps to create an AWS Amazon FPGA Image (AFI) which can run on AWS EC2 F1 instance to verify that the design works in hardware. It assumes that a full system (Vitis project) is built which consists of an *host* application (executable file) and an FPGA binary file (.xclbin).
8 |
9 | ### Create an AFI
10 |
11 | #### AWSEducate users follow [these steps](Creating_AFI_AWSEducate.md) to create an AFI
12 |
13 |
14 | To execute the application on F1, the following files are needed:
15 |
16 | - Host application (executable file)
17 | - Amazon FPGA Image (awsxclbin)
18 |
19 | The awsxclbin is an Amazon specific version of the FPGA binary file (xclbin) produced by the Vitis software.
20 |
21 | The awsxclbin can be created by running the *create\_vitis\_afi.sh* script which is included in the [aws-fpga GitHub repository](https://github.com/aws/aws-fpga/tree/master/Vitis#2-create-an-amazon-fpga-image-afi).
22 |
23 | The script can be found in the following location in the aws-fpga repository:
24 |
25 | ```sh
26 | $VITIS_DIR/tools/create_vitis_afi.sh
27 | ```
28 |
29 | 1. Before running the commands below, make sure the Vitis setup script has been sourced (the following command assumes the aws-fpga Git repository is cloned to the user home area)
30 |
31 | ```sh
32 | source ~/aws-fpga/vitis_setup.sh
33 | ```
34 |
35 | 1. Set up S3 bucket region
36 |
37 | For instance:
38 |
39 | ```sh
40 | aws configure set region us-east-1
41 | ```
42 |
43 | Note: the region may change for your instance. This command will create/update the `~/.aws/config` file
44 |
45 | 1. Create an AFI by running the `create_vitis_afi.sh` script and wait for the completion of the AFI creation process
46 |
47 | ```sh
48 | $VITIS_DIR/tools/create_vitis_afi.sh -xclbin=.xclbin -s3_bucket= -s3_dcp_key= -s3_logs_key=
49 | ```
50 |
51 | In the above command, set your *xclbin* file as ``; the Amazon S3 ``, ``, and `` with the names you had given when running CLI script. You can choose any valid folder name for the dcp and logs folder. The Amazon S3 bucket name should match an S3 bucket you have set up.
52 |
53 | Learn more about setting up S3 buckets [here](https://github.com/aws/aws-fpga/blob/master/Vitis/docs/Setup_AWS_CLI_and_S3_Bucket.md)
54 |
55 | The `create_vitis_afi.sh` script does the following:
56 |
57 | - Starts a background process to create the AFI
58 | - Generates a `*_afi_id.txt` which contains the FPGA Image Identifier (or AFI ID) and Global FPGA Image Identifier (or AGFI ID) of the generated AFIs
59 | - Creates the `*.awsxclbin` AWS FPGA binary file which is passed to the host application to determine which AFI should be loaded to the FPGA.
60 | - Uploads the `*.xclbin` to the AWS cloud for processing.
61 |
62 | ## Check the AFI status
63 |
64 | The AFI will become available after some time in the AWS cloud and can then be used to program the FPGA in an AWS EC2 F1 instance. To check the AFI status, the AFI ID is required.
65 |
66 | * In the directory the `create_vitis_afi.sh` script was run, enter the following command to find the AFI ID
67 |
68 | ```sh
69 | cat *afi_id.txt
70 | ```
71 |
72 | * Enter the `describe-fpga-images` API command to check the status of the AFI generation process:
73 |
74 | ```sh
75 | aws ec2 describe-fpga-images --fpga-image-ids
76 | ```
77 |
78 | * For example,
79 |
80 | ```sh
81 | aws ec2 describe-fpga-images --fpga-image-ids afi-0b9167434a1c74ba9
82 | ```
83 |
84 | Or you can use a handy shortcut to pass the AFI id directly to the command. Read the file, get the second row, remove `"` and `,` and finally remove everything before the colon included
85 |
86 | ```sh
87 | aws ec2 describe-fpga-images --fpga-image-ids $(cat *afi_id.txt | sed -n '2p' | tr -d '",' | sed 's/.*://')
88 | ```
89 |
90 | Note: When AFI creation is in progress, the *State* will be `pending`. When the AFI creation is finished, the output should show `available`:
91 |
92 | ```sh
93 | ...
94 | "State": {
95 | "Code": "available"
96 | },
97 |
98 | ...
99 | ```
100 |
101 | Wait until the AFI becomes available before proceeding to execute on the F1 instance.
102 |
103 | ## Regenerate .awsxclbin
104 |
105 | You can regenerate the `.awsxclbin` file as long as you have access to `*agfi_id.txt` and `*.xclbin` files
106 |
107 | 1. Edit these variable with the corresponding names
108 |
109 | ```sh
110 | export xclbin=
111 | export agfi_id=<*_agfi_id.txt>
112 | export awsxclbin=
113 | ```
114 |
115 | 1. Generate `.awsxclbin` file
116 |
117 | ```sh
118 | xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${agfi_id} -o ${awsxclbin}.awsxclbin
119 | ```
120 |
121 | ---------------------------------------
122 |
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/docs/Creating_AFI_AWSEducate.md:
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1 | ---
2 | layout: default
3 | ---
4 |
5 | # Creating an Amazon FPGA Image (AFI) using AWSEducate
6 |
7 | This document guides you through the steps to create an AWS Amazon FPGA Image (AFI), when using AWSEducate instance, which can run on AWS EC2 F1 instance to verify that the design works in hardware. It assumes that a full system (Vitis project) is built which consists of an *host* application (executable file) and an FPGA binary file (.xclbin).
8 |
9 | ### Create an AFI
10 |
11 | 1. Setup CLI and Create S3 bucket
12 |
13 | - Create an empty file called *credentials* using the following commands
14 |
15 | ```
16 | cd
17 | mkdir .aws
18 | cd .aws
19 | gedit credentials
20 | ```
21 |
22 | - Go to the Vocareum window and click on **Account Details**
23 | - Click on the **Show** button
24 | - Copy the content into the *credentials* file, save the file, and exit
25 | - Create a S3 bucket which will be used for registering xclbin (Note: touch command below is necessary to have non-empty folders. The files will be copied into these sub-folders
26 |
27 | ```
28 | aws s3 mb s3:// --region us-east-1
29 | aws s3 mb s3:///
30 | touch FILES_GO_HERE.txt
31 | aws s3 cp FILES_GO_HERE.txt s3:////
32 | aws s3 mb s3:///
33 | touch FILES_GO_HERE.txt
34 | aws s3 cp FILES_GO_HERE.txt s3:////
35 | ```
36 |
37 | 1. Configure aws by executing following command and providing credentials
38 |
39 | Note that anytime you want to create AFI, the credentials file content must be updated. You must rerun the command every time before you run the create_visit_afi.sh script if this is a new session
40 |
41 | ```
42 | aws configure
43 | AWS Access Key ID [****************J5NS]:
44 | AWS Secret Access Key [****************N4bG]:
45 | Default region name [None]: us-east-1
46 | Default output format [None]: json
47 | ```
48 |
49 | 2. Submit the xclbin to generate AFI (with extension awsxclbin) using the following command
50 |
51 | ```
52 | $VITIS_DIR/tools/create_vitis_afi.sh -xclbin= -s3_bucket= -s3_dcp_key= -s3_logs_key=
53 | ```
54 |
55 | The bucket-name, dcp-folder-name, and logs-folder-name should match the one used while creating them
56 | 3. Once submitted successfully, an *time_stamp*\_afi\_id.txt file will be created. Open the file and make a note of the afi-id. Execute the following command to see the status of the AFI:
57 |
58 | `aws ec2 describe-fpga-images --fpga-image-ids `
59 |
60 | Wait for about 30 minutes before the status changes from *pending* to **available**. You can log out and login back to check the status
61 |
62 |
63 | ## Regenerate .awsxclbin
64 |
65 | You can regenerate the `.awsxclbin` file as long as you have access to `*agfi_id.txt` and `*.xclbin` files
66 |
67 | 1. Edit these variable with the corresponding names
68 |
69 | ```sh
70 | export xclbin=
71 | export agfi_id=<*_agfi_id.txt>
72 | export awsxclbin=
73 | ```
74 |
75 | 1. Generate `.awsxclbin` file
76 |
77 | ```sh
78 | xclbinutil -i $xclbin --remove-section PARTITION_METADATA --remove-section SYSTEM_METADATA --replace-section BITSTREAM:RAW:${agfi_id} -o ${awsxclbin}.awsxclbin
79 | ```
80 |
81 | ---------------------------------------
82 |
--------------------------------------------------------------------------------
/docs/Gemfile:
--------------------------------------------------------------------------------
1 | # frozen_string_literal: true
2 |
3 | source 'https://rubygems.org'
4 |
5 | gemspec
6 |
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/docs/README.md:
--------------------------------------------------------------------------------
1 |
4 |
5 | # Xilinx University Program Vitis Tutorial
6 |
7 | ## Introduction
8 |
9 | Welcome to the XUP Vitis-based Compute Acceleration tutorial. These labs will provide hands-on experience using the [Vitis unified software platform](https://www.xilinx.com/products/design-tools/vitis.html) with Xilinx FPGA hardware. You will learn how to develop applications using the Vitis development environment that supports OpenCL/C/C++ and RTL kernels.
10 |
11 | The tutorial instructions target the following hardware and software:
12 |
13 | * Vitis 2021.1
14 | * AWS EC2 F1 f1.2xlarge (cloud)
15 |
16 | This tutorial shows you how to use Vitis with AWS EC2 F1. Sources and precompiled solutions are provided for AWS EC2 F1 x2.large. You may be able to use the Vitis tutorial instructions with other cloud providers, and other hardware.
17 |
18 |
19 | ## Run Tutorial
20 |
21 | You can run this tutorial in different ways.
22 |
23 | 1. If you have an Alveo board, you can run all parts of the tutorial on a local machine.
24 |
25 | 1. You can use the Vitis software in the cloud, with hardware in the cloud (AWS F1).
26 | * For running your design in AWS you will need to [create an AFI](Creating_AFI.md)
27 |
28 | 1. You can use the Vitis software on a local machine for building designs, and only switch to the cloud to deploy in hardware, make sure you build for the correct shell.
29 |
30 | Once you have decided how you want to run the tutorial, follow the appropriate instructions below.
31 |
32 | ### XUP AWS Tutorial
33 |
34 | If you are attending an instructor-led XUP AWS tutorial, preconfigured AWS F1 instances will be provided for you. Use the following instructions to [connect to your assigned AWS XUP tutorial instance](./setup_xup_aws_workshop.md)
35 |
36 | ### AWS EC2 F1
37 |
38 | An [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) (Amazon Machine Image) is available with the Xilinx Vitis software preinstalled. This can be used to target AWS EC2 F1 hardware. An AMI is like a Virtual Machine image. You can use this AMI and the following instructions to [set up and connect to an AWS instance](./setup_aws.md)
39 |
40 | You can also install [Vitis unified software platform](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html) on your local machine, build design offline, and use AWS F1 hardware for testing. See the Amazon guide to use [AWS EC2 FPGA Development Kit](https://github.com/aws/aws-fpga) for details on setting up your machine.
41 |
42 | ### Local computer
43 |
44 | To use your own computer, [install and set up Vitis and install the Alveo U200 packages](./setup_local_computer.md)
45 |
46 | ### Clone repository
47 |
48 | You also need to clone this repository to get a copy of the source code, the lab steps consider that this repository is cloned directly in the home directory (\~).
49 |
50 | ```sh
51 | git clone git@github.com:Xilinx/xup_compute_acceleration.git ~
52 | ```
53 |
54 | ## Tutorial overview
55 |
56 | The complete set of labs includes the following modules; it is recommended to complete each lab before proceeding to the next
57 |
58 | 1. [**Introduction to Vitis Part 1**](Vitis_intro-1.md):
59 | This lab shows you how to use the Vitis GUI to create a new project using a simple vector addition example. You will run CPU emulation (`sw_emu`) to verify functional correctness of the example design.
60 |
61 | 1. [**Introduction to Vitis Part 2**](Vitis_intro-2.md):
62 | In this lab you will continue with the previous example and run hardware emulation (`hw_emu`) to verify the functionality of the generated hardware design and profile the whole application. You will then use *AWS F1* or *on-premise* hardware to validate the design using a pre-generated host application and FPGA binary.
63 |
64 | 1. [**Improving Performance**](Improving_Performance_lab.md):
65 | This lab shows how bandwidth can be improved, and thus system performance, by using wider data path and transferring data in parallel using multiple memory banks.
66 |
67 | 1. [**Optimization**](Optimization_lab.md):
68 | This lab guides you through the steps to analyze various generated reports and then apply optimization techniques, such as `DATAFLOW` on the host program and `PIPELINING` on kernel side to improve throughput and data transfer rate.
69 |
70 | 1. [**Vision Lab**](Vision_lab.md):
71 | In this lab you will create a Vitis design using the command line. The design uses two kernels from the [Vitis Accelerated Libraries](https://xilinx.github.io/Vitis_Libraries/), **image resize** and **image resize & blur**. You will run software emulation and test the kernels in hardware.
72 |
73 | 1. [**PYNQ Labs**](pynq_labs.md):
74 | In this series of labs you will learn how to use PYNQ for easier user of Xilinx compute acceleration platforms.
75 |
76 | ### Advanced labs
77 |
78 | These labs are intended for hardware designers who may want to use RTL to build kernels, and learn how to use lower level hardware debug features in Vitis.
79 |
80 | 1. [**RTL-Kernel**](rtl_kernel_lab.md):
81 | This lab guides you through the steps involved in using a RTL Kernel wizard to wrap a user RTL-based IP so the generated IP can be used in a Vitis project and application development.
82 |
83 | 1. [**Hardware Debugging**](debug_lab.md):
84 | This lab will show you how to carry out host application debug, and debug of the hardware kernel.
85 |
86 | 1. [**Streaming**](streaming_lab.md):
87 | This lab will show you how to incorporate kernels having streaming interfaces.
88 |
89 | ---------------------------------------
90 |
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/docs/Vitis_intro-1.md:
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1 | ---
2 | layout: default
3 | ---
4 |
5 | # Introduction to Vitis Part 1
6 |
7 | ## Introduction
8 |
9 | This lab guides you through the steps involved in creating a Vitis project using Graphical User Interface (GUI). After creating the project, you will run software emulation to verify the functionality of the design.
10 |
11 | ### References
12 |
13 | For more details on the Vitis IDE see the Vitis documentation for [Creating a Vitis IDE Project](https://docs.xilinx.com/r/2021.1-English/ug1393-vitis-application-acceleration/Creating-a-Vitis-IDE-Project).
14 |
15 |
16 | ### Description of example application
17 |
18 | This lab uses an example application available in Vitis. It consists of a host application and kernel (written in C++/OpenCL). The kernel is a simple vector addition. The elements of 2 vectors (A & B) are added together, and the result returned in a third array (C). The host application initializes the two input arrays, send data to the kernel, and reads back the result.
19 |
20 | You will compile and test a software only version of the application. The *vector add* kernel will then be implemented as a hardware kernel. You will first build and run a *Software Emulation* version of the design, followed by a *Hardware Emulation* version which will run a simulation of the hardware model of the kernel along with the host application. You will then test the design with the hardware kernel running in the FPGA in the next part of the lab.
21 |
22 | ## Objectives
23 |
24 | After completing this lab (part 1 and part 2), you will learn how to:
25 |
26 | * Create a project using the Vitis GUI
27 | - Run *Software Emulation* to verify the functionality of a design
28 | - Run Hardware Emulation to verify the functionality of the generated hardware design
29 | - Build the system and test it in hardware
30 | - Perform profile and application timeline analysis in hardware emulation
31 |
32 | ## Steps
33 |
34 | ### Create a Vitis Project
35 |
36 | 1. If you have not run [lab setup](setup_xup_aws_workshop.md#lab-setup), run it now
37 |
38 | 1. In a terminal, start the Vitis GUI by running
39 |
40 | ```sh
41 | vitis
42 | ```
43 | 1. Set the Vitis *workspace* to a new empty folder, such as `/home//workspace` and click **Launch**
44 |
45 | 
46 |
47 | 1. The Vitis IDE Welcome page will be displayed
48 |
49 | 
50 |
51 | 1. Create a new application project
52 |
53 | Click **Create Application Project** from Welcome page, or **File > New > Application Project** to create a new application
54 |
55 | 
56 |
57 | 1. Click **Next >** in the first window
58 |
59 | 
60 |
61 | 1. Select `xilinx_aws-vu9p-f1_shell-v04261818_201920_2` platform and click **Next >**
62 |
63 | If you do not see this platform, check you followed the [lab set up instructions](setup_xup_aws_workshop.md#lab-setup) to set the `PLATFORM_REPO_PATHS` variable. You can select the platform by clicking the `+` button and browsing to `~/aws-fpga/Vitis/aws_platform/` and selecting `xilinx_aws-vu9p-f1_shell-v04261818_201920_2`
64 |
65 | 
66 |
67 | 1. Name the project `vadd` and click **Next >**
68 |
69 | 
70 |
71 | 1. Select `Empty Application` in the *Templates* window and click **Finish**
72 |
73 | 
74 |
75 | The project is generated. Observe the top-level folder is called vadd\_system, under which three sub-folders **(vadd\_kernels, vadd\_system\_hw\_link, vadd)** are generated. The **vadd\_kernels** folder will hold all the kernel related files, the **vadd\_system\_hw\_link** will hold all linked kernel related files, and the **vadd** folder will hold all the host application related files.
76 |
77 | 
78 |
79 | Since the _Empty_ project template was selected, the **vadd** and **vadd_kernels** will have empty **src** folders
80 |
81 | 1. In the `Explorer` view, expand and right-click on **vadd\_system > vadd > src** and select **Import Sources...**
82 |
83 | 
84 |
85 | 1. In the *Import Sources* window, click *Browse* and navigate to `~/xup_compute_acceleration/sources/vadd_lab/` and click **Open**
86 |
87 | 1. Select the **vadd.cpp, xcl2.cpp, and xcl2.hpp** files as they are part of the host code and click **Finish**
88 |
89 | 
90 |
91 | Expand the `src` folder in the `Explorer` view to verify that the three files were added.
92 |
93 | 1. Similarly, import the hardware kernel code (**krnl\_vadd.cpp**) under the **vadd\_system > vadd\_kernels > src** folder
94 |
95 | 1. In the *Explorer* view, double-click on the **vadd\_kernels.prj** under the **vadd\_system > vadd\_kernels** folder to open the corresponding *Hardware Kernel Project Settings*
96 |
97 | 
98 |
99 | 1. Click the **Add Hardware function** button () on the *Hardware Functions* panel's ribbon
100 |
101 | 
102 |
103 | 1. Select **krnl_vadd(int \*, int \*, int \*, unsigned int) - krnl_vadd.cpp** in the *Add Hardware Functions* window and click **OK**
104 |
105 | 
106 |
107 | 1. Verify that *krnl_vadd* is added as a *Hardware Function*
108 |
109 | 
110 |
111 | ### Build and Run Software Emulation
112 |
113 | 1. Select the **vadd_system** tab in the project settings view
114 |
115 | 1. Check the *Active build configuration* is set to **Emulation-SW** on the upper right corner of *System Project Settings* view
116 |
117 | 1. In the *Explore* view, select **vadd_system** and build the design by clicking the hammer button () on top buttons bar, or right click `vadd_system` and select **Build Project**
118 |
119 | 
120 |
121 | This step compiles each of the kernels, links them, and compiles the host application
122 |
123 | 1. Run Software Emulation
124 |
125 | To launch software emulation, select `vadd_system` either in the **Assistant** view or in the **Explorer** view and then click on the run button 
126 |
127 | 1. Select the **Launch SW Emulator** option and click **OK**
128 |
129 | Observe the application has run and the output is displayed in the *Console* view
130 |
131 | ```console
132 | Found Platform
133 | Platform Name: Xilinx
134 | INFO: Reading /home/centos/workspace/vadd_system/Emulation-SW/binary_container_1.xclbin
135 | Loading: '/home/centos/workspace/vadd_system/Emulation-SW/binary_container_1.xclbin'
136 | Trying to program device[0]: xilinx_aws-vu9p-f1_shell-v04261818_201920_2
137 | Device[0]: program successful!
138 | Running Vector add with 32768 elements
139 | Launching Hardware Kernel...
140 | Getting Hardware Results...
141 | TEST PASSED
142 | ```
143 |
144 | You can leave the project open as you will continue from this step in the second part of this lab
145 |
146 | ## Conclusion
147 |
148 | In this lab, you used Vitis to create a vector add project using the provided source code. You then ran the design using the software emulation flow.
149 |
150 | ---------------------------------------
151 |
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/docs/report_issues.md:
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1 | ---
2 | layout: default
3 | ---
4 |
5 | # Report an Issue
6 |
7 | This page covers the basics to report an issue either to your instructor or using the built-in GitHub Issues tracker
8 |
9 | When reporting an issue provide the following information.
10 |
11 | - A brief description of the issue and how to reproduce it
12 |
13 | - Section in lab or page you found the issue
14 |
15 | - How you are running the tutorial? Cloud (AWS) or on-premises
16 |
17 | - Screenshots or code snippets if appropriate
18 | - Check how to [create and highlight code](https://docs.github.com/en/github/writing-on-github/creating-and-highlighting-code-blocks)
19 |
20 | - Tools and OS versions if the issue is in a lab
21 |
22 | - `vitis -version`
23 | - `xbutil version`
24 | - `lsb_release -a`
25 |
26 |
27 | Report the issue to your instructor or open a [new issue](https://github.com/Xilinx/xup_compute_acceleration/issues).
28 | It is always a good idea to check previous issues to in case that it has been already resolved.
29 |
30 | ---------------------------------------
31 |
60 |
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/docs/setup_aws.md:
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1 | ---
2 | layout: default
3 | ---
4 |
5 | # Connecting to AWS
6 |
7 | To get started with AWS, you will need an Amazon account. You will also need AWS credit to run the tutorial. If you are a professor or a student, you may be eligible to free credit by registering with [AWS educate](https://aws.amazon.com/education/awseducate/).
8 |
9 | ## Set up an AWS instance
10 |
11 | Use [this guide](https://docs.aws.amazon.com/efs/latest/ug/gs-step-one-create-ec2-resources.html) to setup and AWS instance. Make sure to use the [FPGA Developer AMI version 1.9.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ/ref=portal_asin_url) which includes Xilinx Vitis 2020.1 tools that this tutorial is based on.
12 |
13 | ### Login into the AWS and starting an F1 instance
14 |
15 | 1. Once you have an account, log in to the EC2 AWS Console:
16 |
17 | https://console.aws.amazon.com/ec2
18 |
19 | This should bring you to the EC2 dashboard (Elastic Compute).
20 |
21 | In the EC2 dashboard, select Launch Instance. From here you should be able to start your instance.
22 |
23 | ## Additional setup
24 |
25 | You may want to do some additional setup to allow you to VNC to your instance. You can also follow the instructions in [Setup XUP AWS Workshop](setup_xup_aws_workshop.md) to connect to your instance.
26 |
27 | ### VNC server setup
28 |
29 | When setting up an instance for the first time, you need to install vncserver software.
30 |
31 | #### Install VNC server
32 | In a terminal, execute the following commands
33 |
34 | ```sh
35 | sudo yum install -y tigervnc-server
36 | sudo yum groupinstall -y "Server with GUI"
37 | ```
38 |
39 | When launching vncserver, you will be prompted to set up a password that you will need later.
40 |
41 | ### Start vncserver
42 |
43 | Each time you start an instance, you will need to start vncserver
44 |
45 | ```sh
46 | vncserver -geometry 1920x1080
47 | ```
48 |
49 | 1. You can choose your preferred geometry (screen size)
50 |
51 | 1. You should see a status message in the terminal once *vncserver* has started.
52 |
53 | 1. Take note of the number after the “:”
54 |
55 | 1. In this case, 1. This is the port the VNC viewer will connect to on the VNC server and needs to be specified as a two digit number below: 01.
56 |
57 | 1. Connect to AWS instance from VNC viewer.
58 |
59 | 1. From VNC viewer, specify the IP address of your AWS instance, followed by the VNC port number (as identified above), in this case :1
60 |
61 | 1. When prompted, enter the VNC server password set up earlier.
62 |
63 | 1. You should then be connected to the AWS instance.
64 |
65 |
66 | ### Verify XRT and Vitis tools
67 |
68 | Open a terminal and verify that Xilinx Vitis tools have been preinstalled and are on the path:
69 |
70 | ```sh
71 | which vitis
72 | ```
73 |
74 | Note that the XRT tools are installed (/opt/xilinx/xrt) but are not included on the path by default.
75 |
76 | ```sh
77 | sudo chmod 777 /opt/xilinx/xrt/setup.sh
78 | #Source XRT every time a new terminal is open
79 | echo "source /opt/xilinx/xrt/setup.sh" >> ~/.bashrc
80 | #Reload .bashrc in the current terminal
81 | source ~/.bashrc
82 | ```
83 |
84 | ### Clone AWS-FPGA repository and set variables
85 |
86 | 1. Open a terminal
87 |
88 | 1. If you are using the Xilinx provided instances then execute the following to clone the *aws-fpga* repository and setup the Xilinx tools. `aws-fpga` includes the AWS F1 tools, Hardware Development Kit (HDK) and documentation
89 |
90 | ```sh
91 | cd ~
92 | git clone https://github.com/aws/aws-fpga -b v1.4.21
93 | echo "export PLATFORM_REPO_PATHS=~/aws-fpga/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_2/" >> ~/.bashrc
94 | echo "source /opt/xilinx/xrt/setup.sh" >> ~/.bashrc
95 | echo "source $XILINX_VITIS/settings64.sh" >> ~/.bashrc
96 | git clone https://github.com/Xilinx/xup_compute_acceleration.git
97 | source ~/.bashrc
98 | source ~/aws-fpga/vitis_setup.sh
99 | source ~/aws-fpga/vitis_runtime_setup.sh
100 | ```
101 |
102 | The previous commands will:
103 | - Clone the AWS F1 tools
104 | - Setup the platform directory
105 | - Clone this repository to get source code
106 | - Source XRT
107 | - Source AWS F1 tools
108 |
109 | 1. If you are using the AWSEducate instances then execute the following to clone the *xup\_compute\_acceleration* repository. No additional variables need to be set as the provided AMI has all necessary files including `aws-fpga` repository cloning, the AWS F1 tools, Hardware Development Kit (HDK) and documentation
110 |
111 | ```sh
112 | git clone https://github.com/Xilinx/xup_compute_acceleration.git
113 | ```
114 |
115 | The previous command will:
116 | - Clone this repository to get source code and solutions
117 |
118 | For more details see: https://github.com/aws/aws-fpga/blob/master/Vitis/README.md
119 |
120 | ---------------------------------------
121 |
--------------------------------------------------------------------------------
/docs/setup_local_computer.md:
--------------------------------------------------------------------------------
1 | ---
2 | layout: default
3 | ---
4 |
5 | # Setup Vitis on your own computer
6 |
7 | To run (or build) these labs on your own computer, install Vitis. For non-commercial/academic use, Vitis licenses are free.
8 |
9 | [Download Vitis](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html) and install the tools. Make sure you install the version targeted in this tutorial.
10 |
11 | [Download XRT and the U200 package](https://www.xilinx.com/products/boards-and-kits/alveo/u200.html#gettingStarted) for your computer, and install both packages.
12 |
13 | ## Setup the tools
14 |
15 | Add the following to your environment setup.
16 |
17 | ```sh
18 | source /opt/xilinx/xrt/setup.(c)sh
19 | source $XILINX_VITIS/settings64.(c)sh
20 | export PLATFORM_REPO_PATHS=$ALVEO_PLATFORM_INSTALLATION_DIRECTORY
21 | ```
22 |
23 | ---------------------------------------
24 |
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https://raw.githubusercontent.com/Xilinx/xup_compute_acceleration/569955f50bb7ad972adaf60e48085323ff4e0aec/solutions/vision_lab/src/data/fish_wallpaper.jpg
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/solutions/vision_lab/src/data/fish_wallpaper_small.jpg:
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https://raw.githubusercontent.com/Xilinx/xup_compute_acceleration/569955f50bb7ad972adaf60e48085323ff4e0aec/solutions/vision_lab/src/data/fish_wallpaper_small.jpg
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/solutions/vision_lab/vision_example.awsxclbin:
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https://raw.githubusercontent.com/Xilinx/xup_compute_acceleration/569955f50bb7ad972adaf60e48085323ff4e0aec/solutions/vision_lab/vision_example.awsxclbin
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/solutions/vitis_intro_lab/21_08_02-195528_afi_id.txt:
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1 | {
2 | "FpgaImageId": "afi-06ed13aa766b43d90",
3 | "FpgaImageGlobalId": "agfi-0b7756c19a2fe4c13"
4 | }
5 |
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/solutions/vitis_intro_lab/21_08_02-195528_agfi_id.txt:
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1 | agfi-0b7756c19a2fe4c13
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/solutions/vitis_intro_lab/binary_container_1.awsxclbin:
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https://raw.githubusercontent.com/Xilinx/xup_compute_acceleration/569955f50bb7ad972adaf60e48085323ff4e0aec/solutions/vitis_intro_lab/binary_container_1.awsxclbin
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/solutions/vitis_intro_lab/xrt.ini:
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1 | [Debug]
2 | opencl_summary=true
3 | power_profile=false
4 | opencl_trace=true
5 | lop_trace=false
6 | xrt_trace=false
7 | data_transfer_trace=coarse
8 | stall_trace=off
9 | app_debug=true
10 |
11 |
--------------------------------------------------------------------------------
/sources/common/xcl2.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #include "xcl2.hpp"
37 | #include
38 | #include
39 | #if defined(_WINDOWS)
40 | #include
41 | #else
42 | #include
43 | #endif
44 |
45 | namespace xcl {
46 | std::vector get_devices(const std::string &vendor_name) {
47 | size_t i;
48 | cl_int err;
49 | std::vector platforms;
50 | OCL_CHECK(err, err = cl::Platform::get(&platforms));
51 | cl::Platform platform;
52 | for (i = 0; i < platforms.size(); i++) {
53 | platform = platforms[i];
54 | OCL_CHECK(err, std::string platformName =
55 | platform.getInfo(&err));
56 | if (platformName == vendor_name) {
57 | std::cout << "Found Platform" << std::endl;
58 | std::cout << "Platform Name: " << platformName.c_str() << std::endl;
59 | break;
60 | }
61 | }
62 | if (i == platforms.size()) {
63 | std::cout << "Error: Failed to find Xilinx platform" << std::endl;
64 | exit(EXIT_FAILURE);
65 | }
66 | // Getting ACCELERATOR Devices and selecting 1st such device
67 | std::vector devices;
68 | OCL_CHECK(err,
69 | err = platform.getDevices(CL_DEVICE_TYPE_ACCELERATOR, &devices));
70 | return devices;
71 | }
72 |
73 | std::vector get_xil_devices() { return get_devices("Xilinx"); }
74 |
75 | std::vector
76 | read_binary_file(const std::string &xclbin_file_name) {
77 | std::cout << "INFO: Reading " << xclbin_file_name << std::endl;
78 | FILE *fp;
79 | if ((fp = fopen(xclbin_file_name.c_str(), "r")) == NULL) {
80 | printf("ERROR: %s xclbin not available please build\n",
81 | xclbin_file_name.c_str());
82 | exit(EXIT_FAILURE);
83 | }
84 | // Loading XCL Bin into char buffer
85 | std::cout << "Loading: '" << xclbin_file_name.c_str() << "'\n";
86 | std::ifstream bin_file(xclbin_file_name.c_str(), std::ifstream::binary);
87 | bin_file.seekg(0, bin_file.end);
88 | auto nb = bin_file.tellg();
89 | bin_file.seekg(0, bin_file.beg);
90 | std::vector buf;
91 | buf.resize(nb);
92 | bin_file.read(reinterpret_cast(buf.data()), nb);
93 | return buf;
94 | }
95 |
96 | bool is_emulation() {
97 | bool ret = false;
98 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
99 | if (xcl_mode != NULL) {
100 | ret = true;
101 | }
102 | return ret;
103 | }
104 |
105 | bool is_hw_emulation() {
106 | bool ret = false;
107 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
108 | if ((xcl_mode != NULL) && !strcmp(xcl_mode, "hw_emu")) {
109 | ret = true;
110 | }
111 | return ret;
112 | }
113 |
114 | bool is_xpr_device(const char *device_name) {
115 | const char *output = strstr(device_name, "xpr");
116 |
117 | if (output == NULL) {
118 | return false;
119 | } else {
120 | return true;
121 | }
122 | }
123 | }; // namespace xcl
--------------------------------------------------------------------------------
/sources/common/xcl2.hpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2018, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #pragma once
37 |
38 | #define CL_HPP_CL_1_2_DEFAULT_BUILD
39 | #define CL_HPP_TARGET_OPENCL_VERSION 120
40 | #define CL_HPP_MINIMUM_OPENCL_VERSION 120
41 | #define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY 1
42 | #define CL_USE_DEPRECATED_OPENCL_1_2_APIS
43 |
44 | // OCL_CHECK doesn't work if call has templatized function call
45 | #define OCL_CHECK(error, call) \
46 | call; \
47 | if (error != CL_SUCCESS) { \
48 | printf("%s:%d Error calling " #call ", error code is: %d\n", __FILE__, \
49 | __LINE__, error); \
50 | exit(EXIT_FAILURE); \
51 | }
52 |
53 | #include
54 | #include
55 | #include
56 | #include
57 | // When creating a buffer with user pointer (CL_MEM_USE_HOST_PTR), under the
58 | // hood
59 | // User ptr is used if and only if it is properly aligned (page aligned). When
60 | // not
61 | // aligned, runtime has no choice but to create its own host side buffer that
62 | // backs
63 | // user ptr. This in turn implies that all operations that move data to and from
64 | // device incur an extra memcpy to move data to/from runtime's own host buffer
65 | // from/to user pointer. So it is recommended to use this allocator if user wish
66 | // to
67 | // Create Buffer/Memory Object with CL_MEM_USE_HOST_PTR to align user buffer to
68 | // the
69 | // page boundary. It will ensure that user buffer will be used when user create
70 | // Buffer/Mem Object with CL_MEM_USE_HOST_PTR.
71 | template struct aligned_allocator {
72 | using value_type = T;
73 |
74 | aligned_allocator() {}
75 |
76 | aligned_allocator(const aligned_allocator &) {}
77 |
78 | template aligned_allocator(const aligned_allocator &) {}
79 |
80 | T *allocate(std::size_t num) {
81 | void *ptr = nullptr;
82 |
83 | #if defined(_WINDOWS)
84 | {
85 | ptr = _aligned_malloc(num * sizeof(T), 4096);
86 | if (ptr == NULL) {
87 | std::cout << "Failed to allocate memory" << std::endl;
88 | exit(EXIT_FAILURE);
89 | }
90 | }
91 | #else
92 | {
93 | if (posix_memalign(&ptr, 4096, num * sizeof(T)))
94 | throw std::bad_alloc();
95 | }
96 | #endif
97 | return reinterpret_cast(ptr);
98 | }
99 | void deallocate(T *p, std::size_t num) {
100 | #if defined(_WINDOWS)
101 | _aligned_free(p);
102 | #else
103 | free(p);
104 | #endif
105 | }
106 | };
107 |
108 | namespace xcl {
109 | std::vector get_xil_devices();
110 | std::vector get_devices(const std::string &vendor_name);
111 | std::vector
112 | read_binary_file(const std::string &xclbin_file_name);
113 | bool is_emulation();
114 | bool is_hw_emulation();
115 | bool is_xpr_device(const char *device_name);
116 | class Stream {
117 | public:
118 | static decltype(&clCreateStream) createStream;
119 | static decltype(&clReleaseStream) releaseStream;
120 | static decltype(&clReadStream) readStream;
121 | static decltype(&clWriteStream) writeStream;
122 | static decltype(&clPollStreams) pollStreams;
123 | static void init(const cl_platform_id &platform) {
124 | void *bar =
125 | clGetExtensionFunctionAddressForPlatform(platform, "clCreateStream");
126 | createStream = (decltype(&clCreateStream))bar;
127 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReleaseStream");
128 | releaseStream = (decltype(&clReleaseStream))bar;
129 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReadStream");
130 | readStream = (decltype(&clReadStream))bar;
131 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clWriteStream");
132 | writeStream = (decltype(&clWriteStream))bar;
133 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clPollStreams");
134 | pollStreams = (decltype(&clPollStreams))bar;
135 | }
136 | };
137 | class P2P {
138 | public:
139 | static decltype(&xclGetMemObjectFd) getMemObjectFd;
140 | static decltype(&xclGetMemObjectFromFd) getMemObjectFromFd;
141 | static void init(const cl_platform_id &platform) {
142 | void *bar =
143 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFd");
144 | getMemObjectFd = (decltype(&xclGetMemObjectFd))bar;
145 | bar = clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFromFd");
146 | getMemObjectFromFd = (decltype(&xclGetMemObjectFromFd))bar;
147 | }
148 | };
149 | class Ext {
150 | public:
151 | static decltype(&xclGetComputeUnitInfo) getComputeUnitInfo;
152 | static void init(const cl_platform_id &platform) {
153 | void *bar =
154 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetComputeUnitInfo");
155 | getComputeUnitInfo = (decltype(&xclGetComputeUnitInfo))bar;
156 | }
157 | };
158 | }
--------------------------------------------------------------------------------
/sources/graph_lab/graph.patch:
--------------------------------------------------------------------------------
1 | --- Makefile
2 | +++ Makefile
3 | @@ -43,7 +43,7 @@ help::
4 | TARGET ?= sw_emu
5 |
6 | # ################### Setting up default value of DEVICE ##############################
7 | -DEVICE ?= xilinx_u50_gen3x16_xdma_201920_3
8 | +DEVICE ?= xilinx_aws-vu9p-f1_shell-v04261818_201920_2
9 |
10 | # ###################### Setting up default value of HOST_ARCH #######################
11 | HOST_ARCH ?= x86
12 | @@ -53,11 +53,6 @@ ifeq ($(findstring zc, $(DEVICE)), zc)
13 | $(error [ERROR]: This project is not supported for $(DEVICE).)
14 | endif
15 |
16 | -# #################### Checking if DEVICE in whitelist ############################
17 | -ifneq ($(findstring u50, $(DEVICE)), u50)
18 | -$(warning [WARNING]: This project has not been tested for $(DEVICE). It may or may not work.)
19 | -endif
20 | -
21 | # ######################## Setting up Project Variables #################################
22 | MK_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
23 | XF_PROJ_ROOT ?= $(shell bash -c 'export MK_PATH=$(MK_PATH); echo $${MK_PATH%/L2/*}')
24 | @@ -107,9 +102,6 @@ CXXFLAGS += -I$(CUR_DIR)/src/
25 | ifeq ($(HOST_ARCH), x86)
26 | LDFLAGS += -L$(XILINX_HLS)/lnx64/tools/fpo_v7_0 -Wl,--as-needed -lgmp -lmpfr -lIp_floating_point_v7_0_bitacc_cmodel
27 | endif
28 | -ifneq (,$(shell echo $(XPLATFORM) | awk '/u50/'))
29 | -CXXFLAGS += -D USE_HBM
30 | -endif
31 |
32 | # ################### Setting package and image directory #######################
33 |
34 | @@ -121,9 +113,7 @@ HOST_ARGS := -xclbin $(BUILD_DIR)/shortestPath_top.xclbin -o $(XFLIB_DIR)/L2/te
35 | VPP_FLAGS += -t $(TARGET) --platform $(XPLATFORM) --save-temps --optimize 2
36 | VPP_FLAGS += --hls.jobs 8
37 | VPP_LDFLAGS += --vivado.synth.jobs 8 --vivado.impl.jobs 8
38 | -ifneq (,$(shell echo $(XPLATFORM) | awk '/u50/'))
39 | VPP_FLAGS += --config $(CUR_DIR)/conn_u50.cfg
40 | -endif
41 |
42 | VPP_FLAGS += -I$(XFLIB_DIR)/L2/include
43 | VPP_FLAGS += -I$(XFLIB_DIR)/../database/L1/include/hw
44 |
45 | --- conn_u50.cfg
46 | +++ conn_u50.cfg
47 | @@ -1,9 +1,9 @@
48 | [connectivity]
49 | -sp=shortestPath_top.m_axi_gmem0:HBM[0]
50 | -sp=shortestPath_top.m_axi_gmem1:HBM[2]
51 | -sp=shortestPath_top.m_axi_gmem2:HBM[4]
52 | -sp=shortestPath_top.m_axi_gmem3:HBM[0]
53 | -sp=shortestPath_top.m_axi_gmem4:HBM[2]
54 | -sp=shortestPath_top.m_axi_gmem5:HBM[4]
55 | -slr=shortestPath_top:SLR0
56 | +sp=shortestPath_top.m_axi_gmem0:DDR[0]
57 | +sp=shortestPath_top.m_axi_gmem1:DDR[0]
58 | +sp=shortestPath_top.m_axi_gmem2:DDR[0]
59 | +sp=shortestPath_top.m_axi_gmem3:DDR[0]
60 | +sp=shortestPath_top.m_axi_gmem4:DDR[0]
61 | +sp=shortestPath_top.m_axi_gmem5:DDR[0]
62 | +slr=shortestPath_top:SLR1
63 | nk=shortestPath_top:1:shortestPath_top
64 |
65 | --- utils.mk
66 | +++ utils.mk
67 | @@ -19,7 +19,7 @@
68 | #+-------------------------------------------------------------------------------
69 |
70 | REPORT := no
71 | -PROFILE := no
72 | +PROFILE := yes
73 | DEBUG := no
74 |
75 | #'estimate' for estimate report generation
76 | @@ -31,7 +31,7 @@ endif
77 |
78 | #Generates profile summary report
79 | ifeq ($(PROFILE), yes)
80 | -VPP_LDFLAGS += --profile_kernel data:all:all:all
81 | +VPP_LDFLAGS += -g --profile_kernel data:all:all:all
82 | endif
83 |
84 | #Generates debug summary report
85 | @@ -148,7 +148,7 @@ ifeq ($(filter $(TARGET),sw_emu hw_emu hw),)
86 | $(error TARGET is not sw_emu, hw_emu or hw)
87 | endif
88 |
89 | -ifneq (,$(wildcard $(DEVICE)))
90 | +ifeq (,$(wildcard $(DEVICE)))
91 | # Use DEVICE as a file path
92 | XPLATFORM := $(DEVICE)
93 | else
94 |
--------------------------------------------------------------------------------
/sources/graph_lab/xrt.ini:
--------------------------------------------------------------------------------
1 | [Debug]
2 | opencl_summary=true
3 | power_profile=false
4 | opencl_trace=true
5 | lop_trace=false
6 | xrt_trace=false
7 | data_transfer_trace=coarse
8 | stall_trace=off
9 | app_debug=true
10 | [Emulation]
11 | debug_mode=gui
--------------------------------------------------------------------------------
/sources/streaming_lab/krnl_fir.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 | **********/
29 |
30 | /*
31 | * x(k) -------------------------------------- ------------
32 | * | | | |
33 | * | | | |
34 | * c(0)->(x) c(1)->(x) c(2)->(x) ... c(n-1)->(x)
35 | * | | | |
36 | * | | | |
37 | * y(k) <--(+)<--|z-1|<--(+)<--|z-1|<--(+)<-- <--|z-1|<---
38 | *
39 | *
40 | * prod 0 1 2 n-1
41 | * state 0 1 n-2
42 | *
43 | *
44 | *
45 | *
46 | * Sampling frequency 44,100 Hz
47 | *
48 | * Bands:
49 | * -------------------------------------------
50 | * | from | to | gain | ripple/att|
51 | * |----------|-----------|------|-----------|
52 | * | 0 Hz | 500 Hz | 0 | -40 dB |
53 | * | 1,500 Hz | 5,500 Hz | 1 | 0.9 dB |
54 | * | 6,500 Hz | 22,050 Hz | 0 | -40dB |
55 | * -------------------------------------------
56 | */
57 |
58 | #include "ap_axi_sdata.h"
59 | #include "ap_int.h"
60 | #include "hls_stream.h"
61 |
62 | typedef ap_axis<32, 0, 0, 0> axis;
63 |
64 | #define TAP_NUM 73
65 |
66 | ap_int<16> coe[TAP_NUM] = {
67 | -137, -73, 139, 210, 384, 339, 263, 69, -15, 0, 177, 352, 424, 275,
68 | -20, -318, -420, -273, 21, 211, 86, -387, -991, -1380, -1294, -772,
69 | -175, -6, -582, -1761, -2918, -3223, -2086, 449, 3620, 6243, 7258,
70 | 6243, 3620, 449, -2086, -3223, -2918, -1761, -582, -6, -175, -772,
71 | -1294, -1380, -991, -387, 86, 211, 21, -273, -420, -318, -20, 275,
72 | 424, 352, 177, 0, -15, 69, 263, 339, 384, 210, 139, -73, -137
73 | };
74 |
75 |
76 | /**
77 | * @brief FIR filter. Implemented using the transposed form
78 | * The coefficients are static.
79 | *
80 | * NOTE: This is not the most efficient way to implement a FIR filter
81 | * on an Xilinx FPGA. However, it is the simples version that reduces
82 | * the long critical path to a multiply accumulate.
83 | * For efficient implementation review UG073 and PG149
84 | *
85 | * @param[in] x Sample (k)
86 | * @param[out] y Output (k)
87 | */
88 |
89 | extern "C" {
90 | void krnl_fir(hls::stream &x, hls::stream &y) {
91 | #pragma HLS PIPELINE II=1
92 | #pragma HLS INTERFACE ap_ctrl_none port=return
93 |
94 | ap_int<48> prod[TAP_NUM];
95 | #pragma HLS ARRAY_PARTITION variable=prod dim=1 complete
96 | static ap_int<48> state[TAP_NUM-1] = {
97 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
98 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
99 | 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
100 | #pragma HLS ARRAY_PARTITION variable=state dim=1 complete
101 |
102 | #ifndef __SYNTHESIS__
103 | while(1)
104 | #else
105 | if (!x.empty())
106 | #endif
107 | {
108 | axis x_k = x.read();
109 | /*Multiply input x_k with coefficients*/
110 | for (unsigned int i = 0; i < TAP_NUM; i++){
111 | prod[i] = coe[i] * x_k.data;
112 | }
113 |
114 | /*Compute output*/
115 | ap_int<48> y_k = prod[0] + state[0];
116 |
117 | /*Compute addition and update the state. If the AXI4-Stream channel
118 | has tlast asserted reset the state*/
119 | if(!x_k.last){
120 | for (unsigned int i = 0; i < TAP_NUM-2; i++){
121 | state[i] = state[i+1] + prod[i+1];
122 | }
123 | state[TAP_NUM-2] = prod[TAP_NUM-1];
124 | }
125 | else {
126 | for (unsigned int i = 0; i < TAP_NUM-1; i++){
127 | state[i] = 0;
128 | }
129 | }
130 |
131 | /* generate output stream */
132 | axis out;
133 | out.data = y_k(47,16);
134 | out.last = x_k.last;
135 | y.write(out);
136 | }
137 | }
138 | }
--------------------------------------------------------------------------------
/sources/streaming_lab/krnl_mm2s.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 |
37 | /* */
38 |
39 | #include "ap_axi_sdata.h"
40 | #include "ap_int.h"
41 | #include "hls_stream.h"
42 |
43 | #define DWIDTH 32
44 |
45 | typedef ap_axis axis;
46 |
47 |
48 | /**
49 | * @brief This is a data mover kernel which reads data from global memory(DDR/HBM) via
50 | * memory mapped interface and writes to a stream interface to another kernel
51 | *
52 | * @param[in] in Memory mapped interface
53 | * @param[out] m2s Output stream interface
54 | * @param[in] samples The number of samples (transactions)
55 | */
56 |
57 | extern "C" {
58 | void krnl_mm2s(ap_uint *in,
59 | hls::stream &m2s,
60 | unsigned int samples
61 | ) {
62 |
63 | axis v;
64 | data_mover:
65 | // Auto-pipeline is going to apply pipeline to this loop
66 | for (unsigned int i = 0; i < samples; i++) {
67 | v.data = in[i];
68 | // assert last when last piece of data
69 | v.last = (i == (samples-1)) ? 1 : 0;
70 | // Write to stream interface
71 | m2s.write(v);
72 | }
73 | }
74 | }
--------------------------------------------------------------------------------
/sources/streaming_lab/krnl_s2mm.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 |
37 | /* */
38 |
39 | #include "ap_axi_sdata.h"
40 | #include "ap_int.h"
41 | #include "hls_stream.h"
42 |
43 | #define DWIDTH 32
44 |
45 | typedef ap_axiu axis;
46 |
47 |
48 | /**
49 | * @brief This is a stream to memory mapped data mover kernel which takes input from a
50 | * stream and writes data to global memory via memory mapped interface
51 | *
52 | * @param[out] out Memory mapped interface
53 | * @param[in] s2m Input stream interface
54 | * @param[in] samples The number of samples (transactions)
55 | */
56 |
57 | extern "C" {
58 | void krnl_s2mm(ap_uint *out,
59 | hls::stream &s2m,
60 | unsigned int samples
61 | ) {
62 |
63 | axis v;
64 | data_mover:
65 | // Auto-pipeline is going to apply pipeline to this loop
66 | for (unsigned int i = 0; i < samples; i++) {
67 | // Read from stream and write to memory
68 | v = s2m.read();
69 | out[i] = v.data;
70 | }
71 | }
72 | }
--------------------------------------------------------------------------------
/sources/streaming_lab/linking.cfg:
--------------------------------------------------------------------------------
1 | profile_kernel=data:krnl_mm2s:all:all
2 | profile_kernel=data:krnl_s2mm:all:all
3 | profile_kernel=data:krnl_mm2s:krnl_mm2s_1:in:all
4 | profile_kernel=data:krnl_s2mm:krnl_s2mm_1:out:all
5 |
6 | [connectivity]
7 | #Connect mm2s to fir input
8 | stream_connect=krnl_mm2s_1.m2s:krnl_fir_1.x
9 |
10 | #Connect fir to s2mm
11 | stream_connect=krnl_fir_1.y:krnl_s2mm_1.s2m
12 |
13 | # Assign SRL
14 | slr=krnl_mm2s_1:SLR1
15 | slr=krnl_s2mm_1:SLR1
16 | slr=krnl_fir_1:SLR1
17 |
18 | # Assign memory bank
19 | sp=krnl_mm2s_1.in:DDR[0]
20 | sp=krnl_s2mm_1.out:DDR[2]
--------------------------------------------------------------------------------
/sources/streaming_lab/xcl2.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #include "xcl2.hpp"
37 | #include
38 | #include
39 | #if defined(_WINDOWS)
40 | #include
41 | #else
42 | #include
43 | #endif
44 |
45 | namespace xcl {
46 | std::vector get_devices(const std::string &vendor_name) {
47 | size_t i;
48 | cl_int err;
49 | std::vector platforms;
50 | OCL_CHECK(err, err = cl::Platform::get(&platforms));
51 | cl::Platform platform;
52 | for (i = 0; i < platforms.size(); i++) {
53 | platform = platforms[i];
54 | OCL_CHECK(err, std::string platformName =
55 | platform.getInfo(&err));
56 | if (platformName == vendor_name) {
57 | std::cout << "Found Platform" << std::endl;
58 | std::cout << "Platform Name: " << platformName.c_str() << std::endl;
59 | break;
60 | }
61 | }
62 | if (i == platforms.size()) {
63 | std::cout << "Error: Failed to find Xilinx platform" << std::endl;
64 | exit(EXIT_FAILURE);
65 | }
66 | // Getting ACCELERATOR Devices and selecting 1st such device
67 | std::vector devices;
68 | OCL_CHECK(err,
69 | err = platform.getDevices(CL_DEVICE_TYPE_ACCELERATOR, &devices));
70 | return devices;
71 | }
72 |
73 | std::vector get_xil_devices() { return get_devices("Xilinx"); }
74 |
75 | std::vector
76 | read_binary_file(const std::string &xclbin_file_name) {
77 | std::cout << "INFO: Reading " << xclbin_file_name << std::endl;
78 | FILE *fp;
79 | if ((fp = fopen(xclbin_file_name.c_str(), "r")) == NULL) {
80 | printf("ERROR: %s xclbin not available please build\n",
81 | xclbin_file_name.c_str());
82 | exit(EXIT_FAILURE);
83 | }
84 | // Loading XCL Bin into char buffer
85 | std::cout << "Loading: '" << xclbin_file_name.c_str() << "'\n";
86 | std::ifstream bin_file(xclbin_file_name.c_str(), std::ifstream::binary);
87 | bin_file.seekg(0, bin_file.end);
88 | auto nb = bin_file.tellg();
89 | bin_file.seekg(0, bin_file.beg);
90 | std::vector buf;
91 | buf.resize(nb);
92 | bin_file.read(reinterpret_cast(buf.data()), nb);
93 | return buf;
94 | }
95 |
96 | bool is_emulation() {
97 | bool ret = false;
98 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
99 | if (xcl_mode != NULL) {
100 | ret = true;
101 | }
102 | return ret;
103 | }
104 |
105 | bool is_hw_emulation() {
106 | bool ret = false;
107 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
108 | if ((xcl_mode != NULL) && !strcmp(xcl_mode, "hw_emu")) {
109 | ret = true;
110 | }
111 | return ret;
112 | }
113 |
114 | bool is_xpr_device(const char *device_name) {
115 | const char *output = strstr(device_name, "xpr");
116 |
117 | if (output == NULL) {
118 | return false;
119 | } else {
120 | return true;
121 | }
122 | }
123 | }; // namespace xcl
--------------------------------------------------------------------------------
/sources/streaming_lab/xcl2.hpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2018, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #pragma once
37 |
38 | #define CL_HPP_CL_1_2_DEFAULT_BUILD
39 | #define CL_HPP_TARGET_OPENCL_VERSION 120
40 | #define CL_HPP_MINIMUM_OPENCL_VERSION 120
41 | #define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY 1
42 | #define CL_USE_DEPRECATED_OPENCL_1_2_APIS
43 |
44 | // OCL_CHECK doesn't work if call has templatized function call
45 | #define OCL_CHECK(error, call) \
46 | call; \
47 | if (error != CL_SUCCESS) { \
48 | printf("%s:%d Error calling " #call ", error code is: %d\n", __FILE__, \
49 | __LINE__, error); \
50 | exit(EXIT_FAILURE); \
51 | }
52 |
53 | #include
54 | #include
55 | #include
56 | #include
57 | // When creating a buffer with user pointer (CL_MEM_USE_HOST_PTR), under the
58 | // hood
59 | // User ptr is used if and only if it is properly aligned (page aligned). When
60 | // not
61 | // aligned, runtime has no choice but to create its own host side buffer that
62 | // backs
63 | // user ptr. This in turn implies that all operations that move data to and from
64 | // device incur an extra memcpy to move data to/from runtime's own host buffer
65 | // from/to user pointer. So it is recommended to use this allocator if user wish
66 | // to
67 | // Create Buffer/Memory Object with CL_MEM_USE_HOST_PTR to align user buffer to
68 | // the
69 | // page boundary. It will ensure that user buffer will be used when user create
70 | // Buffer/Mem Object with CL_MEM_USE_HOST_PTR.
71 | template struct aligned_allocator {
72 | using value_type = T;
73 |
74 | aligned_allocator() {}
75 |
76 | aligned_allocator(const aligned_allocator &) {}
77 |
78 | template aligned_allocator(const aligned_allocator &) {}
79 |
80 | T *allocate(std::size_t num) {
81 | void *ptr = nullptr;
82 |
83 | #if defined(_WINDOWS)
84 | {
85 | ptr = _aligned_malloc(num * sizeof(T), 4096);
86 | if (ptr == NULL) {
87 | std::cout << "Failed to allocate memory" << std::endl;
88 | exit(EXIT_FAILURE);
89 | }
90 | }
91 | #else
92 | {
93 | if (posix_memalign(&ptr, 4096, num * sizeof(T)))
94 | throw std::bad_alloc();
95 | }
96 | #endif
97 | return reinterpret_cast(ptr);
98 | }
99 | void deallocate(T *p, std::size_t num) {
100 | #if defined(_WINDOWS)
101 | _aligned_free(p);
102 | #else
103 | free(p);
104 | #endif
105 | }
106 | };
107 |
108 | namespace xcl {
109 | std::vector get_xil_devices();
110 | std::vector get_devices(const std::string &vendor_name);
111 | std::vector
112 | read_binary_file(const std::string &xclbin_file_name);
113 | bool is_emulation();
114 | bool is_hw_emulation();
115 | bool is_xpr_device(const char *device_name);
116 | class Stream {
117 | public:
118 | static decltype(&clCreateStream) createStream;
119 | static decltype(&clReleaseStream) releaseStream;
120 | static decltype(&clReadStream) readStream;
121 | static decltype(&clWriteStream) writeStream;
122 | static decltype(&clPollStreams) pollStreams;
123 | static void init(const cl_platform_id &platform) {
124 | void *bar =
125 | clGetExtensionFunctionAddressForPlatform(platform, "clCreateStream");
126 | createStream = (decltype(&clCreateStream))bar;
127 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReleaseStream");
128 | releaseStream = (decltype(&clReleaseStream))bar;
129 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReadStream");
130 | readStream = (decltype(&clReadStream))bar;
131 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clWriteStream");
132 | writeStream = (decltype(&clWriteStream))bar;
133 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clPollStreams");
134 | pollStreams = (decltype(&clPollStreams))bar;
135 | }
136 | };
137 | class P2P {
138 | public:
139 | static decltype(&xclGetMemObjectFd) getMemObjectFd;
140 | static decltype(&xclGetMemObjectFromFd) getMemObjectFromFd;
141 | static void init(const cl_platform_id &platform) {
142 | void *bar =
143 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFd");
144 | getMemObjectFd = (decltype(&xclGetMemObjectFd))bar;
145 | bar = clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFromFd");
146 | getMemObjectFromFd = (decltype(&xclGetMemObjectFromFd))bar;
147 | }
148 | };
149 | class Ext {
150 | public:
151 | static decltype(&xclGetComputeUnitInfo) getComputeUnitInfo;
152 | static void init(const cl_platform_id &platform) {
153 | void *bar =
154 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetComputeUnitInfo");
155 | getComputeUnitInfo = (decltype(&xclGetComputeUnitInfo))bar;
156 | }
157 | };
158 | }
--------------------------------------------------------------------------------
/sources/vadd_lab/krnl_vadd.cpp:
--------------------------------------------------------------------------------
1 | /**
2 | Copyright (c) 2021, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
24 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 | */
29 |
30 | /*
31 | Vector Addition Kernel Implementation
32 | Arguments:
33 | in1 (input) --> Input Vector1
34 | in2 (input) --> Input Vector2
35 | out (output) --> Output Vector
36 | elements (input) --> Number the elements in the Vector
37 | */
38 |
39 | extern "C" {
40 | void krnl_vadd(const int* in1, // Read-Only Vector 1
41 | const int* in2, // Read-Only Vector 2
42 | int* out, // Output Result
43 | int elements // Number of elements
44 | ) {
45 | //#pragma HLS INTERFACE mode=m_axi bundle=gmem0 port=in1
46 | //#pragma HLS INTERFACE mode=m_axi bundle=gmem1 port=in2
47 | //#pragma HLS INTERFACE mode=m_axi bundle=gmem2 port=out
48 |
49 | // Simple vector addition kernel.
50 | vadd1:
51 | for (int i = 0; i < elements; i++) {
52 | //for (int i = 0; i < (elements/16)*16; i++) {
53 | #pragma HLS LOOP_TRIPCOUNT avg=4096 max=4096 min=4096
54 | //#pragma HLS UNROLL factor=16
55 | out[i] = in1[i] + in2[i];
56 | }
57 | }
58 | }
59 |
--------------------------------------------------------------------------------
/sources/vadd_lab/xcl2.cpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2020, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #include "xcl2.hpp"
37 | #include
38 | #include
39 | #if defined(_WINDOWS)
40 | #include
41 | #else
42 | #include
43 | #endif
44 |
45 | namespace xcl {
46 | std::vector get_devices(const std::string &vendor_name) {
47 | size_t i;
48 | cl_int err;
49 | std::vector platforms;
50 | OCL_CHECK(err, err = cl::Platform::get(&platforms));
51 | cl::Platform platform;
52 | for (i = 0; i < platforms.size(); i++) {
53 | platform = platforms[i];
54 | OCL_CHECK(err, std::string platformName =
55 | platform.getInfo(&err));
56 | if (platformName == vendor_name) {
57 | std::cout << "Found Platform" << std::endl;
58 | std::cout << "Platform Name: " << platformName.c_str() << std::endl;
59 | break;
60 | }
61 | }
62 | if (i == platforms.size()) {
63 | std::cout << "Error: Failed to find Xilinx platform" << std::endl;
64 | exit(EXIT_FAILURE);
65 | }
66 | // Getting ACCELERATOR Devices and selecting 1st such device
67 | std::vector devices;
68 | OCL_CHECK(err,
69 | err = platform.getDevices(CL_DEVICE_TYPE_ACCELERATOR, &devices));
70 | return devices;
71 | }
72 |
73 | std::vector get_xil_devices() { return get_devices("Xilinx"); }
74 |
75 | std::vector
76 | read_binary_file(const std::string &xclbin_file_name) {
77 | std::cout << "INFO: Reading " << xclbin_file_name << std::endl;
78 | FILE *fp;
79 | if ((fp = fopen(xclbin_file_name.c_str(), "r")) == NULL) {
80 | printf("ERROR: %s xclbin not available please build\n",
81 | xclbin_file_name.c_str());
82 | exit(EXIT_FAILURE);
83 | }
84 | // Loading XCL Bin into char buffer
85 | std::cout << "Loading: '" << xclbin_file_name.c_str() << "'\n";
86 | std::ifstream bin_file(xclbin_file_name.c_str(), std::ifstream::binary);
87 | bin_file.seekg(0, bin_file.end);
88 | auto nb = bin_file.tellg();
89 | bin_file.seekg(0, bin_file.beg);
90 | std::vector buf;
91 | buf.resize(nb);
92 | bin_file.read(reinterpret_cast(buf.data()), nb);
93 | return buf;
94 | }
95 |
96 | bool is_emulation() {
97 | bool ret = false;
98 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
99 | if (xcl_mode != NULL) {
100 | ret = true;
101 | }
102 | return ret;
103 | }
104 |
105 | bool is_hw_emulation() {
106 | bool ret = false;
107 | char *xcl_mode = getenv("XCL_EMULATION_MODE");
108 | if ((xcl_mode != NULL) && !strcmp(xcl_mode, "hw_emu")) {
109 | ret = true;
110 | }
111 | return ret;
112 | }
113 |
114 | bool is_xpr_device(const char *device_name) {
115 | const char *output = strstr(device_name, "xpr");
116 |
117 | if (output == NULL) {
118 | return false;
119 | } else {
120 | return true;
121 | }
122 | }
123 | }; // namespace xcl
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/sources/vadd_lab/xcl2.hpp:
--------------------------------------------------------------------------------
1 | /**********
2 | Copyright (c) 2018, Xilinx, Inc.
3 | All rights reserved.
4 |
5 | Redistribution and use in source and binary forms, with or without modification,
6 | are permitted provided that the following conditions are met:
7 |
8 | 1. Redistributions of source code must retain the above copyright notice,
9 | this list of conditions and the following disclaimer.
10 |
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 | this list of conditions and the following disclaimer in the documentation
13 | and/or other materials provided with the distribution.
14 |
15 | 3. Neither the name of the copyright holder nor the names of its contributors
16 | may be used to endorse or promote products derived from this software
17 | without specific prior written permission.
18 |
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 | ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 | ARE DISCLAIMED.
23 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 | INDIRECT,
25 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 | LIMITED TO,
27 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
28 | BUSINESS INTERRUPTION)
29 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 | LIABILITY,
31 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 | THIS SOFTWARE,
33 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 | **********/
35 |
36 | #pragma once
37 |
38 | #define CL_HPP_CL_1_2_DEFAULT_BUILD
39 | #define CL_HPP_TARGET_OPENCL_VERSION 120
40 | #define CL_HPP_MINIMUM_OPENCL_VERSION 120
41 | #define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY 1
42 | #define CL_USE_DEPRECATED_OPENCL_1_2_APIS
43 |
44 | // OCL_CHECK doesn't work if call has templatized function call
45 | #define OCL_CHECK(error, call) \
46 | call; \
47 | if (error != CL_SUCCESS) { \
48 | printf("%s:%d Error calling " #call ", error code is: %d\n", __FILE__, \
49 | __LINE__, error); \
50 | exit(EXIT_FAILURE); \
51 | }
52 |
53 | #include
54 | #include
55 | #include
56 | #include
57 | // When creating a buffer with user pointer (CL_MEM_USE_HOST_PTR), under the
58 | // hood
59 | // User ptr is used if and only if it is properly aligned (page aligned). When
60 | // not
61 | // aligned, runtime has no choice but to create its own host side buffer that
62 | // backs
63 | // user ptr. This in turn implies that all operations that move data to and from
64 | // device incur an extra memcpy to move data to/from runtime's own host buffer
65 | // from/to user pointer. So it is recommended to use this allocator if user wish
66 | // to
67 | // Create Buffer/Memory Object with CL_MEM_USE_HOST_PTR to align user buffer to
68 | // the
69 | // page boundary. It will ensure that user buffer will be used when user create
70 | // Buffer/Mem Object with CL_MEM_USE_HOST_PTR.
71 | template struct aligned_allocator {
72 | using value_type = T;
73 |
74 | aligned_allocator() {}
75 |
76 | aligned_allocator(const aligned_allocator &) {}
77 |
78 | template aligned_allocator(const aligned_allocator &) {}
79 |
80 | T *allocate(std::size_t num) {
81 | void *ptr = nullptr;
82 |
83 | #if defined(_WINDOWS)
84 | {
85 | ptr = _aligned_malloc(num * sizeof(T), 4096);
86 | if (ptr == NULL) {
87 | std::cout << "Failed to allocate memory" << std::endl;
88 | exit(EXIT_FAILURE);
89 | }
90 | }
91 | #else
92 | {
93 | if (posix_memalign(&ptr, 4096, num * sizeof(T)))
94 | throw std::bad_alloc();
95 | }
96 | #endif
97 | return reinterpret_cast(ptr);
98 | }
99 | void deallocate(T *p, std::size_t num) {
100 | #if defined(_WINDOWS)
101 | _aligned_free(p);
102 | #else
103 | free(p);
104 | #endif
105 | }
106 | };
107 |
108 | namespace xcl {
109 | std::vector get_xil_devices();
110 | std::vector get_devices(const std::string &vendor_name);
111 | std::vector
112 | read_binary_file(const std::string &xclbin_file_name);
113 | bool is_emulation();
114 | bool is_hw_emulation();
115 | bool is_xpr_device(const char *device_name);
116 | class Stream {
117 | public:
118 | static decltype(&clCreateStream) createStream;
119 | static decltype(&clReleaseStream) releaseStream;
120 | static decltype(&clReadStream) readStream;
121 | static decltype(&clWriteStream) writeStream;
122 | static decltype(&clPollStreams) pollStreams;
123 | static void init(const cl_platform_id &platform) {
124 | void *bar =
125 | clGetExtensionFunctionAddressForPlatform(platform, "clCreateStream");
126 | createStream = (decltype(&clCreateStream))bar;
127 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReleaseStream");
128 | releaseStream = (decltype(&clReleaseStream))bar;
129 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clReadStream");
130 | readStream = (decltype(&clReadStream))bar;
131 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clWriteStream");
132 | writeStream = (decltype(&clWriteStream))bar;
133 | bar = clGetExtensionFunctionAddressForPlatform(platform, "clPollStreams");
134 | pollStreams = (decltype(&clPollStreams))bar;
135 | }
136 | };
137 | class P2P {
138 | public:
139 | static decltype(&xclGetMemObjectFd) getMemObjectFd;
140 | static decltype(&xclGetMemObjectFromFd) getMemObjectFromFd;
141 | static void init(const cl_platform_id &platform) {
142 | void *bar =
143 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFd");
144 | getMemObjectFd = (decltype(&xclGetMemObjectFd))bar;
145 | bar = clGetExtensionFunctionAddressForPlatform(platform, "xclGetMemObjectFromFd");
146 | getMemObjectFromFd = (decltype(&xclGetMemObjectFromFd))bar;
147 | }
148 | };
149 | class Ext {
150 | public:
151 | static decltype(&xclGetComputeUnitInfo) getComputeUnitInfo;
152 | static void init(const cl_platform_id &platform) {
153 | void *bar =
154 | clGetExtensionFunctionAddressForPlatform(platform, "xclGetComputeUnitInfo");
155 | getComputeUnitInfo = (decltype(&xclGetComputeUnitInfo))bar;
156 | }
157 | };
158 | }
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/sources/vision_lab/src/connectivity_aws.ini:
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1 | profile_kernel=data:resize_accel_rgb:resize_accel_rgb_1:image_in:all
2 | profile_kernel=data:resize_accel_rgb:resize_accel_rgb_1:image_out:all
3 | profile_kernel=data:resize_blur_rgb:resize_blur_rgb_1:image_in:all
4 | profile_kernel=data:resize_blur_rgb:resize_blur_rgb_1:image_out:all
5 | trace_memory=FIFO:64K
6 |
7 | [connectivity]
8 | sp=resize_accel_rgb_1.m_axi_image_in_gmem:DDR[0]
9 | sp=resize_accel_rgb_1.m_axi_image_out_gmem:DDR[0]
10 | slr=resize_accel_rgb_1:SLR1
11 |
12 | sp=resize_blur_rgb_1.m_axi_image_in_gmem:DDR[0]
13 | sp=resize_blur_rgb_1.m_axi_image_out_gmem:DDR[0]
14 | slr=resize_blur_rgb_1:SLR1
15 |
16 |
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/sources/vision_lab/src/data/README.md:
--------------------------------------------------------------------------------
1 | # Image License
2 |
3 | The images in this folder have a [Pixabay License](https://pixabay.com/service/license/)
4 |
5 | The original image was downloaded from [here](https://pixabay.com/photos/nose-doctor-fish-fish-aquarium-zoo-2206103/)
6 |
7 | ---------------------------------------
8 |