├── README.md └── RISC-V-RV32I-CPU ├── RISC-V-RV32I.xlsx ├── risc_v_cpu1 ├── CPU_tb_behav.wcfg ├── risc_v_cpu1.cache │ ├── ip │ │ └── 2019.1 │ │ │ ├── 01c34d024152aa3b │ │ │ ├── 01c34d024152aa3b.xci │ │ │ ├── inst_blkmem.dcp │ │ │ ├── inst_blkmem_sim_netlist.v │ │ │ ├── inst_blkmem_sim_netlist.vhdl │ │ │ ├── inst_blkmem_stub.v │ │ │ └── inst_blkmem_stub.vhdl │ │ │ ├── 144e6d518235e484 │ │ │ ├── 144e6d518235e484.xci │ │ │ ├── inst_blkmem.dcp │ │ │ ├── inst_blkmem_sim_netlist.v │ │ │ ├── inst_blkmem_sim_netlist.vhdl │ │ │ ├── inst_blkmem_stub.v │ │ │ └── inst_blkmem_stub.vhdl │ │ │ └── d1e4bbae9053ce8a │ │ │ ├── d1e4bbae9053ce8a.xci │ │ │ ├── inst_blkmem.dcp │ │ │ ├── inst_blkmem_sim_netlist.v │ │ │ ├── inst_blkmem_sim_netlist.vhdl │ │ │ ├── inst_blkmem_stub.v │ │ │ ├── inst_blkmem_stub.vhdl │ │ │ └── stats.txt │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── risc_v_cpu1.hw │ └── risc_v_cpu1.lpr ├── risc_v_cpu1.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── data_blkmem │ │ │ ├── data_blkmem.veo │ │ │ └── data_blkmem.vho │ │ └── inst_blkmem │ │ │ ├── inst_blkmem.veo │ │ │ ├── inst_blkmem.vho │ │ │ ├── inst_blkmem_stub.v │ │ │ └── inst_blkmem_stub.vhdl │ ├── ipstatic │ │ └── simulation │ │ │ └── blk_mem_gen_v8_4.v │ ├── mem_init_files │ │ └── summary.log │ └── sim_scripts │ │ └── inst_blkmem │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── run.f │ │ └── summary.log │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── simulate.do │ │ └── summary.log │ │ ├── xcelium │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── run.f │ │ └── summary.log │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── summary.log │ │ ├── vlog.prj │ │ └── xsim.ini ├── risc_v_cpu1.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ └── vrs_config_3.xml │ └── inst_blkmem_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── inst_blkmem.dcp │ │ ├── inst_blkmem.tcl │ │ ├── inst_blkmem.vds │ │ ├── inst_blkmem_utilization_synth.pb │ │ ├── inst_blkmem_utilization_synth.rpt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── risc_v_cpu1.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── CPU_tb.tcl │ │ ├── CPU_tb_behav.wdb │ │ ├── CPU_tb_vlog.prj │ │ ├── compile.bat │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_12664.backup.jou │ │ ├── webtalk_12664.backup.log │ │ ├── webtalk_21072.backup.jou │ │ ├── webtalk_21072.backup.log │ │ ├── webtalk_2148.backup.jou │ │ ├── webtalk_2148.backup.log │ │ ├── webtalk_22300.backup.jou │ │ ├── webtalk_22300.backup.log │ │ ├── webtalk_8964.backup.jou │ │ ├── webtalk_8964.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── CPU_tb_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @a@l@u.sdb │ │ │ ├── @c@p@u.sdb │ │ │ ├── @c@p@u_tb.sdb │ │ │ ├── @p@c.sdb │ │ │ ├── control_unit.sdb │ │ │ ├── ctrl_path.sdb │ │ │ ├── data_blkmem.sdb │ │ │ ├── data_path.sdb │ │ │ ├── decoder.sdb │ │ │ ├── glbl.sdb │ │ │ ├── inst_blkmem.sdb │ │ │ ├── regfile.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xsim.ini.bak │ │ ├── xvlog.log │ │ └── xvlog.pb ├── risc_v_cpu1.srcs │ ├── sim_1 │ │ └── new │ │ │ └── CPU_tb.v │ └── sources_1 │ │ ├── ip │ │ ├── data_blkmem │ │ │ ├── data_blkmem.dcp │ │ │ ├── data_blkmem.veo │ │ │ ├── data_blkmem.vho │ │ │ ├── data_blkmem.xci │ │ │ ├── data_blkmem.xml │ │ │ ├── data_blkmem_ooc.xdc │ │ │ ├── data_blkmem_sim_netlist.v │ │ │ ├── data_blkmem_sim_netlist.vhdl │ │ │ ├── data_blkmem_stub.v │ │ │ ├── data_blkmem_stub.vhdl │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ │ └── data_blkmem.v │ │ │ ├── simulation │ │ │ │ └── blk_mem_gen_v8_4.v │ │ │ ├── summary.log │ │ │ └── synth │ │ │ │ └── data_blkmem.vhd │ │ └── inst_blkmem │ │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── inst_blkmem.dcp │ │ │ ├── inst_blkmem.veo │ │ │ ├── inst_blkmem.vho │ │ │ ├── inst_blkmem.xci │ │ │ ├── inst_blkmem.xml │ │ │ ├── inst_blkmem_ooc.xdc │ │ │ ├── inst_blkmem_sim_netlist.v │ │ │ ├── inst_blkmem_sim_netlist.vhdl │ │ │ ├── inst_blkmem_stub.v │ │ │ ├── inst_blkmem_stub.vhdl │ │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ └── inst_blkmem.v │ │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ │ ├── summary.log │ │ │ └── synth │ │ │ └── inst_blkmem.vhd │ │ └── new │ │ ├── ALU.v │ │ ├── CPU.v │ │ ├── PC.v │ │ ├── control_unit.v │ │ ├── ctrl_path.v │ │ ├── data_path.v │ │ ├── decoder.v │ │ └── regfile.v ├── risc_v_cpu1.xpr ├── vivado.jou ├── vivado.log ├── vivado_10020.backup.jou ├── vivado_10020.backup.log ├── vivado_10516.backup.jou ├── vivado_10516.backup.log ├── vivado_11852.backup.jou ├── vivado_11852.backup.log ├── vivado_19720.backup.jou ├── vivado_19720.backup.log ├── vivado_8400.backup.jou ├── vivado_8400.backup.log └── vivado_pid2488.str ├── risc_v_cpu2 ├── CPU_tb2_behav.wcfg ├── risc_v_cpu2.cache │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ ├── webtalk_pa.xml │ │ └── xsim.wdf ├── risc_v_cpu2.hw │ └── risc_v_cpu2.lpr ├── risc_v_cpu2.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── data_blkmem │ │ │ ├── data_blkmem.veo │ │ │ └── data_blkmem.vho │ │ └── inst_blkmem │ │ │ ├── inst_blkmem.veo │ │ │ ├── inst_blkmem.vho │ │ │ ├── inst_blkmem_stub.v │ │ │ └── inst_blkmem_stub.vhdl │ ├── ipstatic │ │ └── simulation │ │ │ └── blk_mem_gen_v8_4.v │ ├── mem_init_files │ │ └── summary.log │ └── sim_scripts │ │ └── inst_blkmem │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── run.f │ │ └── summary.log │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── inst_blkmem.udo │ │ ├── simulate.do │ │ ├── summary.log │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── simulate.do │ │ └── summary.log │ │ ├── xcelium │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── run.f │ │ └── summary.log │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_blkmem.sh │ │ ├── summary.log │ │ ├── vlog.prj │ │ └── xsim.ini ├── risc_v_cpu2.runs │ └── inst_blkmem_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── inst_blkmem.dcp │ │ ├── inst_blkmem.tcl │ │ ├── inst_blkmem.vds │ │ ├── inst_blkmem_utilization_synth.pb │ │ ├── inst_blkmem_utilization_synth.rpt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── risc_v_cpu2.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── CPU_tb.tcl │ │ ├── CPU_tb2.tcl │ │ ├── CPU_tb2_behav.wdb │ │ ├── CPU_tb2_vlog.prj │ │ ├── CPU_tb_behav.wdb │ │ ├── CPU_tb_vlog.prj │ │ ├── compile.bat │ │ ├── elaborate.bat │ │ ├── elaborate.log │ │ ├── glbl.v │ │ ├── simulate.bat │ │ ├── simulate.log │ │ ├── webtalk.jou │ │ ├── webtalk.log │ │ ├── webtalk_11712.backup.jou │ │ ├── webtalk_11712.backup.log │ │ ├── webtalk_13012.backup.jou │ │ ├── webtalk_13012.backup.log │ │ ├── webtalk_14996.backup.jou │ │ ├── webtalk_14996.backup.log │ │ ├── webtalk_19444.backup.jou │ │ ├── webtalk_19444.backup.log │ │ ├── webtalk_5456.backup.jou │ │ ├── webtalk_5456.backup.log │ │ ├── xelab.pb │ │ ├── xsim.dir │ │ ├── CPU_tb2_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ └── xsim_webtalk.tcl │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ ├── CPU_tb_behav │ │ │ ├── Compile_Options.txt │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.c │ │ │ │ └── xsim_1.win64.obj │ │ │ ├── webtalk │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ └── usage_statistics_ext_xsim.xml │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rlx │ │ │ ├── xsim.rtti │ │ │ ├── xsim.svtype │ │ │ ├── xsim.type │ │ │ ├── xsim.xdbg │ │ │ ├── xsimSettings.ini │ │ │ ├── xsimcrash.log │ │ │ ├── xsimk.exe │ │ │ └── xsimkernel.log │ │ └── xil_defaultlib │ │ │ ├── @a@l@u.sdb │ │ │ ├── @c@p@u.sdb │ │ │ ├── @c@p@u_tb.sdb │ │ │ ├── @c@p@u_tb2.sdb │ │ │ ├── @p@c.sdb │ │ │ ├── branch_jump.sdb │ │ │ ├── control_unit.sdb │ │ │ ├── ctrl_path.sdb │ │ │ ├── data_blkmem.sdb │ │ │ ├── data_path.sdb │ │ │ ├── decoder.sdb │ │ │ ├── glbl.sdb │ │ │ ├── inst_blkmem.sdb │ │ │ ├── regfile.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xsim.ini.bak │ │ ├── xvlog.log │ │ └── xvlog.pb ├── risc_v_cpu2.srcs │ ├── sim_1 │ │ └── new │ │ │ ├── CPU_tb.v │ │ │ └── CPU_tb2.v │ └── sources_1 │ │ ├── ip │ │ ├── data_blkmem │ │ │ ├── data_blkmem.dcp │ │ │ ├── data_blkmem.veo │ │ │ ├── data_blkmem.vho │ │ │ ├── data_blkmem.xci │ │ │ ├── data_blkmem.xml │ │ │ ├── data_blkmem_ooc.xdc │ │ │ ├── data_blkmem_sim_netlist.v │ │ │ ├── data_blkmem_sim_netlist.vhdl │ │ │ ├── data_blkmem_stub.v │ │ │ ├── data_blkmem_stub.vhdl │ │ │ ├── doc │ │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── misc │ │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ │ └── data_blkmem.v │ │ │ ├── simulation │ │ │ │ └── blk_mem_gen_v8_4.v │ │ │ ├── summary.log │ │ │ └── synth │ │ │ │ └── data_blkmem.vhd │ │ └── inst_blkmem │ │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── inst_blkmem.dcp │ │ │ ├── inst_blkmem.veo │ │ │ ├── inst_blkmem.vho │ │ │ ├── inst_blkmem.xci │ │ │ ├── inst_blkmem.xml │ │ │ ├── inst_blkmem_ooc.xdc │ │ │ ├── inst_blkmem_sim_netlist.v │ │ │ ├── inst_blkmem_sim_netlist.vhdl │ │ │ ├── inst_blkmem_stub.v │ │ │ ├── inst_blkmem_stub.vhdl │ │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ └── inst_blkmem.v │ │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ │ ├── summary.log │ │ │ └── synth │ │ │ └── inst_blkmem.vhd │ │ └── new │ │ ├── ALU.v │ │ ├── CPU.v │ │ ├── PC.v │ │ ├── branch_jump.v │ │ ├── control_unit.v │ │ ├── ctrl_path.v │ │ ├── data_path.v │ │ ├── decoder.v │ │ └── regfile.v ├── risc_v_cpu2.xpr ├── vivado.jou ├── vivado.log ├── vivado_7128.backup.jou ├── vivado_7128.backup.log ├── vivado_pid23856.str └── vivado_pid7128.str └── 说明.pptx /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Xinyang-ZHANG/RISC_V_RV32I_5stage_pipeline/HEAD/README.md -------------------------------------------------------------------------------- /RISC-V-RV32I-CPU/RISC-V-RV32I.xlsx: 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