├── Documentation_FPGA_ClassD.pdf ├── PWM_Modulator.vhd ├── README.md ├── UpSampler.vhd ├── audiosystem.vhd ├── blockdiagram.png ├── clk.sdc ├── i2s_rxtx.vhd ├── main_bitmap.bin ├── noiseshaper.vhd ├── pins.pcf └── top.vhd /Documentation_FPGA_ClassD.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/Documentation_FPGA_ClassD.pdf -------------------------------------------------------------------------------- /PWM_Modulator.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/PWM_Modulator.vhd -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/README.md -------------------------------------------------------------------------------- /UpSampler.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/UpSampler.vhd -------------------------------------------------------------------------------- /audiosystem.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/audiosystem.vhd -------------------------------------------------------------------------------- /blockdiagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/blockdiagram.png -------------------------------------------------------------------------------- /clk.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/clk.sdc -------------------------------------------------------------------------------- /i2s_rxtx.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/i2s_rxtx.vhd -------------------------------------------------------------------------------- /main_bitmap.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/main_bitmap.bin -------------------------------------------------------------------------------- /noiseshaper.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/noiseshaper.vhd -------------------------------------------------------------------------------- /pins.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/pins.pcf -------------------------------------------------------------------------------- /top.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier/HEAD/top.vhd --------------------------------------------------------------------------------