├── source └── empty_file_for_keep_directory ├── PnR ├── work │ ├── design │ │ └── empty_file_for_keep_directory │ ├── output │ │ └── empty_file_for_keep_directory │ └── timing │ │ └── empty_file_for_keep_directory ├── scripts │ ├── pin_fix.tcl │ ├── Default.view │ ├── pin.tcl │ ├── place.tcl │ ├── fplan.tcl │ ├── cts.tcl │ ├── verify.tcl │ ├── top-level.tcl │ ├── pplan.tcl │ └── route.tcl └── run_PnR ├── simulation ├── sdf │ └── empty_file_for_keep_directory ├── work │ └── empty_file_for_keep_directory ├── testbench │ └── empty_file_for_keep_directory ├── script │ ├── sdf_cmd_generate_pnr │ └── sdf_cmd_generate_syn └── run_sim ├── synthesis ├── work │ ├── log │ │ └── empty_file_for_keep_directory │ ├── output │ │ └── empty_file_for_keep_directory │ └── report │ │ └── empty_file_for_keep_directory ├── scripts │ ├── upf │ └── synthesis.tcl └── run_syn ├── lib └── lib_path └── README.md /source/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /PnR/work/design/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /PnR/work/output/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /PnR/work/timing/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /simulation/sdf/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /simulation/work/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /synthesis/work/log/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /simulation/testbench/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /synthesis/work/output/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /synthesis/work/report/empty_file_for_keep_directory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /simulation/script/sdf_cmd_generate_pnr: -------------------------------------------------------------------------------- 1 | topmodule=$1 2 | echo "COMPILED_SDF_FILE = \"../../PnR/work/output/${topmodule}_pnr.sdf.X\", 3 | SCOPE = tb_${topmodule}.DUT_${topmodule}, 4 | MTM_CONTROL = \"MAXIMUM\", 5 | LOG_FILE = \"${topmodule}_pnr_sdf.log\";" > ../sdf/sdf.cmd -------------------------------------------------------------------------------- /simulation/script/sdf_cmd_generate_syn: -------------------------------------------------------------------------------- 1 | topmodule=$1 2 | echo "COMPILED_SDF_FILE = \"../../synthesis/work/output/${topmodule}_syn.sdf.X\", 3 | SCOPE = tb_${topmodule}.DUT_${topmodule}, 4 | MTM_CONTROL = \"MAXIMUM\", 5 | LOG_FILE = \"${topmodule}_syn_sdf.log\";" > ../sdf/sdf.cmd -------------------------------------------------------------------------------- /lib/lib_path: -------------------------------------------------------------------------------- 1 | # Edit this file to set the path to your technology libraries 2 | # These variables are used by the synthesis, PnR and simulation scripts 3 | target_library="" 4 | library_search_path="" 5 | stdcell_verilog="" 6 | cap_table="" 7 | fillerCells="" 8 | clockBufName="" 9 | lef="" -------------------------------------------------------------------------------- /synthesis/scripts/upf: -------------------------------------------------------------------------------- 1 | set_design_top $top_module 2 | upf_version 2.0 3 | create_supply_port vpwr 4 | create_supply_port vgnd 5 | create_supply_net vpwr 6 | create_supply_net vgnd 7 | connect_supply_net vpwr -ports vpwr 8 | connect_supply_net vgnd -ports vgnd 9 | create_supply_set SS_VDD -function { power vpwr } -function { ground vgnd } -function { nwell vpwr} -function { pwell vgnd } 10 | create_power_domain PD_VDD -include_scope -supply {primary SS_VDD} 11 | set_port_attributes -applies_to both -elements . -driver_supply SS_VDD -receiver_supply SS_VDD -------------------------------------------------------------------------------- /PnR/scripts/pin_fix.tcl: -------------------------------------------------------------------------------- 1 | foreach pin [get_db ports] { 2 | 3 | set name [get_db $pin .name] 4 | set side [get_db $pin .side] 5 | set xL [get_db $pin .location.x] 6 | set yL [get_db $pin .location.y] 7 | set layer [get_db $pin .layer.name] 8 | 9 | if {$side == "east"} { 10 | set xL [expr {$xL - 0.5}] 11 | edit_pin -layer ${layer} -side Inside -assign $xL $yL -pin ${name} 12 | } elseif {$side == "west"} { 13 | set xL [expr {$xL - 0.5}] 14 | edit_pin -layer ${layer} -side Inside -assign $xL $yL -pin ${name} 15 | } else { 16 | puts "Do nothing" 17 | } 18 | 19 | } 20 | -------------------------------------------------------------------------------- /PnR/scripts/Default.view: -------------------------------------------------------------------------------- 1 | # Version:1.0 MMMC View Definition File 2 | # Do Not Remove Above Line 3 | create_rc_corner -name rc -cap_table {../../lib/sky130_cap.captable} -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0} 4 | create_library_set -name libSTD -timing {../../lib/scs130lp_tt_1.62_25_nldm.lib} 5 | create_constraint_mode -name Constraints -sdc_files {../../synthesis/work/output/snn_fixed_16_2_4_4_2_syn.sdc} 6 | create_delay_corner -name Delay -library_set {libSTD} -rc_corner {rc} 7 | create_analysis_view -name Default -constraint_mode {Constraints} -delay_corner {Delay} 8 | set_analysis_view -setup {Default} -hold {Default} 9 | -------------------------------------------------------------------------------- /PnR/scripts/pin.tcl: -------------------------------------------------------------------------------- 1 | 2 | editPin -use GROUND -pinWidth 0.14 -pinDepth 0.8 -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Top -layer 3 -spreadType start -spacing 2.04 -start 10.0 208.42 -pin {miso cs mosi sck VDD VSS} 3 | 4 | 5 | 6 | editPin -pinWidth 0.14 -pinDepth 0.595 -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Bottom -layer 3 -spreadType start -spacing 2.04 -start 72.333 1.158 -pin {{gpioin1[0]} {gpioin1[1]} {gpioin1[2]} {gpioin1[3]} {gpioin1[4]} {gpioin1[5]} {gpioin1[6]} {gpioin1[7]}} 7 | 8 | 9 | editPin -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Bottom -layer 3 -spreadType start -spacing 2.0 -start 20.542 0.843 -pin {{gpioout3[0]} {gpioout3[1]} {gpioout3[2]} {gpioout3[3]} {gpioout3[4]} {gpioout3[5]} {gpioout3[6]} {gpioout3[7]}} 10 | 11 | 12 | -------------------------------------------------------------------------------- /PnR/scripts/place.tcl: -------------------------------------------------------------------------------- 1 | 2 | puts "----------Placing Cells-----------" 3 | 4 | setPlaceMode -place_global_place_io_pins true 5 | setPlaceMode -fp false 6 | placeDesign 7 | setDrawView place 8 | fit 9 | 10 | # Now run the first optimization step - pre-CTS (Clock Tree Synthesis) 11 | # in-place optimization. 12 | setOptMode -yieldEffort none 13 | setOptMode -effort high 14 | setOptMode -maxDensity 0.9 15 | setOptMode -drcMargin 0.0 16 | setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0 17 | setOptMode -SimplifyNetlist false 18 | setOptMode -fixCap true -fixTran true -fixFanoutLoad true 19 | optDesign -preCTS -outDir work/report/ 20 | #optDesign -postCTS 21 | fit 22 | # saveNetlist [format "%s_soc.v" $BASENAME] -includePowerGround 23 | 24 | # Save the design so far 25 | saveDesign work/design/${BASENAME}_placed.enc 26 | puts "-------------Done Placing Cells-----" 27 | -------------------------------------------------------------------------------- /PnR/scripts/fplan.tcl: -------------------------------------------------------------------------------- 1 | ##################################################### 2 | # Floorplanning (Erik Brunvand, 2008) # 3 | ##################################################### 4 | puts "-------------Floorplanning---------------" 5 | # 6 | # Make a floorplan - this works fine for projects that are all 7 | # standard cells and include no blocks that need hand placement... 8 | setDrawView fplan 9 | #setFPlanRowSpacingAndType $rowgap 2 10 | #floorPlan -site core -r $aspect $usepct $coregap $coregap $coregap $coregap 11 | #setRoutingStyle -top -style m 12 | #fit 13 | 14 | getIoFlowFlag 15 | setFPlanRowSpacingAndType $rowgap 2 16 | setIoFlowFlag 0 17 | #floorPlan -flip s -r $aspect $usepct $coregap $coregap $coregap $coregap 18 | floorPlan -flip s -r $aspect $usepct $coregap $coregap $coregap $coregap 19 | uiSetTool select 20 | getIoFlowFlag 21 | fit 22 | 23 | 24 | 25 | # 26 | # Save design so far 27 | saveDesign ../work/design/${BASENAME}_fplan.enc 28 | saveFPlan ../work/design/${BASENAME}.fp 29 | puts "--------------Floorplanning done-----------" 30 | -------------------------------------------------------------------------------- /PnR/scripts/cts.tcl: -------------------------------------------------------------------------------- 1 | 2 | puts "--------Clock Tree Synthesis-------" 3 | 4 | # Create the clock tree spec from the .sdc file 5 | createClockTreeSpec -output $BASENAME.ctstch -invFootprint $clockBufName 6 | specifyClockTree -clkfile $BASENAME.ctstch 7 | 8 | # Use -useCTSRouteGuide to use routing guide during CTS. 9 | setCTSMode -useCTSRouteGuide 10 | 11 | # Set routeClkNet to use Nanoroute during CTS. 12 | setCTSMode -routeClkNet 13 | 14 | # Perform clocktree synthesis 15 | clockDesign -outDir ${BASENAME}_clock_reports 16 | 17 | 18 | 19 | # Run the second optimization - post-CTS 20 | setOptMode -yieldEffort none 21 | setOptMode -highEffort 22 | setOptMode -maxDensity 0.95 23 | setOptMode -drcMargin 0.0 24 | setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0 25 | setOptMode -noSimplifyNetlist 26 | getOpCond -max 27 | getOpCond -max 28 | setOptMode -fixCap true -fixTran true -fixFanoutLoad false 29 | optDesign -postCTS 30 | optDesign -postCTS -hold 31 | # Save the design so far 32 | saveDesign ${BASENAME}_cts.enc 33 | puts "---------Clock Tree Synthesis done----" 34 | -------------------------------------------------------------------------------- /synthesis/scripts/synthesis.tcl: -------------------------------------------------------------------------------- 1 | # Set the search paths to the libraries and the HDL files 2 | # Remember that "." means your current directory. Add more directories 3 | # after the . if you like. 4 | set_db log_file log/genus.log 5 | set_db cmd_file log/genus.cmd 6 | set_db init_hdl_search_path {../../source} 7 | # top_module is defined in the command line with -execute "set top_module " 8 | 9 | read_libs ${target_library} 10 | # check_library -lib_cell [get_lib_cells] 11 | 12 | read_hdl [glob ../../source/*v] 13 | 14 | elaborate $top_module 15 | 16 | read_sdc ../scripts/${top_module}.sdc 17 | 18 | read_power_intent ../scripts/upf 19 | apply_power_intent 20 | commit_power_intent 21 | 22 | set_db syn_generic_effort medium 23 | set_db syn_map_effort medium 24 | set_db syn_opt_effort medium 25 | 26 | syn_generic 27 | syn_map 28 | syn_opt 29 | 30 | report timing > report/${top_module}_timing.rep 31 | report gates > report/${top_module}_cell.rep 32 | report power > report/${top_module}_power.rep 33 | 34 | write_netlist -mapped > output/${top_module}_syn.v 35 | write_netlist -pg -mapped > output/${top_module}_pg_syn.v 36 | write_sdf > output/${top_module}_syn.sdf 37 | write_sdc > output/${top_module}_syn.sdc 38 | 39 | exit -------------------------------------------------------------------------------- /PnR/scripts/verify.tcl: -------------------------------------------------------------------------------- 1 | 2 | puts "----------Verifying and File Output-------------" 3 | # 4 | # Verify the connectivity and geometry 5 | verifyConnectivity -type regular -error 50 -warning 50 \ 6 | -reportfile ../work/report/${BASENAME}_Conn_regular.rpt 7 | verifyConnectivity -type special -error 50 -warning 50 \ 8 | -reportfile ../work/report/${BASENAME}_Conn_special.rpt 9 | verifyGeometry -allowSameCellViols -noSameNet -noOverlap\ 10 | -reportfile ../work/report/${BASENAME}_Geom.rpt 11 | 12 | puts "----------Output ${BASENAME}.def file------------" 13 | # Export the DEF, v, spef, sdf, lef, and lib files 14 | saveDesign ../work/design/${BASENAME}_done.enc -def 15 | 16 | 17 | streamOut [format "../work/output/%s_soc.gds" $BASENAME] -mapFile /afs/glue.umd.edu/department/enee/software/cadskywaterpdk/pdk/V2.1.306/LIBS/S130/s130_innovus.layermap -libName Test -structureName $BASENAME -units 2000 -mode ALL 18 | 19 | puts "----------Output ${BASENAME}_soc.v file---------" 20 | saveNetlist [format "../work/output/%s_soc.v" $BASENAME] -includePowerGround 21 | 22 | 23 | extractRC -outfile ../work/output/$BASENAME.cap 24 | rcOut -spef ../work/output/$BASENAME.spef 25 | 26 | 27 | # Generate timing model for PrimeTime 28 | writeTimingCon -pt -filePrefix ../work/timing/${BASENAME}_done 29 | 30 | puts "------------Verify and file output done------" 31 | -------------------------------------------------------------------------------- /synthesis/run_syn: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # a simple bash script for Cadence Genus 4 | 5 | echo "Genus Synthesis Control Script" 6 | 7 | # Read target_library and target_library_path from ../lib/lib_path 8 | target_library=$(grep '^target_library=' ../lib/lib_path | cut -d'=' -f2) 9 | library_search_path=$(grep '^library_search_path=' ../lib/lib_path | cut -d'=' -f2) 10 | 11 | if [ -z "$target_library" ]; then 12 | echo "Error: target_library not found in ../lib/lib_path." 13 | exit 1 14 | fi 15 | if [ -z "$library_search_path" ]; then 16 | echo "Error: library_search_path not found in ../lib/lib_path." 17 | exit 1 18 | fi 19 | 20 | echo "target_library: $target_library" 21 | echo "library_search_path: $library_search_path" 22 | 23 | # reset control variables 24 | gui=0 25 | topmodule="" 26 | newtopflag=0 27 | top=0 28 | 29 | # read and process input arguments 30 | for arg in $@ 31 | do 32 | if [ "$arg" == "-gui" ] 33 | then 34 | gui=1 35 | elif [ $newtopflag == 1 ] 36 | then 37 | topmodule=$arg 38 | newtopflag=0 39 | elif [ "$arg" == "-top" ] 40 | then 41 | newtopflag=1 42 | top=1 43 | fi 44 | done 45 | 46 | echo "" 47 | pushd work 48 | 49 | 50 | if [ $gui == 1 ] 51 | then 52 | if [ $top == 1 ] 53 | then 54 | genus -execute "set target_library $target_library; set_db init_lib_search_path $library_search_path; set top_module $topmodule" -f ../scripts/synthesis.tcl -gui 55 | else 56 | genus -gui 57 | fi 58 | else 59 | if [ $top == 1 ] 60 | then 61 | genus -execute "set target_library $target_library; set_db init_lib_search_path $library_search_path; set top_module $topmodule" -f ../scripts/synthesis.tcl 62 | else 63 | genus 64 | fi 65 | fi 66 | 67 | echo "Deleting following log files" 68 | find . -maxdepth 1 -type f 69 | find . -maxdepth 1 -type f -exec rm -f {} \; 70 | 71 | popd 72 | 73 | 74 | 75 | -------------------------------------------------------------------------------- /PnR/scripts/top-level.tcl: -------------------------------------------------------------------------------- 1 | 2 | # set the BASENAME for the config files. This will also 3 | # be used for the .lib, .lef, .v, and .spef files 4 | # that are generated by this script 5 | setMultiCpuUsage -localCpu max 6 | 7 | # set the name of the filler cells - you don't need a list 8 | # if you only have one 9 | # set fillerCells [list "design_lib_fill_1" "design_lib_fill_2" "design_lib_fill_4" "design_lib_fill_8"] 10 | 11 | # choose numbers that make sense for you 12 | set usepct 0.4;# percent utilization in placing cells 13 | set rowgap 0 ;# gap between pairs of std cell rows 14 | set aspect 0.7;# aspect ratio of overall cell (1.0 is square) 15 | # less than 1.0 is landscape, greaterF than 1.0 is portrait 16 | 17 | ############################################################# 18 | # You may not have to change things below this line - but check! 19 | ############################################################# 20 | # set clockBufName design_lib_clkbuf_1;# Footprint of inverter in .lib file 21 | 22 | # Set some values that define the power rings and stripes. 23 | # use these defaults, or choose your own. 24 | # Note that all these numbers should be divisible by 3 so 25 | # that they fit on the lambda grid 26 | set pwidth 0.5 ;# power rail width 27 | set pspace 1.0 ;# power rail space 28 | set swidth 1.0 ;# power stripe width 29 | set sspace 1;# power stripe spacing 30 | set soffset 1.0;# power stripe offset to first stripe 31 | set coregap 4.0;# gap between the core and the power rails 32 | set set_to_set_distance 3.0; 33 | 34 | set init_gnd_net vgnd 35 | set init_pwr_net vpwr 36 | # set init_lef_file {../../lib/design_lib.tlef 37 | # ../../lib/design_lib.lef} 38 | set init_verilog ../../synthesis/work/output/${BASENAME}_pg_syn.v 39 | set init_mmmc_file ../scripts/Default.view 40 | 41 | init_design 42 | 43 | # source the files that operate on the circuit 44 | source ../scripts/fplan.tcl ;# create the floorplan (might be done by hand...) 45 | # saveNetlist [format "%s_soc.v" $BASENAME] -includePowerGround 46 | source ../scripts/pplan.tcl ;# create the power rings and stripes 47 | # source pin.tcl 48 | # source pin_fix.tcl 49 | 50 | 51 | addWellTap -cell design_lib_tap -cellInterval 50 -checkerBoard 52 | source ../scripts/place.tcl ;# Place the cells and optimize (pre-CTS) 53 | addTieHiLo -cell design_lib_tie -prefix tieOff 54 | #source cts.tcl ;# Create the clock tree, and optimize (post-CTS) 55 | source ../scripts/route.tcl ;# Route the design using nanoRoute 56 | source ../scripts/verify.tcl ;# Verify the design and produce output files 57 | # exit 58 | -------------------------------------------------------------------------------- /PnR/scripts/pplan.tcl: -------------------------------------------------------------------------------- 1 | 2 | puts "-------------Power Planning----------------" 3 | puts "-------Making power rings------------------" 4 | # 5 | # Make power and ground rings 6 | # $pwidth microns wide with $pspace spacing between them 7 | # and centered in the channel 8 | 9 | #addRing -skip_via_on_wire_shape Noshape -skip_via_on_pin Standardcell -stacked_via_top_layer met6 -type core_rings -jog_distance 0.2 -threshold 0.2 -nets {VGND VPWR} -follow core -stacked_via_bottom_layer met1 -layer {bottom met1 top met1 right met2 left met2} -width $pwidth -spacing $pspace 10 | 11 | # globalNetConnect vpwr -type pgpin -pin vpwr -inst * -all -override 12 | # globalNetConnect vgnd -type pgpin -pin vgnd -inst * -all -override 13 | # globalNetConnect vpwr -type pgpin -pin vpb -inst * -all -override 14 | # globalNetConnect vgnd -type pgpin -pin vnb -inst * -all -override 15 | # globalNetConnect vpwr -type tiehi -inst * -all -override 16 | # globalNetConnect vgnd -type tielo -inst * -all -override 17 | 18 | addRing -nets {vpwr vgnd} -type core_rings -follow core -layer {top met1 bottom met1 left met2 right met2} -width $pwidth -spacing $sspace -offset $soffset -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid None 19 | set sprCreateIeStripeNets {} 20 | set sprCreateIeStripeLayers {} 21 | set sprCreateIeStripeWidth 1 22 | set sprCreateIeStripeSpacing 1 23 | set sprCreateIeStripeThreshold 1 24 | 25 | 26 | 27 | # 28 | puts "------making power stripes-----------------" 29 | # 30 | # Make Power Stripes. This step is optional. If you keep it in remember to 31 | # check the stripe spacing (set-to-set-distance = $sspace) 32 | # and stripe offset (xleft-offset = $soffset)) 33 | #addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit M2 -max_same_layer_jog_length 6 -padcore_ring_bottom_layer_limit M1 -number_of_sets 1 -skip_via_on_pin Standardcell -stacked_via_top_layer AP -padcore_ring_top_layer_limit M2 -spacing 2 -merge_stripes_value 0.1 -direction horizontal -layer M1 -block_ring_bottom_layer_limit M1 -width 1 -nets {vdd vss} -stacked_via_bottom_layer M1 34 | 35 | #addStripe -block_ring_top_layer_limit M3 -max_same_layer_jog_length 3.0 \ 36 | # -snap_wire_center_to_grid Grid -padcore_ring_bottom_layer_limit M1 \ 37 | # -set_to_set_distance $sspace -stacked_via_top_layer M3 \ 38 | # -padcore_ring_top_layer_limit M3 -spacing $pspace -xleft_offset $soffset \ 39 | # -merge_stripes_value 1.5 -layer M2 -block_ring_bottom_layer_limit M1 \ 40 | # -width $swidth -nets {vss vdd} -stacked_via_bottom_layer M1 41 | # 42 | # Use the special-router to route the vdd! and gnd! nets 43 | sroute -jogControl { preferWithChanges differentLayer } -nets {vgnd vpwr} 44 | 45 | # Save the design so far 46 | saveDesign ../work/design/${BASENAME}_pplan.enc 47 | puts "-------------Power Planning done---------" 48 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Digital Design Automation Scripts 2 | 3 | This repository contains automation scripts for digital design flow using Cadence EDA tools. The scripts streamline the process of simulation, synthesis, and place & route operations. 4 | 5 | ## Prerequisites 6 | - Cadence Xcelium for simulation 7 | - Cadence Genus for synthesis 8 | - Cadence Innovus for place & route 9 | - Valid technology libraries and PDKs 10 | ## Scripts Overview 11 | 12 | ### 1. `run_sim` 13 | This script is used for running simulations using Cadence Xcelium. 14 | 15 | #### Features: 16 | - Supports cleaning the work directory. 17 | - Allows compiling source files and standard cells. 18 | - Enables simulation with or without GUI. 19 | - Supports waveform viewing. 20 | 21 | #### Usage: 22 | ```bash 23 | ./run_sim [options] 24 | ``` 25 | 26 | #### Options: 27 | - `-clean`: Cleans the work directory. 28 | - `-compile`: Compiles the source files. 29 | - `-sim`: Runs the simulation (also triggers compilation). 30 | - `-cells`: Includes standard cells during compilation. 31 | - `-gui`: Runs the simulation in GUI mode. 32 | - `-waveform`: Opens the waveform viewer. 33 | - `-top `: Specifies the top module for simulation. 34 | 35 | #### Example: 36 | ```bash 37 | ./run_sim -sim -gui -top my_top_module 38 | ``` 39 | 40 | --- 41 | 42 | ### 2. `run_syn` 43 | This script is used for running synthesis using Cadence Genus. 44 | 45 | #### Features: 46 | - Supports GUI and non-GUI modes. 47 | - Allows specifying the top module for synthesis. 48 | 49 | #### Usage: 50 | ```bash 51 | ./run_syn [options] 52 | ``` 53 | 54 | #### Options: 55 | - `-gui`: Launches the synthesis process in GUI mode. 56 | - `-top `: Specifies the top module for synthesis. 57 | 58 | #### Example: 59 | ```bash 60 | ./run_syn -gui -top my_top_module 61 | ``` 62 | 63 | --- 64 | 65 | 66 | ### 3. `run_PnR` 67 | This script is used for running place and route using Cadence Innovus. 68 | 69 | #### Features: 70 | - Supports GUI and non-GUI modes. 71 | - Allows specifying the top module for place and route. 72 | 73 | #### Usage: 74 | ```bash 75 | ./run_PnR [options] 76 | ``` 77 | 78 | #### Options: 79 | - `-gui`: Launches the place and route process in GUI mode. 80 | - `-top `: Specifies the top module for place and route. 81 | 82 | #### Example: 83 | ```bash 84 | ./run_PnR -gui -top my_top_module 85 | ``` 86 | 87 | --- 88 | 89 | ## Notes 90 | - Edit `lib/lib_path` file to fit your PDK. 91 | - Each directory contains an `empty_file_for_keep_directory` file. These files are used to preserve empty directory structures in Git repositories. Remove these files when adding actual design content. 92 | - Ensure that the required Cadence tools (Genus, Xcelium, and Innovus) are installed and properly configured in your environment. 93 | - Design libraries are not included and users should modify library paths according to their setup. 94 | - The scripts assume specific directory structures for source files, testbenches, and synthesis outputs. Adjust paths in the scripts if necessary. 95 | - Always backup your work before running automation scripts. 96 | - Review and customize script settings before execution to match your specific design requirements. 97 | -------------------------------------------------------------------------------- /PnR/run_PnR: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # a simple bash script for Cadence Innovus 4 | 5 | echo "Innovus Plance & Route Control Script" 6 | 7 | # read cap_table, target_library and library_search_path from ../lib/lib_path 8 | target_library=$(grep '^target_library=' ../lib/lib_path | cut -d'=' -f2) 9 | library_search_path=$(grep '^library_search_path=' ../lib/lib_path | cut -d'=' -f2) 10 | cap_table=$(grep '^cap_table=' ../lib/lib_path | cut -d'=' -f2) 11 | clockBufName=$(grep '^clockBufName=' ../lib/lib_path | cut -d'=' -f2) 12 | fillerCells=$(grep '^fillerCells=' ../lib/lib_path | cut -d'=' -f2) 13 | lef=$(grep '^lef=' ../lib/lib_path | cut -d'=' -f2) 14 | if [ -z "$target_library" ]; then echo "Error: target_library not found in ../lib/lib_path." ; exit 1 ; fi 15 | if [ -z "$library_search_path" ]; then echo "Error: library_search_path not found in ../lib/lib_path." ; exit 1 ; fi 16 | if [ -z "$cap_table" ]; then echo "Error: cap_table not found in ../lib/lib_path." ; exit 1; fi 17 | if [ -z "$clockBufName" ]; then echo "Error: clockBufName not found in ../lib/lib_path." ; exit 1; fi 18 | if [ -z "$fillerCells" ]; then echo "Error: fillerCells not found in ../lib/lib_path." ; exit 1; fi 19 | if [ -z "$lef" ]; then echo "Error: lef not found in ../lib/lib_path." ; exit 1; fi 20 | 21 | # reset control variables 22 | gui=0 23 | topmodule="" 24 | newtopflag=0 25 | top=0 26 | 27 | # read and process input arguments 28 | for arg in $@ 29 | do 30 | if [ "$arg" == "-gui" ] 31 | then 32 | gui=1 33 | elif [ $newtopflag == 1 ] 34 | then 35 | topmodule=$arg 36 | newtopflag=0 37 | elif [ "$arg" == "-top" ] 38 | then 39 | newtopflag=1 40 | top=1 41 | fi 42 | done 43 | 44 | echo "" 45 | pushd work 46 | 47 | # Create the Default.view file with the correct .sdc file path 48 | cat > ../scripts/Default.view <