├── .github ├── archlinux │ ├── .SRCINFO │ └── PKGBUILD ├── autolabeler.yml └── workflows │ └── arch-pkg.yml ├── .gitignore ├── .gitmodules ├── .readthedocs.yaml ├── .update-contributing.py ├── CODE_OF_CONDUCT.md ├── CONTRIBUTING.md ├── COPYING ├── README.md ├── create-empty-db.sh ├── devices.json ├── diamond.sh ├── diamond_tcl.sh ├── docs ├── .gitignore ├── Makefile ├── architecture │ ├── bitstream_format.rst │ ├── general_routing.rst │ ├── global_routing.rst │ ├── glossary.rst │ ├── overview.rst │ └── tiles.rst ├── conf.py ├── db_dev_process │ └── overview.rst ├── dsp_support │ └── dsp_support.rst ├── index.rst ├── libtrellis │ ├── overview.rst │ └── textconfig.rst ├── markdown_code_symlinks.py └── requirements.txt ├── environment.sh ├── examples ├── .gitignore ├── README.md ├── ecp5_evn │ ├── Makefile │ ├── README.md │ ├── blinky.v │ └── ecp5evn.lpf ├── ecp5_evn_multiboot │ ├── Makefile │ ├── README.md │ ├── blinky1.v │ ├── blinky2.v │ └── ecp5evn.lpf ├── picorv32_tinyfpga │ ├── .gitignore │ ├── Makefile │ ├── attosoc.v │ ├── attosoc_tb.v │ ├── firmware.s │ ├── io_wrapper.v │ ├── picorv32.v │ └── sections.lds ├── picorv32_ulx3s │ ├── .gitignore │ ├── Makefile │ ├── attosoc.v │ ├── attosoc_tb.v │ ├── firmware.s │ ├── io_wrapper.v │ ├── picorv32.v │ └── sections.lds ├── picorv32_versa5g │ ├── .gitignore │ ├── Makefile │ ├── attosoc.v │ ├── attosoc_tb.v │ ├── firmware.s │ ├── io_wrapper.v │ ├── picorv32.v │ └── sections.lds ├── soc_ecp5_evn │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── attosoc.v │ ├── attosoc_tb.v │ ├── ecp5evn.lpf │ ├── firmware.c │ ├── makehex.py │ ├── picorv32.v │ ├── pll.v │ ├── sections.lds │ ├── simpleuart.v │ ├── start.s │ └── top.v ├── soc_versa5g │ ├── .gitignore │ ├── Makefile │ ├── attosoc.v │ ├── attosoc_tb.v │ ├── firmware.c │ ├── makehex.py │ ├── picorv32.v │ ├── pll.v │ ├── sections.lds │ ├── simpleuart.v │ ├── start.s │ ├── top.v │ └── versa.lpf ├── tinyfpga_ax │ ├── .gitignore │ ├── Makefile │ ├── blinky.lpf │ ├── blinky.v │ ├── blinky_ext.lpf │ ├── blinky_ext.v │ ├── uart.lpf │ └── uart.v ├── tinyfpga_rev1 │ ├── Makefile │ ├── blinky.v │ ├── empty_85k.config │ └── morse.v ├── tinyfpga_rev2 │ ├── Makefile │ ├── morse.lpf │ └── morse.v ├── ulx3s │ ├── 12.mk │ ├── 85k.mk │ ├── README.md │ ├── blinky.v │ ├── hello.v │ ├── pll_120.v │ ├── uart.v │ ├── ulx3s_v20.lpf │ └── util.v ├── ulx3s_12k_multiboot │ ├── Makefile │ ├── README.md │ ├── blinky1.v │ ├── blinky2.v │ └── ulx3s.lpf └── versa5g │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── demo.v │ ├── make_14seg.py │ ├── text.in │ └── versa.lpf ├── experiments ├── .gitignore ├── ECP5 │ ├── interconnect_poc │ │ ├── fuzz_single_mux.py │ │ └── mux_template.ncl │ └── lut_init │ │ ├── fuzz_lut_init.py │ │ └── lut_init_template.ncl ├── README.md └── machxo2 │ ├── ccu2_mux │ ├── ccu2_mux.py │ └── ccu2_template.ncl │ ├── center_mux │ ├── center_mux.py │ └── center_mux_template.ncl │ ├── findnets │ ├── findnets.py │ └── plc2route.ncl │ ├── interconnect_poc │ ├── fuzz_single_mux.py │ └── mux_template.ncl │ └── io_params │ ├── .gitignore │ ├── io_params.py │ └── io_params_template.v ├── fuzzers ├── .gitignore ├── ECP5 │ ├── 001-plc2_routing │ │ ├── fuzzer.py │ │ └── plc2route.ncl │ ├── 003-lut_init │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lut.ncl │ ├── 005-reg_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── reg.ncl │ ├── 007-plc2_cemux │ │ ├── cemux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 008-plc2_clkmux │ │ ├── clkmux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 009-plc2_lsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lsr.ncl │ ├── 010-plc2_modes │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── modes.ncl │ ├── 011-ccu2_inject │ │ ├── ccu2.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 012-ccu2_nmux │ │ ├── ccu2.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 013-plc2_mkmux │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── mkmux.ncl │ ├── 014-plc2_wremux │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── wremux.ncl │ ├── 017-patch_carry │ │ └── fuzzer.py │ ├── 020-tap_drive │ │ ├── fuzzer.py │ │ └── tap.ncl │ ├── 021-spine │ │ ├── fuzzer.py │ │ ├── spine_25k.ncl │ │ ├── spine_45k.ncl │ │ └── spine_85k.ncl │ ├── 023-cmux │ │ ├── cmux_25k.ncl │ │ ├── cmux_45k.ncl │ │ ├── cmux_85k.ncl │ │ └── fuzzer.py │ ├── 025-midmux │ │ ├── emux_25k.ncl │ │ ├── emux_45k.ncl │ │ ├── emux_85k.ncl │ │ └── fuzzer.py │ ├── 026-dcc │ │ ├── dcc.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 027-dcs │ │ ├── dcs.ncl │ │ ├── dcs_25k.ncl │ │ ├── dcs_85k.ncl │ │ ├── empty.ncl │ │ ├── empty_25k.ncl │ │ ├── empty_85k.ncl │ │ └── fuzzer.py │ ├── 028-copy_midmux │ │ └── fuzzer.py │ ├── 030-cib_routing │ │ ├── cibroute.ncl │ │ └── fuzzer.py │ ├── 031-cib_lr_routing │ │ ├── cibroute.ncl │ │ └── fuzzer.py │ ├── 033-copy_cib_routing │ │ └── fuzzer.py │ ├── 040-ebr_routing │ │ ├── ebrroute.ncl │ │ └── fuzzer.py │ ├── 041-ebr_config │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 042-ebr_mux │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 043-cib_constmux │ │ ├── cibconst.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 045-copy_cib_routing_2 │ │ └── fuzzer.py │ ├── 047-copy_ebr_config │ │ └── fuzzer.py │ ├── 050-pio_routing │ │ ├── fuzzer.py │ │ ├── pioroute.ncl │ │ └── pioroute_spicb.ncl │ ├── 051-pio_ioconfig │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pio.lpf │ │ └── pio.v │ ├── 053-pio_term │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pio.lpf │ │ └── pio.v │ ├── 057-bankref │ │ ├── empty.ncl │ │ ├── empty_25k.ncl │ │ ├── empty_85k.ncl │ │ ├── fuzzer.py │ │ └── pio.v │ ├── 060-iologic_modes │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 061-basic_ddr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 063-oddrxn │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 064-iddrxn │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 065-mddrx │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 066-iodelay │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 067-ioreg │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── iologic.ncl │ ├── 069-copy_pio_data │ │ └── fuzzer.py │ ├── 070-dsp_routing │ │ ├── dsproute.ncl │ │ └── fuzzer.py │ ├── 071-dsp_constmux │ │ ├── dspconfig.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 073-mult18_config │ │ ├── dspconfig.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 075-alu54b_config │ │ ├── dspconfig.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 076-dsp_cibo │ │ ├── dspconfig.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 077-copy_dsp_config │ │ └── fuzzer.py │ ├── 090-pll_routing │ │ ├── fuzzer.py │ │ ├── pllroute.ncl │ │ ├── pllroute_25k.ncl │ │ └── pllroute_85k.ncl │ ├── 091-pll_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── pllconfig.ncl │ ├── 095-copy_pllconfig │ │ └── fuzzer.py │ ├── 100-usrmclk │ │ ├── cclk.ncl │ │ ├── cclk_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 101-dtr │ │ ├── dtr.ncl │ │ ├── dtr_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 102-oscg │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── osc.ncl │ │ └── osc_routing.ncl │ ├── 103-gsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── gsr.ncl │ │ ├── gsr_routing.ncl │ │ ├── gsr_routing_25k.ncl │ │ └── gsr_routing_85k.ncl │ ├── 104-jtagg │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── jtag.ncl │ │ └── jtag_routing.ncl │ ├── 105-sedga │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── sed.ncl │ │ └── sed_routing.ncl │ ├── 110-dcu_routing │ │ ├── dcuroute.ncl │ │ └── fuzzer.py │ ├── 112-dcu_config │ │ ├── dcuconfig.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 114-extrefb │ │ ├── empty.ncl │ │ ├── extref.ncl │ │ ├── extref_routing.ncl │ │ └── fuzzer.py │ ├── 116-midmux-dcu │ │ ├── emux_25k.ncl │ │ ├── emux_45k.ncl │ │ ├── emux_85k.ncl │ │ └── fuzzer.py │ ├── 117-pcsclkdiv │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pcsclkdiv.ncl │ │ └── pcsclkdiv_routing.ncl │ ├── 120-clkdiv │ │ ├── clkdiv.ncl │ │ ├── clkdiv_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 121-eclk │ │ ├── emux_45k.ncl │ │ └── fuzzer.py │ ├── 122-eclksync │ │ ├── eclksync.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 125-brgeclk │ │ ├── emux_45k.ncl │ │ └── fuzzer.py │ ├── 126-eclkbridgecs │ │ ├── eclkbridge.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 130-dqsbuf │ │ ├── dqsbuf.ncl │ │ ├── dqsbuf_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 132-dlldel │ │ ├── dlldel.ncl │ │ ├── dlldel_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 133-ddrdll │ │ ├── ddrdll.ncl │ │ ├── ddrdll_25k.ncl │ │ ├── ddrdll_routing.ncl │ │ ├── ddrdll_routing_25k.ncl │ │ ├── empty.ncl │ │ ├── empty_25k.ncl │ │ └── fuzzer.py │ ├── 140-sysconfig │ │ ├── empty.ncl │ │ ├── empty.prf │ │ └── fuzzer.py │ ├── 142-bitargs │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 143-bankref8 │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pio.lpf │ │ └── pio.v │ ├── 144-bootaddr │ │ └── fuzzer.py │ └── 900-db_fixup │ │ └── fuzzer.py ├── README.md ├── machxo2 │ ├── 001-plc2_routing │ │ ├── fuzzer.py │ │ └── plc2route.ncl │ ├── 003-lut_init │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lut.ncl │ ├── 005-reg_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── reg.ncl │ ├── 007-plc2_cemux │ │ ├── cemux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 008-plc2_clkmux │ │ ├── clkmux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 009-plc2_lsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lsr.ncl │ ├── 010-plc2_modes │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── modes.ncl │ ├── 011-ccu2_inject │ │ ├── ccu2.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 014-plc2_wremux │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── wremux.ncl │ ├── 017-patch_carry │ │ └── fuzzer.py │ ├── 020-center-mux │ │ ├── 1200 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ ├── 2000 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ ├── 4000 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ └── 7000 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ ├── 021-glb-entry │ │ ├── 1200 │ │ │ ├── empty.ncl │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ └── 7000 │ │ │ ├── empty.ncl │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ ├── 022-glb-cib_ebr │ │ ├── 1200 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 2000 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 4000 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ └── 7000 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ ├── 023-glb-dcc │ │ ├── 1200 │ │ │ ├── dcc.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 7000 │ │ │ ├── dcc.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 024-glb-branch │ │ ├── fuzzer.py │ │ ├── tap_1200.ncl │ │ ├── tap_2000.ncl │ │ ├── tap_4000.ncl │ │ └── tap_7000.ncl │ ├── 025-glb-dcm │ │ ├── 1200 │ │ │ ├── dcm.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 7000 │ │ │ ├── dcm.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 034-cib_ebrn │ │ ├── cibroute_1200.ncl │ │ ├── cibroute_2000.ncl │ │ ├── cibroute_4000.ncl │ │ ├── cibroute_7000.ncl │ │ └── fuzzer.py │ ├── 035-copy-cib_ebr0 │ │ └── fuzzer.py │ ├── 040-ebr_routing │ │ ├── ebrroute.ncl │ │ ├── fuzzer.py │ │ └── mk_nets.py │ ├── 041-ebr_config │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 042-ebr_mux │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 047-copy_ebr_config │ │ └── fuzzer.py │ ├── 050-pio_routing │ │ ├── fuzzer.py │ │ ├── mk_nets.py │ │ ├── pioroute_1200.ncl │ │ ├── pioroute_2000.ncl │ │ ├── pioroute_4000.ncl │ │ └── pioroute_7000.ncl │ ├── 051-pio_attrs │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── empty_4000.ncl │ │ ├── empty_7000.ncl │ │ ├── fuzzer.py │ │ ├── pio.lpf │ │ └── pio.v │ ├── 052-pio_fixup │ │ └── fuzzer.py │ ├── 054-pgmux │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── empty_7000.ncl │ │ ├── fuzzer.py │ │ ├── pio_1200.ncl │ │ ├── pio_2000.ncl │ │ └── pio_7000.ncl │ ├── 057-bankref │ │ ├── empty_1200.ncl │ │ ├── fuzzer.py │ │ └── pio.v │ ├── 059-copy-pio_routing │ │ └── fuzzer.py │ ├── 060-iologic_modes │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1200.ncl │ │ └── iologic_2000.ncl │ ├── 061-basic_ddr │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1200.ncl │ │ └── iologic_2000.ncl │ ├── 063-oddrxn │ │ ├── empty_1200.ncl │ │ ├── fuzzer.py │ │ └── iologic_1200.ncl │ ├── 064-iddrxn │ │ ├── empty_1200.ncl │ │ ├── fuzzer.py │ │ └── iologic_1200.ncl │ ├── 066-iodelay │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1200.ncl │ │ └── iologic_2000.ncl │ ├── 067-ioreg │ │ ├── empty_1200.ncl │ │ ├── empty_2000.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1200.ncl │ │ └── iologic_2000.ncl │ ├── 069-copy_pio_data │ │ └── fuzzer.py │ ├── 090-pll_routing │ │ ├── fuzzer.py │ │ ├── mk_nets.py │ │ ├── pllroute_1200.ncl │ │ ├── pllroute_2000.ncl │ │ ├── pllroute_4000.ncl │ │ ├── pllroute_4000R.ncl │ │ ├── pllroute_7000.ncl │ │ └── pllroute_7000R.ncl │ ├── 091-pll_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── pllconfig.ncl │ ├── 102-oscg │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── osc.ncl │ │ └── osc_routing.ncl │ ├── 103-gsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── gsr.ncl │ │ └── gsr_routing.ncl │ ├── 104-jtagf │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── jtag.ncl │ │ ├── routing_1200.ncl │ │ ├── routing_2000.ncl │ │ ├── routing_4000.ncl │ │ └── routing_7000.ncl │ ├── 105-sedfa │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── sed.ncl │ │ ├── sed_mode.ncl │ │ └── sed_routing.ncl │ ├── 106-tsall │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── tsall.ncl │ │ └── tsall_routing.ncl │ ├── 107-start │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── start.ncl │ │ └── start_routing.ncl │ ├── 108-pcntr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pcntr.ncl │ │ └── pcntr_routing.ncl │ ├── 109-efb │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── routing_1200.ncl │ │ ├── routing_2000.ncl │ │ ├── routing_4000.ncl │ │ └── routing_7000.ncl │ ├── 120-clkdiv │ │ ├── 1200 │ │ │ ├── clkdiv.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 2000 │ │ │ ├── clkdiv.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 121-eclk │ │ ├── fuzzer.py │ │ ├── routing_1200.ncl │ │ ├── routing_2000.ncl │ │ ├── routing_4000.ncl │ │ └── routing_7000.ncl │ ├── 122-eclksync │ │ ├── 1200 │ │ │ ├── eclksync.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 2000 │ │ │ ├── eclksync.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 126-eclkbridgecs │ │ ├── 1200 │ │ │ ├── eclkbridge.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 7000 │ │ │ ├── eclkbridge.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 132-dlldel │ │ ├── 1200 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 2000 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 4000 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 7000 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 133-dqsdll │ │ ├── dqsdll.ncl │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── routing_1200.ncl │ │ ├── routing_2000.ncl │ │ ├── routing_4000.ncl │ │ └── routing_7000.ncl │ ├── 140-sysconfig │ │ ├── empty.ncl │ │ ├── empty.prf │ │ └── fuzzer.py │ ├── 142-bitargs │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 900-db_fixup │ │ └── fuzzer.py ├── machxo3 │ ├── 001-plc2_routing │ │ ├── fuzzer.py │ │ └── plc2route.ncl │ ├── 003-lut_init │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lut.ncl │ ├── 005-reg_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── reg.ncl │ ├── 007-plc2_cemux │ │ ├── cemux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 008-plc2_clkmux │ │ ├── clkmux.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 009-plc2_lsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── lsr.ncl │ ├── 010-plc2_modes │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── modes.ncl │ ├── 011-ccu2_inject │ │ ├── ccu2.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 014-plc2_wremux │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── wremux.ncl │ ├── 017-patch_carry │ │ └── fuzzer.py │ ├── 020-center-mux │ │ ├── 1300 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ ├── 2100 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ ├── 4300 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ ├── 6900 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ │ └── 9400 │ │ │ ├── center-mux.ncl │ │ │ ├── fuzzer.py │ │ │ └── mk_nets.py │ ├── 021-glb-entry │ │ ├── 1300 │ │ │ ├── empty.ncl │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 6900 │ │ │ ├── empty.ncl │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ └── 9400 │ │ │ ├── empty.ncl │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ ├── 022-glb-cib_ebr │ │ ├── 1300 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 2100 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 4300 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ ├── 6900 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ │ └── 9400 │ │ │ ├── fuzzer.py │ │ │ └── tap.ncl │ ├── 023-glb-dcc │ │ ├── 1300 │ │ │ ├── dcc.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 6900 │ │ │ ├── dcc.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 9400 │ │ │ ├── dcc.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 024-glb-branch │ │ ├── fuzzer.py │ │ ├── tap_1300.ncl │ │ ├── tap_2100.ncl │ │ ├── tap_4300.ncl │ │ ├── tap_6900.ncl │ │ └── tap_9400.ncl │ ├── 025-glb-dcm │ │ ├── 1300 │ │ │ ├── dcm.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 6900 │ │ │ ├── dcm.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 9400 │ │ │ ├── dcm.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 034-cib_ebrn │ │ ├── cibroute_1300.ncl │ │ ├── cibroute_2100.ncl │ │ ├── cibroute_4300.ncl │ │ ├── cibroute_6900.ncl │ │ ├── cibroute_9400.ncl │ │ └── fuzzer.py │ ├── 035-copy-cib_ebr0 │ │ └── fuzzer.py │ ├── 040-ebr_routing │ │ ├── ebrroute.ncl │ │ ├── fuzzer.py │ │ └── mk_nets.py │ ├── 041-ebr_config │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 042-ebr_mux │ │ ├── ebr.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 047-copy_ebr_config │ │ └── fuzzer.py │ ├── 050-pio_routing │ │ ├── fuzzer.py │ │ ├── mk_nets.py │ │ ├── pioroute_1300.ncl │ │ ├── pioroute_2100.ncl │ │ ├── pioroute_4300.ncl │ │ ├── pioroute_6900.ncl │ │ └── pioroute_9400.ncl │ ├── 051-pio_attrs │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── empty_4300.ncl │ │ ├── empty_6900.ncl │ │ ├── empty_9400.ncl │ │ ├── fuzzer.py │ │ ├── pio.lpf │ │ └── pio.v │ ├── 052-pio_fixup │ │ └── fuzzer.py │ ├── 054-pgmux │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── empty_6900.ncl │ │ ├── fuzzer.py │ │ ├── pio_1300.ncl │ │ ├── pio_2100.ncl │ │ └── pio_6900.ncl │ ├── 057-bankref │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── empty_4300.ncl │ │ ├── empty_6900.ncl │ │ ├── empty_9400.ncl │ │ ├── fuzzer.py │ │ └── pio.v │ ├── 059-copy-pio_routing │ │ └── fuzzer.py │ ├── 060-iologic_modes │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1300.ncl │ │ └── iologic_2100.ncl │ ├── 061-basic_ddr │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1300.ncl │ │ └── iologic_2100.ncl │ ├── 063-oddrxn │ │ ├── empty_1300.ncl │ │ ├── fuzzer.py │ │ └── iologic_1300.ncl │ ├── 064-iddrxn │ │ ├── empty_1300.ncl │ │ ├── fuzzer.py │ │ └── iologic_1300.ncl │ ├── 066-iodelay │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1300.ncl │ │ └── iologic_2100.ncl │ ├── 067-ioreg │ │ ├── empty_1300.ncl │ │ ├── empty_2100.ncl │ │ ├── fuzzer.py │ │ ├── iologic_1300.ncl │ │ └── iologic_2100.ncl │ ├── 069-copy_pio_data │ │ └── fuzzer.py │ ├── 090-pll_routing │ │ ├── fuzzer.py │ │ ├── mk_nets.py │ │ ├── pllroute_1300.ncl │ │ ├── pllroute_2100.ncl │ │ ├── pllroute_4300.ncl │ │ ├── pllroute_4300R.ncl │ │ ├── pllroute_6900.ncl │ │ ├── pllroute_6900R.ncl │ │ ├── pllroute_9400.ncl │ │ └── pllroute_9400R.ncl │ ├── 091-pll_config │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── pllconfig.ncl │ ├── 102-oscg │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── osc.ncl │ │ └── osc_routing.ncl │ ├── 103-gsr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── gsr.ncl │ │ └── gsr_routing.ncl │ ├── 104-jtagf │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── jtag.ncl │ │ ├── routing_1300.ncl │ │ ├── routing_2100.ncl │ │ ├── routing_4300.ncl │ │ ├── routing_6900.ncl │ │ └── routing_9400.ncl │ ├── 105-sedfa │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── sed.ncl │ │ ├── sed_mode.ncl │ │ └── sed_routing.ncl │ ├── 106-tsall │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── tsall.ncl │ │ └── tsall_routing.ncl │ ├── 107-start │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── start.ncl │ │ └── start_routing.ncl │ ├── 108-pcntr │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── pcntr.ncl │ │ └── pcntr_routing.ncl │ ├── 109-efb │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── routing_1300.ncl │ │ ├── routing_2100.ncl │ │ ├── routing_4300.ncl │ │ ├── routing_6900.ncl │ │ └── routing_9400.ncl │ ├── 120-clkdiv │ │ ├── 1300 │ │ │ ├── clkdiv.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 2100 │ │ │ ├── clkdiv.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 121-eclk │ │ ├── fuzzer.py │ │ ├── routing_1300.ncl │ │ ├── routing_2100.ncl │ │ ├── routing_4300.ncl │ │ ├── routing_6900.ncl │ │ └── routing_9400.ncl │ ├── 122-eclksync │ │ ├── 1300 │ │ │ ├── eclksync.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 2100 │ │ │ ├── eclksync.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 126-eclkbridgecs │ │ ├── 1300 │ │ │ ├── eclkbridge.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 6900 │ │ │ ├── eclkbridge.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 9400 │ │ │ ├── eclkbridge.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 132-dlldel │ │ ├── 1300 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 2100 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 4300 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ ├── 6900 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ │ └── 9400 │ │ │ ├── dlldel.ncl │ │ │ ├── dlldel_routing.ncl │ │ │ ├── empty.ncl │ │ │ └── fuzzer.py │ ├── 133-dqsdll │ │ ├── dqsdll.ncl │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ ├── routing_1300.ncl │ │ ├── routing_2100.ncl │ │ ├── routing_4300.ncl │ │ ├── routing_6900.ncl │ │ └── routing_9400.ncl │ ├── 140-sysconfig │ │ ├── empty.ncl │ │ ├── empty.prf │ │ └── fuzzer.py │ ├── 142-bitargs │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 900-db_fixup │ │ └── fuzzer.py └── machxo3d │ ├── 001-plc2_routing │ ├── fuzzer.py │ └── plc2route.ncl │ ├── 003-lut_init │ ├── empty.ncl │ ├── fuzzer.py │ └── lut.ncl │ ├── 005-reg_config │ ├── empty.ncl │ ├── fuzzer.py │ └── reg.ncl │ ├── 007-plc2_cemux │ ├── cemux.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 008-plc2_clkmux │ ├── clkmux.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 009-plc2_lsr │ ├── empty.ncl │ ├── fuzzer.py │ └── lsr.ncl │ ├── 010-plc2_modes │ ├── empty.ncl │ ├── fuzzer.py │ └── modes.ncl │ ├── 011-ccu2_inject │ ├── ccu2.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 014-plc2_wremux │ ├── empty.ncl │ ├── fuzzer.py │ └── wremux.ncl │ ├── 017-patch_carry │ └── fuzzer.py │ ├── 020-center-mux │ ├── 4300 │ │ ├── center-mux.ncl │ │ ├── fuzzer.py │ │ └── mk_nets.py │ └── 9400 │ │ ├── center-mux.ncl │ │ ├── fuzzer.py │ │ └── mk_nets.py │ ├── 021-glb-entry │ ├── 4300 │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── tap.ncl │ └── 9400 │ │ ├── empty.ncl │ │ ├── fuzzer.py │ │ └── tap.ncl │ ├── 022-glb-cib_ebr │ ├── 4300 │ │ ├── fuzzer.py │ │ └── tap.ncl │ └── 9400 │ │ ├── fuzzer.py │ │ └── tap.ncl │ ├── 023-glb-dcc │ ├── 4300 │ │ ├── dcc.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 9400 │ │ ├── dcc.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 024-glb-branch │ ├── fuzzer.py │ ├── tap_4300.ncl │ └── tap_9400.ncl │ ├── 025-glb-dcm │ ├── 4300 │ │ ├── dcm.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 9400 │ │ ├── dcm.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 034-cib_ebrn │ ├── cibroute_4300.ncl │ ├── cibroute_9400.ncl │ └── fuzzer.py │ ├── 035-copy-cib_ebr0 │ └── fuzzer.py │ ├── 040-ebr_routing │ ├── ebrroute.ncl │ ├── fuzzer.py │ └── mk_nets.py │ ├── 041-ebr_config │ ├── ebr.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 042-ebr_mux │ ├── ebr.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 047-copy_ebr_config │ └── fuzzer.py │ ├── 050-pio_routing │ ├── fuzzer.py │ ├── mk_nets.py │ ├── pioroute_4300.ncl │ └── pioroute_9400.ncl │ ├── 051-pio_attrs │ ├── empty_9400.ncl │ ├── fuzzer.py │ ├── pio.lpf │ └── pio.v │ ├── 052-pio_fixup │ └── fuzzer.py │ ├── 054-pgmux │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── pio_9400.ncl │ ├── 057-bankref │ ├── empty_4300.ncl │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── pio.v │ ├── 059-copy-pio_routing │ └── fuzzer.py │ ├── 060-iologic_modes │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 061-basic_ddr │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 063-oddrxn │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 064-iddrxn │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 066-iodelay │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 067-ioreg │ ├── empty_9400.ncl │ ├── fuzzer.py │ └── iologic_9400.ncl │ ├── 069-copy_pio_data │ └── fuzzer.py │ ├── 090-pll_routing │ ├── fuzzer.py │ ├── mk_nets.py │ ├── pllroute_4300.ncl │ ├── pllroute_4300R.ncl │ ├── pllroute_9400.ncl │ └── pllroute_9400R.ncl │ ├── 091-pll_config │ ├── empty.ncl │ ├── fuzzer.py │ └── pllconfig.ncl │ ├── 102-oscj │ ├── empty.ncl │ ├── fuzzer.py │ ├── osc.ncl │ └── osc_routing.ncl │ ├── 103-gsr │ ├── empty.ncl │ ├── fuzzer.py │ ├── gsr.ncl │ └── gsr_routing.ncl │ ├── 104-jtagf │ ├── empty.ncl │ ├── fuzzer.py │ ├── jtag.ncl │ ├── routing_4300.ncl │ └── routing_9400.ncl │ ├── 105-sedfa │ ├── empty.ncl │ ├── fuzzer.py │ ├── sed.ncl │ ├── sed_mode.ncl │ └── sed_routing.ncl │ ├── 106-tsall │ ├── empty.ncl │ ├── fuzzer.py │ ├── tsall.ncl │ └── tsall_routing.ncl │ ├── 107-start │ ├── empty.ncl │ ├── fuzzer.py │ ├── start.ncl │ └── start_routing.ncl │ ├── 108-pcntr │ ├── empty.ncl │ ├── fuzzer.py │ ├── pcntr.ncl │ └── pcntr_routing.ncl │ ├── 109-efb │ ├── fuzzer.py │ ├── routing_4300.ncl │ └── routing_9400.ncl │ ├── 120-clkdiv │ ├── clkdiv.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 121-eclk │ ├── fuzzer.py │ ├── routing_4300.ncl │ └── routing_9400.ncl │ ├── 122-eclksync │ ├── eclksync.ncl │ ├── empty.ncl │ └── fuzzer.py │ ├── 126-eclkbridgecs │ ├── 4300 │ │ ├── eclkbridge.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 9400 │ │ ├── eclkbridge.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 132-dlldel │ ├── 4300 │ │ ├── dlldel.ncl │ │ ├── dlldel_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ └── 9400 │ │ ├── dlldel.ncl │ │ ├── dlldel_routing.ncl │ │ ├── empty.ncl │ │ └── fuzzer.py │ ├── 133-dqsdll │ ├── dqsdll.ncl │ ├── empty.ncl │ ├── fuzzer.py │ ├── routing_4300.ncl │ └── routing_9400.ncl │ ├── 140-sysconfig │ ├── empty.ncl │ ├── empty.prf │ └── fuzzer.py │ ├── 142-bitargs │ ├── empty.ncl │ └── fuzzer.py │ └── 900-db_fixup │ └── fuzzer.py ├── libtrellis ├── .gitignore ├── 3rdparty │ └── pybind11 │ │ ├── .appveyor.yml │ │ ├── .clang-format │ │ ├── .clang-tidy │ │ ├── .cmake-format.yaml │ │ ├── .codespell-ignore-lines │ │ ├── .gitattributes │ │ ├── .github │ │ ├── CODEOWNERS │ │ ├── CONTRIBUTING.md │ │ ├── ISSUE_TEMPLATE │ │ │ ├── bug-report.md │ │ │ ├── bug-report.yml │ │ │ ├── config.yml │ │ │ ├── feature-request.md │ │ │ └── question.md │ │ ├── dependabot.yml │ │ ├── labeler.yml │ │ ├── labeler_merged.yml │ │ ├── matchers │ │ │ └── pylint.json │ │ ├── pull_request_template.md │ │ └── workflows │ │ │ ├── ci.yml │ │ │ ├── configure.yml │ │ │ ├── format.yml │ │ │ ├── labeler.yml │ │ │ ├── pip.yml │ │ │ └── upstream.yml │ │ ├── .gitignore │ │ ├── .pre-commit-config.yaml │ │ ├── .readthedocs.yml │ │ ├── CMakeLists.txt │ │ ├── LICENSE │ │ ├── MANIFEST.in │ │ ├── README.rst │ │ ├── docs │ │ ├── Doxyfile │ │ ├── _static │ │ │ ├── css │ │ │ │ └── custom.css │ │ │ └── theme_overrides.css │ │ ├── advanced │ │ │ ├── cast │ │ │ │ ├── chrono.rst │ │ │ │ ├── custom.rst │ │ │ │ ├── eigen.rst │ │ │ │ ├── functional.rst │ │ │ │ ├── index.rst │ │ │ │ ├── overview.rst │ │ │ │ ├── stl.rst │ │ │ │ └── strings.rst │ │ │ ├── classes.rst │ │ │ ├── embedding.rst │ │ │ ├── exceptions.rst │ │ │ ├── functions.rst │ │ │ ├── misc.rst │ │ │ ├── pycpp │ │ │ │ ├── index.rst │ │ │ │ ├── numpy.rst │ │ │ │ ├── object.rst │ │ │ │ └── utilities.rst │ │ │ └── smart_ptrs.rst │ │ ├── basics.rst │ │ ├── benchmark.py │ │ ├── benchmark.rst │ │ ├── changelog.rst │ │ ├── classes.rst │ │ ├── cmake │ │ │ └── index.rst │ │ ├── compiling.rst │ │ ├── conf.py │ │ ├── faq.rst │ │ ├── index.rst │ │ ├── installing.rst │ │ ├── limitations.rst │ │ ├── pybind11-logo.png │ │ ├── pybind11_vs_boost_python1.png │ │ ├── pybind11_vs_boost_python1.svg │ │ ├── pybind11_vs_boost_python2.png │ │ ├── pybind11_vs_boost_python2.svg │ │ ├── reference.rst │ │ ├── release.rst │ │ ├── requirements.txt │ │ └── upgrade.rst │ │ ├── include │ │ └── pybind11 │ │ │ ├── attr.h │ │ │ ├── buffer_info.h │ │ │ ├── cast.h │ │ │ ├── chrono.h │ │ │ ├── common.h │ │ │ ├── complex.h │ │ │ ├── detail │ │ │ ├── class.h │ │ │ ├── common.h │ │ │ ├── descr.h │ │ │ ├── init.h │ │ │ ├── internals.h │ │ │ ├── type_caster_base.h │ │ │ └── typeid.h │ │ │ ├── eigen.h │ │ │ ├── embed.h │ │ │ ├── eval.h │ │ │ ├── functional.h │ │ │ ├── gil.h │ │ │ ├── iostream.h │ │ │ ├── numpy.h │ │ │ ├── operators.h │ │ │ ├── options.h │ │ │ ├── pybind11.h │ │ │ ├── pytypes.h │ │ │ ├── stl.h │ │ │ ├── stl │ │ │ └── filesystem.h │ │ │ └── stl_bind.h │ │ ├── noxfile.py │ │ ├── pybind11 │ │ ├── __init__.py │ │ ├── __main__.py │ │ ├── _version.py │ │ ├── _version.pyi │ │ ├── commands.py │ │ ├── py.typed │ │ ├── setup_helpers.py │ │ └── setup_helpers.pyi │ │ ├── pyproject.toml │ │ ├── setup.cfg │ │ ├── setup.py │ │ ├── tests │ │ ├── CMakeLists.txt │ │ ├── conftest.py │ │ ├── constructor_stats.h │ │ ├── cross_module_gil_utils.cpp │ │ ├── cross_module_interleaved_error_already_set.cpp │ │ ├── env.py │ │ ├── extra_python_package │ │ │ ├── pytest.ini │ │ │ └── test_files.py │ │ ├── extra_setuptools │ │ │ ├── pytest.ini │ │ │ └── test_setuphelper.py │ │ ├── local_bindings.h │ │ ├── object.h │ │ ├── pybind11_cross_module_tests.cpp │ │ ├── pybind11_tests.cpp │ │ ├── pybind11_tests.h │ │ ├── pytest.ini │ │ ├── requirements.txt │ │ ├── test_async.cpp │ │ ├── test_async.py │ │ ├── test_buffers.cpp │ │ ├── test_buffers.py │ │ ├── test_builtin_casters.cpp │ │ ├── test_builtin_casters.py │ │ ├── test_call_policies.cpp │ │ ├── test_call_policies.py │ │ ├── test_callbacks.cpp │ │ ├── test_callbacks.py │ │ ├── test_chrono.cpp │ │ ├── test_chrono.py │ │ ├── test_class.cpp │ │ ├── test_class.py │ │ ├── test_cmake_build │ │ │ ├── CMakeLists.txt │ │ │ ├── embed.cpp │ │ │ ├── installed_embed │ │ │ │ └── CMakeLists.txt │ │ │ ├── installed_function │ │ │ │ └── CMakeLists.txt │ │ │ ├── installed_target │ │ │ │ └── CMakeLists.txt │ │ │ ├── main.cpp │ │ │ ├── subdirectory_embed │ │ │ │ └── CMakeLists.txt │ │ │ ├── subdirectory_function │ │ │ │ └── CMakeLists.txt │ │ │ ├── subdirectory_target │ │ │ │ └── CMakeLists.txt │ │ │ └── test.py │ │ ├── test_const_name.cpp │ │ ├── test_const_name.py │ │ ├── test_constants_and_functions.cpp │ │ ├── test_constants_and_functions.py │ │ ├── test_copy_move.cpp │ │ ├── test_copy_move.py │ │ ├── test_custom_type_casters.cpp │ │ ├── test_custom_type_casters.py │ │ ├── test_custom_type_setup.cpp │ │ ├── test_custom_type_setup.py │ │ ├── test_docstring_options.cpp │ │ ├── test_docstring_options.py │ │ ├── test_eigen.cpp │ │ ├── test_eigen.py │ │ ├── test_embed │ │ │ ├── CMakeLists.txt │ │ │ ├── catch.cpp │ │ │ ├── external_module.cpp │ │ │ ├── test_interpreter.cpp │ │ │ ├── test_interpreter.py │ │ │ └── test_trampoline.py │ │ ├── test_enum.cpp │ │ ├── test_enum.py │ │ ├── test_eval.cpp │ │ ├── test_eval.py │ │ ├── test_eval_call.py │ │ ├── test_exceptions.cpp │ │ ├── test_exceptions.h │ │ ├── test_exceptions.py │ │ ├── test_factory_constructors.cpp │ │ ├── test_factory_constructors.py │ │ ├── test_gil_scoped.cpp │ │ ├── test_gil_scoped.py │ │ ├── test_iostream.cpp │ │ ├── test_iostream.py │ │ ├── test_kwargs_and_defaults.cpp │ │ ├── test_kwargs_and_defaults.py │ │ ├── test_local_bindings.cpp │ │ ├── test_local_bindings.py │ │ ├── test_methods_and_attributes.cpp │ │ ├── test_methods_and_attributes.py │ │ ├── test_modules.cpp │ │ ├── test_modules.py │ │ ├── test_multiple_inheritance.cpp │ │ ├── test_multiple_inheritance.py │ │ ├── test_numpy_array.cpp │ │ ├── test_numpy_array.py │ │ ├── test_numpy_dtypes.cpp │ │ ├── test_numpy_dtypes.py │ │ ├── test_numpy_vectorize.cpp │ │ ├── test_numpy_vectorize.py │ │ ├── test_opaque_types.cpp │ │ ├── test_opaque_types.py │ │ ├── test_operator_overloading.cpp │ │ ├── test_operator_overloading.py │ │ ├── test_pickling.cpp │ │ ├── test_pickling.py │ │ ├── test_pytypes.cpp │ │ ├── test_pytypes.py │ │ ├── test_sequences_and_iterators.cpp │ │ ├── test_sequences_and_iterators.py │ │ ├── test_smart_ptr.cpp │ │ ├── test_smart_ptr.py │ │ ├── test_stl.cpp │ │ ├── test_stl.py │ │ ├── test_stl_binders.cpp │ │ ├── test_stl_binders.py │ │ ├── test_tagbased_polymorphic.cpp │ │ ├── test_tagbased_polymorphic.py │ │ ├── test_thread.cpp │ │ ├── test_thread.py │ │ ├── test_union.cpp │ │ ├── test_union.py │ │ ├── test_virtual_functions.cpp │ │ ├── test_virtual_functions.py │ │ ├── valgrind-numpy-scipy.supp │ │ └── valgrind-python.supp │ │ └── tools │ │ ├── FindCatch.cmake │ │ ├── FindEigen3.cmake │ │ ├── FindPythonLibsNew.cmake │ │ ├── JoinPaths.cmake │ │ ├── check-style.sh │ │ ├── cmake_uninstall.cmake.in │ │ ├── codespell_ignore_lines_from_errors.py │ │ ├── libsize.py │ │ ├── make_changelog.py │ │ ├── pybind11.pc.in │ │ ├── pybind11Common.cmake │ │ ├── pybind11Config.cmake.in │ │ ├── pybind11NewTools.cmake │ │ ├── pybind11Tools.cmake │ │ ├── pyproject.toml │ │ ├── setup_global.py.in │ │ └── setup_main.py.in ├── CMakeLists.txt ├── README.md ├── examples │ ├── .gitignore │ ├── bit_to_config.py │ ├── compare_bits.py │ ├── config_to_bit.py │ ├── ddgraph.py │ ├── ecp5um45_bits.py │ ├── graph.py │ ├── logic_tile_bits.py │ ├── logic_tile_config.py │ ├── or_to_and.py │ ├── unknown_stats.py │ └── unpack_repack.py ├── include │ ├── Bels.hpp │ ├── BitDatabase.hpp │ ├── Bitstream.hpp │ ├── CRAM.hpp │ ├── Chip.hpp │ ├── ChipConfig.hpp │ ├── Database.hpp │ ├── DatabasePath.hpp │ ├── DedupChipdb.hpp │ ├── RoutingGraph.hpp │ ├── Tile.hpp │ ├── TileConfig.hpp │ ├── Util.hpp │ ├── list_indexing_suite.h │ └── set_indexing_suite.h ├── src │ ├── Bels.cpp │ ├── BitDatabase.cpp │ ├── Bitstream.cpp │ ├── CRAM.cpp │ ├── Chip.cpp │ ├── ChipConfig.cpp │ ├── Database.cpp │ ├── DedupChipdb.cpp │ ├── OptChipdb.cpp │ ├── PyTrellis.cpp │ ├── RoutingGraph.cpp │ ├── Tile.cpp │ ├── TileConfig.cpp │ └── Util.cpp └── tools │ ├── ecpbram.cpp │ ├── ecpmulti.cpp │ ├── ecppack.cpp │ ├── ecppll.cpp │ ├── ecpunpack.cpp │ ├── version.cpp.in │ ├── version.hpp │ └── wasmexcept.hpp ├── metadata └── ECP5 │ ├── LFE5U-12F │ └── globals.json │ ├── LFE5U-25F │ └── globals.json │ ├── LFE5U-45F │ └── globals.json │ ├── LFE5U-85F │ └── globals.json │ ├── LFE5UM-25F │ └── globals.json │ ├── LFE5UM-45F │ └── globals.json │ ├── LFE5UM-85F │ └── globals.json │ ├── LFE5UM5G-25F │ └── globals.json │ ├── LFE5UM5G-45F │ └── globals.json │ └── LFE5UM5G-85F │ └── globals.json ├── minitests ├── .gitignore ├── ECP5 │ ├── dsp │ │ ├── mult.v │ │ ├── mult1.v │ │ ├── mult1n.ncl │ │ └── preadd.v │ ├── iologic │ │ ├── iddr.v │ │ ├── iddr2.v │ │ ├── iddr7.v │ │ ├── iddr_LSR.v │ │ ├── iddr_inv.v │ │ ├── idelay.v │ │ ├── ireg.v │ │ ├── ireg2.v │ │ ├── oddr.v │ │ ├── oddr7.v │ │ ├── oreg.v │ │ ├── oshx2a.v │ │ └── toreg.v │ ├── ncl │ │ ├── lut.ncl │ │ ├── lut_0.ncl │ │ └── lut_or.ncl │ └── potpourri │ │ ├── dtr.v │ │ ├── jtagg.v │ │ ├── osc.v │ │ └── osc_div.ncl ├── README.md ├── config │ ├── usermclk.lpf │ └── usermclk.v ├── ebr │ ├── ebr.v │ ├── ebr_init.v │ ├── ebr_init_rand.dat │ ├── ebr_init_rand.v │ ├── ebr_inv.v │ └── init.py ├── global │ ├── global.lpf │ └── global.v ├── logic_to_global │ └── l2g.v ├── lut │ ├── const_0.v │ ├── const_1.v │ ├── lut.v │ ├── lut4_reg.v │ ├── lut5_reg.v │ └── lut7.v ├── machxo2 │ ├── cb2 │ │ └── cb2.v │ ├── dcc │ │ ├── dcc1.v │ │ └── dcc2.v │ ├── efb2 │ │ └── EFB.v │ ├── osch │ │ ├── osch.lpf │ │ └── osch.v │ ├── pio │ │ └── bb_machxo2.v │ ├── spr │ │ └── spr.v │ └── vref │ │ ├── vref.lpf │ │ └── vref.v ├── pio │ ├── bb.v │ └── ib.v ├── reg │ ├── async.v │ ├── async_gsr.v │ ├── async_sr.v │ ├── ce.v │ ├── ce_0.v │ ├── ce_inv.v │ ├── ce_over_lsr.v │ ├── clk_0.v │ ├── clk_1.v │ ├── clk_inv.v │ ├── ffmux.v │ ├── gsr.v │ ├── gsr2.v │ ├── latch.v │ ├── latch_inv.v │ ├── lsr_inv.v │ ├── lsr_over_ce.v │ ├── lut_reg.v │ ├── plain.v │ ├── reset.v │ ├── set.v │ └── set_inv.v ├── timing │ ├── arc.ncl │ ├── routed.ncl │ ├── routed_long.ncl │ ├── unrouted_long.ncl │ └── unrouted_long_alt.ncl ├── timing_distances │ ├── span2h │ │ ├── .gitignore │ │ └── make_dists.py │ ├── span2v │ │ ├── .gitignore │ │ └── make_dists.py │ └── span6h │ │ ├── .gitignore │ │ └── make_dists.py ├── timing_loads │ ├── local │ │ ├── .gitignore │ │ └── make_loads.py │ └── span2 │ │ ├── .gitignore │ │ └── make_loads.py └── wire │ ├── wire.v │ ├── wire_pad.lpf │ └── wire_pad.v ├── misc ├── basecfgs │ ├── README.md │ ├── empty_lfe5u-25f.config │ ├── empty_lfe5u-45f.config │ ├── empty_lfe5u-85f.config │ ├── empty_lfe5um-25f.config │ ├── empty_lfe5um-45f.config │ ├── empty_lfe5um-85f.config │ ├── empty_lfe5um5g-25f.config │ ├── empty_lfe5um5g-45f.config │ ├── empty_lfe5um5g-85f.config │ └── empty_machxo2-1200hc.config └── openocd │ ├── ecp5-evn.cfg │ ├── ecp5-versa.cfg │ ├── ecp5-versa5g.cfg │ ├── trellisboard.cfg │ ├── ulx3s.cfg │ └── ulx3s_85k.cfg ├── third_party └── README.md ├── timing ├── fuzzers │ ├── .gitignore │ ├── ECP5 │ │ ├── 010-basic-cells │ │ │ └── fuzzer.py │ │ ├── 012-io │ │ │ ├── fuzzer.py │ │ │ └── pio.v │ │ ├── 013-iol │ │ │ ├── fuzzer.py │ │ │ └── pio.v │ │ ├── 014-ebr │ │ │ ├── ebr_regmode.v │ │ │ ├── ebr_writemode.v │ │ │ └── fuzzer.py │ │ ├── 015-mult │ │ │ ├── fuzzer.py │ │ │ └── mult_pipemode.v │ │ └── 020-basic_routing │ │ │ └── fuzzer.py │ ├── MachXO2 │ │ ├── 010-basic-cells │ │ │ └── fuzzer.py │ │ ├── 012-io │ │ │ ├── fuzzer.py │ │ │ └── pio.v │ │ ├── 014-ebr │ │ │ ├── ebr_regmode.v │ │ │ ├── ebr_writemode.v │ │ │ └── fuzzer.py │ │ └── 020-basic_routing │ │ │ └── fuzzer.py │ ├── MachXO3 │ │ ├── 010-basic-cells │ │ │ └── fuzzer.py │ │ ├── 012-io │ │ │ ├── fuzzer.py │ │ │ └── pio.v │ │ ├── 013-iol │ │ │ ├── fuzzer.py │ │ │ └── pio.v │ │ ├── 014-ebr │ │ │ ├── ebr_regmode.v │ │ │ ├── ebr_writemode.v │ │ │ └── fuzzer.py │ │ └── 020-basic_routing │ │ │ └── fuzzer.py │ └── MachXO3D │ │ ├── 010-basic-cells │ │ └── fuzzer.py │ │ ├── 012-io │ │ ├── fuzzer.py │ │ └── pio.v │ │ ├── 014-ebr │ │ ├── ebr_regmode.v │ │ ├── ebr_writemode.v │ │ └── fuzzer.py │ │ └── 020-basic_routing │ │ └── fuzzer.py ├── resource │ ├── altair.v │ ├── distributed_ram.v │ ├── jt49.v │ ├── jt5205.v │ ├── jt7759.v │ ├── math.v │ ├── nescore.v │ ├── picorv32_large.v │ ├── picorv32_large_blockram.v │ └── picorv32_x20.v └── util │ ├── .gitignore │ ├── __init__.py │ ├── cell_fuzzers.py │ ├── cell_html.py │ ├── cell_timings.py │ ├── design_pip_classes.py │ ├── extract_ncl_routing.py │ ├── interconnect_html.py │ ├── parse_sdf.py │ ├── pip_classes.py │ ├── timing_dbs.py │ └── timing_solver.py ├── tools ├── .gitignore ├── README.md ├── __init__.py ├── bit_to_svf.py ├── compare_bits.py ├── connectivity.py ├── create_empty_bitdbs.py ├── demobuilder │ ├── __init__.py │ ├── blinky.py │ ├── design.py │ └── route.py ├── ecp_vlog.py ├── export_baseconfig.py ├── extract_tilegrid.py ├── get_tilegrid_all.py ├── html_all.py ├── html_bits.py ├── html_tilegrid.py └── read_pinout.py └── util ├── common ├── __init__.py ├── database.py ├── devices.py ├── diamond.py ├── isptcl.py ├── nets │ ├── __init__.py │ ├── __main__.py │ ├── ecp5.py │ ├── general.py │ ├── machxo2.py │ └── util.py └── tiles.py └── fuzz ├── dbcopy.py ├── dbfixup.py ├── fuzzconfig.py ├── fuzzloops.py ├── interconnect.py └── nonrouting.py /.github/archlinux/.SRCINFO: -------------------------------------------------------------------------------- 1 | pkgname = prjtrellis-git 2 | -------------------------------------------------------------------------------- /.github/autolabeler.yml: -------------------------------------------------------------------------------- 1 | # Types of things 2 | fuzzers: ["fuzzers"] 3 | minitests: ["minitests"] 4 | experiments: ["experiments"] 5 | 6 | docs: ["docs", "*.md", "COPYING"] 7 | infra: [".travis", ".travis.yml", ".github", "Docker*", ".gcloud*", ".style.yapf", "vagrant", "cloudbuild.*", "download-latest-db.sh"] 8 | tools: ["tools", "utils", "htmlgen"] 9 | libtrellis: ["libtrellis"] 10 | 11 | third-party: ["third_party", ".gitmodules"] 12 | -------------------------------------------------------------------------------- /.github/workflows/arch-pkg.yml: -------------------------------------------------------------------------------- 1 | name: arch-pkg 2 | on: [push, pull_request] 3 | 4 | jobs: 5 | arch-pkg: 6 | runs-on: ubuntu-latest 7 | steps: 8 | - uses: actions/checkout@v4 9 | - name: Build Arch Linux package 10 | uses: 2m/arch-pkgbuild-builder@v1.21 11 | with: 12 | target: 'pkgbuild' 13 | pkgname: '.github/archlinux' 14 | 15 | 16 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | #python 2 | __pycache__/ 3 | *.pyc 4 | 5 | #Environments 6 | /user_environment.sh 7 | *..DS_Store 8 | 9 | #logs 10 | ispTcl.log 11 | ispTcl.log.* 12 | ispTcl.tcl 13 | ispTcl.tcl.* 14 | .ispTcl.lock 15 | work_*/ 16 | 17 | #Editors and IDEs 18 | .*.d 19 | .*.swp 20 | .*.swo 21 | .*.swn 22 | .*.swm 23 | *.log 24 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "database"] 2 | path = database 3 | url = https://github.com/YosysHQ/prjtrellis-db 4 | -------------------------------------------------------------------------------- /.readthedocs.yaml: -------------------------------------------------------------------------------- 1 | version: 2 2 | 3 | build: 4 | os: ubuntu-22.04 5 | tools: 6 | python: '3.11' 7 | 8 | sphinx: 9 | configuration: docs/conf.py 10 | 11 | python: 12 | install: 13 | - requirements: docs/requirements.txt 14 | -------------------------------------------------------------------------------- /create-empty-db.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | rm -rf database 3 | mkdir -p database 4 | echo '*' > database/.gitignore 5 | cp devices.json database/ 6 | cp -r metadata/* database/ 7 | python3 tools/get_tilegrid_all.py 8 | python3 tools/create_empty_bitdbs.py 9 | -------------------------------------------------------------------------------- /docs/.gitignore: -------------------------------------------------------------------------------- 1 | _build 2 | -------------------------------------------------------------------------------- /docs/architecture/overview.rst: -------------------------------------------------------------------------------- 1 | .. _architecture_overview-label: 2 | 3 | Overview 4 | ======== 5 | 6 | The ECP5 FPGA is arranged internally as a grid of :doc:`Tiles `. Each tile contains bits that configure routing 7 | and/or the tile's functionality. 8 | 9 | Inside the ECP5 there is both :doc:`general routing `, which connects nearby tiles together 10 | (spanning up to 12 tiles) and :doc:`global routing `, which allows high fanout signals to connect to all 11 | tiles within a :term:`quadrant` (such as clocks). 12 | -------------------------------------------------------------------------------- /docs/requirements.txt: -------------------------------------------------------------------------------- 1 | docutils 2 | sphinx 3 | sphinx-autobuild 4 | 5 | breathe 6 | recommonmark 7 | sphinx_rtd_theme 8 | sphinxcontrib-napoleon 9 | -------------------------------------------------------------------------------- /examples/.gitignore: -------------------------------------------------------------------------------- 1 | *.bit 2 | *.svf 3 | *.json 4 | *_out.config 5 | *.blif 6 | 7 | -------------------------------------------------------------------------------- /examples/ecp5_evn/README.md: -------------------------------------------------------------------------------- 1 | # ECP5 Evaluation Board Example 2 | 3 | Run `make prog` to load the example to the board. 4 | 5 | You must ensure JP2 is shorted to connect the 12MHz 6 | FTDI clock to the FPGA. -------------------------------------------------------------------------------- /examples/ecp5_evn_multiboot/blinky1.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input btn, output [7:0] led); 2 | reg [23:0] cnt = 0; 3 | 4 | always@(posedge clk) begin 5 | cnt <= cnt + 1; 6 | end 7 | assign led[0] = cnt[22]; 8 | assign led[7:1] = 7'b1111111; 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/ecp5_evn_multiboot/blinky2.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input btn, output [7:0] led); 2 | reg [23:0] cnt = 0; 3 | 4 | always@(posedge clk) begin 5 | cnt <= cnt + 1; 6 | end 7 | assign led[7] = cnt[22]; 8 | assign led[6:0] = 7'b1111111; 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/picorv32_tinyfpga/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.hex 3 | *.json 4 | *_out.config 5 | *.bit 6 | *.vvp 7 | *.vcd -------------------------------------------------------------------------------- /examples/picorv32_tinyfpga/attosoc_tb.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | reg clk; 4 | 5 | always #5 clk = (clk === 1'b0); 6 | 7 | initial begin 8 | $dumpfile("testbench.vcd"); 9 | $dumpvars(0, testbench); 10 | 11 | repeat (10) begin 12 | repeat (256) @(posedge clk); 13 | $display("+256 cycles"); 14 | end 15 | $finish; 16 | end 17 | 18 | wire led; 19 | 20 | always @(led) begin 21 | #1 $display("%b", clk); 22 | end 23 | 24 | attosoc uut ( 25 | .clk (clk ), 26 | .led (led ) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/picorv32_tinyfpga/firmware.s: -------------------------------------------------------------------------------- 1 | start: 2 | li a0, 0x01 3 | li a1, 0x02000000 4 | blink: 5 | sw a0, 0(a1) 6 | xor a0, a0, 0x01 7 | j blink 8 | -------------------------------------------------------------------------------- /examples/picorv32_tinyfpga/io_wrapper.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk_pin, 3 | output led_pin 4 | ); 5 | 6 | wire clk, led; 7 | 8 | reg [17:0] div; 9 | 10 | always @(posedge clk) 11 | div <= div + 1'b1; 12 | 13 | (* LOC="B17" *) (* IO_TYPE="LVCMOS33" *) 14 | TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk)); 15 | 16 | (* LOC="A7" *) (* IO_TYPE="LVCMOS33" *) 17 | TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin), .I(led)); 18 | 19 | attosoc soc( 20 | .clk(div[17]), 21 | .led(led) 22 | ); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/picorv32_ulx3s/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.hex 3 | *.json 4 | *_out.config 5 | *.bit 6 | *.vvp 7 | *.vcd -------------------------------------------------------------------------------- /examples/picorv32_ulx3s/attosoc_tb.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | reg clk; 4 | 5 | always #5 clk = (clk === 1'b0); 6 | 7 | initial begin 8 | $dumpfile("testbench.vcd"); 9 | $dumpvars(0, testbench); 10 | 11 | repeat (10) begin 12 | repeat (256) @(posedge clk); 13 | $display("+256 cycles"); 14 | end 15 | $finish; 16 | end 17 | 18 | wire [7:0] led; 19 | 20 | always @(led) begin 21 | #1 $display("%b", led); 22 | end 23 | 24 | attosoc uut ( 25 | .clk (clk ), 26 | .led (led ) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/picorv32_versa5g/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.hex 3 | *.json 4 | *_out.config 5 | *.bit 6 | *.vvp 7 | *.vcd 8 | *.svf 9 | -------------------------------------------------------------------------------- /examples/picorv32_versa5g/attosoc_tb.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | reg clk; 4 | 5 | always #5 clk = (clk === 1'b0); 6 | 7 | initial begin 8 | $dumpfile("testbench.vcd"); 9 | $dumpvars(0, testbench); 10 | 11 | repeat (10) begin 12 | repeat (256) @(posedge clk); 13 | $display("+256 cycles"); 14 | end 15 | $finish; 16 | end 17 | 18 | wire [7:0] led; 19 | 20 | always @(led) begin 21 | #1 $display("%b", led); 22 | end 23 | 24 | attosoc uut ( 25 | .clk (clk ), 26 | .led (led ) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/soc_ecp5_evn/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.hex 3 | *.json 4 | *_out.config 5 | *.bit 6 | *.vvp 7 | *.vcd 8 | *.svf 9 | *.bin 10 | -------------------------------------------------------------------------------- /examples/soc_ecp5_evn/attosoc_tb.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | reg clk; 4 | 5 | always #5 clk = (clk === 1'b0); 6 | 7 | initial begin 8 | $dumpfile("testbench.vcd"); 9 | $dumpvars(0, testbench); 10 | 11 | repeat (10) begin 12 | repeat (50000) @(posedge clk); 13 | $display("+50000 cycles"); 14 | end 15 | $finish; 16 | end 17 | 18 | wire [7:0] led; 19 | 20 | always @(led) begin 21 | #1 $display("%b", led); 22 | end 23 | 24 | attosoc uut ( 25 | .clk (clk ), 26 | .led (led ) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/soc_ecp5_evn/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clkin, 3 | output [7:0] led, 4 | output uart_tx, 5 | input uart_rx, 6 | output clkout 7 | ); 8 | 9 | wire clk; 10 | wire [7:0] int_led; 11 | 12 | pll_12_50 pll( 13 | .clki(clkin), 14 | .clko(clk) 15 | ); 16 | 17 | attosoc soc( 18 | .clk(clk), 19 | .led(int_led), 20 | .uart_tx(uart_tx), 21 | .uart_rx(uart_rx), 22 | ); 23 | 24 | assign led = ~int_led; 25 | assign clkout = clk; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /examples/soc_versa5g/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.hex 3 | *.json 4 | *_out.config 5 | *.bit 6 | *.vvp 7 | *.vcd 8 | *.svf 9 | *.bin 10 | -------------------------------------------------------------------------------- /examples/soc_versa5g/attosoc_tb.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | reg clk; 4 | 5 | always #5 clk = (clk === 1'b0); 6 | 7 | initial begin 8 | $dumpfile("testbench.vcd"); 9 | $dumpvars(0, testbench); 10 | 11 | repeat (10) begin 12 | repeat (50000) @(posedge clk); 13 | $display("+50000 cycles"); 14 | end 15 | $finish; 16 | end 17 | 18 | wire [7:0] led; 19 | 20 | always @(led) begin 21 | #1 $display("%b", led); 22 | end 23 | 24 | attosoc uut ( 25 | .clk (clk ), 26 | .led (led ) 27 | ); 28 | endmodule 29 | -------------------------------------------------------------------------------- /examples/soc_versa5g/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clkin, 3 | output [7:0] led, 4 | output uart_tx, 5 | input uart_rx, 6 | ); 7 | 8 | wire clk; 9 | wire [7:0] int_led; 10 | 11 | pll_100_50 pll( 12 | .clki(clkin), 13 | .clko(clk) 14 | ); 15 | 16 | attosoc soc( 17 | .clk(clk), 18 | .led(int_led), 19 | .uart_tx(uart_tx), 20 | .uart_rx(uart_rx) 21 | ); 22 | 23 | assign led = ~int_led; 24 | endmodule 25 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/.gitignore: -------------------------------------------------------------------------------- 1 | *.dump 2 | *.twr 3 | *.txt 4 | *.ncl 5 | *.tmp 6 | *.jed 7 | *.hex 8 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/blinky.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "pin1" SITE "13" ; 4 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/blinky.v: -------------------------------------------------------------------------------- 1 | // Modified from: 2 | // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2 3 | 4 | module TinyFPGA_A2 ( 5 | inout pin1 6 | ); 7 | 8 | 9 | wire clk; 10 | 11 | OSCH #( 12 | .NOM_FREQ("2.08") 13 | ) internal_oscillator_inst ( 14 | .STDBY(1'b0), 15 | .OSC(clk) 16 | ); 17 | 18 | reg [23:0] led_timer; 19 | 20 | always @(posedge clk) begin 21 | led_timer <= led_timer + 1; 22 | end 23 | 24 | // left side of board 25 | assign pin1 = led_timer[23]; 26 | endmodule 27 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/blinky_ext.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "pin1" SITE "13" ; 4 | LOCATE COMP "clk" SITE "21" ; 5 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/blinky_ext.v: -------------------------------------------------------------------------------- 1 | // Modified from: 2 | // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2 3 | 4 | module TinyFPGA_A2 ( 5 | inout pin1, 6 | input clk 7 | ); 8 | 9 | reg [23:0] led_timer; 10 | 11 | always @(posedge clk) begin 12 | led_timer <= led_timer + 1; 13 | end 14 | 15 | // left side of board 16 | assign pin1 = led_timer[23]; 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/tinyfpga_ax/uart.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "serial_rx" SITE "13" ; 4 | LOCATE COMP "serial_tx" SITE "14" ; 5 | LOCATE COMP "user_led" SITE "16" ; 6 | LOCATE COMP "user_led_1" SITE "17" ; 7 | LOCATE COMP "user_led_2" SITE "20" ; 8 | LOCATE COMP "user_led_3" SITE "21" ; 9 | LOCATE COMP "user_led_4" SITE "23" ; 10 | LOCATE COMP "clk12" SITE "25" ; 11 | -------------------------------------------------------------------------------- /examples/tinyfpga_rev1/Makefile: -------------------------------------------------------------------------------- 1 | PROJ=morse 2 | 3 | all: ${PROJ}.bit 4 | 5 | %.json: %.v 6 | yosys -p "synth_ecp5 -top top -json $@" $< 7 | 8 | %_out.config: %.json 9 | nextpnr-ecp5 --json $< --textcfg $@ --85k --package CSFBGA285 10 | 11 | %.bit: %_out.config 12 | ecppack $< $@ 13 | 14 | clean: 15 | rm *.bit *.svf *_out.config *.json 16 | 17 | prog: ${PROJ}.bit 18 | tinyprog -p $< 19 | 20 | .PHONY: all clean prog 21 | 22 | -------------------------------------------------------------------------------- /examples/tinyfpga_rev1/blinky.v: -------------------------------------------------------------------------------- 1 | module top(input clk_pin, output led_pin); 2 | 3 | wire clk, led; 4 | 5 | (* LOC="B18" *) (* IO_TYPE="LVCMOS33" *) 6 | TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk)); 7 | 8 | (* LOC="C1" *) (* IO_TYPE="LVCMOS33" *) 9 | TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin), .I(led)); 10 | 11 | reg [23:0] ctr = 0; 12 | always @(posedge clk) 13 | ctr <= ctr + 1'b1; 14 | 15 | assign led = ctr[23]; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /examples/tinyfpga_rev2/Makefile: -------------------------------------------------------------------------------- 1 | PROJ=morse 2 | 3 | all: ${PROJ}.bit 4 | 5 | %.json: %.v 6 | yosys -p "synth_ecp5 -top top -json $@" $< 7 | 8 | %_out.config: %.json 9 | nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --package CSFBGA285 --lpf morse.lpf 10 | 11 | %.bit: %_out.config 12 | ecppack $< $@ 13 | 14 | prog: ${PROJ}.bit 15 | tinyprog -p $< 16 | 17 | clean: 18 | rm -f *.bit *.svf *_out.config *.json 19 | 20 | .PHONY: all prog clean 21 | .PRECIOUS: ${PROJ}.json ${PROJ}_out.config 22 | -------------------------------------------------------------------------------- /examples/tinyfpga_rev2/morse.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "clk" SITE "B17"; 2 | LOCATE COMP "led" SITE "A7"; 3 | 4 | IOBUF PORT "clk" IO_TYPE=LVCMOS33; 5 | IOBUF PORT "led" IO_TYPE=LVCMOS33; 6 | -------------------------------------------------------------------------------- /examples/ulx3s_12k_multiboot/blinky1.v: -------------------------------------------------------------------------------- 1 | module top(input clk, output [7:0] led); 2 | reg [23:0] cnt = 0; 3 | 4 | always@(posedge clk) begin 5 | cnt <= cnt + 1; 6 | end 7 | assign led[0] = cnt[22]; 8 | assign led[7:1] = 7'b1111111; 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/ulx3s_12k_multiboot/blinky2.v: -------------------------------------------------------------------------------- 1 | module top(input clk, output [7:0] led); 2 | reg [23:0] cnt = 0; 3 | 4 | always@(posedge clk) begin 5 | cnt <= cnt + 1; 6 | end 7 | assign led[7] = cnt[22]; 8 | assign led[6:0] = 7'b1111111; 9 | endmodule 10 | -------------------------------------------------------------------------------- /examples/versa5g/.gitignore: -------------------------------------------------------------------------------- 1 | *.vh 2 | *.svf 3 | -------------------------------------------------------------------------------- /examples/versa5g/README.md: -------------------------------------------------------------------------------- 1 | # ECP5 Versa-5G Demo 2 | 3 | Run `make prog` to build & load, LEDs will count and 4 | a message will scroll on the 14-segment display. 5 | 6 | If your Versa board is new, you will need to change 7 | J50 to bypass the iSPclock. Re-arrange the jumpers 8 | to connect pins 1-2 and 3-5 (leaving one jumper spare). 9 | See p19 of the Versa Board user guide. 10 | -------------------------------------------------------------------------------- /examples/versa5g/text.in: -------------------------------------------------------------------------------- 1 | HELLO WORLD FROM PROJECT TRELLIS ON THE VERSA BOARD 2 | -------------------------------------------------------------------------------- /experiments/.gitignore: -------------------------------------------------------------------------------- 1 | *_out.ncl 2 | *.bit 3 | *.dump 4 | *.test 5 | *.incd 6 | *.bin 7 | *.tmp/ 8 | work/ 9 | *_out.txt 10 | *_filter.txt 11 | -------------------------------------------------------------------------------- /experiments/README.md: -------------------------------------------------------------------------------- 1 | ### [Experiments](experiments) 2 | 3 | Experiments are like "minitests" except are only useful for a short period of 4 | time. Files are committed here to allow people to see how we are trying to 5 | understand the bitstream. 6 | -------------------------------------------------------------------------------- /experiments/machxo2/ccu2_mux/ccu2_template.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:CCU2 " 18 | "CCU2::S0=0xfaaa,S1=0xfaaa${muxcfg}" 19 | "FCO:FCO "; 20 | primitive CCU2 "CCU"; 21 | } 22 | site R10C11A; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /experiments/machxo2/io_params/.gitignore: -------------------------------------------------------------------------------- 1 | *_diff.txt 2 | -------------------------------------------------------------------------------- /fuzzers/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.journal 3 | -------------------------------------------------------------------------------- /fuzzers/ECP5/003-lut_init/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/003-lut_init/lut.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:LOGIC " 18 | "K${k}::H${k}=${lut_func} " 19 | "F${k}:F "; 20 | primitive K${k} i3_4_lut; 21 | } 22 | site R19C33${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/ECP5/005-reg_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/007-plc2_cemux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/008-plc2_clkmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/009-plc2_lsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/010-plc2_modes/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/010-plc2_modes/modes.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:${mode} "; 18 | primitive REG0 q_6; 19 | } 20 | site R19C33${slice}; 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /fuzzers/ECP5/011-ccu2_inject/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/012-ccu2_nmux/ccu2.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:CCU2 " 18 | "CCU2::S0=0x9009,S1=0x9009${muxcfg}" 19 | "FCO:FCO "; 20 | primitive CCU2 "CCU"; 21 | } 22 | site R19C33${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/ECP5/012-ccu2_nmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/013-plc2_mkmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/014-plc2_wremux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/014-plc2_wremux/wremux.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:DPRAM " 18 | "DPRAM::DO0=0x0000,DO1=0x0000 " 19 | "WREMUX:${wremux} "; 20 | primitive DPRAM q_6; 21 | } 22 | site R19C33${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/ECP5/017-patch_carry/fuzzer.py: -------------------------------------------------------------------------------- 1 | import pytrellis 2 | 3 | def main(): 4 | pytrellis.load_database("../../../database") 5 | db = pytrellis.get_tile_bitdata(pytrellis.TileLocator("ECP5", "LFE5U-25F", "PLC2")) 6 | fc = pytrellis.FixedConnection() 7 | fc.source = "FCO" 8 | fc.sink = "E1_HFIE0000" 9 | db.add_fixed_conn(fc) 10 | db.save() 11 | 12 | if __name__ == "__main__": 13 | main() 14 | -------------------------------------------------------------------------------- /fuzzers/ECP5/026-dcc/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DCC 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DCC; 15 | ${comment} program "MODE:DCCA " 16 | ${comment} "DCCA::::CE=#SIG"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/026-dcc/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/dcs.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DCS 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DCS; 15 | ${comment} program "MODE:DCSC " 16 | ${comment} "DCSC:::DCSMODE=${dcsmode}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/dcs_25k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DCS 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DCS; 15 | ${comment} program "MODE:DCSC " 16 | ${comment} "DCSC:::DCSMODE=${dcsmode}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/dcs_85k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-85F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DCS 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DCS; 15 | ${comment} program "MODE:DCSC " 16 | ${comment} "DCSC:::DCSMODE=${dcsmode}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/empty_25k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/027-dcs/empty_85k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-85F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/028-copy_midmux/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbcopy 2 | import pytrellis 3 | 4 | def main(): 5 | pytrellis.load_database("../../../database") 6 | dbcopy.dbcopy("ECP5", "LFE5U-25F", "BMID_0V", "BMID_0H", copy_enums=True, copy_words=True) 7 | dbcopy.dbcopy("ECP5", "LFE5U-25F", "BMID_2V", "BMID_2", copy_enums=True, copy_words=True) 8 | 9 | 10 | if __name__ == "__main__": 11 | main() 12 | -------------------------------------------------------------------------------- /fuzzers/ECP5/033-copy_cib_routing/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbcopy 2 | import pytrellis 3 | 4 | 5 | def main(): 6 | pytrellis.load_database("../../../database") 7 | dbcopy.dbcopy("ECP5", "LFE5U-25F", "CIB", "CIB_EBR") 8 | 9 | 10 | if __name__ == "__main__": 11 | main() 12 | -------------------------------------------------------------------------------- /fuzzers/ECP5/041-ebr_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/042-ebr_mux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/043-cib_constmux/cibconst.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp EBR 13 | { 14 | logical { 15 | cellmodel-name EBR; 16 | program "MODE:DP16KD " 17 | "DP16KD:::GSR=DISABLED:\" 18 | "${sig}=${val}"; 19 | } 20 | site EBR_R25C26; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/043-cib_constmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/051-pio_ioconfig/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA554; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/051-pio_ioconfig/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE = ${cfg_vio}; 2 | -------------------------------------------------------------------------------- /fuzzers/ECP5/053-pio_term/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA554; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/053-pio_term/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE = ${cfg_vio}; 2 | -------------------------------------------------------------------------------- /fuzzers/ECP5/057-bankref/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/057-bankref/empty_25k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/057-bankref/empty_85k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-85F; 8 | package CABGA756; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/060-iologic_modes/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/060-iologic_modes/iologic.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | ${comment} comp Q_MGIOL 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${s}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site ${loc}; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/ECP5/061-basic_ddr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/063-oddrxn/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/063-oddrxn/iologic.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name IOLOGIC; 17 | program "MODE:ODDRXN " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/064-iddrxn/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/064-iddrxn/iologic.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name IOLOGIC; 17 | program "MODE:IDDRXN " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/065-mddrx/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/066-iodelay/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/067-ioreg/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/071-dsp_constmux/dspconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | comp MULT 12 | { 13 | logical { 14 | cellmodel-name ${cmodel}; 15 | program "MODE:${mode}" 16 | "${mode}::::${settings}"; 17 | } 18 | site ${loc}; 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/ECP5/071-dsp_constmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/073-mult18_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/075-alu54b_config/dspconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp MULT 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ALU54; 15 | ${comment} program "MODE:${mode} " 16 | ${comment} "${mode}:::${settings}"; 17 | ${comment} } 18 | ${comment} site ${loc}; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/ECP5/075-alu54b_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/076-dsp_cibo/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/091-pll_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/091-pll_config/pllconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp PLL 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PLL; 15 | ${comment} program "MODE:EHXPLLL " 16 | ${comment} "EHXPLLL:::${settings}"; 17 | ${comment} } 18 | ${comment} site ${loc}; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/ECP5/095-copy_pllconfig/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbcopy 2 | import pytrellis 3 | 4 | 5 | def main(): 6 | pytrellis.load_database("../../../database") 7 | copy_rules = { 8 | "PLL1_LR": ["BANKREF4"] 9 | } 10 | for src, dest_tiles in sorted(copy_rules.items()): 11 | for dest in dest_tiles: 12 | dbcopy.dbcopy("ECP5", "LFE5U-25F", src, dest, copy_conns=True, copy_muxes=True, copy_enums=True, 13 | copy_words=True) 14 | 15 | if __name__ == "__main__": 16 | main() 17 | -------------------------------------------------------------------------------- /fuzzers/ECP5/100-usrmclk/cclk.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp I_N 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name CCLK; 15 | ${comment} program ; 16 | ${comment} primitive PAD I_N; 17 | ${comment} } 18 | ${comment} site CCLK; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/100-usrmclk/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/101-dtr/dtr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DTR_N 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DTR; 15 | ${comment} program "MODE:DTR " 16 | ${comment} "DTR:#ON "; 17 | ${comment} } 18 | ${comment} site DTR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/101-dtr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/102-oscg/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/102-oscg/osc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp OSC 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name OSC; 15 | ${comment} program "MODE:OSCG " 16 | ${comment} "OSCG:::DIV=${div}"; 17 | ${comment} } 18 | ${comment} site OSC; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/103-gsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/103-gsr/gsr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp GSR 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name GSR; 15 | ${comment} program "GSRMODE:${gsrmode} " 16 | ${comment} "SYNCMODE:${syncmode}"; 17 | ${comment} } 18 | ${comment} site GSR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/104-jtagg/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/104-jtagg/jtag.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp JTAG 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name JTAG; 15 | ${comment} program "MODE:JTAGG " 16 | ${comment} "JTAGG:::ER1=${er1},ER2=${er2}"; 17 | ${comment} } 18 | ${comment} site JTAG; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/105-sedga/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/112-dcu_config/dcuconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00g; 7 | device LFE5UM5G-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | ${comment} comp DCU 13 | ${comment} { 14 | ${comment} logical { 15 | ${comment} cellmodel-name DCU; 16 | ${comment} program "MODE:DCUA " 17 | ${comment} "DCUA:::${settings}"; 18 | ${comment} } 19 | ${comment} site DCU0; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/ECP5/112-dcu_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00g; 7 | device LFE5UM5G-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/ECP5/114-extrefb/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00g; 7 | device LFE5UM5G-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/114-extrefb/extref.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00g; 7 | device LFE5UM5G-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp EXTREF 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name EXTREF; 15 | ${comment} program "MODE:EXTREFB " 16 | ${comment} "EXTREFB${program}"; 17 | ${comment} } 18 | ${comment} site EXTREF0; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/117-pcsclkdiv/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00g; 7 | device LFE5UM5G-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/120-clkdiv/clkdiv.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp CDIV 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name CLKDIV; 15 | ${comment} program "MODE:CLKDIVF " 16 | ${comment} "CLKDIVF:::DIV=${div},GSR=${gsr}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/120-clkdiv/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/122-eclksync/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCB " 16 | ${comment} "ECLKSYNCB:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/122-eclksync/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/126-eclkbridgecs/eclkbridge.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKBRIDGECS; 15 | ${comment} program "MODE:ECLKBRIDGECS " 16 | ${comment} "ECLKBRIDGECS:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/126-eclkbridgecs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/130-dqsbuf/dqsbuf.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DQS0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DQS; 15 | ${comment} program "MODE:DQSBUFM " 16 | ${comment} "DQSBUFM:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/130-dqsbuf/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/132-dlldel/dlldel.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DLLDEL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DLLDEL; 15 | ${comment} program "MODE:DLLDELD " 16 | ${comment} "DLLDELD:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/132-dlldel/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/133-ddrdll/ddrdll.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DDRDLL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DDRDLL; 15 | ${comment} program "MODE:DDRDLLA " 16 | ${comment} "DDRDLLA:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/133-ddrdll/ddrdll_25k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | ${comment} comp DDRDLL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DDRDLL; 15 | ${comment} program "MODE:DDRDLLA " 16 | ${comment} "DDRDLLA:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/ECP5/133-ddrdll/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/133-ddrdll/empty_25k.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-25F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/140-sysconfig/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/140-sysconfig/empty.prf: -------------------------------------------------------------------------------- 1 | SYSCONFIG ${sysconfig}; -------------------------------------------------------------------------------- /fuzzers/ECP5/142-bitargs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/143-bankref8/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture sa5p00; 7 | device LFE5U-45F; 8 | package CABGA381; 9 | performance "8"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/ECP5/143-bankref8/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE=${vcc} ; 2 | -------------------------------------------------------------------------------- /fuzzers/ECP5/900-db_fixup/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbfixup 2 | import pytrellis 3 | 4 | device = "LFE5UM5G-45F" 5 | 6 | 7 | def main(): 8 | pytrellis.load_database("../../../database") 9 | chip = pytrellis.Chip("LFE5UM5G-45F") 10 | tiletypes = set() 11 | for tile in chip.get_all_tiles(): 12 | tiletypes.add(tile.info.type) 13 | 14 | for tiletype in sorted(tiletypes): 15 | dbfixup.dbfixup("ECP5", device, tiletype) 16 | 17 | 18 | if __name__ == "__main__": 19 | main() 20 | -------------------------------------------------------------------------------- /fuzzers/README.md: -------------------------------------------------------------------------------- 1 | ### Fuzzers 2 | 3 | Fuzzers are the scripts which generate the large number of bitstream. 4 | 5 | They are called "fuzzers" because they follow an approach similar to the 6 | [idea of software testing through fuzzing](https://en.wikipedia.org/wiki/Fuzzing). 7 | -------------------------------------------------------------------------------- /fuzzers/machxo2/003-lut_init/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/003-lut_init/lut.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:LOGIC " 18 | "K${k}::H${k}=${lut_func} " 19 | "F${k}:F "; 20 | primitive K${k} i3_4_lut; 21 | } 22 | site R10C11${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/machxo2/005-reg_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/007-plc2_cemux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/008-plc2_clkmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/009-plc2_lsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/010-plc2_modes/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/010-plc2_modes/modes.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:${mode} "; 18 | primitive REG0 q_6; 19 | } 20 | site R10C11${slice}; 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /fuzzers/machxo2/011-ccu2_inject/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/014-plc2_wremux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/021-glb-entry/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/021-glb-entry/7000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/023-glb-dcc/1200/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/023-glb-dcc/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/023-glb-dcc/7000/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/023-glb-dcc/7000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/025-glb-dcm/1200/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/025-glb-dcm/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/025-glb-dcm/7000/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/025-glb-dcm/7000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/035-copy-cib_ebr0/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbcopy 2 | import pytrellis 3 | import nets 4 | 5 | # Based on prior fuzzing conjecture that CIB_EBR 6 | # 0,1,2, and DUMMY have the same layout. 7 | 8 | shared_tiles = ["CIB_EBR1", "CIB_EBR2", "CIB_EBR_DUMMY"] 9 | 10 | def main(): 11 | pytrellis.load_database("../../../database") 12 | 13 | for dest in shared_tiles: 14 | dbcopy.dbcopy("MachXO2", "LCMXO2-1200HC", "CIB_EBR0", dest) 15 | 16 | 17 | if __name__ == "__main__": 18 | main() 19 | -------------------------------------------------------------------------------- /fuzzers/machxo2/041-ebr_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/042-ebr_mux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/051-pio_attrs/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/051-pio_attrs/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/051-pio_attrs/empty_4000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-4000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/051-pio_attrs/empty_7000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/051-pio_attrs/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE = ${cfg_vio}; 2 | -------------------------------------------------------------------------------- /fuzzers/machxo2/052-pio_fixup/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbfixup 2 | import pytrellis 3 | 4 | def main(): 5 | pytrellis.load_database("../../../database") 6 | dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_L0", (29, 11)) 7 | 8 | dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_R0", (29, 59), (0, 48)) 9 | 10 | dbfixup.remove_enum_bits("MachXO2", "LCMXO2-2000HC", "ULC3PIC", (29, 11)) 11 | 12 | dbfixup.remove_enum_bits("MachXO2", "LCMXO2-2000HC", "URC1PIC", (29, 59), (0, 48)) 13 | if __name__ == "__main__": 14 | main() 15 | -------------------------------------------------------------------------------- /fuzzers/machxo2/054-pgmux/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/054-pgmux/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/054-pgmux/empty_7000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/057-bankref/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/060-iologic_modes/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/060-iologic_modes/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/060-iologic_modes/iologic_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp io 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${side}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site "${loc}"; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo2/060-iologic_modes/iologic_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp io 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${side}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site "${loc}"; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo2/061-basic_ddr/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/061-basic_ddr/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/063-oddrxn/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/063-oddrxn/iologic_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name TIOLOGIC; 17 | program "MODE:ODDR4 " 18 | "${mode}"; 19 | } 20 | site "${loc}"; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/064-iddrxn/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/064-iddrxn/iologic_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name BIOLOGIC; 17 | program "MODE:IDDR4 " 18 | "${mode}"; 19 | } 20 | site "${loc}"; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/066-iodelay/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/066-iodelay/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/067-ioreg/empty_1200.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/067-ioreg/empty_2000.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/091-pll_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/091-pll_config/pllconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp PLL 13 | ${comment} { 14 | ${comment} logical { 15 | ${comment} cellmodel-name PLL; 16 | ${comment} program "MODE:EHXPLLJ " 17 | ${comment} "EHXPLLJ:::${settings}"; 18 | ${comment} } 19 | ${comment} site ${loc}; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo2/102-oscg/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package QFN32; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/103-gsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/103-gsr/gsr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp GSR 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name GSR; 15 | ${comment} program "GSRMODE:${gsrmode} " 16 | ${comment} "SYNCMODE:${syncmode}"; 17 | ${comment} } 18 | ${comment} site GSR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/104-jtagf/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/104-jtagf/jtag.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | ${comment} comp JTAG 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name JTAG; 15 | ${comment} program "MODE:JTAGF " 16 | ${comment} "JTAGF:::ER1=${er1},ER2=${er2}"; 17 | ${comment} } 18 | ${comment} site JTAG; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/105-sedfa/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/105-sedfa/sed_mode.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp SED 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name SED; 15 | ${comment} program "MODE:${mode} " 16 | ${comment} "${mode}:::"; 17 | ${comment} } 18 | ${comment} site SED; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/machxo2/106-tsall/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/106-tsall/tsall.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp ts 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name TSALL; 15 | ${comment} program "MODE:TSALL " 16 | ${comment} "TSALL:${tsall}"; 17 | ${comment} } 18 | ${comment} site TSALL; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/107-start/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/107-start/start.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp start 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name START; 15 | ${comment} program "MODE:START " 16 | ${comment} "START:${start}"; 17 | ${comment} } 18 | ${comment} site START; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/108-pcntr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/108-pcntr/pcntr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp pcntr 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PCNTR; 15 | ${comment} program "MODE:PCNTR " 16 | ${comment} "PCNTR:::${program}"; 17 | ${comment} } 18 | ${comment} site PCNTR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/109-efb/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo2/120-clkdiv/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/120-clkdiv/2000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/122-eclksync/1200/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCA " 16 | ${comment} "ECLKSYNCA:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/122-eclksync/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/122-eclksync/2000/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCA " 16 | ${comment} "ECLKSYNCA:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/122-eclksync/2000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/126-eclkbridgecs/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/126-eclkbridgecs/7000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/1200/dlldel.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp DLLDEL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DLLDEL; 15 | ${comment} program "MODE:DLLDELC " 16 | ${comment} "DLLDELC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/1200/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/2000/dlldel.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | ${comment} comp DLLDEL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DLLDEL; 15 | ${comment} program "MODE:DLLDELC " 16 | ${comment} "DLLDELC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/2000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-2000HC; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/4000/dlldel.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-4000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | ${comment} comp DLLDEL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DLLDEL; 15 | ${comment} program "MODE:DLLDELC " 16 | ${comment} "DLLDELC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/4000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-4000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/7000/dlldel.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | ${comment} comp DLLDEL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DLLDEL; 15 | ${comment} program "MODE:DLLDELC " 16 | ${comment} "DLLDELC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/132-dlldel/7000/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-7000HC; 8 | package FPBGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/133-dqsdll/dqsdll.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | ${comment} comp DDRDLL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DQSDLL; 15 | ${comment} program "MODE:DQSDLLC " 16 | ${comment} "DQSDLLC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo2/133-dqsdll/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/140-sysconfig/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo2/140-sysconfig/empty.prf: -------------------------------------------------------------------------------- 1 | ${sysconfig} 2 | -------------------------------------------------------------------------------- /fuzzers/machxo2/142-bitargs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo2c00; 7 | device LCMXO2-1200HC; 8 | package TQFP144; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/003-lut_init/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/003-lut_init/lut.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:LOGIC " 18 | "K${k}::H${k}=${lut_func} " 19 | "F${k}:F "; 20 | primitive K${k} i3_4_lut; 21 | } 22 | site R10C11${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/machxo3/005-reg_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/007-plc2_cemux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/008-plc2_clkmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/009-plc2_lsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/010-plc2_modes/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/010-plc2_modes/modes.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:${mode} "; 18 | primitive REG0 q_6; 19 | } 20 | site R10C11${slice}; 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /fuzzers/machxo3/011-ccu2_inject/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/014-plc2_wremux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/021-glb-entry/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/021-glb-entry/6900/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/021-glb-entry/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/1300/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/6900/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/6900/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/9400/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/023-glb-dcc/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/1300/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/6900/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/6900/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/9400/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/025-glb-dcm/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/041-ebr_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/042-ebr_mux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/empty_4300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-4300C; 8 | package CABGA324; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/empty_6900.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/051-pio_attrs/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE = ${cfg_vio}; 2 | -------------------------------------------------------------------------------- /fuzzers/machxo3/052-pio_fixup/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbfixup 2 | import pytrellis 3 | 4 | def main(): 5 | pytrellis.load_database("../../../database") 6 | dbfixup.remove_enum_bits("MachXO3", "LCMXO3LF-1300E", "PIC_L0", (29, 11)) 7 | 8 | dbfixup.remove_enum_bits("MachXO3", "LCMXO3LF-1300E", "PIC_R0", (29, 59), (0, 48)) 9 | 10 | dbfixup.remove_enum_bits("MachXO3", "LCMXO3LF-2100C", "ULC3PIC", (29, 11)) 11 | 12 | dbfixup.remove_enum_bits("MachXO3", "LCMXO3LF-2100C", "URC1PIC", (29, 59), (0, 48)) 13 | if __name__ == "__main__": 14 | main() 15 | -------------------------------------------------------------------------------- /fuzzers/machxo3/054-pgmux/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/054-pgmux/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/054-pgmux/empty_6900.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/057-bankref/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/057-bankref/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/057-bankref/empty_4300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-4300C; 8 | package CABGA324; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/057-bankref/empty_6900.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/057-bankref/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/060-iologic_modes/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/060-iologic_modes/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/060-iologic_modes/iologic_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp io 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${side}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site ${loc}; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo3/060-iologic_modes/iologic_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | ${comment} comp io 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${side}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site ${loc}; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo3/061-basic_ddr/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/061-basic_ddr/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/063-oddrxn/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/063-oddrxn/iologic_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name TIOLOGIC; 17 | program "MODE:ODDR4 " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/064-iddrxn/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/064-iddrxn/iologic_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name BIOLOGIC; 17 | program "MODE:IDDR4 " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/066-iodelay/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/066-iodelay/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/067-ioreg/empty_1300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/067-ioreg/empty_2100.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/091-pll_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo3/091-pll_config/pllconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | ${comment} comp PLL 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PLL; 15 | ${comment} program "MODE:EHXPLLJ " 16 | ${comment} "EHXPLLJ:::${settings}"; 17 | ${comment} } 18 | ${comment} site ${loc}; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/machxo3/102-oscg/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo3/103-gsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/103-gsr/gsr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp GSR 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name GSR; 15 | ${comment} program "GSRMODE:${gsrmode} " 16 | ${comment} "SYNCMODE:${syncmode}"; 17 | ${comment} } 18 | ${comment} site GSR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/104-jtagf/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/104-jtagf/jtag.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | ${comment} comp JTAG 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name JTAG; 15 | ${comment} program "MODE:JTAGF " 16 | ${comment} "JTAGF:::ER1=${er1},ER2=${er2}"; 17 | ${comment} } 18 | ${comment} site JTAG; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/105-sedfa/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/105-sedfa/sed_mode.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp SED 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name SED; 15 | ${comment} program "MODE:${mode} " 16 | ${comment} "${mode}:::"; 17 | ${comment} } 18 | ${comment} site SED; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/machxo3/106-tsall/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/106-tsall/tsall.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp ts 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name TSALL; 15 | ${comment} program "MODE:TSALL " 16 | ${comment} "TSALL:${tsall}"; 17 | ${comment} } 18 | ${comment} site TSALL; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/107-start/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/107-start/start.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp start 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name START; 15 | ${comment} program "MODE:START " 16 | ${comment} "START:${start}"; 17 | ${comment} } 18 | ${comment} site START; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/108-pcntr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/108-pcntr/pcntr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp pcntr 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PCNTR; 15 | ${comment} program "MODE:PCNTR " 16 | ${comment} "PCNTR:::${program}"; 17 | ${comment} } 18 | ${comment} site PCNTR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/109-efb/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/120-clkdiv/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/120-clkdiv/2100/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/122-eclksync/1300/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCA " 16 | ${comment} "ECLKSYNCA:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/122-eclksync/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/122-eclksync/2100/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCA " 16 | ${comment} "ECLKSYNCA:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/122-eclksync/2100/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/126-eclkbridgecs/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/126-eclkbridgecs/6900/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/126-eclkbridgecs/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/132-dlldel/1300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/132-dlldel/2100/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-2100C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/132-dlldel/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-4300C; 8 | package CABGA256; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/132-dlldel/6900/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-6900C; 8 | package CABGA400; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/132-dlldel/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-9400C; 8 | package CABGA484; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/133-dqsdll/dqsdll.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | ${comment} comp DDRDLL0 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name DQSDLL; 15 | ${comment} program "MODE:DQSDLLC " 16 | ${comment} "DQSDLLC:::${program}"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3/133-dqsdll/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package WLCSP36; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/140-sysconfig/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3/140-sysconfig/empty.prf: -------------------------------------------------------------------------------- 1 | ${sysconfig} 2 | -------------------------------------------------------------------------------- /fuzzers/machxo3/142-bitargs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/003-lut_init/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/003-lut_init/lut.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:LOGIC " 18 | "K${k}::H${k}=${lut_func} " 19 | "F${k}:F "; 20 | primitive K${k} i3_4_lut; 21 | } 22 | site R10C11${slice}; 23 | } 24 | 25 | } 26 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/005-reg_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/007-plc2_cemux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/008-plc2_clkmux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/009-plc2_lsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/010-plc2_modes/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/010-plc2_modes/modes.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | comp SLICE_0 13 | { 14 | logical 15 | { 16 | cellmodel-name SLICE; 17 | program "MODE:${mode} "; 18 | primitive REG0 q_6; 19 | } 20 | site R10C11${slice}; 21 | } 22 | 23 | } 24 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/011-ccu2_inject/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/014-plc2_wremux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/021-glb-entry/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/021-glb-entry/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/023-glb-dcc/4300/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/023-glb-dcc/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/023-glb-dcc/9400/dcc.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCC; 17 | ${comment} program "MODE:DCCA " 18 | ${comment} "DCCA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/023-glb-dcc/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/025-glb-dcm/4300/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/025-glb-dcm/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/025-glb-dcm/9400/dcm.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | ${comment} comp I1 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name DCM; 17 | ${comment} program "MODE:DCMA " 18 | ${comment} "DCMA:#ON "; 19 | ${comment} } 20 | ${comment} site ${site}; 21 | ${comment} } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/025-glb-dcm/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/041-ebr_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/042-ebr_mux/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/051-pio_attrs/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA484; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/051-pio_attrs/pio.lpf: -------------------------------------------------------------------------------- 1 | SYSCONFIG CONFIG_IOVOLTAGE = ${cfg_vio}; 2 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/052-pio_fixup/fuzzer.py: -------------------------------------------------------------------------------- 1 | import dbfixup 2 | import pytrellis 3 | 4 | def main(): 5 | pytrellis.load_database("../../../database") 6 | dbfixup.remove_enum_bits("MachXO3D", "LCMXO3D-9400HC", "PIC_L0", (29, 11)) 7 | dbfixup.remove_enum_bits("MachXO3D", "LCMXO3D-9400HC", "PIC_L0_I3C", (29, 11)) 8 | 9 | dbfixup.remove_enum_bits("MachXO3D", "LCMXO3D-9400HC", "PIC_R1", (29, 59), (0, 48)) 10 | 11 | if __name__ == "__main__": 12 | main() 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/054-pgmux/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA484; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/057-bankref/empty_4300.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/057-bankref/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/060-iologic_modes/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/060-iologic_modes/iologic_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | ${comment} comp io 13 | ${comment} { 14 | ${comment} logical 15 | ${comment} { 16 | ${comment} cellmodel-name ${side}IOLOGIC; 17 | ${comment} ${program}; 18 | ${comment} } 19 | ${comment} site ${loc}; 20 | ${comment} } 21 | } 22 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/061-basic_ddr/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/063-oddrxn/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/063-oddrxn/iologic_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name TIOLOGIC; 17 | program "MODE:ODDR4 " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/064-iddrxn/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/064-iddrxn/iologic_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | comp Q_MGIOL 13 | { 14 | logical 15 | { 16 | cellmodel-name BIOLOGIC; 17 | program "MODE:IDDR4 " 18 | "${mode}"; 19 | } 20 | site ${loc}; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/066-iodelay/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/067-ioreg/empty_9400.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/091-pll_config/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/091-pll_config/pllconfig.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp PLL 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PLL; 15 | ${comment} program "MODE:EHXPLLJ " 16 | ${comment} "EHXPLLJ:::${settings}"; 17 | ${comment} } 18 | ${comment} site ${loc}; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/102-oscj/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/103-gsr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/103-gsr/gsr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp GSR 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name GSR; 15 | ${comment} program "GSRMODE:${gsrmode} " 16 | ${comment} "SYNCMODE:${syncmode}"; 17 | ${comment} } 18 | ${comment} site GSR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/104-jtagf/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/104-jtagf/jtag.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp JTAG 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name JTAG; 15 | ${comment} program "MODE:JTAGF " 16 | ${comment} "JTAGF:::ER1=${er1},ER2=${er2}"; 17 | ${comment} } 18 | ${comment} site JTAG; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/105-sedfa/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/105-sedfa/sed_mode.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp SED 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name SED; 15 | ${comment} program "MODE:${mode} " 16 | ${comment} "${mode}:::"; 17 | ${comment} } 18 | ${comment} site SED; 19 | ${comment} } 20 | } 21 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/106-tsall/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/106-tsall/tsall.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp ts 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name TSALL; 15 | ${comment} program "MODE:TSALL " 16 | ${comment} "TSALL:${tsall}"; 17 | ${comment} } 18 | ${comment} site TSALL; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/107-start/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/107-start/start.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp start 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name START; 15 | ${comment} program "MODE:START " 16 | ${comment} "START:${start}"; 17 | ${comment} } 18 | ${comment} site START; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/108-pcntr/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/108-pcntr/pcntr.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp pcntr 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name PCNTR; 15 | ${comment} program "MODE:PCNTR " 16 | ${comment} "PCNTR:::${program}"; 17 | ${comment} } 18 | ${comment} site PCNTR; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/120-clkdiv/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/122-eclksync/eclksync.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | ${comment} comp ES 12 | ${comment} { 13 | ${comment} logical { 14 | ${comment} cellmodel-name ECLKSYNC; 15 | ${comment} program "MODE:ECLKSYNCA " 16 | ${comment} "ECLKSYNCA:#ON"; 17 | ${comment} } 18 | ${comment} site ${site}; 19 | ${comment} } 20 | 21 | 22 | } 23 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/122-eclksync/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/126-eclkbridgecs/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/126-eclkbridgecs/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/132-dlldel/4300/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-4300HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/132-dlldel/9400/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/133-dqsdll/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/140-sysconfig/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture xo3c00f; 7 | device LCMXO3LF-1300E; 8 | package CSFBGA121; 9 | performance "6"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/140-sysconfig/empty.prf: -------------------------------------------------------------------------------- 1 | ${sysconfig} 2 | -------------------------------------------------------------------------------- /fuzzers/machxo3d/142-bitargs/empty.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | design top 3 | { 4 | device 5 | { 6 | architecture se5c00; 7 | device LCMXO3D-9400HC; 8 | package CABGA256; 9 | performance "5"; 10 | } 11 | 12 | } 13 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.gitattributes: -------------------------------------------------------------------------------- 1 | docs/*.svg binary 2 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/CODEOWNERS: -------------------------------------------------------------------------------- 1 | *.cmake @henryiii 2 | CMakeLists.txt @henryiii 3 | *.yml @henryiii 4 | *.yaml @henryiii 5 | /tools/ @henryiii 6 | /pybind11/ @henryiii 7 | noxfile.py @henryiii 8 | .clang-format @henryiii 9 | .clang-tidy @henryiii 10 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/ISSUE_TEMPLATE/config.yml: -------------------------------------------------------------------------------- 1 | blank_issues_enabled: false 2 | contact_links: 3 | - name: Ask a question 4 | url: https://github.com/pybind/pybind11/discussions/new 5 | about: Please ask and answer questions here, or propose new ideas. 6 | - name: Gitter room 7 | url: https://gitter.im/pybind/Lobby 8 | about: A room for discussing pybind11 with an active community 9 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | # Maintain dependencies for GitHub Actions 4 | - package-ecosystem: "github-actions" 5 | directory: "/" 6 | schedule: 7 | interval: "daily" 8 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/labeler.yml: -------------------------------------------------------------------------------- 1 | docs: 2 | - any: 3 | - 'docs/**/*.rst' 4 | - '!docs/changelog.rst' 5 | - '!docs/upgrade.rst' 6 | 7 | ci: 8 | - '.github/workflows/*.yml' 9 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/labeler_merged.yml: -------------------------------------------------------------------------------- 1 | needs changelog: 2 | - all: 3 | - '!docs/changelog.rst' 4 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.github/workflows/labeler.yml: -------------------------------------------------------------------------------- 1 | name: Labeler 2 | on: 3 | pull_request_target: 4 | types: [closed] 5 | 6 | jobs: 7 | label: 8 | name: Labeler 9 | runs-on: ubuntu-latest 10 | steps: 11 | 12 | - uses: actions/labeler@main 13 | if: github.event.pull_request.merged == true 14 | with: 15 | repo-token: ${{ secrets.GITHUB_TOKEN }} 16 | configuration-path: .github/labeler_merged.yml 17 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/.readthedocs.yml: -------------------------------------------------------------------------------- 1 | python: 2 | version: 3 3 | requirements_file: docs/requirements.txt 4 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/MANIFEST.in: -------------------------------------------------------------------------------- 1 | recursive-include pybind11/include/pybind11 *.h 2 | recursive-include pybind11 *.py 3 | recursive-include pybind11 py.typed 4 | include pybind11/share/cmake/pybind11/*.cmake 5 | include LICENSE README.rst pyproject.toml setup.py setup.cfg 6 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/_static/css/custom.css: -------------------------------------------------------------------------------- 1 | .highlight .go { 2 | color: #707070; 3 | } 4 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/_static/theme_overrides.css: -------------------------------------------------------------------------------- 1 | .wy-table-responsive table td, 2 | .wy-table-responsive table th { 3 | white-space: initial !important; 4 | } 5 | .rst-content table.docutils td { 6 | vertical-align: top !important; 7 | } 8 | div[class^='highlight'] pre { 9 | white-space: pre; 10 | white-space: pre-wrap; 11 | } 12 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/advanced/pycpp/index.rst: -------------------------------------------------------------------------------- 1 | Python C++ interface 2 | #################### 3 | 4 | pybind11 exposes Python types and functions using thin C++ wrappers, which 5 | makes it possible to conveniently call Python code from C++ without resorting 6 | to Python's C API. 7 | 8 | .. toctree:: 9 | :maxdepth: 2 10 | 11 | object 12 | numpy 13 | utilities 14 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/cmake/index.rst: -------------------------------------------------------------------------------- 1 | CMake helpers 2 | ------------- 3 | 4 | Pybind11 can be used with ``add_subdirectory(extern/pybind11)``, or from an 5 | install with ``find_package(pybind11 CONFIG)``. The interface provided in 6 | either case is functionally identical. 7 | 8 | .. cmake-module:: ../../tools/pybind11Config.cmake.in 9 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/pybind11-logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/docs/pybind11-logo.png -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/pybind11_vs_boost_python1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/docs/pybind11_vs_boost_python1.png -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/pybind11_vs_boost_python2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/docs/pybind11_vs_boost_python2.png -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/docs/requirements.txt: -------------------------------------------------------------------------------- 1 | breathe==4.34.0 2 | furo==2022.6.21 3 | sphinx==5.0.2 4 | sphinx-copybutton==0.5.0 5 | sphinxcontrib-moderncmakedomain==3.21.4 6 | sphinxcontrib-svg2pdfconverter==1.2.0 7 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/include/pybind11/common.h: -------------------------------------------------------------------------------- 1 | #include "detail/common.h" 2 | #warning "Including 'common.h' is deprecated. It will be removed in v3.0. Use 'pybind11.h'." 3 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/pybind11/__init__.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | if sys.version_info < (3, 6): 4 | msg = "pybind11 does not support Python < 3.6. 2.9 was the last release supporting Python 2.7 and 3.5." 5 | raise ImportError(msg) 6 | 7 | 8 | from ._version import __version__, version_info 9 | from .commands import get_cmake_dir, get_include, get_pkgconfig_dir 10 | 11 | __all__ = ( 12 | "version_info", 13 | "__version__", 14 | "get_include", 15 | "get_cmake_dir", 16 | "get_pkgconfig_dir", 17 | ) 18 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/pybind11/_version.py: -------------------------------------------------------------------------------- 1 | from typing import Union 2 | 3 | 4 | def _to_int(s: str) -> Union[int, str]: 5 | try: 6 | return int(s) 7 | except ValueError: 8 | return s 9 | 10 | 11 | __version__ = "2.11.0.dev1" 12 | version_info = tuple(_to_int(s) for s in __version__.split(".")) 13 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/pybind11/_version.pyi: -------------------------------------------------------------------------------- 1 | from typing import Union, Tuple 2 | 3 | def _to_int(s: str) -> Union[int, str]: ... 4 | 5 | __version__: str 6 | version_info: Tuple[Union[int, str], ...] 7 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/pybind11/py.typed: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/pybind11/py.typed -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/extra_python_package/pytest.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/tests/extra_python_package/pytest.ini -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/extra_setuptools/pytest.ini: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/libtrellis/3rdparty/pybind11/tests/extra_setuptools/pytest.ini -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_cmake_build/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | namespace py = pybind11; 3 | 4 | PYBIND11_MODULE(test_cmake_build, m) { 5 | m.def("add", [](int i, int j) { return i + j; }); 6 | } 7 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_cmake_build/test.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | import test_cmake_build 4 | 5 | assert isinstance(__file__, str) # Test this is properly set 6 | 7 | assert test_cmake_build.add(1, 2) == 3 8 | print(f"{sys.argv[1]} imports, runs, and adds: 1 + 2 = 3") 9 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_embed/test_interpreter.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | from widget_module import Widget 4 | 5 | 6 | class DerivedWidget(Widget): 7 | def __init__(self, message): 8 | super().__init__(message) 9 | 10 | def the_answer(self): 11 | return 42 12 | 13 | def argv0(self): 14 | return sys.argv[0] 15 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_embed/test_trampoline.py: -------------------------------------------------------------------------------- 1 | import trampoline_module 2 | 3 | 4 | def func(): 5 | class Test(trampoline_module.test_override_cache_helper): 6 | def func(self): 7 | return 42 8 | 9 | return Test() 10 | 11 | 12 | def func2(): 13 | class Test(trampoline_module.test_override_cache_helper): 14 | pass 15 | 16 | return Test() 17 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_eval_call.py: -------------------------------------------------------------------------------- 1 | # This file is called from 'test_eval.py' 2 | 3 | if "call_test2" in locals(): 4 | call_test2(y) # noqa: F821 undefined name 5 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_exceptions.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #include "pybind11_tests.h" 3 | 4 | #include 5 | 6 | // shared exceptions for cross_module_tests 7 | 8 | class PYBIND11_EXPORT_EXCEPTION shared_exception : public pybind11::builtin_exception { 9 | public: 10 | using builtin_exception::builtin_exception; 11 | explicit shared_exception() : shared_exception("") {} 12 | void set_error() const override { PyErr_SetString(PyExc_RuntimeError, what()); } 13 | }; 14 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tests/test_union.py: -------------------------------------------------------------------------------- 1 | from pybind11_tests import union_ as m 2 | 3 | 4 | def test_union(): 5 | instance = m.TestUnion() 6 | 7 | instance.as_uint = 10 8 | assert instance.as_int == 10 9 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tools/pybind11.pc.in: -------------------------------------------------------------------------------- 1 | prefix=@prefix_for_pc_file@ 2 | includedir=@includedir_for_pc_file@ 3 | 4 | Name: @PROJECT_NAME@ 5 | Description: Seamless operability between C++11 and Python 6 | Version: @PROJECT_VERSION@ 7 | Cflags: -I${includedir} 8 | -------------------------------------------------------------------------------- /libtrellis/3rdparty/pybind11/tools/pyproject.toml: -------------------------------------------------------------------------------- 1 | [build-system] 2 | requires = ["setuptools>=42", "wheel"] 3 | build-backend = "setuptools.build_meta" 4 | -------------------------------------------------------------------------------- /libtrellis/README.md: -------------------------------------------------------------------------------- 1 | # libtrellis - Utilities for Manipulating Lattice FPGA Bitstreams -------------------------------------------------------------------------------- /libtrellis/examples/.gitignore: -------------------------------------------------------------------------------- 1 | *.bit 2 | *.ncl 3 | *.dump 4 | -------------------------------------------------------------------------------- /libtrellis/examples/ddgraph.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | """ 3 | Testing the routing graph generator 4 | """ 5 | import pytrellis 6 | import sys 7 | 8 | pytrellis.load_database("../../database") 9 | chip = pytrellis.Chip("LFE5U-25F") 10 | dd = pytrellis.make_dedup_chipdb(chip) 11 | print(len(dd.locationTypes)) 12 | -------------------------------------------------------------------------------- /libtrellis/examples/logic_tile_config.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | """ 3 | This simple example uses PyTrellis to dump config of all logic tiles as text 4 | """ 5 | import pytrellis 6 | import sys 7 | 8 | pytrellis.load_database("../../database") 9 | bs = pytrellis.Bitstream.read_bit(sys.argv[1]) 10 | chip = bs.deserialise_chip() 11 | for tile in chip.get_tiles_by_type("PLC2"): 12 | cfg = tile.dump_config() 13 | if len(cfg.strip()) > 0: 14 | print(".tile {}".format(tile.info.name)) 15 | print(cfg) 16 | print() 17 | -------------------------------------------------------------------------------- /libtrellis/examples/unpack_repack.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | """ 3 | This simple example uses PyTrellis to unpack and pack a bitstream 4 | """ 5 | import pytrellis 6 | 7 | pytrellis.load_database("../../../prjtrellis-db") 8 | bs = pytrellis.Bitstream.read_bit("../../minitests/lut/lut.bit") 9 | chip = bs.deserialise_chip() 10 | repack = pytrellis.Bitstream.serialise_chip(chip) 11 | repack.write_bit("repack.bit") 12 | -------------------------------------------------------------------------------- /libtrellis/src/Util.cpp: -------------------------------------------------------------------------------- 1 | #include "Util.hpp" 2 | 3 | namespace Trellis { 4 | VerbosityLevel verbosity = VerbosityLevel::DEBUG; 5 | } 6 | -------------------------------------------------------------------------------- /libtrellis/tools/version.cpp.in: -------------------------------------------------------------------------------- 1 | #include "version.hpp" 2 | const std::string git_describe_str = "@CURRENT_GIT_VERSION@"; 3 | -------------------------------------------------------------------------------- /libtrellis/tools/version.hpp: -------------------------------------------------------------------------------- 1 | #ifndef VERSION_H 2 | #define VERSION_H 3 | #include 4 | extern const std::string git_describe_str; 5 | #endif 6 | -------------------------------------------------------------------------------- /minitests/.gitignore: -------------------------------------------------------------------------------- 1 | *.tmp/ 2 | *.bit 3 | *.dump 4 | *.incd 5 | *_out.ncl 6 | *.ncd 7 | *.out 8 | *.twr 9 | *.config 10 | *.sdf -------------------------------------------------------------------------------- /minitests/ECP5/dsp/mult.v: -------------------------------------------------------------------------------- 1 | module top(input [17:0] a, input [17:0] b, input [35:0] c, output [35:0] q); 2 | 3 | (* syn_multstyle="block_mult" *) 4 | wire [35:0] product = a * b; 5 | assign q = product + c; 6 | 7 | endmodule 8 | 9 | -------------------------------------------------------------------------------- /minitests/ECP5/dsp/mult1n.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | // designname: dut 3 | // Creation time stamp: 02/09/19 17:09:09 4 | design dut 5 | { 6 | device 7 | { 8 | architecture sa5p00; 9 | device LFE5U-25F; 10 | package CABGA381; 11 | performance "8"; 12 | } 13 | 14 | comp dsp 15 | { 16 | 17 | logical 18 | { 19 | cellmodel-name MULT18; 20 | program "MODE:MULT18X18D " 21 | "MULT18X18D:::"; 22 | } 23 | site MULT18_R13C5; 24 | } 25 | 26 | } 27 | -------------------------------------------------------------------------------- /minitests/ECP5/dsp/preadd.v: -------------------------------------------------------------------------------- 1 | module top(input [8:0] a, input [8:0] b, input [8:0] c, output [17:0] q); 2 | wire [8:0] add = a + b; 3 | (* syn_multstyle = "block_mult" *) 4 | wire [17:0] res = add * c; 5 | assign q = res; 6 | endmodule 7 | 8 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/iddr.v: -------------------------------------------------------------------------------- 1 | module iddr(input D, SCLK, RST, output Q0, Q1); 2 | IDDRX1F iddr_i(.D(D), .SCLK(SCLK), .RST(RST), .Q0(Q0), .Q1(Q1)); 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/iddr2.v: -------------------------------------------------------------------------------- 1 | module oddr7(input D, input ECLK, RST, output [3:0] Q); 2 | wire SCLK; 3 | 4 | CLKDIVF #(.DIV("2.0")) cdiv_i (.CLKI(ECLK), .RST(RST), .ALIGNWD(1'b0), .CDIVX(SCLK)); 5 | 6 | IDDRX2F oddr_i(.Q0(Q[0]), .Q1(Q[1]), .Q2(Q[2]), .Q3(Q[3]), 7 | .ECLK(ECLK), .SCLK(SCLK), .RST(RST), 8 | .D(D)); 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/iddr7.v: -------------------------------------------------------------------------------- 1 | module oddr7(input D, input ALIGNWD, ECLK, RST, output [3:0] Q); 2 | wire SCLK; 3 | 4 | CLKDIVF #(.DIV("3.5")) cdiv_i (.CLKI(ECLK), .RST(RST), .ALIGNWD(1'b0), .CDIVX(SCLK)); 5 | 6 | IDDR71B oddr_i(.Q0(Q[0]), .Q1(Q[1]), .Q2(Q[2]), .Q3(Q[3]), 7 | .ECLK(ECLK), .SCLK(SCLK), .ALIGNWD(ALIGNWD), .RST(RST), 8 | .D(D)); 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/iddr_LSR.v: -------------------------------------------------------------------------------- 1 | module iddr(input [3:0] D, SCLK, RST, output [3:0] Q0, Q1); 2 | IDDRX1F iddr_i0(.D(D[0]), .SCLK(SCLK), .RST(RST), .Q0(Q0[0]), .Q1(Q1[0])); 3 | IDDRX1F iddr_i1(.D(D[1]), .SCLK(SCLK), .RST(!RST), .Q0(Q0[1]), .Q1(Q1[1])); 4 | IDDRX1F iddr_i2(.D(D[2]), .SCLK(SCLK), .RST(RST||Q0[0]), .Q0(Q0[2]), .Q1(Q1[2])); 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/iddr_inv.v: -------------------------------------------------------------------------------- 1 | module iddr(input D, SCLK, RST, output Q0, Q1); 2 | IDDRX1F iddr_i(.D(D), .SCLK(!SCLK), .RST(RST), .Q0(Q0), .Q1(Q1)); 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/idelay.v: -------------------------------------------------------------------------------- 1 | module idelay(input D, MOVE, LOADN, DIR, output Q, CFLAG); 2 | wire dly_out; 3 | DELAYF dly_f (.A(D), .MOVE(MOVE), .LOADN(LOADN), .DIRECTION(DIR), .Z(dly_out), .CFLAG(CFLAG)); 4 | assign Q = ~dly_out; 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/ireg.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, output q); 2 | IFS1P3IX ireg_i (.D(d), .SCLK(clk), .SP(1'b1), .CD(1'b0), 3 | .Q(q)); 4 | endmodule 5 | 6 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/ireg2.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, s, output q); 2 | IFS1P3JX ireg_i (.D(d), .SCLK(clk), .SP(1'b1), .PD(s), 3 | .Q(q)); 4 | endmodule 5 | 6 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/oddr.v: -------------------------------------------------------------------------------- 1 | module oddr(output Q, input SCLK, RST, D0, D1); 2 | ODDRX1F oddr_i(.Q(Q), .SCLK(SCLK), .RST(RST), .D0(D0), .D1(D1)); 3 | endmodule 4 | 5 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/oddr7.v: -------------------------------------------------------------------------------- 1 | module oddr7(input [6:0] D, input ECLK, RST, output Q); 2 | wire SCLK; 3 | 4 | CLKDIVF #(.DIV("3.5")) cdiv_i (.CLKI(ECLK), .RST(RST), .ALIGNWD(1'b0), .CDIVX(SCLK)); 5 | 6 | ODDR71B oddr_i(.D0(D[0]), .D1(D[1]), .D2(D[2]), .D3(D[3]), .D4(D[4]), .D5(D[5]), .D6(D[6]), 7 | .ECLK(ECLK), .SCLK(SCLK), .RST(RST), 8 | .Q(Q)); 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/oreg.v: -------------------------------------------------------------------------------- 1 | module top(input clk, ce, lsr, d, output q); 2 | OFS1P3IX oreg_i (.D(d), .SCLK(clk), .SP(ce), .CD(lsr), 3 | .Q(q)); 4 | endmodule 5 | 6 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/oshx2a.v: -------------------------------------------------------------------------------- 1 | module oshx(input [1:0] D, input ECLK, RST, output Q); 2 | wire SCLK; 3 | 4 | CLKDIVF #(.DIV("2.0")) cdiv_i (.CLKI(ECLK), .RST(RST), .ALIGNWD(1'b0), .CDIVX(SCLK)); 5 | 6 | OSHX2A OSHX2A_i(.D0(D[0]), .D1(D[1]), 7 | .ECLK(ECLK), .SCLK(SCLK), .RST(RST), 8 | .Q(Q)); 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/ECP5/iologic/toreg.v: -------------------------------------------------------------------------------- 1 | module top(input clk, ce, lsr, d, t, output p); 2 | wire tr, q; 3 | OFS1P3IX oreg_i (.D(d), .SCLK(clk), .SP(ce), .CD(lsr), .Q(q)); 4 | OFS1P3IX treg_i (.D(t), .SCLK(clk), .SP(ce), .CD(lsr), .Q(tr)); 5 | 6 | OBZ ob_i(.I(q), .T(tr), .O(p)); 7 | endmodule 8 | 9 | -------------------------------------------------------------------------------- /minitests/ECP5/potpourri/dtr.v: -------------------------------------------------------------------------------- 1 | module top(input start, output [7:0] dtr); 2 | 3 | DTR dtr_i( 4 | .STARTPULSE(start), 5 | .DTROUT7(dtr[7]), 6 | .DTROUT6(dtr[6]), 7 | .DTROUT5(dtr[5]), 8 | .DTROUT4(dtr[4]), 9 | .DTROUT3(dtr[3]), 10 | .DTROUT2(dtr[2]), 11 | .DTROUT1(dtr[1]), 12 | .DTROUT0(dtr[0]) 13 | ); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /minitests/ECP5/potpourri/jtagg.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input TCK, TMS, TDI, JTDO2, JTDO1, 3 | output TDO, JTDI, JTCK, JRTI2, JRTI1, 4 | output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 5 | ); 6 | JTAGG jtag_i(.TCK(TCK), .TMS(TMS), .TDI(TDI), .JTDO2(JTDO2), .JTDO1(JTDO2), 7 | .TDO(TDO), .JTDI(JTDI), .JTCK(JTCK), .JRTI2(JRTI2), .JRTI1(JRTI1), 8 | .JSHIFT(JSHIFT), .JUPDATE(JUPDATE), .JRSTN(JRSTN), .JCE2(JCE2), .JCE1(JCE1)); 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/ECP5/potpourri/osc.v: -------------------------------------------------------------------------------- 1 | module top(output osc); 2 | 3 | OSCG #( .DIV(100) ) osc_i (.OSC(osc)); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /minitests/ECP5/potpourri/osc_div.ncl: -------------------------------------------------------------------------------- 1 | ::FROM-WRITER; 2 | // designname: top 3 | // Creation time stamp: 10/24/18 20:04:40 4 | design top 5 | { 6 | device 7 | { 8 | architecture sa5p00; 9 | device LFE5U-45F; 10 | package CABGA381; 11 | performance "8"; 12 | } 13 | 14 | 15 | comp osc_i 16 | { 17 | 18 | logical 19 | { 20 | cellmodel-name OSC; 21 | program "MODE:OSCG " 22 | "OSCG:::DIV=64 "; 23 | } 24 | site OSC; 25 | } 26 | 27 | 28 | } 29 | -------------------------------------------------------------------------------- /minitests/README.md: -------------------------------------------------------------------------------- 1 | ### Minitests 2 | 3 | There are also "minitests" which are designs which can be viewed by a human to 4 | better understand how to generate more useful designs. 5 | -------------------------------------------------------------------------------- /minitests/config/usermclk.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "I" SITE "H3"; 2 | LOCATE COMP "TS" SITE "E1"; 3 | 4 | -------------------------------------------------------------------------------- /minitests/config/usermclk.v: -------------------------------------------------------------------------------- 1 | module top(input I, TS); 2 | 3 | USRMCLK mclk_i (.USRMCLKI(I), .USRMCLKTS(TS)) 4 | /* synthesis syn_noprune=1 */; 5 | endmodule -------------------------------------------------------------------------------- /minitests/ebr/ebr.v: -------------------------------------------------------------------------------- 1 | module ebr_test(input clk, input [9:0] addr, input [8:0] d, input we, output reg [8:0] q); 2 | reg [8:0] mem[0:1023]; 3 | 4 | always @(posedge clk) begin 5 | if (we) mem[addr] <= d; 6 | q <= mem[addr]; 7 | end 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /minitests/ebr/ebr_init.v: -------------------------------------------------------------------------------- 1 | module ebr_test(input clk, input [9:0] addr, input [8:0] d, input we, output reg [8:0] q); 2 | reg [8:0] mem[0:1023]; 3 | initial mem[1] = 9'b000000001; 4 | always @(posedge clk) begin 5 | if (we) mem[addr] <= d; 6 | q <= mem[addr]; 7 | end 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /minitests/ebr/ebr_init_rand.v: -------------------------------------------------------------------------------- 1 | module ebr_test(input clk, input [10:0] addr, input [8:0] d, input we, output reg [8:0] q); 2 | reg [8:0] mem[0:2047]; 3 | 4 | initial $readmemh("ebr_init_rand.dat", mem); 5 | always @(posedge clk) begin 6 | if (we) mem[addr] <= d; 7 | q <= mem[addr]; 8 | end 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /minitests/ebr/ebr_inv.v: -------------------------------------------------------------------------------- 1 | module ebr_inv(input clk, input [9:0] addr, input [8:0] d, input we, output reg [8:0] q); 2 | reg [8:0] mem[0:1023]; 3 | 4 | always @(negedge clk) begin 5 | if (we) mem[addr] <= d; 6 | q <= mem[addr]; 7 | end 8 | endmodule 9 | 10 | -------------------------------------------------------------------------------- /minitests/ebr/init.py: -------------------------------------------------------------------------------- 1 | import random 2 | random.seed(1) 3 | for i in range(2048): 4 | print("{:03x}".format(random.randint(0, 511))) 5 | -------------------------------------------------------------------------------- /minitests/global/global.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS; 2 | BLOCK ASYNCPATHS; 3 | FREQUENCY NET "clk" 200.00000 MHz; 4 | USE PRIMARY NET "clk"; 5 | #LOCATE COMP "fd_0" SITE "R2C2D"; 6 | #LOCATE COMP "fd_1" SITE "R2C124D"; 7 | #LOCATE COMP "fd_2" SITE "R93C124A"; 8 | #LOCATE COMP "fd_3" SITE "R93C2A"; -------------------------------------------------------------------------------- /minitests/global/global.v: -------------------------------------------------------------------------------- 1 | module global_test(input clk, input a, output q); 2 | 3 | reg reg_0 /* synthesis COMP=slice0 LOC="R2C2D" */; 4 | reg reg_1 /* synthesis COMP=slice1 LOC="R2C124D" */; 5 | reg reg_2 /* synthesis COMP=slice2 LOC="R93C124A" */; 6 | reg reg_3 /* synthesis COMP=slice3 LOC="R93C2A" */; 7 | reg reg_4; 8 | 9 | always @(posedge clk) begin 10 | reg_0 <= a; 11 | reg_1 <= reg_0; 12 | reg_2 <= reg_1; 13 | reg_3 <= reg_2; 14 | reg_4 <= reg_3; 15 | end 16 | 17 | assign q = reg_4; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /minitests/lut/const_0.v: -------------------------------------------------------------------------------- 1 | module top(output f); 2 | assign f = 0; 3 | endmodule 4 | -------------------------------------------------------------------------------- /minitests/lut/const_1.v: -------------------------------------------------------------------------------- 1 | module top(output f); 2 | assign f = 1; 3 | endmodule 4 | -------------------------------------------------------------------------------- /minitests/lut/lut.v: -------------------------------------------------------------------------------- 1 | module top(input a, input b, input c, input d, output q); 2 | assign q = a & b & c & d; 3 | endmodule 4 | -------------------------------------------------------------------------------- /minitests/lut/lut4_reg.v: -------------------------------------------------------------------------------- 1 | module top(input a, input b, input c, input d, input clk, output reg q); 2 | 3 | wire q_in; 4 | 5 | LUT4 #(.init (32'hF444)) I1 ( .A (a), .B (b), .C (c), .D (d), .Z (q_in) ); 6 | 7 | always @(posedge clk) begin 8 | q <= q_in; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /minitests/lut/lut5_reg.v: -------------------------------------------------------------------------------- 1 | module top(input a, input b, input c, input d, input e, input clk, output reg q); 2 | 3 | wire q_in; 4 | 5 | LUT5 #(.init (32'hF4444)) I1 ( .A (a), .B (b), .C (c), .D (d), .E (e), .Z (q_in) ); 6 | 7 | always @(posedge clk) begin 8 | q <= q_in; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /minitests/lut/lut7.v: -------------------------------------------------------------------------------- 1 | module top(input a, input b, input c, input d, input e, input f, input g, input clk, output q); 2 | 3 | // https://www.guidgenerator.com/online-guid-generator.aspx 4 | LUT7 #(.init (128'hd13686b35db74bd88bbb244fc3fd36af)) I1 ( .A (a), .B (b), .C (c), .D (d), .E (e), .F (f), .G (g), .Z (q) ); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /minitests/machxo2/cb2/cb2.v: -------------------------------------------------------------------------------- 1 | module top(input pc0, input pc1, input con, output nc0, output nc1); 2 | CB2 C1 ( .CI (1'b0), .PC0 (pc0), .PC1 (pc1), .CON (con), .NC0 (nc0), .NC1 (nc1) ); 3 | endmodule 4 | -------------------------------------------------------------------------------- /minitests/machxo2/dcc/dcc1.v: -------------------------------------------------------------------------------- 1 | module dcc_test1(input clki, input ce, output clko); 2 | 3 | DCCA I1 (.CLKI (clki), .CE (ce), .CLKO (clko)); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /minitests/machxo2/dcc/dcc2.v: -------------------------------------------------------------------------------- 1 | module dcc_test2(input clki, input ce0, input ce1, output clko); 2 | 3 | wire clk_int; 4 | 5 | // Despite EPIC claiming more DCCs exist, and the synthesizer accepting 6 | // the LOC constraint, trying to use the other DCCs causes an assertion failure 7 | // during placement! 8 | 9 | DCCA I1 (.CLKI (clki), .CE (ce0), .CLKO (clk_int)); 10 | DCCA I2 (.CLKI (clk_int), .CE (ce1), .CLKO (clko)) /* synthesis LOC=DCC_R6C14_0B */; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /minitests/machxo2/osch/osch.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "clk" SITE "13" ; 4 | -------------------------------------------------------------------------------- /minitests/machxo2/osch/osch.v: -------------------------------------------------------------------------------- 1 | module osch ( 2 | input clk, 3 | output stdby 4 | ); 5 | 6 | wire out; 7 | 8 | OSCH #( 9 | .NOM_FREQ("2.08") 10 | ) osch_clk ( 11 | .STDBY(stdby), 12 | .OSC(out) 13 | ); 14 | 15 | assign clk = stdby; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /minitests/machxo2/pio/bb_machxo2.v: -------------------------------------------------------------------------------- 1 | module top(input pad); 2 | 3 | wire dummyo, dummyi; 4 | 5 | (* LOC="PB11C" *) 6 | (* IO_TYPE="LVTTL33" *) 7 | BB i_b(.B(pad), .O(dummyo), .I(1'b1), .T(dummyi)); 8 | 9 | // Dummy load 10 | GSR gsr_i(.GSR(dummyo)); 11 | 12 | // Dummy source 13 | OSCH osc_i(.OSC(dummyi)); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /minitests/machxo2/spr/spr.v: -------------------------------------------------------------------------------- 1 | module top(input [3:0] di, input ck, input wre, input [3:0] ad, output [3:0] d_o); 2 | 3 | SPR16X4C #(.initval ("0xF444")) R1 ( .DI3 (di[3]), .DI2 (di[2]), .DI1 (di[1]), .DI0 (di[0]), 4 | .CK (ck), .WRE (wre), .AD3 (ad[3]), .AD2 (ad[2]), .AD1 (ad[1]), .AD0 (ad[0]), 5 | .DO3 (d_o[3]), .DO2 (d_o[2]), .DO1 (d_o[1]), .DO0 (d_o[0])); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /minitests/machxo2/vref/vref.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "in" SITE "12" ; 4 | LOCATE COMP "out" SITE "13" ; 5 | IOBUF PORT "in" HYSTERESIS=NA IO_TYPE=LVCMOS25R33 VREF="MyVref" ; 6 | LOCATE VREF "MyVref" SITE "11" ; 7 | IOBUF PORT "out" IO_TYPE=LVCMOS33 ; 8 | -------------------------------------------------------------------------------- /minitests/machxo2/vref/vref.v: -------------------------------------------------------------------------------- 1 | module vref ( 2 | input in, 3 | output out 4 | ); 5 | 6 | assign out = in; 7 | 8 | endmodule -------------------------------------------------------------------------------- /minitests/pio/bb.v: -------------------------------------------------------------------------------- 1 | module top(input pad); 2 | 3 | wire dummyo, dummyi; 4 | 5 | (* LOC="P4" *) 6 | (* IO_TYPE="LVTTL33" *) 7 | BB i_b(.B(pad), .O(dummyo), .I(1'b1), .T(dummyi)); 8 | 9 | // Dummy load 10 | GSR gsr_i(.GSR(dummyo)); 11 | 12 | // Dummy source 13 | OSCG osc_i(.OSC(dummyi)); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /minitests/pio/ib.v: -------------------------------------------------------------------------------- 1 | module top(input pad); 2 | 3 | (* LOC="P4" *) 4 | (* IO_TYPE="LVTTL33" *) 5 | IB i_b(.I(pad), .O(dummy)); 6 | 7 | // Dummy load 8 | GSR gsr_i(.GSR(dummy)); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /minitests/reg/async.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, output reg q); 2 | always @(posedge clk or posedge set) 3 | if (set) 4 | q <= 1'b1; 5 | else 6 | q <= d; 7 | endmodule 8 | -------------------------------------------------------------------------------- /minitests/reg/async_gsr.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, r, output reg q); 2 | GSR gsr(.GSR(r)); 3 | always @(posedge clk or posedge set) 4 | if (set) 5 | q <= 1'b1; 6 | else 7 | q <= d; 8 | endmodule 9 | -------------------------------------------------------------------------------- /minitests/reg/async_sr.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, reset, cen, output reg q); 2 | always @(posedge clk or posedge set or posedge reset) 3 | if (set) 4 | q <= 1'b1; 5 | else if(reset) 6 | q <= 1'b0; 7 | else if(cen) 8 | q <= d; 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/reg/ce.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, cen, output reg q); 2 | always @(posedge clk) 3 | if (cen) 4 | q <= d; 5 | endmodule 6 | -------------------------------------------------------------------------------- /minitests/reg/ce_0.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, input s, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3JX ff(.D(d), .SP(1'b0), .PD(s), .CK(clk), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/ce_inv.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, cen, output reg q); 2 | always @(posedge clk) 3 | if (!cen) 4 | q <= d; 5 | endmodule 6 | -------------------------------------------------------------------------------- /minitests/reg/ce_over_lsr.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, cen, output reg q); 2 | always @(posedge clk) 3 | if (cen) 4 | if (set) 5 | q <= 1'b1; 6 | else 7 | q <= d; 8 | endmodule 9 | -------------------------------------------------------------------------------- /minitests/reg/clk_0.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, input s, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3JX ff(.D(d), .SP(1'b0), .PD(s), .CK(1'b0), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/clk_1.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, input s, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3JX ff(.D(d), .SP(1'b0), .PD(s), .CK(1'b1), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/clk_inv.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, output reg q); 2 | always @(negedge clk) 3 | q <= d; 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/ffmux.v: -------------------------------------------------------------------------------- 1 | module top(input CK, SD, SP, D0, D1, output Q); 2 | 3 | FL1P3AZ ff(.CK(CK), .SD(SD), .SP(SP), .D0(D0), .D1(D1), .Q(Q)); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /minitests/reg/gsr.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3AX ff(.D(d), .SP(1'b1), .CK(clk), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/gsr2.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, input s, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3JX ff(.D(d), .SP(1'b1), .PD(s), .CK(clk), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/latch.v: -------------------------------------------------------------------------------- 1 | module top(input set, input reset, input d, output reg q); 2 | always @(set or reset) begin 3 | if(reset) begin 4 | q <= 0; 5 | end else if(set) begin 6 | q <= d; 7 | end 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/reg/latch_inv.v: -------------------------------------------------------------------------------- 1 | module top(input set, input reset, input d, output reg q); 2 | always @(set or reset) begin 3 | if(reset) begin 4 | q <= 0; 5 | end else if(~set) begin 6 | q <= d; 7 | end 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /minitests/reg/lsr_inv.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, input r, input s, output q); 2 | GSR gsr(.GSR(r)); 3 | FD1P3JX ff(.D(d), .SP(1'b0), .PD(!s), .CK(clk), .Q(q)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/lsr_over_ce.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, cen, output reg q); 2 | always @(posedge clk) 3 | if (set) 4 | q <= 1'b1; 5 | else 6 | if (cen) 7 | q <= d; 8 | endmodule 9 | -------------------------------------------------------------------------------- /minitests/reg/lut_reg.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input a, output reg q); 2 | always @(posedge clk) 3 | q <= ~a; 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/plain.v: -------------------------------------------------------------------------------- 1 | module top(input clk, input d, output reg q); 2 | always @(posedge clk) 3 | q <= d; 4 | endmodule 5 | -------------------------------------------------------------------------------- /minitests/reg/reset.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, reset, output reg q); 2 | initial q = 1'b1; 3 | always @(posedge clk) 4 | if (reset) 5 | q <= 1'b0; 6 | else 7 | q <= d; 8 | endmodule 9 | -------------------------------------------------------------------------------- /minitests/reg/set.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, output reg q); 2 | always @(posedge clk) 3 | if (set) 4 | q <= 1'b1; 5 | else 6 | q <= d; 7 | endmodule 8 | -------------------------------------------------------------------------------- /minitests/reg/set_inv.v: -------------------------------------------------------------------------------- 1 | module top(input clk, d, set, output reg q); 2 | always @(posedge clk) 3 | if (!set) 4 | q <= 1'b1; 5 | else 6 | q <= d; 7 | endmodule 8 | -------------------------------------------------------------------------------- /minitests/timing_distances/span2h/.gitignore: -------------------------------------------------------------------------------- 1 | *.ncl 2 | -------------------------------------------------------------------------------- /minitests/timing_distances/span2v/.gitignore: -------------------------------------------------------------------------------- 1 | *.ncl 2 | -------------------------------------------------------------------------------- /minitests/timing_distances/span6h/.gitignore: -------------------------------------------------------------------------------- 1 | *.ncl 2 | -------------------------------------------------------------------------------- /minitests/timing_loads/local/.gitignore: -------------------------------------------------------------------------------- 1 | *.ncl 2 | -------------------------------------------------------------------------------- /minitests/timing_loads/span2/.gitignore: -------------------------------------------------------------------------------- 1 | *.ncl 2 | -------------------------------------------------------------------------------- /minitests/wire/wire.v: -------------------------------------------------------------------------------- 1 | module top(input a, output q); 2 | assign q = a; 3 | endmodule 4 | -------------------------------------------------------------------------------- /minitests/wire/wire_pad.lpf: -------------------------------------------------------------------------------- 1 | LOCATE COMP "a" SITE "C5" ; #PL11A 2 | LOCATE COMP "q" SITE "C11" ; #PT36B -------------------------------------------------------------------------------- /minitests/wire/wire_pad.v: -------------------------------------------------------------------------------- 1 | module top(input a, output q); 2 | assign q = a; 3 | endmodule 4 | -------------------------------------------------------------------------------- /misc/basecfgs/README.md: -------------------------------------------------------------------------------- 1 | # Skeleton Configuration Files 2 | 3 | These contain unknown bits that should always be included in a 4 | bitstream for each architecture. 5 | 6 | -------------------------------------------------------------------------------- /misc/basecfgs/empty_machxo2-1200hc.config: -------------------------------------------------------------------------------- 1 | .device LCMXO2-1200HC 2 | 3 | .tile EBR_R6C11:EBR1 4 | unknown: F0B12 5 | 6 | .tile EBR_R6C15:EBR1 7 | unknown: F0B12 8 | 9 | .tile EBR_R6C18:EBR1 10 | unknown: F0B12 11 | 12 | .tile EBR_R6C21:EBR1 13 | unknown: F0B12 14 | 15 | .tile EBR_R6C2:EBR1 16 | unknown: F0B12 17 | 18 | .tile EBR_R6C5:EBR1 19 | unknown: F0B12 20 | 21 | .tile EBR_R6C8:EBR1 22 | unknown: F0B12 23 | 24 | .tile PT4:CFG0 25 | unknown: F5B30 26 | unknown: F5B32 27 | unknown: F5B36 28 | 29 | .tile PT7:CFG3 30 | unknown: F5B18 31 | -------------------------------------------------------------------------------- /misc/openocd/ecp5-evn.cfg: -------------------------------------------------------------------------------- 1 | # this supports ECP5 Evaluation Board 2 | 3 | interface ftdi 4 | ftdi_device_desc "Lattice ECP5 Evaluation Board" 5 | ftdi_vid_pid 0x0403 0x6010 6 | # channel 1 does not have any functionality 7 | ftdi_channel 0 8 | # just TCK TDI TDO TMS, no reset 9 | ftdi_layout_init 0xfff8 0xfffb 10 | reset_config none 11 | 12 | # default speed 13 | adapter_khz 5000 14 | 15 | # ECP5 device - LFE5UM5G-85F 16 | jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043 17 | -------------------------------------------------------------------------------- /misc/openocd/trellisboard.cfg: -------------------------------------------------------------------------------- 1 | # TrellisBoard OpenOCD config 2 | 3 | interface ftdi 4 | # ftdi_device_desc "TrellisBoard" 5 | ftdi_vid_pid 0x0403 0x6010 6 | # channel 1 does not have any functionality 7 | ftdi_channel 0 8 | # just TCK TDI TDO TMS, no reset 9 | ftdi_layout_init 0xfff8 0xfffb 10 | reset_config none 11 | 12 | # default speed 13 | adapter_khz 5000 14 | 15 | # ECP5 device - LFE5UM5G-85F 16 | jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043 17 | -------------------------------------------------------------------------------- /misc/openocd/ulx3s.cfg: -------------------------------------------------------------------------------- 1 | interface ft232r 2 | ft232r_vid_pid 0x0403 0x6015 3 | # ULX3S specific GPIO setting 4 | ft232r_tck_num DSR 5 | ft232r_tms_num DCD 6 | ft232r_tdi_num RI 7 | ft232r_tdo_num CTS 8 | # trst/srst are not used but must have different values than above 9 | ft232r_trst_num RTS 10 | ft232r_srst_num DTR 11 | adapter_khz 1000 12 | 13 | jtag newtap ecp5 tap -irlen 8 -expected-id 0x41112043 14 | -------------------------------------------------------------------------------- /misc/openocd/ulx3s_85k.cfg: -------------------------------------------------------------------------------- 1 | interface ft232r 2 | ft232r_vid_pid 0x0403 0x6015 3 | # ULX3S specific GPIO setting 4 | ft232r_tck_num DSR 5 | ft232r_tms_num DCD 6 | ft232r_tdi_num RI 7 | ft232r_tdo_num CTS 8 | # trst/srst are not used but must have different values than above 9 | ft232r_trst_num RTS 10 | ft232r_srst_num DTR 11 | adapter_khz 1000 12 | 13 | jtag newtap ecp5 tap -irlen 8 -expected-id 0x41113043 14 | -------------------------------------------------------------------------------- /third_party/README.md: -------------------------------------------------------------------------------- 1 | ### Third Party 2 | 3 | Third party contains code not developed as part of Project Trellis. 4 | -------------------------------------------------------------------------------- /timing/fuzzers/.gitignore: -------------------------------------------------------------------------------- 1 | work/ -------------------------------------------------------------------------------- /timing/fuzzers/ECP5/010-basic-cells/fuzzer.py: -------------------------------------------------------------------------------- 1 | import cell_fuzzers 2 | 3 | 4 | def main(): 5 | cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/distributed_ram.v", "../../../resource/nescore.v"]) 6 | 7 | 8 | if __name__ == "__main__": 9 | main() 10 | -------------------------------------------------------------------------------- /timing/resource/math.v: -------------------------------------------------------------------------------- 1 | module top ( 2 | input clk, 3 | input [31:0] a, 4 | input [31:0] b, 5 | input [7:0] c, 6 | 7 | output reg [63:0] d 8 | ); 9 | 10 | reg [63:0] tmp; 11 | always @(posedge clk) begin 12 | tmp <= tmp + 123323; 13 | d <= (a + b) * c + tmp; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /timing/util/.gitignore: -------------------------------------------------------------------------------- 1 | *.csv 2 | .lock* 3 | *.json 4 | -------------------------------------------------------------------------------- /timing/util/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/timing/util/__init__.py -------------------------------------------------------------------------------- /tools/.gitignore: -------------------------------------------------------------------------------- 1 | ecpunpack 2 | *.bit 3 | *.dump 4 | *.out 5 | work_*/ 6 | *.tmp/ 7 | *.dbg 8 | -------------------------------------------------------------------------------- /tools/README.md: -------------------------------------------------------------------------------- 1 | # Initial ECP5 bitstream analysis tools 2 | 3 | `ecpunpack` can unpack a bitstream from .bit format to a series of (bit, frame) tuples. 4 | 5 | `compare_bits.py` compares the output of ecpunpack with the output of `bstool -d` in Diamond. 6 | 7 | EBR initialisation commands are not yet supported and will cause ecpunpack to fail. 8 | -------------------------------------------------------------------------------- /tools/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/tools/__init__.py -------------------------------------------------------------------------------- /tools/demobuilder/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/tools/demobuilder/__init__.py -------------------------------------------------------------------------------- /util/common/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/YosysHQ/prjtrellis/f98e72e4963d9c9da57620595282e58d46a045f7/util/common/__init__.py -------------------------------------------------------------------------------- /util/common/nets/__init__.py: -------------------------------------------------------------------------------- 1 | from .general import * 2 | import ecp5 3 | import machxo2 4 | from .util import * 5 | -------------------------------------------------------------------------------- /util/common/nets/util.py: -------------------------------------------------------------------------------- 1 | # Useful functions for constructing nets. 2 | def char_range(c1, c2): 3 | """Generates the characters from `c1` to `c2`, exclusive.""" 4 | for c in range(ord(c1), ord(c2)): 5 | yield chr(c) 6 | 7 | def net_product(net_list, range_iter): 8 | return [n.format(i) for i in range_iter for n in net_list] 9 | --------------------------------------------------------------------------------