├── .gitignore ├── MachXO └── tiledata │ ├── CLK0 │ └── bits.db │ ├── CLK1 │ └── bits.db │ ├── CLK2 │ └── bits.db │ ├── CLK3 │ └── bits.db │ ├── CLK4 │ └── bits.db │ ├── CLK5 │ └── bits.db │ ├── FPLC │ └── bits.db │ ├── LLC │ └── bits.db │ ├── LRC │ └── bits.db │ ├── PLC │ └── bits.db │ ├── ULC │ └── bits.db │ ├── URC │ └── bits.db │ ├── CLK0_2K │ └── bits.db │ ├── CLK1_2K │ └── bits.db │ ├── CLK2_2K │ └── bits.db │ ├── CLK3_2K │ └── bits.db │ ├── CLK4_2K │ └── bits.db │ ├── CLK5_2K │ └── bits.db │ ├── CLK_DUMMY │ └── bits.db │ ├── LLC256 │ └── bits.db │ ├── LRC256 │ └── bits.db │ ├── PIC2_L │ └── bits.db │ ├── PIC2_R │ └── bits.db │ ├── PIC4_B │ └── bits.db │ ├── PIC4_L │ └── bits.db │ ├── PIC4_R │ └── bits.db │ ├── PIC4_T │ └── bits.db │ ├── PIC6_B │ └── bits.db │ ├── PIC6_T │ └── bits.db │ ├── PIC_L │ └── bits.db │ ├── PIC_L_GSR │ └── bits.db │ ├── PIC_L_ISP │ └── bits.db │ ├── PIC_L_OSC │ └── bits.db │ ├── PIC_R │ └── bits.db │ ├── ULC256 │ └── bits.db │ ├── URC256 │ └── bits.db │ ├── CLK_DUMMY_PICB │ └── bits.db │ ├── CLK_DUMMY_PICT │ └── bits.db │ ├── LLC_EBR2K_0 │ └── bits.db │ ├── PIC2_L_EBR1K_0 │ └── bits.db │ ├── PIC2_L_EBR2K_1 │ └── bits.db │ ├── PIC2_L_EBR2K_2 │ └── bits.db │ ├── PIC2_L_EBR2K_3 │ └── bits.db │ ├── PIC2_L_GSR │ └── bits.db │ ├── PIC2_L_ISP │ └── bits.db │ ├── PIC2_L_OSC │ └── bits.db │ ├── PIC2_L_PLL1K │ └── bits.db │ ├── PIC2_R_LVDS │ └── bits.db │ ├── PIC4_L_EBR1K_1 │ └── bits.db │ ├── PIC4_L_EBR1K_2 │ └── bits.db │ ├── PIC4_L_EBR1K_3 │ └── bits.db │ ├── PIC4_L_EBR1K_4 │ └── bits.db │ ├── PIC4_L_EBR1K_5 │ └── bits.db │ ├── PIC4_L_EBR1K_6 │ └── bits.db │ ├── PIC4_L_EBR2K_4 │ └── bits.db │ ├── PIC4_L_EBR2K_5 │ └── bits.db │ ├── PIC4_L_EBR2K_6 │ └── bits.db │ ├── PIC4_L_EBR2K_7 │ └── bits.db │ ├── PIC4_L_EBR2K_8 │ └── bits.db │ ├── PIC4_L_EBR2K_9 │ └── bits.db │ ├── ULC_EBR2K_20 │ └── bits.db │ ├── PIC2_L_EBR2K_19 │ └── bits.db │ ├── PIC4_L_EBR2K_10 │ └── bits.db │ ├── PIC4_L_EBR2K_11 │ └── bits.db │ ├── PIC4_L_EBR2K_12 │ └── bits.db │ ├── PIC4_L_EBR2K_13 │ └── bits.db │ ├── PIC4_L_EBR2K_14 │ └── bits.db │ ├── PIC4_L_EBR2K_15 │ └── bits.db │ ├── PIC4_L_EBR2K_16 │ └── bits.db │ ├── PIC4_L_EBR2K_17 │ └── bits.db │ └── PIC4_L_EBR2K_18 │ └── bits.db ├── ECP5 ├── tiledata │ ├── OSC │ │ └── bits.db │ ├── POR │ │ └── bits.db │ ├── DSP_CMUX_UR │ │ └── bits.db │ ├── DUMMY_TILE_0 │ │ └── bits.db │ ├── DUMMY_TILE_1 │ │ └── bits.db │ ├── DUMMY_TILE_2 │ │ └── bits.db │ ├── DUMMY_TILE_4 │ │ └── bits.db │ ├── DUMMY_TILE_5 │ │ └── bits.db │ ├── DUMMY_TILE_6 │ │ └── bits.db │ ├── DUMMY_TILE_7 │ │ └── bits.db │ ├── DUMMY_TILE_8 │ │ └── bits.db │ ├── DUMMY_TILE_A │ │ └── bits.db │ ├── DUMMY_TILE_E │ │ └── bits.db │ ├── DUMMY_TILE_F │ │ └── bits.db │ ├── DUMMY_TILE_S │ │ └── bits.db │ ├── DUMMY_TILE_T │ │ └── bits.db │ ├── MIB_CIB_LRC │ │ └── bits.db │ ├── MIB_CIB_LX │ │ └── bits.db │ ├── MIB_CIB_RX │ │ └── bits.db │ ├── PVT_COUNT2 │ │ └── bits.db │ ├── MIB_CIB_LRC_A │ │ └── bits.db │ ├── VIQ_BUF │ │ └── bits.db │ ├── BANKREF0 │ │ └── bits.db │ ├── BANKREF1 │ │ └── bits.db │ ├── BANKREF2 │ │ └── bits.db │ ├── BANKREF7 │ │ └── bits.db │ ├── BANKREF2A │ │ └── bits.db │ ├── BANKREF7A │ │ └── bits.db │ ├── BANKREF3 │ │ └── bits.db │ ├── BANKREF6 │ │ └── bits.db │ ├── DTR │ │ └── bits.db │ ├── MIB_EBR8 │ │ └── bits.db │ ├── DSP_SPINE_UL1 │ │ └── bits.db │ ├── EBR_SPINE_LL3 │ │ └── bits.db │ ├── MIB_EBR1 │ │ └── bits.db │ ├── DDRDLL_LL │ │ └── bits.db │ ├── DDRDLL_LR │ │ └── bits.db │ ├── DDRDLL_UL │ │ └── bits.db │ ├── DDRDLL_ULA │ │ └── bits.db │ ├── DDRDLL_UR │ │ └── bits.db │ ├── DDRDLL_URA │ │ └── bits.db │ ├── DCU7 │ │ └── bits.db │ ├── EBR_CMUX_LL │ │ └── bits.db │ ├── EBR_CMUX_LL_25K │ │ └── bits.db │ ├── MIB_DSP8 │ │ └── bits.db │ ├── MIB_EBR3 │ │ └── bits.db │ ├── BMID_2V │ │ └── bits.db │ ├── EBR_SPINE_LL0 │ │ └── bits.db │ ├── EBR_SPINE_LL1 │ │ └── bits.db │ ├── EBR_SPINE_LL2 │ │ └── bits.db │ ├── EBR_SPINE_LR0 │ │ └── bits.db │ ├── EBR_SPINE_LR1 │ │ └── bits.db │ ├── EBR_SPINE_LR2 │ │ └── bits.db │ ├── EBR_SPINE_UL0 │ │ └── bits.db │ ├── EBR_SPINE_UL1 │ │ └── bits.db │ ├── EBR_SPINE_UL2 │ │ └── bits.db │ ├── EBR_SPINE_UR0 │ │ └── bits.db │ ├── EBR_SPINE_UR1 │ │ └── bits.db │ ├── EBR_SPINE_UR2 │ │ └── bits.db │ ├── DSP_CMUX_UL │ │ └── bits.db │ ├── TAP_DRIVE │ │ └── bits.db │ ├── TAP_DRIVE_CIB │ │ └── bits.db │ ├── DCU8 │ │ └── bits.db │ ├── MIB_EBR5 │ │ └── bits.db │ ├── DCU6 │ │ └── bits.db │ ├── DCU2 │ │ └── bits.db │ ├── DCU5 │ │ └── bits.db │ ├── DSP_SPINE_UL0 │ │ └── bits.db │ ├── DSP_SPINE_UR0 │ │ └── bits.db │ ├── DSP_SPINE_UR1 │ │ └── bits.db │ ├── PLL1_UL │ │ └── bits.db │ ├── PLL1_UR │ │ └── bits.db │ ├── PLL1_LR │ │ └── bits.db │ ├── MIB_EBR7 │ │ └── bits.db │ ├── BANKREF8 │ │ └── bits.db │ ├── BANKREF4 │ │ └── bits.db │ ├── DCU4 │ │ └── bits.db │ ├── DCU3 │ │ └── bits.db │ ├── PIOT1 │ │ └── bits.db │ ├── DCU1 │ │ └── bits.db │ └── SPICB0 │ │ └── bits.db ├── LFE5U-12F │ └── globals.json ├── LFE5U-25F │ └── globals.json ├── LFE5UM-25F │ └── globals.json ├── LFE5UM5G-25F │ └── globals.json ├── LFE5U-45F │ └── globals.json ├── LFE5UM-45F │ └── globals.json ├── LFE5UM5G-45F │ └── globals.json ├── LFE5U-85F │ └── globals.json ├── LFE5UM-85F │ └── globals.json └── LFE5UM5G-85F │ └── globals.json ├── MachXO2 └── tiledata │ ├── CENTER0 │ └── bits.db │ ├── CENTER1 │ └── bits.db │ ├── CENTER2 │ └── bits.db │ ├── CENTER3 │ └── bits.db │ ├── CENTER_B │ └── bits.db │ ├── CENTER_T │ └── bits.db │ ├── CFG0_ENDL │ └── bits.db │ ├── EBR0_640 │ └── bits.db │ ├── EBR1_640 │ └── bits.db │ ├── EBR2_640 │ └── bits.db │ ├── EBR_DUMMY │ └── bits.db │ ├── LLC0PIC │ └── bits.db │ ├── LLC1PIC │ └── bits.db │ ├── LRC0PIC │ └── bits.db │ ├── LRC1PIC1 │ └── bits.db │ ├── PIC_TS0 │ └── bits.db │ ├── ULC0_256 │ └── bits.db │ ├── ULC1_640 │ └── bits.db │ ├── URC0VREF │ └── bits.db │ ├── B_DUMMY_ENDL │ └── bits.db │ ├── B_DUMMY_ENDR │ └── bits.db │ ├── CENTER4_640 │ └── bits.db │ ├── CENTER_B_CIB │ └── bits.db │ ├── CENTER_DUMMY │ └── bits.db │ ├── CENTER_EBR_SP │ └── bits.db │ ├── CENTER_T_CIB │ └── bits.db │ ├── CIB_EBR0_640 │ └── bits.db │ ├── CIB_EBR1_640 │ └── bits.db │ ├── CIB_EBR2_640 │ └── bits.db │ ├── CIB_PIC_B0_256 │ └── bits.db │ ├── CIB_PIC_B0_640 │ └── bits.db │ ├── CIB_PIC_TS0 │ └── bits.db │ ├── EBR2_640_END │ └── bits.db │ ├── EBR_DUMMY_END │ └── bits.db │ ├── PIC_B0_256 │ └── bits.db │ ├── PIC_BS0_256 │ └── bits.db │ ├── PIC_B_DUMMY │ └── bits.db │ ├── PIC_L1_VREF3 │ └── bits.db │ ├── PIC_R0_256 │ └── bits.db │ ├── PIC_R1_640 │ └── bits.db │ ├── PIC_RS0_256 │ └── bits.db │ ├── PIC_T0_256 │ └── bits.db │ ├── PIC_T_DUMMY │ └── bits.db │ ├── T_DUMMY_ENDR │ └── bits.db │ ├── B_DUMMY_ENDR_VREF2 │ └── bits.db │ ├── CENTER_B_CIB_256 │ └── bits.db │ ├── CENTER_T_CIB_256 │ └── bits.db │ ├── CIB_EBR2_640_END │ └── bits.db │ ├── CIB_PIC_BS0_256 │ └── bits.db │ ├── CIB_PIC_B_DUMMY_256 │ └── bits.db │ ├── CIB_PIC_B_DUMMY_640 │ └── bits.db │ ├── PIC_L0_DUMMY_256 │ └── bits.db │ ├── PIC_L1_DUMMY_640 │ └── bits.db │ ├── PIC_R0_DUMMY_256 │ └── bits.db │ ├── PIC_R1_DUMMY_640 │ └── bits.db │ ├── PIC_T_DUMMY_VIQ_256 │ └── bits.db │ ├── PIC_T_DUMMY_OSC │ └── bits.db │ ├── CFG2 │ └── bits.db │ ├── CENTER_EBR │ └── bits.db │ ├── EBR2 │ └── bits.db │ ├── EBR2_END │ └── bits.db │ ├── PIC_B_DUMMY_VREF │ └── bits.db │ ├── CENTER4 │ └── bits.db │ ├── CENTERB │ └── bits.db │ ├── CENTER8 │ └── bits.db │ ├── CENTER_EBR_CIB_SP │ └── bits.db │ ├── CENTER6 │ └── bits.db │ ├── CFG3 │ └── bits.db │ ├── DQSDLL_R │ └── bits.db │ ├── DQSDLL_L │ └── bits.db │ ├── CFG0 │ └── bits.db │ └── EBR1 │ └── bits.db ├── MachXO3 └── tiledata │ ├── CENTER_B │ └── bits.db │ ├── CENTER_T │ └── bits.db │ ├── EBR_DUMMY │ └── bits.db │ ├── B_DUMMY_ENDL │ └── bits.db │ ├── B_DUMMY_ENDR │ └── bits.db │ ├── CENTER_B_CIB │ └── bits.db │ ├── CENTER_DUMMY │ └── bits.db │ ├── CENTER_EBR_SP │ └── bits.db │ ├── CENTER_T_CIB │ └── bits.db │ ├── EBR_DUMMY_END │ └── bits.db │ ├── PIC_B_DUMMY │ └── bits.db │ ├── PIC_T_DUMMY │ └── bits.db │ ├── T_DUMMY_ENDR │ └── bits.db │ ├── PIC_T_DUMMY_OSC │ └── bits.db │ ├── CFG2 │ └── bits.db │ ├── CENTER_EBR │ └── bits.db │ ├── EBR2 │ └── bits.db │ ├── EBR2_10K │ └── bits.db │ ├── EBR2_END │ └── bits.db │ ├── EBR2_END_10K │ └── bits.db │ ├── PIC_B_DUMMY_VREF │ └── bits.db │ ├── CENTER4 │ └── bits.db │ ├── CENTER9 │ └── bits.db │ ├── CENTERB │ └── bits.db │ ├── CENTER8 │ └── bits.db │ ├── CENTER_EBR_CIB_SP │ └── bits.db │ ├── CENTER6 │ └── bits.db │ ├── DQSDLL_R │ └── bits.db │ ├── CFG3 │ └── bits.db │ ├── CFG0 │ └── bits.db │ ├── EBR1 │ └── bits.db │ └── EBR1_10K │ └── bits.db ├── MachXO3D └── tiledata │ ├── CENTER_B │ └── bits.db │ ├── CENTER_T │ └── bits.db │ ├── CIB_HSE │ └── bits.db │ ├── B_DUMMY_ENDL │ └── bits.db │ ├── B_DUMMY_ENDR │ └── bits.db │ ├── CENTER_B_CIB │ └── bits.db │ ├── CENTER_DUMMY │ └── bits.db │ ├── CENTER_EBR_SP │ └── bits.db │ ├── CENTER_T_CIB │ └── bits.db │ ├── EBR_DUMMY │ └── bits.db │ ├── PIC_B_DUMMY │ └── bits.db │ ├── PIC_T_DUMMY │ └── bits.db │ ├── PIC_T_DUMMY_OSC │ └── bits.db │ ├── CFG2 │ └── bits.db │ ├── CENTER_EBR │ └── bits.db │ ├── EBR2 │ └── bits.db │ ├── EBR2_10K │ └── bits.db │ ├── EBR2_END │ └── bits.db │ ├── EBR2_END_10K │ └── bits.db │ ├── CENTER9 │ └── bits.db │ ├── CENTERB │ └── bits.db │ ├── CENTER8 │ └── bits.db │ ├── CENTER_EBR_CIB_SP │ └── bits.db │ ├── CENTER6 │ └── bits.db │ ├── DQSDLL_R │ └── bits.db │ ├── DQSDLL_L │ └── bits.db │ ├── CFG0 │ └── bits.db │ ├── CFG3 │ └── bits.db │ └── EBR1 │ └── bits.db └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | html 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK0/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK1/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK2/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK3/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK4/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK5/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/FPLC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/LLC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/LRC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PLC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/ULC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/URC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK0_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK1_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK2_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK3_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK4_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK5_2K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/LLC256/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/LRC256/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_R/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_B/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_R/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_T/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC6_B/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC6_T/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC_L/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC_L_GSR/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC_L_ISP/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC_L_OSC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC_R/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/ULC256/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/URC256/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK_DUMMY_PICB/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/CLK_DUMMY_PICT/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/LLC_EBR2K_0/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_EBR1K_0/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_EBR2K_1/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_EBR2K_2/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_EBR2K_3/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_GSR/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_ISP/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_OSC/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_PLL1K/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_R_LVDS/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_1/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_2/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_3/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_4/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_5/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR1K_6/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_4/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_5/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_6/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_7/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_8/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_9/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/ULC_EBR2K_20/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC2_L_EBR2K_19/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_10/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_11/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_12/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_13/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_14/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_15/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_16/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_17/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /MachXO/tiledata/PIC4_L_EBR2K_18/bits.db: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /ECP5/tiledata/OSC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/POR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_CMUX_UR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_4/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_5/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_7/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_A/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_E/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_F/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_S/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/DUMMY_TILE_T/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_CIB_LRC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_CIB_LX/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_CIB_RX/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/PVT_COUNT2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_B/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_T/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CFG0_ENDL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR0_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR1_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR2_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/LLC0PIC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/LLC1PIC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/LRC0PIC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/LRC1PIC1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_TS0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/ULC0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/ULC1_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/URC0VREF/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_B/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_T/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_B/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_T/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CIB_HSE/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_CIB_LRC_A/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/B_DUMMY_ENDL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/B_DUMMY_ENDR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER4_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_B_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_EBR_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_T_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_EBR0_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_EBR1_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_EBR2_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_B0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_B0_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_TS0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR2_640_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR_DUMMY_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_B0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_BS0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_B_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_L1_VREF3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_R0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_R1_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_RS0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_T0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_T_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/T_DUMMY_ENDR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/B_DUMMY_ENDL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/B_DUMMY_ENDR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_B_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_EBR_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_T_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR_DUMMY_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/PIC_B_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/PIC_T_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3/tiledata/T_DUMMY_ENDR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/B_DUMMY_ENDL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/B_DUMMY_ENDR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_B_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_EBR_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_T_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/PIC_B_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/PIC_T_DUMMY/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/B_DUMMY_ENDR_VREF2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_B_CIB_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_T_CIB_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_EBR2_640_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_BS0_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_B_DUMMY_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CIB_PIC_B_DUMMY_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_L0_DUMMY_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_L1_DUMMY_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_R0_DUMMY_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_R1_DUMMY_640/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_T_DUMMY_VIQ_256/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | 5 | # Fixed Connections 6 | -------------------------------------------------------------------------------- /ECP5/tiledata/VIQ_BUF/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum GSR.SYNCMODE ASYNC 5 | ASYNC - 6 | NONE - 7 | SYNC F2B0 8 | 9 | 10 | # Fixed Connections 11 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_T_DUMMY_OSC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum OSCH.STDBY 0 5 | 0 !F5B46 6 | 1 F5B46 7 | 8 | .config_enum PCNTR.POROFF FALSE 9 | FALSE - 10 | TRUE F5B41 11 | 12 | 13 | # Fixed Connections 14 | -------------------------------------------------------------------------------- /MachXO3/tiledata/PIC_T_DUMMY_OSC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum OSCH.STDBY 0 5 | 0 !F5B46 6 | 1 F5B46 7 | 8 | .config_enum PCNTR.POROFF FALSE 9 | FALSE - 10 | TRUE F5B41 11 | 12 | 13 | # Fixed Connections 14 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/PIC_T_DUMMY_OSC/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum OSCJ.STDBY 0 5 | 0 !F5B46 6 | 1 F5B46 7 | 8 | .config_enum PCNTR.POROFF FALSE 9 | FALSE - 10 | TRUE F5B41 11 | 12 | 13 | # Fixed Connections 14 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CFG2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.BGOFF FALSE 5 | FALSE - 6 | TRUE F5B40 7 | 8 | .config_enum SED.MODE NONE 9 | NONE - 10 | SEDFA F5B32 11 | SEDFB F5B32 12 | 13 | 14 | # Fixed Connections 15 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CFG2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.BGOFF FALSE 5 | FALSE - 6 | TRUE F5B40 7 | 8 | .config_enum SED.MODE NONE 9 | NONE - 10 | SEDFA F5B32 11 | SEDFB F5B32 12 | 13 | 14 | # Fixed Connections 15 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CFG2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.BGOFF FALSE 5 | FALSE - 6 | TRUE F5B40 7 | 8 | .config_enum SED.MODE NONE 9 | NONE - 10 | SEDFA F5B32 11 | SEDFB F5B32 12 | 13 | 14 | # Fixed Connections 15 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_EBR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_EBRG0CLK0 3 | G_ECLKCIBB0 F0B0 F1B0 4 | G_JPCLKT20 F0B0 5 | G_JRPLLCLK1 F1B0 6 | 7 | .mux G_EBRG1CLK0 8 | G_ECLKCIBT0 F0B1 F1B1 9 | G_JPCLKT00 F0B1 10 | G_JRPLLCLK1 F1B1 11 | 12 | 13 | # Non-Routing Configuration 14 | 15 | # Fixed Connections 16 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_EBR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_EBRG0CLK0 3 | G_ECLKCIBB0 F0B0 F1B0 4 | G_JPCLKT20 F0B0 5 | G_JRPLLCLK1 F1B0 6 | 7 | .mux G_EBRG1CLK0 8 | G_ECLKCIBT0 F0B1 F1B1 9 | G_JPCLKT00 F0B1 10 | G_JRPLLCLK1 F1B1 11 | 12 | 13 | # Non-Routing Configuration 14 | 15 | # Fixed Connections 16 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_EBR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_EBRG0CLK0 3 | G_ECLKCIBB0 F0B0 F1B0 4 | G_JPCLKT20 F0B0 5 | G_JRPLLCLK1 F1B0 6 | 7 | .mux G_EBRG1CLK0 8 | G_ECLKCIBT0 F0B1 F1B1 9 | G_JPCLKT00 F0B1 10 | G_JRPLLCLK1 F1B1 11 | 12 | 13 | # Non-Routing Configuration 14 | 15 | # Fixed Connections 16 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.VCCIO NONE 5 | 1V2 !F3B0 !F16B0 !F17B0 !F18B0 6 | 1V5 !F3B0 !F16B0 !F17B0 !F18B0 7 | 1V8 F3B0 F16B0 !F17B0 !F18B0 8 | 2V5 !F3B0 !F16B0 F17B0 !F18B0 9 | 3V3 !F3B0 !F16B0 !F17B0 F18B0 10 | NONE !F3B0 !F16B0 !F17B0 !F18B0 11 | 12 | 13 | # Fixed Connections 14 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.VCCIO NONE 5 | 1V2 !F3B0 !F16B0 !F17B0 !F18B0 6 | 1V5 !F3B0 !F16B0 !F17B0 !F18B0 7 | 1V8 F3B0 F16B0 !F17B0 !F18B0 8 | 2V5 !F3B0 !F16B0 F17B0 !F18B0 9 | 3V3 !F3B0 !F16B0 !F17B0 F18B0 10 | NONE !F3B0 !F16B0 !F17B0 !F18B0 11 | 12 | 13 | # Fixed Connections 14 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Project Trellis - Lattice ECP5 Bitstream Documentation 2 | 3 | [TOC] 4 | 5 | This repo contains the bitstream documentation database for Lattice ECP5 6 | devices. 7 | 8 | This documentation was generated using the 9 | [Project Trellis tools](https://github.com/YosysHQ/prjtrellis). 10 | 11 | # License 12 | 13 | These files are released under the very permissive [CC0 1.0 Universal](COPYING). 14 | 15 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR2_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR2_10K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR2_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR2_END_10K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR2_10K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR2_END/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR2_END_10K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum EBR.DP8KC.DATA_WIDTH_A 9 5 | 1 F0B5 F0B6 F0B7 6 | 2 !F0B5 F0B6 F0B7 7 | 4 !F0B5 !F0B6 F0B7 8 | 9 !F0B5 !F0B6 !F0B7 9 | 10 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 18 11 | 1 F0B5 F0B6 F0B7 12 | 18 !F0B5 !F0B6 !F0B7 13 | 2 !F0B5 F0B6 F0B7 14 | 4 !F0B5 !F0B6 F0B7 15 | 9 !F0B5 !F0B6 !F0B7 16 | 17 | 18 | # Fixed Connections 19 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F4B0 6 | ON F4B0 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F3B0 10 | ON F3B0 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F1B1 !F2B1 !F3B1 !F6B0 14 | 1V5 !F1B1 !F2B1 !F3B1 !F6B0 15 | 1V8 !F1B1 !F2B1 F3B1 F6B0 16 | 2V5 !F1B1 F2B1 !F3B1 !F6B0 17 | 3V3 F1B1 !F2B1 !F3B1 !F6B0 18 | NONE !F1B1 !F2B1 !F3B1 !F6B0 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F7B0 22 | ON F7B0 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF7/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B0 6 | ON F5B0 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F6B0 10 | ON F6B0 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F3B0 !F6B1 !F7B1 !F8B1 14 | 1V5 !F3B0 !F6B1 !F7B1 !F8B1 15 | 1V8 F3B0 F6B1 !F7B1 !F8B1 16 | 2V5 !F3B0 !F6B1 F7B1 !F8B1 17 | 3V3 !F3B0 !F6B1 !F7B1 F8B1 18 | NONE !F3B0 !F6B1 !F7B1 !F8B1 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F2B0 22 | ON F2B0 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF2A/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F4B0 6 | ON F4B0 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F3B0 10 | ON F3B0 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F1B1 !F2B1 !F3B1 !F8B2 14 | 1V5 !F1B1 !F2B1 !F3B1 !F8B2 15 | 1V8 !F1B1 !F2B1 F3B1 F8B2 16 | 2V5 !F1B1 F2B1 !F3B1 !F8B2 17 | 3V3 F1B1 !F2B1 !F3B1 !F8B2 18 | NONE !F1B1 !F2B1 !F3B1 !F8B2 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F9B2 22 | ON F9B2 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF7A/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B0 6 | ON F5B0 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F6B0 10 | ON F6B0 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F3B0 !F6B1 !F7B1 !F8B1 14 | 1V5 !F3B0 !F6B1 !F7B1 !F8B1 15 | 1V8 F3B0 F6B1 !F7B1 !F8B1 16 | 2V5 !F3B0 !F6B1 F7B1 !F8B1 17 | 3V3 !F3B0 !F6B1 !F7B1 F8B1 18 | NONE !F3B0 !F6B1 !F7B1 !F8B1 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F2B0 22 | ON F2B0 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B1 6 | ON F5B1 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F6B1 10 | ON F6B1 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F3B1 !F16B1 !F17B1 !F18B1 14 | 1V5 !F3B1 !F16B1 !F17B1 !F18B1 15 | 1V8 F3B1 F16B1 !F17B1 !F18B1 16 | 2V5 !F3B1 !F16B1 F17B1 !F18B1 17 | 3V3 !F3B1 !F16B1 !F17B1 F18B1 18 | NONE !F3B1 !F16B1 !F17B1 !F18B1 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F2B1 22 | ON F2B1 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B1 6 | ON F5B1 7 | 8 | .config_enum BANK.LVDSO OFF 9 | OFF !F6B1 10 | ON F6B1 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1V2 !F3B1 !F16B1 !F17B1 !F18B1 14 | 1V5 !F3B1 !F16B1 !F17B1 !F18B1 15 | 1V8 F3B1 F16B1 !F17B1 !F18B1 16 | 2V5 !F3B1 !F16B1 F17B1 !F18B1 17 | 3V3 !F3B1 !F16B1 !F17B1 F18B1 18 | NONE !F3B1 !F16B1 !F17B1 !F18B1 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F2B1 22 | ON F2B1 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /ECP5/tiledata/DTR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DTR.MODE NONE 5 | DTR F2B0 6 | NONE !F2B0 7 | 8 | 9 | # Fixed Connections 10 | .fixed_conn N1_JF0 N1_JDTROUT0_DTR 11 | 12 | .fixed_conn N1_JF1 N1_JDTROUT1_DTR 13 | 14 | .fixed_conn N1_JF2 N1_JDTROUT2_DTR 15 | 16 | .fixed_conn N1_JF3 N1_JDTROUT3_DTR 17 | 18 | .fixed_conn N1_JF4 N1_JDTROUT4_DTR 19 | 20 | .fixed_conn N1_JF5 N1_JDTROUT5_DTR 21 | 22 | .fixed_conn N1_JF6 N1_JDTROUT6_DTR 23 | 24 | .fixed_conn N1_JF7 N1_JDTROUT7_DTR 25 | 26 | .fixed_conn N1_JSTARTPULSE_DTR N1_JA0 27 | 28 | -------------------------------------------------------------------------------- /MachXO2/tiledata/PIC_B_DUMMY_VREF/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B13 6 | ON F5B13 7 | 8 | .config_enum BANK.INRD OFF 9 | OFF !F4B13 10 | ON F4B13 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1.2 F4B10 F4B11 F5B10 F5B11 F5B14 14 | 1.5 !F4B10 F4B11 F5B10 !F5B11 F5B14 15 | 1.8 !F4B10 !F4B11 F5B10 !F5B11 F5B14 16 | 2.5 !F4B10 !F4B11 !F5B10 !F5B11 F5B14 17 | 3.3 !F4B10 !F4B11 !F5B10 !F5B11 !F5B14 18 | NONE !F4B10 !F4B11 !F5B10 !F5B11 !F5B14 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F4B14 22 | ON F4B14 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /MachXO3/tiledata/PIC_B_DUMMY_VREF/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum BANK.DIFF_REF OFF 5 | OFF !F5B13 6 | ON F5B13 7 | 8 | .config_enum BANK.INRD OFF 9 | OFF !F4B13 10 | ON F4B13 11 | 12 | .config_enum BANK.VCCIO NONE 13 | 1.2 F4B10 F4B11 F5B10 F5B11 F5B14 14 | 1.5 !F4B10 F4B11 F5B10 !F5B11 F5B14 15 | 1.8 !F4B10 !F4B11 F5B10 !F5B11 F5B14 16 | 2.5 !F4B10 !F4B11 !F5B10 !F5B11 F5B14 17 | 3.3 !F4B10 !F4B11 !F5B10 !F5B11 !F5B14 18 | NONE !F4B10 !F4B11 !F5B10 !F5B11 !F5B14 19 | 20 | .config_enum BANK.VREF OFF 21 | OFF !F4B14 22 | ON F4B14 23 | 24 | 25 | # Fixed Connections 26 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER4/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTERB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER4/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER9/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTERB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER9/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTERB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCC0.MODE NONE 5 | DCCA F27B0 6 | NONE - 7 | 8 | .config_enum DCC1.MODE NONE 9 | DCCA F26B0 10 | NONE - 11 | 12 | .config_enum DCC2.MODE NONE 13 | DCCA F25B0 14 | NONE - 15 | 16 | .config_enum DCC3.MODE NONE 17 | DCCA F24B0 18 | NONE - 19 | 20 | .config_enum DCC4.MODE NONE 21 | DCCA F27B1 22 | NONE - 23 | 24 | .config_enum DCC5.MODE NONE 25 | DCCA F26B1 26 | NONE - 27 | 28 | .config_enum DCC6.MODE NONE 29 | DCCA F25B1 30 | NONE - 31 | 32 | .config_enum DCC7.MODE NONE 33 | DCCA F24B1 34 | NONE - 35 | 36 | .config_enum DCM6.MODE NONE 37 | DCMA F28B0 38 | NONE - 39 | 40 | .config_enum DCM7.MODE NONE 41 | DCMA F28B1 42 | NONE - 43 | 44 | 45 | # Fixed Connections 46 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPRXCLKI0 3 | 9400D_N3_PCLKCIBULQ0 F0B0 F1B1 4 | G_JBCDIV10 F0B0 F0B1 F1B1 5 | G_JBCDIV11 F0B0 F1B1 6 | G_JBCDIVX0 F0B0 F1B1 7 | G_JBCDIVX1 F0B0 F1B1 8 | G_JLPLLCLK0 F0B1 F1B1 9 | G_JLPLLCLK1 F1B1 10 | G_JLPLLCLK2 F1B1 11 | G_JLPLLCLK3 F1B1 12 | G_JPCLKT00 F0B0 F0B1 F1B1 13 | G_JPCLKT01 F0B0 F1B1 14 | G_JPCLKT10 F0B0 15 | G_JPCLKT20 F0B0 F1B1 16 | G_JPCLKT21 F0B0 17 | G_JPCLKT30 F0B0 F1B1 18 | G_JPCLKT40 F0B0 F1B1 19 | G_JPCLKT50 F0B0 F1B1 20 | G_JRPLLCLK0 F1B1 21 | G_JRPLLCLK1 F0B0 22 | G_JRPLLCLK2 F0B0 F0B1 F1B1 23 | G_JRPLLCLK3 F0B0 F1B1 24 | G_JTCDIV10 F0B0 F1B1 25 | G_JTCDIV11 F0B0 F1B1 26 | G_JTCDIVX0 F0B0 F1B1 27 | G_JTCDIVX1 F0B0 28 | G_PCLKCIBVIQT0 F0B0 F0B1 F1B1 29 | 30 | 31 | # Non-Routing Configuration 32 | 33 | # Fixed Connections 34 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_EBR8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR3.WID 111100000 5 | F7B0 6 | F5B0 7 | F4B0 8 | F2B0 9 | F1B0 10 | - 11 | - 12 | - 13 | - 14 | 15 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 16 | 1 F55B0 17 | 18 !F55B0 18 | 2 F55B0 19 | 4 F55B0 20 | 9 F55B0 21 | 22 | .config_enum EBR3.GSR ENABLED 23 | DISABLED F41B0 24 | ENABLED !F41B0 25 | 26 | .config_enum EBR3.MODE NONE 27 | DP16KD F19B0 F26B0 F51B0 28 | NONE !F19B0 !F26B0 !F51B0 29 | PDPW16KD F19B0 F26B0 F51B0 30 | 31 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 32 | 1 F55B0 33 | 18 !F55B0 34 | 2 F55B0 35 | 36 !F55B0 36 | 4 F55B0 37 | 9 F55B0 38 | 39 | .config_enum EBR3.REGMODE_B NOREG 40 | NOREG !F54B0 41 | OUTREG F54B0 42 | 43 | .config_enum EBR3.RSTBMUX RSTB 44 | INV F22B0 45 | RSTB !F22B0 46 | 47 | 48 | # Fixed Connections 49 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPRXCLKI0 3 | 7000_N3_PCLKCIBULQ0 F0B0 F1B1 4 | G_JBCDIV10 F0B0 F0B1 F1B1 5 | G_JBCDIV11 F0B0 F1B1 6 | G_JBCDIVX0 F0B0 F1B1 7 | G_JBCDIVX1 F0B0 F1B1 8 | G_JLPLLCLK0 F0B1 F1B1 9 | G_JLPLLCLK1 F1B1 10 | G_JLPLLCLK2 F1B1 11 | G_JLPLLCLK3 F1B1 12 | G_JPCLKT00 F0B0 F0B1 F1B1 13 | G_JPCLKT01 F0B0 F1B1 14 | G_JPCLKT10 F0B0 15 | G_JPCLKT20 F0B0 F1B1 16 | G_JPCLKT21 F0B0 17 | G_JPCLKT30 F0B0 F1B1 18 | G_JPCLKT31 F0B0 F1B1 19 | G_JPCLKT32 F0B0 F1B1 20 | G_JPCLKT40 F0B0 F1B1 21 | G_JPCLKT50 F0B0 F1B1 22 | G_JRPLLCLK0 F1B1 23 | G_JRPLLCLK1 F0B0 24 | G_JRPLLCLK2 F0B0 F0B1 F1B1 25 | G_JRPLLCLK3 F0B0 F1B1 26 | G_JTCDIV10 F0B0 F1B1 27 | G_JTCDIV11 F0B0 F1B1 28 | G_JTCDIVX0 F0B0 F1B1 29 | G_JTCDIVX1 F0B0 30 | G_PCLKCIBVIQT0 F0B0 F0B1 F1B1 31 | 32 | 33 | # Non-Routing Configuration 34 | 35 | # Fixed Connections 36 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_SPINE_UL1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | 53 | # Fixed Connections 54 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LL3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | 53 | # Fixed Connections 54 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER_EBR_CIB_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux L_HPSX0000 3 | G_VPRX0000 F23B0 4 | 5 | .mux L_HPSX0100 6 | G_VPRX0100 F22B0 7 | 8 | .mux L_HPSX0200 9 | G_VPRX0200 F21B0 10 | 11 | .mux L_HPSX0300 12 | G_VPRX0300 F20B0 13 | 14 | .mux L_HPSX0400 15 | G_VPRX0400 F19B0 16 | 17 | .mux L_HPSX0500 18 | G_VPRX0500 F18B0 19 | 20 | .mux L_HPSX0600 21 | G_VPRX0600 F17B0 22 | 23 | .mux L_HPSX0700 24 | G_VPRX0700 F16B0 25 | 26 | .mux R_HPSX0000 27 | G_VPRX0000 F23B1 28 | 29 | .mux R_HPSX0100 30 | G_VPRX0100 F22B1 31 | 32 | .mux R_HPSX0200 33 | G_VPRX0200 F21B1 34 | 35 | .mux R_HPSX0300 36 | G_VPRX0300 F20B1 37 | 38 | .mux R_HPSX0400 39 | G_VPRX0400 F19B1 40 | 41 | .mux R_HPSX0500 42 | G_VPRX0500 F18B1 43 | 44 | .mux R_HPSX0600 45 | G_VPRX0600 F17B1 46 | 47 | .mux R_HPSX0700 48 | G_VPRX0700 F16B1 49 | 50 | 51 | # Non-Routing Configuration 52 | 53 | # Fixed Connections 54 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPRXCLKI0 3 | 6900_N3_PCLKCIBULQ0 F0B0 F1B1 4 | 9400_N3_PCLKCIBULQ0 F0B0 F1B1 5 | G_JBCDIV10 F0B0 F0B1 F1B1 6 | G_JBCDIV11 F0B0 F1B1 7 | G_JBCDIVX0 F0B0 F1B1 8 | G_JBCDIVX1 F0B0 F1B1 9 | G_JLPLLCLK0 F0B1 F1B1 10 | G_JLPLLCLK1 F1B1 11 | G_JLPLLCLK2 F1B1 12 | G_JLPLLCLK3 F1B1 13 | G_JPCLKT00 F0B0 F0B1 F1B1 14 | G_JPCLKT01 F0B0 F1B1 15 | G_JPCLKT10 F0B0 16 | G_JPCLKT20 F0B0 F1B1 17 | G_JPCLKT21 F0B0 18 | G_JPCLKT30 F0B0 F1B1 19 | G_JPCLKT31 F0B0 F1B1 20 | G_JPCLKT32 F0B0 F1B1 21 | G_JPCLKT40 F0B0 F1B1 22 | G_JPCLKT50 F0B0 F1B1 23 | G_JRPLLCLK0 F1B1 24 | G_JRPLLCLK1 F0B0 25 | G_JRPLLCLK2 F0B0 F0B1 F1B1 26 | G_JRPLLCLK3 F0B0 F1B1 27 | G_JTCDIV10 F0B0 F1B1 28 | G_JTCDIV11 F0B0 F1B1 29 | G_JTCDIVX0 F0B0 F1B1 30 | G_JTCDIVX1 F0B0 31 | G_PCLKCIBVIQT0 F0B0 F0B1 F1B1 32 | 33 | 34 | # Non-Routing Configuration 35 | 36 | # Fixed Connections 37 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER_EBR_CIB_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux L_HPSX0000 3 | G_VPRX0000 F23B0 4 | 5 | .mux L_HPSX0100 6 | G_VPRX0100 F22B0 7 | 8 | .mux L_HPSX0200 9 | G_VPRX0200 F21B0 10 | 11 | .mux L_HPSX0300 12 | G_VPRX0300 F20B0 13 | 14 | .mux L_HPSX0400 15 | G_VPRX0400 F19B0 16 | 17 | .mux L_HPSX0500 18 | G_VPRX0500 F18B0 19 | 20 | .mux L_HPSX0600 21 | G_VPRX0600 F17B0 22 | 23 | .mux L_HPSX0700 24 | G_VPRX0700 F16B0 25 | 26 | .mux R_HPSX0000 27 | G_VPRX0000 F23B1 28 | 29 | .mux R_HPSX0100 30 | G_VPRX0100 F22B1 31 | 32 | .mux R_HPSX0200 33 | G_VPRX0200 F21B1 34 | 35 | .mux R_HPSX0300 36 | G_VPRX0300 F20B1 37 | 38 | .mux R_HPSX0400 39 | G_VPRX0400 F19B1 40 | 41 | .mux R_HPSX0500 42 | G_VPRX0500 F18B1 43 | 44 | .mux R_HPSX0600 45 | G_VPRX0600 F17B1 46 | 47 | .mux R_HPSX0700 48 | G_VPRX0700 F16B1 49 | 50 | 51 | # Non-Routing Configuration 52 | 53 | # Fixed Connections 54 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER_EBR_CIB_SP/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux L_HPSX0000 3 | G_VPRX0000 F23B0 4 | 5 | .mux L_HPSX0100 6 | G_VPRX0100 F22B0 7 | 8 | .mux L_HPSX0200 9 | G_VPRX0200 F21B0 10 | 11 | .mux L_HPSX0300 12 | G_VPRX0300 F20B0 13 | 14 | .mux L_HPSX0400 15 | G_VPRX0400 F19B0 16 | 17 | .mux L_HPSX0500 18 | G_VPRX0500 F18B0 19 | 20 | .mux L_HPSX0600 21 | G_VPRX0600 F17B0 22 | 23 | .mux L_HPSX0700 24 | G_VPRX0700 F16B0 25 | 26 | .mux R_HPSX0000 27 | G_VPRX0000 F23B1 28 | 29 | .mux R_HPSX0100 30 | G_VPRX0100 F22B1 31 | 32 | .mux R_HPSX0200 33 | G_VPRX0200 F21B1 34 | 35 | .mux R_HPSX0300 36 | G_VPRX0300 F20B1 37 | 38 | .mux R_HPSX0400 39 | G_VPRX0400 F19B1 40 | 41 | .mux R_HPSX0500 42 | G_VPRX0500 F18B1 43 | 44 | .mux R_HPSX0600 45 | G_VPRX0600 F17B1 46 | 47 | .mux R_HPSX0700 48 | G_VPRX0700 F16B1 49 | 50 | 51 | # Non-Routing Configuration 52 | 53 | # Fixed Connections 54 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_EBR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR0.WID 000000000 5 | F35B0 6 | F33B0 7 | F32B0 8 | F29B0 9 | F28B0 10 | F26B0 11 | F25B0 12 | F12B0 13 | F22B0 14 | 15 | .config_enum EBR0.ADA1MUX ADA1 16 | ADA1 !F23B0 17 | INV F23B0 18 | 19 | .config_enum EBR0.ASYNC_RESET_RELEASE SYNC 20 | ASYNC F20B0 21 | SYNC !F20B0 22 | 23 | .config_enum EBR0.DP16KD.DATA_WIDTH_B 18 24 | 1 F81B0 25 | 18 !F81B0 26 | 2 F81B0 27 | 4 F81B0 28 | 9 F81B0 29 | 30 | .config_enum EBR0.GSR ENABLED 31 | DISABLED F67B0 32 | ENABLED !F67B0 33 | 34 | .config_enum EBR0.MODE NONE 35 | DP16KD F3B0 F46B0 F54B0 F77B0 36 | NONE !F3B0 !F46B0 !F54B0 !F77B0 37 | PDPW16KD F3B0 F46B0 F54B0 F77B0 38 | 39 | .config_enum EBR0.PDPW16KD.DATA_WIDTH_R 36 40 | 1 F81B0 41 | 18 !F81B0 42 | 2 F81B0 43 | 36 !F81B0 44 | 4 F81B0 45 | 9 F81B0 46 | 47 | .config_enum EBR0.REGMODE_A NOREG 48 | NOREG !F15B0 49 | OUTREG F15B0 50 | 51 | .config_enum EBR0.REGMODE_B NOREG 52 | NOREG !F80B0 53 | OUTREG F80B0 54 | 55 | .config_enum EBR0.RSTAMUX RSTA 56 | INV F13B0 57 | RSTA !F13B0 58 | 59 | .config_enum EBR0.RSTBMUX RSTB 60 | INV F48B0 61 | RSTB !F48B0 62 | 63 | 64 | # Fixed Connections 65 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_LL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux S13W2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | S13W2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_LLDDRDEL S13W2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 S13W2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 S13W2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 S13W2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 S13W2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 S13W2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 S13W2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 S13W2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 S13W2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 S13W2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 S13W2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn S13W2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn S13W2_JCLK_DDRDLL S13W2_JDDRDLLCLK 48 | 49 | .fixed_conn S13W2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn S13W2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn S13W2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_LR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux S13E2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | S13E2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_LRDDRDEL S13E2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 S13E2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 S13E2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 S13E2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 S13E2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 S13E2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 S13E2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 S13E2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 S13E2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 S13E2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 S13E2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn S13E2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn S13E2_JCLK_DDRDLL S13E2_JDDRDLLCLK 48 | 49 | .fixed_conn S13E2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn S13E2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn S13E2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_UL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N10W2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | N10W2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_ULDDRDEL N10W2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 N10W2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 N10W2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 N10W2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 N10W2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 N10W2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 N10W2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 N10W2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 N10W2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 N10W2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 N10W2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn N10W2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn N10W2_JCLK_DDRDLL N10W2_JDDRDLLCLK 48 | 49 | .fixed_conn N10W2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn N10W2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn N10W2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_ULA/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N13W2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | N13W2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_ULDDRDEL N13W2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 N13W2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 N13W2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 N13W2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 N13W2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 N13W2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 N13W2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 N13W2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 N13W2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 N13W2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 N13W2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn N13W2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn N13W2_JCLK_DDRDLL N13W2_JDDRDLLCLK 48 | 49 | .fixed_conn N13W2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn N13W2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn N13W2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_UR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N10E2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | N10E2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_URDDRDEL N10E2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 N10E2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 N10E2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 N10E2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 N10E2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 N10E2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 N10E2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 N10E2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 N10E2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 N10E2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 N10E2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn N10E2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn N10E2_JCLK_DDRDLL N10E2_JDDRDLLCLK 48 | 49 | .fixed_conn N10E2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn N10E2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn N10E2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DDRDLL_URA/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N13E2_JDDRDLLCLK 3 | BNK_ECLK0 F9B0 4 | BNK_ECLK1 F8B0 F9B0 5 | N13E2_JCIBCLK0 F8B0 6 | 7 | 8 | # Non-Routing Configuration 9 | .config_enum DDRDLL.FORCE_MAX_DELAY 10 | NO F13B0 11 | YES F15B0 12 | 13 | .config_enum DDRDLL.GSR ENABLED 14 | DISABLED F12B0 15 | ENABLED - 16 | 17 | .config_enum DDRDLL.MODE NONE 18 | DDRDLLA F14B0 F16B0 19 | NONE - 20 | 21 | 22 | # Fixed Connections 23 | .fixed_conn G_URDDRDEL N13E2_DDRDEL_DDRDLL 24 | 25 | .fixed_conn JF0 N13E2_JDCNTL0_DDRDLL 26 | 27 | .fixed_conn JF1 N13E2_JDCNTL1_DDRDLL 28 | 29 | .fixed_conn JF2 N13E2_JDCNTL2_DDRDLL 30 | 31 | .fixed_conn JF3 N13E2_JDCNTL3_DDRDLL 32 | 33 | .fixed_conn JF4 N13E2_JDCNTL4_DDRDLL 34 | 35 | .fixed_conn JF5 N13E2_JDCNTL5_DDRDLL 36 | 37 | .fixed_conn JF6 N13E2_JDCNTL6_DDRDLL 38 | 39 | .fixed_conn JF7 N13E2_JDCNTL7_DDRDLL 40 | 41 | .fixed_conn JQ0 N13E2_JLOCK_DDRDLL 42 | 43 | .fixed_conn JQ1 N13E2_JDIVOSC_DDRDLL 44 | 45 | .fixed_conn N13E2_JCIBCLK0 JCLK0 46 | 47 | .fixed_conn N13E2_JCLK_DDRDLL N13E2_JDDRDLLCLK 48 | 49 | .fixed_conn N13E2_JFREEZE_DDRDLL JA0 50 | 51 | .fixed_conn N13E2_JRST_DDRDLL JLSR0 52 | 53 | .fixed_conn N13E2_JUDDCNTLN_DDRDLL JB0 54 | 55 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU7/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N1W9_JSERDESREFCLK0 3 | W7_JREFCLKO_EXTREF F59B1 4 | 5 | .mux W7_CH0_RX_REFCLK 6 | W7_RXREFCLK0 F58B1 7 | 8 | .mux W7_CH1_RX_REFCLK 9 | W7_RXREFCLK1 F58B1 10 | 11 | .mux W7_D_REFCLKI 12 | W7_JTXREFCLKCIB F63B1 13 | 14 | 15 | # Non-Routing Configuration 16 | .config DCU.D_BITCLK_FROM_ND_EN 0 17 | F95B1 18 | 19 | .config DCU.D_BITCLK_LOCAL_EN 0 20 | F93B1 21 | 22 | .config DCU.D_BITCLK_ND_EN 0 23 | F94B1 24 | 25 | .config DCU.D_BUS8BIT_SEL 0 26 | F72B1 27 | 28 | .config DCU.D_CDR_LOL_SET 00 29 | F74B1 30 | F75B1 31 | 32 | .config DCU.D_PLL_LOL_SET 00 33 | F85B1 34 | F86B1 35 | 36 | .config DCU.D_REFCK_MODE 000 37 | F66B1 38 | F67B1 39 | F73B1 40 | 41 | .config DCU.D_RG_EN 0 42 | F87B1 43 | 44 | .config DCU.D_RG_SET 00 45 | F88B1 46 | F89B1 47 | 48 | .config DCU.D_SETPLLRC 000000 49 | F76B1 50 | F77B1 51 | F78B1 52 | F79B1 53 | F80B1 54 | F81B1 55 | 56 | .config DCU.D_SYNC_LOCAL_EN 0 57 | F96B1 58 | 59 | .config DCU.D_SYNC_ND_EN 0 60 | F97B1 61 | 62 | .config DCU.D_TX_VCO_CK_DIV 000 63 | F82B1 64 | F83B1 65 | F84B1 66 | 67 | .config EXTREF.REFCK_DCBIAS_EN 0 68 | F62B1 69 | 70 | .config EXTREF.REFCK_RTERM 0 71 | F61B1 72 | 73 | 74 | # Fixed Connections 75 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_CMUX_LL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR3.WID 111100000 5 | F7B0 6 | F5B0 7 | F4B0 8 | F2B0 9 | F1B0 10 | - 11 | - 12 | - 13 | - 14 | 15 | .config_enum DCS1.DCSMODE NEG 16 | CLK0 F70B0 F72B0 F75B0 F77B0 17 | CLK0_HIGH F72B0 F73B0 F77B0 F78B0 18 | CLK0_LOW F72B0 F77B0 19 | CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 20 | CLK1_HIGH F71B0 F73B0 F76B0 F78B0 21 | CLK1_LOW F71B0 F76B0 22 | HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 23 | LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 24 | NEG - 25 | NONE - 26 | POS F73B0 F78B0 27 | 28 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 29 | 1 F55B0 30 | 18 !F55B0 31 | 2 F55B0 32 | 4 F55B0 33 | 9 F55B0 34 | 35 | .config_enum EBR3.GSR ENABLED 36 | DISABLED F41B0 37 | ENABLED !F41B0 38 | 39 | .config_enum EBR3.MODE NONE 40 | DP16KD F19B0 F26B0 F51B0 41 | NONE !F19B0 !F26B0 !F51B0 42 | PDPW16KD F19B0 F26B0 F51B0 43 | 44 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 45 | 1 F55B0 46 | 18 !F55B0 47 | 2 F55B0 48 | 36 !F55B0 49 | 4 F55B0 50 | 9 F55B0 51 | 52 | .config_enum EBR3.REGMODE_B NOREG 53 | NOREG !F54B0 54 | OUTREG F54B0 55 | 56 | .config_enum EBR3.RSTBMUX RSTB 57 | INV F22B0 58 | RSTB !F22B0 59 | 60 | 61 | # Fixed Connections 62 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_CMUX_LL_25K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR3.WID 111100000 5 | F7B0 6 | F5B0 7 | F4B0 8 | F2B0 9 | F1B0 10 | - 11 | - 12 | - 13 | - 14 | 15 | .config_enum DCS1.DCSMODE NEG 16 | CLK0 F70B0 F72B0 F75B0 F77B0 17 | CLK0_HIGH F72B0 F73B0 F77B0 F78B0 18 | CLK0_LOW F72B0 F77B0 19 | CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 20 | CLK1_HIGH F71B0 F73B0 F76B0 F78B0 21 | CLK1_LOW F71B0 F76B0 22 | HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 23 | LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 24 | NEG - 25 | NONE - 26 | POS F73B0 F78B0 27 | 28 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 29 | 1 F55B0 30 | 18 !F55B0 31 | 2 F55B0 32 | 4 F55B0 33 | 9 F55B0 34 | 35 | .config_enum EBR3.GSR ENABLED 36 | DISABLED F41B0 37 | ENABLED !F41B0 38 | 39 | .config_enum EBR3.MODE NONE 40 | DP16KD F19B0 F26B0 F51B0 41 | NONE !F19B0 !F26B0 !F51B0 42 | PDPW16KD F19B0 F26B0 F51B0 43 | 44 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 45 | 1 F55B0 46 | 18 !F55B0 47 | 2 F55B0 48 | 36 !F55B0 49 | 4 F55B0 50 | 9 F55B0 51 | 52 | .config_enum EBR3.REGMODE_B NOREG 53 | NOREG !F54B0 54 | OUTREG F54B0 55 | 56 | .config_enum EBR3.RSTBMUX RSTB 57 | INV F22B0 58 | RSTB !F22B0 59 | 60 | 61 | # Fixed Connections 62 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_DSP8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux W3_JMULTA0 3 | W3_JPO0 F54B0 4 | 5 | .mux W3_JMULTA1 6 | W3_JPO1 F54B0 7 | 8 | .mux W3_JMULTA10 9 | W3_JPO10 F54B0 10 | 11 | .mux W3_JMULTA11 12 | W3_JPO11 F54B0 13 | 14 | .mux W3_JMULTA12 15 | W3_JPO12 F54B0 16 | 17 | .mux W3_JMULTA13 18 | W3_JPO13 F54B0 19 | 20 | .mux W3_JMULTA14 21 | W3_JPO14 F54B0 22 | 23 | .mux W3_JMULTA15 24 | W3_JPO15 F54B0 25 | 26 | .mux W3_JMULTA16 27 | W3_JPO16 F54B0 28 | 29 | .mux W3_JMULTA17 30 | W3_JPO17 F54B0 31 | 32 | .mux W3_JMULTA2 33 | W3_JPO2 F54B0 34 | 35 | .mux W3_JMULTA3 36 | W3_JPO3 F54B0 37 | 38 | .mux W3_JMULTA4 39 | W3_JPO4 F54B0 40 | 41 | .mux W3_JMULTA5 42 | W3_JPO5 F54B0 43 | 44 | .mux W3_JMULTA6 45 | W3_JPO6 F54B0 46 | 47 | .mux W3_JMULTA7 48 | W3_JPO7 F54B0 49 | 50 | .mux W3_JMULTA8 51 | W3_JPO8 F54B0 52 | 53 | .mux W3_JMULTA9 54 | W3_JPO9 F54B0 55 | 56 | 57 | # Non-Routing Configuration 58 | .config_enum ALU54_7.MODE NONE 59 | ALU54B F55B0 F61B0 60 | NONE - 61 | 62 | .config_enum MULT18_5.MODE NONE 63 | MULT18X18D F56B0 F57B0 64 | NONE - 65 | 66 | .config_enum MULT18_5.REG_INPUTB_CLK CLK3 67 | CLK0 - 68 | CLK1 - 69 | CLK2 - 70 | CLK3 - 71 | NONE F55B0 F61B0 72 | 73 | .config_enum MULT18_5.SOURCEB_MODE 74 | B_C_DYNAMIC F51B0 75 | B_SHIFT F60B0 76 | C_SHIFT F59B0 F60B0 77 | HIGHSPEED F51B0 F59B0 78 | 79 | 80 | # Fixed Connections 81 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_EBR3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR1.WID 000000000 5 | F62B0 6 | F59B0 7 | F58B0 8 | F56B0 9 | F55B0 10 | F51B0 11 | F50B0 12 | F39B0 13 | F48B0 14 | 15 | .config_enum EBR1.ADA1MUX ADA1 16 | ADA1 !F49B0 17 | INV F49B0 18 | 19 | .config_enum EBR1.ADA2MUX ADA2 20 | ADA2 !F5B0 21 | INV F5B0 22 | 23 | .config_enum EBR1.ASYNC_RESET_RELEASE SYNC 24 | ASYNC F46B0 25 | SYNC !F46B0 26 | 27 | .config_enum EBR1.CEBMUX CEB 28 | CEB !F17B0 29 | INV F17B0 30 | 31 | .config_enum EBR1.CLKBMUX CLKB 32 | CLKB !F24B0 33 | INV F24B0 34 | 35 | .config_enum EBR1.DP16KD.WRITEMODE_A WRITETHROUGH 36 | NORMAL !F22B0 37 | READBEFOREWRITE F22B0 38 | WRITETHROUGH !F22B0 39 | 40 | .config_enum EBR1.GSR ENABLED 41 | DISABLED F94B0 42 | ENABLED !F94B0 43 | 44 | .config_enum EBR1.MODE NONE 45 | DP16KD !F15B0 F31B0 F72B0 F79B0 F104B0 46 | NONE !F15B0 !F31B0 !F72B0 !F79B0 !F104B0 47 | PDPW16KD F15B0 F31B0 F72B0 F79B0 F104B0 48 | 49 | .config_enum EBR1.OCEBMUX OCEB 50 | INV F2B0 51 | OCEB !F2B0 52 | 53 | .config_enum EBR1.REGMODE_A NOREG 54 | NOREG !F42B0 55 | OUTREG F42B0 56 | 57 | .config_enum EBR1.RESETMODE SYNC 58 | ASYNC F25B0 59 | SYNC !F25B0 60 | 61 | .config_enum EBR1.RSTAMUX RSTA 62 | INV F40B0 63 | RSTA !F40B0 64 | 65 | .config_enum EBR1.RSTBMUX RSTB 66 | INV F74B0 67 | RSTB !F74B0 68 | 69 | .config_enum EBR1.WEBMUX WEB 70 | INV F8B0 71 | WEB !F8B0 72 | 73 | 74 | # Fixed Connections 75 | -------------------------------------------------------------------------------- /ECP5/tiledata/BMID_2V/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_BDCC10CLKI 3 | G_JBLQPCLKCIB1 !F25B0 F27B0 4 | N1W1_JJTCK F25B0 F27B0 5 | 6 | .mux G_BDCC11CLKI 7 | G_JBLQPCLKCIB0 !F28B0 !F29B0 !F30B0 F31B0 8 | G_JLLMPCLKCIB1 F28B0 F29B0 F30B0 !F31B0 9 | G_JSEDCLKOUT !F28B0 F29B0 !F30B0 F31B0 10 | 11 | .mux G_BDCC12CLKI 12 | G_JBLQPCLKCIB0 !F33B0 F35B0 13 | G_JSEDCLKOUT F33B0 F35B0 14 | 15 | .mux G_BDCC13CLKI 16 | G_JBLQPCLKCIB1 !F36B0 !F37B0 !F38B0 F39B0 17 | G_JLRMPCLKCIB1 F36B0 F37B0 F38B0 !F39B0 18 | N1W1_JJTCK !F36B0 F37B0 !F38B0 F39B0 19 | 20 | .mux G_BDCC14CLKI 21 | G_JBRQPCLKCIB0 !F40B0 !F41B0 !F42B0 F43B0 22 | G_JLLMPCLKCIB1 F40B0 F41B0 F42B0 !F43B0 23 | 24 | .mux G_BDCC15CLKI 25 | G_JBRQPCLKCIB1 F47B0 26 | 27 | .mux G_BDCC8CLKI 28 | G_JBRQPCLKCIB1 !F16B0 !F17B0 !F18B0 F19B0 29 | G_JLRMPCLKCIB1 F16B0 F17B0 F18B0 !F19B0 30 | 31 | .mux G_BDCC9CLKI 32 | G_JBRQPCLKCIB0 F23B0 33 | G_JLLMPCLKCIB3 F20B0 F21B0 F22B0 !F23B0 34 | 35 | 36 | # Non-Routing Configuration 37 | .config_enum DCC_B10.MODE NONE 38 | DCCA F10B0 39 | NONE - 40 | 41 | .config_enum DCC_B11.MODE NONE 42 | DCCA F11B0 43 | NONE - 44 | 45 | .config_enum DCC_B12.MODE NONE 46 | DCCA F12B0 47 | NONE - 48 | 49 | .config_enum DCC_B13.MODE NONE 50 | DCCA F13B0 51 | NONE - 52 | 53 | .config_enum DCC_B14.MODE NONE 54 | DCCA F14B0 55 | NONE - 56 | 57 | .config_enum DCC_B15.MODE NONE 58 | DCCA F15B0 59 | NONE - 60 | 61 | .config_enum DCC_B8.MODE NONE 62 | DCCA F8B0 63 | NONE - 64 | 65 | .config_enum DCC_B9.MODE NONE 66 | DCCA F9B0 67 | NONE - 68 | 69 | 70 | # Fixed Connections 71 | -------------------------------------------------------------------------------- /ECP5/LFE5U-12F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 31, 7 | "y1": 25 8 | }, 9 | "UR": { 10 | "x0": 32, 11 | "y0": 0, 12 | "x1": 72, 13 | "y1": 25 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 26, 18 | "x1": 31, 19 | "y1": 50 20 | }, 21 | "LR": { 22 | "x0": 32, 23 | "y0": 26, 24 | "x1": 72, 25 | "y1": 50 26 | } 27 | }, 28 | "taps": { 29 | "C4": { 30 | "lx0": 0, 31 | "lx1": 3, 32 | "rx0": 4, 33 | "rx1": 12 34 | }, 35 | "C22": { 36 | "lx0": 13, 37 | "lx1": 21, 38 | "rx0": 22, 39 | "rx1": 31 40 | }, 41 | "C42": { 42 | "lx0": 32, 43 | "lx1": 41, 44 | "rx0": 42, 45 | "rx1": 50 46 | }, 47 | "C60": { 48 | "lx0": 51, 49 | "lx1": 59, 50 | "rx0": 60, 51 | "rx1": 72 52 | } 53 | }, 54 | "spines": { 55 | "UL4": { 56 | "x": 3, 57 | "y": 13 58 | }, 59 | "LL4": { 60 | "x": 3, 61 | "y": 37 62 | }, 63 | "UL22": { 64 | "x": 21, 65 | "y": 13 66 | }, 67 | "LL22": { 68 | "x": 21, 69 | "y": 37 70 | }, 71 | "UR42": { 72 | "x": 41, 73 | "y": 13 74 | }, 75 | "LR42": { 76 | "x": 41, 77 | "y": 37 78 | }, 79 | "UR60": { 80 | "x": 59, 81 | "y": 13 82 | }, 83 | "LR60": { 84 | "x": 59, 85 | "y": 37 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5U-25F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 31, 7 | "y1": 25 8 | }, 9 | "UR": { 10 | "x0": 32, 11 | "y0": 0, 12 | "x1": 72, 13 | "y1": 25 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 26, 18 | "x1": 31, 19 | "y1": 50 20 | }, 21 | "LR": { 22 | "x0": 32, 23 | "y0": 26, 24 | "x1": 72, 25 | "y1": 50 26 | } 27 | }, 28 | "taps": { 29 | "C4": { 30 | "lx0": 0, 31 | "lx1": 3, 32 | "rx0": 4, 33 | "rx1": 12 34 | }, 35 | "C22": { 36 | "lx0": 13, 37 | "lx1": 21, 38 | "rx0": 22, 39 | "rx1": 31 40 | }, 41 | "C42": { 42 | "lx0": 32, 43 | "lx1": 41, 44 | "rx0": 42, 45 | "rx1": 50 46 | }, 47 | "C60": { 48 | "lx0": 51, 49 | "lx1": 59, 50 | "rx0": 60, 51 | "rx1": 72 52 | } 53 | }, 54 | "spines": { 55 | "UL4": { 56 | "x": 3, 57 | "y": 13 58 | }, 59 | "LL4": { 60 | "x": 3, 61 | "y": 37 62 | }, 63 | "UL22": { 64 | "x": 21, 65 | "y": 13 66 | }, 67 | "LL22": { 68 | "x": 21, 69 | "y": 37 70 | }, 71 | "UR42": { 72 | "x": 41, 73 | "y": 13 74 | }, 75 | "LR42": { 76 | "x": 41, 77 | "y": 37 78 | }, 79 | "UR60": { 80 | "x": 59, 81 | "y": 13 82 | }, 83 | "LR60": { 84 | "x": 59, 85 | "y": 37 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5UM-25F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 31, 7 | "y1": 25 8 | }, 9 | "UR": { 10 | "x0": 32, 11 | "y0": 0, 12 | "x1": 72, 13 | "y1": 25 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 26, 18 | "x1": 31, 19 | "y1": 50 20 | }, 21 | "LR": { 22 | "x0": 32, 23 | "y0": 26, 24 | "x1": 72, 25 | "y1": 50 26 | } 27 | }, 28 | "taps": { 29 | "C4": { 30 | "lx0": 0, 31 | "lx1": 3, 32 | "rx0": 4, 33 | "rx1": 12 34 | }, 35 | "C22": { 36 | "lx0": 13, 37 | "lx1": 21, 38 | "rx0": 22, 39 | "rx1": 31 40 | }, 41 | "C42": { 42 | "lx0": 32, 43 | "lx1": 41, 44 | "rx0": 42, 45 | "rx1": 50 46 | }, 47 | "C60": { 48 | "lx0": 51, 49 | "lx1": 59, 50 | "rx0": 60, 51 | "rx1": 72 52 | } 53 | }, 54 | "spines": { 55 | "UL4": { 56 | "x": 3, 57 | "y": 13 58 | }, 59 | "LL4": { 60 | "x": 3, 61 | "y": 37 62 | }, 63 | "UL22": { 64 | "x": 21, 65 | "y": 13 66 | }, 67 | "LL22": { 68 | "x": 21, 69 | "y": 37 70 | }, 71 | "UR42": { 72 | "x": 41, 73 | "y": 13 74 | }, 75 | "LR42": { 76 | "x": 41, 77 | "y": 37 78 | }, 79 | "UR60": { 80 | "x": 59, 81 | "y": 13 82 | }, 83 | "LR60": { 84 | "x": 59, 85 | "y": 37 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5UM5G-25F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 31, 7 | "y1": 25 8 | }, 9 | "UR": { 10 | "x0": 32, 11 | "y0": 0, 12 | "x1": 72, 13 | "y1": 25 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 26, 18 | "x1": 31, 19 | "y1": 50 20 | }, 21 | "LR": { 22 | "x0": 32, 23 | "y0": 26, 24 | "x1": 72, 25 | "y1": 50 26 | } 27 | }, 28 | "taps": { 29 | "C4": { 30 | "lx0": 0, 31 | "lx1": 3, 32 | "rx0": 4, 33 | "rx1": 12 34 | }, 35 | "C22": { 36 | "lx0": 13, 37 | "lx1": 21, 38 | "rx0": 22, 39 | "rx1": 31 40 | }, 41 | "C42": { 42 | "lx0": 32, 43 | "lx1": 41, 44 | "rx0": 42, 45 | "rx1": 50 46 | }, 47 | "C60": { 48 | "lx0": 51, 49 | "lx1": 59, 50 | "rx0": 60, 51 | "rx1": 72 52 | } 53 | }, 54 | "spines": { 55 | "UL4": { 56 | "x": 3, 57 | "y": 13 58 | }, 59 | "LL4": { 60 | "x": 3, 61 | "y": 37 62 | }, 63 | "UL22": { 64 | "x": 21, 65 | "y": 13 66 | }, 67 | "LL22": { 68 | "x": 21, 69 | "y": 37 70 | }, 71 | "UR42": { 72 | "x": 41, 73 | "y": 13 74 | }, 75 | "LR42": { 76 | "x": 41, 77 | "y": 37 78 | }, 79 | "UR60": { 80 | "x": 59, 81 | "y": 13 82 | }, 83 | "LR60": { 84 | "x": 59, 85 | "y": 37 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5U-45F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 40, 7 | "y1": 34 8 | }, 9 | "UR": { 10 | "x0": 41, 11 | "y0": 0, 12 | "x1": 90, 13 | "y1": 34 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 35, 18 | "x1": 40, 19 | "y1": 71 20 | }, 21 | "LR": { 22 | "x0": 41, 23 | "y0": 35, 24 | "x1": 90, 25 | "y1": 71 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 40 40 | }, 41 | "C51": { 42 | "lx0": 41, 43 | "lx1": 50, 44 | "rx0": 51, 45 | "rx1": 63 46 | }, 47 | "C78": { 48 | "lx0": 64, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 90 52 | } 53 | }, 54 | "spines": { 55 | "UL13": { 56 | "x": 12, 57 | "y": 10 58 | }, 59 | "LL13": { 60 | "x": 12, 61 | "y": 58 62 | }, 63 | "UL31": { 64 | "x": 30, 65 | "y": 10 66 | }, 67 | "LL31": { 68 | "x": 30, 69 | "y": 58 70 | }, 71 | "UR51": { 72 | "x": 50, 73 | "y": 10 74 | }, 75 | "LR51": { 76 | "x": 50, 77 | "y": 58 78 | }, 79 | "UR78": { 80 | "x": 77, 81 | "y": 10 82 | }, 83 | "LR78": { 84 | "x": 77, 85 | "y": 58 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5UM-45F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 40, 7 | "y1": 34 8 | }, 9 | "UR": { 10 | "x0": 41, 11 | "y0": 0, 12 | "x1": 90, 13 | "y1": 34 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 35, 18 | "x1": 40, 19 | "y1": 71 20 | }, 21 | "LR": { 22 | "x0": 41, 23 | "y0": 35, 24 | "x1": 90, 25 | "y1": 71 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 40 40 | }, 41 | "C51": { 42 | "lx0": 41, 43 | "lx1": 50, 44 | "rx0": 51, 45 | "rx1": 63 46 | }, 47 | "C78": { 48 | "lx0": 64, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 90 52 | } 53 | }, 54 | "spines": { 55 | "UL13": { 56 | "x": 12, 57 | "y": 10 58 | }, 59 | "LL13": { 60 | "x": 12, 61 | "y": 58 62 | }, 63 | "UL31": { 64 | "x": 30, 65 | "y": 10 66 | }, 67 | "LL31": { 68 | "x": 30, 69 | "y": 58 70 | }, 71 | "UR51": { 72 | "x": 50, 73 | "y": 10 74 | }, 75 | "LR51": { 76 | "x": 50, 77 | "y": 58 78 | }, 79 | "UR78": { 80 | "x": 77, 81 | "y": 10 82 | }, 83 | "LR78": { 84 | "x": 77, 85 | "y": 58 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/LFE5UM5G-45F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 40, 7 | "y1": 34 8 | }, 9 | "UR": { 10 | "x0": 41, 11 | "y0": 0, 12 | "x1": 90, 13 | "y1": 34 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 35, 18 | "x1": 40, 19 | "y1": 71 20 | }, 21 | "LR": { 22 | "x0": 41, 23 | "y0": 35, 24 | "x1": 90, 25 | "y1": 71 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 40 40 | }, 41 | "C51": { 42 | "lx0": 41, 43 | "lx1": 50, 44 | "rx0": 51, 45 | "rx1": 63 46 | }, 47 | "C78": { 48 | "lx0": 64, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 90 52 | } 53 | }, 54 | "spines": { 55 | "UL13": { 56 | "x": 12, 57 | "y": 10 58 | }, 59 | "LL13": { 60 | "x": 12, 61 | "y": 58 62 | }, 63 | "UL31": { 64 | "x": 30, 65 | "y": 10 66 | }, 67 | "LL31": { 68 | "x": 30, 69 | "y": 58 70 | }, 71 | "UR51": { 72 | "x": 50, 73 | "y": 10 74 | }, 75 | "LR51": { 76 | "x": 50, 77 | "y": 58 78 | }, 79 | "UR78": { 80 | "x": 77, 81 | "y": 10 82 | }, 83 | "LR78": { 84 | "x": 77, 85 | "y": 58 86 | } 87 | } 88 | } 89 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LL0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LL1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LL2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LR0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_LR2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UL0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UL1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UL2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UR0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/EBR_SPINE_UR2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | 51 | # Non-Routing Configuration 52 | .config EBR3.WID 111100000 53 | F7B0 54 | F5B0 55 | F4B0 56 | F2B0 57 | F1B0 58 | - 59 | - 60 | - 61 | - 62 | 63 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 64 | 1 F55B0 65 | 18 !F55B0 66 | 2 F55B0 67 | 4 F55B0 68 | 9 F55B0 69 | 70 | .config_enum EBR3.GSR ENABLED 71 | DISABLED F41B0 72 | ENABLED !F41B0 73 | 74 | .config_enum EBR3.MODE NONE 75 | DP16KD F19B0 F26B0 F51B0 76 | NONE !F19B0 !F26B0 !F51B0 77 | PDPW16KD F19B0 F26B0 F51B0 78 | 79 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 80 | 1 F55B0 81 | 18 !F55B0 82 | 2 F55B0 83 | 36 !F55B0 84 | 4 F55B0 85 | 9 F55B0 86 | 87 | .config_enum EBR3.REGMODE_B NOREG 88 | NOREG !F54B0 89 | OUTREG F54B0 90 | 91 | .config_enum EBR3.RSTBMUX RSTB 92 | INV F22B0 93 | RSTB !F22B0 94 | 95 | 96 | # Fixed Connections 97 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_CMUX_UL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum DCS0.DCSMODE NEG 5 | CLK0 F70B0 F72B0 F75B0 F77B0 6 | CLK0_HIGH F72B0 F73B0 F77B0 F78B0 7 | CLK0_LOW F72B0 F77B0 8 | CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 9 | CLK1_HIGH F71B0 F73B0 F76B0 F78B0 10 | CLK1_LOW F71B0 F76B0 11 | HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 12 | LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 13 | NEG - 14 | NONE - 15 | POS F73B0 F78B0 16 | 17 | 18 | # Fixed Connections 19 | .fixed_conn G_CLK0_DCS0 G_DCS0CLK0 20 | 21 | .fixed_conn G_CLK0_DCS1 G_DCS1CLK0 22 | 23 | .fixed_conn G_CLK1_DCS0 G_DCS0CLK1 24 | 25 | .fixed_conn G_CLK1_DCS1 G_DCS1CLK1 26 | 27 | .fixed_conn G_DCS0 G_DCSOUT_DCS0 28 | 29 | .fixed_conn G_DCS1 G_DCSOUT_DCS1 30 | 31 | .fixed_conn G_JCE_DCCBL 25K_S24_JA0 32 | 33 | .fixed_conn G_JCE_DCCBR 25K_S24E1_JA0 34 | 35 | .fixed_conn G_JCE_DCCTL 25K_JA0 36 | 37 | .fixed_conn G_JCE_DCCTR 25K_E1_JA0 38 | 39 | .fixed_conn G_JCLKI_DCCBL 25K_S24_JD7 40 | 41 | .fixed_conn G_JCLKI_DCCBR 25K_S24E1_JD7 42 | 43 | .fixed_conn G_JCLKI_DCCTL 25K_JD7 44 | 45 | .fixed_conn G_JCLKI_DCCTR 25K_E1_JD7 46 | 47 | .fixed_conn G_JMODESEL_DCS0 25K_JC0 48 | 49 | .fixed_conn G_JMODESEL_DCS1 25K_S24_JC0 50 | 51 | .fixed_conn G_JSEL0_DCS0 25K_JA3 52 | 53 | .fixed_conn G_JSEL0_DCS1 25K_S24_JA3 54 | 55 | .fixed_conn G_JSEL1_DCS0 25K_JA4 56 | 57 | .fixed_conn G_JSEL1_DCS1 25K_S24_JA4 58 | 59 | .fixed_conn G_LLCPCLKCIB0 G_CLKO_DCCBL 60 | 61 | .fixed_conn G_LRCPCLKCIB0 G_CLKO_DCCBR 62 | 63 | .fixed_conn G_ULCPCLKCIB0 G_CLKO_DCCTL 64 | 65 | .fixed_conn G_URCPCLKCIB0 G_CLKO_DCCTR 66 | 67 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CENTER6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VSRX0000 3 | G_JSNETCIBR0 F28B0 4 | G_JSNETCIBT0 F28B1 5 | 6 | .mux G_VSRX0100 7 | G_JPCLKT40 F25B0 8 | G_JSNETCIBB0 F27B1 9 | G_JSNETCIBL0 F27B0 10 | G_JSNETCIBMID0 F26B0 11 | G_JSNETCIBMID5 F25B1 12 | G_JSNETCIBMID6 F26B1 13 | G_JSNETCIBR1 F24B0 14 | G_JSNETCIBT1 F24B1 15 | 16 | .mux G_VSRX0200 17 | G_JPCLKT10 F23B1 18 | G_JSNETCIBL1 F23B0 19 | G_JSNETCIBMID1 F22B0 20 | G_JSNETCIBMID2 F21B0 21 | G_JSNETCIBMID4 F21B1 22 | G_JSNETCIBMID7 F22B1 23 | G_JSNETCIBR0 F20B0 24 | G_JSNETCIBT0 F20B1 25 | 26 | .mux G_VSRX0300 27 | G_JPCLKT50 F19B0 28 | G_JSNETCIBB0 F19B1 29 | G_JSNETCIBMID0 F18B0 30 | G_JSNETCIBMID3 F17B0 31 | G_JSNETCIBMID5 F17B1 32 | G_JSNETCIBMID6 F18B1 33 | G_JSNETCIBR1 F16B0 34 | G_JSNETCIBT1 F16B1 35 | 36 | .mux G_VSRX0400 37 | G_JPCLKT00 F12B1 38 | G_JSNETCIBB1 F15B1 39 | G_JSNETCIBL1 F15B0 40 | G_JSNETCIBMID1 F14B0 41 | G_JSNETCIBMID2 F13B0 42 | G_JSNETCIBMID4 F13B1 43 | G_JSNETCIBMID7 F14B1 44 | G_JSNETCIBR0 F12B0 45 | 46 | .mux G_VSRX0500 47 | G_JPCLKT01 F8B0 48 | G_JSNETCIBB0 F11B1 49 | G_JSNETCIBL0 F11B0 50 | G_JSNETCIBMID0 F10B0 51 | G_JSNETCIBMID3 F9B0 52 | G_JSNETCIBMID5 F9B1 53 | G_JSNETCIBMID6 F10B1 54 | G_JSNETCIBT1 F8B1 55 | 56 | .mux G_VSRX0600 57 | G_JPCLKT20 F6B1 58 | G_JSNETCIBB1 F7B1 59 | G_JSNETCIBL1 F7B0 60 | G_JSNETCIBMID1 F6B0 61 | G_JSNETCIBMID2 F5B0 62 | G_JSNETCIBMID4 F5B1 63 | G_JSNETCIBR0 F4B0 64 | G_JSNETCIBT0 F4B1 65 | 66 | .mux G_VSRX0700 67 | G_JPCLKT21 F2B0 68 | G_JSNETCIBB0 F3B1 69 | G_JSNETCIBL0 F3B0 70 | G_JSNETCIBMID3 F1B0 71 | G_JSNETCIBMID5 F1B1 72 | G_JSNETCIBMID6 F2B1 73 | G_JSNETCIBR1 F0B0 74 | G_JSNETCIBT1 F0B1 75 | 76 | 77 | # Non-Routing Configuration 78 | 79 | # Fixed Connections 80 | -------------------------------------------------------------------------------- /ECP5/tiledata/TAP_DRIVE/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux L_HPBX0000 3 | G_VPTX0000 F3B0 4 | 5 | .mux L_HPBX0100 6 | G_VPTX0100 F2B0 7 | 8 | .mux L_HPBX0200 9 | G_VPTX0200 F3B2 10 | 11 | .mux L_HPBX0300 12 | G_VPTX0300 F2B2 13 | 14 | .mux L_HPBX0400 15 | G_VPTX0400 F0B4 16 | 17 | .mux L_HPBX0500 18 | G_VPTX0500 F1B4 19 | 20 | .mux L_HPBX0600 21 | G_VPTX0600 F0B5 22 | 23 | .mux L_HPBX0700 24 | G_VPTX0700 F1B5 25 | 26 | .mux L_HPBX0800 27 | G_VPTX0800 F3B6 28 | 29 | .mux L_HPBX0900 30 | G_VPTX0900 F2B6 31 | 32 | .mux L_HPBX1000 33 | G_VPTX1000 F3B8 34 | 35 | .mux L_HPBX1100 36 | G_VPTX1100 F2B8 37 | 38 | .mux L_HPBX1200 39 | G_VPTX1200 F3B9 40 | 41 | .mux L_HPBX1300 42 | G_VPTX1300 F2B9 43 | 44 | .mux L_HPBX1400 45 | G_VPTX1400 F0B10 46 | 47 | .mux L_HPBX1500 48 | G_VPTX1500 F1B10 49 | 50 | .mux R_HPBX0000 51 | G_VPTX0000 F0B0 52 | 53 | .mux R_HPBX0100 54 | G_VPTX0100 F1B0 55 | 56 | .mux R_HPBX0200 57 | G_VPTX0200 F0B2 58 | 59 | .mux R_HPBX0300 60 | G_VPTX0300 F1B2 61 | 62 | .mux R_HPBX0400 63 | G_VPTX0400 F3B4 64 | 65 | .mux R_HPBX0500 66 | G_VPTX0500 F2B4 67 | 68 | .mux R_HPBX0600 69 | G_VPTX0600 F3B5 70 | 71 | .mux R_HPBX0700 72 | G_VPTX0700 F2B5 73 | 74 | .mux R_HPBX0800 75 | G_VPTX0800 F0B6 76 | 77 | .mux R_HPBX0900 78 | G_VPTX0900 F1B6 79 | 80 | .mux R_HPBX1000 81 | G_VPTX1000 F1B8 82 | 83 | .mux R_HPBX1100 84 | G_VPTX1100 F0B8 85 | 86 | .mux R_HPBX1200 87 | G_VPTX1200 F0B9 88 | 89 | .mux R_HPBX1300 90 | G_VPTX1300 F1B9 91 | 92 | .mux R_HPBX1400 93 | G_VPTX1400 F3B10 94 | 95 | .mux R_HPBX1500 96 | G_VPTX1500 F2B10 97 | 98 | 99 | # Non-Routing Configuration 100 | 101 | # Fixed Connections 102 | -------------------------------------------------------------------------------- /ECP5/tiledata/TAP_DRIVE_CIB/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux L_HPBX0000 3 | G_VPTX0000 F3B0 4 | 5 | .mux L_HPBX0100 6 | G_VPTX0100 F2B0 7 | 8 | .mux L_HPBX0200 9 | G_VPTX0200 F3B2 10 | 11 | .mux L_HPBX0300 12 | G_VPTX0300 F2B2 13 | 14 | .mux L_HPBX0400 15 | G_VPTX0400 F0B4 16 | 17 | .mux L_HPBX0500 18 | G_VPTX0500 F1B4 19 | 20 | .mux L_HPBX0600 21 | G_VPTX0600 F0B5 22 | 23 | .mux L_HPBX0700 24 | G_VPTX0700 F1B5 25 | 26 | .mux L_HPBX0800 27 | G_VPTX0800 F3B6 28 | 29 | .mux L_HPBX0900 30 | G_VPTX0900 F2B6 31 | 32 | .mux L_HPBX1000 33 | G_VPTX1000 F3B8 34 | 35 | .mux L_HPBX1100 36 | G_VPTX1100 F2B8 37 | 38 | .mux L_HPBX1200 39 | G_VPTX1200 F3B9 40 | 41 | .mux L_HPBX1300 42 | G_VPTX1300 F2B9 43 | 44 | .mux L_HPBX1400 45 | G_VPTX1400 F0B10 46 | 47 | .mux L_HPBX1500 48 | G_VPTX1500 F1B10 49 | 50 | .mux R_HPBX0000 51 | G_VPTX0000 F0B0 52 | 53 | .mux R_HPBX0100 54 | G_VPTX0100 F1B0 55 | 56 | .mux R_HPBX0200 57 | G_VPTX0200 F0B2 58 | 59 | .mux R_HPBX0300 60 | G_VPTX0300 F1B2 61 | 62 | .mux R_HPBX0400 63 | G_VPTX0400 F3B4 64 | 65 | .mux R_HPBX0500 66 | G_VPTX0500 F2B4 67 | 68 | .mux R_HPBX0600 69 | G_VPTX0600 F3B5 70 | 71 | .mux R_HPBX0700 72 | G_VPTX0700 F2B5 73 | 74 | .mux R_HPBX0800 75 | G_VPTX0800 F0B6 76 | 77 | .mux R_HPBX0900 78 | G_VPTX0900 F1B6 79 | 80 | .mux R_HPBX1000 81 | G_VPTX1000 F1B8 82 | 83 | .mux R_HPBX1100 84 | G_VPTX1100 F0B8 85 | 86 | .mux R_HPBX1200 87 | G_VPTX1200 F0B9 88 | 89 | .mux R_HPBX1300 90 | G_VPTX1300 F1B9 91 | 92 | .mux R_HPBX1400 93 | G_VPTX1400 F3B10 94 | 95 | .mux R_HPBX1500 96 | G_VPTX1500 F2B10 97 | 98 | 99 | # Non-Routing Configuration 100 | 101 | # Fixed Connections 102 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CENTER6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VSRX0000 3 | G_JSNETCIBR0 F28B0 4 | G_JSNETCIBT0 F28B1 5 | 6 | .mux G_VSRX0100 7 | G_JPCLKT31 F25B0 8 | G_JPCLKT40 F25B0 9 | G_JSNETCIBB0 F27B1 10 | G_JSNETCIBL0 F27B0 11 | G_JSNETCIBMID0 F26B0 12 | G_JSNETCIBMID5 F25B1 13 | G_JSNETCIBMID6 F26B1 14 | G_JSNETCIBR1 F24B0 15 | G_JSNETCIBT1 F24B1 16 | 17 | .mux G_VSRX0200 18 | G_JPCLKT10 F23B1 19 | G_JSNETCIBL1 F23B0 20 | G_JSNETCIBMID1 F22B0 21 | G_JSNETCIBMID2 F21B0 22 | G_JSNETCIBMID4 F21B1 23 | G_JSNETCIBMID7 F22B1 24 | G_JSNETCIBR0 F20B0 25 | G_JSNETCIBT0 F20B1 26 | 27 | .mux G_VSRX0300 28 | G_JPCLKT32 F19B0 29 | G_JPCLKT50 F19B0 30 | G_JSNETCIBB0 F19B1 31 | G_JSNETCIBMID0 F18B0 32 | G_JSNETCIBMID3 F17B0 33 | G_JSNETCIBMID5 F17B1 34 | G_JSNETCIBMID6 F18B1 35 | G_JSNETCIBR1 F16B0 36 | G_JSNETCIBT1 F16B1 37 | 38 | .mux G_VSRX0400 39 | G_JPCLKT00 F12B1 40 | G_JSNETCIBB1 F15B1 41 | G_JSNETCIBL1 F15B0 42 | G_JSNETCIBMID1 F14B0 43 | G_JSNETCIBMID2 F13B0 44 | G_JSNETCIBMID4 F13B1 45 | G_JSNETCIBMID7 F14B1 46 | G_JSNETCIBR0 F12B0 47 | 48 | .mux G_VSRX0500 49 | G_JPCLKT01 F8B0 50 | G_JSNETCIBB0 F11B1 51 | G_JSNETCIBL0 F11B0 52 | G_JSNETCIBMID0 F10B0 53 | G_JSNETCIBMID3 F9B0 54 | G_JSNETCIBMID5 F9B1 55 | G_JSNETCIBMID6 F10B1 56 | G_JSNETCIBT1 F8B1 57 | 58 | .mux G_VSRX0600 59 | G_JPCLKT20 F6B1 60 | G_JSNETCIBB1 F7B1 61 | G_JSNETCIBL1 F7B0 62 | G_JSNETCIBMID1 F6B0 63 | G_JSNETCIBMID2 F5B0 64 | G_JSNETCIBMID4 F5B1 65 | G_JSNETCIBR0 F4B0 66 | G_JSNETCIBT0 F4B1 67 | 68 | .mux G_VSRX0700 69 | G_JPCLKT21 F2B0 70 | G_JSNETCIBB0 F3B1 71 | G_JSNETCIBL0 F3B0 72 | G_JSNETCIBMID3 F1B0 73 | G_JSNETCIBMID5 F1B1 74 | G_JSNETCIBMID6 F2B1 75 | G_JSNETCIBR1 F0B0 76 | G_JSNETCIBT1 F0B1 77 | 78 | 79 | # Non-Routing Configuration 80 | 81 | # Fixed Connections 82 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CENTER6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VSRX0000 3 | G_JSNETCIBR0 F28B0 4 | G_JSNETCIBT0 F28B1 5 | 6 | .mux G_VSRX0100 7 | G_JPCLKT31 F25B0 8 | G_JPCLKT40 F25B0 9 | G_JSNETCIBB0 F27B1 10 | G_JSNETCIBL0 F27B0 11 | G_JSNETCIBMID0 F26B0 12 | G_JSNETCIBMID5 F25B1 13 | G_JSNETCIBMID6 F26B1 14 | G_JSNETCIBR1 F24B0 15 | G_JSNETCIBT1 F24B1 16 | 17 | .mux G_VSRX0200 18 | G_JPCLKT10 F23B1 19 | G_JSNETCIBL1 F23B0 20 | G_JSNETCIBMID1 F22B0 21 | G_JSNETCIBMID2 F21B0 22 | G_JSNETCIBMID4 F21B1 23 | G_JSNETCIBMID7 F22B1 24 | G_JSNETCIBR0 F20B0 25 | G_JSNETCIBT0 F20B1 26 | 27 | .mux G_VSRX0300 28 | G_JPCLKT32 F19B0 29 | G_JPCLKT50 F19B0 30 | G_JSNETCIBB0 F19B1 31 | G_JSNETCIBMID0 F18B0 32 | G_JSNETCIBMID3 F17B0 33 | G_JSNETCIBMID5 F17B1 34 | G_JSNETCIBMID6 F18B1 35 | G_JSNETCIBR1 F16B0 36 | G_JSNETCIBT1 F16B1 37 | 38 | .mux G_VSRX0400 39 | G_JPCLKT00 F12B1 40 | G_JSNETCIBB1 F15B1 41 | G_JSNETCIBL1 F15B0 42 | G_JSNETCIBMID1 F14B0 43 | G_JSNETCIBMID2 F13B0 44 | G_JSNETCIBMID4 F13B1 45 | G_JSNETCIBMID7 F14B1 46 | G_JSNETCIBR0 F12B0 47 | 48 | .mux G_VSRX0500 49 | G_JPCLKT01 F8B0 50 | G_JSNETCIBB0 F11B1 51 | G_JSNETCIBL0 F11B0 52 | G_JSNETCIBMID0 F10B0 53 | G_JSNETCIBMID3 F9B0 54 | G_JSNETCIBMID5 F9B1 55 | G_JSNETCIBMID6 F10B1 56 | G_JSNETCIBT1 F8B1 57 | 58 | .mux G_VSRX0600 59 | G_JPCLKT20 F6B1 60 | G_JSNETCIBB1 F7B1 61 | G_JSNETCIBL1 F7B0 62 | G_JSNETCIBMID1 F6B0 63 | G_JSNETCIBMID2 F5B0 64 | G_JSNETCIBMID4 F5B1 65 | G_JSNETCIBR0 F4B0 66 | G_JSNETCIBT0 F4B1 67 | 68 | .mux G_VSRX0700 69 | G_JPCLKT21 F2B0 70 | G_JSNETCIBB0 F3B1 71 | G_JSNETCIBL0 F3B0 72 | G_JSNETCIBMID3 F1B0 73 | G_JSNETCIBMID5 F1B1 74 | G_JSNETCIBMID6 F2B1 75 | G_JSNETCIBR1 F0B0 76 | G_JSNETCIBT1 F0B1 77 | 78 | 79 | # Non-Routing Configuration 80 | 81 | # Fixed Connections 82 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config DCU.D_BITCLK_FROM_ND_EN 0 5 | F0B1 6 | 7 | .config DCU.D_CMUSETBIASI 00 8 | F76B1 9 | F77B1 10 | 11 | .config DCU.D_CMUSETI4CPP 0000 12 | F66B1 13 | F67B1 14 | F68B1 15 | F69B1 16 | 17 | .config DCU.D_CMUSETI4CPZ 0000 18 | F61B1 19 | F62B1 20 | F63B1 21 | F64B1 22 | 23 | .config DCU.D_CMUSETI4VCO 00 24 | F43B1 25 | F44B1 26 | 27 | .config DCU.D_CMUSETICP4P 00 28 | F74B1 29 | F75B1 30 | 31 | .config DCU.D_CMUSETICP4Z 000 32 | F70B1 33 | F71B1 34 | F72B1 35 | 36 | .config DCU.D_CMUSETINITVCT 00 37 | F45B1 38 | F46B1 39 | 40 | .config DCU.D_CMUSETISCL4VCO 000 41 | F40B1 42 | F41B1 43 | F42B1 44 | 45 | .config DCU.D_CMUSETP1GM 000 46 | F58B1 47 | F59B1 48 | F60B1 49 | 50 | .config DCU.D_CMUSETP2AGM 000 51 | F51B1 52 | F54B1 53 | F55B1 54 | 55 | .config DCU.D_CMUSETZGM 000 56 | F48B1 57 | F49B1 58 | F50B1 59 | 60 | .config DCU.D_DCO_CALIB_TIME_SEL 00 61 | F98B1 62 | F99B1 63 | 64 | .config DCU.D_IB_PWDNB 0 65 | F6B1 66 | 67 | .config DCU.D_ISETLOS 00000000 68 | F32B1 69 | F33B1 70 | F34B1 71 | F35B1 72 | F36B1 73 | F37B1 74 | F38B1 75 | F39B1 76 | 77 | .config DCU.D_MACROPDB 0 78 | F3B1 79 | 80 | .config DCU.D_PD_ISET 00 81 | F93B1 82 | F94B1 83 | 84 | .config DCU.D_REQ_ISET 000 85 | F90B1 86 | F91B1 87 | F92B1 88 | 89 | .config DCU.D_SETICONST_AUX 00 90 | F84B1 91 | F85B1 92 | 93 | .config DCU.D_SETICONST_CH 00 94 | F88B1 95 | F89B1 96 | 97 | .config DCU.D_SETIRPOLY_AUX 00 98 | F82B1 99 | F83B1 100 | 101 | .config DCU.D_SETIRPOLY_CH 00 102 | F86B1 103 | F87B1 104 | 105 | .config DCU.D_TXPLL_PWDNB 0 106 | F5B1 107 | 108 | .config EXTREF.REFCK_PWDNB 0 109 | F4B1 110 | 111 | 112 | # Fixed Connections 113 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_EBR5/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR2.CSDECODE_B 111 5 | !F22B0 6 | !F13B0 7 | !F7B0 8 | 9 | .config EBR2.WID 000000000 10 | F88B0 11 | F85B0 12 | F84B0 13 | F82B0 14 | F81B0 15 | F79B0 16 | F78B0 17 | F66B0 18 | F75B0 19 | 20 | .config_enum EBR2.ADA0MUX ADA0 21 | ADA0 !F8B0 22 | INV F8B0 23 | 24 | .config_enum EBR2.ADA1MUX ADA1 25 | ADA1 !F76B0 26 | INV F76B0 27 | 28 | .config_enum EBR2.ADA2MUX ADA2 29 | ADA2 !F32B0 30 | INV F32B0 31 | 32 | .config_enum EBR2.ADA3MUX ADA3 33 | ADA3 !F3B0 34 | INV F3B0 35 | 36 | .config_enum EBR2.ADB0MUX ADB0 37 | ADB0 !F1B0 38 | INV F1B0 39 | 40 | .config_enum EBR2.ADB1MUX ADB1 41 | ADB1 !F4B0 42 | INV F4B0 43 | 44 | .config_enum EBR2.ASYNC_RESET_RELEASE SYNC 45 | ASYNC F73B0 46 | SYNC !F73B0 47 | 48 | .config_enum EBR2.CEBMUX CEB 49 | CEB !F43B0 50 | INV F43B0 51 | 52 | .config_enum EBR2.CLKBMUX CLKB 53 | CLKB !F50B0 54 | INV F50B0 55 | 56 | .config_enum EBR2.DP16KD.DATA_WIDTH_A 18 57 | 1 F25B0 58 | 18 !F25B0 59 | 2 F25B0 60 | 4 !F25B0 61 | 9 !F25B0 62 | 63 | .config_enum EBR2.DP16KD.WRITEMODE_A WRITETHROUGH 64 | NORMAL !F48B0 65 | READBEFOREWRITE F48B0 66 | WRITETHROUGH !F48B0 67 | 68 | .config_enum EBR2.MODE NONE 69 | DP16KD F19B0 !F42B0 F57B0 F98B0 F105B0 70 | NONE !F19B0 !F42B0 !F57B0 !F98B0 !F105B0 71 | PDPW16KD F19B0 F42B0 F57B0 F98B0 F105B0 72 | 73 | .config_enum EBR2.OCEBMUX OCEB 74 | INV F29B0 75 | OCEB !F29B0 76 | 77 | .config_enum EBR2.REGMODE_A NOREG 78 | NOREG !F68B0 79 | OUTREG F68B0 80 | 81 | .config_enum EBR2.RESETMODE SYNC 82 | ASYNC F51B0 83 | SYNC !F51B0 84 | 85 | .config_enum EBR2.RSTAMUX RSTA 86 | INV F67B0 87 | RSTA !F67B0 88 | 89 | .config_enum EBR2.RSTBMUX RSTB 90 | INV F101B0 91 | RSTB !F101B0 92 | 93 | .config_enum EBR2.WEBMUX WEB 94 | INV F36B0 95 | WEB !F36B0 96 | 97 | 98 | # Fixed Connections 99 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/DQSDLL_R/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux S1_DQSDLLCLK 3 | G_TECLK0 F3B2 4 | G_TECLK1 F3B2 F4B2 5 | S1_JDQSDLLSCLK F4B2 6 | 7 | 8 | # Non-Routing Configuration 9 | .config TDQSDLL.DEL_VAL 0000000 10 | F2B40 11 | F3B36 12 | F5B29 13 | F2B25 14 | F2B15 15 | F2B8 16 | F3B3 17 | 18 | .config_enum TDQSDLL.DEL_ADJ PLUS 19 | MINUS F5B21 20 | PLUS !F5B21 21 | 22 | .config_enum TDQSDLL.FORCE_MAX_DELAY 23 | NO !F3B25 F5B14 24 | YES F3B25 !F5B14 25 | 26 | .config_enum TDQSDLL.GSR ENABLED 27 | DISABLED F2B3 28 | ENABLED !F2B3 29 | 30 | .config_enum TDQSDLL.LOCK_SENSITIVITY LOW 31 | HIGH F5B44 32 | LOW !F5B44 33 | 34 | .config_enum TDQSDLL.MODE NONE 35 | DQSDLLC F4B29 36 | NONE - 37 | 38 | .config_enum TDQSDLL.RST RST 39 | 0 !F2B2 40 | 1 F2B2 41 | INV F2B2 42 | RST !F2B2 43 | 44 | 45 | # Fixed Connections 46 | .fixed_conn 4300D_S11E3_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 47 | 48 | .fixed_conn 4300D_W13_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 49 | 50 | .fixed_conn 4300D_W13_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 51 | 52 | .fixed_conn 9400D_S15E4_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 53 | 54 | .fixed_conn 9400D_W21_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 55 | 56 | .fixed_conn 9400D_W21_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 57 | 58 | .fixed_conn S1_CLK_DQSDLL S1_DQSDLLCLK 59 | 60 | .fixed_conn S1_JCLK0 S1_JDQSDLLSCLK 61 | 62 | .fixed_conn S1_JDIVOSC_DQSDLLTEST S1_JF1 63 | 64 | .fixed_conn S1_JF0 S1_JLOCK_DQSDLL 65 | 66 | .fixed_conn S1_JFREEZE_DQSDLL S1_JB0 67 | 68 | .fixed_conn S1_JQ0 S1_JSDOUT0_DQSDLLTEST 69 | 70 | .fixed_conn S1_JQ1 S1_JSDOUT1_DQSDLLTEST 71 | 72 | .fixed_conn S1_JQ2 S1_JSDOUT2_DQSDLLTEST 73 | 74 | .fixed_conn S1_JQ3 S1_JSDOUT3_DQSDLLTEST 75 | 76 | .fixed_conn S1_JQ4 S1_JSDOUT4_DQSDLLTEST 77 | 78 | .fixed_conn S1_JQ5 S1_JSDOUT5_DQSDLLTEST 79 | 80 | .fixed_conn S1_JQ6 S1_JSDOUT6_DQSDLLTEST 81 | 82 | .fixed_conn S1_JRST_DQSDLL S1_JLSR0 83 | 84 | .fixed_conn S1_JUDDCNTLN_DQSDLL S1_JA0 85 | 86 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU6/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config DCU.CH1_AUTO_CALIB_EN 0 5 | F47B1 6 | 7 | .config DCU.CH1_AUTO_FACQ_EN 0 8 | F46B1 9 | 10 | .config DCU.CH1_BAND_THRESHOLD 000000 11 | F40B1 12 | F41B1 13 | F42B1 14 | F43B1 15 | F44B1 16 | F45B1 17 | 18 | .config DCU.CH1_CALIB_CK_MODE 0 19 | F48B1 20 | 21 | .config DCU.CH1_CDR_CNT4SEL 00 22 | F32B1 23 | F33B1 24 | 25 | .config DCU.CH1_CDR_CNT8SEL 00 26 | F34B1 27 | F35B1 28 | 29 | .config DCU.CH1_DCOCALDIV 000 30 | F9B1 31 | F10B1 32 | F11B1 33 | 34 | .config DCU.CH1_DCODISBDAVOID 0 35 | F8B1 36 | 37 | .config DCU.CH1_DCOFLTDAC 00 38 | F24B1 39 | F25B1 40 | 41 | .config DCU.CH1_DCOFTNRG 000 42 | F28B1 43 | F29B1 44 | F30B1 45 | 46 | .config DCU.CH1_DCOIOSTUNE 000 47 | F5B1 48 | F6B1 49 | F7B1 50 | 51 | .config DCU.CH1_DCOITUNE 00 52 | F26B1 53 | F27B1 54 | 55 | .config DCU.CH1_DCOITUNE4LSB 000 56 | F2B1 57 | F3B1 58 | F4B1 59 | 60 | .config DCU.CH1_DCOIUPDNX2 0 61 | F15B1 62 | 63 | .config DCU.CH1_DCONUOFLSB 000 64 | F12B1 65 | F13B1 66 | F14B1 67 | 68 | .config DCU.CH1_DCOSCALEI 00 69 | F0B1 70 | F1B1 71 | 72 | .config DCU.CH1_DCOSTARTVAL 000 73 | F18B1 74 | F19B1 75 | F20B1 76 | 77 | .config DCU.CH1_DCOSTEP 00 78 | F16B1 79 | F17B1 80 | 81 | .config DCU.CH1_REG_BAND_OFFSET 0000 82 | F49B1 83 | F50B1 84 | F51B1 85 | F54B1 86 | 87 | .config DCU.CH1_REG_BAND_SEL 000000 88 | F58B1 89 | F59B1 90 | F60B1 91 | F61B1 92 | F62B1 93 | F63B1 94 | 95 | .config DCU.CH1_REG_IDAC_EN 0 96 | F76B1 97 | 98 | .config DCU.CH1_REG_IDAC_SEL 0000000000 99 | F66B1 100 | F67B1 101 | F68B1 102 | F69B1 103 | F70B1 104 | F71B1 105 | F72B1 106 | F73B1 107 | F74B1 108 | F75B1 109 | 110 | .config DCU.D_HIGH_MARK 0000 111 | F102B1 112 | F103B1 113 | F104B1 114 | F105B1 115 | 116 | .config DCU.D_LOW_MARK 0000 117 | F98B1 118 | F99B1 119 | F100B1 120 | F101B1 121 | 122 | .config DCU.D_XGE_MODE 0 123 | F86B1 124 | 125 | 126 | # Fixed Connections 127 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU2/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config DCU.CH0_CDR_CNT4SEL 00 5 | F98B1 6 | F99B1 7 | 8 | .config DCU.CH0_CDR_CNT8SEL 00 9 | F100B1 10 | F101B1 11 | 12 | .config DCU.CH0_DCOATDCFG 00 13 | F63B1 14 | F64B1 15 | 16 | .config DCU.CH0_DCOATDDLY 00 17 | F61B1 18 | F62B1 19 | 20 | .config DCU.CH0_DCOBYPSATD 0 21 | F65B1 22 | 23 | .config DCU.CH0_DCOCALDIV 000 24 | F75B1 25 | F76B1 26 | F77B1 27 | 28 | .config DCU.CH0_DCOCTLGI 000 29 | F58B1 30 | F59B1 31 | F60B1 32 | 33 | .config DCU.CH0_DCODISBDAVOID 0 34 | F74B1 35 | 36 | .config DCU.CH0_DCOFLTDAC 00 37 | F90B1 38 | F91B1 39 | 40 | .config DCU.CH0_DCOFTNRG 000 41 | F94B1 42 | F95B1 43 | F96B1 44 | 45 | .config DCU.CH0_DCOIOSTUNE 000 46 | F71B1 47 | F72B1 48 | F73B1 49 | 50 | .config DCU.CH0_DCOITUNE 00 51 | F92B1 52 | F93B1 53 | 54 | .config DCU.CH0_DCOITUNE4LSB 000 55 | F68B1 56 | F69B1 57 | F70B1 58 | 59 | .config DCU.CH0_DCOIUPDNX2 0 60 | F81B1 61 | 62 | .config DCU.CH0_DCONUOFLSB 000 63 | F78B1 64 | F79B1 65 | F80B1 66 | 67 | .config DCU.CH0_DCOSCALEI 00 68 | F66B1 69 | F67B1 70 | 71 | .config DCU.CH0_DCOSTARTVAL 000 72 | F84B1 73 | F85B1 74 | F86B1 75 | 76 | .config DCU.CH0_DCOSTEP 00 77 | F82B1 78 | F83B1 79 | 80 | .config DCU.CH0_FF_RX_F_CLK_DIS 0 81 | F42B1 82 | 83 | .config DCU.CH0_FF_RX_H_CLK_EN 0 84 | F41B1 85 | 86 | .config DCU.CH0_FF_TX_F_CLK_DIS 0 87 | F44B1 88 | 89 | .config DCU.CH0_FF_TX_H_CLK_EN 0 90 | F43B1 91 | 92 | .config DCU.CH0_PDEN_SEL 0 93 | F3B1 94 | 95 | .config DCU.CH0_RLOS_SEL 0 96 | F15B1 97 | 98 | .config DCU.CH0_RX_DCO_CK_DIV 000 99 | F0B1 100 | F1B1 101 | F2B1 102 | 103 | .config DCU.CH0_RX_LOS_CEQ 00 104 | F11B1 105 | F12B1 106 | 107 | .config DCU.CH0_RX_LOS_EN 0 108 | F14B1 109 | 110 | .config DCU.CH0_RX_LOS_HYST_EN 0 111 | F13B1 112 | 113 | .config DCU.CH0_RX_LOS_LVL 000 114 | F8B1 115 | F9B1 116 | F10B1 117 | 118 | .config DCU.CH0_SEL_SD_RX_CLK 0 119 | F40B1 120 | 121 | .config_enum DCU.MODE NONE 122 | DCUA F6B1 F7B1 123 | NONE - 124 | 125 | 126 | # Fixed Connections 127 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/DQSDLL_L/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N1_DQSDLLCLK 3 | G_BECLK0 F2B2 4 | G_BECLK1 F1B2 F2B2 5 | N1_JDQSDLLSCLK F1B2 6 | 7 | 8 | # Non-Routing Configuration 9 | .config BDQSDLL.DEL_VAL 0000000 10 | F3B40 11 | F2B36 12 | F0B29 13 | F3B25 14 | F3B15 15 | F3B8 16 | F2B3 17 | 18 | .config_enum BDQSDLL.DEL_ADJ PLUS 19 | MINUS F0B21 20 | PLUS !F0B21 21 | 22 | .config_enum BDQSDLL.FORCE_MAX_DELAY 23 | NO F0B14 !F2B25 24 | YES !F0B14 F2B25 25 | 26 | .config_enum BDQSDLL.GSR ENABLED 27 | DISABLED F3B3 28 | ENABLED !F3B3 29 | 30 | .config_enum BDQSDLL.LOCK_SENSITIVITY LOW 31 | HIGH F0B44 32 | LOW !F0B44 33 | 34 | .config_enum BDQSDLL.MODE NONE 35 | DQSDLLC F1B29 36 | NONE - 37 | 38 | .config_enum BDQSDLL.RST RST 39 | 0 !F3B2 40 | 1 F3B2 41 | INV F3B2 42 | RST !F3B2 43 | 44 | 45 | # Fixed Connections 46 | .fixed_conn 4300D_E14_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 47 | 48 | .fixed_conn 4300D_E14_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 49 | 50 | .fixed_conn 4300D_N11W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 51 | 52 | .fixed_conn 4300D_N11W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 53 | 54 | .fixed_conn 4300D_N11W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 55 | 56 | .fixed_conn 9400D_E23_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 57 | 58 | .fixed_conn 9400D_E23_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 59 | 60 | .fixed_conn 9400D_N16W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 61 | 62 | .fixed_conn 9400D_N16W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 63 | 64 | .fixed_conn 9400D_N16W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 65 | 66 | .fixed_conn N1_CLK_DQSDLL N1_DQSDLLCLK 67 | 68 | .fixed_conn N1_JCLK0 N1_JDQSDLLSCLK 69 | 70 | .fixed_conn N1_JDIVOSC_DQSDLLTEST N1_JF1 71 | 72 | .fixed_conn N1_JF0 N1_JLOCK_DQSDLL 73 | 74 | .fixed_conn N1_JFREEZE_DQSDLL N1_JB0 75 | 76 | .fixed_conn N1_JQ0 N1_JSDOUT0_DQSDLLTEST 77 | 78 | .fixed_conn N1_JQ1 N1_JSDOUT1_DQSDLLTEST 79 | 80 | .fixed_conn N1_JQ2 N1_JSDOUT2_DQSDLLTEST 81 | 82 | .fixed_conn N1_JQ3 N1_JSDOUT3_DQSDLLTEST 83 | 84 | .fixed_conn N1_JQ4 N1_JSDOUT4_DQSDLLTEST 85 | 86 | .fixed_conn N1_JQ5 N1_JSDOUT5_DQSDLLTEST 87 | 88 | .fixed_conn N1_JQ6 N1_JSDOUT6_DQSDLLTEST 89 | 90 | .fixed_conn N1_JRST_DQSDLL N1_JLSR0 91 | 92 | .fixed_conn N1_JUDDCNTLN_DQSDLL N1_JA0 93 | 94 | -------------------------------------------------------------------------------- /ECP5/LFE5U-85F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 67, 7 | "y1": 46 8 | }, 9 | "UR": { 10 | "x0": 68, 11 | "y0": 0, 12 | "x1": 126, 13 | "y1": 46 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 47, 18 | "x1": 67, 19 | "y1": 95 20 | }, 21 | "LR": { 22 | "x0": 68, 23 | "y0": 47, 24 | "x1": 126, 25 | "y1": 95 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 43 40 | }, 41 | "C58": { 42 | "lx0": 44, 43 | "lx1": 57, 44 | "rx0": 58, 45 | "rx1": 67 46 | }, 47 | "C78": { 48 | "lx0": 68, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 86 52 | }, 53 | "C96": { 54 | "lx0": 87, 55 | "lx1": 95, 56 | "rx0": 96, 57 | "rx1": 104 58 | }, 59 | "C114": { 60 | "lx0": 105, 61 | "lx1": 113, 62 | "rx0": 114, 63 | "rx1": 126 64 | } 65 | }, 66 | "spines": { 67 | "UL13": { 68 | "x": 12, 69 | "y": 22 70 | }, 71 | "LL13": { 72 | "x": 12, 73 | "y": 70 74 | }, 75 | "UL31": { 76 | "x": 30, 77 | "y": 22 78 | }, 79 | "LL31": { 80 | "x": 30, 81 | "y": 70 82 | }, 83 | "UL58": { 84 | "x": 57, 85 | "y": 22 86 | }, 87 | "LL58": { 88 | "x": 57, 89 | "y": 70 90 | }, 91 | "UR78": { 92 | "x": 77, 93 | "y": 22 94 | }, 95 | "LR78": { 96 | "x": 77, 97 | "y": 70 98 | }, 99 | "UR96": { 100 | "x": 95, 101 | "y": 22 102 | }, 103 | "LR96": { 104 | "x": 95, 105 | "y": 70 106 | }, 107 | "UR114": { 108 | "x": 113, 109 | "y": 22 110 | }, 111 | "LR114": { 112 | "x": 113, 113 | "y": 70 114 | } 115 | } 116 | } 117 | -------------------------------------------------------------------------------- /ECP5/LFE5UM-85F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 67, 7 | "y1": 46 8 | }, 9 | "UR": { 10 | "x0": 68, 11 | "y0": 0, 12 | "x1": 126, 13 | "y1": 46 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 47, 18 | "x1": 67, 19 | "y1": 95 20 | }, 21 | "LR": { 22 | "x0": 68, 23 | "y0": 47, 24 | "x1": 126, 25 | "y1": 95 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 43 40 | }, 41 | "C58": { 42 | "lx0": 44, 43 | "lx1": 57, 44 | "rx0": 58, 45 | "rx1": 67 46 | }, 47 | "C78": { 48 | "lx0": 68, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 86 52 | }, 53 | "C96": { 54 | "lx0": 87, 55 | "lx1": 95, 56 | "rx0": 96, 57 | "rx1": 104 58 | }, 59 | "C114": { 60 | "lx0": 105, 61 | "lx1": 113, 62 | "rx0": 114, 63 | "rx1": 126 64 | } 65 | }, 66 | "spines": { 67 | "UL13": { 68 | "x": 12, 69 | "y": 22 70 | }, 71 | "LL13": { 72 | "x": 12, 73 | "y": 70 74 | }, 75 | "UL31": { 76 | "x": 30, 77 | "y": 22 78 | }, 79 | "LL31": { 80 | "x": 30, 81 | "y": 70 82 | }, 83 | "UL58": { 84 | "x": 57, 85 | "y": 22 86 | }, 87 | "LL58": { 88 | "x": 57, 89 | "y": 70 90 | }, 91 | "UR78": { 92 | "x": 77, 93 | "y": 22 94 | }, 95 | "LR78": { 96 | "x": 77, 97 | "y": 70 98 | }, 99 | "UR96": { 100 | "x": 95, 101 | "y": 22 102 | }, 103 | "LR96": { 104 | "x": 95, 105 | "y": 70 106 | }, 107 | "UR114": { 108 | "x": 113, 109 | "y": 22 110 | }, 111 | "LR114": { 112 | "x": 113, 113 | "y": 70 114 | } 115 | } 116 | } 117 | -------------------------------------------------------------------------------- /ECP5/LFE5UM5G-85F/globals.json: -------------------------------------------------------------------------------- 1 | { 2 | "quadrants": { 3 | "UL": { 4 | "x0": 0, 5 | "y0": 0, 6 | "x1": 67, 7 | "y1": 46 8 | }, 9 | "UR": { 10 | "x0": 68, 11 | "y0": 0, 12 | "x1": 126, 13 | "y1": 46 14 | }, 15 | "LL": { 16 | "x0": 0, 17 | "y0": 47, 18 | "x1": 67, 19 | "y1": 95 20 | }, 21 | "LR": { 22 | "x0": 68, 23 | "y0": 47, 24 | "x1": 126, 25 | "y1": 95 26 | } 27 | }, 28 | "taps": { 29 | "C13": { 30 | "lx0": 0, 31 | "lx1": 12, 32 | "rx0": 13, 33 | "rx1": 21 34 | }, 35 | "C31": { 36 | "lx0": 22, 37 | "lx1": 30, 38 | "rx0": 31, 39 | "rx1": 43 40 | }, 41 | "C58": { 42 | "lx0": 44, 43 | "lx1": 57, 44 | "rx0": 58, 45 | "rx1": 67 46 | }, 47 | "C78": { 48 | "lx0": 68, 49 | "lx1": 77, 50 | "rx0": 78, 51 | "rx1": 86 52 | }, 53 | "C96": { 54 | "lx0": 87, 55 | "lx1": 95, 56 | "rx0": 96, 57 | "rx1": 104 58 | }, 59 | "C114": { 60 | "lx0": 105, 61 | "lx1": 113, 62 | "rx0": 114, 63 | "rx1": 126 64 | } 65 | }, 66 | "spines": { 67 | "UL13": { 68 | "x": 12, 69 | "y": 22 70 | }, 71 | "LL13": { 72 | "x": 12, 73 | "y": 70 74 | }, 75 | "UL31": { 76 | "x": 30, 77 | "y": 22 78 | }, 79 | "LL31": { 80 | "x": 30, 81 | "y": 70 82 | }, 83 | "UL58": { 84 | "x": 57, 85 | "y": 22 86 | }, 87 | "LL58": { 88 | "x": 57, 89 | "y": 70 90 | }, 91 | "UR78": { 92 | "x": 77, 93 | "y": 22 94 | }, 95 | "LR78": { 96 | "x": 77, 97 | "y": 70 98 | }, 99 | "UR96": { 100 | "x": 95, 101 | "y": 22 102 | }, 103 | "LR96": { 104 | "x": 95, 105 | "y": 70 106 | }, 107 | "UR114": { 108 | "x": 113, 109 | "y": 22 110 | }, 111 | "LR114": { 112 | "x": 113, 113 | "y": 70 114 | } 115 | } 116 | } 117 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU5/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux W5_CH1_RX_REFCLK 3 | W5_JCH1RXREFCLKCIB F12B1 4 | 5 | 6 | # Non-Routing Configuration 7 | .config DCU.CH1_DCOATDCFG 00 8 | F103B1 9 | F104B1 10 | 11 | .config DCU.CH1_DCOATDDLY 00 12 | F101B1 13 | F102B1 14 | 15 | .config DCU.CH1_DCOBYPSATD 0 16 | F105B1 17 | 18 | .config DCU.CH1_DCOCTLGI 000 19 | F98B1 20 | F99B1 21 | F100B1 22 | 23 | .config DCU.CH1_FF_RX_F_CLK_DIS 0 24 | F84B1 25 | 26 | .config DCU.CH1_FF_RX_H_CLK_EN 0 27 | F83B1 28 | 29 | .config DCU.CH1_FF_TX_F_CLK_DIS 0 30 | F86B1 31 | 32 | .config DCU.CH1_FF_TX_H_CLK_EN 0 33 | F85B1 34 | 35 | .config DCU.CH1_LDR_RX2CORE_SEL 0 36 | F11B1 37 | 38 | .config DCU.CH1_LEQ_OFFSET_SEL 0 39 | F24B1 40 | 41 | .config DCU.CH1_LEQ_OFFSET_TRIM 000 42 | F25B1 43 | F26B1 44 | F27B1 45 | 46 | .config DCU.CH1_PDEN_SEL 0 47 | F43B1 48 | 49 | .config DCU.CH1_RATE_MODE_RX 0 50 | F9B1 51 | 52 | .config DCU.CH1_RCV_DCC_EN 0 53 | F13B1 54 | 55 | .config DCU.CH1_REQ_EN 0 56 | F32B1 57 | 58 | .config DCU.CH1_REQ_LVL_SET 00 59 | F37B1 60 | F38B1 61 | 62 | .config DCU.CH1_RLOS_SEL 0 63 | F57B1 64 | 65 | .config DCU.CH1_RPWDNB 0 66 | F8B1 67 | 68 | .config DCU.CH1_RTERM_RX 00000 69 | F16B1 70 | F17B1 71 | F18B1 72 | F19B1 73 | F20B1 74 | 75 | .config DCU.CH1_RXIN_CM 00 76 | F22B1 77 | F23B1 78 | 79 | .config DCU.CH1_RXTERM_CM 00 80 | F14B1 81 | F15B1 82 | 83 | .config DCU.CH1_RX_DCO_CK_DIV 000 84 | F40B1 85 | F41B1 86 | F42B1 87 | 88 | .config DCU.CH1_RX_DIV11_SEL 0 89 | F10B1 90 | 91 | .config DCU.CH1_RX_LOS_CEQ 00 92 | F51B1 93 | F54B1 94 | 95 | .config DCU.CH1_RX_LOS_EN 0 96 | F56B1 97 | 98 | .config DCU.CH1_RX_LOS_HYST_EN 0 99 | F55B1 100 | 101 | .config DCU.CH1_RX_LOS_LVL 000 102 | F48B1 103 | F49B1 104 | F50B1 105 | 106 | .config DCU.CH1_RX_RATE_SEL 0000 107 | F33B1 108 | F34B1 109 | F35B1 110 | F36B1 111 | 112 | .config DCU.CH1_SEL_SD_RX_CLK 0 113 | F82B1 114 | 115 | .config DCU.CH1_TDRV_DAT_SEL 00 116 | F4B1 117 | F5B1 118 | 119 | .config DCU.CH1_TDRV_SLICE5_CUR 00 120 | F6B1 121 | F7B1 122 | 123 | .config_enum DCU.MODE NONE 124 | DCUA F46B1 F47B1 125 | NONE - 126 | 127 | 128 | # Fixed Connections 129 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_SPINE_UL0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | .mux W3_JMULTA0 51 | W3_JPO0 F54B0 52 | 53 | .mux W3_JMULTA1 54 | W3_JPO1 F54B0 55 | 56 | .mux W3_JMULTA10 57 | W3_JPO10 F54B0 58 | 59 | .mux W3_JMULTA11 60 | W3_JPO11 F54B0 61 | 62 | .mux W3_JMULTA12 63 | W3_JPO12 F54B0 64 | 65 | .mux W3_JMULTA13 66 | W3_JPO13 F54B0 67 | 68 | .mux W3_JMULTA14 69 | W3_JPO14 F54B0 70 | 71 | .mux W3_JMULTA15 72 | W3_JPO15 F54B0 73 | 74 | .mux W3_JMULTA16 75 | W3_JPO16 F54B0 76 | 77 | .mux W3_JMULTA17 78 | W3_JPO17 F54B0 79 | 80 | .mux W3_JMULTA2 81 | W3_JPO2 F54B0 82 | 83 | .mux W3_JMULTA3 84 | W3_JPO3 F54B0 85 | 86 | .mux W3_JMULTA4 87 | W3_JPO4 F54B0 88 | 89 | .mux W3_JMULTA5 90 | W3_JPO5 F54B0 91 | 92 | .mux W3_JMULTA6 93 | W3_JPO6 F54B0 94 | 95 | .mux W3_JMULTA7 96 | W3_JPO7 F54B0 97 | 98 | .mux W3_JMULTA8 99 | W3_JPO8 F54B0 100 | 101 | .mux W3_JMULTA9 102 | W3_JPO9 F54B0 103 | 104 | 105 | # Non-Routing Configuration 106 | .config_enum ALU54_7.MODE NONE 107 | ALU54B F55B0 F61B0 108 | NONE - 109 | 110 | .config_enum MULT18_5.MODE NONE 111 | MULT18X18D F56B0 F57B0 112 | NONE - 113 | 114 | .config_enum MULT18_5.REG_INPUTB_CLK CLK3 115 | CLK0 - 116 | CLK1 - 117 | CLK2 - 118 | CLK3 - 119 | NONE F55B0 F61B0 120 | 121 | .config_enum MULT18_5.SOURCEB_MODE 122 | B_C_DYNAMIC F51B0 123 | B_SHIFT F60B0 124 | C_SHIFT F59B0 F60B0 125 | HIGHSPEED F51B0 F59B0 126 | 127 | 128 | # Fixed Connections 129 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_SPINE_UR0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | .mux W3_JMULTA0 51 | W3_JPO0 F54B0 52 | 53 | .mux W3_JMULTA1 54 | W3_JPO1 F54B0 55 | 56 | .mux W3_JMULTA10 57 | W3_JPO10 F54B0 58 | 59 | .mux W3_JMULTA11 60 | W3_JPO11 F54B0 61 | 62 | .mux W3_JMULTA12 63 | W3_JPO12 F54B0 64 | 65 | .mux W3_JMULTA13 66 | W3_JPO13 F54B0 67 | 68 | .mux W3_JMULTA14 69 | W3_JPO14 F54B0 70 | 71 | .mux W3_JMULTA15 72 | W3_JPO15 F54B0 73 | 74 | .mux W3_JMULTA16 75 | W3_JPO16 F54B0 76 | 77 | .mux W3_JMULTA17 78 | W3_JPO17 F54B0 79 | 80 | .mux W3_JMULTA2 81 | W3_JPO2 F54B0 82 | 83 | .mux W3_JMULTA3 84 | W3_JPO3 F54B0 85 | 86 | .mux W3_JMULTA4 87 | W3_JPO4 F54B0 88 | 89 | .mux W3_JMULTA5 90 | W3_JPO5 F54B0 91 | 92 | .mux W3_JMULTA6 93 | W3_JPO6 F54B0 94 | 95 | .mux W3_JMULTA7 96 | W3_JPO7 F54B0 97 | 98 | .mux W3_JMULTA8 99 | W3_JPO8 F54B0 100 | 101 | .mux W3_JMULTA9 102 | W3_JPO9 F54B0 103 | 104 | 105 | # Non-Routing Configuration 106 | .config_enum ALU54_7.MODE NONE 107 | ALU54B F55B0 F61B0 108 | NONE - 109 | 110 | .config_enum MULT18_5.MODE NONE 111 | MULT18X18D F56B0 F57B0 112 | NONE - 113 | 114 | .config_enum MULT18_5.REG_INPUTB_CLK CLK3 115 | CLK0 - 116 | CLK1 - 117 | CLK2 - 118 | CLK3 - 119 | NONE F55B0 F61B0 120 | 121 | .config_enum MULT18_5.SOURCEB_MODE 122 | B_C_DYNAMIC F51B0 123 | B_SHIFT F60B0 124 | C_SHIFT F59B0 F60B0 125 | HIGHSPEED F51B0 F59B0 126 | 127 | 128 | # Fixed Connections 129 | -------------------------------------------------------------------------------- /ECP5/tiledata/DSP_SPINE_UR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux G_VPTX0000 3 | G_HPRX0000 F95B0 4 | 5 | .mux G_VPTX0100 6 | G_HPRX0100 F94B0 7 | 8 | .mux G_VPTX0200 9 | G_HPRX0200 F93B0 10 | 11 | .mux G_VPTX0300 12 | G_HPRX0300 F92B0 13 | 14 | .mux G_VPTX0400 15 | G_HPRX0400 F91B0 16 | 17 | .mux G_VPTX0500 18 | G_HPRX0500 F90B0 19 | 20 | .mux G_VPTX0600 21 | G_HPRX0600 F89B0 22 | 23 | .mux G_VPTX0700 24 | G_HPRX0700 F88B0 25 | 26 | .mux G_VPTX0800 27 | G_HPRX0800 F87B0 28 | 29 | .mux G_VPTX0900 30 | G_HPRX0900 F86B0 31 | 32 | .mux G_VPTX1000 33 | G_HPRX1000 F85B0 34 | 35 | .mux G_VPTX1100 36 | G_HPRX1100 F84B0 37 | 38 | .mux G_VPTX1200 39 | G_HPRX1200 F83B0 40 | 41 | .mux G_VPTX1300 42 | G_HPRX1300 F82B0 43 | 44 | .mux G_VPTX1400 45 | G_HPRX1400 F81B0 46 | 47 | .mux G_VPTX1500 48 | G_HPRX1500 F80B0 49 | 50 | .mux W3_JMULTA0 51 | W3_JPO0 F54B0 52 | 53 | .mux W3_JMULTA1 54 | W3_JPO1 F54B0 55 | 56 | .mux W3_JMULTA10 57 | W3_JPO10 F54B0 58 | 59 | .mux W3_JMULTA11 60 | W3_JPO11 F54B0 61 | 62 | .mux W3_JMULTA12 63 | W3_JPO12 F54B0 64 | 65 | .mux W3_JMULTA13 66 | W3_JPO13 F54B0 67 | 68 | .mux W3_JMULTA14 69 | W3_JPO14 F54B0 70 | 71 | .mux W3_JMULTA15 72 | W3_JPO15 F54B0 73 | 74 | .mux W3_JMULTA16 75 | W3_JPO16 F54B0 76 | 77 | .mux W3_JMULTA17 78 | W3_JPO17 F54B0 79 | 80 | .mux W3_JMULTA2 81 | W3_JPO2 F54B0 82 | 83 | .mux W3_JMULTA3 84 | W3_JPO3 F54B0 85 | 86 | .mux W3_JMULTA4 87 | W3_JPO4 F54B0 88 | 89 | .mux W3_JMULTA5 90 | W3_JPO5 F54B0 91 | 92 | .mux W3_JMULTA6 93 | W3_JPO6 F54B0 94 | 95 | .mux W3_JMULTA7 96 | W3_JPO7 F54B0 97 | 98 | .mux W3_JMULTA8 99 | W3_JPO8 F54B0 100 | 101 | .mux W3_JMULTA9 102 | W3_JPO9 F54B0 103 | 104 | 105 | # Non-Routing Configuration 106 | .config_enum ALU54_7.MODE NONE 107 | ALU54B F55B0 F61B0 108 | NONE - 109 | 110 | .config_enum MULT18_5.MODE NONE 111 | MULT18X18D F56B0 F57B0 112 | NONE - 113 | 114 | .config_enum MULT18_5.REG_INPUTB_CLK CLK3 115 | CLK0 - 116 | CLK1 - 117 | CLK2 - 118 | CLK3 - 119 | NONE F55B0 F61B0 120 | 121 | .config_enum MULT18_5.SOURCEB_MODE 122 | B_C_DYNAMIC F51B0 123 | B_SHIFT F60B0 124 | C_SHIFT F59B0 F60B0 125 | HIGHSPEED F51B0 F59B0 126 | 127 | 128 | # Fixed Connections 129 | -------------------------------------------------------------------------------- /ECP5/tiledata/PLL1_UL/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config CLKOP_DIV 0000000 5 | F3B4 6 | F4B4 7 | F5B4 8 | F6B4 9 | F7B4 10 | F8B4 11 | F9B4 12 | 13 | .config CLKOS2_CPHASE 0000001 14 | - 15 | F0B3 16 | F1B3 17 | F2B3 18 | F3B3 19 | F4B3 20 | F5B3 21 | 22 | .config CLKOS2_DIV 0000000 23 | F9B5 24 | F0B6 25 | F1B6 26 | F2B6 27 | F3B6 28 | F4B6 29 | F5B6 30 | 31 | .config CLKOS3_CPHASE 0000000 32 | F6B3 33 | F7B3 34 | F8B3 35 | F9B3 36 | F0B4 37 | F1B4 38 | F2B4 39 | 40 | .config CLKOS3_DIV 0000000 41 | F6B6 42 | F7B6 43 | F8B6 44 | F9B6 45 | F0B7 46 | F1B7 47 | F2B7 48 | 49 | .config CLKOS_DIV 0000000 50 | F0B5 51 | F1B5 52 | F4B5 53 | F5B5 54 | F6B5 55 | F7B5 56 | F8B5 57 | 58 | .config MFG1_TEST 000 59 | F6B8 60 | F7B8 61 | F8B8 62 | 63 | .config MFG2_TEST 000 64 | F3B8 65 | F4B8 66 | F5B8 67 | 68 | .config_enum CLKOP_ENABLE DISABLED 69 | DISABLED - 70 | ENABLED F7B7 71 | 72 | .config_enum CLKOP_TRIM_DELAY 0 73 | 0 !F0B9 !F1B9 !F2B9 !F3B9 !F4B9 74 | 1 F0B9 F1B9 F2B9 !F3B9 !F4B9 75 | 2 F0B9 F1B9 !F2B9 F3B9 !F4B9 76 | 4 F0B9 F1B9 !F2B9 !F3B9 F4B9 77 | 78 | .config_enum CLKOP_TRIM_POL FALLING 79 | FALLING !F5B9 80 | RISING F5B9 81 | 82 | .config_enum CLKOS2_ENABLE DISABLED 83 | DISABLED - 84 | ENABLED F9B7 85 | 86 | .config_enum CLKOS3_ENABLE DISABLED 87 | DISABLED - 88 | ENABLED F0B8 89 | 90 | .config_enum CLKOS_ENABLE DISABLED 91 | DISABLED - 92 | ENABLED F8B7 93 | 94 | .config_enum CLKOS_TRIM_DELAY 0 95 | 0 !F1B9 !F6B9 !F7B9 !F8B9 96 | 1 F1B9 F6B9 !F7B9 !F8B9 97 | 2 F1B9 !F6B9 F7B9 !F8B9 98 | 4 F1B9 !F6B9 !F7B9 F8B9 99 | 100 | .config_enum CLKOS_TRIM_POL FALLING 101 | FALLING !F9B9 102 | RISING F9B9 103 | 104 | .config_enum DPHASE_SOURCE DISABLED 105 | DISABLED !F2B8 106 | ENABLED F2B8 107 | 108 | .config_enum OUTDIVIDER_MUXA DIVA 109 | DIVA - 110 | REFCLK F3B7 111 | 112 | .config_enum OUTDIVIDER_MUXB DIVB 113 | DIVB - 114 | REFCLK F4B7 115 | 116 | .config_enum OUTDIVIDER_MUXC DIVC 117 | DIVC - 118 | REFCLK F5B7 119 | 120 | .config_enum OUTDIVIDER_MUXD DIVD 121 | DIVD - 122 | REFCLK F6B7 123 | 124 | .config_enum SYNC_ENABLE DISABLED 125 | DISABLED !F1B8 126 | ENABLED F1B8 127 | 128 | 129 | # Fixed Connections 130 | -------------------------------------------------------------------------------- /ECP5/tiledata/PLL1_UR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config CLKOP_DIV 0000000 5 | F6B4 6 | F5B4 7 | F4B4 8 | F3B4 9 | F2B4 10 | F1B4 11 | F0B4 12 | 13 | .config CLKOS2_CPHASE 0000001 14 | - 15 | F9B3 16 | F8B3 17 | F7B3 18 | F6B3 19 | F5B3 20 | F4B3 21 | 22 | .config CLKOS2_DIV 0000000 23 | F0B5 24 | F9B6 25 | F8B6 26 | F7B6 27 | F6B6 28 | F5B6 29 | F4B6 30 | 31 | .config CLKOS3_CPHASE 0000000 32 | F3B3 33 | F2B3 34 | F1B3 35 | F0B3 36 | F9B4 37 | F8B4 38 | F7B4 39 | 40 | .config CLKOS3_DIV 0000000 41 | F3B6 42 | F2B6 43 | F1B6 44 | F0B6 45 | F9B7 46 | F8B7 47 | F7B7 48 | 49 | .config CLKOS_DIV 0000000 50 | F9B5 51 | F8B5 52 | F5B5 53 | F4B5 54 | F3B5 55 | F2B5 56 | F1B5 57 | 58 | .config MFG1_TEST 000 59 | F3B8 60 | F2B8 61 | F1B8 62 | 63 | .config MFG2_TEST 000 64 | F6B8 65 | F5B8 66 | F4B8 67 | 68 | .config_enum CLKOP_ENABLE DISABLED 69 | DISABLED - 70 | ENABLED F2B7 71 | 72 | .config_enum CLKOP_TRIM_DELAY 0 73 | 0 !F5B9 !F6B9 !F7B9 !F8B9 !F9B9 74 | 1 !F5B9 !F6B9 F7B9 F8B9 F9B9 75 | 2 !F5B9 F6B9 !F7B9 F8B9 F9B9 76 | 4 F5B9 !F6B9 !F7B9 F8B9 F9B9 77 | 78 | .config_enum CLKOP_TRIM_POL FALLING 79 | FALLING !F4B9 80 | RISING F4B9 81 | 82 | .config_enum CLKOS2_ENABLE DISABLED 83 | DISABLED - 84 | ENABLED F0B7 85 | 86 | .config_enum CLKOS3_ENABLE DISABLED 87 | DISABLED - 88 | ENABLED F9B8 89 | 90 | .config_enum CLKOS_ENABLE DISABLED 91 | DISABLED - 92 | ENABLED F1B7 93 | 94 | .config_enum CLKOS_TRIM_DELAY 0 95 | 0 !F1B9 !F2B9 !F3B9 !F8B9 96 | 1 !F1B9 !F2B9 F3B9 F8B9 97 | 2 !F1B9 F2B9 !F3B9 F8B9 98 | 4 F1B9 !F2B9 !F3B9 F8B9 99 | 100 | .config_enum CLKOS_TRIM_POL FALLING 101 | FALLING !F0B9 102 | RISING F0B9 103 | 104 | .config_enum DPHASE_SOURCE DISABLED 105 | DISABLED !F7B8 106 | ENABLED F7B8 107 | 108 | .config_enum OUTDIVIDER_MUXA DIVA 109 | DIVA - 110 | REFCLK F6B7 111 | 112 | .config_enum OUTDIVIDER_MUXB DIVB 113 | DIVB - 114 | REFCLK F5B7 115 | 116 | .config_enum OUTDIVIDER_MUXC DIVC 117 | DIVC - 118 | REFCLK F4B7 119 | 120 | .config_enum OUTDIVIDER_MUXD DIVD 121 | DIVD - 122 | REFCLK F3B7 123 | 124 | .config_enum SYNC_ENABLE DISABLED 125 | DISABLED !F8B8 126 | ENABLED F8B8 127 | 128 | 129 | # Fixed Connections 130 | -------------------------------------------------------------------------------- /ECP5/tiledata/PLL1_LR/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config CLKOP_DIV 0000000 5 | F43B0 6 | F44B0 7 | F45B0 8 | F46B0 9 | F47B0 10 | F48B0 11 | F49B0 12 | 13 | .config CLKOS2_CPHASE 0000001 14 | - 15 | F30B0 16 | F31B0 17 | F32B0 18 | F33B0 19 | F34B0 20 | F35B0 21 | 22 | .config CLKOS2_DIV 0000000 23 | F59B0 24 | F60B0 25 | F61B0 26 | F62B0 27 | F63B0 28 | F64B0 29 | F65B0 30 | 31 | .config CLKOS3_CPHASE 0000000 32 | F36B0 33 | F37B0 34 | F38B0 35 | F39B0 36 | F40B0 37 | F41B0 38 | F42B0 39 | 40 | .config CLKOS3_DIV 0000000 41 | F66B0 42 | F67B0 43 | F68B0 44 | F69B0 45 | F70B0 46 | F71B0 47 | F72B0 48 | 49 | .config CLKOS_DIV 0000000 50 | F50B0 51 | F51B0 52 | F54B0 53 | F55B0 54 | F56B0 55 | F57B0 56 | F58B0 57 | 58 | .config MFG1_TEST 000 59 | F86B0 60 | F87B0 61 | F88B0 62 | 63 | .config MFG2_TEST 000 64 | F83B0 65 | F84B0 66 | F85B0 67 | 68 | .config_enum CLKOP_ENABLE DISABLED 69 | DISABLED - 70 | ENABLED F77B0 71 | 72 | .config_enum CLKOP_TRIM_DELAY 0 73 | 0 !F90B0 !F91B0 !F92B0 !F93B0 !F94B0 74 | 1 F90B0 F91B0 F92B0 !F93B0 !F94B0 75 | 2 F90B0 F91B0 !F92B0 F93B0 !F94B0 76 | 4 F90B0 F91B0 !F92B0 !F93B0 F94B0 77 | 78 | .config_enum CLKOP_TRIM_POL FALLING 79 | FALLING !F95B0 80 | RISING F95B0 81 | 82 | .config_enum CLKOS2_ENABLE DISABLED 83 | DISABLED - 84 | ENABLED F79B0 85 | 86 | .config_enum CLKOS3_ENABLE DISABLED 87 | DISABLED - 88 | ENABLED F80B0 89 | 90 | .config_enum CLKOS_ENABLE DISABLED 91 | DISABLED - 92 | ENABLED F78B0 93 | 94 | .config_enum CLKOS_TRIM_DELAY 0 95 | 0 !F91B0 !F96B0 !F97B0 !F98B0 96 | 1 F91B0 F96B0 !F97B0 !F98B0 97 | 2 F91B0 !F96B0 F97B0 !F98B0 98 | 4 F91B0 !F96B0 !F97B0 F98B0 99 | 100 | .config_enum CLKOS_TRIM_POL FALLING 101 | FALLING !F99B0 102 | RISING F99B0 103 | 104 | .config_enum DPHASE_SOURCE DISABLED 105 | DISABLED !F82B0 106 | ENABLED F82B0 107 | 108 | .config_enum OUTDIVIDER_MUXA DIVA 109 | DIVA - 110 | REFCLK F73B0 111 | 112 | .config_enum OUTDIVIDER_MUXB DIVB 113 | DIVB - 114 | REFCLK F74B0 115 | 116 | .config_enum OUTDIVIDER_MUXC DIVC 117 | DIVC - 118 | REFCLK F75B0 119 | 120 | .config_enum OUTDIVIDER_MUXD DIVD 121 | DIVD - 122 | REFCLK F76B0 123 | 124 | .config_enum SYNC_ENABLE DISABLED 125 | DISABLED !F81B0 126 | ENABLED F81B0 127 | 128 | 129 | # Fixed Connections 130 | -------------------------------------------------------------------------------- /ECP5/tiledata/MIB_EBR7/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR3.CSDECODE_A 111 5 | !F21B0 6 | !F16B0 7 | !F10B0 8 | 9 | .config EBR3.CSDECODE_B 111 10 | !F48B0 11 | !F39B0 12 | !F34B0 13 | 14 | .config EBR3.WID 000011111 15 | - 16 | - 17 | - 18 | - 19 | - 20 | F105B0 21 | F104B0 22 | F92B0 23 | F101B0 24 | 25 | .config_enum EBR3.ADA0MUX ADA0 26 | ADA0 !F35B0 27 | INV F35B0 28 | 29 | .config_enum EBR3.ADA1MUX ADA1 30 | ADA1 !F102B0 31 | INV F102B0 32 | 33 | .config_enum EBR3.ADA2MUX ADA2 34 | ADA2 !F59B0 35 | INV F59B0 36 | 37 | .config_enum EBR3.ADA3MUX ADA3 38 | ADA3 !F31B0 39 | INV F31B0 40 | 41 | .config_enum EBR3.ADB0MUX ADB0 42 | ADB0 !F28B0 43 | INV F28B0 44 | 45 | .config_enum EBR3.ADB1MUX ADB1 46 | ADB1 !F32B0 47 | INV F32B0 48 | 49 | .config_enum EBR3.ASYNC_RESET_RELEASE SYNC 50 | ASYNC F99B0 51 | SYNC !F99B0 52 | 53 | .config_enum EBR3.CEBMUX CEB 54 | CEB !F70B0 55 | INV F70B0 56 | 57 | .config_enum EBR3.CLKBMUX CLKB 58 | CLKB !F77B0 59 | INV F77B0 60 | 61 | .config_enum EBR3.DP16KD.DATA_WIDTH_A 18 62 | 1 F13B0 F20B0 F24B0 F51B0 63 | 18 !F13B0 !F20B0 !F24B0 !F51B0 64 | 2 F13B0 !F20B0 F24B0 F51B0 65 | 4 F13B0 !F20B0 F24B0 !F51B0 66 | 9 !F13B0 !F20B0 F24B0 !F51B0 67 | 68 | .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 69 | 1 F3B0 F4B0 70 | 18 !F3B0 !F4B0 71 | 2 F3B0 F4B0 72 | 4 !F3B0 F4B0 73 | 9 !F3B0 !F4B0 74 | 75 | .config_enum EBR3.DP16KD.WRITEMODE_A WRITETHROUGH 76 | NORMAL !F75B0 77 | READBEFOREWRITE F75B0 78 | WRITETHROUGH !F75B0 79 | 80 | .config_enum EBR3.DP16KD.WRITEMODE_B WRITETHROUGH 81 | NORMAL !F7B0 82 | READBEFOREWRITE F7B0 83 | WRITETHROUGH !F7B0 84 | 85 | .config_enum EBR3.MODE NONE 86 | DP16KD F46B0 !F68B0 F84B0 87 | NONE !F46B0 !F68B0 !F84B0 88 | PDPW16KD F46B0 F68B0 F84B0 89 | 90 | .config_enum EBR3.OCEBMUX OCEB 91 | INV F56B0 92 | OCEB !F56B0 93 | 94 | .config_enum EBR3.PDPW16KD.DATA_WIDTH_R 36 95 | 1 F3B0 F4B0 96 | 18 !F3B0 !F4B0 97 | 2 F3B0 F4B0 98 | 36 !F3B0 !F4B0 99 | 4 !F3B0 F4B0 100 | 9 !F3B0 !F4B0 101 | 102 | .config_enum EBR3.REGMODE_A NOREG 103 | NOREG !F95B0 104 | OUTREG F95B0 105 | 106 | .config_enum EBR3.RESETMODE SYNC 107 | ASYNC F78B0 108 | SYNC !F78B0 109 | 110 | .config_enum EBR3.RSTAMUX RSTA 111 | INV F93B0 112 | RSTA !F93B0 113 | 114 | .config_enum EBR3.WEBMUX WEB 115 | INV F63B0 116 | WEB !F63B0 117 | 118 | 119 | # Fixed Connections 120 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CFG0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum GSR.GSRMODE NONE 5 | ACTIVE_HIGH F5B40 6 | ACTIVE_LOW F5B40 F5B42 7 | NONE - 8 | 9 | .config_enum GSR.SYNCMODE ASYNC 10 | ASYNC - 11 | NONE - 12 | SYNC F5B44 13 | 14 | .config_enum JTAG.ER1 DISABLED 15 | DISABLED - 16 | ENABLED F5B14 17 | 18 | .config_enum JTAG.ER2 DISABLED 19 | DISABLED - 20 | ENABLED F5B16 21 | 22 | .config_enum SYSCONFIG.BACKGROUND_RECONFIG OFF 23 | OFF - 24 | ON F5B18 F5B24 F5B34 25 | 26 | .config_enum SYSCONFIG.DONEPHASE T3 27 | T0 !F5B30 !F5B32 28 | T1 F5B30 !F5B32 29 | T2 !F5B30 F5B32 30 | T3 F5B30 F5B32 31 | 32 | .config_enum SYSCONFIG.ENABLE_TRANSFR DISABLE 33 | DISABLE - 34 | ENABLE F5B8 F5B18 35 | 36 | .config_enum SYSCONFIG.GOEPHASE T1 37 | T1 - 38 | T2 F5B20 39 | T3 F5B22 40 | 41 | .config_enum SYSCONFIG.GSRPHASE T2 42 | T1 !F5B36 43 | T2 F5B36 44 | T3 !F5B36 F5B38 45 | 46 | .config_enum SYSCONFIG.GWEPHASE T1 47 | T1 - 48 | T2 F5B26 49 | T3 F5B28 50 | 51 | .config_enum SYSCONFIG.SDM_PORT DISABLE 52 | DISABLE - 53 | DONE F5B4 54 | INITN - 55 | PROGRAMN - 56 | PROGRAMN_DONE F5B4 57 | PROGRAMN_DONE_INITN F5B4 58 | 59 | .config_enum TSALL.MODE NONE 60 | NONE - 61 | TSALL F5B10 62 | 63 | .config_enum TSALL.TSALL TSALL 64 | 0 - 65 | 1 F5B12 66 | INV F5B12 67 | TSALL - 68 | 69 | 70 | # Fixed Connections 71 | .fixed_conn 4300D_E9_JPADDOC S1_JTDO_JTAG 72 | 73 | .fixed_conn 9400D_E11_JPADDOC S1_JTDO_JTAG 74 | 75 | .fixed_conn S1_JCLK_GSR S1E2_JCLK0 76 | 77 | .fixed_conn S1_JF4 S1_JJTCK_JTAG 78 | 79 | .fixed_conn S1_JF5 S1_JJTDI_JTAG 80 | 81 | .fixed_conn S1_JF6 S1_JJRSTN_JTAG 82 | 83 | .fixed_conn S1_JF7 S1_JJSHIFT_JTAG 84 | 85 | .fixed_conn S1_JGSR_GSR S1E2_JC4 86 | 87 | .fixed_conn S1_JJTDO1_JTAG S1_JA4 88 | 89 | .fixed_conn S1_JJTDO2_JTAG S1_JB4 90 | 91 | .fixed_conn S1_JQ0 S1_JJUPDATE_JTAG 92 | 93 | .fixed_conn S1_JQ1 S1_JJCE1_JTAG 94 | 95 | .fixed_conn S1_JQ2 S1_JJRTI1_JTAG 96 | 97 | .fixed_conn S1_JQ3 S1_JJCE2_JTAG 98 | 99 | .fixed_conn S1_JQ4 S1_JJRTI2_JTAG 100 | 101 | .fixed_conn S1_JTCK_JTAG 4300D_E11_JPADDIC_PIO 102 | 103 | .fixed_conn S1_JTCK_JTAG 9400D_E18_JPADDIC_PIO 104 | 105 | .fixed_conn S1_JTDI_JTAG 4300D_E9_JPADDID_PIO 106 | 107 | .fixed_conn S1_JTDI_JTAG 9400D_E11_JPADDID_PIO 108 | 109 | .fixed_conn S1_JTMS_JTAG 4300D_E11_JPADDID_PIO 110 | 111 | .fixed_conn S1_JTMS_JTAG 9400D_E18_JPADDID_PIO 112 | 113 | .fixed_conn S1_JTSALLI_TSALL S1E2_JLSR0 114 | 115 | -------------------------------------------------------------------------------- /MachXO3/tiledata/DQSDLL_R/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux S1_DQSDLLCLK 3 | G_TECLK0 F3B2 4 | G_TECLK1 F3B2 F4B2 5 | S1_JDQSDLLSCLK F4B2 6 | 7 | 8 | # Non-Routing Configuration 9 | .config TDQSDLL.DEL_VAL 0000000 10 | F2B40 11 | F3B36 12 | F5B29 13 | F2B25 14 | F2B15 15 | F2B8 16 | F3B3 17 | 18 | .config_enum TDQSDLL.DEL_ADJ PLUS 19 | MINUS F5B21 20 | PLUS !F5B21 21 | 22 | .config_enum TDQSDLL.FORCE_MAX_DELAY 23 | NO !F3B25 F5B14 24 | YES F3B25 !F5B14 25 | 26 | .config_enum TDQSDLL.GSR ENABLED 27 | DISABLED F2B3 28 | ENABLED !F2B3 29 | 30 | .config_enum TDQSDLL.LOCK_SENSITIVITY LOW 31 | HIGH F5B44 32 | LOW !F5B44 33 | 34 | .config_enum TDQSDLL.MODE NONE 35 | DQSDLLC F4B29 36 | NONE - 37 | 38 | .config_enum TDQSDLL.RST RST 39 | 0 !F2B2 40 | 1 F2B2 41 | INV F2B2 42 | RST !F2B2 43 | 44 | 45 | # Fixed Connections 46 | .fixed_conn 1300_S6E2_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 47 | 48 | .fixed_conn 1300_W8_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 49 | 50 | .fixed_conn 1300_W8_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 51 | 52 | .fixed_conn 2100_S8E2_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 53 | 54 | .fixed_conn 2100_W11_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 55 | 56 | .fixed_conn 2100_W11_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 57 | 58 | .fixed_conn 4300_S11E3_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 59 | 60 | .fixed_conn 4300_W13_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 61 | 62 | .fixed_conn 4300_W13_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 63 | 64 | .fixed_conn 6900_S13E4_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 65 | 66 | .fixed_conn 6900_W19_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 67 | 68 | .fixed_conn 6900_W19_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 69 | 70 | .fixed_conn 9400_S15E4_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 71 | 72 | .fixed_conn 9400_W21_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 73 | 74 | .fixed_conn 9400_W21_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 75 | 76 | .fixed_conn S1_CLK_DQSDLL S1_DQSDLLCLK 77 | 78 | .fixed_conn S1_JCLK0 S1_JDQSDLLSCLK 79 | 80 | .fixed_conn S1_JDIVOSC_DQSDLLTEST S1_JF1 81 | 82 | .fixed_conn S1_JF0 S1_JLOCK_DQSDLL 83 | 84 | .fixed_conn S1_JFREEZE_DQSDLL S1_JB0 85 | 86 | .fixed_conn S1_JQ0 S1_JSDOUT0_DQSDLLTEST 87 | 88 | .fixed_conn S1_JQ1 S1_JSDOUT1_DQSDLLTEST 89 | 90 | .fixed_conn S1_JQ2 S1_JSDOUT2_DQSDLLTEST 91 | 92 | .fixed_conn S1_JQ3 S1_JSDOUT3_DQSDLLTEST 93 | 94 | .fixed_conn S1_JQ4 S1_JSDOUT4_DQSDLLTEST 95 | 96 | .fixed_conn S1_JQ5 S1_JSDOUT5_DQSDLLTEST 97 | 98 | .fixed_conn S1_JQ6 S1_JSDOUT6_DQSDLLTEST 99 | 100 | .fixed_conn S1_JRST_DQSDLL S1_JLSR0 101 | 102 | .fixed_conn S1_JUDDCNTLN_DQSDLL S1_JA0 103 | 104 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF8/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config CLKOP_DIV 0000000 5 | F43B0 6 | F44B0 7 | F45B0 8 | F46B0 9 | F47B0 10 | F48B0 11 | F49B0 12 | 13 | .config CLKOS2_CPHASE 0000001 14 | - 15 | F30B0 16 | F31B0 17 | F32B0 18 | F33B0 19 | F34B0 20 | F35B0 21 | 22 | .config CLKOS2_DIV 0000000 23 | F59B0 24 | F60B0 25 | F61B0 26 | F62B0 27 | F63B0 28 | F64B0 29 | F65B0 30 | 31 | .config CLKOS3_CPHASE 0000000 32 | F36B0 33 | F37B0 34 | F38B0 35 | F39B0 36 | F40B0 37 | F41B0 38 | F42B0 39 | 40 | .config CLKOS3_DIV 0000000 41 | F66B0 42 | F67B0 43 | F68B0 44 | F69B0 45 | F70B0 46 | F71B0 47 | F72B0 48 | 49 | .config CLKOS_DIV 0000000 50 | F50B0 51 | F51B0 52 | F54B0 53 | F55B0 54 | F56B0 55 | F57B0 56 | F58B0 57 | 58 | .config MFG1_TEST 000 59 | F86B0 60 | F87B0 61 | F88B0 62 | 63 | .config MFG2_TEST 000 64 | F83B0 65 | F84B0 66 | F85B0 67 | 68 | .config_enum BANK.VCCIO 1V5 69 | 1V2 !F3B0 !F16B0 !F17B0 !F18B0 70 | 1V5 !F3B0 !F16B0 !F17B0 !F18B0 71 | 1V8 F3B0 F16B0 !F17B0 !F18B0 72 | 2V5 !F3B0 !F16B0 F17B0 !F18B0 73 | 3V3 !F3B0 !F16B0 !F17B0 F18B0 74 | NONE !F3B0 !F16B0 F17B0 !F18B0 75 | 76 | .config_enum CLKOP_ENABLE DISABLED 77 | DISABLED - 78 | ENABLED F77B0 79 | 80 | .config_enum CLKOP_TRIM_DELAY 0 81 | 0 !F90B0 !F91B0 !F92B0 !F93B0 !F94B0 82 | 1 F90B0 F91B0 F92B0 !F93B0 !F94B0 83 | 2 F90B0 F91B0 !F92B0 F93B0 !F94B0 84 | 4 F90B0 F91B0 !F92B0 !F93B0 F94B0 85 | 86 | .config_enum CLKOP_TRIM_POL FALLING 87 | FALLING !F95B0 88 | RISING F95B0 89 | 90 | .config_enum CLKOS2_ENABLE DISABLED 91 | DISABLED - 92 | ENABLED F79B0 93 | 94 | .config_enum CLKOS3_ENABLE DISABLED 95 | DISABLED - 96 | ENABLED F80B0 97 | 98 | .config_enum CLKOS_ENABLE DISABLED 99 | DISABLED - 100 | ENABLED F78B0 101 | 102 | .config_enum CLKOS_TRIM_DELAY 0 103 | 0 !F91B0 !F96B0 !F97B0 !F98B0 104 | 1 F91B0 F96B0 !F97B0 !F98B0 105 | 2 F91B0 !F96B0 F97B0 !F98B0 106 | 4 F91B0 !F96B0 !F97B0 F98B0 107 | 108 | .config_enum CLKOS_TRIM_POL FALLING 109 | FALLING !F99B0 110 | RISING F99B0 111 | 112 | .config_enum DPHASE_SOURCE DISABLED 113 | DISABLED !F82B0 114 | ENABLED F82B0 115 | 116 | .config_enum OUTDIVIDER_MUXA DIVA 117 | DIVA - 118 | REFCLK F73B0 119 | 120 | .config_enum OUTDIVIDER_MUXB DIVB 121 | DIVB - 122 | REFCLK F74B0 123 | 124 | .config_enum OUTDIVIDER_MUXC DIVC 125 | DIVC - 126 | REFCLK F75B0 127 | 128 | .config_enum OUTDIVIDER_MUXD DIVD 129 | DIVD - 130 | REFCLK F76B0 131 | 132 | .config_enum SYNC_ENABLE DISABLED 133 | DISABLED !F81B0 134 | ENABLED F81B0 135 | 136 | 137 | # Fixed Connections 138 | -------------------------------------------------------------------------------- /ECP5/tiledata/BANKREF4/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config CLKOP_DIV 0000000 5 | F43B0 6 | F44B0 7 | F45B0 8 | F46B0 9 | F47B0 10 | F48B0 11 | F49B0 12 | 13 | .config CLKOS2_CPHASE 0000001 14 | - 15 | F30B0 16 | F31B0 17 | F32B0 18 | F33B0 19 | F34B0 20 | F35B0 21 | 22 | .config CLKOS2_DIV 0000000 23 | F59B0 24 | F60B0 25 | F61B0 26 | F62B0 27 | F63B0 28 | F64B0 29 | F65B0 30 | 31 | .config CLKOS3_CPHASE 0000000 32 | F36B0 33 | F37B0 34 | F38B0 35 | F39B0 36 | F40B0 37 | F41B0 38 | F42B0 39 | 40 | .config CLKOS3_DIV 0000000 41 | F66B0 42 | F67B0 43 | F68B0 44 | F69B0 45 | F70B0 46 | F71B0 47 | F72B0 48 | 49 | .config CLKOS_DIV 0000000 50 | F50B0 51 | F51B0 52 | F54B0 53 | F55B0 54 | F56B0 55 | F57B0 56 | F58B0 57 | 58 | .config MFG1_TEST 000 59 | F86B0 60 | F87B0 61 | F88B0 62 | 63 | .config MFG2_TEST 000 64 | F83B0 65 | F84B0 66 | F85B0 67 | 68 | .config_enum BANK.VCCIO NONE 69 | 1V2 !F3B0 !F16B0 !F17B0 !F18B0 70 | 1V5 !F3B0 !F16B0 !F17B0 !F18B0 71 | 1V8 F3B0 F16B0 !F17B0 !F18B0 72 | 2V5 !F3B0 !F16B0 F17B0 !F18B0 73 | 3V3 !F3B0 !F16B0 !F17B0 F18B0 74 | NONE !F3B0 !F16B0 !F17B0 !F18B0 75 | 76 | .config_enum CLKOP_ENABLE DISABLED 77 | DISABLED - 78 | ENABLED F77B0 79 | 80 | .config_enum CLKOP_TRIM_DELAY 0 81 | 0 !F90B0 !F91B0 !F92B0 !F93B0 !F94B0 82 | 1 F90B0 F91B0 F92B0 !F93B0 !F94B0 83 | 2 F90B0 F91B0 !F92B0 F93B0 !F94B0 84 | 4 F90B0 F91B0 !F92B0 !F93B0 F94B0 85 | 86 | .config_enum CLKOP_TRIM_POL FALLING 87 | FALLING !F95B0 88 | RISING F95B0 89 | 90 | .config_enum CLKOS2_ENABLE DISABLED 91 | DISABLED - 92 | ENABLED F79B0 93 | 94 | .config_enum CLKOS3_ENABLE DISABLED 95 | DISABLED - 96 | ENABLED F80B0 97 | 98 | .config_enum CLKOS_ENABLE DISABLED 99 | DISABLED - 100 | ENABLED F78B0 101 | 102 | .config_enum CLKOS_TRIM_DELAY 0 103 | 0 !F91B0 !F96B0 !F97B0 !F98B0 104 | 1 F91B0 F96B0 !F97B0 !F98B0 105 | 2 F91B0 !F96B0 F97B0 !F98B0 106 | 4 F91B0 !F96B0 !F97B0 F98B0 107 | 108 | .config_enum CLKOS_TRIM_POL FALLING 109 | FALLING !F99B0 110 | RISING F99B0 111 | 112 | .config_enum DPHASE_SOURCE DISABLED 113 | DISABLED !F82B0 114 | ENABLED F82B0 115 | 116 | .config_enum OUTDIVIDER_MUXA DIVA 117 | DIVA - 118 | REFCLK F73B0 119 | 120 | .config_enum OUTDIVIDER_MUXB DIVB 121 | DIVB - 122 | REFCLK F74B0 123 | 124 | .config_enum OUTDIVIDER_MUXC DIVC 125 | DIVC - 126 | REFCLK F75B0 127 | 128 | .config_enum OUTDIVIDER_MUXD DIVD 129 | DIVD - 130 | REFCLK F76B0 131 | 132 | .config_enum SYNC_ENABLE DISABLED 133 | DISABLED !F81B0 134 | ENABLED F81B0 135 | 136 | 137 | # Fixed Connections 138 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU4/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config DCU.CH1_CC_MATCH_1 0011111111 5 | - 6 | - 7 | - 8 | - 9 | - 10 | - 11 | - 12 | - 13 | F16B1 14 | F17B1 15 | 16 | .config DCU.CH1_CC_MATCH_2 0011111111 17 | - 18 | - 19 | - 20 | - 21 | - 22 | - 23 | - 24 | - 25 | F18B1 26 | F19B1 27 | 28 | .config DCU.CH1_CC_MATCH_3 0000000000 29 | F0B1 30 | F1B1 31 | F2B1 32 | F3B1 33 | F4B1 34 | F5B1 35 | F6B1 36 | F7B1 37 | F20B1 38 | F21B1 39 | 40 | .config DCU.CH1_CC_MATCH_4 0000000000 41 | F8B1 42 | F9B1 43 | F10B1 44 | F11B1 45 | F12B1 46 | F13B1 47 | F14B1 48 | F15B1 49 | F22B1 50 | F23B1 51 | 52 | .config DCU.CH1_LDR_CORE2TX_SEL 0 53 | F69B1 54 | 55 | .config DCU.CH1_RATE_MODE_TX 0 56 | F67B1 57 | 58 | .config DCU.CH1_RTERM_TX 00000 59 | F74B1 60 | F75B1 61 | F76B1 62 | F77B1 63 | F78B1 64 | 65 | .config DCU.CH1_TDRV_POST_EN 0 66 | F71B1 67 | 68 | .config DCU.CH1_TDRV_PRE_EN 0 69 | F70B1 70 | 71 | .config DCU.CH1_TDRV_SLICE0_CUR 000 72 | F98B1 73 | F99B1 74 | F100B1 75 | 76 | .config DCU.CH1_TDRV_SLICE0_SEL 00 77 | F82B1 78 | F83B1 79 | 80 | .config DCU.CH1_TDRV_SLICE1_CUR 000 81 | F101B1 82 | F102B1 83 | F103B1 84 | 85 | .config DCU.CH1_TDRV_SLICE1_SEL 00 86 | F84B1 87 | F85B1 88 | 89 | .config DCU.CH1_TDRV_SLICE2_CUR 00 90 | F104B1 91 | F105B1 92 | 93 | .config DCU.CH1_TDRV_SLICE2_SEL 00 94 | F86B1 95 | F87B1 96 | 97 | .config DCU.CH1_TDRV_SLICE3_CUR 00 98 | F94B1 99 | F95B1 100 | 101 | .config DCU.CH1_TDRV_SLICE3_SEL 00 102 | F88B1 103 | F89B1 104 | 105 | .config DCU.CH1_TDRV_SLICE4_CUR 00 106 | F96B1 107 | F97B1 108 | 109 | .config DCU.CH1_TDRV_SLICE4_SEL 00 110 | F90B1 111 | F91B1 112 | 113 | .config DCU.CH1_TDRV_SLICE5_SEL 00 114 | F92B1 115 | F93B1 116 | 117 | .config DCU.CH1_TPWDNB 0 118 | F66B1 119 | 120 | .config DCU.CH1_TX_CM_SEL 00 121 | F79B1 122 | F80B1 123 | 124 | .config DCU.CH1_TX_DIV11_SEL 0 125 | F68B1 126 | 127 | .config DCU.CH1_TX_POST_SIGN 0 128 | F73B1 129 | 130 | .config DCU.CH1_TX_PRE_SIGN 0 131 | F72B1 132 | 133 | .config DCU.CH1_UDF_COMMA_A 0000000000 134 | F32B1 135 | F33B1 136 | F34B1 137 | F35B1 138 | F36B1 139 | F37B1 140 | F38B1 141 | F39B1 142 | F56B1 143 | F57B1 144 | 145 | .config DCU.CH1_UDF_COMMA_B 0000000000 146 | F40B1 147 | F41B1 148 | F42B1 149 | F43B1 150 | F44B1 151 | F45B1 152 | F46B1 153 | F47B1 154 | F54B1 155 | F55B1 156 | 157 | .config DCU.CH1_UDF_COMMA_MASK 0000000000 158 | F24B1 159 | F25B1 160 | F26B1 161 | F27B1 162 | F28B1 163 | F29B1 164 | F30B1 165 | F31B1 166 | F50B1 167 | F51B1 168 | 169 | 170 | # Fixed Connections 171 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config DCU.CH0_AUTO_CALIB_EN 0 5 | F7B1 6 | 7 | .config DCU.CH0_AUTO_FACQ_EN 0 8 | F6B1 9 | 10 | .config DCU.CH0_BAND_THRESHOLD 000000 11 | F0B1 12 | F1B1 13 | F2B1 14 | F3B1 15 | F4B1 16 | F5B1 17 | 18 | .config DCU.CH0_CALIB_CK_MODE 0 19 | F8B1 20 | 21 | .config DCU.CH0_REG_BAND_OFFSET 0000 22 | F9B1 23 | F10B1 24 | F11B1 25 | F12B1 26 | 27 | .config DCU.CH0_REG_BAND_SEL 000000 28 | F16B1 29 | F17B1 30 | F18B1 31 | F19B1 32 | F20B1 33 | F21B1 34 | 35 | .config DCU.CH0_REG_IDAC_EN 0 36 | F34B1 37 | 38 | .config DCU.CH0_REG_IDAC_SEL 0000000000 39 | F24B1 40 | F25B1 41 | F26B1 42 | F27B1 43 | F28B1 44 | F29B1 45 | F30B1 46 | F31B1 47 | F32B1 48 | F33B1 49 | 50 | .config DCU.CH1_CC_MATCH_1 1100000000 51 | F90B1 52 | F91B1 53 | F92B1 54 | F93B1 55 | F94B1 56 | F95B1 57 | F96B1 58 | F97B1 59 | - 60 | - 61 | 62 | .config DCU.CH1_CC_MATCH_2 1100000000 63 | F98B1 64 | F99B1 65 | F100B1 66 | F101B1 67 | F102B1 68 | F103B1 69 | F104B1 70 | F105B1 71 | - 72 | - 73 | 74 | .config DCU.CH1_CTC_BYPASS 0 75 | F78B1 76 | 77 | .config DCU.CH1_DEC_BYPASS 0 78 | F77B1 79 | 80 | .config DCU.CH1_ENABLE_CG_ALIGN 0 81 | F57B1 82 | 83 | .config DCU.CH1_ENC_BYPASS 0 84 | F69B1 85 | 86 | .config DCU.CH1_GE_AN_ENABLE 0 87 | F54B1 88 | 89 | .config DCU.CH1_INVERT_RX 0 90 | F48B1 91 | 92 | .config DCU.CH1_INVERT_TX 0 93 | F49B1 94 | 95 | .config DCU.CH1_LSM_DISABLE 0 96 | F81B1 97 | 98 | .config DCU.CH1_MATCH_2_ENABLE 0 99 | F86B1 100 | 101 | .config DCU.CH1_MATCH_4_ENABLE 0 102 | F87B1 103 | 104 | .config DCU.CH1_MIN_IPG_CNT 00 105 | F88B1 106 | F89B1 107 | 108 | .config DCU.CH1_PCIE_EI_EN 0 109 | F64B1 110 | 111 | .config DCU.CH1_PCIE_MODE 0 112 | F42B1 113 | 114 | .config DCU.CH1_PCS_DET_TIME_SEL 00 115 | F62B1 116 | F63B1 117 | 118 | .config DCU.CH1_PRBS_ENABLE 0 119 | F56B1 120 | 121 | .config DCU.CH1_PRBS_LOCK 0 122 | F55B1 123 | 124 | .config DCU.CH1_PRBS_SELECTION 0 125 | F50B1 126 | 127 | .config DCU.CH1_RIO_MODE 0 128 | F43B1 129 | 130 | .config DCU.CH1_RX_GEAR_BYPASS 0 131 | F79B1 132 | 133 | .config DCU.CH1_RX_GEAR_MODE 0 134 | F61B1 135 | 136 | .config DCU.CH1_RX_SB_BYPASS 0 137 | F75B1 138 | 139 | .config DCU.CH1_SB_BYPASS 0 140 | F72B1 141 | 142 | .config DCU.CH1_TX_GEAR_BYPASS 0 143 | F67B1 144 | 145 | .config DCU.CH1_TX_GEAR_MODE 0 146 | F60B1 147 | 148 | .config DCU.CH1_UC_MODE 0 149 | F40B1 150 | 151 | .config DCU.CH1_WA_BYPASS 0 152 | F76B1 153 | 154 | .config DCU.CH1_WA_MODE 0 155 | F44B1 156 | 157 | 158 | # Fixed Connections 159 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CFG3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.STDBYOPT 5 | CFG F5B26 6 | USER F5B28 7 | USER_CFG F5B26 F5B28 8 | 9 | .config_enum PCNTR.TIMEOUT COUNTER 10 | BYPASS F5B22 11 | COUNTER - 12 | USER F5B34 13 | 14 | .config_enum PCNTR.WAKEUP 15 | CFG F5B32 16 | USER F5B30 17 | 18 | .config_enum SED.CHECKALWAYS DISABLED 19 | DISABLED - 20 | ENABLED F5B4 21 | 22 | .config_enum SED.CLK_FREQ 2.08 23 | 10.23 F5B8 F5B10 F5B16 24 | 10.64 F5B6 F5B8 F5B10 F5B16 25 | 11.08 F5B12 F5B16 26 | 11.57 F5B6 F5B12 F5B16 27 | 12.09 F5B8 F5B12 F5B16 28 | 12.67 F5B6 F5B8 F5B12 F5B16 29 | 13.30 F5B10 F5B12 F5B16 30 | 14.00 F5B6 F5B10 F5B12 F5B16 31 | 14.78 F5B8 F5B10 F5B12 F5B16 32 | 15.65 F5B6 F5B8 F5B10 F5B12 F5B16 33 | 16.63 F5B14 F5B16 34 | 17.73 F5B6 F5B14 F5B16 35 | 19.00 F5B8 F5B14 F5B16 36 | 2.08 - 37 | 2.15 F5B8 38 | 2.22 F5B10 39 | 2.29 F5B8 F5B10 40 | 2.38 F5B12 41 | 2.46 F5B8 F5B12 42 | 2.56 F5B10 F5B12 43 | 2.66 F5B8 F5B10 F5B12 44 | 2.77 F5B14 45 | 2.89 F5B8 F5B14 46 | 20.46 F5B6 F5B8 F5B14 F5B16 47 | 22.17 F5B10 F5B14 F5B16 48 | 24.18 F5B6 F5B10 F5B14 F5B16 49 | 26.60 F5B8 F5B10 F5B14 F5B16 50 | 29.56 F5B6 F5B8 F5B10 F5B14 F5B16 51 | 3.02 F5B10 F5B14 52 | 3.17 F5B8 F5B10 F5B14 53 | 3.33 F5B12 F5B14 54 | 3.50 F5B8 F5B12 F5B14 55 | 3.69 F5B10 F5B12 F5B14 56 | 3.91 F5B8 F5B10 F5B12 F5B14 57 | 33.25 F5B12 F5B14 F5B16 58 | 4.16 F5B6 59 | 4.29 F5B6 F5B8 60 | 4.43 F5B6 F5B10 61 | 4.59 F5B6 F5B8 F5B10 62 | 4.75 F5B6 F5B12 63 | 4.93 F5B6 F5B8 F5B12 64 | 5.12 F5B6 F5B10 F5B12 65 | 5.32 F5B6 F5B8 F5B10 F5B12 66 | 5.54 F5B6 F5B14 67 | 5.78 F5B6 F5B8 F5B14 68 | 6.05 F5B6 F5B10 F5B14 69 | 6.33 F5B6 F5B8 F5B10 F5B14 70 | 6.65 F5B6 F5B12 F5B14 71 | 7.00 F5B6 F5B8 F5B12 F5B14 72 | 7.39 F5B6 F5B10 F5B12 F5B14 73 | 7.82 F5B6 F5B8 F5B10 F5B12 F5B14 74 | 8.31 F5B16 75 | 8.58 F5B6 F5B16 76 | 8.87 F5B8 F5B16 77 | 9.17 F5B6 F5B8 F5B16 78 | 9.50 F5B10 F5B16 79 | 9.85 F5B6 F5B10 F5B16 80 | 81 | .config_enum SED.MODE NONE 82 | NONE - 83 | SEDFA F5B20 84 | SEDFB F5B2 F5B20 85 | 86 | .config_enum SED.SEDEXCLK_USED NO 87 | NO F5B18 88 | YES !F5B18 89 | 90 | 91 | # Fixed Connections 92 | .fixed_conn S1W2_JF4 S1W3_JAUTODONE_SED 93 | 94 | .fixed_conn S1W2_JF6 S1W3_JSEDDONE_SED 95 | 96 | .fixed_conn S1W2_JF7 S1W3_JSEDERR_SED 97 | 98 | .fixed_conn S1W2_JQ0 S1W3_JSEDINPROG_SED 99 | 100 | .fixed_conn S1W3_JSEDENABLE_SED S1W2_JLSR0 101 | 102 | .fixed_conn S1W3_JSEDEXCLK_SED S1W2_JCLK0 103 | 104 | .fixed_conn S1W3_JSEDFRCERR_SED S1W2_JA0 105 | 106 | .fixed_conn S1W3_JSEDSTART_SED S1W2_JLSR1 107 | 108 | .fixed_conn S1W3_SEDSTDBY_SED S1W3_SEDSTDBY_OSC 109 | 110 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CFG3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.STDBYOPT 5 | CFG F5B26 6 | USER F5B28 7 | USER_CFG F5B26 F5B28 8 | 9 | .config_enum PCNTR.TIMEOUT COUNTER 10 | BYPASS F5B22 11 | COUNTER - 12 | USER F5B34 13 | 14 | .config_enum PCNTR.WAKEUP 15 | CFG F5B32 16 | USER F5B30 17 | 18 | .config_enum SED.CHECKALWAYS DISABLED 19 | DISABLED - 20 | ENABLED F5B4 21 | 22 | .config_enum SED.CLK_FREQ 2.08 23 | 10.23 F5B8 F5B10 F5B16 24 | 10.64 F5B6 F5B8 F5B10 F5B16 25 | 11.08 F5B12 F5B16 26 | 11.57 F5B6 F5B12 F5B16 27 | 12.09 F5B8 F5B12 F5B16 28 | 12.67 F5B6 F5B8 F5B12 F5B16 29 | 13.30 F5B10 F5B12 F5B16 30 | 14.00 F5B6 F5B10 F5B12 F5B16 31 | 14.78 F5B8 F5B10 F5B12 F5B16 32 | 15.65 F5B6 F5B8 F5B10 F5B12 F5B16 33 | 16.63 F5B14 F5B16 34 | 17.73 F5B6 F5B14 F5B16 35 | 19.00 F5B8 F5B14 F5B16 36 | 2.08 - 37 | 2.15 F5B8 38 | 2.22 F5B10 39 | 2.29 F5B8 F5B10 40 | 2.38 F5B12 41 | 2.46 F5B8 F5B12 42 | 2.56 F5B10 F5B12 43 | 2.66 F5B8 F5B10 F5B12 44 | 2.77 F5B14 45 | 2.89 F5B8 F5B14 46 | 20.46 F5B6 F5B8 F5B14 F5B16 47 | 22.17 F5B10 F5B14 F5B16 48 | 24.18 F5B6 F5B10 F5B14 F5B16 49 | 26.60 F5B8 F5B10 F5B14 F5B16 50 | 29.56 F5B6 F5B8 F5B10 F5B14 F5B16 51 | 3.02 F5B10 F5B14 52 | 3.17 F5B8 F5B10 F5B14 53 | 3.33 F5B12 F5B14 54 | 3.50 F5B8 F5B12 F5B14 55 | 3.69 F5B10 F5B12 F5B14 56 | 3.91 F5B8 F5B10 F5B12 F5B14 57 | 33.25 F5B12 F5B14 F5B16 58 | 4.16 F5B6 59 | 4.29 F5B6 F5B8 60 | 4.43 F5B6 F5B10 61 | 4.59 F5B6 F5B8 F5B10 62 | 4.75 F5B6 F5B12 63 | 4.93 F5B6 F5B8 F5B12 64 | 5.12 F5B6 F5B10 F5B12 65 | 5.32 F5B6 F5B8 F5B10 F5B12 66 | 5.54 F5B6 F5B14 67 | 5.78 F5B6 F5B8 F5B14 68 | 6.05 F5B6 F5B10 F5B14 69 | 6.33 F5B6 F5B8 F5B10 F5B14 70 | 6.65 F5B6 F5B12 F5B14 71 | 7.00 F5B6 F5B8 F5B12 F5B14 72 | 7.39 F5B6 F5B10 F5B12 F5B14 73 | 7.82 F5B6 F5B8 F5B10 F5B12 F5B14 74 | 8.31 F5B16 75 | 8.58 F5B6 F5B16 76 | 8.87 F5B8 F5B16 77 | 9.17 F5B6 F5B8 F5B16 78 | 9.50 F5B10 F5B16 79 | 9.85 F5B6 F5B10 F5B16 80 | 81 | .config_enum SED.MODE NONE 82 | NONE - 83 | SEDFA F5B20 84 | SEDFB F5B2 F5B20 85 | 86 | .config_enum SED.SEDEXCLK_USED NO 87 | NO F5B18 88 | YES !F5B18 89 | 90 | 91 | # Fixed Connections 92 | .fixed_conn S1W2_JF4 S1W3_JAUTODONE_SED 93 | 94 | .fixed_conn S1W2_JF6 S1W3_JSEDDONE_SED 95 | 96 | .fixed_conn S1W2_JF7 S1W3_JSEDERR_SED 97 | 98 | .fixed_conn S1W2_JQ0 S1W3_JSEDINPROG_SED 99 | 100 | .fixed_conn S1W3_JSEDENABLE_SED S1W2_JLSR0 101 | 102 | .fixed_conn S1W3_JSEDEXCLK_SED S1W2_JCLK0 103 | 104 | .fixed_conn S1W3_JSEDFRCERR_SED S1W2_JA0 105 | 106 | .fixed_conn S1W3_JSEDSTART_SED S1W2_JLSR1 107 | 108 | .fixed_conn S1W3_SEDSTDBY_SED S1W3_SEDSTDBY_OSC 109 | 110 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/CFG3/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PCNTR.STDBYOPT 5 | CFG F5B26 6 | USER F5B28 7 | USER_CFG F5B26 F5B28 8 | 9 | .config_enum PCNTR.TIMEOUT COUNTER 10 | BYPASS F5B22 11 | COUNTER - 12 | USER F5B34 13 | 14 | .config_enum PCNTR.WAKEUP 15 | CFG F5B32 16 | USER F5B30 17 | 18 | .config_enum SED.CHECKALWAYS DISABLED 19 | DISABLED - 20 | ENABLED F5B4 21 | 22 | .config_enum SED.CLK_FREQ 2.08 23 | 10.23 F5B8 F5B10 F5B16 24 | 10.64 F5B6 F5B8 F5B10 F5B16 25 | 11.08 F5B12 F5B16 26 | 11.57 F5B6 F5B12 F5B16 27 | 12.09 F5B8 F5B12 F5B16 28 | 12.67 F5B6 F5B8 F5B12 F5B16 29 | 13.30 F5B10 F5B12 F5B16 30 | 14.00 F5B6 F5B10 F5B12 F5B16 31 | 14.78 F5B8 F5B10 F5B12 F5B16 32 | 15.65 F5B6 F5B8 F5B10 F5B12 F5B16 33 | 16.63 F5B14 F5B16 34 | 17.73 F5B6 F5B14 F5B16 35 | 19.00 F5B8 F5B14 F5B16 36 | 2.08 - 37 | 2.15 F5B8 38 | 2.22 F5B10 39 | 2.29 F5B8 F5B10 40 | 2.38 F5B12 41 | 2.46 F5B8 F5B12 42 | 2.56 F5B10 F5B12 43 | 2.66 F5B8 F5B10 F5B12 44 | 2.77 F5B14 45 | 2.89 F5B8 F5B14 46 | 20.46 F5B6 F5B8 F5B14 F5B16 47 | 22.17 F5B10 F5B14 F5B16 48 | 24.18 F5B6 F5B10 F5B14 F5B16 49 | 26.60 F5B8 F5B10 F5B14 F5B16 50 | 29.56 F5B6 F5B8 F5B10 F5B14 F5B16 51 | 3.02 F5B10 F5B14 52 | 3.17 F5B8 F5B10 F5B14 53 | 3.33 F5B12 F5B14 54 | 3.50 F5B8 F5B12 F5B14 55 | 3.69 F5B10 F5B12 F5B14 56 | 3.91 F5B8 F5B10 F5B12 F5B14 57 | 33.25 F5B12 F5B14 F5B16 58 | 4.16 F5B6 59 | 4.29 F5B6 F5B8 60 | 4.43 F5B6 F5B10 61 | 4.59 F5B6 F5B8 F5B10 62 | 4.75 F5B6 F5B12 63 | 4.93 F5B6 F5B8 F5B12 64 | 5.12 F5B6 F5B10 F5B12 65 | 5.32 F5B6 F5B8 F5B10 F5B12 66 | 5.54 F5B6 F5B14 67 | 5.78 F5B6 F5B8 F5B14 68 | 6.05 F5B6 F5B10 F5B14 69 | 6.33 F5B6 F5B8 F5B10 F5B14 70 | 6.65 F5B6 F5B12 F5B14 71 | 7.00 F5B6 F5B8 F5B12 F5B14 72 | 7.39 F5B6 F5B10 F5B12 F5B14 73 | 7.82 F5B6 F5B8 F5B10 F5B12 F5B14 74 | 8.31 F5B16 75 | 8.58 F5B6 F5B16 76 | 8.87 F5B8 F5B16 77 | 9.17 F5B6 F5B8 F5B16 78 | 9.50 F5B10 F5B16 79 | 9.85 F5B6 F5B10 F5B16 80 | 81 | .config_enum SED.MODE NONE 82 | NONE - 83 | SEDFA F5B20 84 | SEDFB F5B2 F5B20 85 | 86 | .config_enum SED.SEDEXCLK_USED NO 87 | NO F5B18 88 | YES !F5B18 89 | 90 | 91 | # Fixed Connections 92 | .fixed_conn S1W2_JF4 S1W3_JAUTODONE_SED 93 | 94 | .fixed_conn S1W2_JF6 S1W3_JSEDDONE_SED 95 | 96 | .fixed_conn S1W2_JF7 S1W3_JSEDERR_SED 97 | 98 | .fixed_conn S1W2_JQ0 S1W3_JSEDINPROG_SED 99 | 100 | .fixed_conn S1W3_JSEDENABLE_SED S1W2_JLSR0 101 | 102 | .fixed_conn S1W3_JSEDEXCLK_SED S1W2_JCLK0 103 | 104 | .fixed_conn S1W3_JSEDFRCERR_SED S1W2_JA0 105 | 106 | .fixed_conn S1W3_JSEDSTART_SED S1W2_JLSR1 107 | 108 | .fixed_conn S1W3_SEDSTDBY_SED S1W3_SEDSTDBY_OSC 109 | 110 | -------------------------------------------------------------------------------- /MachXO2/tiledata/DQSDLL_R/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux S1_DQSDLLCLK 3 | G_TECLK0 F3B2 4 | G_TECLK1 F3B2 F4B2 5 | S1_JDQSDLLSCLK F4B2 6 | 7 | 8 | # Non-Routing Configuration 9 | .config TDQSDLL.DEL_VAL 0000000 10 | F2B40 11 | F3B36 12 | F5B29 13 | F2B25 14 | F2B15 15 | F2B8 16 | F3B3 17 | 18 | .config_enum TDQSDLL.DEL_ADJ PLUS 19 | MINUS F5B21 20 | PLUS !F5B21 21 | 22 | .config_enum TDQSDLL.FORCE_MAX_DELAY 23 | NO !F3B25 F5B14 24 | YES F3B25 !F5B14 25 | 26 | .config_enum TDQSDLL.GSR ENABLED 27 | DISABLED F2B3 28 | ENABLED !F2B3 29 | 30 | .config_enum TDQSDLL.LOCK_SENSITIVITY LOW 31 | HIGH F5B44 32 | LOW !F5B44 33 | 34 | .config_enum TDQSDLL.MODE NONE 35 | DQSDLLC F4B29 36 | NONE - 37 | 38 | .config_enum TDQSDLL.RST RST 39 | 0 !F2B2 40 | 1 F2B2 41 | INV F2B2 42 | RST !F2B2 43 | 44 | 45 | # Fixed Connections 46 | .fixed_conn 1200_S6E2_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 47 | 48 | .fixed_conn 1200_S6E2_JDQSDEL0_DQS S1_JDQSDEL_DQSDLL 49 | 50 | .fixed_conn 1200_S6E2_JDQSDEL1_DQS S1_JDQSDEL_DQSDLL 51 | 52 | .fixed_conn 1200_W8_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 53 | 54 | .fixed_conn 1200_W8_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 55 | 56 | .fixed_conn 2000_S8E2_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 57 | 58 | .fixed_conn 2000_S8E2_JDQSDEL0_DQS S1_JDQSDEL_DQSDLL 59 | 60 | .fixed_conn 2000_S8E2_JDQSDEL1_DQS S1_JDQSDEL_DQSDLL 61 | 62 | .fixed_conn 2000_W11_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 63 | 64 | .fixed_conn 2000_W11_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 65 | 66 | .fixed_conn 4000_S11E3_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 67 | 68 | .fixed_conn 4000_S11E3_JDQSDEL0_DQS S1_JDQSDEL_DQSDLL 69 | 70 | .fixed_conn 4000_S11E3_JDQSDEL1_DQS S1_JDQSDEL_DQSDLL 71 | 72 | .fixed_conn 4000_W13_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 73 | 74 | .fixed_conn 4000_W13_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 75 | 76 | .fixed_conn 7000_S13E4_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 77 | 78 | .fixed_conn 7000_S13E4_JDQSDEL0_DQS S1_JDQSDEL_DQSDLL 79 | 80 | .fixed_conn 7000_S13E4_JDQSDEL1_DQS S1_JDQSDEL_DQSDLL 81 | 82 | .fixed_conn 7000_W19_JDQSDEL0_DLLDEL S1_JDQSDEL_DQSDLL 83 | 84 | .fixed_conn 7000_W19_JDQSDEL1_DLLDEL S1_JDQSDEL_DQSDLL 85 | 86 | .fixed_conn S1_CLK_DQSDLL S1_DQSDLLCLK 87 | 88 | .fixed_conn S1_JCLK0 S1_JDQSDLLSCLK 89 | 90 | .fixed_conn S1_JDIVOSC_DQSDLLTEST S1_JF1 91 | 92 | .fixed_conn S1_JF0 S1_JLOCK_DQSDLL 93 | 94 | .fixed_conn S1_JFREEZE_DQSDLL S1_JB0 95 | 96 | .fixed_conn S1_JQ0 S1_JSDOUT0_DQSDLLTEST 97 | 98 | .fixed_conn S1_JQ1 S1_JSDOUT1_DQSDLLTEST 99 | 100 | .fixed_conn S1_JQ2 S1_JSDOUT2_DQSDLLTEST 101 | 102 | .fixed_conn S1_JQ3 S1_JSDOUT3_DQSDLLTEST 103 | 104 | .fixed_conn S1_JQ4 S1_JSDOUT4_DQSDLLTEST 105 | 106 | .fixed_conn S1_JQ5 S1_JSDOUT5_DQSDLLTEST 107 | 108 | .fixed_conn S1_JQ6 S1_JSDOUT6_DQSDLLTEST 109 | 110 | .fixed_conn S1_JRST_DQSDLL S1_JLSR0 111 | 112 | .fixed_conn S1_JUDDCNTLN_DQSDLL S1_JA0 113 | 114 | -------------------------------------------------------------------------------- /MachXO2/tiledata/DQSDLL_L/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux N1_DQSDLLCLK 3 | G_BECLK0 F2B2 4 | G_BECLK1 F1B2 F2B2 5 | N1_JDQSDLLSCLK F1B2 6 | 7 | 8 | # Non-Routing Configuration 9 | .config BDQSDLL.DEL_VAL 0000000 10 | F3B40 11 | F2B36 12 | F0B29 13 | F3B25 14 | F3B15 15 | F3B8 16 | F2B3 17 | 18 | .config_enum BDQSDLL.DEL_ADJ PLUS 19 | MINUS F0B21 20 | PLUS !F0B21 21 | 22 | .config_enum BDQSDLL.FORCE_MAX_DELAY 23 | NO F0B14 !F2B25 24 | YES !F0B14 F2B25 25 | 26 | .config_enum BDQSDLL.GSR ENABLED 27 | DISABLED F3B3 28 | ENABLED !F3B3 29 | 30 | .config_enum BDQSDLL.LOCK_SENSITIVITY LOW 31 | HIGH F0B44 32 | LOW !F0B44 33 | 34 | .config_enum BDQSDLL.MODE NONE 35 | DQSDLLC F1B29 36 | NONE - 37 | 38 | .config_enum BDQSDLL.RST RST 39 | 0 !F3B2 40 | 1 F3B2 41 | INV F3B2 42 | RST !F3B2 43 | 44 | 45 | # Fixed Connections 46 | .fixed_conn 1200_E11_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 47 | 48 | .fixed_conn 1200_E11_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 49 | 50 | .fixed_conn 1200_N6W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 51 | 52 | .fixed_conn 1200_N6W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 53 | 54 | .fixed_conn 1200_N6W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 55 | 56 | .fixed_conn 2000_E12_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 57 | 58 | .fixed_conn 2000_E12_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 59 | 60 | .fixed_conn 2000_N7W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 61 | 62 | .fixed_conn 2000_N7W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 63 | 64 | .fixed_conn 2000_N7W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 65 | 66 | .fixed_conn 4000_E14_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 67 | 68 | .fixed_conn 4000_E14_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 69 | 70 | .fixed_conn 4000_N11W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 71 | 72 | .fixed_conn 4000_N11W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 73 | 74 | .fixed_conn 4000_N11W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 75 | 76 | .fixed_conn 7000_E17_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 77 | 78 | .fixed_conn 7000_E17_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 79 | 80 | .fixed_conn 7000_N14W2_JDQSDEL0_DLLDEL N1_JDQSDEL_DQSDLL 81 | 82 | .fixed_conn 7000_N14W2_JDQSDEL1_DLLDEL N1_JDQSDEL_DQSDLL 83 | 84 | .fixed_conn 7000_N14W2_JDQSDEL2_DLLDEL N1_JDQSDEL_DQSDLL 85 | 86 | .fixed_conn N1_CLK_DQSDLL N1_DQSDLLCLK 87 | 88 | .fixed_conn N1_JCLK0 N1_JDQSDLLSCLK 89 | 90 | .fixed_conn N1_JDIVOSC_DQSDLLTEST N1_JF1 91 | 92 | .fixed_conn N1_JF0 N1_JLOCK_DQSDLL 93 | 94 | .fixed_conn N1_JFREEZE_DQSDLL N1_JB0 95 | 96 | .fixed_conn N1_JQ0 N1_JSDOUT0_DQSDLLTEST 97 | 98 | .fixed_conn N1_JQ1 N1_JSDOUT1_DQSDLLTEST 99 | 100 | .fixed_conn N1_JQ2 N1_JSDOUT2_DQSDLLTEST 101 | 102 | .fixed_conn N1_JQ3 N1_JSDOUT3_DQSDLLTEST 103 | 104 | .fixed_conn N1_JQ4 N1_JSDOUT4_DQSDLLTEST 105 | 106 | .fixed_conn N1_JQ5 N1_JSDOUT5_DQSDLLTEST 107 | 108 | .fixed_conn N1_JQ6 N1_JSDOUT6_DQSDLLTEST 109 | 110 | .fixed_conn N1_JRST_DQSDLL N1_JLSR0 111 | 112 | .fixed_conn N1_JUDDCNTLN_DQSDLL N1_JA0 113 | 114 | -------------------------------------------------------------------------------- /MachXO2/tiledata/CFG0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum GSR.GSRMODE NONE 5 | ACTIVE_HIGH F5B40 6 | ACTIVE_LOW F5B40 F5B42 7 | NONE - 8 | 9 | .config_enum GSR.SYNCMODE ASYNC 10 | ASYNC - 11 | NONE - 12 | SYNC F5B44 13 | 14 | .config_enum JTAG.ER1 DISABLED 15 | DISABLED - 16 | ENABLED F5B14 17 | 18 | .config_enum JTAG.ER2 DISABLED 19 | DISABLED - 20 | ENABLED F5B16 21 | 22 | .config_enum SYSCONFIG.BACKGROUND_RECONFIG OFF 23 | OFF - 24 | ON F5B18 F5B24 F5B34 25 | 26 | .config_enum SYSCONFIG.DONEPHASE T3 27 | T0 !F5B30 !F5B32 28 | T1 F5B30 !F5B32 29 | T2 !F5B30 F5B32 30 | T3 F5B30 F5B32 31 | 32 | .config_enum SYSCONFIG.ENABLE_TRANSFR DISABLE 33 | DISABLE - 34 | ENABLE F5B8 F5B18 35 | 36 | .config_enum SYSCONFIG.GOEPHASE T1 37 | T1 - 38 | T2 F5B20 39 | T3 F5B22 40 | 41 | .config_enum SYSCONFIG.GSRPHASE T2 42 | T1 !F5B36 43 | T2 F5B36 44 | T3 !F5B36 F5B38 45 | 46 | .config_enum SYSCONFIG.GWEPHASE T1 47 | T1 - 48 | T2 F5B26 49 | T3 F5B28 50 | 51 | .config_enum SYSCONFIG.SDM_PORT DISABLE 52 | DISABLE - 53 | DONE F5B4 54 | INITN - 55 | PROGRAMN - 56 | PROGRAMN_DONE F5B4 57 | PROGRAMN_DONE_INITN F5B4 58 | 59 | .config_enum TSALL.MODE NONE 60 | NONE - 61 | TSALL F5B10 62 | 63 | .config_enum TSALL.TSALL TSALL 64 | 0 - 65 | 1 F5B12 66 | INV F5B12 67 | TSALL - 68 | 69 | 70 | # Fixed Connections 71 | .fixed_conn 1200_E6_JPADDOC S1_JTDO_JTAG 72 | 73 | .fixed_conn 2000_E8_JPADDOC S1_JTDO_JTAG 74 | 75 | .fixed_conn 4000_E9_JPADDOC S1_JTDO_JTAG 76 | 77 | .fixed_conn 7000_E10_JPADDOC S1_JTDO_JTAG 78 | 79 | .fixed_conn S1_JCLK_GSR S1E2_JCLK0 80 | 81 | .fixed_conn S1_JF4 S1_JJTCK_JTAG 82 | 83 | .fixed_conn S1_JF5 S1_JJTDI_JTAG 84 | 85 | .fixed_conn S1_JF6 S1_JJRSTN_JTAG 86 | 87 | .fixed_conn S1_JF7 S1_JJSHIFT_JTAG 88 | 89 | .fixed_conn S1_JGSR_GSR S1E2_JC4 90 | 91 | .fixed_conn S1_JJTDO1_JTAG S1_JA4 92 | 93 | .fixed_conn S1_JJTDO2_JTAG S1_JB4 94 | 95 | .fixed_conn S1_JQ0 S1_JJUPDATE_JTAG 96 | 97 | .fixed_conn S1_JQ1 S1_JJCE1_JTAG 98 | 99 | .fixed_conn S1_JQ2 S1_JJRTI1_JTAG 100 | 101 | .fixed_conn S1_JQ3 S1_JJCE2_JTAG 102 | 103 | .fixed_conn S1_JQ4 S1_JJRTI2_JTAG 104 | 105 | .fixed_conn S1_JTCK_JTAG 1200_E7_JPADDIC_PIO 106 | 107 | .fixed_conn S1_JTCK_JTAG 2000_E12_JPADDIC_PIO 108 | 109 | .fixed_conn S1_JTCK_JTAG 4000_E11_JPADDIC_PIO 110 | 111 | .fixed_conn S1_JTCK_JTAG 7000_E13_JPADDIC_PIO 112 | 113 | .fixed_conn S1_JTDI_JTAG 1200_E6_JPADDID_PIO 114 | 115 | .fixed_conn S1_JTDI_JTAG 2000_E8_JPADDID_PIO 116 | 117 | .fixed_conn S1_JTDI_JTAG 4000_E9_JPADDID_PIO 118 | 119 | .fixed_conn S1_JTDI_JTAG 7000_E10_JPADDID_PIO 120 | 121 | .fixed_conn S1_JTMS_JTAG 1200_E7_JPADDID_PIO 122 | 123 | .fixed_conn S1_JTMS_JTAG 2000_E12_JPADDID_PIO 124 | 125 | .fixed_conn S1_JTMS_JTAG 4000_E11_JPADDID_PIO 126 | 127 | .fixed_conn S1_JTMS_JTAG 7000_E13_JPADDID_PIO 128 | 129 | .fixed_conn S1_JTSALLI_TSALL S1E2_JLSR0 130 | 131 | -------------------------------------------------------------------------------- /ECP5/tiledata/PIOT1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum PIOA.BASE_TYPE BIDIR_LVCMOS12 5 | BIDIR_LVCMOS12 - 6 | BIDIR_LVCMOS15 - 7 | BIDIR_LVCMOS18 - 8 | BIDIR_LVCMOS25 - 9 | BIDIR_LVCMOS33 - 10 | BIDIR_LVTTL33 - 11 | INPUT_LVCMOS12 - 12 | INPUT_LVCMOS15 - 13 | INPUT_LVCMOS18 - 14 | INPUT_LVCMOS25 - 15 | INPUT_LVCMOS33 - 16 | INPUT_LVTTL33 - 17 | NONE - 18 | OUTPUT_HSUL12 - 19 | OUTPUT_HSUL12D - 20 | OUTPUT_LVCMOS12 - 21 | OUTPUT_LVCMOS12D F7B0 22 | OUTPUT_LVCMOS15 - 23 | OUTPUT_LVCMOS15D F7B0 24 | OUTPUT_LVCMOS18 - 25 | OUTPUT_LVCMOS18D F7B0 26 | OUTPUT_LVCMOS25 - 27 | OUTPUT_LVCMOS25D F7B0 28 | OUTPUT_LVCMOS33 - 29 | OUTPUT_LVCMOS33D F7B0 F15B0 F16B0 F17B0 30 | OUTPUT_LVDS25E F7B0 31 | OUTPUT_LVPECL33E F7B0 F15B0 F16B0 F17B0 F18B0 32 | OUTPUT_LVTTL33 - 33 | OUTPUT_SSTL135D_I F7B0 F16B0 34 | OUTPUT_SSTL135D_II F7B0 F18B0 35 | OUTPUT_SSTL135_I - 36 | OUTPUT_SSTL135_II - 37 | OUTPUT_SSTL15D_I F7B0 F16B0 38 | OUTPUT_SSTL15D_II F7B0 F18B0 39 | OUTPUT_SSTL15_I - 40 | OUTPUT_SSTL15_II - 41 | OUTPUT_SSTL18D_I F7B0 42 | OUTPUT_SSTL18D_II F7B0 F15B0 F16B0 F17B0 F18B0 43 | OUTPUT_SSTL18_I - 44 | OUTPUT_SSTL18_II - 45 | 46 | .config_enum PIOB.BASE_TYPE NONE 47 | BIDIR_LVCMOS12 F2B0 F4B0 F9B0 48 | BIDIR_LVCMOS15 !F2B0 F9B0 49 | BIDIR_LVCMOS18 !F2B0 F9B0 50 | BIDIR_LVCMOS25 F2B0 F3B0 F9B0 F14B0 51 | BIDIR_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0 52 | BIDIR_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0 53 | INPUT_LVCMOS12 F2B0 F4B0 F9B0 54 | INPUT_LVCMOS15 !F2B0 F9B0 55 | INPUT_LVCMOS18 !F2B0 F9B0 56 | INPUT_LVCMOS25 F2B0 F3B0 F9B0 F14B0 57 | INPUT_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0 58 | INPUT_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0 59 | NONE F2B0 60 | OUTPUT_HSUL12 F2B0 F7B0 F9B0 61 | OUTPUT_LVCMOS12 F2B0 F7B0 F9B0 62 | OUTPUT_LVCMOS15 F2B0 F7B0 F9B0 63 | OUTPUT_LVCMOS18 F2B0 F7B0 F9B0 64 | OUTPUT_LVCMOS25 F2B0 F7B0 F9B0 65 | OUTPUT_LVCMOS33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0 66 | OUTPUT_LVTTL33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0 67 | OUTPUT_SSTL135_I F2B0 F7B0 F9B0 F16B0 68 | OUTPUT_SSTL135_II F2B0 F7B0 F9B0 F17B0 69 | OUTPUT_SSTL15_I F2B0 F7B0 F9B0 F16B0 70 | OUTPUT_SSTL15_II F2B0 F7B0 F9B0 F17B0 71 | OUTPUT_SSTL18_I F2B0 F7B0 F9B0 72 | OUTPUT_SSTL18_II F2B0 F7B0 F9B0 F15B0 F16B0 F17B0 F18B0 73 | 74 | .config_enum PIOB.CLAMP 75 | OFF !F9B0 76 | ON F9B0 77 | 78 | .config_enum PIOB.DRIVE 79 | 12 !F15B0 !F16B0 !F17B0 F18B0 !F19B0 80 | 16 F15B0 F16B0 F17B0 F18B0 !F19B0 81 | 4 !F15B0 !F16B0 F17B0 F18B0 F19B0 82 | 8 F15B0 F16B0 F17B0 !F18B0 !F19B0 83 | 84 | .config_enum PIOB.HYSTERESIS OFF 85 | OFF !F14B0 86 | ON F14B0 87 | 88 | .config_enum PIOB.OPENDRAIN 89 | OFF F9B0 F15B0 F16B0 F17B0 !F26B0 90 | ON !F9B0 !F15B0 !F16B0 !F17B0 F26B0 91 | 92 | .config_enum PIOB.PULLMODE DOWN 93 | DOWN !F7B0 !F8B0 94 | NONE F7B0 !F8B0 95 | UP F7B0 F8B0 96 | 97 | .config_enum PIOB.SLEWRATE SLOW 98 | FAST F25B0 99 | SLOW !F25B0 100 | 101 | 102 | # Fixed Connections 103 | -------------------------------------------------------------------------------- /ECP5/tiledata/DCU1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux W1_CH0_RX_REFCLK 3 | W1_JCH0RXREFCLKCIB F78B1 4 | 5 | 6 | # Non-Routing Configuration 7 | .config DCU.CH0_LDR_CORE2TX_SEL 0 8 | F27B1 9 | 10 | .config DCU.CH0_LDR_RX2CORE_SEL 0 11 | F77B1 12 | 13 | .config DCU.CH0_LEQ_OFFSET_SEL 0 14 | F90B1 15 | 16 | .config DCU.CH0_LEQ_OFFSET_TRIM 000 17 | F91B1 18 | F92B1 19 | F93B1 20 | 21 | .config DCU.CH0_RATE_MODE_RX 0 22 | F75B1 23 | 24 | .config DCU.CH0_RATE_MODE_TX 0 25 | F25B1 26 | 27 | .config DCU.CH0_RCV_DCC_EN 0 28 | F79B1 29 | 30 | .config DCU.CH0_REQ_EN 0 31 | F98B1 32 | 33 | .config DCU.CH0_REQ_LVL_SET 00 34 | F103B1 35 | F104B1 36 | 37 | .config DCU.CH0_RPWDNB 0 38 | F74B1 39 | 40 | .config DCU.CH0_RTERM_RX 00000 41 | F82B1 42 | F83B1 43 | F84B1 44 | F85B1 45 | F86B1 46 | 47 | .config DCU.CH0_RTERM_TX 00000 48 | F32B1 49 | F33B1 50 | F34B1 51 | F35B1 52 | F36B1 53 | 54 | .config DCU.CH0_RXIN_CM 00 55 | F88B1 56 | F89B1 57 | 58 | .config DCU.CH0_RXTERM_CM 00 59 | F80B1 60 | F81B1 61 | 62 | .config DCU.CH0_RX_DIV11_SEL 0 63 | F76B1 64 | 65 | .config DCU.CH0_RX_RATE_SEL 0000 66 | F99B1 67 | F100B1 68 | F101B1 69 | F102B1 70 | 71 | .config DCU.CH0_TDRV_DAT_SEL 00 72 | F70B1 73 | F71B1 74 | 75 | .config DCU.CH0_TDRV_POST_EN 0 76 | F29B1 77 | 78 | .config DCU.CH0_TDRV_PRE_EN 0 79 | F28B1 80 | 81 | .config DCU.CH0_TDRV_SLICE0_CUR 000 82 | F58B1 83 | F59B1 84 | F60B1 85 | 86 | .config DCU.CH0_TDRV_SLICE0_SEL 00 87 | F40B1 88 | F41B1 89 | 90 | .config DCU.CH0_TDRV_SLICE1_CUR 000 91 | F61B1 92 | F62B1 93 | F63B1 94 | 95 | .config DCU.CH0_TDRV_SLICE1_SEL 00 96 | F42B1 97 | F43B1 98 | 99 | .config DCU.CH0_TDRV_SLICE2_CUR 00 100 | F64B1 101 | F65B1 102 | 103 | .config DCU.CH0_TDRV_SLICE2_SEL 00 104 | F44B1 105 | F45B1 106 | 107 | .config DCU.CH0_TDRV_SLICE3_CUR 00 108 | F54B1 109 | F55B1 110 | 111 | .config DCU.CH0_TDRV_SLICE3_SEL 00 112 | F46B1 113 | F47B1 114 | 115 | .config DCU.CH0_TDRV_SLICE4_CUR 00 116 | F56B1 117 | F57B1 118 | 119 | .config DCU.CH0_TDRV_SLICE4_SEL 00 120 | F48B1 121 | F49B1 122 | 123 | .config DCU.CH0_TDRV_SLICE5_CUR 00 124 | F72B1 125 | F73B1 126 | 127 | .config DCU.CH0_TDRV_SLICE5_SEL 00 128 | F50B1 129 | F51B1 130 | 131 | .config DCU.CH0_TPWDNB 0 132 | F24B1 133 | 134 | .config DCU.CH0_TX_CM_SEL 00 135 | F37B1 136 | F38B1 137 | 138 | .config DCU.CH0_TX_DIV11_SEL 0 139 | F26B1 140 | 141 | .config DCU.CH0_TX_POST_SIGN 0 142 | F31B1 143 | 144 | .config DCU.CH0_TX_PRE_SIGN 0 145 | F30B1 146 | 147 | .config DCU.CH0_UDF_COMMA_A 0011111111 148 | - 149 | - 150 | - 151 | - 152 | - 153 | - 154 | - 155 | - 156 | F14B1 157 | F15B1 158 | 159 | .config DCU.CH0_UDF_COMMA_B 0000000000 160 | F0B1 161 | F1B1 162 | F2B1 163 | F3B1 164 | F4B1 165 | F5B1 166 | F6B1 167 | F7B1 168 | F12B1 169 | F13B1 170 | 171 | .config DCU.CH0_UDF_COMMA_MASK 0011111111 172 | - 173 | - 174 | - 175 | - 176 | - 177 | - 178 | - 179 | - 180 | F10B1 181 | F11B1 182 | 183 | 184 | # Fixed Connections 185 | -------------------------------------------------------------------------------- /ECP5/tiledata/SPICB0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | .mux JDIA 3 | INDDA_SIOLOGIC F21B0 4 | 5 | 6 | # Non-Routing Configuration 7 | .config_enum PIOA.BASE_TYPE NONE 8 | BIDIR_LVCMOS12 F0B1 F2B1 F7B1 F54B0 F55B0 9 | BIDIR_LVCMOS15 F5B1 F23B1 F54B0 F55B0 10 | BIDIR_LVCMOS18 F7B1 F54B0 F55B0 11 | BIDIR_LVCMOS25 F0B1 F1B1 F7B1 F11B1 F54B0 F55B0 12 | BIDIR_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0 13 | BIDIR_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0 14 | INPUT_LVCMOS12 F0B1 F2B1 F7B1 15 | INPUT_LVCMOS15 F7B1 16 | INPUT_LVCMOS18 F7B1 17 | INPUT_LVCMOS25 F0B1 F1B1 F7B1 F11B1 18 | INPUT_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1 19 | INPUT_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1 20 | NONE - 21 | OUTPUT_LVCMOS12 F5B1 F7B1 F54B0 F55B0 22 | OUTPUT_LVCMOS15 F5B1 F7B1 F54B0 F55B0 23 | OUTPUT_LVCMOS18 F5B1 F7B1 F54B0 F55B0 24 | OUTPUT_LVCMOS25 F5B1 F7B1 F54B0 F55B0 25 | OUTPUT_LVCMOS33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0 26 | OUTPUT_LVTTL33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0 27 | 28 | .config_enum PIOA.CLAMP 29 | OFF !F7B1 30 | ON F7B1 31 | 32 | .config_enum PIOA.DRIVE 33 | 12 !F12B1 !F13B1 !F14B1 F15B1 !F16B1 34 | 16 F12B1 F13B1 F14B1 F15B1 !F16B1 35 | 4 !F12B1 !F13B1 F14B1 F15B1 F16B1 36 | 8 F12B1 F13B1 F14B1 !F15B1 !F16B1 37 | 38 | .config_enum PIOA.HYSTERESIS OFF 39 | OFF !F11B1 40 | ON F11B1 41 | 42 | .config_enum PIOA.OPENDRAIN 43 | OFF F7B1 F12B1 F13B1 F14B1 !F23B1 44 | ON !F7B1 !F12B1 !F13B1 !F14B1 F23B1 45 | 46 | .config_enum PIOA.PULLMODE DOWN 47 | DOWN !F5B1 !F6B1 48 | NONE F5B1 !F6B1 49 | UP F5B1 F6B1 50 | 51 | .config_enum PIOA.SLEWRATE SLOW 52 | FAST F22B1 53 | SLOW !F22B1 54 | 55 | 56 | # Fixed Connections 57 | .fixed_conn DIA_SIOLOGIC JDIA 58 | 59 | .fixed_conn IOLDOA IOLDOA_SIOLOGIC 60 | 61 | .fixed_conn IOLDOA IOLDODA_SIOLOGIC 62 | 63 | .fixed_conn IOLDOA_PIO IOLDOA 64 | 65 | .fixed_conn IOLDOIA_SIOLOGIC IOLDOA_SIOLOGIC 66 | 67 | .fixed_conn IOLTOA_PIO IOLTOA_SIOLOGIC 68 | 69 | .fixed_conn JCEA_SIOLOGIC N1_JCE0 70 | 71 | .fixed_conn JCLKA_SIOLOGIC N1_JCLK0 72 | 73 | .fixed_conn JDIA JPADDIA_PIO 74 | 75 | .fixed_conn JDIRECTIONA_SIOLOGIC N1_JB1 76 | 77 | .fixed_conn JLOADNA_SIOLOGIC N1_JD1 78 | 79 | .fixed_conn JLSRA_SIOLOGIC N1_JLSR0 80 | 81 | .fixed_conn JMOVEA_SIOLOGIC N1_JC1 82 | 83 | .fixed_conn JPADDOA N1_JA0 84 | 85 | .fixed_conn JPADDTA N1_JB0 86 | 87 | .fixed_conn JTSDATA0A_SIOLOGIC N1_JB0 88 | 89 | .fixed_conn JTXDATA0A_SIOLOGIC N1_JA0 90 | 91 | .fixed_conn JTXDATA1A_SIOLOGIC N1_JC0 92 | 93 | .fixed_conn N1E1_HL7W0001 N1E1_JF3 94 | 95 | .fixed_conn N1_HL7W0001 N1_JF3 96 | 97 | .fixed_conn N1_JF0 JRXDATA0A_SIOLOGIC 98 | 99 | .fixed_conn N1_JF1 JRXDATA1A_SIOLOGIC 100 | 101 | .fixed_conn N1_JF2 JINFFA_SIOLOGIC 102 | 103 | .fixed_conn N1_JF3 JCFLAGA_SIOLOGIC 104 | 105 | .fixed_conn N1_JQ0 JDIA 106 | 107 | .fixed_conn PADDIA_SIOLOGIC JPADDIA_PIO 108 | 109 | .fixed_conn PADDOA_PIO JPADDOA 110 | 111 | .fixed_conn PADDTA_PIO JPADDTA 112 | 113 | -------------------------------------------------------------------------------- /MachXO3/tiledata/CFG0/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config_enum GSR.GSRMODE NONE 5 | ACTIVE_HIGH F5B40 6 | ACTIVE_LOW F5B40 F5B42 7 | NONE - 8 | 9 | .config_enum GSR.SYNCMODE ASYNC 10 | ASYNC - 11 | NONE - 12 | SYNC F5B44 13 | 14 | .config_enum JTAG.ER1 DISABLED 15 | DISABLED - 16 | ENABLED F5B14 17 | 18 | .config_enum JTAG.ER2 DISABLED 19 | DISABLED - 20 | ENABLED F5B16 21 | 22 | .config_enum SYSCONFIG.BACKGROUND_RECONFIG OFF 23 | OFF - 24 | ON F5B18 F5B24 F5B34 25 | 26 | .config_enum SYSCONFIG.DONEPHASE T3 27 | T0 !F5B30 !F5B32 28 | T1 F5B30 !F5B32 29 | T2 !F5B30 F5B32 30 | T3 F5B30 F5B32 31 | 32 | .config_enum SYSCONFIG.ENABLE_TRANSFR DISABLE 33 | DISABLE - 34 | ENABLE F5B8 F5B18 35 | 36 | .config_enum SYSCONFIG.GOEPHASE T1 37 | T1 - 38 | T2 F5B20 39 | T3 F5B22 40 | 41 | .config_enum SYSCONFIG.GSRPHASE T2 42 | T1 !F5B36 43 | T2 F5B36 44 | T3 !F5B36 F5B38 45 | 46 | .config_enum SYSCONFIG.GWEPHASE T1 47 | T1 - 48 | T2 F5B26 49 | T3 F5B28 50 | 51 | .config_enum SYSCONFIG.SDM_PORT DISABLE 52 | DISABLE - 53 | DONE F5B4 54 | INITN - 55 | PROGRAMN - 56 | PROGRAMN_DONE F5B4 57 | PROGRAMN_DONE_INITN F5B4 58 | 59 | .config_enum TSALL.MODE NONE 60 | NONE - 61 | TSALL F5B10 62 | 63 | .config_enum TSALL.TSALL TSALL 64 | 0 - 65 | 1 F5B12 66 | INV F5B12 67 | TSALL - 68 | 69 | 70 | # Fixed Connections 71 | .fixed_conn 1300_E6_JPADDOC S1_JTDO_JTAG 72 | 73 | .fixed_conn 2100_E8_JPADDOC S1_JTDO_JTAG 74 | 75 | .fixed_conn 4300_E9_JPADDOC S1_JTDO_JTAG 76 | 77 | .fixed_conn 6900_E10_JPADDOC S1_JTDO_JTAG 78 | 79 | .fixed_conn 9400_E11_JPADDOC S1_JTDO_JTAG 80 | 81 | .fixed_conn S1_JCLK_GSR S1E2_JCLK0 82 | 83 | .fixed_conn S1_JF4 S1_JJTCK_JTAG 84 | 85 | .fixed_conn S1_JF5 S1_JJTDI_JTAG 86 | 87 | .fixed_conn S1_JF6 S1_JJRSTN_JTAG 88 | 89 | .fixed_conn S1_JF7 S1_JJSHIFT_JTAG 90 | 91 | .fixed_conn S1_JGSR_GSR S1E2_JC4 92 | 93 | .fixed_conn S1_JJTDO1_JTAG S1_JA4 94 | 95 | .fixed_conn S1_JJTDO2_JTAG S1_JB4 96 | 97 | .fixed_conn S1_JQ0 S1_JJUPDATE_JTAG 98 | 99 | .fixed_conn S1_JQ1 S1_JJCE1_JTAG 100 | 101 | .fixed_conn S1_JQ2 S1_JJRTI1_JTAG 102 | 103 | .fixed_conn S1_JQ3 S1_JJCE2_JTAG 104 | 105 | .fixed_conn S1_JQ4 S1_JJRTI2_JTAG 106 | 107 | .fixed_conn S1_JTCK_JTAG 1300_E7_JPADDIC_PIO 108 | 109 | .fixed_conn S1_JTCK_JTAG 2100_E12_JPADDIC_PIO 110 | 111 | .fixed_conn S1_JTCK_JTAG 4300_E11_JPADDIC_PIO 112 | 113 | .fixed_conn S1_JTCK_JTAG 6900_E13_JPADDIC_PIO 114 | 115 | .fixed_conn S1_JTCK_JTAG 9400_E18_JPADDIC_PIO 116 | 117 | .fixed_conn S1_JTDI_JTAG 1300_E6_JPADDID_PIO 118 | 119 | .fixed_conn S1_JTDI_JTAG 2100_E8_JPADDID_PIO 120 | 121 | .fixed_conn S1_JTDI_JTAG 4300_E9_JPADDID_PIO 122 | 123 | .fixed_conn S1_JTDI_JTAG 6900_E10_JPADDID_PIO 124 | 125 | .fixed_conn S1_JTDI_JTAG 9400_E11_JPADDID_PIO 126 | 127 | .fixed_conn S1_JTMS_JTAG 1300_E7_JPADDID_PIO 128 | 129 | .fixed_conn S1_JTMS_JTAG 2100_E12_JPADDID_PIO 130 | 131 | .fixed_conn S1_JTMS_JTAG 4300_E11_JPADDID_PIO 132 | 133 | .fixed_conn S1_JTMS_JTAG 6900_E13_JPADDID_PIO 134 | 135 | .fixed_conn S1_JTMS_JTAG 9400_E18_JPADDID_PIO 136 | 137 | .fixed_conn S1_JTSALLI_TSALL S1E2_JLSR0 138 | 139 | -------------------------------------------------------------------------------- /MachXO2/tiledata/EBR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR.CSDECODE_A 111 5 | !F0B17 6 | !F0B16 7 | !F0B15 8 | 9 | .config EBR.CSDECODE_B 111 10 | !F0B22 11 | !F0B21 12 | !F0B20 13 | 14 | .config EBR.FIFO8KB.AFPOINTER 00000000001111 15 | - 16 | - 17 | - 18 | - 19 | F0B0 20 | F0B1 21 | F0B2 22 | F0B3 23 | F0B4 24 | F0B5 25 | F0B6 26 | F0B7 27 | F0B8 28 | F0B9 29 | 30 | .config EBR.FIFO8KB.CSDECODE_R 11 31 | !F0B21 32 | !F0B20 33 | 34 | .config EBR.FIFO8KB.CSDECODE_W 11 35 | !F0B16 36 | !F0B15 37 | 38 | .config EBR.WID 000000000 39 | F1B23 40 | F1B24 41 | F1B25 42 | F1B26 43 | F1B27 44 | F1B28 45 | F1B29 46 | F1B30 47 | F1B31 48 | 49 | .config_enum EBR.ADA0MUX ADA0 50 | 0 F0B36 !F0B38 51 | 1 F0B36 F0B38 52 | ADA0 !F0B36 !F0B38 53 | INV !F0B36 F0B38 54 | 55 | .config_enum EBR.ADA1MUX ADA1 56 | 0 F0B37 !F0B39 57 | 1 F0B37 F0B39 58 | ADA1 !F0B37 !F0B39 59 | INV !F0B37 F0B39 60 | 61 | .config_enum EBR.ADB0MUX ADB0 62 | 0 F0B32 !F0B34 63 | 1 F0B32 F0B34 64 | ADB0 !F0B32 !F0B34 65 | INV !F0B32 F0B34 66 | 67 | .config_enum EBR.ASYNC_RESET_RELEASE SYNC 68 | ASYNC F1B19 69 | SYNC !F1B19 70 | 71 | .config_enum EBR.DP8KC.DATA_WIDTH_B 9 72 | 1 F0B26 F0B27 F0B28 73 | 2 !F0B26 F0B27 F0B28 74 | 4 !F0B26 !F0B27 F0B28 75 | 9 !F0B26 !F0B27 !F0B28 76 | 77 | .config_enum EBR.DP8KC.WRITEMODE_A NORMAL 78 | NORMAL !F1B3 79 | READBEFOREWRITE F1B3 80 | WRITETHROUGH !F1B3 81 | 82 | .config_enum EBR.DP8KC.WRITEMODE_B NORMAL 83 | NORMAL !F1B3 84 | READBEFOREWRITE F1B3 85 | WRITETHROUGH !F1B3 86 | 87 | .config_enum EBR.FIFO8KB.DATA_WIDTH_R 9 88 | 1 F0B26 F0B27 F0B28 !F0B31 89 | 18 !F0B26 !F0B27 !F0B28 F0B31 90 | 2 !F0B26 F0B27 F0B28 !F0B31 91 | 4 !F0B26 !F0B27 F0B28 !F0B31 92 | 9 !F0B26 !F0B27 !F0B28 !F0B31 93 | 94 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 9 95 | 1 !F0B25 96 | 18 F0B25 97 | 2 !F0B25 98 | 4 !F0B25 99 | 9 !F0B25 100 | 101 | .config_enum EBR.FIFO8KB.EMPTYIMUX INV 102 | EMPTYI F0B22 103 | INV !F0B22 104 | 105 | .config_enum EBR.FIFO8KB.FULLIMUX INV 106 | FULLI F0B17 107 | INV !F0B17 108 | 109 | .config_enum EBR.GSR ENABLED 110 | DISABLED F0B14 111 | ENABLED !F0B14 112 | 113 | .config_enum EBR.MODE NONE 114 | DP8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 115 | FIFO8KB F0B13 F1B0 F1B8 F1B20 F1B21 F1B22 F1B35 116 | NONE - 117 | PDPW8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 118 | 119 | .config_enum EBR.PDPW8KC.DATA_WIDTH_R 9 120 | 1 F0B26 F0B27 F0B28 !F0B31 121 | 18 !F0B26 !F0B27 !F0B28 F0B31 122 | 2 !F0B26 F0B27 F0B28 !F0B31 123 | 4 !F0B26 !F0B27 F0B28 !F0B31 124 | 9 !F0B26 !F0B27 !F0B28 !F0B31 125 | 126 | .config_enum EBR.REGMODE_A NOREG 127 | NOREG !F0B10 128 | OUTREG F0B10 129 | 130 | .config_enum EBR.REGMODE_B NOREG 131 | NOREG !F0B11 132 | OUTREG F0B11 133 | 134 | .config_enum EBR.RESETMODE SYNC 135 | ASYNC !F0B12 136 | SYNC F0B12 137 | 138 | .config_enum EBR.RSTAMUX RSTA 139 | INV F0B18 140 | RSTA !F0B18 141 | 142 | .config_enum EBR.RSTBMUX RSTB 143 | INV F0B23 144 | RSTB !F0B23 145 | 146 | .config_enum EBR.WEAMUX WEA 147 | INV F0B19 148 | WEA !F0B19 149 | 150 | .config_enum EBR.WEBMUX WEB 151 | INV F0B24 152 | WEB !F0B24 153 | 154 | 155 | # Fixed Connections 156 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR.CSDECODE_A 111 5 | !F0B17 6 | !F0B16 7 | !F0B15 8 | 9 | .config EBR.CSDECODE_B 111 10 | !F0B22 11 | !F0B21 12 | !F0B20 13 | 14 | .config EBR.FIFO8KB.AFPOINTER 00000000001111 15 | - 16 | - 17 | - 18 | - 19 | F0B0 20 | F0B1 21 | F0B2 22 | F0B3 23 | F0B4 24 | F0B5 25 | F0B6 26 | F0B7 27 | F0B8 28 | F0B9 29 | 30 | .config EBR.FIFO8KB.CSDECODE_R 11 31 | !F0B21 32 | !F0B20 33 | 34 | .config EBR.FIFO8KB.CSDECODE_W 11 35 | !F0B16 36 | !F0B15 37 | 38 | .config EBR.WID 000000000 39 | F1B23 40 | F1B24 41 | F1B25 42 | F1B26 43 | F1B27 44 | F1B28 45 | F1B29 46 | F1B30 47 | F1B31 48 | 49 | .config_enum EBR.ADA0MUX ADA0 50 | 0 F0B36 !F0B38 51 | 1 F0B36 F0B38 52 | ADA0 !F0B36 !F0B38 53 | INV !F0B36 F0B38 54 | 55 | .config_enum EBR.ADA1MUX ADA1 56 | 0 F0B37 !F0B39 57 | 1 F0B37 F0B39 58 | ADA1 !F0B37 !F0B39 59 | INV !F0B37 F0B39 60 | 61 | .config_enum EBR.ADB0MUX ADB0 62 | 0 F0B32 !F0B34 63 | 1 F0B32 F0B34 64 | ADB0 !F0B32 !F0B34 65 | INV !F0B32 F0B34 66 | 67 | .config_enum EBR.ASYNC_RESET_RELEASE SYNC 68 | ASYNC F1B19 69 | SYNC !F1B19 70 | 71 | .config_enum EBR.DP8KC.DATA_WIDTH_B 9 72 | 1 F0B26 F0B27 F0B28 73 | 2 !F0B26 F0B27 F0B28 74 | 4 !F0B26 !F0B27 F0B28 75 | 9 !F0B26 !F0B27 !F0B28 76 | 77 | .config_enum EBR.DP8KC.WRITEMODE_A NORMAL 78 | NORMAL !F1B3 79 | READBEFOREWRITE F1B3 80 | WRITETHROUGH !F1B3 81 | 82 | .config_enum EBR.DP8KC.WRITEMODE_B NORMAL 83 | NORMAL !F1B3 84 | READBEFOREWRITE F1B3 85 | WRITETHROUGH !F1B3 86 | 87 | .config_enum EBR.FIFO8KB.DATA_WIDTH_R 9 88 | 1 F0B26 F0B27 F0B28 !F0B31 89 | 18 !F0B26 !F0B27 !F0B28 F0B31 90 | 2 !F0B26 F0B27 F0B28 !F0B31 91 | 4 !F0B26 !F0B27 F0B28 !F0B31 92 | 9 !F0B26 !F0B27 !F0B28 !F0B31 93 | 94 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 9 95 | 1 !F0B25 96 | 18 F0B25 97 | 2 !F0B25 98 | 4 !F0B25 99 | 9 !F0B25 100 | 101 | .config_enum EBR.FIFO8KB.EMPTYIMUX INV 102 | EMPTYI F0B22 103 | INV !F0B22 104 | 105 | .config_enum EBR.FIFO8KB.FULLIMUX INV 106 | FULLI F0B17 107 | INV !F0B17 108 | 109 | .config_enum EBR.GSR ENABLED 110 | DISABLED F0B14 111 | ENABLED !F0B14 112 | 113 | .config_enum EBR.MODE NONE 114 | DP8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 115 | FIFO8KB F0B13 F1B0 F1B8 F1B20 F1B21 F1B22 F1B35 116 | NONE - 117 | PDPW8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 118 | 119 | .config_enum EBR.PDPW8KC.DATA_WIDTH_R 9 120 | 1 F0B26 F0B27 F0B28 !F0B31 121 | 18 !F0B26 !F0B27 !F0B28 F0B31 122 | 2 !F0B26 F0B27 F0B28 !F0B31 123 | 4 !F0B26 !F0B27 F0B28 !F0B31 124 | 9 !F0B26 !F0B27 !F0B28 !F0B31 125 | 126 | .config_enum EBR.REGMODE_A NOREG 127 | NOREG !F0B10 128 | OUTREG F0B10 129 | 130 | .config_enum EBR.REGMODE_B NOREG 131 | NOREG !F0B11 132 | OUTREG F0B11 133 | 134 | .config_enum EBR.RESETMODE SYNC 135 | ASYNC !F0B12 136 | SYNC F0B12 137 | 138 | .config_enum EBR.RSTAMUX RSTA 139 | INV F0B18 140 | RSTA !F0B18 141 | 142 | .config_enum EBR.RSTBMUX RSTB 143 | INV F0B23 144 | RSTB !F0B23 145 | 146 | .config_enum EBR.WEAMUX WEA 147 | INV F0B19 148 | WEA !F0B19 149 | 150 | .config_enum EBR.WEBMUX WEB 151 | INV F0B24 152 | WEB !F0B24 153 | 154 | 155 | # Fixed Connections 156 | -------------------------------------------------------------------------------- /MachXO3D/tiledata/EBR1/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR.CSDECODE_A 111 5 | !F0B17 6 | !F0B16 7 | !F0B15 8 | 9 | .config EBR.CSDECODE_B 111 10 | !F0B22 11 | !F0B21 12 | !F0B20 13 | 14 | .config EBR.FIFO8KB.AFPOINTER 00000000001111 15 | - 16 | - 17 | - 18 | - 19 | F0B0 20 | F0B1 21 | F0B2 22 | F0B3 23 | F0B4 24 | F0B5 25 | F0B6 26 | F0B7 27 | F0B8 28 | F0B9 29 | 30 | .config EBR.FIFO8KB.CSDECODE_R 11 31 | !F0B21 32 | !F0B20 33 | 34 | .config EBR.FIFO8KB.CSDECODE_W 11 35 | !F0B16 36 | !F0B15 37 | 38 | .config EBR.WID 000000000 39 | F1B23 40 | F1B24 41 | F1B25 42 | F1B26 43 | F1B27 44 | F1B28 45 | F1B29 46 | F1B30 47 | F1B31 48 | 49 | .config_enum EBR.ADA0MUX ADA0 50 | 0 F0B36 !F0B38 51 | 1 F0B36 F0B38 52 | ADA0 !F0B36 !F0B38 53 | INV !F0B36 F0B38 54 | 55 | .config_enum EBR.ADA1MUX ADA1 56 | 0 F0B37 !F0B39 57 | 1 F0B37 F0B39 58 | ADA1 !F0B37 !F0B39 59 | INV !F0B37 F0B39 60 | 61 | .config_enum EBR.ADB0MUX ADB0 62 | 0 F0B32 !F0B34 63 | 1 F0B32 F0B34 64 | ADB0 !F0B32 !F0B34 65 | INV !F0B32 F0B34 66 | 67 | .config_enum EBR.ASYNC_RESET_RELEASE SYNC 68 | ASYNC F1B19 69 | SYNC !F1B19 70 | 71 | .config_enum EBR.DP8KC.DATA_WIDTH_B 9 72 | 1 F0B26 F0B27 F0B28 73 | 2 !F0B26 F0B27 F0B28 74 | 4 !F0B26 !F0B27 F0B28 75 | 9 !F0B26 !F0B27 !F0B28 76 | 77 | .config_enum EBR.DP8KC.WRITEMODE_A NORMAL 78 | NORMAL !F1B3 79 | READBEFOREWRITE F1B3 80 | WRITETHROUGH !F1B3 81 | 82 | .config_enum EBR.DP8KC.WRITEMODE_B NORMAL 83 | NORMAL !F1B3 84 | READBEFOREWRITE F1B3 85 | WRITETHROUGH !F1B3 86 | 87 | .config_enum EBR.FIFO8KB.DATA_WIDTH_R 9 88 | 1 F0B26 F0B27 F0B28 !F0B31 89 | 18 !F0B26 !F0B27 !F0B28 F0B31 90 | 2 !F0B26 F0B27 F0B28 !F0B31 91 | 4 !F0B26 !F0B27 F0B28 !F0B31 92 | 9 !F0B26 !F0B27 !F0B28 !F0B31 93 | 94 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 9 95 | 1 !F0B25 96 | 18 F0B25 97 | 2 !F0B25 98 | 4 !F0B25 99 | 9 !F0B25 100 | 101 | .config_enum EBR.FIFO8KB.EMPTYIMUX INV 102 | EMPTYI F0B22 103 | INV !F0B22 104 | 105 | .config_enum EBR.FIFO8KB.FULLIMUX INV 106 | FULLI F0B17 107 | INV !F0B17 108 | 109 | .config_enum EBR.GSR ENABLED 110 | DISABLED F0B14 111 | ENABLED !F0B14 112 | 113 | .config_enum EBR.MODE NONE 114 | DP8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B34 115 | FIFO8KB F0B13 F1B0 F1B8 F1B20 F1B21 F1B22 F1B34 116 | NONE - 117 | PDPW8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B34 118 | 119 | .config_enum EBR.PDPW8KC.DATA_WIDTH_R 9 120 | 1 F0B26 F0B27 F0B28 !F0B31 121 | 18 !F0B26 !F0B27 !F0B28 F0B31 122 | 2 !F0B26 F0B27 F0B28 !F0B31 123 | 4 !F0B26 !F0B27 F0B28 !F0B31 124 | 9 !F0B26 !F0B27 !F0B28 !F0B31 125 | 126 | .config_enum EBR.REGMODE_A NOREG 127 | NOREG !F0B10 128 | OUTREG F0B10 129 | 130 | .config_enum EBR.REGMODE_B NOREG 131 | NOREG !F0B11 132 | OUTREG F0B11 133 | 134 | .config_enum EBR.RESETMODE SYNC 135 | ASYNC !F0B12 136 | SYNC F0B12 137 | 138 | .config_enum EBR.RSTAMUX RSTA 139 | INV F0B18 140 | RSTA !F0B18 141 | 142 | .config_enum EBR.RSTBMUX RSTB 143 | INV F0B23 144 | RSTB !F0B23 145 | 146 | .config_enum EBR.WEAMUX WEA 147 | INV F0B19 148 | WEA !F0B19 149 | 150 | .config_enum EBR.WEBMUX WEB 151 | INV F0B24 152 | WEB !F0B24 153 | 154 | 155 | # Fixed Connections 156 | -------------------------------------------------------------------------------- /MachXO3/tiledata/EBR1_10K/bits.db: -------------------------------------------------------------------------------- 1 | # Routing Mux Bits 2 | 3 | # Non-Routing Configuration 4 | .config EBR.CSDECODE_A 111 5 | !F0B17 6 | !F0B16 7 | !F0B15 8 | 9 | .config EBR.CSDECODE_B 111 10 | !F0B22 11 | !F0B21 12 | !F0B20 13 | 14 | .config EBR.FIFO8KB.AFPOINTER 00000000001111 15 | - 16 | - 17 | - 18 | - 19 | F0B0 20 | F0B1 21 | F0B2 22 | F0B3 23 | F0B4 24 | F0B5 25 | F0B6 26 | F0B7 27 | F0B8 28 | F0B9 29 | 30 | .config EBR.FIFO8KB.CSDECODE_R 11 31 | !F0B21 32 | !F0B20 33 | 34 | .config EBR.FIFO8KB.CSDECODE_W 11 35 | !F0B16 36 | !F0B15 37 | 38 | .config EBR.WID 000000000 39 | F1B23 40 | F1B24 41 | F1B25 42 | F1B26 43 | F1B27 44 | F1B28 45 | F1B29 46 | F1B30 47 | F1B31 48 | 49 | .config_enum EBR.ADA0MUX ADA0 50 | 0 F0B36 !F0B38 51 | 1 F0B36 F0B38 52 | ADA0 !F0B36 !F0B38 53 | INV !F0B36 F0B38 54 | 55 | .config_enum EBR.ADA1MUX ADA1 56 | 0 F0B37 !F0B39 57 | 1 F0B37 F0B39 58 | ADA1 !F0B37 !F0B39 59 | INV !F0B37 F0B39 60 | 61 | .config_enum EBR.ADB0MUX ADB0 62 | 0 F0B32 !F0B34 63 | 1 F0B32 F0B34 64 | ADB0 !F0B32 !F0B34 65 | INV !F0B32 F0B34 66 | 67 | .config_enum EBR.ASYNC_RESET_RELEASE SYNC 68 | ASYNC F1B19 69 | SYNC !F1B19 70 | 71 | .config_enum EBR.DP8KC.DATA_WIDTH_B 9 72 | 1 F0B26 F0B27 F0B28 73 | 2 !F0B26 F0B27 F0B28 74 | 4 !F0B26 !F0B27 F0B28 75 | 9 !F0B26 !F0B27 !F0B28 76 | 77 | .config_enum EBR.DP8KC.WRITEMODE_A NORMAL 78 | NORMAL !F1B3 79 | READBEFOREWRITE F1B3 80 | WRITETHROUGH !F1B3 81 | 82 | .config_enum EBR.DP8KC.WRITEMODE_B NORMAL 83 | NORMAL !F1B3 84 | READBEFOREWRITE F1B3 85 | WRITETHROUGH !F1B3 86 | 87 | .config_enum EBR.FIFO8KB.DATA_WIDTH_R 9 88 | 1 F0B26 F0B27 F0B28 !F0B31 89 | 18 !F0B26 !F0B27 !F0B28 F0B31 90 | 2 !F0B26 F0B27 F0B28 !F0B31 91 | 4 !F0B26 !F0B27 F0B28 !F0B31 92 | 9 !F0B26 !F0B27 !F0B28 !F0B31 93 | 94 | .config_enum EBR.FIFO8KB.DATA_WIDTH_W 9 95 | 1 !F0B25 96 | 18 F0B25 97 | 2 !F0B25 98 | 4 !F0B25 99 | 9 !F0B25 100 | 101 | .config_enum EBR.FIFO8KB.EMPTYIMUX INV 102 | EMPTYI F0B22 103 | INV !F0B22 104 | 105 | .config_enum EBR.FIFO8KB.FULLIMUX INV 106 | FULLI F0B17 107 | INV !F0B17 108 | 109 | .config_enum EBR.GSR ENABLED 110 | DISABLED F0B14 111 | ENABLED !F0B14 112 | 113 | .config_enum EBR.MODE NONE 114 | DP8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 115 | FIFO8KB F0B13 F1B0 F1B8 F1B20 F1B21 F1B22 F1B35 116 | NONE - 117 | PDPW8KC F0B13 F1B8 F1B20 F1B21 F1B22 F1B35 118 | 119 | .config_enum EBR.PDPW8KC.DATA_WIDTH_R 9 120 | 1 F0B26 F0B27 F0B28 !F0B31 121 | 18 !F0B26 !F0B27 !F0B28 F0B31 122 | 2 !F0B26 F0B27 F0B28 !F0B31 123 | 4 !F0B26 !F0B27 F0B28 !F0B31 124 | 9 !F0B26 !F0B27 !F0B28 !F0B31 125 | 126 | .config_enum EBR.REGMODE_A NOREG 127 | NOREG !F0B10 128 | OUTREG F0B10 129 | 130 | .config_enum EBR.REGMODE_B NOREG 131 | NOREG !F0B11 132 | OUTREG F0B11 133 | 134 | .config_enum EBR.RESETMODE SYNC 135 | ASYNC !F0B12 136 | SYNC F0B12 137 | 138 | .config_enum EBR.RSTAMUX RSTA 139 | INV F0B18 140 | RSTA !F0B18 141 | 142 | .config_enum EBR.RSTBMUX RSTB 143 | INV F0B23 144 | RSTB !F0B23 145 | 146 | .config_enum EBR.WEAMUX WEA 147 | INV F0B19 148 | WEA !F0B19 149 | 150 | .config_enum EBR.WEBMUX WEB 151 | INV F0B24 152 | WEB !F0B24 153 | 154 | 155 | # Fixed Connections 156 | --------------------------------------------------------------------------------