├── .github └── workflows │ ├── ci.yml │ └── codeql.yml ├── .gitignore ├── .mailmap ├── .readthedocs.yaml ├── COPYING ├── CodeOfConduct ├── README.md ├── bus ├── rvfi_bus_axi4.sv └── rvfi_bus_util.sv ├── checks ├── genchecks.py ├── rvfi_bus_dmem_check.sv ├── rvfi_bus_dmem_fault_check.sv ├── rvfi_bus_dmem_io_order_check.sv ├── rvfi_bus_dmem_io_read_check.sv ├── rvfi_bus_dmem_io_read_fault_check.sv ├── rvfi_bus_dmem_io_write_check.sv ├── rvfi_bus_dmem_io_write_fault_check.sv ├── rvfi_bus_imem_check.sv ├── rvfi_bus_imem_fault_check.sv ├── rvfi_causal_check.sv ├── rvfi_causal_io_check.sv ├── rvfi_causal_mem_check.sv ├── rvfi_channel.sv ├── rvfi_cover_check.sv ├── rvfi_csr_ill_check.sv ├── rvfi_csrc_any_check.sv ├── rvfi_csrc_const_check.sv ├── rvfi_csrc_hpm_check.sv ├── rvfi_csrc_inc_check.sv ├── rvfi_csrc_upcnt_check.sv ├── rvfi_csrc_zero_check.sv ├── rvfi_csrw_check.sv ├── rvfi_dmem_check.sv ├── rvfi_fault_check.sv ├── rvfi_hang_check.sv ├── rvfi_ill_check.sv ├── rvfi_imem_check.sv ├── rvfi_insn_check.sv ├── rvfi_liveness_check.sv ├── rvfi_macros.py ├── rvfi_macros.vh ├── rvfi_pc_bwd_check.sv ├── rvfi_pc_fwd_check.sv ├── rvfi_reg_check.sv ├── rvfi_testbench.sv └── rvfi_unique_check.sv ├── cores ├── VexRiscv │ ├── .gitignore │ ├── README.md │ ├── VexRiscv.v │ ├── checks.cfg │ ├── disasm.py │ ├── dmemcheck.sby │ ├── dmemcheck.sv │ ├── imemcheck.sby │ ├── imemcheck.sv │ └── wrapper.sv ├── nerv │ ├── .gitignore │ ├── COPYING │ ├── Makefile │ ├── NERV.png │ ├── README.md │ ├── axi_cache │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── README.md │ │ ├── axi_ram.v │ │ ├── checks_axi.cfg │ │ ├── checks_internal.cfg │ │ ├── firmware.c │ │ ├── nerv_axi_cache.sv │ │ ├── nerv_axi_cache_dcache.sv │ │ ├── nerv_axi_cache_icache.sv │ │ ├── testbench_axi.sv │ │ ├── testbench_internal.sv │ │ ├── verify_axi.sby │ │ ├── verify_axi.sv │ │ ├── wrapper_axi.sv │ │ └── wrapper_internal.sv │ ├── cexdata.sh │ ├── checks.cfg │ ├── disasm.py │ ├── examples │ │ └── icebreaker │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── firmware.c │ │ │ ├── firmware.s │ │ │ ├── icebreaker.pcf │ │ │ ├── icebreaker_soc.png │ │ │ ├── sections.lds │ │ │ ├── testbench.gtkw │ │ │ ├── testbench.sv │ │ │ └── top.v │ ├── firmware.c │ ├── firmware.s │ ├── imemcheck.sby │ ├── imemcheck.sv │ ├── nerv.sv │ ├── nervsoc.sv │ ├── sections.lds │ ├── testbench.gtkw │ ├── testbench.sv │ ├── trace.gtkw │ ├── vectors.s │ └── wrapper.sv ├── picorv32 │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── cexdata.sh │ ├── checks.cfg │ ├── checks.gtkw │ ├── complete.sby │ ├── complete.sv │ ├── cover.sby │ ├── cover.sv │ ├── disasm.py │ ├── dmemcheck.sv │ ├── equiv.sh │ ├── honest.sby │ ├── honest.sv │ ├── imemcheck.sv │ ├── testbugs.sh │ └── wrapper.sv └── serv │ ├── .gitignore │ ├── README.md │ ├── cexdata.sh │ ├── checks.cfg │ ├── cover.gtkw │ ├── cover.sby │ ├── cover.sv │ ├── disasm.py │ ├── generate.sh │ ├── sbram.sv │ └── wrapper.sv ├── docs ├── .gitignore ├── Makefile ├── make.bat └── source │ ├── _static │ └── custom.css │ ├── conf.py │ ├── config.rst │ ├── csrs.rst │ ├── examplebugs.rst │ ├── index.rst │ ├── procedure.rst │ ├── quickstart.rst │ ├── references.rst │ ├── requirements.txt │ └── rvfi.rst ├── insns ├── generate.py ├── insn_add.v ├── insn_add_uw.v ├── insn_addi.v ├── insn_addiw.v ├── insn_addw.v ├── insn_and.v ├── insn_andi.v ├── insn_andn.v ├── insn_auipc.v ├── insn_bclr.v ├── insn_bclri.v ├── insn_beq.v ├── insn_bext.v ├── insn_bexti.v ├── insn_bge.v ├── insn_bgeu.v ├── insn_binv.v ├── insn_binvi.v ├── insn_blt.v ├── insn_bltu.v ├── insn_bne.v ├── insn_brev8.v ├── insn_bset.v ├── insn_bseti.v ├── insn_c_add.v ├── insn_c_addi.v ├── insn_c_addi16sp.v ├── insn_c_addi4spn.v ├── insn_c_addiw.v ├── insn_c_addw.v ├── insn_c_and.v ├── insn_c_andi.v ├── insn_c_beqz.v ├── insn_c_bnez.v ├── insn_c_j.v ├── insn_c_jal.v ├── insn_c_jalr.v ├── insn_c_jr.v ├── insn_c_ld.v ├── insn_c_ldsp.v ├── insn_c_li.v ├── insn_c_lui.v ├── insn_c_lw.v ├── insn_c_lwsp.v ├── insn_c_mv.v ├── insn_c_or.v ├── insn_c_sd.v ├── insn_c_sdsp.v ├── insn_c_slli.v ├── insn_c_srai.v ├── insn_c_srli.v ├── insn_c_sub.v ├── insn_c_subw.v ├── insn_c_sw.v ├── insn_c_swsp.v ├── insn_c_xor.v ├── insn_clmul.v ├── insn_clmulh.v ├── insn_clmulr.v ├── insn_clz.v ├── insn_clzw.v ├── insn_cpop.v ├── insn_cpopw.v ├── insn_ctz.v ├── insn_ctzw.v ├── insn_div.v ├── insn_divu.v ├── insn_divuw.v ├── insn_divw.v ├── insn_jal.v ├── insn_jalr.v ├── insn_lb.v ├── insn_lbu.v ├── insn_ld.v ├── insn_lh.v ├── insn_lhu.v ├── insn_lui.v ├── insn_lw.v ├── insn_lwu.v ├── insn_max.v ├── insn_maxu.v ├── insn_min.v ├── insn_minu.v ├── insn_mul.v ├── insn_mulh.v ├── insn_mulhsu.v ├── insn_mulhu.v ├── insn_mulw.v ├── insn_or.v ├── insn_orc_b.v ├── insn_ori.v ├── insn_orn.v ├── insn_pack.v ├── insn_packh.v ├── insn_packw.v ├── insn_rem.v ├── insn_remu.v ├── insn_remuw.v ├── insn_remw.v ├── insn_rev8.v ├── insn_rol.v ├── insn_rolw.v ├── insn_ror.v ├── insn_rori.v ├── insn_roriw.v ├── insn_rorw.v ├── insn_sb.v ├── insn_sd.v ├── insn_sext_b.v ├── insn_sext_h.v ├── insn_sh.v ├── insn_sh1add.v ├── insn_sh1add_uw.v ├── insn_sh2add.v ├── insn_sh2add_uw.v ├── insn_sh3add.v ├── insn_sh3add_uw.v ├── insn_sll.v ├── insn_slli.v ├── insn_slli_uw.v ├── insn_slliw.v ├── insn_sllw.v ├── insn_slt.v ├── insn_slti.v ├── insn_sltiu.v ├── insn_sltu.v ├── insn_sra.v ├── insn_srai.v ├── insn_sraiw.v ├── insn_sraw.v ├── insn_srl.v ├── insn_srli.v ├── insn_srliw.v ├── insn_srlw.v ├── insn_sub.v ├── insn_subw.v ├── insn_sw.v ├── insn_unzip.v ├── insn_xnor.v ├── insn_xor.v ├── insn_xori.v ├── insn_xperm4.v ├── insn_xperm8.v ├── insn_zext_h.v ├── insn_zip.v ├── isa_rv32i.txt ├── isa_rv32i.v ├── isa_rv32iZba.txt ├── isa_rv32iZba.v ├── isa_rv32iZba_Zbb_Zbc_Zbs.txt ├── isa_rv32iZba_Zbb_Zbc_Zbs.v ├── isa_rv32iZbb.txt ├── isa_rv32iZbb.v ├── isa_rv32iZbc.txt ├── isa_rv32iZbc.v ├── isa_rv32iZbkb.txt ├── isa_rv32iZbkb.v ├── isa_rv32iZbkb_Zbkc_Zbkx.txt ├── isa_rv32iZbkb_Zbkc_Zbkx.v ├── isa_rv32iZbkc.txt ├── isa_rv32iZbkc.v ├── isa_rv32iZbkx.txt ├── isa_rv32iZbkx.v ├── isa_rv32iZbs.txt ├── isa_rv32iZbs.v ├── isa_rv32ib.txt ├── isa_rv32ib.v ├── isa_rv32ic.txt ├── isa_rv32ic.v ├── isa_rv32im.txt ├── isa_rv32im.v ├── isa_rv32imc.txt ├── isa_rv32imc.v ├── isa_rv64i.txt ├── isa_rv64i.v ├── isa_rv64iZba.txt ├── isa_rv64iZba.v ├── isa_rv64iZba_Zbb_Zbc_Zbs.txt ├── isa_rv64iZba_Zbb_Zbc_Zbs.v ├── isa_rv64iZbb.txt ├── isa_rv64iZbb.v ├── isa_rv64iZbc.txt ├── isa_rv64iZbc.v ├── isa_rv64iZbkb.txt ├── isa_rv64iZbkb.v ├── isa_rv64iZbkb_Zbkc_Zbkx.txt ├── isa_rv64iZbkb_Zbkc_Zbkx.v ├── isa_rv64iZbkc.txt ├── isa_rv64iZbkc.v ├── isa_rv64iZbkx.txt ├── isa_rv64iZbkx.v ├── isa_rv64iZbs.txt ├── isa_rv64iZbs.v ├── isa_rv64ib.txt ├── isa_rv64ib.v ├── isa_rv64ic.txt ├── isa_rv64ic.v ├── isa_rv64im.txt ├── isa_rv64im.v ├── isa_rv64imc.txt └── isa_rv64imc.v ├── monitor └── generate.py └── tests ├── coverage ├── .gitignore ├── coverage.sby ├── coverage.sv ├── generate.py ├── riscv_rv32i_insn.v ├── riscv_rv32ic_insn.v ├── riscv_rv64i_insn.v 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