├── DOC ├── DOC.txt └── xge_mac_spec.pdf ├── DUT ├── auto_verilog.sh ├── custom.el ├── include │ ├── CRC32_D64.v │ ├── CRC32_D8.v │ ├── defines.v │ ├── timescale.v │ └── utils.v └── verilog │ ├── fault_sm.v │ ├── generic_fifo.v │ ├── generic_fifo_ctrl.v │ ├── generic_mem_medium.v │ ├── generic_mem_small.v │ ├── meta_sync.v │ ├── meta_sync_single.v │ ├── rx_data_fifo.v │ ├── rx_dequeue.v │ ├── rx_enqueue.v │ ├── rx_hold_fifo.v │ ├── sync_clk_core.v │ ├── sync_clk_wb.v │ ├── sync_clk_xgmii_tx.v │ ├── tx_data_fifo.v │ ├── tx_dequeue.v │ ├── tx_enqueue.v │ ├── tx_hold_fifo.v │ ├── wishbone_if.v │ └── xge_mac.v ├── README.md └── Testbench ├── Components ├── Agent │ ├── RX_Agent.sv │ └── TX_Agent.sv ├── Coverage_Collector │ └── Coverage_Collector.sv ├── Driver.sv ├── Environment │ └── Environment.sv ├── Monitors │ ├── RX_Monitor.sv │ └── TX_Monitor.sv ├── Scoreboard │ └── Scoreboard.sv └── Sequencer.sv ├── Ethernet_pkg.sv ├── Interface └── Interface.sv ├── Sequences ├── Base_Sequence.sv ├── Large_Packet_Sequence.sv ├── Oversized_Packet_Sequence.sv ├── Reset_Sequence.sv ├── Small_Packet_Sequence.sv └── Zero_IFG_Packet_Sequence.sv ├── Test └── Ethernet_Test.sv ├── Top.sv └── Transactions └── Packet.sv /DOC/DOC.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Youssefmdany/10-Gigabit-Ethernet-MAC-Core-UVM-Verification-/HEAD/DOC/DOC.txt -------------------------------------------------------------------------------- /DOC/xge_mac_spec.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Youssefmdany/10-Gigabit-Ethernet-MAC-Core-UVM-Verification-/HEAD/DOC/xge_mac_spec.pdf -------------------------------------------------------------------------------- /DUT/auto_verilog.sh: -------------------------------------------------------------------------------- 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