├── README.md ├── RTL ├── ALU.sv ├── ALU_Control.sv ├── Control_Unit.sv ├── DataMem.sv ├── EX_MEM.sv ├── Forwarding_Unit.sv ├── ID_EX.sv ├── IF_ID.sv ├── ImmGen.sv ├── InstrMem.sv ├── MEM_WB.sv ├── Mult_Div_Unit.sv ├── PC.sv ├── RISC_V.sv ├── RegFile.sv └── Staller.sv ├── TB ├── Agent.sv ├── Coverage_collector.sv ├── Driver.sv ├── Environment.sv ├── Interface.sv ├── Monitor.sv ├── RISCV_Test.sv ├── RISCV_pkg.sv ├── RISCV_seq_item.sv ├── Scoreboard.sv ├── Sequence.sv ├── Sequencer.sv ├── Top.sv ├── mem_ref_model.sv └── reg_ref_model.sv └── doc └── link to doc /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Youssefmdany/Design-and-UVM-TB-of-RISC-V-Microprocessor/HEAD/README.md -------------------------------------------------------------------------------- /RTL/ALU.sv: -------------------------------------------------------------------------------- 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