├── BackEnd ├── 1_Synthesis │ ├── RISCV_Top.ddc │ ├── RISCV_Top.sdc │ ├── RISCV_Top.sdf │ ├── RISCV_Top.v │ ├── synth_area.rpt │ ├── synth_cells.rpt │ ├── synth_qor.rpt │ ├── synth_resources.rpt │ └── synth_timing.rpt ├── 2_DFT │ ├── RISCV_Top_dft.ddc │ ├── RISCV_Top_dft.sdf │ ├── RISCV_Top_dft.spf │ ├── RISCV_Top_dft.v │ ├── dft_area.report │ ├── dft_coverage.drc_coverage │ ├── dft_qor.report │ ├── dft_scan_path.report │ └── dft_timing.report ├── 3_FloorPlanning │ └── FloorPlanning_Netlist.v ├── 4_PowerPlanning │ ├── PP_cells.rpt │ ├── PP_qor.rpt │ ├── PP_timing.rpt │ ├── PP_timing_hold.rpt │ ├── Power_Planning_legalization.rpt │ └── Power_Planning_netlist.v ├── 5_Placement │ ├── Placement_cells.rpt │ ├── Placement_legalization.rpt │ ├── Placement_netlist.v │ ├── Placement_qor.rpt │ ├── Placement_timing.rpt │ └── Placement_timing_hold.rpt ├── 6_CTS │ ├── CTS_Clock_routing_rules.rpt │ ├── CTS_cells.rpt │ ├── CTS_clk_setting.rpt │ ├── CTS_legalization.rpt │ ├── CTS_netlist.v │ ├── CTS_ports.rpt │ ├── CTS_qor.rpt │ ├── CTS_routing_rules.rpt │ ├── CTS_timing.rpt │ └── CTS_timing_hold.rpt ├── 7_Routing │ ├── RISCV_Top_Routing_Netlist.v │ ├── RISCV_Top_Routing_SDC.sdc │ ├── RISCV_Top_Routing_Spef.spef.maxTLU_125.spef │ ├── RISCV_Top_Routing_Spef.spef.minTLU_125.spef │ ├── RISCV_Top_Routing_Spef.spef.spef_scenario │ ├── RISCV_Top_Routing_def.def │ ├── Routing_Clock_routing_rules.rpt │ ├── Routing_clk_setting.rpt │ ├── Routing_legalization.rpt │ ├── Routing_netlist.v │ ├── Routing_ports.rpt │ ├── Routing_qor.rpt │ ├── Routing_routing_rules.rpt │ ├── Routing_timing.rpt │ ├── Routing_timing_hold.rpt │ └── routing_cells.rpt ├── GDS │ └── RISCV_Top_Routing_GDS.gds └── Scripts │ ├── CTS.tcl │ ├── floorplan.tcl │ ├── ndm.tcl │ ├── placement.tcl │ ├── powerplan.tcl │ ├── pt.tcl │ ├── riscv_constraint.tcl │ ├── riscv_script_dft.tcl │ ├── riscv_script_syn.tcl │ ├── routing.tcl │ └── setup.tcl ├── FrontEnd ├── RTL │ ├── ALU.v │ ├── Cache_Contrl.v │ ├── Cache_Memory.v │ ├── Control_Unit.v │ ├── Data_Memory_System.v │ ├── Data_mem.v │ ├── PC.v │ ├── RISCV.v │ ├── imm_gen.v │ ├── instr_mem.v │ └── reg_file.v ├── TB │ ├── Agent.sv │ ├── Coverage_Collector.sv │ ├── Driver.sv │ ├── Environment.sv │ ├── Interface.sv │ ├── Monitor.sv │ ├── RISCV_Test.sv │ ├── RISCV_Top.sv │ ├── RISCV_pkg.sv │ ├── RISCV_seq_item.sv │ ├── Riscv_param.sv │ ├── Scoreboard.sv │ ├── Sequence.sv │ ├── Sequencer.sv │ ├── mem_ref_model.sv │ └── reg_ref_model.sv └── sim │ ├── simv │ └── simv.vdb │ └── snps │ └── coverage │ └── db │ ├── auxiliary │ ├── dve_debug.xml │ ├── verilog.instance_parameters.txt │ └── verilog.sourceinfo.xml │ ├── design │ └── verilog.design.xml │ ├── shape │ ├── assert.verilog.shape.xml │ ├── branch.verilog.shape.xml │ ├── cond.verilog.exclude.xml │ ├── cond.verilog.shape.xml │ ├── fsm.verilog.exclude.xml │ ├── fsm.verilog.generated_config.txt │ ├── fsm.verilog.shape.xml │ ├── line.verilog.exclude.xml │ ├── line.verilog.shape.xml │ └── tgl.verilog.shape.xml │ └── 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