├── .github └── FUNDING.yml ├── LICENSE ├── README.md ├── README_QUARTUS.md ├── a00_common_functions.py ├── a01_model_low_weights_digit_detector.py ├── a02_generate_random_non_number.py ├── dataset ├── test │ ├── 0 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ └── 11.png │ ├── 1 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ └── 12.png │ ├── 2 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ └── 12.png │ ├── 3 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ ├── 12.png │ │ └── 13.png │ ├── 4 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ ├── 12.png │ │ └── 13.png │ ├── 5 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ ├── 12.png │ │ ├── 13.png │ │ ├── 14.png │ │ └── 15.png │ ├── 6 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ ├── 12.png │ │ ├── 13.png │ │ ├── 14.png │ │ ├── 15.png │ │ ├── 16.png │ │ ├── 17.png │ │ └── 18.png │ ├── 7 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ ├── 12.png │ │ ├── 13.png │ │ └── 14.png │ ├── 8 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ └── 11.png │ ├── 9 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ ├── 11.png │ │ └── 12.png │ └── 10 │ │ ├── 00.png │ │ ├── 01.png │ │ ├── 02.png │ │ ├── 03.png │ │ ├── 04.png │ │ ├── 05.png │ │ ├── 06.png │ │ ├── 07.png │ │ ├── 08.png │ │ ├── 09.png │ │ ├── 10.png │ │ └── 11.png └── train │ ├── 0 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 1 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 2 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 3 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 4 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 5 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ └── 08.png │ ├── 6 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 7 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 8 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ └── 09.png │ ├── 9 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ ├── 09.png │ └── 10.png │ └── 10 │ ├── 00.png │ ├── 01.png │ ├── 02.png │ ├── 03.png │ ├── 04.png │ ├── 05.png │ ├── 06.png │ ├── 07.png │ ├── 08.png │ ├── 09.png │ ├── 10.png │ ├── 11.png │ ├── 12.png │ ├── 13.png │ ├── 14.png │ ├── 15.png │ ├── 16.png │ ├── 17.png │ ├── 18.png │ ├── 19.png │ ├── 20.png │ ├── 21.png │ ├── 22.png │ ├── 23.png │ ├── 24.png │ ├── 25.png │ ├── 26.png │ ├── 27.png │ ├── 28.png │ ├── 29.png │ ├── 30.png │ ├── 31.png │ ├── 32.png │ ├── 33.png │ ├── 34.png │ ├── 35.png │ ├── 36.png │ ├── 37.png │ ├── 38.png │ ├── 39.png │ ├── 40.png │ ├── 41.png │ ├── 42.png │ ├── 43.png │ ├── 44.png │ ├── 45.png │ ├── 46.png │ ├── 47.png │ ├── 48.png │ ├── 49.png │ ├── 50.png │ ├── 51.png │ ├── 52.png │ ├── 53.png │ ├── 54.png │ ├── 55.png │ ├── 56.png │ ├── 57.png │ ├── 58.png │ ├── 59.png │ ├── 60.png │ ├── 61.png │ ├── 62.png │ ├── 63.png │ ├── 64.png │ ├── 65.png │ ├── 66.png │ ├── 67.png │ ├── 68.png │ └── 69.png ├── docs └── modules_pins_eng.docx ├── images ├── Conn-Foto-1.jpg ├── Conn-Foto-2.jpg ├── Connect-Detailed.jpg ├── Connection-photo.jpg ├── Connection-scheme.png ├── Info-Table.png ├── Neural-Net-Structure.png ├── Q-scr-2019-02.png ├── QV_01.png ├── QV_02.png ├── QV_03.png ├── QV_04.png ├── Video-screen.jpg └── Video-screen.png ├── r01_train_neural_net_and_prepare_initial_weights.py ├── r02_rescale_weights_to_use_fixed_point_representation.py ├── r03_find_optimal_bit_for_weights.py ├── r04_verilog_generator_grayscale_file.py ├── r05_verilog_generator_neural_net_structure.py ├── utils └── convert_image_for_testbench.py ├── verilog ├── code │ ├── gray_28x28 │ │ └── grayscale.v │ ├── lcd │ │ ├── hellosoc_top.sv │ │ ├── tft_ili9341.sv │ │ └── tft_ili9341_spi.sv │ ├── neuroset │ │ ├── RAM.v │ │ ├── RAMtoMEM.v │ │ ├── TOP.v │ │ ├── addressRAM.v │ │ ├── border.v │ │ ├── conv.v │ │ ├── conv_TOP.v │ │ ├── database.v │ │ ├── dense.v │ │ ├── maxpooling.v │ │ └── result.v │ ├── synt │ │ ├── cam_config │ │ │ ├── OV7670_config.v │ │ │ ├── OV7670_config_rom.v │ │ │ ├── SCCB_interface.v │ │ │ ├── camera_configure.v │ │ │ ├── camera_read.v │ │ │ └── source.txt │ │ ├── cam_wrp.v │ │ ├── delay_rg.v │ │ ├── fifo_1024x16.qip │ │ ├── fifo_1024x16.v │ │ ├── fsm_global.sv │ │ └── sdram_controller.v │ └── testbench.v ├── imp │ ├── cam_proj.qpf │ ├── cam_proj.qsf │ ├── cam_proj.qws │ ├── cam_proj_assignment_defaults.qdf │ ├── fifo_big.qip │ ├── fifo_big.v │ ├── fifo_big_bb.v │ ├── pll.ppf │ ├── pll.qip │ ├── pll.v │ ├── pll_bb.v │ ├── pll_for_disp.ppf │ ├── pll_for_disp.qip │ ├── pll_for_disp.v │ └── pll_for_disp_bb.v └── top │ └── cam_proj_top.v └── weights ├── keras_model_low_weights_digit_detector.h5 ├── keras_model_low_weights_digit_detector.h5.csv ├── keras_model_low_weights_digit_detector.h5.png ├── keras_model_low_weights_digit_detector_rescaled.h5 └── optimal_bit.pklz /.github/FUNDING.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/.github/FUNDING.yml -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/README.md -------------------------------------------------------------------------------- /README_QUARTUS.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/README_QUARTUS.md -------------------------------------------------------------------------------- /a00_common_functions.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/a00_common_functions.py -------------------------------------------------------------------------------- /a01_model_low_weights_digit_detector.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/a01_model_low_weights_digit_detector.py -------------------------------------------------------------------------------- /a02_generate_random_non_number.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/a02_generate_random_non_number.py -------------------------------------------------------------------------------- /dataset/test/0/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/00.png -------------------------------------------------------------------------------- /dataset/test/0/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/01.png -------------------------------------------------------------------------------- /dataset/test/0/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/02.png -------------------------------------------------------------------------------- /dataset/test/0/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/03.png -------------------------------------------------------------------------------- /dataset/test/0/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/04.png -------------------------------------------------------------------------------- /dataset/test/0/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/05.png -------------------------------------------------------------------------------- /dataset/test/0/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/06.png -------------------------------------------------------------------------------- /dataset/test/0/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/07.png -------------------------------------------------------------------------------- /dataset/test/0/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/08.png -------------------------------------------------------------------------------- /dataset/test/0/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/09.png -------------------------------------------------------------------------------- /dataset/test/0/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/10.png -------------------------------------------------------------------------------- /dataset/test/0/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/0/11.png -------------------------------------------------------------------------------- /dataset/test/1/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/00.png -------------------------------------------------------------------------------- /dataset/test/1/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/01.png -------------------------------------------------------------------------------- /dataset/test/1/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/02.png -------------------------------------------------------------------------------- /dataset/test/1/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/03.png -------------------------------------------------------------------------------- /dataset/test/1/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/04.png -------------------------------------------------------------------------------- /dataset/test/1/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/05.png -------------------------------------------------------------------------------- /dataset/test/1/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/06.png -------------------------------------------------------------------------------- /dataset/test/1/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/07.png -------------------------------------------------------------------------------- /dataset/test/1/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/08.png -------------------------------------------------------------------------------- /dataset/test/1/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/09.png -------------------------------------------------------------------------------- /dataset/test/1/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/10.png -------------------------------------------------------------------------------- /dataset/test/1/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/11.png -------------------------------------------------------------------------------- /dataset/test/1/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/1/12.png -------------------------------------------------------------------------------- /dataset/test/10/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/00.png -------------------------------------------------------------------------------- /dataset/test/10/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/01.png -------------------------------------------------------------------------------- /dataset/test/10/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/02.png -------------------------------------------------------------------------------- /dataset/test/10/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/03.png -------------------------------------------------------------------------------- /dataset/test/10/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/04.png -------------------------------------------------------------------------------- /dataset/test/10/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/05.png -------------------------------------------------------------------------------- /dataset/test/10/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/06.png -------------------------------------------------------------------------------- /dataset/test/10/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/07.png -------------------------------------------------------------------------------- /dataset/test/10/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/08.png -------------------------------------------------------------------------------- /dataset/test/10/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/09.png -------------------------------------------------------------------------------- /dataset/test/10/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/10.png -------------------------------------------------------------------------------- /dataset/test/10/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/10/11.png -------------------------------------------------------------------------------- /dataset/test/2/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/00.png -------------------------------------------------------------------------------- /dataset/test/2/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/01.png -------------------------------------------------------------------------------- /dataset/test/2/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/02.png -------------------------------------------------------------------------------- /dataset/test/2/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/03.png -------------------------------------------------------------------------------- /dataset/test/2/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/04.png -------------------------------------------------------------------------------- /dataset/test/2/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/05.png -------------------------------------------------------------------------------- /dataset/test/2/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/06.png -------------------------------------------------------------------------------- /dataset/test/2/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/07.png -------------------------------------------------------------------------------- /dataset/test/2/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/08.png -------------------------------------------------------------------------------- /dataset/test/2/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/09.png -------------------------------------------------------------------------------- /dataset/test/2/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/10.png -------------------------------------------------------------------------------- /dataset/test/2/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/11.png -------------------------------------------------------------------------------- /dataset/test/2/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/2/12.png -------------------------------------------------------------------------------- /dataset/test/3/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/00.png -------------------------------------------------------------------------------- /dataset/test/3/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/01.png -------------------------------------------------------------------------------- /dataset/test/3/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/02.png -------------------------------------------------------------------------------- /dataset/test/3/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/03.png -------------------------------------------------------------------------------- /dataset/test/3/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/04.png -------------------------------------------------------------------------------- /dataset/test/3/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/05.png -------------------------------------------------------------------------------- /dataset/test/3/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/06.png -------------------------------------------------------------------------------- /dataset/test/3/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/07.png -------------------------------------------------------------------------------- /dataset/test/3/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/08.png -------------------------------------------------------------------------------- /dataset/test/3/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/09.png -------------------------------------------------------------------------------- /dataset/test/3/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/10.png -------------------------------------------------------------------------------- /dataset/test/3/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/11.png -------------------------------------------------------------------------------- /dataset/test/3/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/12.png -------------------------------------------------------------------------------- /dataset/test/3/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/3/13.png -------------------------------------------------------------------------------- /dataset/test/4/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/00.png -------------------------------------------------------------------------------- /dataset/test/4/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/01.png -------------------------------------------------------------------------------- /dataset/test/4/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/02.png -------------------------------------------------------------------------------- /dataset/test/4/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/03.png -------------------------------------------------------------------------------- /dataset/test/4/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/04.png -------------------------------------------------------------------------------- /dataset/test/4/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/05.png -------------------------------------------------------------------------------- /dataset/test/4/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/06.png -------------------------------------------------------------------------------- /dataset/test/4/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/07.png -------------------------------------------------------------------------------- /dataset/test/4/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/08.png -------------------------------------------------------------------------------- /dataset/test/4/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/09.png -------------------------------------------------------------------------------- /dataset/test/4/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/10.png -------------------------------------------------------------------------------- /dataset/test/4/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/11.png -------------------------------------------------------------------------------- /dataset/test/4/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/12.png -------------------------------------------------------------------------------- /dataset/test/4/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/4/13.png -------------------------------------------------------------------------------- /dataset/test/5/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/00.png -------------------------------------------------------------------------------- /dataset/test/5/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/01.png -------------------------------------------------------------------------------- /dataset/test/5/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/02.png -------------------------------------------------------------------------------- /dataset/test/5/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/03.png -------------------------------------------------------------------------------- /dataset/test/5/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/04.png -------------------------------------------------------------------------------- /dataset/test/5/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/05.png -------------------------------------------------------------------------------- /dataset/test/5/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/06.png -------------------------------------------------------------------------------- /dataset/test/5/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/07.png -------------------------------------------------------------------------------- /dataset/test/5/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/08.png -------------------------------------------------------------------------------- /dataset/test/5/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/09.png -------------------------------------------------------------------------------- /dataset/test/5/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/10.png -------------------------------------------------------------------------------- /dataset/test/5/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/11.png -------------------------------------------------------------------------------- /dataset/test/5/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/12.png -------------------------------------------------------------------------------- /dataset/test/5/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/13.png -------------------------------------------------------------------------------- /dataset/test/5/14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/14.png -------------------------------------------------------------------------------- /dataset/test/5/15.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/5/15.png -------------------------------------------------------------------------------- /dataset/test/6/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/00.png -------------------------------------------------------------------------------- /dataset/test/6/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/01.png -------------------------------------------------------------------------------- /dataset/test/6/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/02.png -------------------------------------------------------------------------------- /dataset/test/6/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/03.png -------------------------------------------------------------------------------- /dataset/test/6/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/04.png -------------------------------------------------------------------------------- /dataset/test/6/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/05.png -------------------------------------------------------------------------------- /dataset/test/6/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/06.png -------------------------------------------------------------------------------- /dataset/test/6/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/07.png -------------------------------------------------------------------------------- /dataset/test/6/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/08.png -------------------------------------------------------------------------------- /dataset/test/6/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/09.png -------------------------------------------------------------------------------- /dataset/test/6/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/10.png -------------------------------------------------------------------------------- /dataset/test/6/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/11.png -------------------------------------------------------------------------------- /dataset/test/6/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/12.png -------------------------------------------------------------------------------- /dataset/test/6/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/13.png -------------------------------------------------------------------------------- /dataset/test/6/14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/14.png -------------------------------------------------------------------------------- /dataset/test/6/15.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/15.png -------------------------------------------------------------------------------- /dataset/test/6/16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/16.png -------------------------------------------------------------------------------- /dataset/test/6/17.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/17.png -------------------------------------------------------------------------------- /dataset/test/6/18.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/6/18.png -------------------------------------------------------------------------------- /dataset/test/7/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/00.png -------------------------------------------------------------------------------- /dataset/test/7/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/01.png -------------------------------------------------------------------------------- /dataset/test/7/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/02.png -------------------------------------------------------------------------------- /dataset/test/7/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/03.png -------------------------------------------------------------------------------- /dataset/test/7/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/04.png -------------------------------------------------------------------------------- /dataset/test/7/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/05.png -------------------------------------------------------------------------------- /dataset/test/7/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/06.png -------------------------------------------------------------------------------- /dataset/test/7/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/07.png -------------------------------------------------------------------------------- /dataset/test/7/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/08.png -------------------------------------------------------------------------------- /dataset/test/7/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/09.png -------------------------------------------------------------------------------- /dataset/test/7/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/10.png -------------------------------------------------------------------------------- /dataset/test/7/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/11.png -------------------------------------------------------------------------------- /dataset/test/7/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/12.png -------------------------------------------------------------------------------- /dataset/test/7/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/13.png -------------------------------------------------------------------------------- /dataset/test/7/14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/7/14.png -------------------------------------------------------------------------------- /dataset/test/8/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/00.png -------------------------------------------------------------------------------- /dataset/test/8/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/01.png -------------------------------------------------------------------------------- /dataset/test/8/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/02.png -------------------------------------------------------------------------------- /dataset/test/8/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/03.png -------------------------------------------------------------------------------- /dataset/test/8/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/04.png -------------------------------------------------------------------------------- /dataset/test/8/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/05.png -------------------------------------------------------------------------------- /dataset/test/8/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/06.png -------------------------------------------------------------------------------- /dataset/test/8/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/07.png -------------------------------------------------------------------------------- /dataset/test/8/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/08.png -------------------------------------------------------------------------------- /dataset/test/8/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/09.png -------------------------------------------------------------------------------- /dataset/test/8/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/10.png -------------------------------------------------------------------------------- /dataset/test/8/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/8/11.png -------------------------------------------------------------------------------- /dataset/test/9/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/00.png -------------------------------------------------------------------------------- /dataset/test/9/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/01.png -------------------------------------------------------------------------------- /dataset/test/9/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/02.png -------------------------------------------------------------------------------- /dataset/test/9/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/03.png -------------------------------------------------------------------------------- /dataset/test/9/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/04.png -------------------------------------------------------------------------------- /dataset/test/9/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/05.png -------------------------------------------------------------------------------- /dataset/test/9/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/06.png -------------------------------------------------------------------------------- /dataset/test/9/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/07.png -------------------------------------------------------------------------------- /dataset/test/9/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/08.png -------------------------------------------------------------------------------- /dataset/test/9/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/09.png -------------------------------------------------------------------------------- /dataset/test/9/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/10.png -------------------------------------------------------------------------------- /dataset/test/9/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/11.png -------------------------------------------------------------------------------- /dataset/test/9/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/test/9/12.png -------------------------------------------------------------------------------- /dataset/train/0/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/00.png -------------------------------------------------------------------------------- /dataset/train/0/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/01.png -------------------------------------------------------------------------------- /dataset/train/0/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/02.png -------------------------------------------------------------------------------- /dataset/train/0/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/03.png -------------------------------------------------------------------------------- /dataset/train/0/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/04.png -------------------------------------------------------------------------------- /dataset/train/0/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/05.png -------------------------------------------------------------------------------- /dataset/train/0/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/06.png -------------------------------------------------------------------------------- /dataset/train/0/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/07.png -------------------------------------------------------------------------------- /dataset/train/0/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/08.png -------------------------------------------------------------------------------- /dataset/train/0/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/0/09.png -------------------------------------------------------------------------------- /dataset/train/1/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/00.png -------------------------------------------------------------------------------- /dataset/train/1/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/01.png -------------------------------------------------------------------------------- /dataset/train/1/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/02.png -------------------------------------------------------------------------------- /dataset/train/1/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/03.png -------------------------------------------------------------------------------- /dataset/train/1/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/04.png -------------------------------------------------------------------------------- /dataset/train/1/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/05.png -------------------------------------------------------------------------------- /dataset/train/1/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/06.png -------------------------------------------------------------------------------- /dataset/train/1/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/07.png -------------------------------------------------------------------------------- /dataset/train/1/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/08.png -------------------------------------------------------------------------------- /dataset/train/1/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/1/09.png -------------------------------------------------------------------------------- /dataset/train/10/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/00.png -------------------------------------------------------------------------------- /dataset/train/10/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/01.png -------------------------------------------------------------------------------- /dataset/train/10/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/02.png -------------------------------------------------------------------------------- /dataset/train/10/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/03.png -------------------------------------------------------------------------------- /dataset/train/10/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/04.png -------------------------------------------------------------------------------- /dataset/train/10/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/05.png -------------------------------------------------------------------------------- /dataset/train/10/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/06.png -------------------------------------------------------------------------------- /dataset/train/10/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/07.png -------------------------------------------------------------------------------- /dataset/train/10/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/08.png -------------------------------------------------------------------------------- /dataset/train/10/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/09.png -------------------------------------------------------------------------------- /dataset/train/10/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/10.png -------------------------------------------------------------------------------- /dataset/train/10/11.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/11.png -------------------------------------------------------------------------------- /dataset/train/10/12.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/12.png -------------------------------------------------------------------------------- /dataset/train/10/13.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/13.png -------------------------------------------------------------------------------- /dataset/train/10/14.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/14.png -------------------------------------------------------------------------------- /dataset/train/10/15.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/15.png -------------------------------------------------------------------------------- /dataset/train/10/16.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/16.png -------------------------------------------------------------------------------- /dataset/train/10/17.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/17.png -------------------------------------------------------------------------------- /dataset/train/10/18.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/18.png -------------------------------------------------------------------------------- /dataset/train/10/19.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/19.png -------------------------------------------------------------------------------- /dataset/train/10/20.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/20.png -------------------------------------------------------------------------------- /dataset/train/10/21.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/21.png -------------------------------------------------------------------------------- /dataset/train/10/22.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/22.png -------------------------------------------------------------------------------- /dataset/train/10/23.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/23.png -------------------------------------------------------------------------------- /dataset/train/10/24.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/24.png -------------------------------------------------------------------------------- /dataset/train/10/25.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/25.png -------------------------------------------------------------------------------- /dataset/train/10/26.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/26.png -------------------------------------------------------------------------------- /dataset/train/10/27.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/27.png -------------------------------------------------------------------------------- /dataset/train/10/28.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/28.png -------------------------------------------------------------------------------- /dataset/train/10/29.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/29.png -------------------------------------------------------------------------------- /dataset/train/10/30.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/30.png -------------------------------------------------------------------------------- /dataset/train/10/31.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/31.png -------------------------------------------------------------------------------- /dataset/train/10/32.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/32.png -------------------------------------------------------------------------------- /dataset/train/10/33.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/33.png -------------------------------------------------------------------------------- /dataset/train/10/34.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/34.png -------------------------------------------------------------------------------- /dataset/train/10/35.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/35.png -------------------------------------------------------------------------------- /dataset/train/10/36.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/36.png -------------------------------------------------------------------------------- /dataset/train/10/37.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/37.png -------------------------------------------------------------------------------- /dataset/train/10/38.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/38.png -------------------------------------------------------------------------------- /dataset/train/10/39.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/39.png -------------------------------------------------------------------------------- /dataset/train/10/40.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/40.png -------------------------------------------------------------------------------- /dataset/train/10/41.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/41.png -------------------------------------------------------------------------------- /dataset/train/10/42.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/42.png -------------------------------------------------------------------------------- /dataset/train/10/43.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/43.png -------------------------------------------------------------------------------- /dataset/train/10/44.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/44.png -------------------------------------------------------------------------------- /dataset/train/10/45.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/45.png -------------------------------------------------------------------------------- /dataset/train/10/46.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/46.png -------------------------------------------------------------------------------- /dataset/train/10/47.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/47.png -------------------------------------------------------------------------------- /dataset/train/10/48.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/48.png -------------------------------------------------------------------------------- /dataset/train/10/49.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/49.png -------------------------------------------------------------------------------- /dataset/train/10/50.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/50.png -------------------------------------------------------------------------------- /dataset/train/10/51.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/51.png -------------------------------------------------------------------------------- /dataset/train/10/52.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/52.png -------------------------------------------------------------------------------- /dataset/train/10/53.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/53.png -------------------------------------------------------------------------------- /dataset/train/10/54.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/54.png -------------------------------------------------------------------------------- /dataset/train/10/55.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/55.png -------------------------------------------------------------------------------- /dataset/train/10/56.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/56.png -------------------------------------------------------------------------------- /dataset/train/10/57.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/57.png -------------------------------------------------------------------------------- /dataset/train/10/58.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/58.png -------------------------------------------------------------------------------- /dataset/train/10/59.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/59.png -------------------------------------------------------------------------------- /dataset/train/10/60.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/60.png -------------------------------------------------------------------------------- /dataset/train/10/61.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/61.png -------------------------------------------------------------------------------- /dataset/train/10/62.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/62.png -------------------------------------------------------------------------------- /dataset/train/10/63.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/63.png -------------------------------------------------------------------------------- /dataset/train/10/64.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/64.png -------------------------------------------------------------------------------- /dataset/train/10/65.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/65.png -------------------------------------------------------------------------------- /dataset/train/10/66.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/66.png -------------------------------------------------------------------------------- /dataset/train/10/67.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/67.png -------------------------------------------------------------------------------- /dataset/train/10/68.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/68.png -------------------------------------------------------------------------------- /dataset/train/10/69.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/10/69.png -------------------------------------------------------------------------------- /dataset/train/2/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/00.png -------------------------------------------------------------------------------- /dataset/train/2/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/01.png -------------------------------------------------------------------------------- /dataset/train/2/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/02.png -------------------------------------------------------------------------------- /dataset/train/2/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/03.png -------------------------------------------------------------------------------- /dataset/train/2/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/04.png -------------------------------------------------------------------------------- /dataset/train/2/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/05.png -------------------------------------------------------------------------------- /dataset/train/2/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/06.png -------------------------------------------------------------------------------- /dataset/train/2/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/07.png -------------------------------------------------------------------------------- /dataset/train/2/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/08.png -------------------------------------------------------------------------------- /dataset/train/2/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/2/09.png -------------------------------------------------------------------------------- /dataset/train/3/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/00.png -------------------------------------------------------------------------------- /dataset/train/3/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/01.png -------------------------------------------------------------------------------- /dataset/train/3/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/02.png -------------------------------------------------------------------------------- /dataset/train/3/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/03.png -------------------------------------------------------------------------------- /dataset/train/3/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/04.png -------------------------------------------------------------------------------- /dataset/train/3/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/05.png -------------------------------------------------------------------------------- /dataset/train/3/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/06.png -------------------------------------------------------------------------------- /dataset/train/3/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/07.png -------------------------------------------------------------------------------- /dataset/train/3/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/08.png -------------------------------------------------------------------------------- /dataset/train/3/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/3/09.png -------------------------------------------------------------------------------- /dataset/train/4/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/00.png -------------------------------------------------------------------------------- /dataset/train/4/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/01.png -------------------------------------------------------------------------------- /dataset/train/4/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/02.png -------------------------------------------------------------------------------- /dataset/train/4/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/03.png -------------------------------------------------------------------------------- /dataset/train/4/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/04.png -------------------------------------------------------------------------------- /dataset/train/4/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/05.png -------------------------------------------------------------------------------- /dataset/train/4/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/06.png -------------------------------------------------------------------------------- /dataset/train/4/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/07.png -------------------------------------------------------------------------------- /dataset/train/4/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/08.png -------------------------------------------------------------------------------- /dataset/train/4/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/4/09.png -------------------------------------------------------------------------------- /dataset/train/5/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/00.png -------------------------------------------------------------------------------- /dataset/train/5/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/01.png -------------------------------------------------------------------------------- /dataset/train/5/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/02.png -------------------------------------------------------------------------------- /dataset/train/5/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/03.png -------------------------------------------------------------------------------- /dataset/train/5/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/04.png -------------------------------------------------------------------------------- /dataset/train/5/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/05.png -------------------------------------------------------------------------------- /dataset/train/5/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/06.png -------------------------------------------------------------------------------- /dataset/train/5/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/07.png -------------------------------------------------------------------------------- /dataset/train/5/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/5/08.png -------------------------------------------------------------------------------- /dataset/train/6/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/00.png -------------------------------------------------------------------------------- /dataset/train/6/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/01.png -------------------------------------------------------------------------------- /dataset/train/6/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/02.png -------------------------------------------------------------------------------- /dataset/train/6/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/03.png -------------------------------------------------------------------------------- /dataset/train/6/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/04.png -------------------------------------------------------------------------------- /dataset/train/6/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/05.png -------------------------------------------------------------------------------- /dataset/train/6/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/06.png -------------------------------------------------------------------------------- /dataset/train/6/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/07.png -------------------------------------------------------------------------------- /dataset/train/6/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/08.png -------------------------------------------------------------------------------- /dataset/train/6/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/6/09.png -------------------------------------------------------------------------------- /dataset/train/7/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/00.png -------------------------------------------------------------------------------- /dataset/train/7/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/01.png -------------------------------------------------------------------------------- /dataset/train/7/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/02.png -------------------------------------------------------------------------------- /dataset/train/7/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/03.png -------------------------------------------------------------------------------- /dataset/train/7/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/04.png -------------------------------------------------------------------------------- /dataset/train/7/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/05.png -------------------------------------------------------------------------------- /dataset/train/7/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/06.png -------------------------------------------------------------------------------- /dataset/train/7/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/07.png -------------------------------------------------------------------------------- /dataset/train/7/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/08.png -------------------------------------------------------------------------------- /dataset/train/7/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/7/09.png -------------------------------------------------------------------------------- /dataset/train/8/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/00.png -------------------------------------------------------------------------------- /dataset/train/8/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/01.png -------------------------------------------------------------------------------- /dataset/train/8/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/02.png -------------------------------------------------------------------------------- /dataset/train/8/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/03.png -------------------------------------------------------------------------------- /dataset/train/8/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/04.png -------------------------------------------------------------------------------- /dataset/train/8/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/05.png -------------------------------------------------------------------------------- /dataset/train/8/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/06.png -------------------------------------------------------------------------------- /dataset/train/8/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/07.png -------------------------------------------------------------------------------- /dataset/train/8/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/08.png -------------------------------------------------------------------------------- /dataset/train/8/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/8/09.png -------------------------------------------------------------------------------- /dataset/train/9/00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/00.png -------------------------------------------------------------------------------- /dataset/train/9/01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/01.png -------------------------------------------------------------------------------- /dataset/train/9/02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/02.png -------------------------------------------------------------------------------- /dataset/train/9/03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/03.png -------------------------------------------------------------------------------- /dataset/train/9/04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/04.png -------------------------------------------------------------------------------- /dataset/train/9/05.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/05.png -------------------------------------------------------------------------------- /dataset/train/9/06.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/06.png -------------------------------------------------------------------------------- /dataset/train/9/07.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/07.png -------------------------------------------------------------------------------- /dataset/train/9/08.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/08.png -------------------------------------------------------------------------------- /dataset/train/9/09.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/09.png -------------------------------------------------------------------------------- /dataset/train/9/10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/dataset/train/9/10.png -------------------------------------------------------------------------------- /docs/modules_pins_eng.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/docs/modules_pins_eng.docx -------------------------------------------------------------------------------- /images/Conn-Foto-1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Conn-Foto-1.jpg -------------------------------------------------------------------------------- /images/Conn-Foto-2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Conn-Foto-2.jpg -------------------------------------------------------------------------------- /images/Connect-Detailed.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Connect-Detailed.jpg -------------------------------------------------------------------------------- /images/Connection-photo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Connection-photo.jpg -------------------------------------------------------------------------------- /images/Connection-scheme.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Connection-scheme.png -------------------------------------------------------------------------------- /images/Info-Table.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Info-Table.png -------------------------------------------------------------------------------- /images/Neural-Net-Structure.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Neural-Net-Structure.png -------------------------------------------------------------------------------- /images/Q-scr-2019-02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Q-scr-2019-02.png -------------------------------------------------------------------------------- /images/QV_01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/QV_01.png -------------------------------------------------------------------------------- /images/QV_02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/QV_02.png -------------------------------------------------------------------------------- /images/QV_03.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/QV_03.png -------------------------------------------------------------------------------- /images/QV_04.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/QV_04.png -------------------------------------------------------------------------------- /images/Video-screen.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Video-screen.jpg -------------------------------------------------------------------------------- /images/Video-screen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/images/Video-screen.png -------------------------------------------------------------------------------- /r01_train_neural_net_and_prepare_initial_weights.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/r01_train_neural_net_and_prepare_initial_weights.py -------------------------------------------------------------------------------- /r02_rescale_weights_to_use_fixed_point_representation.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/r02_rescale_weights_to_use_fixed_point_representation.py -------------------------------------------------------------------------------- /r03_find_optimal_bit_for_weights.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/r03_find_optimal_bit_for_weights.py -------------------------------------------------------------------------------- /r04_verilog_generator_grayscale_file.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/r04_verilog_generator_grayscale_file.py -------------------------------------------------------------------------------- /r05_verilog_generator_neural_net_structure.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/r05_verilog_generator_neural_net_structure.py -------------------------------------------------------------------------------- /utils/convert_image_for_testbench.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/utils/convert_image_for_testbench.py -------------------------------------------------------------------------------- /verilog/code/gray_28x28/grayscale.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/gray_28x28/grayscale.v -------------------------------------------------------------------------------- /verilog/code/lcd/hellosoc_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/lcd/hellosoc_top.sv -------------------------------------------------------------------------------- /verilog/code/lcd/tft_ili9341.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/lcd/tft_ili9341.sv -------------------------------------------------------------------------------- /verilog/code/lcd/tft_ili9341_spi.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/lcd/tft_ili9341_spi.sv -------------------------------------------------------------------------------- /verilog/code/neuroset/RAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/RAM.v -------------------------------------------------------------------------------- /verilog/code/neuroset/RAMtoMEM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/RAMtoMEM.v -------------------------------------------------------------------------------- /verilog/code/neuroset/TOP.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/TOP.v -------------------------------------------------------------------------------- /verilog/code/neuroset/addressRAM.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/addressRAM.v -------------------------------------------------------------------------------- /verilog/code/neuroset/border.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/border.v -------------------------------------------------------------------------------- /verilog/code/neuroset/conv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/conv.v -------------------------------------------------------------------------------- /verilog/code/neuroset/conv_TOP.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/conv_TOP.v -------------------------------------------------------------------------------- /verilog/code/neuroset/database.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/database.v -------------------------------------------------------------------------------- /verilog/code/neuroset/dense.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/dense.v -------------------------------------------------------------------------------- /verilog/code/neuroset/maxpooling.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/maxpooling.v -------------------------------------------------------------------------------- /verilog/code/neuroset/result.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/neuroset/result.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/OV7670_config.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_config/OV7670_config.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/OV7670_config_rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_config/OV7670_config_rom.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/SCCB_interface.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_config/SCCB_interface.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/camera_configure.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_config/camera_configure.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/camera_read.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_config/camera_read.v -------------------------------------------------------------------------------- /verilog/code/synt/cam_config/source.txt: -------------------------------------------------------------------------------- 1 | source: https://github.com/westonb/OV7670-Verilog -------------------------------------------------------------------------------- /verilog/code/synt/cam_wrp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/cam_wrp.v -------------------------------------------------------------------------------- /verilog/code/synt/delay_rg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/delay_rg.v -------------------------------------------------------------------------------- /verilog/code/synt/fifo_1024x16.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/fifo_1024x16.qip -------------------------------------------------------------------------------- /verilog/code/synt/fifo_1024x16.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/fifo_1024x16.v -------------------------------------------------------------------------------- /verilog/code/synt/fsm_global.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/fsm_global.sv -------------------------------------------------------------------------------- /verilog/code/synt/sdram_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/synt/sdram_controller.v -------------------------------------------------------------------------------- /verilog/code/testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/code/testbench.v -------------------------------------------------------------------------------- /verilog/imp/cam_proj.qpf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/cam_proj.qpf -------------------------------------------------------------------------------- /verilog/imp/cam_proj.qsf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/cam_proj.qsf -------------------------------------------------------------------------------- /verilog/imp/cam_proj.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/cam_proj.qws -------------------------------------------------------------------------------- /verilog/imp/cam_proj_assignment_defaults.qdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/cam_proj_assignment_defaults.qdf -------------------------------------------------------------------------------- /verilog/imp/fifo_big.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/fifo_big.qip -------------------------------------------------------------------------------- /verilog/imp/fifo_big.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/fifo_big.v -------------------------------------------------------------------------------- /verilog/imp/fifo_big_bb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/fifo_big_bb.v -------------------------------------------------------------------------------- /verilog/imp/pll.ppf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll.ppf -------------------------------------------------------------------------------- /verilog/imp/pll.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll.qip -------------------------------------------------------------------------------- /verilog/imp/pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll.v -------------------------------------------------------------------------------- /verilog/imp/pll_bb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll_bb.v -------------------------------------------------------------------------------- /verilog/imp/pll_for_disp.ppf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll_for_disp.ppf -------------------------------------------------------------------------------- /verilog/imp/pll_for_disp.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll_for_disp.qip -------------------------------------------------------------------------------- /verilog/imp/pll_for_disp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll_for_disp.v -------------------------------------------------------------------------------- /verilog/imp/pll_for_disp_bb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/imp/pll_for_disp_bb.v -------------------------------------------------------------------------------- /verilog/top/cam_proj_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/verilog/top/cam_proj_top.v -------------------------------------------------------------------------------- /weights/keras_model_low_weights_digit_detector.h5: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/weights/keras_model_low_weights_digit_detector.h5 -------------------------------------------------------------------------------- /weights/keras_model_low_weights_digit_detector.h5.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/weights/keras_model_low_weights_digit_detector.h5.csv -------------------------------------------------------------------------------- /weights/keras_model_low_weights_digit_detector.h5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/weights/keras_model_low_weights_digit_detector.h5.png -------------------------------------------------------------------------------- /weights/keras_model_low_weights_digit_detector_rescaled.h5: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/weights/keras_model_low_weights_digit_detector_rescaled.h5 -------------------------------------------------------------------------------- /weights/optimal_bit.pklz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/HEAD/weights/optimal_bit.pklz --------------------------------------------------------------------------------