├── .circleci └── config.yml ├── .gitignore ├── Makefile ├── README.md ├── bench ├── cpp │ ├── Makefile │ ├── rtcdate_tb.cpp │ ├── testb.h │ ├── twoc.cpp │ └── twoc.h └── formal │ ├── .gitignore │ ├── Makefile │ ├── rtcalarm.sby │ ├── rtcbare.sby │ ├── rtcclock.ys │ ├── rtcdate.sby │ ├── rtcgps.sby │ ├── rtclight.sby │ ├── rtcstopwatch.sby │ └── rtctimer.sby ├── doc ├── .gitignore ├── Makefile ├── gpl-3.0.pdf ├── spec.pdf └── src │ ├── GT.eps │ ├── gpl-3.0.tex │ ├── gqtekspec.cls │ └── spec.tex ├── rtcclock.core └── rtl ├── Makefile ├── hexmap.v ├── rtcalarm.v ├── rtcbare.v ├── rtcclock.v ├── rtcdate.v ├── rtcgps.v ├── rtclight.v ├── rtcstopwatch.v └── rtctimer.v /.circleci/config.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | jobs: 3 | build: 4 | docker: 5 | - image: circleci/ruby:2.4.1 6 | steps: 7 | - checkout 8 | - run: 9 | name: Verilator lint check 10 | command: | 11 | echo "make rtl" 12 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | legal.txt 2 | .svn 3 | xilinx 4 | obj_dir 5 | obj-pc 6 | obj-zip 7 | *.o 8 | *.a 9 | *.vcd 10 | .*.swp 11 | .*.swo 12 | svn-commit* 13 | *_tb 14 | *_tb.dbl 15 | *dbg.txt 16 | *dump.txt 17 | tags 18 | cpudefs.h 19 | *.smt2 20 | *.check 21 | *.yslog 22 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: Makefile 4 | ## {{{ 5 | ## Project: A Wishbone Controlled Real--time Clock Core 6 | ## 7 | ## Purpose: 8 | ## 9 | ## Creator: Dan Gisselquist, Ph.D. 10 | ## Gisselquist Technology, LLC 11 | ## 12 | ################################################################################ 13 | ## }}} 14 | ## Copyright (C) 2015-2024, Gisselquist Technology, LLC 15 | ## {{{ 16 | ## This program is free software (firmware): you can redistribute it and/or 17 | ## modify it under the terms of the GNU General Public License as published 18 | ## by the Free Software Foundation, either version 3 of the License, or (at 19 | ## your option) any later version. 20 | ## 21 | ## This program is distributed in the hope that it will be useful, but WITHOUT 22 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 23 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 24 | ## for more details. 25 | ## 26 | ## You should have received a copy of the GNU General Public License along 27 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 28 | ## target there if the PDF file isn't present.) If not, see 29 | ## for a copy. 30 | ## }}} 31 | ## License: GPL, v3, as defined and found on www.gnu.org, 32 | ## {{{ 33 | ## http://www.gnu.org/licenses/gpl.html 34 | ## 35 | ## 36 | ################################################################################ 37 | ## 38 | ## }}} 39 | all: rtl bench 40 | ci: rtl bench doc 41 | SUBMAKE := $(MAKE) --no-print-directory -C 42 | 43 | .PHONY: doc 44 | ## {{{ 45 | doc: 46 | $(SUBMAKE) doc 47 | ## }}} 48 | 49 | .PHONY: rtl 50 | ## {{{ 51 | rtl: 52 | $(SUBMAKE) rtl 53 | ## }}} 54 | 55 | .PHONY: bench 56 | ## {{{ 57 | bench: rtl 58 | $(SUBMAKE) bench/formal 59 | ## }}} 60 | 61 | .PHONY: clean 62 | ## {{{ 63 | clean: 64 | $(SUBMAKE) rtl clean 65 | $(SUBMAKE) bench/formal clean 66 | ## }}} 67 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Real Time Clock Core 2 | 3 | Every FPGA project needs to start with a very simple core. Then, working from 4 | simplicity, more and more complex cores can be built until an eventual 5 | application comes from all the tiny details. 6 | 7 | This real time clock began with one such simple core. All of the pieces to 8 | this clock are simple. Nothing is inherently complex. However, placing this 9 | clock into a larger FPGA structure requires a Wishbone bus, and being able 10 | to command and control an FPGA over a wishbone bus is an achievement in and 11 | of itself. Further, the clock produces outputs that can be used to strobe 12 | an interrupt line. Reading and processing that interrupt line requires 13 | a whole 'nother bit of logic and the ability to capture, recognize, and 14 | respond to interrupts. Hence, once you get a simple clock working, you have 15 | a lot working. 16 | 17 | Included in this repository are several basic cores which can be 18 | used for this purpose: 19 | 20 | - [rtcclock](rtl/rtcclock.v): the original RTC Clock module. This was originally built for a Basys-3 board, and so it also has outputs suitable for commanding LEDs and a seven segment display. 21 | - [rtclight](rtl/rtclight.v): Just the basic RTC, with no LEDs or seven segment display output wires. 22 | - [rtcgps](rtl/rtcgps.v): A real-time clock which can be used together with a cleaned-up GPS PPS, to keep the clock accurate at a subsecond level to the top of the second. Further work is required to get the clock to the correct second, but this will hold it to the correct subsecond interval. 23 | 24 | Since this repository was originally created, the component pieces of the various clocks have been refactored. These are now separate components: 25 | 26 | - [rtcbare](rtl/rtcbare.v): is the bare bones clock itself. This depends upon a PPS signal being given to it, but other wise it will keep track of the time in a BCD formatted register. 27 | - [rtctimer](rtl/rtctimer.v): is a BCD count-down timer. Once zero is reached, an interrupt is created. 28 | - [rtcstopwatch](rtl/rtcstopwatch.v): is a BCD stopwatch that generates a BCD stopwatch containing centi-seconds (10ms) resolution, seconds, minutes, and hours. 29 | - [rtcalarm](rtl/rtcalarm.v): This is a simple component, since it works by comparing the current time against a saved value. Once the value is reached, an alarm is set as an output interrupt wire. 30 | -------------------------------------------------------------------------------- /bench/cpp/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: Makefile 4 | ## {{{ 5 | ## Project: A Wishbone Controlled Real--time Clock Core 6 | ## 7 | ## Purpose: This programs the build process for the test benches 8 | ## associated with the real--time clock (and date) core(s). 9 | ## 10 | ## Creator: Dan Gisselquist, Ph.D. 11 | ## Gisselquist Tecnology, LLC 12 | ## 13 | ################################################################################ 14 | ## }}} 15 | ## Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | ## {{{ 17 | ## This program is free software (firmware): you can redistribute it and/or 18 | ## modify it under the terms of the GNU General Public License as published 19 | ## by the Free Software Foundation, either version 3 of the License, or (at 20 | ## your option) any later version. 21 | ## 22 | ## This program is distributed in the hope that it will be useful, but WITHOUT 23 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | ## for more details. 26 | ## 27 | ## You should have received a copy of the GNU General Public License along 28 | ## with this program. (It's in the $(ROOT)/doc directory, run make with no 29 | ## target there if the PDF file isn't present.) If not, see 30 | ## for a copy. 31 | ## }}} 32 | ## License: GPL, v3, as defined and found on www.gnu.org, 33 | ## {{{ 34 | ## http://www.gnu.org/licenses/gpl.html 35 | ## 36 | ##########################################################################/ 37 | ## }}} 38 | all: rtcdate_tb 39 | # all: rtcclock_tb # rtcclock_tb is not yet written ... 40 | # all: test 41 | CXX := g++ 42 | FLAGS := -Wall -Og -g 43 | OBJDIR := obj-pc 44 | RTLD := ../../rtl 45 | VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"') 46 | VROOT := $(VERILATOR_ROOT) 47 | INCS := -I$(RTLD)/obj_dir/ -I$(VROOT)/include 48 | VOBJDR := $(RTLD)/obj_dir 49 | SYSVDR := $(VROOT)/include 50 | VSRC := verilated.cpp verilated_vcd_c.cpp verilated_threads.cpp 51 | VLIB := $(addprefix $(OBJDIR)/,$(subst .cpp,.o,$(VSRC))) 52 | VINC := -I$(VROOT)/include -I$(VOBJDR)/ 53 | CLKSRCS:= rtcclock_tb.cpp 54 | CLKOBJ := $(subst .cpp,.o,$(CLKSRCS)) 55 | CLKOBJS:= $(addprefix $(OBJDIR)/,$(CLKOBJ)) $(VLIB) 56 | CLKGLB:= $(VOBJDR)/Vrtcgps__ALL.a 57 | CKGSRCS:= rtcgps_tb.cpp 58 | CKGOBJ := $(subst .cpp,.o,$(CKGSRCS)) 59 | CKGOBJS:= $(addprefix $(OBJDIR)/,$(CKGOBJ)) $(VLIB) 60 | CKGLB:= $(VOBJDR)/Vrtcgps__ALL.a 61 | DATSRCS:= rtcdate_tb.cpp 62 | DATOBJ := $(subst .cpp,.o,$(DATSRCS)) 63 | DATOBJS:= $(addprefix $(OBJDIR)/,$(DATOBJ)) $(VLIB) 64 | DATLB:= $(VOBJDR)/Vrtcdate__ALL.a 65 | SOURCES := $(DATSRCS) 66 | 67 | $(OBJDIR)/%.o: %.cpp 68 | $(mk-objdir) 69 | $(CXX) $(FLAGS) $(INCS) -c $< -o $@ 70 | 71 | $(OBJDIR)/%.o: $(SYSVDR)/%.cpp 72 | $(mk-objdir) 73 | $(CXX) $(FLAGS) $(INCS) -c $< -o $@ 74 | 75 | rtcclock_tb: $(CLKOBJS) $(CLKLB) 76 | $(CXX) $(FLAGS) $(INCS) $^ -lpthread -o $@ 77 | 78 | rtcdate_tb: $(DATOBJS) $(DATLB) 79 | $(CXX) $(FLAGS) $(INCS) $^ -lpthread -o $@ 80 | 81 | .PHONY: test 82 | test: rtcclock_tb rtcdate_tb 83 | ./rtcclock_tb 84 | ./rtcdate_tb 85 | 86 | # 87 | define mk-objdir 88 | @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi" 89 | endef 90 | 91 | # 92 | # The "tags" target 93 | ## {{{ 94 | tags: $(SOURCES) $(HEADERS) 95 | @echo "Generating tags" 96 | @ctags $(SOURCES) $(HEADERS) 97 | ## }}} 98 | 99 | .PHONY: clean 100 | ## {{{ 101 | clean: 102 | rm -f rtcclock_tb rtcdate_tb 103 | rm -rf $(OBJDIR)/ 104 | ## }}} 105 | 106 | ## Depends 107 | ## {{{ 108 | # The "depends" target, to know what files things depend upon. The depends 109 | # file itself is kept in $(OBJDIR)/depends.txt 110 | # 111 | define build-depends 112 | $(mk-objdir) 113 | @echo "Building dependency file" 114 | @$(CXX) $(CFLAGS) $(INCS) -MM $(SOURCES) > $(OBJDIR)/xdepends.txt 115 | @sed -e 's/^.*.o: /$(OBJDIR)\/&/' < $(OBJDIR)/xdepends.txt > $(OBJDIR)/depends.txt 116 | @rm $(OBJDIR)/xdepends.txt 117 | endef 118 | 119 | .PHONY: depends 120 | ## {{{ 121 | depends: tags 122 | $(build-depends) 123 | ## }}} 124 | 125 | $(OBJDIR)/depends.txt: depends 126 | 127 | -include $(OBJDIR)/depends.txt 128 | ## }}} 129 | -------------------------------------------------------------------------------- /bench/cpp/rtcdate_tb.cpp: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcdate_tb.cpp 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core 6 | // 7 | // Purpose: To exercise the functionality of the real-time date core. 8 | // If this program works, (and works properly) it will exit 9 | // with an exit code of zero if the core works, and a negative number if 10 | // not. Further, on the last line it will state either SUCCESS or FAIL. 11 | // This program should take no arguments. 12 | // 13 | // This program makes heavy use of the mktime() and gmtime_r libc calls. 14 | // As a result, it really checks that the rtcdate module produces the same 15 | // dates as the libc library. Any differences will be cause for immediate 16 | // test termination and failure. 17 | // 18 | // As of 17 July, 2015, rtcdate.v passes this test. 19 | // 20 | // Creator: Dan Gisselquist, Ph.D. 21 | // Gisselquist Tecnology, LLC 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | // }}} 25 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 26 | // {{{ 27 | // This program is free software (firmware): you can redistribute it and/or 28 | // modify it under the terms of the GNU General Public License as published 29 | // by the Free Software Foundation, either version 3 of the License, or (at 30 | // your option) any later version. 31 | // 32 | // This program is distributed in the hope that it will be useful, but WITHOUT 33 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 34 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 35 | // for more details. 36 | // 37 | // You should have received a copy of the GNU General Public License along 38 | // with this program. (It's in the $(ROOT)/doc directory, run make with no 39 | // target there if the PDF file isn't present.) If not, see 40 | // for a copy. 41 | // }}} 42 | // License: GPL, v3, as defined and found on www.gnu.org, 43 | // {{{ 44 | // http://www.gnu.org/licenses/gpl.html 45 | // 46 | //////////////////////////////////////////////////////////////////////////////// 47 | // 48 | // }}} 49 | #include 50 | #include 51 | #include 52 | 53 | #include "verilated.h" 54 | #include "Vrtcdate.h" 55 | 56 | #include "testb.h" 57 | #include "twoc.h" 58 | 59 | typedef unsigned int BUSV; // Wishbone value 60 | class RTCDATE_TB : public TESTB { 61 | public: 62 | BUSV read(void) { 63 | // {{{ 64 | BUSV result; 65 | 66 | m_core->i_wb_cyc = 1; 67 | m_core->i_wb_stb = 1; 68 | m_core->i_wb_we = 0; 69 | m_core->i_ppd = 0; 70 | tick(); 71 | m_core->i_wb_stb = 0; 72 | // tick(); 73 | 74 | assert(m_core->o_wb_stall == 0); 75 | assert(m_core->o_wb_ack == 1); 76 | result = m_core->o_wb_data; 77 | 78 | m_core->i_wb_cyc = 0; 79 | m_core->i_wb_stb = 0; 80 | m_core->i_wb_we = 0; 81 | m_core->i_ppd = 0; 82 | // printf("WB-READ = %08x\n", m_core->o_wb_data); 83 | 84 | tick(); 85 | 86 | assert(m_core->o_wb_stall == 0); 87 | assert(m_core->o_wb_ack == 0); 88 | 89 | return result; 90 | // }}} 91 | } 92 | 93 | void write(BUSV val) { 94 | // {{{ 95 | // printf("WB-WRITE(%08x)\n", val); 96 | m_core->i_wb_cyc = 1; 97 | m_core->i_wb_stb = 1; 98 | m_core->i_wb_we = 1; 99 | m_core->i_wb_data = val; 100 | m_core->i_wb_sel = 15; 101 | m_core->i_ppd = 0; 102 | tick(); 103 | 104 | m_core->i_wb_cyc = 1; 105 | m_core->i_wb_stb = 0; 106 | m_core->i_wb_we = 0; 107 | m_core->i_ppd = 0; 108 | 109 | assert(m_core->o_wb_stall == 0); 110 | assert(m_core->o_wb_ack == 1); 111 | // printf("%08x =? %08x\n", m_core->o_wb_data, val); 112 | 113 | m_core->i_wb_cyc = 0; 114 | m_core->i_wb_stb = 0; 115 | m_core->i_wb_we = 0; 116 | m_core->i_ppd = 0; 117 | tick(); 118 | 119 | // Let the write propagate through before we inspect it 120 | for(int i=0; i<12; i++) { 121 | tick(); 122 | 123 | // printf("%08x =? %08x\n", m_core->o_wb_data, val); 124 | assert(m_core->o_wb_stall == 0); 125 | assert(m_core->o_wb_ack == 0); 126 | } 127 | // }}} 128 | } 129 | 130 | 131 | BUSV encode(time_t when) { 132 | // {{{ 133 | BUSV bv; 134 | struct tm tv; 135 | gmtime_r(&when, &tv); 136 | 137 | int yr = tv.tm_year + 1900; 138 | bv = yr/1000; bv <<= 4; 139 | bv |= (yr/100)%10; bv <<= 4; 140 | bv |= (yr/10)%10; bv <<= 4; 141 | bv |= yr%10; bv <<= 4; 142 | 143 | int mo = tv.tm_mon+1; 144 | bv |= (mo/10); bv <<= 4; 145 | bv |= (mo%10); bv <<= 4; 146 | 147 | int dy = tv.tm_mday; 148 | bv |= (dy/10); bv <<= 4; 149 | bv |= (dy%10); 150 | 151 | return bv; 152 | // }}} 153 | } 154 | 155 | void set(time_t when) { 156 | write(encode(when)); 157 | } 158 | 159 | bool check(time_t when) { 160 | // {{{ 161 | BUSV bv = encode(when), rv; 162 | rv = read(); 163 | if (bv != rv) { 164 | printf("FAIL: %08x(exp) != %08x (read)\n", bv, rv); 165 | exit(-2); 166 | } 167 | return (bv == rv); 168 | // }}} 169 | } 170 | 171 | void next(void) { 172 | // {{{ 173 | m_core->i_ppd = 1; 174 | m_core->i_wb_cyc = 0; 175 | m_core->i_wb_stb = 0; 176 | 177 | tick(); 178 | 179 | m_core->i_ppd = 0; 180 | m_core->i_wb_cyc = 0; 181 | m_core->i_wb_stb = 0; 182 | 183 | for(int k=0; k<5; k++) 184 | tick(); 185 | // }}} 186 | } 187 | }; 188 | 189 | int main(int argc, char **argv) { 190 | Verilated::commandArgs(argc, argv); 191 | RTCDATE_TB *tb = new RTCDATE_TB; 192 | time_t start, when, stop; 193 | 194 | tb->opentrace("rtcdate.vcd"); 195 | struct tm tv; 196 | bzero(&tv, sizeof(struct tm)); 197 | 198 | // Set to January 1st, 1970, around noon 199 | tv.tm_sec = 0; 200 | tv.tm_min = 0; 201 | tv.tm_hour = 12; 202 | tv.tm_mday = 1; 203 | tv.tm_mon = 0; 204 | tv.tm_year = 70; 205 | start = mktime(&tv); 206 | 207 | // Set to January 1st, 2400, around noon 208 | tv.tm_sec = 0; 209 | tv.tm_min = 0; 210 | tv.tm_hour = 12; 211 | tv.tm_mday = 1; 212 | tv.tm_mon = 0; 213 | tv.tm_year = 4000-1900; 214 | stop = mktime(&tv) - 60*60*24; 215 | 216 | tb->tick(); 217 | tb->tick(); 218 | 219 | tb->set(start); 220 | printf("Initial date: %08x\n", tb->read()); 221 | 222 | for(when=start; when < stop; when+= 60*60*24) { 223 | assert(tb->check(when)); 224 | tb->next(); 225 | } 226 | 227 | printf("Final date : %08x\n", tb->read()); 228 | printf("SUCCESS!\n"); 229 | return 0; 230 | } 231 | -------------------------------------------------------------------------------- /bench/cpp/testb.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: testb.h 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core 6 | // 7 | // Purpose: A wrapper for a common interface to a clocked FPGA core 8 | // begin exercised in Verilator. 9 | // 10 | // Creator: Dan Gisselquist, Ph.D. 11 | // Gisselquist Technology, LLC 12 | // 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // }}} 15 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | // {{{ 17 | // This program is free software (firmware): you can redistribute it and/or 18 | // modify it under the terms of the GNU General Public License as published 19 | // by the Free Software Foundation, either version 3 of the License, or (at 20 | // your option) any later version. 21 | // 22 | // This program is distributed in the hope that it will be useful, but WITHOUT 23 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | // for more details. 26 | // 27 | // You should have received a copy of the GNU General Public License along 28 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | // target there if the PDF file isn't present.) If not, see 30 | // for a copy. 31 | // }}} 32 | // License: GPL, v3, as defined and found on www.gnu.org, 33 | // {{{ 34 | // http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // }}} 39 | #ifndef TESTB_H 40 | #define TESTB_H 41 | 42 | #include 43 | #include 44 | #include 45 | 46 | #define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0); 47 | 48 | template class TESTB { 49 | public: 50 | VA *m_core; 51 | VerilatedVcdC* m_trace; 52 | unsigned long m_tickcount; 53 | 54 | TESTB(void) : m_trace(NULL), m_tickcount(0l) { 55 | m_core = new VA; 56 | Verilated::traceEverOn(true); 57 | m_core->i_clk = 0; 58 | eval(); // Get our initial values set properly. 59 | } 60 | virtual ~TESTB(void) { 61 | closetrace(); 62 | delete m_core; 63 | m_core = NULL; 64 | } 65 | 66 | virtual void opentrace(const char *vcdname) { 67 | if (!m_trace) { 68 | m_trace = new VerilatedVcdC; 69 | m_core->trace(m_trace, 99); 70 | m_trace->open(vcdname); 71 | } 72 | } 73 | 74 | virtual void closetrace(void) { 75 | if (m_trace) { 76 | m_trace->close(); 77 | delete m_trace; 78 | m_trace = NULL; 79 | } 80 | } 81 | 82 | virtual void eval(void) { 83 | m_core->eval(); 84 | } 85 | 86 | virtual void tick(void) { 87 | m_tickcount++; 88 | 89 | // Make sure we have our evaluations straight before the top 90 | // of the clock. This is necessary since some of the 91 | // connection modules may have made changes, for which some 92 | // logic depends. This forces that logic to be recalculated 93 | // before the top of the clock. 94 | eval(); 95 | if (m_trace) m_trace->dump(10*m_tickcount-2); 96 | m_core->i_clk = 1; 97 | eval(); 98 | if (m_trace) m_trace->dump(10*m_tickcount); 99 | m_core->i_clk = 0; 100 | eval(); 101 | if (m_trace) { 102 | m_trace->dump(10*m_tickcount+5); 103 | m_trace->flush(); 104 | } 105 | } 106 | 107 | unsigned long tickcount(void) { 108 | return m_tickcount; 109 | } 110 | }; 111 | 112 | #endif 113 | -------------------------------------------------------------------------------- /bench/cpp/twoc.cpp: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: twoc.cpp 4 | // {{{ 5 | // Project: A Doubletime Pipelined FFT 6 | // 7 | // Purpose: Some various two's complement related C++ helper routines. 8 | // Specifically, these help extract signed numbers from 9 | // packed bitfields, while guaranteeing that the upper bits are properly 10 | // sign extended (or not) as desired. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Tecnology, LLC 14 | // 15 | /////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory, run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | /////////////////////////////////////////////////////////////////////////// 39 | // }}} 40 | #include 41 | #include "twoc.h" 42 | 43 | long sbits(const long val, const int bits) { 44 | // {{{ 45 | long r; 46 | 47 | r = val & ((1l<>1, bits_out); 69 | // printf("TEST! S = %ld, T = %ld\n", s, t); 70 | if (3 == (s&3)) 71 | t = t+1; 72 | return t; 73 | } else { 74 | // A. 0XXXX.0xxxxx -> 0XXXX 75 | // B. 0XXX0.100000 -> 0XXX0; 76 | // C. 0XXX1.100000 -> 0XXX1+1; 77 | // D. 0XXXX.1zzzzz -> 0XXXX+1; 78 | // E. 1XXXX.0xxxxx -> 1XXXX 79 | // F. 1XXX0.100000 -> ??? XXX0; 80 | // G. 1XXX1.100000 -> ??? XXX1+1; 81 | // H. 1XXXX.1zzzzz -> 1XXXX+1; 82 | t = sbits(val>>(bits_in-bits_out), bits_out); // Truncated value 83 | if (0 == ((s >> (bits_in-bits_out-1))&1)) { 84 | // printf("A\n"); 85 | return t; 86 | } else if (0 != (s & ((1<<(bits_in-bits_out-1))-1))) { 87 | // printf("D\n"); 88 | return t+1; 89 | } else if (t&1) { 90 | // printf("C\n"); 91 | return t+1; 92 | } else { // 3 ..?11 93 | // printf("B\n"); 94 | return t; 95 | } 96 | } 97 | // }}} 98 | } 99 | -------------------------------------------------------------------------------- /bench/cpp/twoc.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: twoc.h 4 | // {{{ 5 | // Project: A Doubletime Pipelined FFT 6 | // 7 | // Purpose: Some various two's complement related C++ helper routines. 8 | // Specifically, these help extract signed numbers from packed 9 | // bitfields, while guaranteeing that the upper bits are properly sign 10 | // extended (or not) as desired. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Tecnology, LLC 14 | // 15 | /////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory, run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | /////////////////////////////////////////////////////////////////////////// 39 | // }}} 40 | #ifndef TWOC_H 41 | #define TWOC_H 42 | 43 | extern long sbits(const long val, const int bits); 44 | extern unsigned long ubits(const long val, const int bits); 45 | extern unsigned long rndbits(const long val, const int bi, const int bo); 46 | 47 | #endif 48 | 49 | -------------------------------------------------------------------------------- /bench/formal/.gitignore: -------------------------------------------------------------------------------- 1 | rtcalarm_*/ 2 | rtcbare_*/ 3 | rtcdate_*/ 4 | rtcgps_*/ 5 | rtclight_*/ 6 | rtcstopwatch_*/ 7 | rtctimer_*/ 8 | -------------------------------------------------------------------------------- /bench/formal/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: Makefile 4 | ## {{{ 5 | ## Project: A Wishbone Controlled Real--time Clock Core 6 | ## 7 | ## Purpose: To direct the formal verification of the real time 8 | ## clock core, its brethren and its children. 9 | ## 10 | ## Targets: The default target, all, tests all of the components tested 11 | ## within this module. Each tested top-level component will 12 | ## result in a _/PASS file placed in the given test 13 | ## subdirectory. 14 | ## 15 | ## Creator: Dan Gisselquist, Ph.D. 16 | ## Gisselquist Technology, LLC 17 | ## 18 | ################################################################################ 19 | ## }}} 20 | ## Copyright (C) 2017-2024, Gisselquist Technology, LLC 21 | ## {{{ 22 | ## This program is free software (firmware): you can redistribute it and/or 23 | ## modify it under the terms of the GNU General Public License as published 24 | ## by the Free Software Foundation, either version 3 of the License, or (at 25 | ## your option) any later version. 26 | ## 27 | ## This program is distributed in the hope that it will be useful, but WITHOUT 28 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 29 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 30 | ## for more details. 31 | ## 32 | ## You should have received a copy of the GNU General Public License along 33 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 34 | ## target there if the PDF file isn't present.) If not, see 35 | ## for a copy. 36 | ## }}} 37 | ## License: GPL, v3, as defined and found on www.gnu.org, 38 | ## {{{ 39 | ## http://www.gnu.org/licenses/gpl.html 40 | ## 41 | ## 42 | ################################################################################ 43 | ## 44 | ## }}} 45 | TESTS:=rtcdate rtctimer rtcstopwatch rtcalarm rtcbare rtcgps rtclight # rtcclock 46 | .PHONY: $(TESTS) 47 | all: $(TESTS) 48 | RTL := ../../rtl 49 | 50 | SMTBMC := yosys-smtbmc 51 | # SOLVER := -s z3 52 | SOLVER := -s yices 53 | # SOLVER := -s boolector 54 | BMCARGS := --presat $(SOLVER) 55 | INDARGS := $(SOLVER) -i 56 | 57 | DATE := rtcdate 58 | RTCCK := rtcclock 59 | RTCLT := rtclight 60 | RTCGPS := rtcgps 61 | TIMER := rtctimer 62 | SWATCH := rtcstopwatch 63 | ALARM := rtcalarm 64 | BARE := rtcbare 65 | 66 | $(DATE) : $(DATE)_prf/PASS 67 | ## {{{ 68 | $(DATE)_prf/PASS: $(DATE).sby $(RTL)/$(DATE).v 69 | sby -f $(DATE).sby prf 70 | ## }}} 71 | 72 | # $(RTCCK) : $(RTCCK).check 73 | ## {{{ 74 | # The RTCCK check is now deprecated, and no longer set here. 75 | # $(RTCCK).check: $(RTCCK).smt2 76 | # @rm -f $(RTCCK).check 77 | # $(SMTBMC) $(BMCARGS) -t 40 --dump-vcd $(RTCCK).vcd $(RTCCK).smt2 78 | # $(SMTBMC) $(INDARGS) -t 38 --dump-vcd $(RTCCK).vcd $(RTCCK).smt2 79 | # touch $@ 80 | ## }}} 81 | 82 | $(RTCLT) : $(RTCLT)_prf/PASS 83 | ## {{{ 84 | $(RTCLT)_prf/PASS: $(RTCLT).sby $(RTL)/$(RTCLT).v 85 | sby -f $(RTCLT).sby prf 86 | ## }}} 87 | 88 | $(RTCGPS) : $(RTCGPS)_prf/PASS 89 | ## {{{ 90 | $(RTCGPS)_prf/PASS: $(RTCGPS).sby $(RTL)/$(RTCGPS).v 91 | sby -f $(RTCGPS).sby prf 92 | ## }}} 93 | 94 | $(TIMER) : $(TIMER)_prf 95 | ## {{{ 96 | $(TIMER)_prf: $(TIMER).sby $(RTL)/$(TIMER).v 97 | sby -f $(TIMER).sby prf 98 | ## }}} 99 | 100 | $(SWATCH) : $(SWATCH)_prf/PASS 101 | ## {{{ 102 | $(SWATCH)_prf/PASS: $(SWATCH).sby $(RTL)/$(SWATCH).v 103 | sby -f $(SWATCH).sby prf 104 | ## }}} 105 | 106 | $(ALARM) : $(ALARM)_checkinp/PASS $(ALARM)_validated/PASS 107 | ## {{{ 108 | $(ALARM)_checkinp/PASS: $(RTL)/$(ALARM).v $(ALARM).sby 109 | sby -f $(ALARM).sby checkinp 110 | $(ALARM)_validated/PASS: $(RTL)/$(ALARM).v $(ALARM).sby 111 | sby -f $(ALARM).sby validated 112 | ## }}} 113 | 114 | $(BARE) : $(BARE)_checkinp/PASS $(BARE)_validated/PASS 115 | ## {{{ 116 | $(BARE)_checkinp/PASS: $(RTL)/$(BARE).v $(BARE).sby 117 | sby -f $(BARE).sby checkinp 118 | $(BARE)_validated/PASS: $(RTL)/$(BARE).v $(BARE).sby 119 | sby -f $(BARE).sby validated 120 | ## }}} 121 | 122 | .PHONY: clean 123 | ## {{{ 124 | clean: 125 | rm -rf $(DATE)_*/ 126 | rm -rf $(RTCLT)_*/ 127 | rm -rf $(RTCGPS)_*/ 128 | rm -rf $(TIMER)_*/ 129 | rm -rf $(SWATCH)_*/ 130 | rm -rf $(ALARM)_*/ 131 | rm -rf $(BARE)_*/ 132 | ## rm -f $(RTCCK).smt2 $(RTCCK)*.vcd $(RTCCK).yslog 133 | ## }}} 134 | -------------------------------------------------------------------------------- /bench/formal/rtcalarm.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | checkinp 3 | validated 4 | 5 | [options] 6 | mode prove 7 | 8 | [engines] 9 | smtbmc boolector 10 | 11 | [script] 12 | read_verilog -D RTCALARM -formal rtcalarm.v 13 | checkinp: chparam -set OPT_PREVALIDATED_INPUT 0 rtcalarm 14 | validated: chparam -set OPT_PREVALIDATED_INPUT 1 rtcalarm 15 | prep -top rtcalarm 16 | 17 | [files] 18 | ../../rtl/rtcalarm.v 19 | -------------------------------------------------------------------------------- /bench/formal/rtcbare.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | checkinp 3 | validated 4 | 5 | [options] 6 | mode prove 7 | 8 | [engines] 9 | smtbmc boolector 10 | 11 | [script] 12 | read -formal -D RTCBARE rtcbare.v 13 | checkinp: chparam -set OPT_PREVALIDATED_INPUT 0 rtcbare 14 | validated: chparam -set OPT_PREVALIDATED_INPUT 1 rtcbare 15 | prep -top rtcbare 16 | 17 | [files] 18 | ../../rtl/rtcbare.v 19 | -------------------------------------------------------------------------------- /bench/formal/rtcclock.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D RTCLIGHT -formal ../../rtl/rtcclock.v 2 | read_verilog -D RTCLIGHT -formal ../../rtl/hexmap.v 3 | read_verilog -D RTCLIGHT -formal ../../rtl/rtcbare.v 4 | read_verilog -D RTCLIGHT -formal ../../rtl/rtcalarm.v 5 | read_verilog -D RTCLIGHT -formal ../../rtl/rtctimer.v 6 | read_verilog -D RTCLIGHT -formal ../../rtl/rtcstopwatch.v 7 | prep -top rtcclock -nordff 8 | write_smt2 -wires rtcclock.smt2 9 | -------------------------------------------------------------------------------- /bench/formal/rtcdate.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | mode prove 6 | 7 | [engines] 8 | smtbmc 9 | 10 | [script] 11 | read_verilog -D RTCDATE -formal rtcdate.v 12 | proc -norom 13 | prep -top rtcdate 14 | 15 | [files] 16 | ../../rtl/rtcdate.v 17 | 18 | -------------------------------------------------------------------------------- /bench/formal/rtcgps.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | mode prove 6 | 7 | [engines] 8 | smtbmc 9 | 10 | [script] 11 | read_verilog -D RTCGPS -formal rtcgps.v 12 | read_verilog -D RTCGPS -formal rtcbare.v 13 | read_verilog -D RTCGPS -formal rtcalarm.v 14 | read_verilog -D RTCGPS -formal rtctimer.v 15 | read_verilog -D RTCGPS -formal rtcstopwatch.v 16 | prep -top rtcgps 17 | 18 | [files] 19 | ../../rtl/rtcgps.v 20 | ../../rtl/rtcbare.v 21 | ../../rtl/rtcalarm.v 22 | ../../rtl/rtctimer.v 23 | ../../rtl/rtcstopwatch.v 24 | -------------------------------------------------------------------------------- /bench/formal/rtclight.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | [options] 4 | mode prove 5 | 6 | [engines] 7 | smtbmc 8 | 9 | [script] 10 | read_verilog -D RTCLIGHT -formal rtclight.v 11 | read_verilog -D RTCLIGHT -formal rtcbare.v 12 | read_verilog -D RTCLIGHT -formal rtcalarm.v 13 | read_verilog -D RTCLIGHT -formal rtctimer.v 14 | read_verilog -D RTCLIGHT -formal rtcstopwatch.v 15 | prep -top rtclight 16 | 17 | [files] 18 | ../../rtl/rtclight.v 19 | ../../rtl/rtcbare.v 20 | ../../rtl/rtcalarm.v 21 | ../../rtl/rtctimer.v 22 | ../../rtl/rtcstopwatch.v 23 | -------------------------------------------------------------------------------- /bench/formal/rtcstopwatch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | mode prove 6 | 7 | [engines] 8 | smtbmc boolector 9 | 10 | [script] 11 | read_verilog -D STOPWATCH -formal rtcstopwatch.v 12 | prep -top rtcstopwatch 13 | 14 | [files] 15 | ../../rtl/rtcstopwatch.v 16 | -------------------------------------------------------------------------------- /bench/formal/rtctimer.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | mode prove 6 | 7 | [engines] 8 | smtbmc boolector 9 | 10 | [script] 11 | read_verilog -D RTCTIMER -formal rtctimer.v 12 | prep -top rtctimer 13 | 14 | [files] 15 | ../../rtl/rtctimer.v 16 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | *.out 2 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | all: gpl-3.0.pdf spec.pdf 2 | DSRC := src 3 | 4 | ## GPL 5 | ## {{{ 6 | gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex 7 | latex $(DSRC)/gpl-3.0.tex 8 | latex $(DSRC)/gpl-3.0.tex 9 | dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi 10 | ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf 11 | rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps 12 | ## }}} 13 | 14 | ## SPEC 15 | ## {{{ 16 | spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps 17 | cd $(DSRC)/; latex spec.tex 18 | cd $(DSRC)/; latex spec.tex 19 | dvips -q -z -t letter -P pdf -o spec.ps $(DSRC)/spec.dvi 20 | ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf 21 | rm $(DSRC)/spec.dvi $(DSRC)/spec.log 22 | rm $(DSRC)/spec.aux $(DSRC)/spec.toc 23 | rm $(DSRC)/spec.lot # $(DSRC)/spec.lof 24 | rm spec.ps 25 | ## }}} 26 | -------------------------------------------------------------------------------- /doc/gpl-3.0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/rtcclock/b8db1c36b3ce52046f89ce91b203dafcff86a8ab/doc/gpl-3.0.pdf -------------------------------------------------------------------------------- /doc/spec.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/rtcclock/b8db1c36b3ce52046f89ce91b203dafcff86a8ab/doc/spec.pdf -------------------------------------------------------------------------------- /doc/src/GT.eps: -------------------------------------------------------------------------------- 1 | %!PS-Adobe-3.0 EPSF-3.0 2 | %%BoundingBox: 0 0 504 288 3 | %%Creator: Gisselquist Technology LLC 4 | %%Title: Gisselquist Technology Logo 5 | %%CreationDate: 11 Mar 2014 6 | %%EndComments 7 | %%BeginProlog 8 | /black { 0 setgray } def 9 | /white { 1 setgray } def 10 | /height { 288 } def 11 | /lw { height 8 div } def 12 | %%EndProlog 13 | % %%Page: 1 14 | 15 | false { % A bounding box 16 | 0 setlinewidth 17 | newpath 18 | 0 0 moveto 19 | 0 height lineto 20 | 1.625 height mul lw add 0 rlineto 21 | 0 height neg rlineto 22 | closepath stroke 23 | } if 24 | 25 | true { % The "G" 26 | newpath 27 | height 2 div 1.25 mul height moveto 28 | height 2 div height 4 div sub height lineto 29 | 0 height 3 4 div mul lineto 30 | 0 height 4 div lineto 31 | height 4 div 0 lineto 32 | height 3 4 div mul 0 lineto 33 | height height 4 div lineto 34 | height height 2 div lineto 35 | % 36 | height lw sub height 2 div lineto 37 | height lw sub height 4 div lw 2 div add lineto 38 | height 3 4 div mul lw 2 div sub lw lineto 39 | height 4 div lw 2 div add lw lineto 40 | lw height 4 div lw 2 div add lineto 41 | lw height 3 4 div mul lw 2 div sub lineto 42 | height 4 div lw 2 div add height lw sub lineto 43 | height 2 div 1.25 mul height lw sub lineto 44 | closepath fill 45 | newpath 46 | height 2 div height 2 div moveto 47 | height 2 div 0 rlineto 48 | 0 height 2 div neg rlineto 49 | lw neg 0 rlineto 50 | 0 height 2 div lw sub rlineto 51 | height 2 div height 2 div lw sub lineto 52 | closepath fill 53 | } if 54 | 55 | height 2 div 1.25 mul lw add 0 translate 56 | false { 57 | newpath 58 | 0 height moveto 59 | height 0 rlineto 60 | 0 lw neg rlineto 61 | height lw sub 2 div neg 0 rlineto 62 | 0 height lw sub neg rlineto 63 | lw neg 0 rlineto 64 | 0 height lw sub rlineto 65 | height lw sub 2 div neg 0 rlineto 66 | 0 lw rlineto 67 | closepath fill 68 | } if 69 | 70 | true { % The "T" of "GT". 71 | newpath 72 | 0 height moveto 73 | height lw add 2 div 0 rlineto 74 | 0 height neg rlineto 75 | lw neg 0 rlineto 76 | 0 height lw sub rlineto 77 | height lw sub 2 div neg 0 rlineto 78 | closepath fill 79 | 80 | % The right half of the top of the "T" 81 | newpath 82 | % (height + lw)/2 + lw 83 | height lw add 2 div lw add height moveto 84 | % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw 85 | height 3 lw mul sub 2 div 0 rlineto 86 | 0 lw neg rlineto 87 | height 3 lw mul sub 2 div neg 0 rlineto 88 | closepath fill 89 | } if 90 | 91 | 92 | grestore 93 | showpage 94 | %%EOF 95 | -------------------------------------------------------------------------------- /doc/src/gpl-3.0.tex: -------------------------------------------------------------------------------- 1 | \documentclass[11pt]{article} 2 | 3 | \title{GNU GENERAL PUBLIC LICENSE} 4 | \date{Version 3, 29 June 2007} 5 | 6 | \begin{document} 7 | \maketitle 8 | 9 | \begin{center} 10 | {\parindent 0in 11 | 12 | Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/} 13 | 14 | \bigskip 15 | Everyone is permitted to copy and distribute verbatim copies of this 16 | 17 | license document, but changing it is not allowed.} 18 | 19 | \end{center} 20 | 21 | \renewcommand{\abstractname}{Preamble} 22 | \begin{abstract} 23 | The GNU General Public License is a free, copyleft license for 24 | software and other kinds of works. 25 | 26 | The licenses for most software and other practical works are designed 27 | to take away your freedom to share and change the works. By contrast, 28 | the GNU General Public License is intended to guarantee your freedom to 29 | share and change all versions of a program--to make sure it remains free 30 | software for all its users. We, the Free Software Foundation, use the 31 | GNU General Public License for most of our software; it applies also to 32 | any other work released this way by its authors. You can apply it to 33 | your programs, too. 34 | 35 | When we speak of free software, we are referring to freedom, not 36 | price. Our General Public Licenses are designed to make sure that you 37 | have the freedom to distribute copies of free software (and charge for 38 | them if you wish), that you receive source code or can get it if you 39 | want it, that you can change the software or use pieces of it in new 40 | free programs, and that you know you can do these things. 41 | 42 | To protect your rights, we need to prevent others from denying you 43 | these rights or asking you to surrender the rights. Therefore, you have 44 | certain responsibilities if you distribute copies of the software, or if 45 | you modify it: responsibilities to respect the freedom of others. 46 | 47 | For example, if you distribute copies of such a program, whether 48 | gratis or for a fee, you must pass on to the recipients the same 49 | freedoms that you received. You must make sure that they, too, receive 50 | or can get the source code. And you must show them these terms so they 51 | know their rights. 52 | 53 | Developers that use the GNU GPL protect your rights with two steps: 54 | (1) assert copyright on the software, and (2) offer you this License 55 | giving you legal permission to copy, distribute and/or modify it. 56 | 57 | For the developers' and authors' protection, the GPL clearly explains 58 | that there is no warranty for this free software. For both users' and 59 | authors' sake, the GPL requires that modified versions be marked as 60 | changed, so that their problems will not be attributed erroneously to 61 | authors of previous versions. 62 | 63 | Some devices are designed to deny users access to install or run 64 | modified versions of the software inside them, although the manufacturer 65 | can do so. This is fundamentally incompatible with the aim of 66 | protecting users' freedom to change the software. The systematic 67 | pattern of such abuse occurs in the area of products for individuals to 68 | use, which is precisely where it is most unacceptable. Therefore, we 69 | have designed this version of the GPL to prohibit the practice for those 70 | products. If such problems arise substantially in other domains, we 71 | stand ready to extend this provision to those domains in future versions 72 | of the GPL, as needed to protect the freedom of users. 73 | 74 | Finally, every program is threatened constantly by software patents. 75 | States should not allow patents to restrict development and use of 76 | software on general-purpose computers, but in those that do, we wish to 77 | avoid the special danger that patents applied to a free program could 78 | make it effectively proprietary. To prevent this, the GPL assures that 79 | patents cannot be used to render the program non-free. 80 | 81 | The precise terms and conditions for copying, distribution and 82 | modification follow. 83 | \end{abstract} 84 | 85 | \begin{center} 86 | {\Large \sc Terms and Conditions} 87 | \end{center} 88 | 89 | 90 | \begin{enumerate} 91 | 92 | \addtocounter{enumi}{-1} 93 | 94 | \item Definitions. 95 | 96 | ``This License'' refers to version 3 of the GNU General Public License. 97 | 98 | ``Copyright'' also means copyright-like laws that apply to other kinds of 99 | works, such as semiconductor masks. 100 | 101 | ``The Program'' refers to any copyrightable work licensed under this 102 | License. Each licensee is addressed as ``you''. ``Licensees'' and 103 | ``recipients'' may be individuals or organizations. 104 | 105 | To ``modify'' a work means to copy from or adapt all or part of the work 106 | in a fashion requiring copyright permission, other than the making of an 107 | exact copy. The resulting work is called a ``modified version'' of the 108 | earlier work or a work ``based on'' the earlier work. 109 | 110 | A ``covered work'' means either the unmodified Program or a work based 111 | on the Program. 112 | 113 | To ``propagate'' a work means to do anything with it that, without 114 | permission, would make you directly or secondarily liable for 115 | infringement under applicable copyright law, except executing it on a 116 | computer or modifying a private copy. Propagation includes copying, 117 | distribution (with or without modification), making available to the 118 | public, and in some countries other activities as well. 119 | 120 | To ``convey'' a work means any kind of propagation that enables other 121 | parties to make or receive copies. Mere interaction with a user through 122 | a computer network, with no transfer of a copy, is not conveying. 123 | 124 | An interactive user interface displays ``Appropriate Legal Notices'' 125 | to the extent that it includes a convenient and prominently visible 126 | feature that (1) displays an appropriate copyright notice, and (2) 127 | tells the user that there is no warranty for the work (except to the 128 | extent that warranties are provided), that licensees may convey the 129 | work under this License, and how to view a copy of this License. If 130 | the interface presents a list of user commands or options, such as a 131 | menu, a prominent item in the list meets this criterion. 132 | 133 | \item Source Code. 134 | 135 | The ``source code'' for a work means the preferred form of the work 136 | for making modifications to it. ``Object code'' means any non-source 137 | form of a work. 138 | 139 | A ``Standard Interface'' means an interface that either is an official 140 | standard defined by a recognized standards body, or, in the case of 141 | interfaces specified for a particular programming language, one that 142 | is widely used among developers working in that language. 143 | 144 | The ``System Libraries'' of an executable work include anything, other 145 | than the work as a whole, that (a) is included in the normal form of 146 | packaging a Major Component, but which is not part of that Major 147 | Component, and (b) serves only to enable use of the work with that 148 | Major Component, or to implement a Standard Interface for which an 149 | implementation is available to the public in source code form. A 150 | ``Major Component'', in this context, means a major essential component 151 | (kernel, window system, and so on) of the specific operating system 152 | (if any) on which the executable work runs, or a compiler used to 153 | produce the work, or an object code interpreter used to run it. 154 | 155 | The ``Corresponding Source'' for a work in object code form means all 156 | the source code needed to generate, install, and (for an executable 157 | work) run the object code and to modify the work, including scripts to 158 | control those activities. However, it does not include the work's 159 | System Libraries, or general-purpose tools or generally available free 160 | programs which are used unmodified in performing those activities but 161 | which are not part of the work. For example, Corresponding Source 162 | includes interface definition files associated with source files for 163 | the work, and the source code for shared libraries and dynamically 164 | linked subprograms that the work is specifically designed to require, 165 | such as by intimate data communication or control flow between those 166 | subprograms and other parts of the work. 167 | 168 | The Corresponding Source need not include anything that users 169 | can regenerate automatically from other parts of the Corresponding 170 | Source. 171 | 172 | The Corresponding Source for a work in source code form is that 173 | same work. 174 | 175 | \item Basic Permissions. 176 | 177 | All rights granted under this License are granted for the term of 178 | copyright on the Program, and are irrevocable provided the stated 179 | conditions are met. This License explicitly affirms your unlimited 180 | permission to run the unmodified Program. The output from running a 181 | covered work is covered by this License only if the output, given its 182 | content, constitutes a covered work. This License acknowledges your 183 | rights of fair use or other equivalent, as provided by copyright law. 184 | 185 | You may make, run and propagate covered works that you do not 186 | convey, without conditions so long as your license otherwise remains 187 | in force. You may convey covered works to others for the sole purpose 188 | of having them make modifications exclusively for you, or provide you 189 | with facilities for running those works, provided that you comply with 190 | the terms of this License in conveying all material for which you do 191 | not control copyright. Those thus making or running the covered works 192 | for you must do so exclusively on your behalf, under your direction 193 | and control, on terms that prohibit them from making any copies of 194 | your copyrighted material outside their relationship with you. 195 | 196 | Conveying under any other circumstances is permitted solely under 197 | the conditions stated below. Sublicensing is not allowed; section 10 198 | makes it unnecessary. 199 | 200 | \item Protecting Users' Legal Rights From Anti-Circumvention Law. 201 | 202 | No covered work shall be deemed part of an effective technological 203 | measure under any applicable law fulfilling obligations under article 204 | 11 of the WIPO copyright treaty adopted on 20 December 1996, or 205 | similar laws prohibiting or restricting circumvention of such 206 | measures. 207 | 208 | When you convey a covered work, you waive any legal power to forbid 209 | circumvention of technological measures to the extent such circumvention 210 | is effected by exercising rights under this License with respect to 211 | the covered work, and you disclaim any intention to limit operation or 212 | modification of the work as a means of enforcing, against the work's 213 | users, your or third parties' legal rights to forbid circumvention of 214 | technological measures. 215 | 216 | \item Conveying Verbatim Copies. 217 | 218 | You may convey verbatim copies of the Program's source code as you 219 | receive it, in any medium, provided that you conspicuously and 220 | appropriately publish on each copy an appropriate copyright notice; 221 | keep intact all notices stating that this License and any 222 | non-permissive terms added in accord with section 7 apply to the code; 223 | keep intact all notices of the absence of any warranty; and give all 224 | recipients a copy of this License along with the Program. 225 | 226 | You may charge any price or no price for each copy that you convey, 227 | and you may offer support or warranty protection for a fee. 228 | 229 | \item Conveying Modified Source Versions. 230 | 231 | You may convey a work based on the Program, or the modifications to 232 | produce it from the Program, in the form of source code under the 233 | terms of section 4, provided that you also meet all of these conditions: 234 | \begin{enumerate} 235 | \item The work must carry prominent notices stating that you modified 236 | it, and giving a relevant date. 237 | 238 | \item The work must carry prominent notices stating that it is 239 | released under this License and any conditions added under section 240 | 7. This requirement modifies the requirement in section 4 to 241 | ``keep intact all notices''. 242 | 243 | \item You must license the entire work, as a whole, under this 244 | License to anyone who comes into possession of a copy. This 245 | License will therefore apply, along with any applicable section 7 246 | additional terms, to the whole of the work, and all its parts, 247 | regardless of how they are packaged. This License gives no 248 | permission to license the work in any other way, but it does not 249 | invalidate such permission if you have separately received it. 250 | 251 | \item If the work has interactive user interfaces, each must display 252 | Appropriate Legal Notices; however, if the Program has interactive 253 | interfaces that do not display Appropriate Legal Notices, your 254 | work need not make them do so. 255 | \end{enumerate} 256 | A compilation of a covered work with other separate and independent 257 | works, which are not by their nature extensions of the covered work, 258 | and which are not combined with it such as to form a larger program, 259 | in or on a volume of a storage or distribution medium, is called an 260 | ``aggregate'' if the compilation and its resulting copyright are not 261 | used to limit the access or legal rights of the compilation's users 262 | beyond what the individual works permit. Inclusion of a covered work 263 | in an aggregate does not cause this License to apply to the other 264 | parts of the aggregate. 265 | 266 | \item Conveying Non-Source Forms. 267 | 268 | You may convey a covered work in object code form under the terms 269 | of sections 4 and 5, provided that you also convey the 270 | machine-readable Corresponding Source under the terms of this License, 271 | in one of these ways: 272 | \begin{enumerate} 273 | \item Convey the object code in, or embodied in, a physical product 274 | (including a physical distribution medium), accompanied by the 275 | Corresponding Source fixed on a durable physical medium 276 | customarily used for software interchange. 277 | 278 | \item Convey the object code in, or embodied in, a physical product 279 | (including a physical distribution medium), accompanied by a 280 | written offer, valid for at least three years and valid for as 281 | long as you offer spare parts or customer support for that product 282 | model, to give anyone who possesses the object code either (1) a 283 | copy of the Corresponding Source for all the software in the 284 | product that is covered by this License, on a durable physical 285 | medium customarily used for software interchange, for a price no 286 | more than your reasonable cost of physically performing this 287 | conveying of source, or (2) access to copy the 288 | Corresponding Source from a network server at no charge. 289 | 290 | \item Convey individual copies of the object code with a copy of the 291 | written offer to provide the Corresponding Source. This 292 | alternative is allowed only occasionally and noncommercially, and 293 | only if you received the object code with such an offer, in accord 294 | with subsection 6b. 295 | 296 | \item Convey the object code by offering access from a designated 297 | place (gratis or for a charge), and offer equivalent access to the 298 | Corresponding Source in the same way through the same place at no 299 | further charge. You need not require recipients to copy the 300 | Corresponding Source along with the object code. If the place to 301 | copy the object code is a network server, the Corresponding Source 302 | may be on a different server (operated by you or a third party) 303 | that supports equivalent copying facilities, provided you maintain 304 | clear directions next to the object code saying where to find the 305 | Corresponding Source. Regardless of what server hosts the 306 | Corresponding Source, you remain obligated to ensure that it is 307 | available for as long as needed to satisfy these requirements. 308 | 309 | \item Convey the object code using peer-to-peer transmission, provided 310 | you inform other peers where the object code and Corresponding 311 | Source of the work are being offered to the general public at no 312 | charge under subsection 6d. 313 | \end{enumerate} 314 | 315 | A separable portion of the object code, whose source code is excluded 316 | from the Corresponding Source as a System Library, need not be 317 | included in conveying the object code work. 318 | 319 | A ``User Product'' is either (1) a ``consumer product'', which means any 320 | tangible personal property which is normally used for personal, family, 321 | or household purposes, or (2) anything designed or sold for incorporation 322 | into a dwelling. In determining whether a product is a consumer product, 323 | doubtful cases shall be resolved in favor of coverage. For a particular 324 | product received by a particular user, ``normally used'' refers to a 325 | typical or common use of that class of product, regardless of the status 326 | of the particular user or of the way in which the particular user 327 | actually uses, or expects or is expected to use, the product. A product 328 | is a consumer product regardless of whether the product has substantial 329 | commercial, industrial or non-consumer uses, unless such uses represent 330 | the only significant mode of use of the product. 331 | 332 | ``Installation Information'' for a User Product means any methods, 333 | procedures, authorization keys, or other information required to install 334 | and execute modified versions of a covered work in that User Product from 335 | a modified version of its Corresponding Source. The information must 336 | suffice to ensure that the continued functioning of the modified object 337 | code is in no case prevented or interfered with solely because 338 | modification has been made. 339 | 340 | If you convey an object code work under this section in, or with, or 341 | specifically for use in, a User Product, and the conveying occurs as 342 | part of a transaction in which the right of possession and use of the 343 | User Product is transferred to the recipient in perpetuity or for a 344 | fixed term (regardless of how the transaction is characterized), the 345 | Corresponding Source conveyed under this section must be accompanied 346 | by the Installation Information. But this requirement does not apply 347 | if neither you nor any third party retains the ability to install 348 | modified object code on the User Product (for example, the work has 349 | been installed in ROM). 350 | 351 | The requirement to provide Installation Information does not include a 352 | requirement to continue to provide support service, warranty, or updates 353 | for a work that has been modified or installed by the recipient, or for 354 | the User Product in which it has been modified or installed. Access to a 355 | network may be denied when the modification itself materially and 356 | adversely affects the operation of the network or violates the rules and 357 | protocols for communication across the network. 358 | 359 | Corresponding Source conveyed, and Installation Information provided, 360 | in accord with this section must be in a format that is publicly 361 | documented (and with an implementation available to the public in 362 | source code form), and must require no special password or key for 363 | unpacking, reading or copying. 364 | 365 | \item Additional Terms. 366 | 367 | ``Additional permissions'' are terms that supplement the terms of this 368 | License by making exceptions from one or more of its conditions. 369 | Additional permissions that are applicable to the entire Program shall 370 | be treated as though they were included in this License, to the extent 371 | that they are valid under applicable law. If additional permissions 372 | apply only to part of the Program, that part may be used separately 373 | under those permissions, but the entire Program remains governed by 374 | this License without regard to the additional permissions. 375 | 376 | When you convey a copy of a covered work, you may at your option 377 | remove any additional permissions from that copy, or from any part of 378 | it. (Additional permissions may be written to require their own 379 | removal in certain cases when you modify the work.) You may place 380 | additional permissions on material, added by you to a covered work, 381 | for which you have or can give appropriate copyright permission. 382 | 383 | Notwithstanding any other provision of this License, for material you 384 | add to a covered work, you may (if authorized by the copyright holders of 385 | that material) supplement the terms of this License with terms: 386 | \begin{enumerate} 387 | \item Disclaiming warranty or limiting liability differently from the 388 | terms of sections 15 and 16 of this License; or 389 | 390 | \item Requiring preservation of specified reasonable legal notices or 391 | author attributions in that material or in the Appropriate Legal 392 | Notices displayed by works containing it; or 393 | 394 | \item Prohibiting misrepresentation of the origin of that material, or 395 | requiring that modified versions of such material be marked in 396 | reasonable ways as different from the original version; or 397 | 398 | \item Limiting the use for publicity purposes of names of licensors or 399 | authors of the material; or 400 | 401 | \item Declining to grant rights under trademark law for use of some 402 | trade names, trademarks, or service marks; or 403 | 404 | \item Requiring indemnification of licensors and authors of that 405 | material by anyone who conveys the material (or modified versions of 406 | it) with contractual assumptions of liability to the recipient, for 407 | any liability that these contractual assumptions directly impose on 408 | those licensors and authors. 409 | \end{enumerate} 410 | 411 | All other non-permissive additional terms are considered ``further 412 | restrictions'' within the meaning of section 10. If the Program as you 413 | received it, or any part of it, contains a notice stating that it is 414 | governed by this License along with a term that is a further 415 | restriction, you may remove that term. If a license document contains 416 | a further restriction but permits relicensing or conveying under this 417 | License, you may add to a covered work material governed by the terms 418 | of that license document, provided that the further restriction does 419 | not survive such relicensing or conveying. 420 | 421 | If you add terms to a covered work in accord with this section, you 422 | must place, in the relevant source files, a statement of the 423 | additional terms that apply to those files, or a notice indicating 424 | where to find the applicable terms. 425 | 426 | Additional terms, permissive or non-permissive, may be stated in the 427 | form of a separately written license, or stated as exceptions; 428 | the above requirements apply either way. 429 | 430 | \item Termination. 431 | 432 | You may not propagate or modify a covered work except as expressly 433 | provided under this License. Any attempt otherwise to propagate or 434 | modify it is void, and will automatically terminate your rights under 435 | this License (including any patent licenses granted under the third 436 | paragraph of section 11). 437 | 438 | However, if you cease all violation of this License, then your 439 | license from a particular copyright holder is reinstated (a) 440 | provisionally, unless and until the copyright holder explicitly and 441 | finally terminates your license, and (b) permanently, if the copyright 442 | holder fails to notify you of the violation by some reasonable means 443 | prior to 60 days after the cessation. 444 | 445 | Moreover, your license from a particular copyright holder is 446 | reinstated permanently if the copyright holder notifies you of the 447 | violation by some reasonable means, this is the first time you have 448 | received notice of violation of this License (for any work) from that 449 | copyright holder, and you cure the violation prior to 30 days after 450 | your receipt of the notice. 451 | 452 | Termination of your rights under this section does not terminate the 453 | licenses of parties who have received copies or rights from you under 454 | this License. If your rights have been terminated and not permanently 455 | reinstated, you do not qualify to receive new licenses for the same 456 | material under section 10. 457 | 458 | \item Acceptance Not Required for Having Copies. 459 | 460 | You are not required to accept this License in order to receive or 461 | run a copy of the Program. Ancillary propagation of a covered work 462 | occurring solely as a consequence of using peer-to-peer transmission 463 | to receive a copy likewise does not require acceptance. However, 464 | nothing other than this License grants you permission to propagate or 465 | modify any covered work. These actions infringe copyright if you do 466 | not accept this License. Therefore, by modifying or propagating a 467 | covered work, you indicate your acceptance of this License to do so. 468 | 469 | \item Automatic Licensing of Downstream Recipients. 470 | 471 | Each time you convey a covered work, the recipient automatically 472 | receives a license from the original licensors, to run, modify and 473 | propagate that work, subject to this License. You are not responsible 474 | for enforcing compliance by third parties with this License. 475 | 476 | An ``entity transaction'' is a transaction transferring control of an 477 | organization, or substantially all assets of one, or subdividing an 478 | organization, or merging organizations. If propagation of a covered 479 | work results from an entity transaction, each party to that 480 | transaction who receives a copy of the work also receives whatever 481 | licenses to the work the party's predecessor in interest had or could 482 | give under the previous paragraph, plus a right to possession of the 483 | Corresponding Source of the work from the predecessor in interest, if 484 | the predecessor has it or can get it with reasonable efforts. 485 | 486 | You may not impose any further restrictions on the exercise of the 487 | rights granted or affirmed under this License. For example, you may 488 | not impose a license fee, royalty, or other charge for exercise of 489 | rights granted under this License, and you may not initiate litigation 490 | (including a cross-claim or counterclaim in a lawsuit) alleging that 491 | any patent claim is infringed by making, using, selling, offering for 492 | sale, or importing the Program or any portion of it. 493 | 494 | \item Patents. 495 | 496 | A ``contributor'' is a copyright holder who authorizes use under this 497 | License of the Program or a work on which the Program is based. The 498 | work thus licensed is called the contributor's ``contributor version''. 499 | 500 | A contributor's ``essential patent claims'' are all patent claims 501 | owned or controlled by the contributor, whether already acquired or 502 | hereafter acquired, that would be infringed by some manner, permitted 503 | by this License, of making, using, or selling its contributor version, 504 | but do not include claims that would be infringed only as a 505 | consequence of further modification of the contributor version. For 506 | purposes of this definition, ``control'' includes the right to grant 507 | patent sublicenses in a manner consistent with the requirements of 508 | this License. 509 | 510 | Each contributor grants you a non-exclusive, worldwide, royalty-free 511 | patent license under the contributor's essential patent claims, to 512 | make, use, sell, offer for sale, import and otherwise run, modify and 513 | propagate the contents of its contributor version. 514 | 515 | In the following three paragraphs, a ``patent license'' is any express 516 | agreement or commitment, however denominated, not to enforce a patent 517 | (such as an express permission to practice a patent or covenant not to 518 | sue for patent infringement). To ``grant'' such a patent license to a 519 | party means to make such an agreement or commitment not to enforce a 520 | patent against the party. 521 | 522 | If you convey a covered work, knowingly relying on a patent license, 523 | and the Corresponding Source of the work is not available for anyone 524 | to copy, free of charge and under the terms of this License, through a 525 | publicly available network server or other readily accessible means, 526 | then you must either (1) cause the Corresponding Source to be so 527 | available, or (2) arrange to deprive yourself of the benefit of the 528 | patent license for this particular work, or (3) arrange, in a manner 529 | consistent with the requirements of this License, to extend the patent 530 | license to downstream recipients. ``Knowingly relying'' means you have 531 | actual knowledge that, but for the patent license, your conveying the 532 | covered work in a country, or your recipient's use of the covered work 533 | in a country, would infringe one or more identifiable patents in that 534 | country that you have reason to believe are valid. 535 | 536 | If, pursuant to or in connection with a single transaction or 537 | arrangement, you convey, or propagate by procuring conveyance of, a 538 | covered work, and grant a patent license to some of the parties 539 | receiving the covered work authorizing them to use, propagate, modify 540 | or convey a specific copy of the covered work, then the patent license 541 | you grant is automatically extended to all recipients of the covered 542 | work and works based on it. 543 | 544 | A patent license is ``discriminatory'' if it does not include within 545 | the scope of its coverage, prohibits the exercise of, or is 546 | conditioned on the non-exercise of one or more of the rights that are 547 | specifically granted under this License. You may not convey a covered 548 | work if you are a party to an arrangement with a third party that is 549 | in the business of distributing software, under which you make payment 550 | to the third party based on the extent of your activity of conveying 551 | the work, and under which the third party grants, to any of the 552 | parties who would receive the covered work from you, a discriminatory 553 | patent license (a) in connection with copies of the covered work 554 | conveyed by you (or copies made from those copies), or (b) primarily 555 | for and in connection with specific products or compilations that 556 | contain the covered work, unless you entered into that arrangement, 557 | or that patent license was granted, prior to 28 March 2007. 558 | 559 | Nothing in this License shall be construed as excluding or limiting 560 | any implied license or other defenses to infringement that may 561 | otherwise be available to you under applicable patent law. 562 | 563 | \item No Surrender of Others' Freedom. 564 | 565 | If conditions are imposed on you (whether by court order, agreement or 566 | otherwise) that contradict the conditions of this License, they do not 567 | excuse you from the conditions of this License. If you cannot convey a 568 | covered work so as to satisfy simultaneously your obligations under this 569 | License and any other pertinent obligations, then as a consequence you may 570 | not convey it at all. For example, if you agree to terms that obligate you 571 | to collect a royalty for further conveying from those to whom you convey 572 | the Program, the only way you could satisfy both those terms and this 573 | License would be to refrain entirely from conveying the Program. 574 | 575 | \item Use with the GNU Affero General Public License. 576 | 577 | Notwithstanding any other provision of this License, you have 578 | permission to link or combine any covered work with a work licensed 579 | under version 3 of the GNU Affero General Public License into a single 580 | combined work, and to convey the resulting work. The terms of this 581 | License will continue to apply to the part which is the covered work, 582 | but the special requirements of the GNU Affero General Public License, 583 | section 13, concerning interaction through a network will apply to the 584 | combination as such. 585 | 586 | \item Revised Versions of this License. 587 | 588 | The Free Software Foundation may publish revised and/or new versions of 589 | the GNU General Public License from time to time. Such new versions will 590 | be similar in spirit to the present version, but may differ in detail to 591 | address new problems or concerns. 592 | 593 | Each version is given a distinguishing version number. If the 594 | Program specifies that a certain numbered version of the GNU General 595 | Public License ``or any later version'' applies to it, you have the 596 | option of following the terms and conditions either of that numbered 597 | version or of any later version published by the Free Software 598 | Foundation. If the Program does not specify a version number of the 599 | GNU General Public License, you may choose any version ever published 600 | by the Free Software Foundation. 601 | 602 | If the Program specifies that a proxy can decide which future 603 | versions of the GNU General Public License can be used, that proxy's 604 | public statement of acceptance of a version permanently authorizes you 605 | to choose that version for the Program. 606 | 607 | Later license versions may give you additional or different 608 | permissions. However, no additional obligations are imposed on any 609 | author or copyright holder as a result of your choosing to follow a 610 | later version. 611 | 612 | \item Disclaimer of Warranty. 613 | 614 | \begin{sloppypar} 615 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 616 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE 617 | COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' 618 | WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, 619 | INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 620 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE 621 | RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. 622 | SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 623 | NECESSARY SERVICING, REPAIR OR CORRECTION. 624 | \end{sloppypar} 625 | 626 | \item Limitation of Liability. 627 | 628 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN 629 | WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES 630 | AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 631 | DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 632 | DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM 633 | (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 634 | INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE 635 | OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH 636 | HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 637 | DAMAGES. 638 | 639 | \item Interpretation of Sections 15 and 16. 640 | 641 | If the disclaimer of warranty and limitation of liability provided 642 | above cannot be given local legal effect according to their terms, 643 | reviewing courts shall apply local law that most closely approximates 644 | an absolute waiver of all civil liability in connection with the 645 | Program, unless a warranty or assumption of liability accompanies a 646 | copy of the Program in return for a fee. 647 | 648 | \begin{center} 649 | {\Large\sc End of Terms and Conditions} 650 | 651 | \bigskip 652 | How to Apply These Terms to Your New Programs 653 | \end{center} 654 | 655 | If you develop a new program, and you want it to be of the greatest 656 | possible use to the public, the best way to achieve this is to make it 657 | free software which everyone can redistribute and change under these terms. 658 | 659 | To do so, attach the following notices to the program. It is safest 660 | to attach them to the start of each source file to most effectively 661 | state the exclusion of warranty; and each file should have at least 662 | the ``copyright'' line and a pointer to where the full notice is found. 663 | 664 | {\footnotesize 665 | \begin{verbatim} 666 | 667 | 668 | Copyright (C) 669 | 670 | This program is free software: you can redistribute it and/or modify 671 | it under the terms of the GNU General Public License as published by 672 | the Free Software Foundation, either version 3 of the License, or 673 | (at your option) any later version. 674 | 675 | This program is distributed in the hope that it will be useful, 676 | but WITHOUT ANY WARRANTY; without even the implied warranty of 677 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 678 | GNU General Public License for more details. 679 | 680 | You should have received a copy of the GNU General Public License 681 | along with this program. If not, see . 682 | \end{verbatim} 683 | } 684 | 685 | Also add information on how to contact you by electronic and paper mail. 686 | 687 | If the program does terminal interaction, make it output a short 688 | notice like this when it starts in an interactive mode: 689 | 690 | {\footnotesize 691 | \begin{verbatim} 692 | Copyright (C) 693 | 694 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 695 | This is free software, and you are welcome to redistribute it 696 | under certain conditions; type `show c' for details. 697 | \end{verbatim} 698 | } 699 | 700 | The hypothetical commands {\tt show w} and {\tt show c} should show 701 | the appropriate 702 | parts of the General Public License. Of course, your program's commands 703 | might be different; for a GUI interface, you would use an ``about box''. 704 | 705 | You should also get your employer (if you work as a programmer) or 706 | school, if any, to sign a ``copyright disclaimer'' for the program, if 707 | necessary. For more information on this, and how to apply and follow 708 | the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. 709 | 710 | The GNU General Public License does not permit incorporating your 711 | program into proprietary programs. If your program is a subroutine 712 | library, you may consider it more useful to permit linking proprietary 713 | applications with the library. If this is what you want to do, use 714 | the GNU Lesser General Public License instead of this License. But 715 | first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. 716 | 717 | \end{enumerate} 718 | 719 | \end{document} 720 | -------------------------------------------------------------------------------- /doc/src/gqtekspec.cls: -------------------------------------------------------------------------------- 1 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ 2 | % 3 | % Copyright (C) 2015-2024, Gisselquist Technology, LLC 4 | % 5 | % This template is free software: you can redistribute it and/or modify it 6 | % under the terms of the GNU General Public License as published by the 7 | % Free Software Foundation, either version 3 of the License, or (at your 8 | % option) any later version. 9 | % 10 | % This template is distributed in the hope that it will be useful, but WITHOUT 11 | % ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 12 | % FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 | % for more details. 14 | % 15 | % You should have received a copy of the GNU General Public License along 16 | % with this program. If not, see for a copy. 17 | % 18 | % License: GPL, v3, as defined and found on www.gnu.org, 19 | % http://www.gnu.org/licenses/gpl.html 20 | % 21 | % 22 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 23 | % \NeedsTeXFormat{LaTeX2e}[1995/12/01] 24 | \ProvidesClass{gqtekspec}[2024/01/16 v0.1 -- Gisselquist Technology Specification] 25 | \typeout{by Dan Gisselquist} 26 | \LoadClassWithOptions{report} 27 | \usepackage{datetime} 28 | \usepackage{graphicx} 29 | \usepackage[dvips]{pstricks} 30 | \usepackage{hhline} 31 | \usepackage{colortbl} 32 | \definecolor{webgreen}{rgb}{0,0.5,0} 33 | \usepackage[dvips,colorlinks=true,linkcolor=webgreen]{hyperref} 34 | \newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}} 35 | \setlength{\hoffset}{0.25in} 36 | \setlength{\voffset}{-0.5in} 37 | \setlength{\marginparwidth}{0in} 38 | \setlength{\marginparsep}{0in} 39 | \setlength{\textwidth}{6in} 40 | \setlength{\oddsidemargin}{0in} 41 | 42 | % ************************************** 43 | % * APPENDIX * 44 | % ************************************** 45 | % 46 | \newcommand\appfl@g{\appendixname} %used to test \@chapapp 47 | % 48 | % \renewcommand\appendix{\par\clearpage 49 | % \setcounter{chapter}{0}% 50 | % \setcounter{section}{0}% 51 | % \renewcommand\@chapapp{\appendixname}% 52 | % \renewcommand\thechapter{\Alph{chapter}} 53 | % \if@nosectnum\else 54 | % \renewcommand\thesection{\Alph{chapter}.\arabic{section}} 55 | % \fi 56 | % } 57 | 58 | 59 | % FIGURE 60 | % redefine the @caption command to put a period after the figure or 61 | % table number in the lof and lot tables 62 | \long\def\@caption#1[#2]#3{\par\addcontentsline{\csname 63 | ext@#1\endcsname}{#1}{\protect\numberline{\csname 64 | the#1\endcsname.}{\ignorespaces #2}}\begingroup 65 | \@parboxrestore 66 | \normalsize 67 | \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par 68 | \endgroup} 69 | 70 | % **************************************** 71 | % * TABLE OF CONTENTS, ETC. * 72 | % **************************************** 73 | 74 | \renewcommand\contentsname{Contents} 75 | \renewcommand\listfigurename{Figures} 76 | \renewcommand\listtablename{Tables} 77 | 78 | \newif\if@toc \@tocfalse 79 | \renewcommand\tableofcontents{% 80 | \begingroup% temporarily set if@toc so that \@schapter will not 81 | % put Table of Contents in the table of contents. 82 | \@toctrue 83 | \chapter*{\contentsname} 84 | \endgroup 85 | \thispagestyle{gqtekspecplain} 86 | 87 | \baselineskip=10pt plus .5pt minus .5pt 88 | 89 | {\raggedleft Page \par\vskip-\parskip} 90 | \@starttoc{toc}% 91 | \baselineskip=\normalbaselineskip 92 | } 93 | 94 | \def\l@appendix{\pagebreak[3] 95 | \vskip 1.0em plus 1pt % space above appendix line 96 | \@dottedtocline{0}{0em}{8em}} 97 | 98 | \def\l@chapter{\pagebreak[3] 99 | \vskip 1.0em plus 1pt % space above appendix line 100 | \@dottedtocline{0}{0em}{4em}} 101 | 102 | % \if@nosectnum\else 103 | % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}} 104 | % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}} 105 | % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}} 106 | % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}} 107 | % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}} 108 | % \fi 109 | 110 | % LIST OF FIGURES 111 | % 112 | \def\listoffigures{% 113 | \begingroup 114 | \chapter*{\listfigurename}% 115 | \endgroup 116 | \thispagestyle{gqtekspecplain}% 117 | 118 | \baselineskip=10pt plus .5pt minus .5pt% 119 | 120 | {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}% 121 | 122 | \rule[2mm]{\textwidth}{0.5mm}\par 123 | 124 | \@starttoc{lof}% 125 | \baselineskip=\normalbaselineskip}% 126 | 127 | \def\l@figure{\@dottedtocline{1}{1em}{4.0em}} 128 | 129 | % LIST OF TABLES 130 | % 131 | \def\listoftables{% 132 | \begingroup 133 | \chapter*{\listtablename}% 134 | \endgroup 135 | \thispagestyle{gqtekspecplain}% 136 | \baselineskip=10pt plus .5pt minus .5pt% 137 | {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}% 138 | 139 | % Added line underneath headings, 20 Jun 01, Capt Todd Hale. 140 | \rule[2mm]{\textwidth}{0.5mm}\par 141 | 142 | \@starttoc{lot}% 143 | \baselineskip=\normalbaselineskip}% 144 | 145 | \let\l@table\l@figure 146 | 147 | % **************************************** 148 | % * PAGE STYLES * 149 | % **************************************** 150 | % 151 | \def\ps@gqtekspectoc{% 152 | \let\@mkboth\@gobbletwo 153 | \def \@oddhead{} 154 | \def \@oddfoot{\rm 155 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} 156 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 157 | \def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo 158 | \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}} 159 | \def \@oddfoot{\rm 160 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} 161 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 162 | 163 | \def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo 164 | \def \@oddhead{} 165 | \def \@oddfoot{\rm 166 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} 167 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 168 | \def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo 169 | \def \@oddhead{\rm 170 | \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} % 171 | \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} 172 | 173 | \def \@oddfoot{\rm 174 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} 175 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 176 | 177 | \def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo 178 | \def \@oddhead{} 179 | \def \@oddfoot{\rm 180 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} 181 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 182 | \def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo 183 | \def \@oddhead{\rm 184 | \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} % 185 | \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} 186 | 187 | \def \@oddfoot{\rm 188 | \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} 189 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 190 | 191 | \def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo 192 | \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}} 193 | \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}} 194 | \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} 195 | 196 | % \def\author#1{\def\auth@r{#1}} 197 | % \def\title#1{\def\ti@tle{#1}} 198 | 199 | \def\logo{\begin{pspicture}(0,0)(5.67in,0.75in) 200 | \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}} 201 | \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}} 202 | \end{pspicture}} 203 | % TITLEPAGE 204 | % 205 | \def\titlepage{\setcounter{page}{1} 206 | \typeout{^^JTitle Page.} 207 | \thispagestyle{empty} 208 | \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill} 209 | \vskip 2\baselineskip 210 | \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus 211 | \vskip 2\baselineskip 212 | \vspace*{10pt}\vfil 213 | \begin{minipage}{\textwidth}\raggedleft 214 | \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi 215 | \vspace*{15pt} 216 | {\Huge\bfseries\MakeUppercase\@title} \\ 217 | \vskip 10\baselineskip 218 | \Large \@author \\ 219 | \ifemail{\Large \@email}\\\fi 220 | \vskip 6\baselineskip 221 | \Large \usdate\@date \\ 222 | \end{minipage} 223 | % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle 224 | \vspace*{30pt} 225 | \vfil 226 | \newpage\baselineskip=\normalbaselineskip} 227 | 228 | \newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}% 229 | {\vfill\newpage} 230 | % **************************************** 231 | % * CHAPTER DEFINITIONS * 232 | % **************************************** 233 | % 234 | \renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi 235 | \thispagestyle{gqtekspecplain}% 236 | \global\@topnum\z@ 237 | \@afterindentfalse 238 | \secdef\@chapter\@schapter} 239 | \renewcommand\@makechapterhead[1]{% 240 | \hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@ 241 | \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@ 242 | \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@ 243 | \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% 244 | \par\nobreak\vskip 40\p@} 245 | \renewcommand\@makeschapterhead[1]{% 246 | \hbox to \textwidth{\hfill{\Huge\bfseries #1}}% 247 | \par\nobreak\vskip 40\p@} 248 | % **************************************** 249 | % * INITIALIZATION * 250 | % **************************************** 251 | % 252 | % Default initializations 253 | 254 | \ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos. 255 | \onecolumn % Single-column. 256 | \pagenumbering{roman} % the first chapter will change pagenumbering 257 | % to arabic 258 | \setcounter{page}{1} % in case a titlepage is not requested 259 | % otherwise titlepage sets page to 1 since the 260 | % flyleaf is not counted as a page 261 | \widowpenalty 10000 % completely discourage widow lines 262 | \clubpenalty 10000 % completely discourage club (orphan) lines 263 | \raggedbottom % don't force alignment of bottom of pages 264 | 265 | \date{\today} 266 | \newif\ifproject\projectfalse 267 | \def\project#1{\projecttrue\gdef\@project{#1}} 268 | \def\@project{} 269 | \newif\ifemail\emailfalse 270 | \def\email#1{\emailtrue\gdef\@email{#1}} 271 | \def\@email{} 272 | \def\revision#1{\gdef\r@vision{#1}} 273 | \def\r@vision{} 274 | \def\at{\makeatletter @\makeatother} 275 | \newdateformat{theyear}{\THEYEAR} 276 | \newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}% 277 | \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries Revision History}}\vskip 10\p@\noindent% 278 | \begin{tabular}{|p{0.5in}|p{1in}|p{1in}|p{2.875in}|}\hline 279 | \rowcolor[gray]{0.8} Rev. & Date & Author & Description\\\hline\hline} 280 | {\end{tabular}\clearpage} 281 | \newenvironment{clocklist}{\begin{tabular}{|p{0.75in}|p{0.5in}|l|l|p{2.875in}|}\hline 282 | \rowcolor[gray]{0.85} Name & Source & \multicolumn{2}{l|}{Rates (MHz)} & Description \\\hhline{~|~|-|-|~}% 283 | \rowcolor[gray]{0.85} & & Max & Min & \\\hline\hline}% 284 | {\end{tabular}} 285 | \newenvironment{reglist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.5in}|p{0.5in}|p{2.875in}|}\hline 286 | \rowcolor[gray]{0.85} Name & Address & Width & Access & Description \\\hline\hline}% 287 | {\end{tabular}} 288 | \newenvironment{bitlist}{\begin{tabular}{|p{0.5in}|p{0.5in}|p{3.875in}|}\hline 289 | \rowcolor[gray]{0.85} Bit \# & Access & Description \\\hline\hline}% 290 | {\end{tabular}} 291 | \newenvironment{portlist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.75in}|p{3.375in}|}\hline 292 | \rowcolor[gray]{0.85} Port & Width & Direction & Description \\\hline\hline}% 293 | {\end{tabular}} 294 | \newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline 295 | \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}% 296 | {\end{tabular}} 297 | \newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}} 298 | \endinput 299 | -------------------------------------------------------------------------------- /doc/src/spec.tex: -------------------------------------------------------------------------------- 1 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2 | %% 3 | %% Filename: spec.tex 4 | %% {{{ 5 | %% Project: A Wishbone Controlled Real-Time clock Core 6 | %% 7 | %% Purpose: This LaTeX file contains all of the documentation/description 8 | %% currently provided with this FPGA Real-time Clock Core. 9 | %% It's not nearly as interesting as the PDF file it creates, so I'd 10 | %% recommend reading that before diving into this file. You should be 11 | %% able to find the PDF file in the SVN distribution together with this 12 | %% PDF file and a copy of the GPL-3.0 license this file is distributed 13 | %% under. If not, just type 'make' in the doc directory and it (should) 14 | %% build without a problem. 15 | %% 16 | %% Creator: Dan Gisselquist 17 | %% Gisselquist Technology, LLC 18 | %% 19 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 20 | %% }}} 21 | %% Copyright (C) 2015-2024, Gisselquist Technology, LLC 22 | %% {{{ 23 | %% This program is free software (firmware): you can redistribute it and/or 24 | %% modify it under the terms of the GNU General Public License as published 25 | %% by the Free Software Foundation, either version 3 of the License, or (at 26 | %% your option) any later version. 27 | %% 28 | %% This program is distributed in the hope that it will be useful, but WITHOUT 29 | %% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 30 | %% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 31 | %% for more details. 32 | %% 33 | %% You should have received a copy of the GNU General Public License along 34 | %% with this program. (It's in the $(ROOT)/doc directory, run make with no 35 | %% target there if the PDF file isn't present.) If not, see 36 | %% for a copy. 37 | %% }}} 38 | %% License: GPL, v3, as defined and found on www.gnu.org, 39 | %% {{{ 40 | %% http://www.gnu.org/licenses/gpl.html 41 | %% 42 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 43 | %% }}} 44 | \documentclass{gqtekspec} 45 | \project{Real-Time Clock} 46 | \title{Specification} 47 | \author{Dan Gisselquist, Ph.D.} 48 | \email{dgisselq (at) opencores.org} 49 | \revision{Rev.~0.1} 50 | \begin{document} 51 | \pagestyle{gqtekspecplain} 52 | \titlepage 53 | \begin{license} 54 | Copyright (C) \theyear\today, Gisselquist Technology, LLC 55 | 56 | This project is free software (firmware): you can redistribute it and/or 57 | modify it under the terms of the GNU General Public License as published 58 | by the Free Software Foundation, either version 3 of the License, or (at 59 | your option) any later version. 60 | 61 | This program is distributed in the hope that it will be useful, but WITHOUT 62 | ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 63 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 64 | for more details. 65 | 66 | You should have received a copy of the GNU General Public License along 67 | with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a 68 | copy. 69 | \end{license} 70 | \begin{revisionhistory} 71 | 0.3 & 11/07/2015 & Gisselquist & RTC--Light, and RTC--GPS added\\\hline 72 | 0.2 & 7/11/2015 & Gisselquist & Date interface added\\\hline 73 | 0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline 74 | \end{revisionhistory} 75 | % Revision History 76 | % Table of Contents, named Contents 77 | \tableofcontents 78 | % \listoffigures 79 | \listoftables 80 | \begin{preface} 81 | Every FPGA project needs to start with a very simple core. Then, working 82 | from simplicity, more and more complex cores can be built until an eventual 83 | application comes from all the tiny details. 84 | 85 | This real time clock began with one such simple core. All of the pieces to 86 | this clock are simple. Nothing is inherently complex. However, placing this 87 | clock into a larger FPGA structure requires a Wishbone bus, and being able 88 | to command and control an FPGA over a wishbone bus is an achievement in 89 | itself. Further, the clock produces seven segment display output values 90 | and LED output values. These are also simple outputs, but still take a lot 91 | of work to complete. Finally, this clock will strobe an interrupt line. 92 | Reading and processing that interrupt line requires a whole 'nuther bit of 93 | logic and the ability to capture, recognize, and respond to interrupts. 94 | Hence, once you get a simple clock working, you have a lot working. 95 | \end{preface} 96 | 97 | \chapter{Introduction} 98 | \pagenumbering{arabic} 99 | \setcounter{page}{1} 100 | 101 | This Real--Time Clock implements a twenty four hour clock, count-down timer, 102 | stopwatch and alarm. It is designed to be configurable to adjust to whatever 103 | clock speed the underlying architecture is running on, so with only minor 104 | changes should run on any fundamental clock rate from about 66~kHz on up to 105 | 250~TeraHertz with varying levels of accuracy along the way. 106 | 107 | Distributed with this clock is a similar Real--Time Date module. This 108 | second module can track the day, month, and year while properly accounting 109 | for varying days in each month and leap years, when they happen. Also 110 | distributed with the clock are a light version of the clock, offering no 111 | LED nor seven segment display capability, and a GPS version, with an 112 | interface allowing it to be synchronized to a GPS module. 113 | 114 | Together, the clock and date module offer a fairly full feature set of 115 | capability: date, time, alarms, a countdown timer and a stopwatch, all 116 | features which are available from the wishbone bus. 117 | 118 | Other interfaces exist as well. 119 | 120 | Should you wish to investigate your clock's stability or try to guarantee 121 | its fine precision accuracy, it is possible to provide a time hack pulse to 122 | the clock and subsequently read what all of the internal registers were set 123 | to at that time. 124 | 125 | When either the count--down timer reaches zero or the clock reaches the alarm 126 | time (if set), the clock module will produce an impulse which can be used as 127 | an interrupt trigger. 128 | 129 | This clock will also provide outputs sufficient to drive an external seven 130 | segment display driver and 16 LED's. 131 | 132 | Future enhancements may allow for button control and fine precision clock 133 | adjustment. 134 | 135 | The layout of this specification follows the format set by OpenCores. 136 | This introduction is the first chapter. Following this introduction is 137 | a short chapter describing how this clock is implemented, 138 | Chapt.~\ref{chap:arch}. Following this description, the Chapt.~\ref{chap:ops} 139 | gives a brief overview of how to operate the clock. Most of the details, 140 | however, are in the registers and their definitions. These you can find in 141 | Chapt.~\ref{chap:regs}. As for the wishbone, the wishbone spec requires a 142 | wishbone datasheet which you can find in Chapt.~\ref{chap:wishbone}. 143 | That leaves the final pertinent information necessary for implementing this 144 | core in Chapt.~\ref{chap:ioports}, the definitions and meanings of the 145 | various I/O ports. 146 | 147 | As always, write me if you have any questions or problems. 148 | 149 | \chapter{Architecture}\label{chap:arch} 150 | 151 | Central to this real time clock architecture is a 48~bit sub--second register. 152 | This register is incremented every clock by a user defined 32~bit value, 153 | {\tt CKSPEED}. When the register turns over at the end of each second, a 154 | second has taken place and all of the various clock (and date) registers are 155 | adjusted. 156 | 157 | Well, not quite but almost. The 48~bit register is actually split into a 158 | lower 40~bit register that is common to all clock components, as well as 159 | separate eight bit upper registers for the clock, timer, and stopwatch. In 160 | this fashion, these separate components can have different definitions for 161 | when seconds begin and end, and with sufficient precision to satisfy most 162 | applications. 163 | 164 | The next thing to note about this architecture is the format of the various 165 | clock registers: Binary Coded Decimal, or BCD. Hence an {\tt 8'h59} refers 166 | to a value of 59, rather than 89. In this fashion, setting the time to 167 | {\tt 24'h231520} will set it to 23~hours, 15~minutes, and 20~seconds. The 168 | only exception to this BCD format are the subseconds fields found in the 169 | stopwatch and time hack registers. Seconds and above are all encoded as BCD. 170 | 171 | \chapter{Operation}\label{chap:ops} 172 | 173 | \section{Time} 174 | To set the time, simply write to the clock register the current value of the 175 | time. If the seconds hand is written as zero, subsecond time will be cleared 176 | as well. The new clock value takes place one clock period after the value 177 | is written to the bus. 178 | 179 | To set only some parts of the time and not others, such as the minutes but 180 | not seconds or hours, write all '1's to the seconds and hours. In this way, 181 | writing a {\tt 24'h3f17ff} will set the minutes to 17, but not affect the 182 | rest of the clock. 183 | 184 | This is also the way to adjust the display without adjusting time. Suppose 185 | you wish to switch to display option '1', just write a {\tt 32'h013fffff} to 186 | the register and the display will switch without adjusting time. 187 | 188 | \section{Count-down Timer} 189 | To use the count down timer, set it to the amount of time you wish to count 190 | down for. When ready, or even in the same cycle, enable the count--down 191 | timer by setting the RUN bit high. At this point in time, the count--down 192 | timer is running. When it gets to zero, it will stop and trigger an interrupt. 193 | You can tell if the alarm has been triggered by the TRIGGER bit being set. 194 | Any write to the timer register will clear the alarm condition. 195 | 196 | While the timer is running, writing a '0' to the timer register will stop it 197 | without clearing the time remaining. In this state, writing to the register 198 | the RUN bit by itself will restart the timer, while anything else will set the 199 | timer to a new value. Further, if the timer is stopped at zero, then writing 200 | zero to the timer will reset the timer to the last start time it had. 201 | 202 | \section{Stopwatch} 203 | The stop watch supports three operations: start, stop, and clear. Writing a 204 | '1' to the stop watch register will start the stopwatch, while writing a '0' 205 | will stop it. When it starts next, it will start where it left off unless the 206 | register is cleared. To clear the register and set it back to zero, write a 207 | '2' to the register. This will effectively stop the register and clear it in 208 | one step. If the register is already stopped, writing a '3' will clear and 209 | start it in one step. However, the register can only be cleared while stopped. 210 | If the register is running, writing a '3' will have no effect. 211 | 212 | \section{Alarm} 213 | To set the alarm, just write the alarm time to the alarm register together 214 | with alarm enable bit. As with the time register, setting any field, 215 | whether hours, minutes, or seconds, to {\tt 8'hff} has no effect on that 216 | field. Hence, the alarm may be activated by writing {\tt 25'h13fffff} to 217 | the register and deactivated by writing {\tt 25'h03fffff}. 218 | 219 | Once the alarm is tripped, the RTC core will generate an interrupt. Further, 220 | the tripped bit in the alarm register will be set. To clear this bit and the 221 | alarm tripped condition, either disable the alarm or write a '1' to this bit. 222 | 223 | \section{Time Hacks} 224 | 225 | For finer precision timing, the RTC module allows for setting a time 226 | hack and reading the value from the device. On the clock following the 227 | time hack being high, the internal state, to include the time and the 48~bit 228 | counter, will be recorded and may then be read out. In this fashion, 229 | it is possible to capture, with as much precision as the device offers, 230 | the current time within the device. 231 | 232 | It is the users responsibility to read the time hack registers before a 233 | subsequent time hack pulse sets them to new values. 234 | 235 | \section{Date} 236 | The Real--Time Date module is really a separate module from the Real--Time 237 | Clock module, but that doesn't prevent it from working just like the others. 238 | To set the date, just write the new date value to the address of the date. 239 | Further, as with the clock time, setting any particular field of the date to 240 | all ones, such as setting the month to {\tt 8'hff}, will cause that portion of 241 | the date to retain it's current value. In this way, one part of the date 242 | may be set and not others. 243 | 244 | \section{RTC--Light} 245 | The RTC Light module is nearly identical to the RTC clock module, save that 246 | it has been simplified for environments that have neither LED outputs nor 247 | seven segment display to drive. Further, the time hack registers have been 248 | replaced with read--only zero producing registers. Further, if the high 249 | order bit of the wishbone address is fixed to zero, the clock speed will no 250 | longer be adjustable--reducing the logic even further. 251 | 252 | This module is independent of the RTC clock module. 253 | 254 | \section{RTC GPS} 255 | As part of a GPS driven RTC solution, the RTC GPS module is provided. This 256 | module will use an externally provided PPS signal, one clock pulse wide and 257 | synchronized with the system clock, as well as an externally provided 258 | clock speed register. It has no time hack capability. Further, when the 259 | external GPS valid line is true, these additional two inputs will drive the 260 | clock. 261 | 262 | Operating this clock requires a variety of external GPS circuitry: a clocked 263 | PPS generator to generate both the PPS signal and the system clock speed 264 | reference, and a serial port processor to read the GPS time from the 265 | NMEA stream and to set the time value. With these external circuits, this 266 | clock will then have sub--millisecond accuracy. 267 | 268 | \chapter{Registers}\label{chap:regs} 269 | This RTC clock module supports eight registers, as listed in 270 | Tbl.~\ref{tbl:reglist}. Of these eight, the first four have been so placed 271 | as to be the more routine or user used registers, while the latter four are 272 | more lower level. 273 | \begin{table}[htbp] 274 | \begin{center} 275 | \begin{reglist} 276 | CLOCK & 0 & 32 & R/W & Wall clock time register\\\hline 277 | TIMER & 1 & 32 & R/W & Count--down timer\\\hline 278 | STPWTCH & 2 & 32 & R/W & Stopwatch control and value\\\hline 279 | ALARM & 3 & 32 & R/W & Alarm time, and setting\\\hline\hline 280 | CKSPEED & 4 & 32 & R/W & Clock speed control.\\\hline 281 | HACKTIME &5 & 32 & R & Wall clock time at last hack.\\\hline 282 | HACKCNTHI&6 & 32 & R & Wall clock time.\\\hline 283 | HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline 284 | \end{reglist}\caption{List of Registers}\label{tbl:reglist} 285 | \end{center}\end{table} 286 | Each register will be discussed in detail in this chapter. 287 | 288 | The Date module supports its own register, listed in 289 | Tbl.~\ref{tbl:datereg}. 290 | \begin{table}[htbp] 291 | \begin{center} 292 | \begin{reglist} 293 | DATE & 0 & 32 & R/W & Calendar date register\\\hline 294 | \end{reglist}\caption{Date Register}\label{tbl:datereg} 295 | \end{center}\end{table} 296 | This register will be discussed after we discuss the time registers. 297 | 298 | \section{Clock Time Register} 299 | The various bit fields associated with the current time may be found in 300 | the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}. 301 | \begin{table}[htbp]\begin{center} 302 | \begin{bitlist} 303 | 26--31 & R & Always return zero.\\\hline 304 | 24--25 & R/W & Seven Segment Display Mode.\\\hline 305 | 22--23 & R & Always return zero.\\\hline 306 | 16--21 & R/W & Current time, BCD hours\\\hline 307 | 8--15 & R/W & Current time, BCD minutes\\\hline 308 | 0--7 & R/W & Current time, BCD seconds\\\hline 309 | \end{bitlist} 310 | \caption{Clock Time Register Bit Definitions}\label{tbl:clockreg} 311 | \end{center}\end{table} 312 | This register contains six clock digits: two each for hours, minutes, and 313 | seconds. Each of these digits is encoded in Binary Coded Decimal (BCD). 314 | Therefore, 23~hours would be encoded as 6'h23 and not 6'h17. Writes to each 315 | of the various subcomponent registers will set that register, unless the 316 | write value is a 8'hff. The behaviour of the clock when non--decimal 317 | values are written, other than all F's, is undefined. 318 | 319 | Separate from the time, however, is the seven segment display mode. Four 320 | values are currently supported: 2'h0 to display the hours and minutes, 321 | 2'h1 to display the timer in minutes and seconds, 2'h2 to display the 322 | stopwatch in lower order minutes, seconds, and sixteenths of a second, and 323 | 2'h3 to display the minutes and seconds of the current time. In all cases, 324 | the decimal point will appear to the right of the lowest order digit 325 | and will blink with the second hand. That is, the decimal will be high for 326 | the second half of any second, and low at the top of the second. 327 | 328 | In the case of the RTC light, the seven segment display controller bits have 329 | been wired to zeros. 330 | 331 | In the case of the RTC modified for GPS, the most significant bit \#31 has 332 | been modified to produce a zero if the GPS lock signal is true, or a one 333 | for an error condition. 334 | 335 | \section{Countdown Timer Register} 336 | The countdown timer register, whose bit--wise values are shown in 337 | Tbl.~\ref{tbl:timer}, 338 | \begin{table}[htbp] 339 | \begin{center} 340 | \begin{bitlist} 341 | 26--31 & R & Unused, always read as '0'.\\\hline 342 | 25 & R/W & Alarm condition. Write a '1' to clear.\\\hline 343 | 24 & R/W & Running, stopped on '0'\\\hline 344 | 16--23 & R/W & BCD Hours\\\hline 345 | 8--15 & R/W & BCD Minutes\\\hline 346 | 0--7 & R/W & BCD Seconds\\\hline 347 | \end{bitlist} 348 | \caption{Count--down Timer register}\label{tbl:timer} 349 | \end{center}\end{table} 350 | controls the operation of the count--down timer. To use this timer, write 351 | some amount of time to the register, then write zeros with bit 24 set. The 352 | register will then reach an alarm condition after counting down that amount 353 | of time. (Alternatively, you could set bit 24 while writing the register, 354 | to set and start it in one operation.) To stop the register while it is 355 | running, just write all zeros. To restart the register, provided more than a 356 | second remains, write a {\tt 26'h1000000} to set it running again. Once 357 | the timer alarms, the timer will stop and the alarm condition will be set. 358 | Any write to the timer register after the alarm condition has been set will 359 | clear the alarm condition. 360 | 361 | \section{Stopwatch Register} 362 | The various bits of the stopwatch register are shown in 363 | Tbl.~\ref{tbl:stopwatch}. 364 | \begin{table}[htbp] 365 | \begin{center} 366 | \begin{bitlist} 367 | 24--31 & R & Hours\\\hline 368 | 16--23 & R & Minutes\\\hline 369 | 8--15 & R & Sub Seconds\\\hline 370 | 1--7 & R & Sub Seconds\\\hline 371 | 1 & W & Clear\\\hline 372 | 0 & R/W & Running\\\hline 373 | \end{bitlist} 374 | \caption{Stopwatch Register}\label{tbl:stopwatch} 375 | \end{center}\end{table} 376 | Of note is the bottom bit that, when set, means the stop watch is running. 377 | Set this bit to '1' to start the stopwatch, or to '0' to stop the stopwatch. 378 | Further, while the stopwatch is stopped, a '1' can be written to the clear 379 | bit. This will zero out the stopwatch and set it back to zero. 380 | 381 | \section{Alarm Register} 382 | The various bits of the alarm register are shown in Tbl.~\ref{tbl:alarm}. 383 | \begin{table}[htbp] 384 | \begin{center} 385 | \begin{bitlist} 386 | 26--31 & R & Always reads zeros. \\\hline 387 | 25 & R/W & Alarm tripped. Write a '1' to this register to clear any alarm 388 | condition. (A tripped alarm will not trip again.)\\\hline 389 | 24 & R/W & Alarm enabled\\\hline 390 | 16--23 & R & Alarm time, BCD hours\\\hline 391 | 8--15 & R & Alarm time, BCD minutes\\\hline 392 | 0--7 & R/W & Alarm time, BCD Seconds\\\hline 393 | \end{bitlist} 394 | \caption{Alarm Register}\label{tbl:alarm} 395 | \end{center}\end{table} 396 | Basically, the alarm register consists a time and two more bits. The extra 397 | two bits encode whether or not the alarm is enabled, and whether or not it has 398 | been tripped. The alarm will be {\em tripped} whenever it is enabled, and the 399 | time changes to equal the alarm time. Once tripped, the alarm will stay 400 | in the alarmed or tripped condition until either a '1' is written to the 401 | tripped bit, or the alarm is disabled. 402 | 403 | As with the clock and timer registers, writing eight ones to any of the 404 | BCD fields when writing to this register will leave those fields untouched. 405 | 406 | \section{Clock Speed Register} 407 | The actual speed of the clock is controlled by the {\tt CKSPEED} register, 408 | shown in Tbl.~\ref{tbl:ckspeed}. 409 | \begin{table}[htbp] 410 | \begin{center} 411 | \begin{bitlist} 412 | 0--31 & R/W & 48~bit counter time increment\\\hline 413 | \end{bitlist} 414 | \caption{Clock Speed Register}\label{tbl:ckspeed} 415 | \end{center}\end{table} 416 | This register contains a simple 32~bit unsigned value. To step the clock, 417 | this value is extended to 48~bits and added to the fractional seconds value. 418 | 419 | This value should be set to $2^{48}$ divided by the clock frequency of the 420 | controlling clock. Hence, for a 100~MHz clock, this value would be set to 421 | {\tt 32'd2814750}. For clocks near 100~MHz, this allows adjusting speed 422 | within about 40~clocks per second. For clocks near 500~MHz, this allows 423 | time adjustment to an accuracy of about about 800~clocks per second. In 424 | both cases, this is good enough to maintain a clock with less than a 425 | microsecond loss over the course of a year. Hence, this RTC module provides 426 | more logical stability than most hardware clocks on the market today. 427 | 428 | \section{Time--hack time} 429 | To support finer precision clock control, the time--hack capability exists. 430 | This capability consists of three registers, the time--hack time register 431 | shown in Tbl.~\ref{tbl:hacktime}, 432 | \begin{table}[htbp] 433 | \begin{center} 434 | \begin{bitlist} 435 | 24--31 & R & BCD Hours.\\\hline 436 | 16--23 & R & BCD Minutes.\\\hline 437 | 8--15 & R & BCD seconds.\\\hline 438 | 0--7 & R & Subseconds, encoded in 256ths of a second\\\hline 439 | \end{bitlist} 440 | \caption{Time Hack Time Register}\label{tbl:hacktime} 441 | \end{center}\end{table} 442 | and two registers (Tbls.~\ref{tbl:hackcnthi} 443 | \begin{table}[htbp] 444 | \begin{center} 445 | \begin{bitlist} 446 | 0--31 & R & Upper 32 bits of the internal 40~bit counter.\\\hline 447 | \end{bitlist} 448 | \caption{Time Hack Counter, High}\label{tbl:hackcnthi} 449 | \end{center}\end{table} 450 | and~\ref{tbl:hackcntlo}) 451 | \begin{table}[htbp] 452 | \begin{center} 453 | \begin{bitlist} 454 | 24--31 & R & Bottom 8~bits of the internal 40~bit counter.\\\hline 455 | 0--23 & R & Always read as '0'.\\\hline 456 | \end{bitlist} 457 | \caption{Time Hack Counter, Low}\label{tbl:hackcntlo} 458 | \end{center}\end{table} 459 | capturing the contents of the 40~bit internal counter at the time of the hack. 460 | 461 | The time--hack time register is perhaps the simplest to understand. This 462 | captures the time of the time--hack in hours, minutes, seconds, and 8~fractional 463 | subsecond bits. The top 24~bits of this register will match the bottom 24~bits 464 | of the clock~time register at the time of the time hack. The bottom eight 465 | bits are the top eight bits of the 48~bit subsecond time counter. The 466 | rest of those 48~bits may then be returned in the other two time hack counter 467 | registers. 468 | 469 | At present, this functionality isn't yet truly fully featured. Once fully 470 | featured, there will (should) be a mechanism for adjusting this counter based 471 | upon information gleaned from the hack time. Implementation details have 472 | to date prevented this portion of the design from being implemented. 473 | 474 | \section{Date Register} 475 | The year, month, and day of month fields may all be found within the 476 | {\tt DATE} register of the Real--Time Date module, shown in 477 | Tbl.~\ref{tbl:datebits}. 478 | \begin{table}[htbp]\begin{center} 479 | \begin{bitlist} 480 | 30--31 & R & Always return zero.\\\hline 481 | 16--29 & R/W & Four digit BCD year\\\hline 482 | 13--15 & R & Always return zero.\\\hline 483 | 8--12 & R/W & Two digit BCD month\\\hline 484 | 6--7 & R & Always return zero.\\\hline 485 | 0--5 & R/W & Two digit BCD day of month\\\hline 486 | \end{bitlist} 487 | \caption{Date Register Bit Definitions}\label{tbl:datebits} 488 | \end{center}\end{table} 489 | Further, according to the common calendar convention, the minimum day and month 490 | are one and not zero. 491 | 492 | \chapter{Wishbone Datasheet}\label{chap:wishbone} 493 | Tbl.~\ref{tbl:wishbone} 494 | \begin{table}[htbp] 495 | \begin{center} 496 | \begin{wishboneds} 497 | Revision level of wishbone & WB B4 spec \\\hline 498 | Type of interface & Slave, Read/Write \\\hline 499 | Port size & 32--bit \\\hline 500 | Port granularity & 32--bit \\\hline 501 | Maximum Operand Size & 32--bit \\\hline 502 | Data transfer ordering & (Irrelevant) \\\hline 503 | Clock constraints & Faster than 66~kHz \\\hline 504 | Signal Names & \begin{tabular}{ll} 505 | Signal Name & Wishbone Equivalent \\\hline 506 | {\tt i\_clk} & {\tt CLK\_I} \\ 507 | {\tt i\_wb\_cyc} & {\tt CYC\_I} \\ 508 | {\tt i\_wb\_stb} & {\tt STB\_I} \\ 509 | {\tt i\_wb\_we} & {\tt WE\_I} \\ 510 | {\tt i\_wb\_addr} & {\tt ADR\_I} \\ 511 | {\tt i\_wb\_data} & {\tt DAT\_I} \\ 512 | {\tt o\_wb\_ack} & {\tt ACK\_O} \\ 513 | {\tt o\_wb\_stall} & {\tt STALL\_O} \\ 514 | {\tt o\_wb\_data} & {\tt DAT\_O} 515 | \end{tabular}\\\hline 516 | \end{wishboneds} 517 | \caption{Wishbone Datasheet}\label{tbl:wishbone} 518 | \end{center}\end{table} 519 | is required by the wishbone specification, and so 520 | it is included here. The big thing to notice is that both the real time clock 521 | and the real time date modules act as wishbone slaves, and that all accesses 522 | to the registers of either module are 32--bit reads and writes. The address 523 | bus does not offer 524 | byte level, but rather 32--bit word level resolution. Select lines are not 525 | implemented. Bit ordering is the normal ordering where bit~31 is the most 526 | significant bit and so forth. Although the stall line is implemented, it is 527 | always zero. Access delays are a single clock, so the clock after a read or 528 | write is placed on the bus the {\tt i\_wb\_ack} line will be high. 529 | 530 | \iffalse 531 | \chapter{Clocks}\label{chap:clocks} 532 | 533 | This core is based upon the Basys--3 design. The Basys--3 development board 534 | contains one external 100~MHz clock, which is sufficient to run this 535 | core. The logic within the core can also be run faster, or slower, as is 536 | necessary to meet the timing constraints associated with the internal 537 | operations of the core and it's surrounding environment. See 538 | Table.~\ref{tbl:clocks}. 539 | \begin{table}[htbp] 540 | \begin{center} 541 | \begin{clocklist} 542 | i\_clk & External & 250~THz & 66~kHz & System clock.\\\hline 543 | \end{clocklist} 544 | \caption{List of Clocks}\label{tbl:clocks} 545 | \end{center}\end{table} 546 | 547 | \fi 548 | 549 | \chapter{I/O Ports}\label{chap:ioports} 550 | The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone} 551 | \begin{table}[htbp] 552 | \begin{center} 553 | \begin{portlist} 554 | i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline 555 | i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline 556 | i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline 557 | i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline 558 | i\_wb\_addr & 5 & Input & Wishbone address.\\\hline 559 | i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing 560 | (configuring) the core from the bus.\\\hline 561 | o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or 562 | signifying valid data in the case of a wishbone read request. 563 | \\\hline 564 | o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another 565 | wishbone access, effectively stalling the bus.\\\hline 566 | o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read 567 | from the interface.\\\hline 568 | \end{portlist} 569 | \caption{Wishbone I/O Ports}\label{tbl:iowishbone} 570 | \end{center}\end{table} 571 | and~Tbl.~\ref{tbl:ioother}. 572 | \begin{table}[htbp] 573 | \begin{center} 574 | \begin{portlist} 575 | o\_sseg & 32 & Output & Lines to control a seven segment display, to be 576 | sent to that display's driver. Each eight bit byte controls 577 | one digit in the display, with the bottom bit in the byte 578 | controlling the decimal point.\\\hline 579 | o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting 580 | from zero to all ones each minute, and synchronized with each 581 | minute so as to create an indicator of when the next minute 582 | will take place when only the hours and minutes can be 583 | displayed.\\\hline 584 | o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the 585 | clock needs to generate an interrupt, it will set this line 586 | high for one clock cycle. \\\hline 587 | o\_ppd & 1 & Output & A `pulse per day' signal which can be fed into the 588 | real--time date module. This line will be high on the clock before 589 | the stroke of midnight, allowing the date module to turn over to the 590 | next day at exactly the same time the clock module turns over to the 591 | next day.\\\hline 592 | i\_hack & 1 & Input & When this line is raised, copies are made of the 593 | internal state registers on the next clock. These registers can then 594 | be used for an accurate time hack regarding the state of the clock 595 | at the time this line was strobed.\\\hline 596 | \end{portlist} 597 | \caption{Other I/O Ports}\label{tbl:ioother} 598 | \end{center}\end{table} 599 | Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in 600 | Chapt.~\ref{chap:wishbone}, and so need no further discussion here. 601 | 602 | This clock is designed for command and control via the wishbone. No other 603 | registers, beyond the wishbone bus, are required. However, several other 604 | may be valuable. These other registers are listed in Tbl.~\ref{tbl:ioother}. 605 | We'll discuss each of these in turn. 606 | 607 | First of the other I/O registers is the {\tt o\_sseg} register. This register 608 | encodes which outputs of a seven segment display need to be turned on to 609 | represent the value of the clock requested. This register consists of four 610 | eight bit bytes, with the highest order byte referencing the highest order 611 | display segment value. In each byte, the low order bit references a decimal 612 | point. The other bits are ordered around the zero, with the top bit being 613 | the top bar of a '0', the next highest order bit and so on following the 614 | zero clockwise. The final bit of each byte, the bit in the two's place, 615 | encodes whether or not the middle line is to be displayed. When either timer 616 | or alarm is triggered, this display will blink until the triggering conditions 617 | are cleared. 618 | 619 | This output is expected to be the input to a seven segment display driver, 620 | rather than being the output to the display itself. 621 | 622 | The next output lines are the 16~lines of the {\tt o\_led} bus. When connected 623 | with 16~LED's, these lines will create a counting display that will count up 624 | to each minute, synchronized to the minute. When either timer or alarm has 625 | triggered, all of the LED's will flash together until the triggered condition 626 | is reset. 627 | 628 | The third other line is the {\tt o\_interrupt} line. This line will be 629 | strobed by the RTC module any time the alarm is triggered or the timer runs 630 | out. The line will not remain high, but neither will it trigger a second 631 | time until the underlying interrupt is cleared. That is, the timer will only 632 | trigger once until cleared as will the alarm, but the alarm may trigger after 633 | the timer has triggered and before the timer clears. 634 | 635 | As a fourth additional line, the clock module produces a one pulse per day 636 | signal, {\tt o\_ppd}. This signal is designed to be the only necessary 637 | coordinated input between the clock and date module. Feeding it straight 638 | into the date module will keep the two synchronized. 639 | 640 | The final other I/O line is a simple input line. This line is expected to be 641 | strobed for one clock cycle any time a time hack is required. For example, 642 | should you wish to read and synchronize to a GPS PPS signal, strobe the device 643 | with the PPS (after dealing with any metastability issues), and read the time 644 | hacks that are produced. 645 | 646 | The real--time date module has a similar set of I/O ports to the clock. These 647 | are listed in Tbl.~\ref{tbl:iodate}. 648 | \begin{table}[htbp] 649 | \begin{center} 650 | \begin{portlist} 651 | i\_clk & 1 & Input & The system clock.\\\hline 652 | i\_ppd & 1 & Input & The one pulse per day strobe from the clock module.\\\hline 653 | i\_wb\_cyc & 1 & Input & Wishbone bus cycle.\\\hline 654 | i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline 655 | i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline 656 | i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing 657 | (configuring) the core from the bus.\\\hline 658 | o\_wb\_ack & 1 & Output & Equal to the bus cycle line anded with the strobe 659 | line, and delayed by one clock---essentially acknowledging any 660 | wishbone access.\\\hline 661 | o\_wb\_stall & 1 & Output & Fixed to zer.\\\hline 662 | o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read 663 | from the interface.\\\hline 664 | \end{portlist} 665 | \caption{Wishbone I/O Ports}\label{tbl:iodate} 666 | \end{center}\end{table} 667 | There are two big things to notice. The first is the {\tt i\_ppd} signal. 668 | This should be connected straight from the clock module's {\tt o\_ppd} signal 669 | into this module. The second difference is the lack of any address lines. 670 | This is appropriate since the date module provides a single register only. 671 | 672 | % Appendices 673 | % Index 674 | \end{document} 675 | 676 | 677 | -------------------------------------------------------------------------------- /rtcclock.core: -------------------------------------------------------------------------------- 1 | CAPI=1 2 | [main] 3 | description = A Real Time Clock Core 4 | 5 | [fileset rtl] 6 | files = 7 | rtl/rtcclock.v 8 | rtl/rtclight.v 9 | rtl/rtcgps.v 10 | rtl/rtcdate.v 11 | rtl/hexmap.v 12 | file_type = verilogSource 13 | 14 | -------------------------------------------------------------------------------- /rtl/Makefile: -------------------------------------------------------------------------------- 1 | ############################################################################/ 2 | ## 3 | ## Filename: Makefile 4 | ## {{{ 5 | ## Project: A Wishbone Controlled Real--time Clock Core 6 | ## 7 | ## Purpose: This is the Makefile to build the verilator test bench code 8 | ## from the RTL code. The TB code in the bench/cpp directory 9 | ## will then reference the library results from this file. To build the 10 | ## verilator libraries, just type 'make' on a line by itself. 11 | ## 12 | ## Creator: Dan Gisselquist, Ph.D. 13 | ## Gisselquist Tecnology, LLC 14 | ## 15 | ##########################################################################/ 16 | ## }}} 17 | ## Copyright (C) 2015-2024, Gisselquist Technology, LLC 18 | ## {{{ 19 | ## This program is free software (firmware): you can redistribute it and/or 20 | ## modify it under the terms of the GNU General Public License as published 21 | ## by the Free Software Foundation, either version 3 of the License, or (at 22 | ## your option) any later version. 23 | ## 24 | ## This program is distributed in the hope that it will be useful, but WITHOUT 25 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | ## for more details. 28 | ## 29 | ## You should have received a copy of the GNU General Public License along 30 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | ## target there if the PDF file isn't present.) If not, see 32 | ## for a copy. 33 | ## }}} 34 | ## License: GPL, v3, as defined and found on www.gnu.org, 35 | ## {{{ 36 | ## http://www.gnu.org/licenses/gpl.html 37 | ## 38 | ##########################################################################/ 39 | ## 40 | ## }}} 41 | # This is really simple ... 42 | all: rtcdate rtclight rtcgps rtcclock 43 | OBJDR := ./obj_dir 44 | BENCHD := ../bench/cpp 45 | VERILATOR := verilator 46 | VFLAGS := -Wall -MMD -trace -cc 47 | SUBMAKE := $(MAKE) --no-print-directory -C 48 | 49 | .PHONY: rtcclock 50 | ## {{{ 51 | rtcclock: $(OBJDR)/Vrtcclock__ALL.a 52 | $(OBJDR)/Vrtcclock.cpp $(OBJDR)/Vrtcclock.h: rtcclock.v 53 | $(VERILATOR) $(VFLAGS) rtcclock.v 54 | # $(OBJDR)/Vrtcclock__ALL.a: $(OBJDR)/Vrtcclock.h 55 | $(OBJDR)/Vrtcclock__ALL.a: $(OBJDR)/Vrtcclock.cpp 56 | $(SUBMAKE) $(OBJDR)/ -f Vrtcclock.mk 57 | ## }}} 58 | 59 | .PHONY: rtcdate 60 | ## {{{ 61 | rtcdate: $(OBJDR)/Vrtcdate__ALL.a 62 | $(OBJDR)/Vrtcdate.cpp $(OBJDR)/Vrtcdate.h: rtcdate.v 63 | $(VERILATOR) $(VFLAGS) rtcdate.v 64 | # $(OBJDR)/Vrtcdate__ALL.a: $(OBJDR)/Vrtcdate.h 65 | $(OBJDR)/Vrtcdate__ALL.a: $(OBJDR)/Vrtcdate.cpp 66 | $(SUBMAKE) $(OBJDR)/ -f Vrtcdate.mk 67 | ## }}} 68 | 69 | .PHONY: rtclight 70 | ## {{{ 71 | rtclight: $(OBJDR)/Vrtclight__ALL.a 72 | $(OBJDR)/Vrtclight.cpp $(OBJDR)/Vrtclight.h: rtclight.v 73 | $(VERILATOR) $(VFLAGS) rtclight.v 74 | # $(OBJDR)/Vrtclight__ALL.a: $(OBJDR)/Vrtclight.h 75 | $(OBJDR)/Vrtclight__ALL.a: $(OBJDR)/Vrtclight.cpp 76 | $(SUBMAKE) $(OBJDR)/ -f Vrtclight.mk 77 | ## }}} 78 | 79 | .PHONY: rtcgps 80 | ## {{{ 81 | rtcgps: $(OBJDR)/Vrtcgps__ALL.a 82 | $(OBJDR)/Vrtcgps.cpp $(OBJDR)/Vrtcgps.h: rtcgps.v 83 | $(VERILATOR) $(VFLAGS) rtcgps.v 84 | # $(OBJDR)/Vrtcgps__ALL.a: $(OBJDR)/Vrtcgps.h 85 | $(OBJDR)/Vrtcgps__ALL.a: $(OBJDR)/Vrtcgps.cpp 86 | $(SUBMAKE) $(OBJDR)/ -f Vrtcgps.mk 87 | ## }}} 88 | 89 | ## Dependency handling 90 | ## {{{ 91 | DEPS := $(wildcard $(OBJDR)/*.d) 92 | 93 | ifneq ($(DEPS),) 94 | include $(DEPS) 95 | endif 96 | ## }}} 97 | 98 | .PHONY: clean 99 | ## {{{ 100 | clean: 101 | rm -rf $(OBJDR) 102 | ## }}} 103 | 104 | -------------------------------------------------------------------------------- /rtl/hexmap.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: hexmap.v 4 | // {{{ 5 | // Project: A Real--time Clock Core 6 | // 7 | // Purpose: Converts a 4'bit hexadecimal value to the seven bits needed 8 | // by a seven segment display, specifying which bits are on and 9 | // which are off. 10 | // 11 | // The display I am working with, however, requires a separate 12 | // controller. This file only provides part of the input for that 13 | // controller. That controller deals with turning on each part 14 | // of the display in a rotating fashion, since the hardware I have 15 | // cannot display more than one character at a time. So, 16 | // buyer beware--this is not a complete seven segment display 17 | // solution. 18 | // 19 | // 20 | // The outputs of this routine are numbered as follows: 21 | // o_map[7] turns on the bar at the top of the display 22 | // o_map[6] turns on the top of the '1' 23 | // o_map[5] turns on the bottom of a '1' 24 | // o_map[4] turns on the bar at the bottom of the display 25 | // o_map[3] turns on the vertical bar at the bottom left 26 | // o_map[2] turns on the vertical bar at the top left, and 27 | // o_map[1] turns on the bar in the middle of the display. 28 | // The dash if you will. 29 | // Bit zero, from elsewhere, would be the decimal point. 30 | // 31 | // Creator: Dan Gisselquist, Ph.D. 32 | // Gisselquist Tecnology, LLC 33 | // 34 | /////////////////////////////////////////////////////////////////////////// 35 | // }}} 36 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 37 | // {{{ 38 | // This program is free software (firmware): you can redistribute it and/or 39 | // modify it under the terms of the GNU General Public License as published 40 | // by the Free Software Foundation, either version 3 of the License, or (at 41 | // your option) any later version. 42 | // 43 | // This program is distributed in the hope that it will be useful, but WITHOUT 44 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 45 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 46 | // for more details. 47 | // 48 | // You should have received a copy of the GNU General Public License along 49 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 50 | // target there if the PDF file isn't present.) If not, see 51 | // for a copy. 52 | // }}} 53 | // License: GPL, v3, as defined and found on www.gnu.org, 54 | // {{{ 55 | // http://www.gnu.org/licenses/gpl.html 56 | // 57 | //////////////////////////////////////////////////////////////////////////////// 58 | // 59 | `default_nettype none 60 | // }}} 61 | module hexmap( 62 | // {{{ 63 | input wire i_clk, 64 | input wire [3:0] i_hex, 65 | output reg [7:1] o_map 66 | // }}} 67 | ); 68 | 69 | always @(posedge i_clk) 70 | case(i_hex) 71 | 4'h0: o_map <= { 7'b1111110 }; 72 | 4'h1: o_map <= { 7'b0110000 }; 73 | 4'h2: o_map <= { 7'b1101101 }; 74 | 4'h3: o_map <= { 7'b1111001 }; 75 | 4'h4: o_map <= { 7'b0110011 }; 76 | 4'h5: o_map <= { 7'b1011011 }; 77 | 4'h6: o_map <= { 7'b1011111 }; 78 | 4'h7: o_map <= { 7'b1110000 }; 79 | 4'h8: o_map <= { 7'b1111111 }; 80 | 4'h9: o_map <= { 7'b1111011 }; 81 | 4'ha: o_map <= { 7'b1110111 }; 82 | 4'hb: o_map <= { 7'b0011111 }; // b 83 | 4'hc: o_map <= { 7'b1001110 }; 84 | 4'hd: o_map <= { 7'b0111101 }; // d 85 | 4'he: o_map <= { 7'b1001111 }; 86 | 4'hf: o_map <= { 7'b1000111 }; 87 | endcase 88 | endmodule 89 | -------------------------------------------------------------------------------- /rtl/rtcalarm.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcalarm.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch 6 | // 7 | // Purpose: Implement an alarm for a real time clock. 8 | // 9 | // 10 | // Creator: Dan Gisselquist, Ph.D. 11 | // Gisselquist Technology, LLC 12 | // 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // }}} 15 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | // {{{ 17 | // This program is free software (firmware): you can redistribute it and/or 18 | // modify it under the terms of the GNU General Public License as published 19 | // by the Free Software Foundation, either version 3 of the License, or (at 20 | // your option) any later version. 21 | // 22 | // This program is distributed in the hope that it will be useful, but WITHOUT 23 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | // for more details. 26 | // 27 | // You should have received a copy of the GNU General Public License along 28 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | // target there if the PDF file isn't present.) If not, see 30 | // for a copy. 31 | // }}} 32 | // License: GPL, v3, as defined and found on www.gnu.org, 33 | // {{{ 34 | // http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // 39 | `default_nettype none 40 | // }}} 41 | // set, clear, turn on, turn off 42 | module rtcalarm #( 43 | // {{{ 44 | parameter [0:0] OPT_PREVALIDATED_INPUT = 1'b0, 45 | parameter [21:0] OPT_INITIAL_ALARM_TIME = 0, 46 | parameter [0:0] OPT_START_ENABLED = 0, 47 | parameter [0:0] OPT_FIXED_ALARM_TIME = 0 48 | // }}} 49 | ) ( 50 | // {{{ 51 | input wire i_clk, i_reset, 52 | // 53 | input wire [21:0] i_now, 54 | // 55 | input wire i_wr, 56 | input wire i_clear, i_enable, 57 | input wire [21:0] i_alarm_time, 58 | input wire [2:0] i_valid, 59 | // 60 | output wire [31:0] o_data, 61 | output wire o_alarm 62 | // }}} 63 | ); 64 | 65 | // Signal declarations 66 | // {{{ 67 | reg [2:0] pre_valid; 68 | reg [21:0] validated_alarm_time; 69 | reg [21:0] alarm_time, past_time; 70 | reg enabled, // Whether the alarm is enabled 71 | tripped; // Whether the alarm has tripped 72 | // }}} 73 | 74 | // 75 | // The alarm code 76 | // 77 | // Set the alarm register to the time you wish the board to "alarm". 78 | // The "alarm" will take place once per day at that time. At that 79 | // time, the RTC code will generate a clock interrupt, and the CPU/host 80 | // can come and see that the alarm tripped. 81 | // 82 | // 83 | 84 | // enabled 85 | // {{{ 86 | initial enabled = OPT_START_ENABLED; 87 | always @(posedge i_clk) 88 | if (i_reset) 89 | enabled <= OPT_START_ENABLED; 90 | else if (i_wr) 91 | enabled <= i_enable; 92 | // }}} 93 | 94 | always @(posedge i_clk) 95 | past_time <= i_now; 96 | 97 | // tripped 98 | // {{{ 99 | initial tripped= 1'b0; 100 | always @(posedge i_clk) 101 | if (i_reset) 102 | tripped <= 1'b0; 103 | else if ((enabled)&&(i_now == alarm_time)&&(i_now != past_time)) 104 | tripped <= 1'b1; 105 | else if ((i_wr)&&(i_clear)) 106 | tripped <= 1'b0; 107 | // }}} 108 | 109 | // pre_valid, validated_alarm_time 110 | // {{{ 111 | generate if (OPT_PREVALIDATED_INPUT) 112 | begin : INPUT_IS_VALID 113 | // {{{ 114 | always @(*) 115 | pre_valid = ((!OPT_FIXED_ALARM_TIME)&&(i_wr)) 116 | ? i_valid : 0; 117 | 118 | always @(*) 119 | validated_alarm_time = i_valid; 120 | // }}} 121 | end else begin : CHECK_INPUT_VALIDITY 122 | // {{{ 123 | initial pre_valid = 0; 124 | always @(posedge i_clk) 125 | if ((i_reset)||(!i_wr)||(OPT_FIXED_ALARM_TIME)) 126 | pre_valid <= 0; 127 | else begin 128 | 129 | pre_valid[0] <= (i_valid[0]) 130 | &&(i_alarm_time[7:0] <= 8'h59) 131 | &&(i_alarm_time[3:0] <= 4'h9); 132 | 133 | pre_valid[1] <= (i_valid[1]) 134 | &&(i_alarm_time[15:8] <= 8'h59) 135 | &&(i_alarm_time[11:8] <= 4'h9); 136 | 137 | pre_valid[2] <= (i_valid[2]) 138 | &&(i_alarm_time[21:16] <= 6'h23) 139 | &&(i_alarm_time[19:16] <= 4'h9); 140 | end 141 | 142 | always @(posedge i_clk) 143 | validated_alarm_time <= i_alarm_time; 144 | // }}} 145 | end endgenerate 146 | // }}} 147 | 148 | // alarm_time 149 | // {{{ 150 | initial alarm_time = OPT_INITIAL_ALARM_TIME; 151 | always @(posedge i_clk) 152 | if (i_reset) 153 | alarm_time <= OPT_INITIAL_ALARM_TIME; 154 | else if (!OPT_FIXED_ALARM_TIME) begin 155 | // Only adjust the alarm hours if the requested hours 156 | // are valid. This allows writes to the register, 157 | // without a prior read, to leave these configuration 158 | // bits alone. 159 | if (pre_valid[0]) // Seconds 160 | alarm_time[7:0] <= validated_alarm_time[7:0]; 161 | if (pre_valid[1]) // Minutes 162 | alarm_time[15:8] <= validated_alarm_time[15:8]; 163 | if (pre_valid[2]) // Hours 164 | alarm_time[21:16] <= validated_alarm_time[21:16]; 165 | end 166 | // }}} 167 | 168 | assign o_data = { 6'h0, tripped, enabled, 2'b00, alarm_time }; 169 | assign o_alarm = tripped; 170 | 171 | // Make verilator happy 172 | // {{{ 173 | // verilator lint_off UNUSED 174 | // wire unused; 175 | // assign unused = &{ 1'b0, i_wb_cyc, i_wb_data[31:26] }; 176 | // verilator lint_on UNUSED 177 | // }}} 178 | //////////////////////////////////////////////////////////////////////////////// 179 | //////////////////////////////////////////////////////////////////////////////// 180 | //////////////////////////////////////////////////////////////////////////////// 181 | // 182 | // Formal properties 183 | // {{{ 184 | //////////////////////////////////////////////////////////////////////////////// 185 | //////////////////////////////////////////////////////////////////////////////// 186 | //////////////////////////////////////////////////////////////////////////////// 187 | `ifdef FORMAL 188 | `ifdef RTCALARM 189 | `define ASSUME assume 190 | `define ASSERT assert 191 | `else 192 | `define ASSUME assert 193 | `define ASSERT assume 194 | `endif 195 | 196 | reg f_past_valid; 197 | initial f_past_valid = 1'b0; 198 | always @(posedge i_clk) 199 | f_past_valid <= 1'b1; 200 | 201 | always @(posedge i_clk) 202 | if (!f_past_valid) 203 | `ASSUME((i_now == 0)&&(!i_wr)); 204 | 205 | always @(posedge i_clk) 206 | if ((!f_past_valid)||($past(i_reset))) 207 | begin 208 | `ASSERT(!tripped); 209 | `ASSERT(enabled == OPT_START_ENABLED); 210 | `ASSERT(alarm_time == OPT_INITIAL_ALARM_TIME); 211 | end 212 | 213 | always @(*) 214 | if (OPT_FIXED_ALARM_TIME) 215 | `ASSERT(alarm_time == OPT_INITIAL_ALARM_TIME); 216 | 217 | always @(*) 218 | begin 219 | `ASSUME(i_now[ 3: 0] <= 4'h9); 220 | `ASSUME(i_now[ 7: 4] <= 4'h5); 221 | `ASSUME(i_now[11: 8] <= 4'h9); 222 | `ASSUME(i_now[15:12] <= 4'h5); 223 | `ASSUME(i_now[19:16] <= 4'h9); 224 | `ASSUME(i_now[21:16] <= 8'h23); 225 | end 226 | 227 | generate if (OPT_PREVALIDATED_INPUT) 228 | begin : F_ASSUME_VALID_INPUTS 229 | 230 | always @(*) 231 | if (pre_valid[0]) 232 | begin 233 | `ASSUME(i_alarm_time[ 3: 0] <= 4'h9); 234 | `ASSUME(i_alarm_time[ 7: 4] <= 4'h5); 235 | end 236 | 237 | always @(*) 238 | if (pre_valid[1]) 239 | begin 240 | `ASSUME(i_alarm_time[11: 8] <= 4'h9); 241 | `ASSUME(i_alarm_time[15:12] <= 4'h5); 242 | end 243 | 244 | always @(*) 245 | if (pre_valid[2]) 246 | begin 247 | `ASSUME(i_alarm_time[19:16] <= 4'h9); 248 | `ASSUME(i_alarm_time[21:16] <= 8'h23); 249 | end 250 | 251 | end endgenerate 252 | 253 | always @(*) 254 | begin 255 | `ASSERT(alarm_time[ 3: 0] <= 4'h9); 256 | `ASSERT(alarm_time[ 7: 4] <= 4'h5); 257 | `ASSERT(alarm_time[11: 8] <= 4'h9); 258 | `ASSERT(alarm_time[15:12] <= 4'h5); 259 | `ASSERT(alarm_time[19:16] <= 4'h9); 260 | `ASSERT(alarm_time[21:16] <= 8'h23); 261 | end 262 | 263 | always @(posedge i_clk) 264 | if ((f_past_valid)&&($past(enabled))&&(!$past(i_reset)) 265 | &&($past(i_now) == $past(alarm_time)) 266 | &&($past(i_now) != $past(past_time))) 267 | `ASSERT(tripped); 268 | else if ((!f_past_valid)||($past(i_reset))||(!$past(tripped))) 269 | `ASSERT(!tripped); 270 | else if (($past(i_wr))&&($past(i_clear))) 271 | `ASSERT(!tripped); 272 | 273 | always @(posedge i_clk) 274 | if ((f_past_valid)&&($past(i_wr))&&(!$past(i_reset))) 275 | `ASSERT(enabled == $past(i_enable)); 276 | 277 | //////////////////////////////////////////////////////////////////////// 278 | // 279 | // Cover checks 280 | // {{{ 281 | //////////////////////////////////////////////////////////////////////// 282 | // 283 | always @(posedge i_clk) 284 | if ((f_past_valid)&&(!$past(tripped))) 285 | cover(tripped); 286 | 287 | always @(posedge i_clk) 288 | if ((f_past_valid)&&($past(tripped))) 289 | cover(!tripped); 290 | // }}} 291 | `endif 292 | // }}} 293 | endmodule 294 | -------------------------------------------------------------------------------- /rtl/rtcbare.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcbare.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch 6 | // 7 | // Purpose: This is the bare RTC clock logic. It accepts an (optional) 8 | // 1pps signal input, and has a write interface for setting 9 | // the clock. The clock itself is a BCD integer of the form 00HHMMSS. 10 | // 11 | // Writes to the clock will change the current data. The change will 12 | // take roughly five clocks to propagate, to insure that there are no 13 | // violations of the BCD clock format. 14 | // 15 | // Upon a PPS strobe (true for one clock only), the clock will advance. 16 | // The clock rate is assumed to be faster than 5Hz, allowing BCD 17 | // propagation through the clock fabric. 18 | // 19 | // The clock also outputs a PPD output. This is a once-per-day strobe 20 | // that will be true on the clock prior to the new day. It is used by 21 | // the rtcdate core to advance the date. 22 | // 23 | // Creator: Dan Gisselquist, Ph.D. 24 | // Gisselquist Technology, LLC 25 | // 26 | //////////////////////////////////////////////////////////////////////////////// 27 | // }}} 28 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 29 | // {{{ 30 | // This program is free software (firmware): you can redistribute it and/or 31 | // modify it under the terms of the GNU General Public License as published 32 | // by the Free Software Foundation, either version 3 of the License, or (at 33 | // your option) any later version. 34 | // 35 | // This program is distributed in the hope that it will be useful, but WITHOUT 36 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 37 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 38 | // for more details. 39 | // 40 | // You should have received a copy of the GNU General Public License along 41 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 42 | // target there if the PDF file isn't present.) If not, see 43 | // for a copy. 44 | // }}} 45 | // License: GPL, v3, as defined and found on www.gnu.org, 46 | // {{{ 47 | // http://www.gnu.org/licenses/gpl.html 48 | // 49 | // 50 | //////////////////////////////////////////////////////////////////////////////// 51 | // 52 | // 53 | `default_nettype none 54 | // }}} 55 | module rtcbare #( 56 | // {{{ 57 | // Set OPT_PREVALIDATED_INPUT to 1'b1 if the instantiating 58 | // module will never set i_wr true with invalid BCD data in 59 | // i_data. Otherwise, setting it to zero will cause a 60 | // validation check, and ignore any incoming values that are 61 | // not valid BCD on a bytewise level. 62 | parameter [0:0] OPT_PREVALIDATED_INPUT = 1'b0 63 | // }}} 64 | ) ( 65 | // {{{ 66 | input wire i_clk, i_reset, 67 | // Wishbone interface 68 | input wire i_pps, i_wr, 69 | input wire [21:0] i_data, 70 | input wire [2:0] i_valid, 71 | // Output registers 72 | output wire [21:0] o_data, // multiplexed based on i_wb_adr 73 | // A once-per-day strobe on the last clock of the day 74 | output wire o_ppd 75 | // }}} 76 | ); 77 | 78 | // Signal declarations 79 | // {{{ 80 | reg [21:0] bcd_clock, next_clock; 81 | reg [5:0] carry; 82 | reg pre_ppd; 83 | 84 | reg [2:0] pre_valid; 85 | reg [21:0] pre_bcd_clock; 86 | 87 | reg [2:0] suppressed, suppress_count; 88 | // }}} 89 | 90 | // pre_ppd 91 | // {{{ 92 | initial pre_ppd = 1'b0; 93 | always @(posedge i_clk) 94 | if (i_reset) 95 | pre_ppd <= 1'b0; 96 | else 97 | pre_ppd <= (bcd_clock == 22'h23_59_59); 98 | // }}} 99 | 100 | // carry, next_clock 101 | // {{{ 102 | initial carry = 0; 103 | initial next_clock = 22'h00_00_01; 104 | always @(posedge i_clk) 105 | if (i_reset) 106 | begin 107 | next_clock <= 22'h00_00_01; 108 | carry <= 0; 109 | end else begin 110 | // Takes 7 clocks to converge 111 | 112 | // Seconds 113 | carry[0] <= (bcd_clock[ 3: 0] >= 4'h9); 114 | carry[1] <= (bcd_clock[ 7: 4] >= 4'h5)&&( carry[ 0]); 115 | // Minutes 116 | carry[2] <= (bcd_clock[11: 8] >= 4'h9)&&(&carry[1:0]); 117 | carry[3] <= (bcd_clock[15:12] >= 4'h5)&&(&carry[2:0]); 118 | // Hours 119 | carry[4] <= (bcd_clock[19:16] >= 4'h9)&&(&carry[3:0]); 120 | carry[5] <= (bcd_clock[21:16] >= 6'h23)&&(&carry[3:0]); 121 | 122 | // Seconds 123 | if (carry[0]) 124 | next_clock[3:0] <= 4'h0; 125 | else 126 | next_clock[3:0] <= bcd_clock[3:0] + 4'h1; 127 | 128 | if (carry[1]) 129 | next_clock[7:4] <= 4'h0; 130 | else if (carry[0]) 131 | next_clock[7:4] <= bcd_clock[7:4] + 4'h1; 132 | else 133 | next_clock[7:4] <= bcd_clock[7:4]; 134 | 135 | // Minutes 136 | if (carry[2]) 137 | next_clock[11:8] <= 4'h0; 138 | else if (carry[1]) 139 | next_clock[11:8] <= bcd_clock[11:8] + 4'h1; 140 | else 141 | next_clock[11:8] <= bcd_clock[11:8]; 142 | 143 | if (carry[3]) 144 | next_clock[15:12] <= 4'h0; 145 | else if (carry[2]) 146 | next_clock[15:12] <= bcd_clock[15:12] + 4'h1; 147 | else 148 | next_clock[15:12] <= bcd_clock[15:12]; 149 | 150 | // Hours 151 | if ((carry[4])||(carry[5])) 152 | next_clock[19:16] <= 4'h0; 153 | else if (carry[3]) 154 | next_clock[19:16] <= bcd_clock[19:16] + 4'h1; 155 | else 156 | next_clock[19:16] <= bcd_clock[19:16]; 157 | 158 | if (carry[5]) 159 | next_clock[21:20] <= 2'h0; 160 | else if (carry[4]) 161 | next_clock[21:20] <= bcd_clock[21:20] + 2'h1; 162 | else 163 | next_clock[21:20] <= bcd_clock[21:20]; 164 | end 165 | // }}} 166 | 167 | // pre_bcd_clock, pre_valid 168 | // {{{ 169 | // Validate the input before setting the clock 170 | generate if (OPT_PREVALIDATED_INPUT) 171 | begin : NO_VALIDATION_REQUIRED 172 | // {{{ 173 | // Write data through with no check 174 | // This can be combinatorial, with no clock required. 175 | // 176 | always @(*) 177 | if (i_wr) 178 | pre_valid = i_valid; 179 | else 180 | pre_valid = 0; 181 | 182 | always @(*) 183 | pre_bcd_clock = i_data; 184 | // }}} 185 | end else begin : VALIDATE_INPUT_BCD 186 | // {{{ 187 | // Double check that the input contains valid BCD data 188 | // 189 | // We'll use this to prevent a write given invalid data 190 | // Requires one clock between write request and data update 191 | // 192 | initial pre_valid = 0; 193 | always @(posedge i_clk) 194 | if (i_reset) 195 | pre_valid <= 0; 196 | else if (i_wr) 197 | begin 198 | // Seconds 199 | pre_valid[0] <= (i_valid[0])&&(i_data[7:0] <= 8'h59) 200 | &&(i_data[3:0] <= 4'h9); 201 | // Minutes 202 | pre_valid[1] <= (i_valid[1])&&(i_data[15:8] <= 8'h59) 203 | &&(i_data[11:8] <= 4'h9); 204 | // Hours 205 | pre_valid[2] <= (i_valid[2])&&(i_data[21:16] <= 6'h23) 206 | &&(i_data[19:16] <= 4'h9); 207 | end else 208 | pre_valid <= 0; 209 | 210 | always @(posedge i_clk) 211 | pre_bcd_clock <= i_data; 212 | // }}} 213 | end endgenerate 214 | // }}} 215 | 216 | // suprpressed, suppress_count 217 | // {{{ 218 | initial suppressed = 3'h7; 219 | initial suppress_count = 3'h5; 220 | always @(posedge i_clk) 221 | if (i_reset) 222 | begin 223 | suppressed <= 3'h7; 224 | suppress_count <= 3'h5; 225 | end else if (|pre_valid) 226 | begin 227 | suppressed[0] <= (suppressed[0])||(pre_valid[ 0]!=1'b0); 228 | suppressed[1] <= (suppressed[1])||(pre_valid[1:0]!=2'b00); 229 | suppressed[2] <= (suppressed[2])||(pre_valid[2:0]!=3'b000); 230 | suppress_count <= 3'h5; 231 | end else if (suppress_count > 0) 232 | suppress_count <= suppress_count - 1; 233 | else 234 | suppressed <= 0; 235 | // }}} 236 | 237 | // bcd_clock 238 | // {{{ 239 | initial bcd_clock = 0; 240 | always @(posedge i_clk) 241 | if (i_reset) 242 | bcd_clock <= 0; 243 | else begin 244 | if (i_pps) 245 | begin 246 | if (!suppressed[0]) 247 | bcd_clock[7:0] <= next_clock[7:0]; 248 | if (!suppressed[1]) 249 | bcd_clock[15:8] <= next_clock[15:8]; 250 | if (!suppressed[2]) 251 | bcd_clock[21:16] <= next_clock[21:16]; 252 | end 253 | if (pre_valid[0]) 254 | bcd_clock[7:0] <= pre_bcd_clock[7:0]; 255 | if (pre_valid[1]) 256 | bcd_clock[15:8] <= pre_bcd_clock[15:8]; 257 | if (pre_valid[2]) 258 | bcd_clock[21:16] <= pre_bcd_clock[21:16]; 259 | end 260 | // }}} 261 | 262 | assign o_data = bcd_clock; 263 | assign o_ppd = (pre_ppd)&&(i_pps); 264 | //////////////////////////////////////////////////////////////////////////////// 265 | //////////////////////////////////////////////////////////////////////////////// 266 | //////////////////////////////////////////////////////////////////////////////// 267 | // 268 | // Formal properties 269 | // {{{ 270 | //////////////////////////////////////////////////////////////////////////////// 271 | //////////////////////////////////////////////////////////////////////////////// 272 | //////////////////////////////////////////////////////////////////////////////// 273 | `ifdef FORMAL 274 | `ifdef RTCBARE 275 | `define ASSUME assume 276 | `define ASSERT assert 277 | `else 278 | `define ASSUME assert 279 | `define ASSERT assert 280 | `endif 281 | 282 | reg f_past_valid; 283 | initial f_past_valid = 1'b0; 284 | always @(posedge i_clk) 285 | f_past_valid <= 1'b1; 286 | 287 | // 288 | always @(*) 289 | begin 290 | `ASSERT(bcd_clock[ 3: 0] <= 4'h9); 291 | `ASSERT(bcd_clock[ 7: 4] <= 4'h5); 292 | `ASSERT(bcd_clock[11: 8] <= 4'h9); 293 | `ASSERT(bcd_clock[15:12] <= 4'h5); 294 | `ASSERT(bcd_clock[19:16] <= 4'h9); 295 | `ASSERT(bcd_clock[21:16] <= 6'h23); 296 | end 297 | 298 | 299 | generate if (OPT_PREVALIDATED_INPUT) 300 | begin : F_ASSUME_VALID_INPUTS 301 | 302 | always @(*) 303 | if (i_wr) 304 | begin 305 | if (i_valid[0]) 306 | begin 307 | `ASSUME(i_data[ 3: 0] <= 4'h9); 308 | `ASSUME(i_data[ 7: 4] <= 4'h5); 309 | end 310 | 311 | if (i_valid[1]) 312 | begin 313 | `ASSUME(i_data[11: 8] <= 4'h9); 314 | `ASSUME(i_data[15:12] <= 4'h5); 315 | end 316 | 317 | if (i_valid[2]) 318 | begin 319 | `ASSUME(i_data[19:16] <= 4'h9); 320 | `ASSUME(i_data[21:16] <= 8'h23); 321 | end 322 | end 323 | 324 | end else begin : F_ASSERT_PREVALIDATED 325 | 326 | always @(*) 327 | if (pre_valid[0]) 328 | begin 329 | `ASSERT(pre_bcd_clock[ 3: 0] <= 4'h9); 330 | `ASSERT(pre_bcd_clock[ 7: 4] <= 4'h5); 331 | end 332 | 333 | always @(*) 334 | if (pre_valid[1]) 335 | begin 336 | `ASSERT(pre_bcd_clock[11: 8] <= 4'h9); 337 | `ASSERT(pre_bcd_clock[15:12] <= 4'h5); 338 | end 339 | 340 | always @(*) 341 | if (pre_valid[2]) 342 | begin 343 | `ASSERT(pre_bcd_clock[19:16] <= 4'h9); 344 | `ASSERT(pre_bcd_clock[21:16] <= 8'h23); 345 | end 346 | 347 | end endgenerate 348 | 349 | always @(*) 350 | begin 351 | `ASSERT(bcd_clock[ 3: 0] <= 4'h9); 352 | `ASSERT(bcd_clock[ 7: 4] <= 4'h5); 353 | `ASSERT(bcd_clock[11: 8] <= 4'h9); 354 | `ASSERT(bcd_clock[15:12] <= 4'h5); 355 | `ASSERT(bcd_clock[19:16] <= 4'h9); 356 | `ASSERT(bcd_clock[21:16] <= 8'h23); 357 | end 358 | 359 | reg [7:0] f_past_pps; 360 | initial f_past_pps = 0; 361 | always @(posedge i_clk) 362 | if (i_reset) 363 | f_past_pps <= 0; 364 | else if (i_pps) 365 | f_past_pps <= 8'hff; 366 | else 367 | f_past_pps <= { f_past_pps[6:0], 1'b0 }; 368 | 369 | always @(*) 370 | if (f_past_pps[7]) 371 | `ASSUME(!i_pps); 372 | 373 | always @(*) 374 | `ASSERT(suppress_count <= 3'h5); 375 | always @(*) 376 | if (suppressed[0]) 377 | `ASSERT(suppressed[1]); 378 | always @(*) 379 | if (suppressed[1]) 380 | `ASSERT(suppressed[2]); 381 | `endif 382 | // }}}} 383 | endmodule 384 | -------------------------------------------------------------------------------- /rtl/rtcclock.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcclock.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core 6 | // 7 | // Purpose: Implement a real time clock, including alarm, count--down 8 | // timer, stopwatch, variable time frequency, and more. 9 | // 10 | // Designed originally with Digilent's Basys3 in mind. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // 41 | `default_nettype none 42 | // }}} 43 | module rtcclock #( 44 | // {{{ 45 | //2af31e = 2^48 / 100e6 MHz 46 | parameter DEFAULT_SPEED = 32'd2814750, // == 2^48/ClkSpd 47 | parameter [0:0] OPT_TIMER = 1'b1, 48 | OPT_STOPWATCH = 1'b1, 49 | OPT_ALARM = 1'b1 50 | // }}} 51 | ) ( 52 | // {{{ 53 | input wire i_clk, i_reset, 54 | // Wishbone interface 55 | input wire i_wb_cyc, i_wb_stb, i_wb_we, 56 | input wire [2:0] i_wb_addr, 57 | input wire [31:0] i_wb_data, 58 | input wire [3:0] i_wb_sel, 59 | // o_wb_ack, o_wb_stb, o_wb_data, // no reads here 60 | // // Button inputs 61 | // input i_btn, 62 | // Output registers 63 | output reg [31:0] o_data, // muxd based on i_wb_addr 64 | // Output controls 65 | output reg [31:0] o_sseg, 66 | output wire [15:0] o_led, 67 | output wire o_interrupt, 68 | // A once-per-day strobe on the last clock of the day 69 | o_ppd, 70 | // Time setting hack(s) 71 | input wire i_hack 72 | // }}} 73 | ); 74 | 75 | // Signal declarations 76 | // {{{ 77 | reg [31:0] ckspeed; 78 | reg [1:0] clock_display; 79 | 80 | wire [31:0] timer_data, alarm_data; 81 | wire [30:0] stopwatch_data; 82 | wire [21:0] clock_data; 83 | wire sp_sel; 84 | reg ck_wr, tm_wr, al_wr; 85 | 86 | wire tm_int, al_int; 87 | 88 | reg [25:0] wr_data; 89 | reg [2:0] wr_valid; 90 | reg wr_zero; 91 | reg ck_carry; 92 | reg [39:0] ck_counter; 93 | wire ck_pps, ck_ppd; 94 | reg ck_prepps, ck_ppm; 95 | reg [7:0] ck_sub; 96 | reg [21:0] ck_last_clock; 97 | wire sw_running; 98 | reg r_hack_carry; 99 | reg [29:0] hack_time; 100 | reg [39:0] hack_counter; 101 | wire tm_alarm; 102 | reg [15:0] h_sseg; 103 | reg [3:1] dmask; 104 | wire [31:0] w_sseg; 105 | wire al_tripped; 106 | reg [17:0] ledreg; 107 | // }}} 108 | 109 | assign sp_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b100)); 110 | 111 | // ck_wr, tm_wr, al_wr 112 | // {{{ 113 | initial { ck_wr, tm_wr, al_wr } = 0; 114 | always @(posedge i_clk) 115 | if (i_reset) 116 | begin 117 | ck_wr <= 1'b0; 118 | tm_wr <= 1'b0; 119 | al_wr <= 1'b0; 120 | end else begin 121 | ck_wr <= ((i_wb_stb)&&(i_wb_addr==3'b000)&&(i_wb_we)); 122 | tm_wr <= ((i_wb_stb)&&(i_wb_addr==3'b001)&&(i_wb_we)); 123 | al_wr <= ((i_wb_stb)&&(i_wb_addr==3'b011)&&(i_wb_we)); 124 | end 125 | // }}} 126 | 127 | // wr_data, wr_valid, wr_zero, clock_display 128 | // {{{ 129 | always @(posedge i_clk) 130 | begin 131 | wr_data <= i_wb_data[25:0]; 132 | wr_valid[0] <= (i_wb_sel[0])&&(i_wb_data[3:0] <= 4'h9) 133 | &&(i_wb_data[7:4] <= 4'h5); 134 | wr_valid[1] <= (i_wb_sel[1])&&(i_wb_data[11:8] <= 4'h9) 135 | &&(i_wb_data[15:12] <= 4'h5); 136 | wr_valid[2] <= (i_wb_sel[2])&&(i_wb_data[19:16] <= 4'h9) 137 | &&(i_wb_data[21:16] <= 6'h23); 138 | wr_zero <= (i_wb_data[23:0] == 0); 139 | 140 | 141 | if((i_wb_stb)&&(i_wb_addr==3'b000)&&(i_wb_we)&&(i_wb_sel[3])) 142 | clock_display <= i_wb_data[25:24]; 143 | end 144 | // }}} 145 | //////////////////////////////////////////////////////////////////////// 146 | // 147 | // Core time generator--generate the once per second pulse 148 | // {{{ 149 | //////////////////////////////////////////////////////////////////////// 150 | // 151 | // 152 | 153 | // ck_carry, ck_counter 154 | // {{{ 155 | initial ck_carry = 1'b0; 156 | initial ck_counter = 40'h00; 157 | always @(posedge i_clk) 158 | { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed }; 159 | // }}} 160 | 161 | assign ck_pps = (ck_carry)&&(ck_prepps); 162 | 163 | // ck_sub, ck_prepps 164 | // {{{ 165 | always @(posedge i_clk) 166 | begin 167 | if (ck_carry) 168 | ck_sub <= ck_sub + 8'h1; 169 | ck_prepps <= (ck_sub == 8'hff); 170 | end 171 | // }}} 172 | 173 | // rtcbare 174 | // {{{ 175 | rtcbare clock(i_clk, i_reset, ck_pps, 176 | ck_wr, wr_data[21:0], wr_valid, clock_data, ck_ppd); 177 | // }}} 178 | 179 | // ck_ppm 180 | // {{{ 181 | always @(posedge i_clk) 182 | ck_ppm <= (clock_data[14:8] == 7'h59); 183 | // }}} 184 | 185 | // ck_last_clock 186 | // {{{ 187 | // Clock updates take several clocks, so let's make sure we 188 | // are only looking at a valid clock value before testing it. 189 | always @(posedge i_clk) 190 | ck_last_clock <= clock_data[21:0]; 191 | // }}} 192 | // }}} 193 | //////////////////////////////////////////////////////////////////////// 194 | // 195 | // Timer 196 | // {{{ 197 | //////////////////////////////////////////////////////////////////////// 198 | // 199 | // 200 | 201 | generate if (OPT_TIMER) 202 | begin : TIMER 203 | 204 | rtctimer #(.LGSUBCK(8)) 205 | timer(i_clk, i_reset, ck_carry, tm_wr, wr_data[24:0], 206 | wr_valid, wr_zero, timer_data, tm_int); 207 | 208 | end else begin : NOTIMER 209 | // {{{ 210 | assign tm_int = 0; 211 | assign timer_data = 0; 212 | 213 | // Make verilator happy 214 | // verilator lint_off UNUSED 215 | wire timer_unused; 216 | assign timer_unused = tm_wr; 217 | // verilator lint_on UNUSED 218 | // }}} 219 | end endgenerate 220 | // }}} 221 | //////////////////////////////////////////////////////////////////////// 222 | // 223 | // Stopwatch 224 | // {{{ 225 | //////////////////////////////////////////////////////////////////////// 226 | // 227 | // 228 | 229 | generate if (OPT_STOPWATCH) 230 | begin 231 | 232 | reg [2:0] sw_ctrl; 233 | initial sw_ctrl = 0; 234 | always @(posedge i_clk) 235 | if (i_reset) 236 | sw_ctrl <= 0; 237 | else if (i_wb_stb && i_wb_we && i_wb_sel[0] && i_wb_addr == 3'b010) 238 | sw_ctrl <= { i_wb_data[1:0], !i_wb_data[0] }; 239 | else 240 | sw_ctrl <= 0; 241 | 242 | rtcstopwatch rtcstop(i_clk, i_reset, ckspeed, 243 | sw_ctrl[2], sw_ctrl[1], sw_ctrl[0], 244 | stopwatch_data, sw_running); 245 | 246 | end else begin 247 | // {{{ 248 | assign stopwatch_data = 0; 249 | assign sw_running = 0; 250 | // }}} 251 | end endgenerate 252 | // }}} 253 | //////////////////////////////////////////////////////////////////////// 254 | // 255 | // Alarm 256 | // {{{ 257 | //////////////////////////////////////////////////////////////////////// 258 | // 259 | // 260 | 261 | generate if (OPT_ALARM) 262 | begin : ALARM 263 | 264 | rtcalarm alarm(i_clk, i_reset, clock_data[21:0], 265 | al_wr, wr_data[25], wr_data[24], wr_data[21:0], 266 | wr_valid[2:0], 267 | alarm_data, al_int); 268 | 269 | 270 | end else begin : NO_ALARM 271 | // {{{ 272 | assign alarm_data = 0; 273 | assign al_int = 0; 274 | // }}} 275 | end endgenerate 276 | // }}} 277 | //////////////////////////////////////////////////////////////////////// 278 | // 279 | // Clock rate control 280 | // {{{ 281 | //////////////////////////////////////////////////////////////////////// 282 | // 283 | // 284 | 285 | // 286 | // The ckspeed register is equal to 2^48 divded by the number of 287 | // clock ticks you expect per second. Adjust high for a slower 288 | // clock, lower for a faster clock. In this fashion, a single 289 | // real time clock RTL file can handle tracking the clock in any 290 | // device. Further, because this is only the lower 32 bits of a 291 | // 48 bit counter per seconds, the clock jitter is kept below 292 | // 1 part in 65 thousand. 293 | // 294 | initial ckspeed = DEFAULT_SPEED; 295 | // In the case of verilator, comment the above and uncomment the line 296 | // below. The clock constant below is "close" to simulation time, 297 | // meaning that my verilator simulation is running about 300x slower 298 | // than board time. 299 | // initial ckspeed = 32'd786432000; 300 | always @(posedge i_clk) 301 | if ((sp_sel)&&(i_wb_we)) 302 | ckspeed <= i_wb_data; 303 | // }}} 304 | //////////////////////////////////////////////////////////////////////// 305 | // 306 | // Time hacks 307 | // {{{ 308 | //////////////////////////////////////////////////////////////////////// 309 | // 310 | // 311 | 312 | // 313 | // If you want very fine precision control over your clock, you need 314 | // to be able to transfer time from one location to another. This 315 | // is the beginning of that means: by setting a wire, i_hack, high 316 | // on a particular input, you can then read (later) what the clock 317 | // time was on that input. 318 | // 319 | // What's missing from this high precision adjustment mechanism is a 320 | // means of actually adjusting this time based upon the time 321 | // difference you measure here between the hack time and some time 322 | // on another clock, but we'll get there. 323 | // 324 | initial hack_time = 30'h0000; 325 | initial hack_counter = 40'h0000; 326 | always @(posedge i_clk) 327 | if (i_hack) 328 | begin 329 | hack_time <= { clock_data[21:0], ck_sub }; 330 | hack_counter <= ck_counter; 331 | r_hack_carry <= ck_carry; 332 | // if ck_carry is set, the clock register is in the 333 | // middle of a two clock update. In that case .... 334 | end else if (r_hack_carry) 335 | begin // update again on the next clock to get the correct hack time. 336 | hack_time <= { clock_data[21:0], ck_sub }; 337 | r_hack_carry <= 1'b0; 338 | end 339 | 340 | assign tm_alarm = timer_data[25]; 341 | // }}} 342 | //////////////////////////////////////////////////////////////////////// 343 | // 344 | // 7-Segment display control 345 | // {{{ 346 | //////////////////////////////////////////////////////////////////////// 347 | // 348 | // 349 | 350 | always @(posedge i_clk) 351 | case(clock_display) 352 | 2'h1: begin 353 | // {{{ 354 | h_sseg <= timer_data[15:0]; 355 | if (tm_alarm) dmask <= 3'h7; 356 | else begin 357 | dmask[3] <= (12'h000 != timer_data[23:12]); // timer[15:12] 358 | dmask[2] <= (16'h000 != timer_data[23: 8]); // timer[11: 8] 359 | dmask[1] <= (20'h000 != timer_data[23: 4]); // timer[ 7: 4] 360 | // dmask[0] <= 1'b1; // Always on 361 | end end 362 | // }}} 363 | 2'h2: begin 364 | // {{{ 365 | h_sseg <= stopwatch_data[19:4]; 366 | dmask[3] <= (12'h00 != stopwatch_data[27:16]); 367 | dmask[2] <= (16'h000 != stopwatch_data[27:12]); 368 | dmask[1] <= 1'b1; // Always on, stopwatch[11:8] 369 | // dmask[0] <= 1'b1; // Always on, stopwatch[7:4] 370 | end 371 | // }}} 372 | 2'h3: begin 373 | // {{{ 374 | h_sseg <= ck_last_clock[15:0]; 375 | dmask[3:1] <= 3'h7; 376 | end 377 | // }}} 378 | default: begin // 4'h0 379 | // {{{ 380 | h_sseg <= { 2'b00, ck_last_clock[21:8] }; 381 | dmask[2:1] <= 2'b11; 382 | dmask[3] <= (2'b00 != ck_last_clock[21:20]); 383 | end 384 | // }}} 385 | endcase 386 | 387 | assign w_sseg[ 0] = (!ck_sub[7]); 388 | assign w_sseg[ 8] = (clock_display == 2'h2); 389 | assign w_sseg[16] = ((clock_display == 2'h0) 390 | &&(!ck_sub[7]))||(clock_display == 2'h3); 391 | assign w_sseg[24] = 1'b0; 392 | hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]); 393 | hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]); 394 | hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]); 395 | hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]); 396 | 397 | assign al_tripped = alarm_data[25]; 398 | 399 | always @(posedge i_clk) 400 | if ((tm_alarm || al_tripped)&&(ck_sub[7])) 401 | // If timer or alarm have tripped, make the display 402 | // blink at 1Hz, 50% duty cycle 403 | o_sseg <= 32'h0000; 404 | else 405 | o_sseg <= { 406 | (dmask[3])?w_sseg[31:24]:8'h00, 407 | (dmask[2])?w_sseg[23:16]:8'h00, 408 | (dmask[1])?w_sseg[15: 8]:8'h00, 409 | w_sseg[ 7: 0] }; 410 | // }}} 411 | //////////////////////////////////////////////////////////////////////// 412 | // 413 | // LED control 414 | // {{{ 415 | //////////////////////////////////////////////////////////////////////// 416 | // 417 | // 418 | 419 | // 420 | // Use the LED's to count up to a minute. 421 | always @(posedge i_clk) 422 | // At the top of any minute, start the led register back at 423 | // zero 424 | if ((ck_pps)&&(ck_ppm)) 425 | ledreg <= 18'h00; 426 | // Otherwise, 256 times a second, add 11 to an 18 bit counter. 427 | else if (ck_carry) 428 | ledreg <= ledreg + 18'h11; 429 | 430 | // The top 8 bits of this counter will form our LED setting. 431 | // Since the Basys3 board has two sets of LED's, we inverse the bottom 432 | // set for a pretty display. 433 | // 434 | // If either alarm or timer have tripped, blink the LED display at 435 | // 1Hz, 50% duty cycle 436 | // 437 | assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}: 438 | { ledreg[17:10], 439 | ledreg[10], ledreg[11], ledreg[12], ledreg[13], 440 | ledreg[14], ledreg[15], ledreg[16], ledreg[17] }; 441 | // }}} 442 | //////////////////////////////////////////////////////////////////////// 443 | // 444 | // Last bits: o_interrupt, and o_data 445 | // {{{ 446 | //////////////////////////////////////////////////////////////////////// 447 | // 448 | // 449 | 450 | 451 | assign o_interrupt = tm_int || al_int; 452 | 453 | // A once-per day strobe, on the last second of the day so that the 454 | // the next clock is the first clock of the day. This is useful for 455 | // connecting this module to a year/month/date date/calendar module. 456 | assign o_ppd = (ck_ppd)&&(ck_pps); 457 | 458 | always @(posedge i_clk) 459 | case(i_wb_addr[2:0]) 460 | 3'b000: o_data <= { 6'h00, clock_display, 2'b00, clock_data[21:0] }; 461 | 3'b001: o_data <= timer_data; 462 | 3'b010: o_data <= { sw_running, stopwatch_data }; 463 | 3'b011: o_data <= alarm_data; 464 | 3'b100: o_data <= ckspeed; 465 | 3'b101: o_data <= { 2'b00, hack_time }; 466 | 3'b110: o_data <= hack_counter[39:8]; 467 | 3'b111: o_data <= { hack_counter[7:0], 24'h00 }; 468 | endcase 469 | // }}} 470 | 471 | // Make verilator hapy 472 | // {{{ 473 | // verilator lint_off UNUSED 474 | wire unused; 475 | assign unused = i_wb_cyc; 476 | // verilator lint_on UNUSED 477 | // }}} 478 | `ifdef FORMAL 479 | // This design has not been formally verified. The section exists 480 | // only as a place holder for such verification when implemented. 481 | always @(*) 482 | assume(ckspeed > 0); 483 | `endif 484 | endmodule 485 | -------------------------------------------------------------------------------- /rtl/rtcdate.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcdate.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core 6 | // 7 | // Purpose: 8 | // This core provides a real-time date function that can be coupled with 9 | // a real-time clock. The date provided is in Binary Coded Decimal (bcd) 10 | // form, and available for reading and writing over the Wishbone Bus. 11 | // 12 | // WARNING: Race conditions exist when updating the date across the Wishbone 13 | // bus at or near midnight. (This should be obvious, but it bears 14 | // stating.) Specifically, if the update command shows up at the same 15 | // clock as the ppd clock, then the ppd clock will be ignored and the 16 | // new date will be the date of the day following midnight. However, 17 | // if the update command shows up one clock before the ppd, then the date 18 | // may be updated, but may have problems dealing with the last day of the 19 | // month or year. To avoid race conditions, update the date sometime 20 | // after the stroke of midnight and before 5 clocks before the next 21 | // midnight. If you are concerned that you might hit a race condition, 22 | // just read the clock again (5+ clocks later) to make certain you set 23 | // it correctly. 24 | // 25 | // 26 | // Creator: Dan Gisselquist, Ph.D. 27 | // Gisselquist Technology, LLC 28 | // 29 | //////////////////////////////////////////////////////////////////////////////// 30 | // }}} 31 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 32 | // {{{ 33 | // This program is free software (firmware): you can redistribute it and/or 34 | // modify it under the terms of the GNU General Public License as published 35 | // by the Free Software Foundation, either version 3 of the License, or (at 36 | // your option) any later version. 37 | // 38 | // This program is distributed in the hope that it will be useful, but WITHOUT 39 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 40 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 41 | // for more details. 42 | // 43 | // You should have received a copy of the GNU General Public License along 44 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 45 | // target there if the PDF file isn't present.) If not, see 46 | // for a copy. 47 | // }}} 48 | // License: GPL, v3, as defined and found on www.gnu.org, 49 | // {{{ 50 | // http://www.gnu.org/licenses/gpl.html 51 | // 52 | // 53 | //////////////////////////////////////////////////////////////////////////////// 54 | // 55 | // 56 | `default_nettype none 57 | // }}} 58 | module rtcdate #( 59 | parameter [29:0] INITIAL_DATE = 30'h20000101 60 | ) ( 61 | // {{{ 62 | input wire i_clk, 63 | // A one part per day signal, i.e. basically a clock enable 64 | // line that controls when the beginning of the day happens. 65 | // This line should be high on the very last second of any day 66 | // in order for the rtcdate module to always have the right 67 | // date. 68 | input wire i_ppd, 69 | // Wishbone inputs 70 | input wire i_wb_cyc, i_wb_stb, i_wb_we, 71 | input wire [31:0] i_wb_data, 72 | input wire [3:0] i_wb_sel, 73 | // Wishbone outputs 74 | output wire o_wb_stall, 75 | output reg o_wb_ack, 76 | output wire [31:0] o_wb_data 77 | // }}} 78 | ); 79 | 80 | // Signal declarations 81 | // {{{ 82 | wire update; 83 | reg [9:0] r_block_updates; 84 | reg [5:0] r_day; 85 | reg [4:0] r_mon; 86 | reg [13:0] r_year; 87 | 88 | reg last_day_of_month, last_day_of_year, is_leap_year; 89 | reg [5:0] days_per_month; 90 | reg year_divisible_by_four, century_year, four_century_year; 91 | reg [5:0] next_day, fixd_day; 92 | reg [4:0] next_mon, fixd_mon; 93 | reg [13:0] next_year; 94 | reg [2:0] next_year_c; 95 | // }}} 96 | 97 | // r_block_updates 98 | // {{{ 99 | initial r_block_updates = 10'h3ff; 100 | always @(posedge i_clk) 101 | if ((i_wb_we)&&(i_wb_stb)) 102 | r_block_updates <= 10'h3ff; 103 | else 104 | r_block_updates <= { r_block_updates[8:0], 1'b0 }; 105 | // }}} 106 | 107 | assign update = (i_ppd)&&(!r_block_updates[9]); 108 | 109 | // days_per_month 110 | // {{{ 111 | initial days_per_month = 6'h31; // Remember, this is BCD 112 | always @(posedge i_clk) 113 | begin // Clock 3 114 | case(r_mon) 115 | 5'h01: days_per_month <= 6'h31; // Jan 116 | 5'h02: days_per_month <= (is_leap_year)? 6'h29:6'h28; 117 | 5'h03: days_per_month <= 6'h31; // March 118 | 5'h04: days_per_month <= 6'h30; // April 119 | 5'h05: days_per_month <= 6'h31; // May 120 | 5'h06: days_per_month <= 6'h30; // June 121 | 5'h07: days_per_month <= 6'h31; // July 122 | 5'h08: days_per_month <= 6'h31; // August 123 | 5'h09: days_per_month <= 6'h30; // Sept 124 | 5'h10: days_per_month <= 6'h31; // October 125 | 5'h11: days_per_month <= 6'h30; // November 126 | 5'h12: days_per_month <= 6'h31; // December 127 | default: days_per_month <= 6'h31; // Invalid month 128 | endcase 129 | end 130 | // }}} 131 | 132 | //////////////////////////////////////////////////////////////////////// 133 | // 134 | // Years 135 | // {{{ 136 | //////////////////////////////////////////////////////////////////////// 137 | // 138 | // 139 | 140 | initial last_day_of_month = 1'b0; 141 | always @(posedge i_clk) // Clock 4 142 | last_day_of_month <= (r_day >= days_per_month); 143 | 144 | initial last_day_of_year = 1'b0; 145 | always @(posedge i_clk) // Clock 5 146 | last_day_of_year <= (last_day_of_month) && (r_mon == 5'h12); 147 | 148 | 149 | initial year_divisible_by_four = 1'b0; 150 | always @(posedge i_clk) // Clock 1 151 | year_divisible_by_four<= ((!r_year[0])&&(r_year[4]==r_year[1])); 152 | 153 | initial century_year = 1'b0; 154 | always @(posedge i_clk) // Clock 1 155 | century_year <= (r_year[7:0] == 8'h00); 156 | 157 | initial four_century_year = 1'b0; 158 | always @(posedge i_clk) // Clock 1 159 | four_century_year <= ((!r_year[8])&&((r_year[12]==r_year[9]))); 160 | 161 | initial is_leap_year = 1'b0; 162 | always @(posedge i_clk) // Clock 2 163 | is_leap_year <= (year_divisible_by_four)&&((!century_year) 164 | ||((century_year)&&(four_century_year))); 165 | 166 | // }}} 167 | //////////////////////////////////////////////////////////////////////// 168 | // 169 | // Days 170 | // {{{ 171 | //////////////////////////////////////////////////////////////////////// 172 | // 173 | // 174 | 175 | // Adjust the day of month 176 | initial next_day = INITIAL_DATE[5:0]; 177 | always @(posedge i_clk) 178 | if (last_day_of_month) 179 | next_day <= 6'h01; 180 | else if (r_day[3:0] != 4'h9) 181 | next_day <= { r_day[5:4], (r_day[3:0]+4'h1) }; 182 | else 183 | next_day <= { (r_day[5:4]+2'h1), 4'h0 }; 184 | 185 | initial fixd_day = INITIAL_DATE[5:0]; 186 | always @(posedge i_clk) 187 | if ((r_day == 0)||(r_day > days_per_month)) 188 | fixd_day <= 6'h01; 189 | else if (r_day[3:0] > 4'h9) 190 | begin 191 | fixd_day[3:0] <= 4'h0; 192 | fixd_day[5:4] <= r_day[5:4] + 1'b1; 193 | end else 194 | fixd_day <= r_day; 195 | 196 | initial r_day = INITIAL_DATE[5:0]; 197 | always @(posedge i_clk) 198 | begin // Depends upon 9 inputs 199 | if (update) 200 | r_day <= next_day; 201 | else if (r_block_updates[5:4] == 2'b10) 202 | r_day <= fixd_day; 203 | 204 | if ((i_wb_stb)&&(i_wb_we)&&(!i_wb_data[7])&&(i_wb_sel[0])) 205 | r_day <= i_wb_data[5:0]; 206 | end 207 | // }}} 208 | //////////////////////////////////////////////////////////////////////// 209 | // 210 | // Months 211 | // {{{ 212 | //////////////////////////////////////////////////////////////////////// 213 | // 214 | // 215 | 216 | // Adjust the month of the year 217 | initial next_mon = 5'h01; 218 | always @(posedge i_clk) 219 | if (last_day_of_year) 220 | next_mon <= 5'h01; 221 | else if ((last_day_of_month)&&(r_mon[3:0] != 4'h9)) 222 | next_mon <= { r_mon[4], (r_mon[3:0] + 4'h1) }; 223 | else if (last_day_of_month) 224 | begin 225 | next_mon[3:0] <= 4'h0; 226 | next_mon[4] <= 1; 227 | end else 228 | next_mon <= r_mon; 229 | 230 | initial fixd_mon = INITIAL_DATE[12:8]; 231 | always @(posedge i_clk) 232 | if ((r_mon == 0)||(r_mon > 5'h12)||(r_mon[3:0] > 4'h9)) 233 | fixd_mon <= 5'h01; 234 | else 235 | fixd_mon <= r_mon; 236 | 237 | initial r_mon = INITIAL_DATE[12:8]; 238 | always @(posedge i_clk) 239 | begin // Depeds upon 9 inputs 240 | if (update) 241 | r_mon <= next_mon; 242 | else if (r_block_updates[8:7] == 2'b10) 243 | r_mon <= fixd_mon; 244 | 245 | if ((i_wb_stb)&&(i_wb_we)&&(!i_wb_data[15])&&(i_wb_sel[1])) 246 | r_mon <= i_wb_data[12:8]; 247 | end 248 | // }}} 249 | //////////////////////////////////////////////////////////////////////// 250 | // 251 | // Years (again) 252 | // {{{ 253 | //////////////////////////////////////////////////////////////////////// 254 | // 255 | // 256 | 257 | // Adjust the year 258 | initial next_year = INITIAL_DATE[29:16]; 259 | initial next_year_c = 0; 260 | always @(posedge i_clk) 261 | begin // Takes 5 clocks to propagate 262 | next_year_c[0] <= (r_year[ 3: 0]>=4'h9); 263 | next_year_c[1] <= (r_year[ 7: 4]>4'h9)||((r_year[ 7: 4]==4'h9)&&(next_year_c[0])); 264 | next_year_c[2] <= (r_year[11: 8]>4'h9)||((r_year[11: 8]==4'h9)&&(next_year_c[1])); 265 | next_year[ 3: 0] <= (next_year_c[0])? 4'h0:(r_year[ 3: 0]+4'h1); 266 | next_year[ 7: 4] <= (next_year_c[1])? 4'h0: 267 | (next_year_c[0])?(r_year[ 7: 4]+4'h1) 268 | : (r_year[7:4]); 269 | next_year[11: 8] <= (next_year_c[2])? 4'h0: 270 | (next_year_c[1])?(r_year[11: 8]+4'h1) 271 | : (r_year[11: 8]); 272 | next_year[13:12] <= (next_year_c[2])?(r_year[13:12]+2'h1):r_year[13:12]; 273 | 274 | 275 | if ((i_wb_stb)&&(i_wb_we)&&(!i_wb_data[31]) 276 | &&(i_wb_sel[3:2]==2'b11)) 277 | next_year_c <= 3'h0; 278 | end 279 | 280 | initial r_year = INITIAL_DATE[29:16]; 281 | always @(posedge i_clk) 282 | begin // 11 inputs 283 | // Deal with any out of bounds conditions 284 | if (r_year[3:0] > 4'h9) 285 | r_year[3:0] <= 4'h0; 286 | if (r_year[7:4] > 4'h9) 287 | r_year[7:4] <= 4'h0; 288 | if (r_year[11:8] > 4'h9) 289 | r_year[11:8] <= 4'h0; 290 | if ((update)&&(last_day_of_year)) 291 | r_year <= next_year; 292 | 293 | if ((i_wb_stb)&&(i_wb_we)&&(!i_wb_data[31]) 294 | &&(i_wb_sel[3:2]==2'b11)) 295 | r_year <= i_wb_data[29:16]; 296 | end 297 | // }}} 298 | //////////////////////////////////////////////////////////////////////// 299 | // 300 | // Bus returns 301 | // {{{ 302 | //////////////////////////////////////////////////////////////////////// 303 | // 304 | // 305 | 306 | initial o_wb_ack = 1'b0; 307 | always @(posedge i_clk) 308 | o_wb_ack <= (i_wb_stb); 309 | 310 | assign o_wb_stall = 1'b0; 311 | assign o_wb_data = { 2'h0, r_year, 3'h0, r_mon, 2'h0, r_day }; 312 | // }}} 313 | 314 | // Make Verilator happy 315 | // {{{ 316 | // verilator lint_off UNUSED 317 | wire unused; 318 | assign unused = &{ 1'b0, i_wb_cyc, i_wb_data[30], i_wb_data[14:13], 319 | i_wb_data[6] }; 320 | // verilator lint_on UNUSED 321 | // }}} 322 | //////////////////////////////////////////////////////////////////////////////// 323 | //////////////////////////////////////////////////////////////////////////////// 324 | //////////////////////////////////////////////////////////////////////////////// 325 | // 326 | // Formal properties 327 | // {{{ 328 | //////////////////////////////////////////////////////////////////////////////// 329 | //////////////////////////////////////////////////////////////////////////////// 330 | //////////////////////////////////////////////////////////////////////////////// 331 | `ifdef FORMAL 332 | reg f_past_valid; 333 | reg [8:0] f_past_ppd; 334 | 335 | initial f_past_valid = 1'b0; 336 | always @(posedge i_clk) 337 | f_past_valid <= 1'b1; 338 | 339 | always @(*) 340 | if (!f_past_valid) 341 | begin 342 | assume(!i_wb_stb); 343 | assume(!i_wb_we); 344 | assume(!i_wb_sel); 345 | assume(!i_ppd); 346 | end 347 | 348 | always @(posedge i_clk) 349 | if (f_past_valid) 350 | assert(o_wb_ack == $past(i_wb_stb)); 351 | 352 | initial f_past_ppd = 8'h00; 353 | always @(posedge i_clk) 354 | if (i_ppd) 355 | f_past_ppd <= 9'h1ff; 356 | else 357 | f_past_ppd <= { f_past_ppd[7:0], 1'b0 }; 358 | 359 | always @(posedge i_clk) 360 | if (|f_past_ppd) 361 | assume(!i_ppd); 362 | 363 | always @(posedge i_clk) 364 | if (!r_block_updates[9]) 365 | begin 366 | assert(r_day[3:0] <= 4'h9); 367 | assert(r_day > 0); 368 | assert(r_day <= days_per_month); 369 | assert(days_per_month > 6'h27); 370 | assert(days_per_month[3:0] <= 4'h9); 371 | if ((f_past_valid)&&(!$past(i_ppd))) 372 | begin 373 | assert((r_mon == 5'h02)|| 374 | (days_per_month == 6'h31)||(days_per_month == 6'h30)); 375 | assert((r_mon != 5'h02)|| 376 | (days_per_month == 6'h28)||(days_per_month == 6'h29)); 377 | end 378 | 379 | if (r_mon[4]) 380 | begin 381 | assert(r_mon[3:2]==0); 382 | assert(r_mon[1:0]!=2'b11); 383 | end else begin 384 | assert(r_mon[3:0]<=4'h9); 385 | end 386 | 387 | assert(r_year[ 3: 0] <= 4'h9); 388 | assert(r_year[ 7: 4] <= 4'h9); 389 | assert(r_year[11: 8] <= 4'h9); 390 | end 391 | `endif 392 | // }}} 393 | endmodule 394 | -------------------------------------------------------------------------------- /rtl/rtcgps.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcgps.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch 6 | // 7 | // Purpose: Implement a real time clock, including alarm, count--down 8 | // timer, stopwatch, variable time frequency, and more. 9 | // 10 | // This particular version has hooks for a GPS 1PPS, as well as a 11 | // finely tracked clock speed output, to allow for fine clock precision 12 | // and good freewheeling even if/when GPS is lost. 13 | // 14 | // 15 | // Creator: Dan Gisselquist, Ph.D. 16 | // Gisselquist Technology, LLC 17 | // 18 | //////////////////////////////////////////////////////////////////////////////// 19 | // }}} 20 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 21 | // {{{ 22 | // This program is free software (firmware): you can redistribute it and/or 23 | // modify it under the terms of the GNU General Public License as published 24 | // by the Free Software Foundation, either version 3 of the License, or (at 25 | // your option) any later version. 26 | // 27 | // This program is distributed in the hope that it will be useful, but WITHOUT 28 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 29 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 30 | // for more details. 31 | // 32 | // You should have received a copy of the GNU General Public License along 33 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 34 | // target there if the PDF file isn't present.) If not, see 35 | // for a copy. 36 | // 37 | // License: GPL, v3, as defined and found on www.gnu.org, 38 | // http://www.gnu.org/licenses/gpl.html 39 | // 40 | // 41 | //////////////////////////////////////////////////////////////////////////////// 42 | // 43 | // 44 | `default_nettype none 45 | // }}} 46 | module rtcgps #( 47 | // {{{ 48 | parameter DEFAULT_SPEED = 32'd2814750, //= 2^48 / CkSpd 49 | parameter [0:0] OPT_TIMER = 1'b1, 50 | parameter [0:0] OPT_STOPWATCH = 1'b1, 51 | parameter [0:0] OPT_ALARM = 1'b1 52 | // }}} 53 | ) ( 54 | // {{{ 55 | input wire i_clk, i_reset, 56 | // 57 | // Wishbone interface 58 | input wire i_wb_cyc, i_wb_stb, i_wb_we, 59 | input wire [1:0] i_wb_addr, 60 | input wire [31:0] i_wb_data, 61 | input wire [3:0] i_wb_sel, 62 | // 63 | output reg o_wb_ack, 64 | output wire o_wb_stall, 65 | output reg [31:0] o_wb_data, 66 | // Output registers 67 | output wire o_interrupt, 68 | // A once-per-day strobe on the last clock of the day 69 | o_ppd, 70 | // GPS interface 71 | input wire i_gps_valid, i_gps_pps, 72 | input wire [31:0] i_gps_ckspeed, 73 | // Our personal timing PPS, for debug purposes 74 | output wire o_rtc_pps 75 | // }}} 76 | ); 77 | 78 | // Signal descriptions 79 | // {{{ 80 | reg [31:0] ckspeed; 81 | 82 | wire [21:0] clock_data; 83 | wire [31:0] timer_data, alarm_data; 84 | wire [30:0] stopwatch_data; 85 | wire sw_running, ck_ppd; 86 | 87 | reg ck_wr, tm_wr, al_wr, wr_zero; 88 | reg [31:0] wr_data; 89 | reg [2:0] wr_valid; 90 | wire tm_int, al_int; 91 | reg [39:0] ck_counter; 92 | reg ck_carry, ck_sub_carry; 93 | wire [7:0] ck_sub; 94 | reg ck_pps; 95 | // }}} 96 | 97 | // ck_wr, tm_wr, al_wr 98 | // {{{ 99 | initial ck_wr = 1'b0; 100 | initial tm_wr = 1'b0; 101 | initial al_wr = 1'b0; 102 | always @(posedge i_clk) 103 | if (i_reset) 104 | begin 105 | ck_wr <= 1'b0; 106 | tm_wr <= 1'b0; 107 | al_wr <= 1'b0; 108 | end else begin 109 | ck_wr <= ((i_wb_stb)&&(i_wb_addr==2'b00)&&(i_wb_we)); 110 | tm_wr <= ((i_wb_stb)&&(i_wb_addr==2'b01)&&(i_wb_we)); 111 | //sw_wr<=((i_wb_stb)&&(i_wb_addr==2'b10)&&(i_wb_we)); 112 | al_wr <= ((i_wb_stb)&&(i_wb_addr==2'b11)&&(i_wb_we)); 113 | end 114 | // }}} 115 | 116 | // wr_data, wr_valid, wr_zero 117 | // {{{ 118 | always @(posedge i_clk) 119 | begin 120 | wr_data <= i_wb_data; 121 | wr_valid[0] <= (i_wb_sel[0])&&(i_wb_data[3:0] <= 4'h9) 122 | &&(i_wb_data[7:4] <= 4'h5); 123 | wr_valid[1] <= (i_wb_sel[1])&&(i_wb_data[11:8] <= 4'h9) 124 | &&(i_wb_data[15:12] <= 4'h5); 125 | wr_valid[2] <= (i_wb_sel[2])&&(i_wb_data[19:16] <= 4'h9) 126 | &&(i_wb_data[21:16] <= 6'h23); 127 | wr_zero <= (i_wb_data[23:0]==0); 128 | end 129 | // }}} 130 | //////////////////////////////////////////////////////////////////////// 131 | // 132 | // The bare clock 133 | // {{{ 134 | //////////////////////////////////////////////////////////////////////// 135 | // 136 | // 137 | rtcbare clock(i_clk, i_reset, ck_pps, 138 | ck_wr, wr_data[21:0], wr_valid, clock_data, ck_ppd); 139 | // }}} 140 | //////////////////////////////////////////////////////////////////////// 141 | // 142 | // Timer 143 | // {{{ 144 | //////////////////////////////////////////////////////////////////////// 145 | // 146 | // 147 | 148 | generate if (OPT_TIMER) 149 | begin 150 | rtctimer #(.LGSUBCK(8)) 151 | timer(i_clk, i_reset, ck_sub_carry, 152 | tm_wr, wr_data[24:0], 153 | wr_valid, wr_zero, timer_data, tm_int); 154 | end else begin 155 | assign tm_int = 0; 156 | assign timer_data = 0; 157 | end endgenerate 158 | // }}} 159 | //////////////////////////////////////////////////////////////////////// 160 | // 161 | // Stopwatch 162 | // {{{ 163 | //////////////////////////////////////////////////////////////////////// 164 | // 165 | // 166 | 167 | generate if (OPT_STOPWATCH) 168 | begin 169 | reg [2:0] sw_ctrl; 170 | 171 | initial sw_ctrl = 0; 172 | always @(posedge i_clk) 173 | if (i_reset) 174 | sw_ctrl <= 0; 175 | else if (i_wb_stb && i_wb_sel[0] && i_wb_addr == 2'b10) 176 | sw_ctrl <= { i_wb_data[1:0], !i_wb_data[0] }; 177 | else 178 | sw_ctrl <= 0; 179 | 180 | rtcstopwatch rtcstop(i_clk, i_reset, ckspeed, 181 | sw_ctrl[2], sw_ctrl[1], sw_ctrl[0], 182 | stopwatch_data, sw_running); 183 | 184 | end else begin 185 | 186 | assign stopwatch_data = 0; 187 | assign sw_running = 0; 188 | 189 | end endgenerate 190 | // }}} 191 | //////////////////////////////////////////////////////////////////////// 192 | // 193 | // Alarm 194 | // {{{ 195 | //////////////////////////////////////////////////////////////////////// 196 | // 197 | // 198 | 199 | generate if (OPT_ALARM) 200 | begin 201 | 202 | rtcalarm alarm(i_clk, i_reset, clock_data[21:0], 203 | al_wr, wr_data[25], wr_data[24], wr_data[21:0], 204 | wr_valid, alarm_data, al_int); 205 | end else begin 206 | 207 | assign alarm_data = 0; 208 | assign al_int = 0; 209 | 210 | end endgenerate 211 | // }}} 212 | //////////////////////////////////////////////////////////////////////// 213 | // 214 | // Sub-second tracking 215 | // {{{ 216 | //////////////////////////////////////////////////////////////////////// 217 | // 218 | // 219 | 220 | initial ck_carry = 1'b0; 221 | initial ck_sub_carry = 1'b0; 222 | initial ck_counter = 0; 223 | always @(posedge i_clk) 224 | if (i_reset) 225 | begin 226 | ck_counter <= 0; 227 | ck_carry <= 1'b0; 228 | ck_sub_carry <= 1'b0; 229 | end else if ((i_gps_valid)&&(i_gps_pps)) 230 | begin 231 | ck_carry <= 0; 232 | // Start our counter 2 clocks into the future. 233 | // Why? Because if we hit the PPS, we'll be delayed 234 | // one clock from true time. This (hopefully) locks 235 | // us back onto true time. Further, if we end up 236 | // off (i.e., go off before the GPS tick ...) then 237 | // the GPS tick will put us back on track ... likewise 238 | // we've got code following that should keep us from 239 | // ever producing two PPS's per second. 240 | ck_counter <= { 7'h00, ckspeed, 1'b0 }; 241 | ck_sub_carry <= ckspeed[31]; 242 | 243 | end else begin 244 | 245 | { ck_sub_carry, ck_counter[31:0] } 246 | <= ck_counter[31:0] + ckspeed; 247 | { ck_carry, ck_counter[39:32] } 248 | <= ck_counter[39:32] + { 7'h0, ck_sub_carry }; 249 | end 250 | 251 | assign ck_sub = ck_counter[39:32]; 252 | 253 | always @(posedge i_clk) 254 | if ((i_gps_pps)&&(i_gps_valid)&&(ck_sub[7])) 255 | // If the GPS is ahead of us, jump forward and set 256 | // the PPS high 257 | ck_pps <= 1'b1; 258 | else if ((ck_carry)&&(ck_sub == 8'h00)) 259 | // Otherwise, if there is no GPS, or if the GPS is 260 | // late, then set the ck_pps on the roll over of 261 | // ck_sub 262 | ck_pps <= 1'b1; 263 | else 264 | // in all other cases, ck_pps should be zero. It's a 265 | // strobe signal that should only (if ever) be true 266 | // for a single clock cycle per second 267 | ck_pps <= 1'b0; 268 | // }}} 269 | //////////////////////////////////////////////////////////////////////// 270 | // 271 | // Clock speed 272 | // {{{ 273 | //////////////////////////////////////////////////////////////////////// 274 | // 275 | // 276 | 277 | // 278 | // The ckspeed register is equal to 2^48 divded by the number of 279 | // clock ticks you expect per second. Adjust high for a slower 280 | // clock, lower for a faster clock. In this fashion, a single 281 | // real time clock RTL file can handle tracking the clock in any 282 | // device. Further, because this is only the lower 32 bits of a 283 | // 48 bit counter per seconds, the clock jitter is kept below 284 | // 1 part in 65 thousand. 285 | // 286 | initial ckspeed = DEFAULT_SPEED; 287 | always @(posedge i_clk) 288 | if (i_gps_valid) 289 | ckspeed <= i_gps_ckspeed; 290 | // }}} 291 | //////////////////////////////////////////////////////////////////////// 292 | // 293 | // o_interrupt and bus responses 294 | // {{{ 295 | //////////////////////////////////////////////////////////////////////// 296 | // 297 | // 298 | 299 | assign o_interrupt = tm_int || al_int; 300 | 301 | // A once-per day strobe, on the last second of the day so that the 302 | // the next clock is the first clock of the day. This is useful for 303 | // connecting this module to a year/month/date date/calendar module. 304 | assign o_ppd = (ck_ppd)&&(ck_pps); 305 | 306 | // o_wb_data 307 | // {{{ 308 | initial o_wb_data = 0; 309 | always @(posedge i_clk) 310 | case(i_wb_addr) 311 | 2'b00: o_wb_data <= { !i_gps_valid, 7'h0, 2'b00,clock_data[21:0] }; 312 | 2'b01: o_wb_data <= timer_data; 313 | 2'b10: o_wb_data <= { sw_running, stopwatch_data }; 314 | 2'b11: o_wb_data <= alarm_data; 315 | endcase 316 | // }}} 317 | 318 | // o_wb_ack 319 | // {{{ 320 | initial o_wb_ack = 0; 321 | always @(posedge i_clk) 322 | if (i_reset) 323 | o_wb_ack <= 0; 324 | else 325 | o_wb_ack <= i_wb_stb; 326 | // }}} 327 | 328 | assign o_wb_stall = 0; 329 | // }}} 330 | 331 | assign o_rtc_pps = ck_pps; 332 | 333 | // Make verilator happy 334 | // {{{ 335 | // verilator lint_off UNUSED 336 | wire unused; 337 | assign unused = &{ 1'b0, i_wb_cyc, wr_data[31:26], i_wb_sel[3] }; 338 | // verilator lint_on UNUSED 339 | // }}} 340 | `ifdef FORMAL 341 | `ifdef RTCGPS 342 | `define ASSUME assume 343 | `define ASSERT assert 344 | `else 345 | `define ASSUME assert 346 | `define ASSERT assume 347 | `endif 348 | 349 | always @(*) 350 | `ASSUME(i_gps_ckspeed >0); 351 | always @(*) 352 | `ASSUME(!i_gps_ckspeed[31]); 353 | 354 | // reg f_past_valid; 355 | // initial f_past_valid = 1'b0; 356 | // always @(posedge i_clk) 357 | // f_past_valid <= 1'b1; 358 | 359 | `endif 360 | endmodule 361 | -------------------------------------------------------------------------------- /rtl/rtclight.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtclight.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core 6 | // 7 | // Purpose: Implement a real time clock, including alarm, count--down 8 | // timer, stopwatch, variable time frequency, and more. 9 | // 10 | // This is a light-weight version of the RTC found in this directory. 11 | // Unlike the full RTC, this version does not support time hacks, seven 12 | // segment display outputs, or LED's. It is an RTC for an internal core 13 | // only. (That's how I was using it on one of my projects anyway ...) 14 | // 15 | // 16 | // Creator: Dan Gisselquist, Ph.D. 17 | // Gisselquist Technology, LLC 18 | // 19 | //////////////////////////////////////////////////////////////////////////////// 20 | // }}} 21 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 22 | // {{{ 23 | // This program is free software (firmware): you can redistribute it and/or 24 | // modify it under the terms of the GNU General Public License as published 25 | // by the Free Software Foundation, either version 3 of the License, or (at 26 | // your option) any later version. 27 | // 28 | // This program is distributed in the hope that it will be useful, but WITHOUT 29 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 30 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 31 | // for more details. 32 | // 33 | // You should have received a copy of the GNU General Public License along 34 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 35 | // target there if the PDF file isn't present.) If not, see 36 | // for a copy. 37 | // }}} 38 | // License: GPL, v3, as defined and found on www.gnu.org, 39 | // {{{ 40 | // http://www.gnu.org/licenses/gpl.html 41 | // 42 | // 43 | //////////////////////////////////////////////////////////////////////////////// 44 | // 45 | // 46 | `default_nettype none 47 | // }}} 48 | module rtclight #( 49 | // {{{ 50 | parameter DEFAULT_SPEED = 32'd2814750, // 100 Mhz 51 | parameter [0:0] OPT_TIMER = 1'b1, 52 | parameter [0:0] OPT_STOPWATCH = 1'b1, 53 | parameter [0:0] OPT_ALARM = 1'b1, 54 | parameter [0:0] OPT_FIXED_SPEED = 1'b1 55 | // }}} 56 | ) ( 57 | // {{{ 58 | input wire i_clk, i_reset, 59 | // Wishbone interface 60 | input wire i_wb_cyc, i_wb_stb, i_wb_we, 61 | input wire [2:0] i_wb_addr, 62 | input wire [31:0] i_wb_data, 63 | input wire [3:0] i_wb_sel, 64 | // 65 | output wire o_wb_stall, 66 | output reg o_wb_ack, 67 | output reg [31:0] o_wb_data, 68 | // Output controls 69 | output wire o_interrupt, 70 | // A once-per-second strobe 71 | o_pps, 72 | // A once-per-day strobe on the last clock of the day 73 | o_ppd 74 | // }}} 75 | ); 76 | 77 | // Signal declarations 78 | // {{{ 79 | reg [31:0] ckspeed; 80 | 81 | wire [21:0] clock_data; 82 | wire [31:0] timer_data, alarm_data; 83 | wire [30:0] stopwatch_data; 84 | wire sw_running; 85 | 86 | reg ck_wr, tm_wr, al_wr, wr_zero; 87 | reg [31:0] wr_data; 88 | reg [2:0] wr_valid; 89 | wire tm_int, al_int; 90 | 91 | reg ck_carry; 92 | reg [39:0] ck_counter; 93 | wire ck_pps, ck_ppd; 94 | reg ck_prepps; 95 | reg [7:0] ck_sub; 96 | wire sp_sel; 97 | // }}} 98 | 99 | // ck_wr, tm_wr, al_wr 100 | // {{{ 101 | initial ck_wr = 1'b0; 102 | initial tm_wr = 1'b0; 103 | initial al_wr = 1'b0; 104 | always @(posedge i_clk) 105 | if (i_reset) 106 | begin 107 | ck_wr <= 1'b0; 108 | tm_wr <= 1'b0; 109 | al_wr <= 1'b0; 110 | end else begin 111 | ck_wr <= ((i_wb_stb)&&(i_wb_addr==3'b000)&&(i_wb_we)); 112 | tm_wr <= ((i_wb_stb)&&(i_wb_addr==3'b001)&&(i_wb_we)); 113 | //sw_wr<=((i_wb_stb)&&(i_wb_addr==3'b010)&&(i_wb_we)); 114 | al_wr <= ((i_wb_stb)&&(i_wb_addr==3'b011)&&(i_wb_we)); 115 | end 116 | // }}} 117 | 118 | // wr_data, wr_valid, wr_zero 119 | // {{{ 120 | always @(posedge i_clk) 121 | begin 122 | wr_data <= i_wb_data; 123 | wr_valid[0] <= (i_wb_sel[0])&&(i_wb_data[3:0] <= 4'h9) 124 | &&(i_wb_data[7:4] <= 4'h5); 125 | wr_valid[1] <= (i_wb_sel[1])&&(i_wb_data[11:8] <= 4'h9) 126 | &&(i_wb_data[15:12] <= 4'h5); 127 | wr_valid[2] <= (i_wb_sel[2])&&(i_wb_data[19:16] <= 4'h9) 128 | &&(i_wb_data[21:16] <= 6'h23); 129 | wr_zero <= (i_wb_data[23:0]==0); 130 | end 131 | // }}} 132 | //////////////////////////////////////////////////////////////////////// 133 | // 134 | // Sub-clock handling, PPS generation 135 | // {{{ 136 | //////////////////////////////////////////////////////////////////////// 137 | // 138 | 139 | initial ck_carry = 1'b0; 140 | initial ck_counter = 40'h00; 141 | always @(posedge i_clk) 142 | { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed }; 143 | 144 | assign ck_pps = (ck_carry)&&(ck_prepps); 145 | assign o_pps = ck_pps; 146 | 147 | always @(posedge i_clk) 148 | begin 149 | if (ck_carry) 150 | ck_sub <= ck_sub + 8'h1; 151 | ck_prepps <= (ck_sub == 8'hff); 152 | end 153 | // }}} 154 | //////////////////////////////////////////////////////////////////////// 155 | // 156 | // Bare clock 157 | // {{{ 158 | //////////////////////////////////////////////////////////////////////// 159 | // 160 | // 161 | rtcbare clock(i_clk, i_reset, ck_pps, 162 | ck_wr, wr_data[21:0], wr_valid, clock_data, ck_ppd); 163 | // }}} 164 | //////////////////////////////////////////////////////////////////////// 165 | // 166 | // Timer 167 | // {{{ 168 | //////////////////////////////////////////////////////////////////////// 169 | // 170 | // 171 | generate if (OPT_TIMER) 172 | begin 173 | rtctimer #(.LGSUBCK(8)) 174 | timer(i_clk, i_reset, ck_carry, 175 | tm_wr, wr_data[24:0], 176 | wr_valid, wr_zero, timer_data, tm_int); 177 | end else begin 178 | assign tm_int = 0; 179 | assign timer_data = 0; 180 | 181 | // Verilator lint_off UNUSED 182 | wire unused_timer; 183 | assign unused_timer = tm_wr; 184 | // Verilator lint_on UNUSED 185 | end endgenerate 186 | // }}} 187 | //////////////////////////////////////////////////////////////////////// 188 | // 189 | // Stopwatch 190 | // {{{ 191 | //////////////////////////////////////////////////////////////////////// 192 | // 193 | // 194 | 195 | generate if (OPT_STOPWATCH) 196 | begin 197 | reg [2:0] sw_ctrl; 198 | 199 | initial sw_ctrl = 0; 200 | always @(posedge i_clk) 201 | if (i_reset) 202 | sw_ctrl <= 0; 203 | else if (i_wb_stb && i_wb_we && i_wb_sel[0] && i_wb_addr == 3'b010) 204 | sw_ctrl <= { i_wb_data[1:0], !i_wb_data[0] }; 205 | else 206 | sw_ctrl <= 0; 207 | 208 | rtcstopwatch rtcstop(i_clk, i_reset, ckspeed, 209 | sw_ctrl[2], sw_ctrl[1], sw_ctrl[0], 210 | stopwatch_data, sw_running); 211 | 212 | end else begin 213 | 214 | assign stopwatch_data = 0; 215 | assign sw_running = 0; 216 | 217 | end endgenerate 218 | // }}} 219 | //////////////////////////////////////////////////////////////////////// 220 | // 221 | // Alarm 222 | // {{{ 223 | //////////////////////////////////////////////////////////////////////// 224 | // 225 | // 226 | 227 | generate if (OPT_ALARM) 228 | begin 229 | 230 | rtcalarm alarm(i_clk, i_reset, clock_data[21:0], 231 | al_wr, wr_data[25], wr_data[24], wr_data[21:0], 232 | wr_valid, alarm_data, al_int); 233 | end else begin 234 | 235 | assign alarm_data = 0; 236 | assign al_int = 0; 237 | 238 | // Verilator lint_off UNUSED 239 | wire unused_alarm; 240 | assign unused_alarm = al_wr; 241 | // Verilator lint_on UNUSED 242 | end endgenerate 243 | // }}} 244 | //////////////////////////////////////////////////////////////////////// 245 | // 246 | // Clock speedx control 247 | // {{{ 248 | //////////////////////////////////////////////////////////////////////// 249 | // 250 | // 251 | 252 | // 253 | // The ckspeed register is equal to 2^48 divded by the number of 254 | // clock ticks you expect per second. Adjust high for a slower 255 | // clock, lower for a faster clock. In this fashion, a single 256 | // real time clock RTL file can handle tracking the clock in any 257 | // device. Further, because this is only the lower 32 bits of a 258 | // 48 bit counter per seconds, the clock jitter is kept below 259 | // 1 part in 65 thousand. 260 | generate if (!OPT_FIXED_SPEED) 261 | begin : ADJUSTABLE_CLOCK_RATE 262 | 263 | assign sp_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b100)); 264 | 265 | initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz 266 | always @(posedge i_clk) 267 | if ((sp_sel)&&(i_wb_we)) 268 | ckspeed <= i_wb_data; 269 | 270 | end else begin : FIXED_CLOCK_DIVIDER 271 | 272 | assign sp_sel = 0; 273 | always @(*) 274 | ckspeed = DEFAULT_SPEED; 275 | 276 | end endgenerate 277 | // }}} 278 | //////////////////////////////////////////////////////////////////////// 279 | // 280 | // Bus returns 281 | // {{{ 282 | //////////////////////////////////////////////////////////////////////// 283 | // 284 | // 285 | 286 | assign o_wb_stall = 1'b0; 287 | 288 | initial o_wb_ack = 0; 289 | always @(posedge i_clk) 290 | if (i_reset) 291 | o_wb_ack <= 1'b0; 292 | else 293 | o_wb_ack <= i_wb_stb; 294 | 295 | always @(posedge i_clk) 296 | case(i_wb_addr[2:0]) 297 | 3'b000: o_wb_data <= { 10'h0, clock_data }; 298 | 3'b001: o_wb_data <= timer_data; 299 | 3'b010: o_wb_data <= { sw_running, stopwatch_data }; 300 | 3'b011: o_wb_data <= alarm_data; 301 | 3'b100: o_wb_data <= ckspeed; 302 | default: o_wb_data <= 32'h000; 303 | endcase 304 | // }}} 305 | 306 | // o_ppd 307 | // {{{ 308 | // A once-per day strobe, on the last second of the day so that the 309 | // the next clock is the first clock of the day. This is useful for 310 | // connecting this module to a year/month/date date/calendar module. 311 | assign o_ppd = (ck_ppd); 312 | // }}} 313 | 314 | assign o_interrupt = tm_int || al_int; 315 | 316 | 317 | // Make verilator hapy 318 | // {{{ 319 | // verilator lint_off UNUSED 320 | wire unused; 321 | assign unused = &{ 1'b0, sp_sel, i_wb_cyc, wr_data[31:25], i_wb_sel[3] }; 322 | // verilator lint_on UNUSED 323 | // }}} 324 | `ifdef FORMAL 325 | // 326 | `ifdef RTCLIGHT 327 | `define ASSUME assume 328 | `define ASSERT assert 329 | `else 330 | `define ASSUME assert 331 | `define ASSERT assume 332 | `endif 333 | 334 | always @(*) 335 | if ((sp_sel)&&(i_wb_we)) 336 | `ASSUME(i_wb_data > 0); 337 | 338 | `endif 339 | endmodule 340 | -------------------------------------------------------------------------------- /rtl/rtcstopwatch.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtcstopwatch.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch 6 | // 7 | // Purpose: Implement a stop watch in BCD. 8 | // 9 | // Creator: Dan Gisselquist, Ph.D. 10 | // Gisselquist Technology, LLC 11 | // 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // }}} 14 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 15 | // {{{ 16 | // This program is free software (firmware): you can redistribute it and/or 17 | // modify it under the terms of the GNU General Public License as published 18 | // by the Free Software Foundation, either version 3 of the License, or (at 19 | // your option) any later version. 20 | // 21 | // This program is distributed in the hope that it will be useful, but WITHOUT 22 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 23 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 24 | // for more details. 25 | // 26 | // You should have received a copy of the GNU General Public License along 27 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 28 | // target there if the PDF file isn't present.) If not, see 29 | // for a copy. 30 | // }}} 31 | // License: GPL, v3, as defined and found on www.gnu.org, 32 | // {{{ 33 | // http://www.gnu.org/licenses/gpl.html 34 | // 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // 39 | `default_nettype none 40 | // }}} 41 | module rtcstopwatch( 42 | // {{{ 43 | input wire i_clk, i_reset, 44 | // 45 | input wire [31:0] i_ckstep, 46 | input wire i_clear, i_start, i_stop, 47 | output wire [30:0] o_value, 48 | output wire o_running 49 | // }}} 50 | ); 51 | 52 | // Signal declarations 53 | // {{{ 54 | reg [30:0] counter; 55 | reg [45:0] sw_subticks; 56 | reg [36:0] sw_step; 57 | reg [13:0] last_step; 58 | reg [6:0] sw_carry; 59 | reg sw_ppms, carry, sw_running; 60 | reg [30:0] next_sw; 61 | // }}} 62 | 63 | // i_ckstep 64 | // {{{ 65 | // i_ckstep is the bottom 32 bits of a 48 counter step that rolls over 66 | // once per second. If we multiply by 100, we'll then have a 48 bit 67 | // counter step that will roll over once every 10 milliseconds. 68 | // The bottom two of those bits are always zero, so they can be 69 | // dropped. This will give us a 46 bit step. 70 | always @(posedge i_clk) 71 | sw_step <= { 1'b0, i_ckstep, 4'h0 } 72 | + { 2'b0, i_ckstep, 3'h0 } 73 | + { 5'h0, i_ckstep }; 74 | // }}} 75 | 76 | always @(posedge i_clk) 77 | last_step <= sw_step[36:23]; 78 | 79 | // sw_ppms, sw_subticks, carry 80 | // {{{ 81 | initial sw_ppms = 0; 82 | initial sw_subticks = 0; 83 | initial carry = 0; 84 | always @(posedge i_clk) 85 | if (i_reset) 86 | { sw_ppms, carry, sw_subticks } <= 0; 87 | else if ((i_start)||((sw_running)&&(!i_stop))) 88 | begin 89 | { carry, sw_subticks[22:0] } 90 | <= sw_subticks[22:0] + sw_step[22:0]; 91 | { sw_ppms, sw_subticks[45:23] } <= 92 | sw_subticks[45:23] 93 | + {{(9){1'b0}}, last_step[13:0]} 94 | + {{(23){1'b0}}, carry }; 95 | end else 96 | sw_ppms <= 1'b0; 97 | // }}} 98 | 99 | // 100 | // Stopwatch functionality 101 | // 102 | // Setting bit '0' starts the stop watch, clearing it stops it. 103 | // Writing to the register with bit '1' high will clear the stopwatch, 104 | // and return it to zero provided that the stopwatch is stopped either 105 | // before or after the write. Hence, writing a '2' to the device 106 | // will always stop and clear it, whereas writing a '3' to the device 107 | // will only clear it if it was already stopped. 108 | // 109 | 110 | // next_sw 111 | // {{{ 112 | initial next_sw = 0; 113 | always @(posedge i_clk) 114 | if (i_reset || i_clear) 115 | begin 116 | sw_carry <= 0; 117 | next_sw <= 0; 118 | end else begin 119 | sw_carry[0] <= (counter[ 3: 0] >= 4'h9); 120 | sw_carry[1] <= (counter[ 7: 4] >= 4'h9) && (sw_carry[0]); 121 | sw_carry[2] <= (counter[11: 8] >= 4'h9) && (&sw_carry[1]); 122 | sw_carry[3] <= (counter[14:12] >= 3'h5) && (&sw_carry[2]); 123 | sw_carry[4] <= (counter[19:16] >= 4'h9) && (&sw_carry[3]); 124 | sw_carry[5] <= (counter[22:20] >= 3'h5) && (&sw_carry[4]); 125 | sw_carry[6] <= (counter[27:24] >= 4'h9) && (&sw_carry[5]); 126 | 127 | // Tens of Milliseconds 128 | if (sw_carry[0]) 129 | next_sw[3:0] <= 0; 130 | else 131 | next_sw[3:0] <= counter[3:0] + 4'h1; 132 | 133 | if (sw_carry[1]) 134 | next_sw[7:4] <= 0; 135 | else if (sw_carry[0]) 136 | next_sw[7:4] <= counter[7:4] + 4'h1; 137 | else 138 | next_sw[7:4] <= counter[7:4]; 139 | 140 | // Seconds 141 | if (sw_carry[2]) 142 | next_sw[11:8] <= 0; 143 | else if (sw_carry[1]) 144 | next_sw[11:8] <= counter[11:8] + 4'h1; 145 | else 146 | next_sw[11:8] <= counter[11:8]; 147 | 148 | if (sw_carry[3]) 149 | next_sw[14:12] <= 0; 150 | else if (sw_carry[2]) 151 | next_sw[14:12] <= counter[14:12] + 3'h1; 152 | else 153 | next_sw[14:12] <= counter[14:12]; 154 | next_sw[15] <= 1'b0; 155 | 156 | // Minute 157 | if (sw_carry[4]) 158 | next_sw[19:16] <= 0; 159 | else if (sw_carry[3]) 160 | next_sw[19:16] <= counter[19:16] + 4'h1; 161 | else 162 | next_sw[19:16] <= counter[19:16]; 163 | 164 | if (sw_carry[5]) 165 | next_sw[22:20] <= 0; 166 | else if (sw_carry[4]) 167 | next_sw[22:20] <= counter[22:20] + 3'h1; 168 | else 169 | next_sw[22:20] <= counter[22:20]; 170 | next_sw[23] <= 1'b0; 171 | 172 | // Hour 173 | if (sw_carry[6]) 174 | next_sw[27:24] <= 0; 175 | else if (sw_carry[5]) 176 | next_sw[27:24] <= counter[27:24] + 4'h1; 177 | else 178 | next_sw[27:24] <= counter[27:24]; 179 | 180 | if (sw_carry[6]) 181 | next_sw[30:28] <= counter[30:28] + 1'b1; 182 | end 183 | // }}} 184 | 185 | // counter 186 | // {{{ 187 | initial counter = 31'h00000; 188 | always @(posedge i_clk) 189 | if (i_reset || i_clear) 190 | counter <= 0; 191 | else if ((sw_ppms)&&(sw_running)) 192 | counter <= next_sw; 193 | // }}} 194 | 195 | // sw_running 196 | // {{{ 197 | initial sw_running = 0; 198 | always @(posedge i_clk) 199 | if (i_reset || i_stop) 200 | sw_running <= 1'b0; 201 | else if (i_start) 202 | sw_running <= 1'b1; 203 | // }}} 204 | 205 | assign o_value = counter; 206 | assign o_running = sw_running; 207 | 208 | // Make verilator happy 209 | // {{{ 210 | // verilator lint_off UNUSED 211 | wire unused; 212 | assign unused = &{ 1'b0, sw_step[2:0] }; 213 | // verilator lint_on UNUSED 214 | // }}} 215 | //////////////////////////////////////////////////////////////////////////////// 216 | //////////////////////////////////////////////////////////////////////////////// 217 | //////////////////////////////////////////////////////////////////////////////// 218 | // 219 | // Formal properties 220 | // {{{ 221 | //////////////////////////////////////////////////////////////////////////////// 222 | //////////////////////////////////////////////////////////////////////////////// 223 | //////////////////////////////////////////////////////////////////////////////// 224 | `ifdef FORMAL 225 | `ifdef STOPWATCH 226 | `define ASSUME assume 227 | `define ASSERT assert 228 | `else 229 | `define ASSUME assert 230 | `define ASSERT assume 231 | `endif 232 | 233 | reg f_past_valid; 234 | initial f_past_valid = 1'b0; 235 | always @(posedge i_clk) 236 | f_past_valid <= 1'b1; 237 | 238 | always @(*) 239 | `ASSUME(i_ckstep > 0); 240 | 241 | initial `ASSUME(!i_clear); 242 | initial `ASSUME(!i_start); 243 | initial `ASSUME(!i_stop); 244 | 245 | always @(posedge i_clk) 246 | if ((!f_past_valid)||($past(i_reset))) 247 | begin 248 | `ASSERT(counter == 0); 249 | `ASSERT(!sw_running); 250 | end else if ($past(i_clear)) 251 | `ASSERT(counter == 0); 252 | else if (!$past(sw_running)) 253 | `ASSERT($stable(counter)); 254 | 255 | always @(*) 256 | begin 257 | // Tens of Milliseconds 258 | `ASSERT(counter[ 3: 0] <= 4'h9); 259 | `ASSERT(counter[ 7: 4] <= 4'h9); 260 | // Seconds 261 | `ASSERT(counter[11: 8] <= 4'h9); 262 | `ASSERT(counter[15:12] <= 4'h5); 263 | // Minutes 264 | `ASSERT(counter[19:16] <= 4'h9); 265 | `ASSERT(counter[23:20] <= 4'h5); 266 | // Hours 267 | `ASSERT(counter[27:24] <= 4'h9); 268 | end 269 | 270 | always @(*) 271 | if (sw_subticks[45:37] != 0) 272 | `ASSUME(!sw_ppms); 273 | 274 | always @(posedge i_clk) 275 | if ((f_past_valid)&&($past(sw_ppms))) 276 | `ASSERT(!sw_ppms); 277 | 278 | `endif 279 | // }}} 280 | endmodule 281 | -------------------------------------------------------------------------------- /rtl/rtctimer.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtctimer.v 4 | // {{{ 5 | // Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch 6 | // 7 | // Purpose: Implements a count down timer 8 | // 9 | // 10 | // Creator: Dan Gisselquist, Ph.D. 11 | // Gisselquist Technology, LLC 12 | // 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // }}} 15 | // Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | // {{{ 17 | // This program is free software (firmware): you can redistribute it and/or 18 | // modify it under the terms of the GNU General Public License as published 19 | // by the Free Software Foundation, either version 3 of the License, or (at 20 | // your option) any later version. 21 | // 22 | // This program is distributed in the hope that it will be useful, but WITHOUT 23 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | // for more details. 26 | // 27 | // You should have received a copy of the GNU General Public License along 28 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | // target there if the PDF file isn't present.) If not, see 30 | // for a copy. 31 | // }}} 32 | // License: GPL, v3, as defined and found on www.gnu.org, 33 | // {{{ 34 | // http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // 39 | `default_nettype none 40 | // }}} 41 | module rtctimer #( 42 | // {{{ 43 | parameter LGSUBCK = 2 44 | // }}} 45 | ) ( 46 | // {{{ 47 | input wire i_clk, i_reset, 48 | // 49 | input wire i_sub_ck, 50 | // 51 | input wire i_wr, 52 | input wire [24:0] i_data, 53 | input wire [2:0] i_valid, 54 | input wire i_zero, 55 | output wire [31:0] o_data, 56 | output wire o_interrupt 57 | // }}} 58 | ); 59 | 60 | // Signal declarations 61 | // {{{ 62 | reg [23:0] bcd_timer; 63 | // wire [6:0] bcd_hours, bcd_minutes, bcd_seconds; 64 | // assign bcd_seconds = bcd_timer[ 6:0]; 65 | // assign bcd_minutes = bcd_timer[14:8]; 66 | // assign bcd_hours = bcd_timer[22:16]; 67 | 68 | // 69 | reg [23:0] next_timer; 70 | reg [4:0] tmr_carry, pre_tmr_carry; 71 | reg last_tick; 72 | 73 | reg tm_pre_pps, tm_int, tm_running, tm_alarm; 74 | wire tm_stopped, tm_pps; 75 | reg [(LGSUBCK-1):0] tm_sub; 76 | // }}} 77 | 78 | // pre_tmr_carry, tmr_carry, next_timer 79 | // {{{ 80 | initial tmr_carry = 0; 81 | initial next_timer = 0; 82 | always @(posedge i_clk) 83 | begin 84 | pre_tmr_carry[0] <= (bcd_timer[ 3: 0]== 4'h0); 85 | pre_tmr_carry[1] <= (bcd_timer[ 6: 4]== 3'h0);//&&(tmr_carry[0]); 86 | pre_tmr_carry[2] <= (bcd_timer[11: 8]== 4'h0);//&&(tmr_carry[1]); 87 | pre_tmr_carry[3] <= (bcd_timer[14:12]== 3'h0);//&&(tmr_carry[2]); 88 | pre_tmr_carry[4] <= (bcd_timer[19:16]== 4'h0);//&&(tmr_carry[3]); 89 | tmr_carry[0] <= pre_tmr_carry[0]; 90 | tmr_carry[1] <= (&pre_tmr_carry[1:0]); 91 | tmr_carry[2] <= (&pre_tmr_carry[2:0]); 92 | tmr_carry[3] <= (&pre_tmr_carry[3:0]); 93 | tmr_carry[4] <= (&pre_tmr_carry[4:0]); 94 | last_tick <= (bcd_timer[23:1] == 0); 95 | 96 | // Keep unused bits at zero 97 | next_timer <= 24'h00; 98 | // Seconds 99 | // {{{ 100 | if (tmr_carry[0]) 101 | next_timer[3:0] <= 4'h9; 102 | else 103 | next_timer[ 3: 0] <= (bcd_timer[ 3: 0]-4'h1); 104 | 105 | if (tmr_carry[1]) 106 | next_timer[6:4] <= 3'h5; 107 | else if (tmr_carry[0]) 108 | next_timer[ 6: 4] <= (bcd_timer[ 6: 4]-3'h1); 109 | else 110 | next_timer[6:4] <= bcd_timer[6:4]; 111 | // }}} 112 | 113 | // Minutes 114 | // {{{ 115 | if (tmr_carry[2]) 116 | next_timer[11:8] <= 4'h9; 117 | else if (tmr_carry[1]) 118 | next_timer[11:8] <= bcd_timer[11:8]-4'h1; 119 | else 120 | next_timer[11:8] <= bcd_timer[11:8]; 121 | if (tmr_carry[3]) 122 | next_timer[14:12] <= 3'h5; 123 | else if (tmr_carry[2]) 124 | next_timer[14:12] <= (bcd_timer[14:12]-3'h1); 125 | else 126 | next_timer[14:12] <= bcd_timer[14:12]; 127 | // }}} 128 | 129 | // Hours 130 | // {{{ 131 | if (tmr_carry[4]) 132 | next_timer[19:16] <= 4'h9; 133 | else if (tmr_carry[3]) 134 | next_timer[19:16] <= bcd_timer[19:16]-4'h1; 135 | else 136 | next_timer[19:16] <= bcd_timer[19:16]; 137 | 138 | if (tmr_carry[4]) 139 | next_timer[23:20] <= (bcd_timer[23:20]-4'h1); 140 | else 141 | next_timer[23:20] <= bcd_timer[23:20]; 142 | // }}} 143 | end 144 | // }}} 145 | 146 | assign tm_stopped = !tm_running; 147 | 148 | // tm_sub 149 | // {{{ 150 | initial tm_sub = 0; 151 | always @(posedge i_clk) 152 | if ((i_reset)||((i_wr)&&(!tm_running)&&(&i_valid)&&(!i_zero))) 153 | tm_sub <= 0; 154 | else if ((i_sub_ck)&&(tm_running)) 155 | tm_sub <= tm_sub + 1; 156 | // }}} 157 | 158 | // tm_pre_pps, tm_pps 159 | // {{{ 160 | initial tm_pre_pps = 1'b0; 161 | always @(posedge i_clk) 162 | if ((i_reset)||((i_wr)&&(!tm_running))) 163 | tm_pre_pps <= 0; 164 | else if ((i_sub_ck)&&(tm_running)) 165 | tm_pre_pps <= (&tm_sub[LGSUBCK-1:1])&&(!tm_sub[0]); 166 | else 167 | tm_pre_pps <= (&tm_sub); 168 | 169 | assign tm_pps = (tm_pre_pps)&&(i_sub_ck); 170 | // }}} 171 | 172 | // bcd_timer, tm_int, tm_running, tm_alarm 173 | // {{{ 174 | initial bcd_timer = 24'h00; 175 | initial tm_int = 1'b0; 176 | initial tm_running = 1'b0; 177 | initial tm_alarm = 1'b0; 178 | always @(posedge i_clk) 179 | if (i_reset) 180 | begin 181 | tm_alarm <= 0; 182 | bcd_timer <= 0; 183 | tm_running <= 0; 184 | tm_int <= 0; 185 | end else begin 186 | if ((tm_pps)&&(tm_running)) 187 | bcd_timer <= next_timer; 188 | if ((tm_running)&&(tm_pps)) 189 | begin 190 | bcd_timer <= next_timer; 191 | if (last_tick) 192 | tm_alarm <= 1'b1; 193 | end 194 | 195 | bcd_timer[ 7] <= 1'b0; 196 | bcd_timer[15] <= 1'b0; 197 | 198 | tm_int <= (tm_running)&&(tm_pps)&&(!tm_alarm)&&(last_tick); 199 | 200 | if ((tm_pps)&&(last_tick)) // Stop the timer on an alarm 201 | tm_running <= 1'b0; 202 | else if (i_wr) 203 | begin 204 | if (tm_running) 205 | tm_running <= i_data[24]; 206 | else if ((i_zero)&&(bcd_timer != 0)) 207 | tm_running <= i_data[24]; 208 | else 209 | tm_running <= (!i_zero)&&(&i_valid); 210 | end 211 | 212 | if ((i_wr)&&(tm_stopped)) // Writes while stopped 213 | begin 214 | // 215 | if ((&i_valid)&&(!i_zero)) 216 | bcd_timer[23:0] <= i_data[23:0]; 217 | 218 | // Still ... any write clears the alarm 219 | tm_alarm <= 1'b0; 220 | end 221 | end 222 | // }}} 223 | 224 | assign o_interrupt = tm_int; 225 | assign o_data = { 6'h00, tm_alarm, tm_running, bcd_timer }; 226 | 227 | // Make Verilator happy 228 | // {{{ 229 | // verilator lint_off UNUSED 230 | // wire unused; 231 | // assign unused = &{ 1'b0, i_data[31:25] }; 232 | // verilator lint_on UNUSED 233 | // }}} 234 | //////////////////////////////////////////////////////////////////////////////// 235 | //////////////////////////////////////////////////////////////////////////////// 236 | //////////////////////////////////////////////////////////////////////////////// 237 | // 238 | // Formal properties 239 | // {{{ 240 | //////////////////////////////////////////////////////////////////////////////// 241 | //////////////////////////////////////////////////////////////////////////////// 242 | //////////////////////////////////////////////////////////////////////////////// 243 | `ifdef FORMAL 244 | `ifdef RTCTIMER 245 | `define ASSUME assume 246 | `define ASSERT assert 247 | `else 248 | `define ASSUME assert 249 | `define ASSERT assume 250 | `endif 251 | 252 | reg f_past_valid; 253 | initial f_past_valid = 1'b0; 254 | always @(posedge i_clk) 255 | f_past_valid <= 1'b1; 256 | 257 | always @(posedge i_clk) 258 | if ((!f_past_valid)||($past(i_reset))) 259 | begin 260 | `ASSUME(!i_wr); 261 | // 262 | `ASSERT(tm_sub == 0); 263 | `ASSERT(!tm_pps); 264 | `ASSERT(bcd_timer == 0); 265 | end 266 | 267 | always @(*) 268 | if (i_wr) 269 | begin 270 | if (i_valid[0]) 271 | begin 272 | `ASSUME(i_data[3:0] <= 4'h9); 273 | `ASSUME(i_data[7:4] <= 4'h5); 274 | end 275 | if (i_valid[1]) 276 | begin 277 | `ASSUME(i_data[11: 8] <= 4'h9); 278 | `ASSUME(i_data[15:12] <= 4'h5); 279 | end 280 | if (i_valid[2]) 281 | begin 282 | `ASSUME(i_data[19:16] <= 4'h9); 283 | end 284 | 285 | `ASSUME(i_zero == (i_data[23:0] == 0)); 286 | end 287 | // 288 | // 289 | // Timer assertions 290 | // 291 | // 292 | initial `ASSERT(tm_stopped); 293 | initial `ASSERT(!tm_alarm); 294 | always @(posedge i_clk) 295 | begin 296 | `ASSERT(bcd_timer[ 3: 0] <= 4'h9); 297 | `ASSERT(bcd_timer[ 7: 4] <= 4'h5); 298 | `ASSERT(bcd_timer[11: 8] <= 4'h9); 299 | `ASSERT(bcd_timer[15:12] <= 4'h5); 300 | `ASSERT(bcd_timer[19:16] <= 4'h9); 301 | // 302 | `ASSERT(bcd_timer[ 7] == 1'b0); 303 | `ASSERT(bcd_timer[15] == 1'b0); 304 | // 305 | end 306 | 307 | always @(posedge i_clk) 308 | if ((f_past_valid)&&(!$past(i_reset))) 309 | begin 310 | if ((!$past(tm_running))&&(!$past(i_wr))) 311 | `ASSERT($stable(bcd_timer)); 312 | if (($past(tm_pps))&&(!$past(i_wr))) 313 | begin 314 | if ($past(bcd_timer[3:0] != 4'h0)) 315 | `ASSERT($stable(bcd_timer[23:4])); 316 | if ($past(bcd_timer[6:0] != 7'h00)) 317 | `ASSERT($stable(bcd_timer[23:8])); 318 | if ($past(bcd_timer[11:0] != 12'h0000)) 319 | `ASSERT($stable(bcd_timer[23:12])); 320 | if ($past(bcd_timer[15:0] != 16'h0000)) 321 | `ASSERT($stable(bcd_timer[23:16])); 322 | if ($past(bcd_timer[19:0] != 20'h00000)) 323 | `ASSERT($stable(bcd_timer[23:20])); 324 | end 325 | 326 | if (($past(tm_running))&&(!$past(tm_pps))) 327 | `ASSERT($stable(bcd_timer)); 328 | 329 | if (tm_alarm) 330 | `ASSERT(bcd_timer[23:0] == 0); 331 | end 332 | 333 | always @(*) 334 | if (tm_alarm) 335 | `ASSERT(!tm_running); 336 | always @(*) 337 | if (tm_running) 338 | `ASSERT(bcd_timer[23:0] != 0); 339 | always @(*) 340 | if (tm_sub > 2) 341 | `ASSERT(last_tick == (bcd_timer[23:1] == 0)); 342 | always @(*) 343 | if (!&tm_sub) 344 | `ASSERT(tm_pps == 0); 345 | /* 346 | always @(posedge i_clk) 347 | if ((f_past_valid)&&(!$past(i_reset)) 348 | &&($past(tm_sub != 0))&&(tm_sub == 0)) 349 | `ASSERT($past(i_wr)||(tm_pps)); 350 | */ 351 | 352 | always @(posedge i_clk) 353 | cover(tm_int); 354 | 355 | always @(posedge i_clk) 356 | if ((f_past_valid)&&($past(!tm_alarm))) 357 | cover(tm_alarm); 358 | 359 | always @(posedge i_clk) 360 | if ((f_past_valid)&&(!$past(i_reset))&&($past(tm_alarm))) 361 | cover(!tm_alarm); 362 | `endif 363 | // }}} 364 | endmodule 365 | --------------------------------------------------------------------------------