├── .gitignore ├── Makefile ├── README.md ├── bench ├── README.md ├── cpp │ ├── Makefile │ ├── aximemsim.cpp │ └── aximemsim.h ├── formal │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── addrdecode.sby │ ├── afifo.gtkw │ ├── afifo.sby │ ├── apbslave.gtkw │ ├── apbslave.sby │ ├── apbxclk.sby │ ├── axi3reorder.sby │ ├── axi_addr_miter.sby │ ├── axi_addr_miter.v │ ├── axil2apb.gtkw │ ├── axil2apb.sby │ ├── axil2axis.gtkw │ ├── axil2axis.sby │ ├── axildouble.sby │ ├── axilempty.sby │ ├── axilgpio.sby │ ├── axilrd2wbsp.gtkw │ ├── axilrd2wbsp.sby │ ├── axilsafety.gtkw │ ├── axilsafety.sby │ ├── axilsingle.gtkw │ ├── axilsingle.sby │ ├── axilupsz.gtkw │ ├── axilupsz.sby │ ├── axilwr2wbsp.gtkw │ ├── axilwr2wbsp.sby │ ├── axilxbar.sby │ ├── axilxbar_4x1.gtkw │ ├── axilxbar_cvr1x3.gtkw │ ├── axilxbar_prf1x8.gtkw │ ├── axim2wbsp.ys │ ├── aximrd2wbsp.gtkw │ ├── aximrd2wbsp.sby │ ├── axiperf.sby │ ├── axisbroadcast.sby │ ├── axisgfsm.gtkw │ ├── axisgfsm.sby │ ├── axispacker.gtkw │ ├── axispacker.sby │ ├── axisrandom.sby │ ├── axissafety.gtkw │ ├── axissafety.sby │ ├── axisswitch.gtkw │ ├── axisswitch.sby │ ├── axlite2wbsp.gtkw │ ├── axlite2wbsp.sby │ ├── demoaxi.gtkw │ ├── demoaxi.sby │ ├── easyaxil.gtkw │ ├── easyaxil.sby │ ├── fapb_master.v │ ├── fapb_slave.v │ ├── fav_slave.v │ ├── faxi_addr.v │ ├── faxi_master.v │ ├── faxi_slave.v │ ├── faxil_master.v │ ├── faxil_register.v │ ├── faxil_slave.v │ ├── faxis_master.v │ ├── faxis_slave.v │ ├── fwb_master.v │ ├── fwb_register.v │ ├── fwb_slave.v │ ├── fwbc_master.v │ ├── fwbc_slave.v │ ├── genreport.pl │ ├── passcheck.sh │ ├── sfifo.sby │ ├── skidbuffer.gtkw │ ├── skidbuffer.sby │ ├── wbarbiter.gtkw │ ├── wbarbiter.sby │ ├── wbc2pipeline.gtkw │ ├── wbc2pipeline.sby │ ├── wbm2axilite.sby │ ├── wbm2axisp.sby │ ├── wbm2axisp.ys │ ├── wbp2classic.gtkw │ ├── wbp2classic.sby │ ├── wbsafety.gtkw │ ├── wbsafety.sby │ ├── wbxbar.sby │ ├── wbxclk.gtkw │ ├── wbxclk.sby │ ├── xlnxdemo.gtkw │ ├── xlnxdemo.sby │ ├── xlnxdemo.v │ ├── xlnxdemo_2018_3.v │ ├── xlnxdemo_2020_2.vhd │ ├── xlnxfull_2018_3.v │ ├── xlnxstream_2018_3.gtkw │ ├── xlnxstream_2018_3.sby │ └── xlnxstream_2018_3.v ├── mcy │ └── easyaxil │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── axi_tb.h │ │ ├── config.mcy │ │ ├── devbus.h │ │ ├── easyaxil_tb.cpp │ │ ├── easyaxil_tb.sv │ │ ├── easyprops.sv │ │ ├── test_eq.sh │ │ ├── test_fm.sby │ │ ├── test_fm.sh │ │ ├── test_sim.sh │ │ └── testb.h └── rtl │ └── saxi_slave.v ├── doc ├── .gitignore ├── Makefile ├── axi-multiwrite.dia ├── axi-multiwrite.png ├── axis2mm_mb.json ├── axis2mm_mb.png ├── axis2mm_mb.svg ├── axis2mm_sb.json ├── axis2mm_sb.png ├── axis2mm_sb.svg ├── axisafety.dia ├── axisafety.png ├── axisafety2.dia ├── axisafety2.png ├── axisafety2.svg ├── axixbar.dia ├── axixbar.png ├── axixbarx2-latency.png ├── busprops.pdf ├── chexpo-2021.pdf ├── demo2019.pdf ├── gfx │ ├── axi-bad-wstrb.json │ ├── axi-bad-wstrb.png │ ├── axi-bad-wstrb.svg │ ├── axi-fault-isolator.dia │ ├── axi-gpio-reads.json │ ├── axi-gpio-reads.png │ ├── axi-gpio-writes.json │ ├── axi-gpio-writes.png │ ├── axi-gpio-writes.svg │ ├── axi-handshake-ref.png │ ├── axi-in-everything.dia │ ├── axi-in-everything.svg │ ├── axi-in-everything.tex │ ├── axi-intel-bvalid-code.png │ ├── axi-intel-bvalid.png │ ├── axi-intel-wlast-code.png │ ├── axi-intel-wlast.png │ ├── axi-intel-wready.png │ ├── axi-last-err.json │ ├── axi-last-err.png │ ├── axi-last-err.svg │ ├── axi-narrow-burst-bkram-pg78-page46.png │ ├── axi-narrow-burst-spec-1.png │ ├── axi-narrow-burst-spec-2big.png │ ├── axi-narrow-burst-spec-3lil.png │ ├── axi-narrow-burst-spec-4lanes.png │ ├── axi-narrow-burst-spec-5bloc.png │ ├── axi-narrow-burst-spec-6wstrb.png │ ├── axi-not-simple.dia │ ├── axi-not-simple.dia.autosave │ ├── axi-not-simple.png │ ├── axi-perf-mon.png │ ├── axi-read-fault.png │ ├── axi-safety-valid.dia │ ├── axi-spec-registered.png │ ├── axi-wdata.json │ ├── axi-wdata.png │ ├── axi-wdata.svg │ ├── axi-write-demo.png │ ├── axi-write-example.png │ ├── axi2axil-read-burst.json │ ├── axi2axil-read-burst.png │ ├── axi2axil-read-burst.svg │ ├── axi2axil-read-single.json │ ├── axi2axil-read-single.png │ ├── axi2axil-read-single.svg │ ├── axi2axil-write-burst.json │ ├── axi2axil-write-burst.png │ ├── axi2axil-write-burst.svg │ ├── axi_narrow_burst-pg78.jpg │ ├── axidma.json │ ├── axidma.png │ ├── axidma.svg │ ├── axidouble-read.json │ ├── axidouble-read.png │ ├── axidouble-read.svg │ ├── axidouble-write.json │ ├── axidouble-write.png │ ├── axidouble-write.svg │ ├── axif-8pt-readburst.png │ ├── axif-8pt-writeburst.png │ ├── axifull-bvalid-fail-trace.png │ ├── axifull-bvalid-fail.json │ ├── axifull-bvalid-fail.png │ ├── axifull-bvalid-fail.svg │ ├── axifull-rd.json │ ├── axifull-rd.png │ ├── axifull-rd.svg │ ├── axifull-rdid.json │ ├── axifull-rdid.png │ ├── axifull-rdid.svg │ ├── axifull-rdwr.json │ ├── axifull-rdwr.png │ ├── axifull-rdwr.svg │ ├── axifull-wlast.json │ ├── axifull-wlast.png │ ├── axifull-wlast.svg │ ├── axifull-wr.json │ ├── axifull-wr.png │ ├── axifull-wr.svg │ ├── axil-double-valid.json │ ├── axil-double-valid.png │ ├── axil-missed-handshake.json │ ├── axil-missed-handshake.png │ ├── axil-read-example.png │ ├── axil-registered.png │ ├── axil-xilinx-read-broken.png │ ├── axil2apb-reads.png │ ├── axildouble-rd.png │ ├── axildouble-wr.png │ ├── axilsafety-diagram.png │ ├── axilsafety-readfault-burst.png │ ├── axilsafety-readfault-burst.svg │ ├── axilsingle-rd.png │ ├── axilsingle-wr.png │ ├── axilxbar-vivado-floorplanning.png │ ├── aximrd2wbsp.json │ ├── aximrd2wbsp.png │ ├── aximwr2wbsp-burst.json │ ├── aximwr2wbsp-burst.png │ ├── aximwr2wbsp-single.json │ ├── aximwr2wbsp-single.png │ ├── axisafety-fault.dia │ ├── axisafety-reset.dia │ ├── axivdma.json │ ├── axivdma.png │ ├── axivdma.svg │ ├── axivfifo.json │ ├── axivfifo.png │ ├── axivfifo.svg │ ├── axixbar-latency.png │ ├── brken-axilite.dia │ ├── brken-axilite.png │ ├── demofull-rd-basic.png │ ├── demofull-rd-double.png │ ├── demofull-wr-double.png │ ├── demofull-write-cover-trace.png │ ├── fv-example10-axil.png │ ├── misbehaving-axi-slave.dia │ ├── misbehaving-axi-slave.png │ ├── safety-proofs.dia │ ├── safety-proofs.png │ ├── swerv_ar_w.png │ ├── wbaxi-bridge-rresp-fail-code.png │ ├── wbaxi-bridge-rresp-fail.json │ ├── wbaxi-bridge-rresp-fail.png │ ├── wbaxi-bridge-rresp-fail.svg │ ├── wbxclk-annotated.dia │ ├── wbxclk-annotated.png │ ├── wbxclk.json │ ├── wbxclk.png │ ├── wbxclk.svg │ ├── xilinx-axilite2axi.png │ ├── xlnxstream.json │ ├── xlnxstream.png │ ├── xlnxstream.svg │ └── xlnxstream_trace.png ├── gpl-3.0.pdf ├── orconf2019.pdf └── src │ └── gpl-3.0.tex ├── rtl ├── .gitignore ├── Makefile ├── README.md ├── addrdecode.v ├── afifo.v ├── apbslave.v ├── apbxclk.v ├── axi2axi3.v ├── axi2axilite.v ├── axi2axilsub.v ├── axi32axi.v ├── axi3reorder.v ├── axi_addr.v ├── axidma.v ├── axidouble.v ├── axiempty.v ├── axil2apb.v ├── axil2axis.v ├── axildouble.v ├── axilempty.v ├── axilfetch.v ├── axilgpio.v ├── axilite2axi.v ├── axilrd2wbsp.v ├── axilsafety.v ├── axilsingle.v ├── axilupsz.v ├── axilwr2wbsp.v ├── axilxbar.v ├── axim2wbsp.v ├── aximm2s.v ├── aximrd2wbsp.v ├── aximwr2wbsp.v ├── axiperf.v ├── axis2mm.v ├── axisafety.v ├── axisbroadcast.v ├── axisgdma.v ├── axisgfsm.v ├── axispacker.v ├── axisrandom.v ├── axissafety.v ├── axisswitch.v ├── axivcamera.v ├── axivdisplay.v ├── axivfifo.v ├── axixbar.v ├── axixclk.v ├── axlite2wbsp.v ├── axlite_wrapper.vhd ├── demoaxi.v ├── demofull.v ├── easyaxil.v ├── migsdram.v ├── sfifo.v ├── sfifothresh.v ├── skidbuffer.v ├── wbarbiter.v ├── wbc2pipeline.v ├── wbdown.v ├── wbm2axilite.v ├── wbm2axisp.v ├── wbp2classic.v ├── wbsafety.v ├── wbupsz.v ├── wbxbar.v └── wbxclk.v └── wb2axip.core /.gitignore: -------------------------------------------------------------------------------- 1 | legal.txt 2 | a.out 3 | .svn 4 | xilinx 5 | obj_dir 6 | obj-pc 7 | obj-zip 8 | *.o 9 | *.a 10 | *.vcd 11 | .swp 12 | .*.swp 13 | .*.swo 14 | svn-commit* 15 | *_tb 16 | *_tb.dbl 17 | *dbg.txt 18 | *dump.txt 19 | *debug.txt 20 | tags 21 | cpudefs.h 22 | design.h 23 | octave-workspace 24 | core 25 | 20*.tjz 26 | *.autosave 27 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: Makefile 4 | ## {{{ 5 | ## Project: WB2AXIPSP: bus bridges and other odds and ends 6 | ## 7 | ## Purpose: A master project makefile. It tries to build all targets 8 | ## within the project, mostly by directing subdirectory makes. 9 | ## 10 | ## Targets: 11 | ## 12 | ## Creator: Dan Gisselquist, Ph.D. 13 | ## Gisselquist Technology, LLC 14 | ## 15 | ################################################################################ 16 | ## }}} 17 | ## Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | ## {{{ 19 | ## This file is part of the WB2AXIP project. 20 | ## 21 | ## The WB2AXIP project contains free software and gateware, licensed under the 22 | ## Apache License, Version 2.0 (the "License"). You may not use this project, 23 | ## or this file, except in compliance with the License. You may obtain a copy 24 | ## of the License at 25 | ## }}} 26 | ## http://www.apache.org/licenses/LICENSE-2.0 27 | ## {{{ 28 | ## Unless required by applicable law or agreed to in writing, software 29 | ## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 30 | ## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 31 | ## License for the specific language governing permissions and limitations 32 | ## under the License. 33 | ## 34 | ################################################################################ 35 | ## 36 | ## }}} 37 | .PHONY: all 38 | all: archive rtl formal 39 | # all: verilated sw bench bit 40 | # 41 | # Could also depend upon load, if desired, but not necessary 42 | BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"` 43 | RTL := `find rtl -name "*.v"` `find rtl -name Makefile` 44 | NOTES := `find . -name "*.txt"` `find . -name "*.html"` 45 | YYMMDD:=`date +%Y%m%d` 46 | 47 | .PHONY: archive 48 | ## {{{ 49 | archive: 50 | tar --transform s,^,$(YYMMDD)-wb2axi/, -chjf $(YYMMDD)-wb2axi.tjz $(BENCH) $(RTL) $(NOTES) 51 | ## }}} 52 | 53 | .PHONY: verilated rtl 54 | ## {{{ 55 | verilated: 56 | cd rtl ; $(MAKE) --no-print-directory 57 | 58 | rtl: verilated 59 | ## }}} 60 | 61 | .PHONY: bench 62 | ## {{{ 63 | bench: rtl 64 | cd bench/cpp ; $(MAKE) --no-print-directory 65 | ## }}} 66 | 67 | .PHONY: formal 68 | ## {{{ 69 | formal: 70 | $(MAKE) --no-print-directory -C bench/formal 71 | ## }}} 72 | 73 | .PHONY: doc 74 | ## {{{ 75 | doc: 76 | cd doc ; $(MAKE) --no-print-directory 77 | ## }}} 78 | 79 | 80 | -------------------------------------------------------------------------------- /bench/README.md: -------------------------------------------------------------------------------- 1 | This repository contains three types of bench testing information. 2 | 3 | 1. [Formal scripts and properties](formal) for the use in formal proofs using 4 | SymbiYosys. To be complete, each formal script will produce a full proof 5 | (with induction), together with a series of cover traces demonstrating 6 | all of what the design should/could do, and at high speed. You can find 7 | many of these cover results posted in the [../doc](../doc/gfx) directory. 8 | 9 | 2. [CPP scripts](cpp) for use with Verilator. These aren't very well developed, 10 | and were not used to verify anything here. 11 | 12 | 3. [MCY information](mcy). [MCY](https://github.com/YosysHQ/mcy) is a new 13 | program built by SymbioticEDA for the purpose of testing whether or not 14 | a test bench is sufficient for determining if a design truly works. My 15 | [mcy directory](mcy) contains my attempts and efforts at using this program. 16 | -------------------------------------------------------------------------------- /bench/cpp/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: bench/cpp/Makefile 4 | ## {{{ 5 | ## Project: WB2AXIPSP: bus bridges and other odds and ends 6 | ## 7 | ## Purpose: 8 | ## 9 | ## Creator: Dan Gisselquist, Ph.D. 10 | ## Gisselquist Technology, LLC 11 | ## 12 | ################################################################################ 13 | ## }}} 14 | ## Copyright (C) 2015-2025, Gisselquist Technology, LLC 15 | ## {{{ 16 | ## This file is part of the WB2AXIP project. 17 | ## 18 | ## The WB2AXIP project contains free software and gateware, licensed under the 19 | ## Apache License, Version 2.0 (the "License"). You may not use this project, 20 | ## or this file, except in compliance with the License. You may obtain a copy 21 | ## of the License at 22 | ## }}} 23 | ## http://www.apache.org/licenses/LICENSE-2.0 24 | ## {{{ 25 | ## Unless required by applicable law or agreed to in writing, software 26 | ## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 27 | ## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 28 | ## License for the specific language governing permissions and limitations 29 | ## under the License. 30 | ## 31 | ################################################################################ 32 | ## 33 | ## 34 | CXX := g++ 35 | FLAGS := -Wall -Og -g 36 | OBJDIR := obj-pc 37 | RTLD := ../verilog 38 | VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT| head -1 | sed -e " s/^.*=\s*//"') 39 | INCS := -I$(RTLD)/obj_dir/ -I$(VROOT)/include 40 | SOURCES := # testset.cpp 41 | VOBJDR := $(RTLD)/obj_dir 42 | VLIB := $(VROOT)/include/verilated.cpp 43 | SIMSRCS := aximemsim.cpp # testset.cpp 44 | SIMOBJ := $(subst .cpp,.o,$(SIMSRCS)) 45 | SIMOBJS:= $(addprefix $(OBJDIR)/,$(SIMOBJ)) 46 | ## }}} 47 | all: $(OBJDIR)/ testset 48 | 49 | $(OBJDIR)/: 50 | @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi" 51 | 52 | $(OBJDIR)/aximemsim.o: aximemsim.cpp aximemsim.h 53 | 54 | $(OBJDIR)/%.o: %.cpp 55 | $(CXX) $(FLAGS) $(INCS) -c $< -o $@ 56 | 57 | # testset: $(OBJDIR)/testset.o $(OBJDIR)/aximemsim.o $(VOBJDR)/Vtestset__ALL.a 58 | # $(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@ 59 | .PHONY: testset 60 | testset: 61 | @echo 62 | @echo "I seem to have lost the testset.cpp file that this test suite" 63 | @echo "was based off of. Hence, the suite is incomplete." 64 | @echo 65 | 66 | .PHONY: clean 67 | clean: 68 | rm -rf $(OBJDIR)/ 69 | # rm -f ./testset 70 | 71 | -------------------------------------------------------------------------------- /bench/cpp/aximemsim.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/cpp/aximemsim.h 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: To attempt to emulate how the MIG responds to AXI requests. 8 | // Of course, this is written with no knowledge of how MIG actually 9 | // responds, just a touch of knowledge regarding how a DDR3 memory works, 10 | // so ... your mileage might vary. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2016-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This file is part of the WB2AXIP project. 20 | // 21 | // The WB2AXIP project contains free software and gateware, licensed under the 22 | // Apache License, Version 2.0 (the "License"). You may not use this project, 23 | // or this file, except in compliance with the License. You may obtain a copy 24 | // of the License at 25 | // }}} 26 | // http://www.apache.org/licenses/LICENSE-2.0 27 | // {{{ 28 | // Unless required by applicable law or agreed to in writing, software 29 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 30 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 31 | // License for the specific language governing permissions and limitations 32 | // under the License. 33 | // 34 | //////////////////////////////////////////////////////////////////////////////// 35 | // 36 | #ifndef AXIMEMSIM_H 37 | #define AXIMEMSIM_H 38 | // }}} 39 | typedef struct { 40 | unsigned addr; 41 | int id, len, size, burst, lock, cache, prot, qos; 42 | bool ready, valid; 43 | } AXI_AWBUS; 44 | 45 | typedef struct { 46 | unsigned addr; 47 | int id, len, size, burst, lock, cache, prot, qos; 48 | bool ready, valid; 49 | } AXI_ARBUS; 50 | 51 | typedef struct { 52 | int strb; 53 | unsigned data[4]; // 128 bits 54 | int ready, valid, last; 55 | } AXI_WBUS; 56 | 57 | typedef struct { 58 | int id, resp; 59 | int ready, valid; 60 | } AXI_WRESP; 61 | 62 | typedef struct { 63 | int id, resp; 64 | unsigned data[4]; // 128 bits 65 | int ready, valid, last; 66 | } AXI_RDATA; 67 | 68 | typedef struct { 69 | AXI_AWBUS aw; 70 | AXI_ARBUS ar; 71 | AXI_WBUS w; 72 | AXI_WRESP b; 73 | AXI_RDATA r; 74 | } AXIBUS; 75 | 76 | class AXIMEMSIM { 77 | unsigned *m_mem; 78 | public: 79 | AXIMEMSIM(unsigned abits); 80 | void apply(AXIBUS &bus); 81 | }; 82 | 83 | #endif 84 | -------------------------------------------------------------------------------- /bench/formal/.gitignore: -------------------------------------------------------------------------------- 1 | *.smt2 2 | *.yslog 3 | *.check 4 | *.ys.v 5 | addrdecode*/ 6 | afifo*/ 7 | apbslave*/ 8 | apbxclk*/ 9 | axi2axilite*/ 10 | axi_addr_miter*/ 11 | axidma*/ 12 | axil2axis*/ 13 | axil2apb*/ 14 | axildouble*/ 15 | axilempty*/ 16 | axilgpio*/ 17 | axilite2axi*/ 18 | axilwr2wbsp*/ 19 | axilrd2wbsp*/ 20 | axilsafety*/ 21 | axilsingle*/ 22 | axildouble*/ 23 | axilupsz*/ 24 | axilxbar*/ 25 | axidouble*/ 26 | aximrd2wbsp*/ 27 | aximwr2wbsp*/ 28 | aximm2s*/ 29 | axiperf*/ 30 | axis2mm*/ 31 | axisafety*/ 32 | axisgfsm*/ 33 | axisbroadcast*/ 34 | axispacker*/ 35 | axisrandom*/ 36 | axissafety*/ 37 | axisswitch*/ 38 | axixbar*/ 39 | axixclk*/ 40 | axlite2wbsp*/ 41 | demoaxi*/ 42 | demofull*/ 43 | easyaxil*/ 44 | sfifo*/ 45 | skidbuffer*/ 46 | wbarbiter*/ 47 | wbdown*/ 48 | wbm2axilite*/ 49 | wbm2axisp*/ 50 | wbp2classic*/ 51 | wbc2pipeline*/ 52 | wbsafety*/ 53 | xlnxdemo_*/ 54 | xlnxfull_*/ 55 | xlnxstream_*/ 56 | wbxbar*/ 57 | wbxclk*/ 58 | -------------------------------------------------------------------------------- /bench/formal/README.md: -------------------------------------------------------------------------------- 1 | Every IP component in the [rtl](../../rtl) directory should have a respective 2 | SymbiYosys script here. (A .sby file.) Many of the AXI scripts remain 3 | proprietary and so get published elsewhere, but the AXI-lite and Wishbone 4 | scripts can be found here. 5 | 6 | In addition to the formal verification scripts found in this directory, 7 | you'll also find a series of bus properties for various interface standards. 8 | In general, these property sets are found in pairs--one property set for the 9 | slave, and a second property set for verifying the bus master. I routinely 10 | compare these sets against each other using [meld](https://meldmerge.org), 11 | so you shouldn't find any really substantial differences between them. 12 | 13 | ## Wishbone (Pipelined) 14 | 15 | [Master](fwb_master.v) and [Slave](fwb_slave.v) properties. 16 | 17 | My properties insist on two clarifications to the WB specification: 1) any 18 | bus cycle may be aborted by dropping the CYC line, and 2) the CYC line will 19 | drop and all bus cycles will be aborted following any bus error. I've also 20 | dropped the retry signal from the standard. 21 | 22 | ## Wishbone (Classic) 23 | 24 | [Master](fwbc_master.v) and [Slave](fwbc_slave.v) properties. 25 | 26 | ## AXI4-Lite 27 | 28 | [Master](faxil_master.v) and [Slave](faxil_slave.v) properties. These may 29 | be the easiest AXI4-lite property sets to use. 30 | 31 | There's also a [register data checking](faxil_register.v) property set, for 32 | use when checking that the value of a simple AXI-lite register is properly 33 | handled. 34 | 35 | ## AXI4 36 | 37 | These properties are kept in a separate repository. You can see some of what 38 | they contain in the [master](faxi_master.v) and [slave](faxi_slave.v) properties 39 | contained in this directory. The full properties, however, will allow you to 40 | do a proper induction (unbounded) proof. Those full properties can also handle 41 | out-of-order packet returns, such as AXI permits, to make certain that a 42 | core is fully/properly functional. The difficulty of checking these out of 43 | order properties using induction is one of the reasons these properties may be 44 | purchased rather than downloaded for free. 45 | 46 | ## AXI Stream 47 | 48 | [Master](faxis_master.v) and [slave](faxis_slave.v) properties. 49 | 50 | I rarely use these properties, however. I've found that every AXI stream 51 | slave is unique, especially input or output slaves that operate at a fixed 52 | rate. These properties also rely upon default portlist properties for 53 | the rarely used signals, `TID`, `TKEEP`, `TDEST`, and `TUSER`, something 54 | Yosys didn't yet support when they were first written. 55 | 56 | That said, the properties are currently good enough as is to prove that 57 | [Xilinx's AXI-Stream master](xlnxstream_2018_3.v) demonstration IP is broken. 58 | 59 | ## Avalon 60 | 61 | It's been a while since I've worked with Avalon, but the [slave 62 | properties](fav_slave.v) found here saved my bacon in a 63 | [Cyclone-V design](https://zipcpu.com/blog/2018/02/09/first-cyclonev.html) 64 | more than once. These properties only use a subset of the Avalon signals 65 | as well, and don't support any of the burst signaling capabilities of Avalon. 66 | 67 | ## APB 68 | 69 | [Master](fapb_master.v) and [slave](fapb_slave.v) properties. 70 | -------------------------------------------------------------------------------- /bench/formal/addrdecode.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prfrlp prf opt_registered opt_lowpower 3 | prfr prf opt_registered 4 | prfc prf 5 | cvrrlp cvr opt_registered opt_lowpower 6 | cvrr cvr opt_registered 7 | cvrc cvr 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 4 12 | cvr: mode cover 13 | cvr: depth 16 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -define ADDRDECODE 20 | read -formal addrdecode.v 21 | --pycode-begin-- 22 | cmd = "hierarchy -top addrdecode" 23 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 24 | cmd += " -chparam OPT_REGISTERED %d" % (1 if "opt_registered" in tags else 0) 25 | output(cmd) 26 | --pycode-end-- 27 | prep -top addrdecode 28 | 29 | [files] 30 | ../../rtl/addrdecode.v 31 | -------------------------------------------------------------------------------- /bench/formal/afifo.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Dec 11 04:26:37 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1054 8 | [pos] -1 -1 9 | *-5.190785 160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 196 11 | [signals_width] 150 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 315 14 | @28 15 | [color] 3 16 | afifo.i_wclk 17 | [color] 3 18 | afifo.i_wr_reset_n 19 | [color] 3 20 | afifo.i_wr 21 | @22 22 | [color] 3 23 | afifo.i_wr_data[15:0] 24 | @28 25 | [color] 3 26 | afifo.o_wr_full 27 | @200 28 | - 29 | @28 30 | [color] 2 31 | afifo.i_rclk 32 | [color] 2 33 | afifo.i_rd_reset_n 34 | [color] 2 35 | afifo.i_rd 36 | @22 37 | [color] 2 38 | afifo.o_rd_data[15:0] 39 | @28 40 | [color] 2 41 | afifo.o_rd_empty 42 | @200 43 | - 44 | @22 45 | [color] 3 46 | afifo.wr_addr[3:0] 47 | [color] 3 48 | afifo.wr_rgray[3:0] 49 | afifo.rd_addr[3:0] 50 | afifo.rd_wgray[3:0] 51 | @200 52 | - 53 | @28 54 | afifo.f_state[1:0] 55 | @22 56 | afifo.f_addr[3:0] 57 | @28 58 | afifo.pre_rclk 59 | afifo.pre_wclk 60 | afifo.now_rclk 61 | @22 62 | afifo.mem<0>[15:0] 63 | @200 64 | - 65 | @22 66 | afifo.rd_wgray[3:0] 67 | afifo.rgray[3:0] 68 | @200 69 | - 70 | @22 71 | afifo.wgray[3:0] 72 | afifo.wr_rgray[3:0] 73 | afifo.f_first[15:0] 74 | @23 75 | afifo.f_next[15:0] 76 | @200 77 | - 78 | @28 79 | afifo.f_first_in_fifo 80 | afifo.f_next_in_fifo 81 | [pattern_trace] 1 82 | [pattern_trace] 0 83 | -------------------------------------------------------------------------------- /bench/formal/afifo.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | prfopt prf opt_dstb 5 | cvropt cvr opt_dstb 6 | 7 | [options] 8 | prf: mode prove 9 | prf: depth 4 10 | cvr: mode cover 11 | cvr: depth 32 12 | multiclock on 13 | 14 | [engines] 15 | smtbmc boolector 16 | 17 | [script] 18 | read -formal -D AFIFO afifo.v 19 | opt_dstb: hierarchy -top afifo -chparam F_OPT_DATA_STB 1 20 | ~opt_dstb: hierarchy -top afifo -chparam F_OPT_DATA_STB 0 21 | prep -top afifo 22 | 23 | [files] 24 | ../../rtl/afifo.v 25 | -------------------------------------------------------------------------------- /bench/formal/apbslave.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Aug 19 14:48:18 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1787 600 8 | [pos] -1 -1 9 | *-3.628906 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 196 11 | [signals_width] 126 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 155 14 | @28 15 | apbslave.PRESETn 16 | apbslave.PCLK 17 | @200 18 | - 19 | @28 20 | [color] 3 21 | apbslave.PSEL 22 | [color] 3 23 | apbslave.PWRITE 24 | [color] 3 25 | apbslave.PENABLE 26 | @29 27 | [color] 2 28 | apbslave.PREADY 29 | @22 30 | [color] 3 31 | apbslave.PADDR[11:0] 32 | [color] 3 33 | apbslave.PWDATA[31:0] 34 | @23 35 | [color] 2 36 | apbslave.PRDATA[31:0] 37 | @29 38 | [color] 2 39 | apbslave.PSLVERR 40 | @200 41 | - 42 | @22 43 | apbslave.f_addr[11:0] 44 | apbslave.f_data[31:0] 45 | [pattern_trace] 1 46 | [pattern_trace] 0 47 | -------------------------------------------------------------------------------- /bench/formal/apbslave.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 4 8 | cvr: mode cover 9 | cvr: depth 15 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal apbslave.v 16 | read -formal fapb_slave.v 17 | prep -top apbslave 18 | 19 | [files] 20 | ../../rtl/apbslave.v 21 | fapb_slave.v 22 | -------------------------------------------------------------------------------- /bench/formal/apbxclk.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 11 8 | cvr: mode cover 9 | cvr: depth 90 # 72 should be sufficient 10 | multiclock on 11 | 12 | [engines] 13 | smtbmc 14 | 15 | [script] 16 | read -formal apbxclk.v 17 | read -formal fapb_slave.v 18 | read -formal fapb_master.v 19 | prep -top apbxclk 20 | 21 | [files] 22 | ../../rtl/apbxclk.v 23 | fapb_slave.v 24 | fapb_master.v 25 | -------------------------------------------------------------------------------- /bench/formal/axi3reorder.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | bmcsreg bmc opt_sreg 3 | bmcfifo bmc 4 | bmcsreglp bmc opt_sreg opt_lowpower 5 | bmcfifolp bmc opt_lowpower 6 | bmcsreglat bmc opt_sreg opt_low_latency 7 | bmcfifolat bmc opt_low_latency 8 | bmcsreglatlp bmc opt_sreg opt_lowpower opt_low_latency 9 | bmcfifolatlp bmc opt_lowpower opt_low_latency 10 | cvrsreg cvr opt_sreg # 34 steps 11 | cvrfifo cvr cvrfifo # 21 steps 12 | cvrsreglp cvr opt_sreg opt_lowpower # 34 steps 13 | cvrfifolp cvr opt_lowpower cvrfifo # 21 steps 14 | cvrsreglat cvr opt_sreg opt_low_latency # 34 steps 15 | cvrfifolat cvr opt_low_latency cvrfifo 16 | cvrsreglatlp cvr opt_sreg opt_lowpower opt_low_latency 17 | cvrfifolatlp cvr opt_lowpower opt_low_latency cvrfifo 18 | 19 | [options] 20 | bmc: mode bmc 21 | bmc: depth 40 22 | cvr: mode cover 23 | cvr: depth 40 24 | # bmcsreg: 18 steps of BMC takes 19 hrs 25 | # bmcfifo: 22 steps of BMC takes 16 hrs 26 | # bmcsreglp: 18 steps of BMC takes 17 hrs 27 | # bmcfifolp: 23 steps of BMC takes 20 hrs 28 | 29 | [engines] 30 | # smtbmc 31 | smtbmc boolector 32 | 33 | [script] 34 | cvrfifo: read -define SFIFO 35 | read -formal sfifo.v 36 | read -formal axi3reorder.v 37 | --pycode-begin-- 38 | cmd = "hierarchy -top axi3reorder -chparam DW 8 -chparam OPT_LGWFIFO 2" 39 | cmd += " -chparam C_AXI_ID_WIDTH 2" 40 | cmd += " -chparam OPT_METHOD %d" % (1 if "opt_sreg" in tags else 2) 41 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 42 | cmd += " -chparam OPT_LOW_LATENCY %d" % (1 if "opt_low_latency" in tags else 0) 43 | output(cmd) 44 | --pycode-end-- 45 | prep -top axi3reorder 46 | 47 | [files] 48 | ../../rtl/sfifo.v 49 | ../../rtl/axi3reorder.v 50 | -------------------------------------------------------------------------------- /bench/formal/axi_addr_miter.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf8 3 | prf16 4 | prf32 5 | prf64 6 | prf128 7 | prf256 8 | prf512 9 | prf1024 10 | 11 | [options] 12 | mode bmc 13 | depth 2 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -formal axi_addr.v 20 | read -formal faxi_addr.v 21 | read -formal axi_addr_miter.v 22 | prf8: hierarchy -top axi_addr_miter -chparam DW 8 23 | prf16: hierarchy -top axi_addr_miter -chparam DW 16 24 | prf32: hierarchy -top axi_addr_miter -chparam DW 32 25 | prf64: hierarchy -top axi_addr_miter -chparam DW 64 26 | prf128: hierarchy -top axi_addr_miter -chparam DW 128 27 | prf256: hierarchy -top axi_addr_miter -chparam DW 256 28 | prf512: hierarchy -top axi_addr_miter -chparam DW 512 29 | prf1024: hierarchy -top axi_addr_miter -chparam DW 1024 30 | 31 | prep -top axi_addr_miter 32 | 33 | [files] 34 | ../../rtl/axi_addr.v 35 | faxi_addr.v 36 | axi_addr_miter.v 37 | -------------------------------------------------------------------------------- /bench/formal/axi_addr_miter.v: -------------------------------------------------------------------------------- 1 | module axi_addr_miter(i_last_addr, i_size, i_burst, i_len); 2 | parameter AW = 32, 3 | DW = 32; 4 | input wire [AW-1:0] i_last_addr; 5 | input wire [2:0] i_size; // 1b, 2b, 4b, 8b, etc 6 | input wire [1:0] i_burst; // fixed, incr, wrap, reserved 7 | input wire [7:0] i_len; 8 | 9 | localparam DSZ = $clog2(DW)-3; 10 | 11 | wire [7:0] ref_incr; 12 | wire [AW-1:0] ref_next_addr; 13 | 14 | faxi_addr #(.AW(AW)) 15 | ref(i_last_addr, i_size, i_burst, i_len,ref_incr,ref_next_addr); 16 | 17 | wire [AW-1:0] uut_next_addr; 18 | 19 | axi_addr #(.AW(AW), .DW(DW)) 20 | uut(i_last_addr, i_size, i_burst, i_len, uut_next_addr); 21 | 22 | always @(*) 23 | assert(DW == (1<<(DSZ+3))); 24 | 25 | always @(*) 26 | assume(i_burst != 2'b11); 27 | 28 | always @(*) 29 | assume(i_size <= DSZ); 30 | 31 | always @(*) 32 | if (i_burst == 2'b10) 33 | begin 34 | assume((i_len == 1) 35 | ||(i_len == 3) 36 | ||(i_len == 7) 37 | ||(i_len == 15)); 38 | end 39 | 40 | reg aligned; 41 | 42 | always @(*) 43 | begin 44 | aligned = 0; 45 | case(DSZ) 46 | 3'b000: aligned = 1; 47 | 3'b001: aligned = (i_last_addr[0] == 0); 48 | 3'b010: aligned = (i_last_addr[1:0] == 0); 49 | 3'b011: aligned = (i_last_addr[2:0] == 0); 50 | 3'b100: aligned = (i_last_addr[3:0] == 0); 51 | 3'b101: aligned = (i_last_addr[4:0] == 0); 52 | 3'b110: aligned = (i_last_addr[5:0] == 0); 53 | 3'b111: aligned = (i_last_addr[6:0] == 0); 54 | endcase 55 | end 56 | 57 | always @(*) 58 | if (i_burst == 2'b10) 59 | assume(aligned); 60 | 61 | always @(*) 62 | assert(uut_next_addr == ref_next_addr); 63 | 64 | always @(*) 65 | if (i_burst == 2'b01) 66 | assume(i_last_addr[AW-1:12] == ref_next_addr[AW-1:12]); 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /bench/formal/axil2apb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Sat Nov 21 00:36:12 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1920 1029 7 | [pos] -1 -1 8 | *-5.628906 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 196 10 | [signals_width] 230 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 315 13 | @28 14 | axil2apb.S_AXI_ARESETN 15 | axil2apb.S_AXI_ACLK 16 | @200 17 | - 18 | @c00200 19 | -AXI writes 20 | @28 21 | [color] 3 22 | axil2apb.S_AXI_AWVALID 23 | [color] 2 24 | axil2apb.S_AXI_AWREADY 25 | @22 26 | [color] 3 27 | axil2apb.S_AXI_AWADDR[31:0] 28 | @28 29 | [color] 3 30 | axil2apb.S_AXI_AWPROT[2:0] 31 | @200 32 | - 33 | @28 34 | [color] 3 35 | axil2apb.S_AXI_WVALID 36 | [color] 2 37 | axil2apb.S_AXI_WREADY 38 | @22 39 | [color] 3 40 | axil2apb.S_AXI_WDATA[31:0] 41 | [color] 3 42 | axil2apb.S_AXI_WSTRB[3:0] 43 | @200 44 | - 45 | @28 46 | [color] 2 47 | axil2apb.S_AXI_BVALID 48 | [color] 3 49 | axil2apb.S_AXI_BREADY 50 | [color] 2 51 | axil2apb.S_AXI_BRESP[1:0] 52 | axil2apb.axil_write_ready 53 | @1401200 54 | -AXI writes 55 | @800200 56 | -AXI reads 57 | @28 58 | [color] 3 59 | axil2apb.S_AXI_ARVALID 60 | [color] 2 61 | axil2apb.S_AXI_ARREADY 62 | @22 63 | [color] 3 64 | axil2apb.S_AXI_ARADDR[31:0] 65 | @28 66 | [color] 3 67 | axil2apb.S_AXI_ARPROT[2:0] 68 | @200 69 | - 70 | @29 71 | [color] 2 72 | axil2apb.S_AXI_RVALID 73 | @28 74 | [color] 3 75 | axil2apb.S_AXI_RREADY 76 | @22 77 | [color] 2 78 | axil2apb.S_AXI_RDATA[31:0] 79 | @28 80 | [color] 2 81 | axil2apb.S_AXI_RRESP[1:0] 82 | axil2apb.axil_read_ready 83 | axil2apb.arskd_valid 84 | @1000200 85 | -AXI reads 86 | @800200 87 | -APB out 88 | @28 89 | [color] 2 90 | axil2apb.M_APB_PSEL 91 | [color] 2 92 | axil2apb.M_APB_PENABLE 93 | [color] 3 94 | axil2apb.M_APB_PREADY 95 | @22 96 | [color] 2 97 | axil2apb.M_APB_PADDR[31:0] 98 | @28 99 | [color] 2 100 | axil2apb.M_APB_PWRITE 101 | @22 102 | [color] 2 103 | axil2apb.M_APB_PWDATA[31:0] 104 | @28 105 | [color] 2 106 | axil2apb.M_APB_PPROT[2:0] 107 | @22 108 | [color] 2 109 | axil2apb.M_APB_PWSTRB[3:0] 110 | [color] 3 111 | axil2apb.M_APB_PRDATA[31:0] 112 | @28 113 | [color] 3 114 | axil2apb.M_APB_PSLVERR 115 | @1000200 116 | -APB out 117 | [pattern_trace] 1 118 | [pattern_trace] 0 119 | -------------------------------------------------------------------------------- /bench/formal/axil2apb.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfskd prf opt_skidbuffer 4 | cvr opt_skidbuffer 5 | 6 | [options] 7 | prf: mode prove 8 | prf: depth 20 9 | cvr: mode cover 10 | cvr: depth 40 11 | 12 | [engines] 13 | smtbmc 14 | 15 | [script] 16 | read -formal axil2apb.v 17 | read -formal fapb_master.v 18 | read -formal faxil_slave.v 19 | read -formal skidbuffer.v 20 | opt_skidbuffer: hierarchy -top axil2apb -chparam OPT_OUTGOING_SKIDBUFFER 1 21 | ~opt_skidbuffer: hierarchy -top axil2apb -chparam OPT_OUTGOING_SKIDBUFFER 0 22 | prep -top axil2apb 23 | 24 | [files] 25 | ../../rtl/axil2apb.v 26 | ../../rtl/skidbuffer.v 27 | faxil_slave.v 28 | fapb_master.v 29 | -------------------------------------------------------------------------------- /bench/formal/axil2axis.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Sun Apr 19 18:19:02 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1021 8 | [pos] -1 -1 9 | *-4.124164 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] axil2axis. 11 | [sst_width] 270 12 | [signals_width] 190 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 290 15 | @28 16 | axil2axis.S_AXI_ACLK 17 | axil2axis.S_AXI_ARESETN 18 | @c00200 19 | -AXIL Writes 20 | @28 21 | [color] 3 22 | axil2axis.S_AXI_AWVALID 23 | [color] 2 24 | axil2axis.S_AXI_AWREADY 25 | @22 26 | [color] 3 27 | axil2axis.S_AXI_AWADDR[3:0] 28 | @28 29 | [color] 3 30 | axil2axis.S_AXI_AWPROT[2:0] 31 | @200 32 | - 33 | @28 34 | [color] 3 35 | axil2axis.S_AXI_WVALID 36 | [color] 2 37 | axil2axis.S_AXI_WREADY 38 | @22 39 | [color] 3 40 | axil2axis.S_AXI_WDATA[31:0] 41 | [color] 3 42 | axil2axis.S_AXI_WSTRB[3:0] 43 | @200 44 | - 45 | @28 46 | [color] 2 47 | axil2axis.S_AXI_BVALID 48 | [color] 3 49 | axil2axis.S_AXI_BREADY 50 | [color] 2 51 | axil2axis.S_AXI_BRESP[1:0] 52 | @1401200 53 | -AXIL Writes 54 | @c00200 55 | -Stream Master 56 | @28 57 | [color] 2 58 | axil2axis.M_AXIS_TVALID 59 | [color] 3 60 | axil2axis.M_AXIS_TREADY 61 | [color] 2 62 | axil2axis.M_AXIS_TLAST 63 | @22 64 | axil2axis.wfifo_fill[9:0] 65 | @1401200 66 | -Stream Master 67 | @c00200 68 | -AXIL Reads 69 | @28 70 | [color] 3 71 | axil2axis.S_AXI_ARVALID 72 | [color] 2 73 | axil2axis.S_AXI_ARREADY 74 | @22 75 | [color] 3 76 | axil2axis.S_AXI_ARADDR[3:0] 77 | @28 78 | [color] 3 79 | axil2axis.S_AXI_ARPROT[2:0] 80 | @200 81 | - 82 | @28 83 | [color] 2 84 | axil2axis.S_AXI_RVALID 85 | [color] 3 86 | axil2axis.S_AXI_RREADY 87 | @22 88 | [color] 2 89 | axil2axis.S_AXI_RDATA[31:0] 90 | @28 91 | [color] 2 92 | axil2axis.S_AXI_RRESP[1:0] 93 | @1401200 94 | -AXIL Reads 95 | @c00200 96 | -Stream Slave 97 | @28 98 | [color] 3 99 | axil2axis.S_AXIS_TVALID 100 | [color] 2 101 | axil2axis.S_AXIS_TREADY 102 | [color] 3 103 | axil2axis.S_AXIS_TLAST 104 | @22 105 | axil2axis.rfifo_fill[9:0] 106 | @1401200 107 | -Stream Slave 108 | [pattern_trace] 1 109 | [pattern_trace] 0 110 | -------------------------------------------------------------------------------- /bench/formal/axil2axis.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf opt_sink opt_src opt_sign opt_sign opt_timeout 3 | prflps prf opt_sink opt_src opt_sign opt_lowpower opt_sign 4 | prflpu prf opt_sink opt_src opt_sign opt_lowpower 5 | prfsink prf opt_sink opt_src opt_sign 6 | prfsource prf opt_sink opt_src opt_sign 7 | cvr opt_sink opt_src opt_timeout 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 6 12 | cvr: mode cover 13 | cvr: depth 40 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -formal axil2axis.v 20 | read -formal skidbuffer.v 21 | read -formal sfifo.v 22 | read -formal faxil_slave.v 23 | --pycode-begin-- 24 | cmd = "hierarchy -top axil2axis" 25 | cmd += " -chparam OPT_TIMEOUT %d" % (5 if "opt_timeout" in tags else 0) 26 | cmd += " -chparam LGFIFO %d" % (2 if "cvr" in tags else 5) 27 | cmd += " -chparam OPT_SINK %d" % (1 if "opt_sink" in tags else 0) 28 | cmd += " -chparam OPT_SOURCE %d" % (1 if "opt_src" in tags else 0) 29 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 30 | cmd += " -chparam OPT_SIGN_EXTEND %d" % (1 if "opt_sign" in tags else 0) 31 | output(cmd); 32 | --pycode-end-- 33 | prep -top axil2axis 34 | 35 | [files] 36 | ../../rtl/axil2axis.v 37 | ../../rtl/skidbuffer.v 38 | ../../rtl/sfifo.v 39 | faxil_slave.v 40 | -------------------------------------------------------------------------------- /bench/formal/axildouble.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 14 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc boolector 13 | # prf: abc pdr 14 | 15 | [script] 16 | read -formal addrdecode.v 17 | read -formal axildouble.v 18 | read -formal faxil_slave.v 19 | read -formal faxil_master.v 20 | read -formal sfifo.v 21 | read -formal skidbuffer.v 22 | prep -top axildouble 23 | 24 | [files] 25 | ../../rtl/sfifo.v 26 | ../../rtl/skidbuffer.v 27 | ../../rtl/addrdecode.v 28 | ../../rtl/axildouble.v 29 | faxil_slave.v 30 | faxil_master.v 31 | -------------------------------------------------------------------------------- /bench/formal/axilempty.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prfreg prf 3 | cvrreg cvr 4 | prfskd prf opt_skidbuffer 5 | cvrskd cvr opt_skidbuffer 6 | prfreglp prf opt_lowpower 7 | prfskdlp prf opt_skidbuffer opt_lowpower 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 3 12 | cvr: mode cover 13 | cvr: depth 40 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -formal axilempty.v 20 | opt_skidbuffer: read -formal skidbuffer.v 21 | read -formal faxil_slave.v 22 | --pycode-begin-- 23 | cmd = "hierarchy -top axilempty" 24 | cmd += " -chparam OPT_SKIDBUFFER %d" % (1 if "opt_skidbuffer" in tags else 0) 25 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 26 | output(cmd); 27 | --pycode-end-- 28 | prep -top axilempty 29 | 30 | [files] 31 | ../../rtl/axilempty.v 32 | opt_skidbuffer: ../../rtl/skidbuffer.v 33 | faxil_slave.v 34 | -------------------------------------------------------------------------------- /bench/formal/axilgpio.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prfreg prf 3 | cvrreg cvr 4 | prfskd prf opt_skidbuffer 5 | cvrskd cvr opt_skidbuffer 6 | prfreglp prf opt_lowpower 7 | prfskdlp prf opt_skidbuffer opt_lowpower 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 3 12 | cvr: mode cover 13 | cvr: depth 40 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -formal axilgpio.v 20 | opt_skidbuffer: read -formal skidbuffer.v 21 | read -formal faxil_register.v 22 | read -formal faxil_slave.v 23 | --pycode-begin-- 24 | cmd = "hierarchy -top axilgpio" 25 | cmd += " -chparam OPT_SKIDBUFFER %d" % (1 if "opt_skidbuffer" in tags else 0) 26 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 27 | output(cmd); 28 | --pycode-end-- 29 | prep -top axilgpio 30 | 31 | [files] 32 | ../../rtl/axilgpio.v 33 | opt_skidbuffer: ../../rtl/skidbuffer.v 34 | faxil_slave.v 35 | faxil_register.v 36 | -------------------------------------------------------------------------------- /bench/formal/axilrd2wbsp.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Fri Dec 28 05:15:33 2018 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1898 600 8 | [pos] -1 -1 9 | *-5.054117 210 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 270 11 | [signals_width] 210 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 143 14 | @28 15 | [color] 3 16 | axilrd2wbsp.i_axi_reset_n 17 | [color] 3 18 | axilrd2wbsp.i_clk 19 | @200 20 | - 21 | @28 22 | axilrd2wbsp.i_axi_arvalid 23 | axilrd2wbsp.o_axi_arready 24 | @22 25 | axilrd2wbsp.i_axi_araddr[27:0] 26 | axilrd2wbsp.i_axi_arcache[3:0] 27 | @28 28 | axilrd2wbsp.i_axi_arprot[2:0] 29 | @200 30 | - 31 | @28 32 | [color] 2 33 | axilrd2wbsp.o_axi_rvalid 34 | [color] 2 35 | axilrd2wbsp.i_axi_rready 36 | @22 37 | [color] 2 38 | axilrd2wbsp.o_axi_rdata[31:0] 39 | @28 40 | [color] 2 41 | axilrd2wbsp.o_axi_rresp[1:0] 42 | @200 43 | - 44 | @28 45 | axilrd2wbsp.o_wb_cyc 46 | axilrd2wbsp.o_wb_stb 47 | @22 48 | axilrd2wbsp.o_wb_addr[25:0] 49 | @28 50 | [color] 2 51 | axilrd2wbsp.i_wb_stall 52 | [color] 2 53 | axilrd2wbsp.i_wb_ack 54 | @23 55 | [color] 2 56 | axilrd2wbsp.i_wb_data[31:0] 57 | @28 58 | [color] 2 59 | axilrd2wbsp.i_wb_err 60 | @200 61 | - 62 | @28 63 | [color] 3 64 | axilrd2wbsp.r_stb 65 | @22 66 | [color] 3 67 | axilrd2wbsp.r_addr[25:0] 68 | [pattern_trace] 1 69 | [pattern_trace] 0 70 | -------------------------------------------------------------------------------- /bench/formal/axilrd2wbsp.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr 3 | prf 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 5 8 | cvr: mode cover 9 | cvr: depth 32 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D AXILRD2WBSP axilrd2wbsp.v 16 | read -formal -D AXILRD2WBSP faxil_slave.v 17 | read -formal -D AXILRD2WBSP fwb_master.v 18 | prep -top axilrd2wbsp 19 | 20 | [files] 21 | ../../rtl/axilrd2wbsp.v 22 | faxil_slave.v 23 | fwb_master.v 24 | -------------------------------------------------------------------------------- /bench/formal/axilsafety.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Apr 22 14:55:50 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1021 8 | [pos] -1 -1 9 | *-6.333802 496 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] axilsafety. 11 | [sst_width] 270 12 | [signals_width] 246 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 290 15 | @28 16 | axilsafety.S_AXI_ACLK 17 | axilsafety.S_AXI_ARESETN 18 | @c00200 19 | -Slave Write 20 | @28 21 | [color] 3 22 | axilsafety.S_AXI_AWVALID 23 | [color] 2 24 | axilsafety.S_AXI_AWREADY 25 | @22 26 | [color] 3 27 | axilsafety.S_AXI_AWADDR[27:0] 28 | @28 29 | [color] 3 30 | axilsafety.S_AXI_AWPROT[2:0] 31 | @200 32 | - 33 | @28 34 | [color] 3 35 | axilsafety.S_AXI_WVALID 36 | [color] 2 37 | axilsafety.S_AXI_WREADY 38 | @22 39 | [color] 3 40 | axilsafety.S_AXI_WDATA[31:0] 41 | [color] 3 42 | axilsafety.S_AXI_WSTRB[3:0] 43 | @200 44 | - 45 | @28 46 | [color] 2 47 | axilsafety.S_AXI_BVALID 48 | [color] 3 49 | axilsafety.S_AXI_BREADY 50 | [color] 2 51 | axilsafety.S_AXI_BRESP[1:0] 52 | @1401200 53 | -Slave Write 54 | @28 55 | [color] 1 56 | axilsafety.o_write_fault 57 | @c00201 58 | -Slave Read 59 | @28 60 | [color] 3 61 | axilsafety.S_AXI_ARVALID 62 | [color] 2 63 | axilsafety.S_AXI_ARREADY 64 | @22 65 | [color] 3 66 | axilsafety.S_AXI_ARADDR[27:0] 67 | @28 68 | [color] 3 69 | axilsafety.S_AXI_ARPROT[2:0] 70 | @200 71 | - 72 | @28 73 | [color] 2 74 | axilsafety.S_AXI_RVALID 75 | [color] 3 76 | axilsafety.S_AXI_RREADY 77 | @22 78 | [color] 2 79 | axilsafety.S_AXI_RDATA[31:0] 80 | @28 81 | [color] 2 82 | axilsafety.S_AXI_RRESP[1:0] 83 | @1401201 84 | -Slave Read 85 | @28 86 | [color] 1 87 | axilsafety.o_read_fault 88 | [color] 2 89 | axilsafety.M_AXI_ARESETN 90 | @c00200 91 | -Downstream Write 92 | @28 93 | [color] 2 94 | axilsafety.M_AXI_AWVALID 95 | [color] 3 96 | axilsafety.M_AXI_AWREADY 97 | @22 98 | [color] 2 99 | axilsafety.M_AXI_AWADDR[27:0] 100 | @28 101 | [color] 2 102 | axilsafety.M_AXI_AWPROT[2:0] 103 | @200 104 | - 105 | @28 106 | [color] 2 107 | axilsafety.M_AXI_WVALID 108 | [color] 3 109 | axilsafety.M_AXI_WREADY 110 | @22 111 | [color] 2 112 | axilsafety.M_AXI_WDATA[31:0] 113 | [color] 2 114 | axilsafety.M_AXI_WSTRB[3:0] 115 | @200 116 | - 117 | @28 118 | [color] 3 119 | axilsafety.M_AXI_BVALID 120 | [color] 2 121 | axilsafety.M_AXI_BREADY 122 | [color] 3 123 | axilsafety.M_AXI_BRESP[1:0] 124 | @1401200 125 | -Downstream Write 126 | @c00200 127 | -Downstream Read 128 | @28 129 | [color] 2 130 | axilsafety.M_AXI_ARVALID 131 | [color] 3 132 | axilsafety.M_AXI_ARREADY 133 | @22 134 | [color] 2 135 | axilsafety.M_AXI_ARADDR[27:0] 136 | @28 137 | [color] 2 138 | axilsafety.M_AXI_ARPROT[2:0] 139 | @200 140 | - 141 | @28 142 | [color] 3 143 | axilsafety.M_AXI_RVALID 144 | [color] 2 145 | axilsafety.M_AXI_RREADY 146 | @22 147 | [color] 3 148 | axilsafety.M_AXI_RDATA[31:0] 149 | @28 150 | [color] 3 151 | axilsafety.M_AXI_RRESP[1:0] 152 | @1401200 153 | -Downstream Read 154 | @22 155 | axilsafety.aw_stall_counter[3:0] 156 | @28 157 | axilsafety.aw_stall_limit 158 | @22 159 | axilsafety.w_stall_counter[3:0] 160 | @28 161 | axilsafety.w_stall_limit 162 | @200 163 | - 164 | @c00200 165 | -Read Fault 166 | @22 167 | axilsafety.r_stall_counter[3:0] 168 | axilsafety.r_ack_timer[3:0] 169 | axilsafety.downstream_r_count[3:0] 170 | @200 171 | - 172 | @28 173 | axilsafety.downstream_r_zero 174 | axilsafety.r_stall_limit 175 | axilsafety.r_ack_limit 176 | axilsafety.last_rvalid 177 | axilsafety.last_rchanged 178 | @22 179 | axilsafety.r_count[3:0] 180 | axilsafety.faxils_rd_outstanding[3:0] 181 | axilsafety.ASSUME_FAULTLESS.faxilm_rd_outstanding[3:0] 182 | @1401200 183 | -Read Fault 184 | @200 185 | - 186 | @22 187 | axilsafety.faxils_awr_outstanding[3:0] 188 | axilsafety.faxils_rd_outstanding[3:0] 189 | axilsafety.faxils_wr_outstanding[3:0] 190 | axilsafety.aw_count[3:0] 191 | axilsafety.aw_stall_counter[3:0] 192 | axilsafety.downstream_aw_count[3:0] 193 | axilsafety.downstream_w_count[3:0] 194 | axilsafety.r_count[3:0] 195 | axilsafety.r_stall_counter[3:0] 196 | axilsafety.w_count[3:0] 197 | axilsafety.w_stall_counter[3:0] 198 | [pattern_trace] 1 199 | [pattern_trace] 0 200 | -------------------------------------------------------------------------------- /bench/formal/axilsafety.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr fault opt_reset 4 | fault prf 5 | prfr prf opt_reset 6 | faultr fault prf opt_reset 7 | longr fault prf opt_reset opt_long_reset 8 | prlong prf opt_reset opt_long_reset 9 | 10 | [options] 11 | prf: mode prove 12 | prf: depth 23 13 | cvr: mode cover 14 | cvr: depth 32 15 | 16 | [engines] 17 | smtbmc 18 | 19 | [script] 20 | read -formal axilsafety.v 21 | read -formal skidbuffer.v 22 | read -formal faxil_slave.v 23 | read -formal faxil_master.v 24 | --pycode-begin-- 25 | cmd = "hierarchy -top axilsafety" 26 | cmd += " -chparam F_OPT_FAULTLESS %d" % (0 if "fault" in tags else 1) 27 | cmd += " -chparam OPT_SELF_RESET %d" % (1 if "opt_reset" in tags else 0) 28 | cmd += " -chparam OPT_MIN_RESET %d" % (16 if "opt_long_reset" in tags else 0) 29 | cmd += " -chparam OPT_TIMEOUT 10" 30 | output(cmd) 31 | --pycode-end-- 32 | prep -top axilsafety 33 | 34 | [files] 35 | ../../rtl/skidbuffer.v 36 | ../../rtl/axilsafety.v 37 | faxil_slave.v 38 | faxil_master.v 39 | -------------------------------------------------------------------------------- /bench/formal/axilsingle.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Aug 19 20:26:38 2019 4 | [*] 5 | [dumpfile_mtime] "Mon Aug 19 20:23:51 2019" 6 | [dumpfile_size] 31391 7 | [timestart] 0 8 | [size] 1920 1029 9 | [pos] -1 -1 10 | *-3.628906 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 196 12 | [signals_width] 238 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 306 15 | @28 16 | axilsingle.S_AXI_ACLK 17 | axilsingle.S_AXI_ARESETN 18 | @200 19 | - 20 | @c00200 21 | -S_WRITE 22 | @28 23 | [color] 3 24 | axilsingle.S_AXI_AWVALID 25 | axilsingle.S_AXI_AWREADY 26 | @22 27 | [color] 3 28 | axilsingle.S_AXI_AWADDR[31:0] 29 | @28 30 | [color] 3 31 | axilsingle.S_AXI_AWPROT[2:0] 32 | @200 33 | - 34 | @28 35 | [color] 3 36 | axilsingle.S_AXI_WVALID 37 | axilsingle.S_AXI_WREADY 38 | @22 39 | [color] 3 40 | axilsingle.S_AXI_WDATA[31:0] 41 | [color] 3 42 | axilsingle.S_AXI_WSTRB[3:0] 43 | @200 44 | - 45 | @28 46 | [color] 3 47 | axilsingle.S_AXI_BVALID 48 | axilsingle.S_AXI_BREADY 49 | [color] 3 50 | axilsingle.S_AXI_BRESP[1:0] 51 | @1401200 52 | -S_WRITE 53 | @800200 54 | -S_READ 55 | @28 56 | [color] 3 57 | axilsingle.S_AXI_ARVALID 58 | axilsingle.S_AXI_ARREADY 59 | @22 60 | [color] 3 61 | axilsingle.S_AXI_ARADDR[31:0] 62 | @28 63 | [color] 3 64 | axilsingle.S_AXI_ARPROT[2:0] 65 | @200 66 | - 67 | @28 68 | [color] 3 69 | axilsingle.S_AXI_RVALID 70 | axilsingle.S_AXI_RREADY 71 | @22 72 | [color] 3 73 | axilsingle.S_AXI_RDATA[31:0] 74 | @28 75 | [color] 3 76 | axilsingle.S_AXI_RRESP[1:0] 77 | @1000200 78 | -S_READ 79 | @200 80 | - 81 | @c00201 82 | -M_WRITE 83 | @22 84 | [color] 2 85 | axilsingle.M_AXI_AWVALID[7:0] 86 | @28 87 | [color] 2 88 | axilsingle.M_AXI_AWPROT[2:0] 89 | @200 90 | - 91 | @22 92 | axilsingle.M_AXI_WDATA[31:0] 93 | axilsingle.M_AXI_WSTRB[3:0] 94 | @200 95 | - 96 | @22 97 | axilsingle.M_AXI_BRESP[15:0] 98 | @1401201 99 | -M_WRITE 100 | @200 101 | - 102 | @800200 103 | -M_READ 104 | @22 105 | [color] 2 106 | axilsingle.M_AXI_ARVALID[7:0] 107 | @28 108 | [color] 2 109 | axilsingle.M_AXI_ARPROT[2:0] 110 | @200 111 | - 112 | @22 113 | axilsingle.M_AXI_RDATA[255:0] 114 | axilsingle.M_AXI_RRESP[15:0] 115 | @1000200 116 | -M_READ 117 | @200 118 | - 119 | - 120 | @28 121 | axilsingle.awskid_valid 122 | @22 123 | axilsingle.awskid_addr[29:0] 124 | @28 125 | axilsingle.awskid_prot[2:0] 126 | @22 127 | axilsingle.awskid_sel[8:0] 128 | @200 129 | - 130 | @28 131 | axilsingle.arskid_valid 132 | @22 133 | axilsingle.arskid_addr[31:0] 134 | @28 135 | axilsingle.arskid_prot[2:0] 136 | @22 137 | axilsingle.arskid_sel[8:0] 138 | @200 139 | - 140 | @28 141 | axilsingle.wskid_valid 142 | axilsingle.write_resp[1:0] 143 | @22 144 | axilsingle.wskid_data[35:0] 145 | @200 146 | - 147 | @28 148 | axilsingle.write_ready 149 | @22 150 | axilsingle.wout_valids[8:0] 151 | axilsingle.wout_addr[29:0] 152 | @200 153 | - 154 | @28 155 | axilsingle.woskid_ready 156 | axilsingle.woskid_valid 157 | @22 158 | axilsingle.write_index[29:0] 159 | @200 160 | - 161 | @28 162 | axilsingle.write_bvalid 163 | axilsingle.bempty 164 | axilsingle.bffull 165 | axilsingle.bfill[2:0] 166 | axilsingle.bfull 167 | @200 168 | - 169 | @28 170 | axilsingle.read_rvalid 171 | axilsingle.rdfull 172 | @22 173 | axilsingle.read_index[29:0] 174 | axilsingle.read_rdata[31:0] 175 | @28 176 | axilsingle.read_ready 177 | axilsingle.read_resp[1:0] 178 | axilsingle.rempty 179 | axilsingle.rfill[2:0] 180 | axilsingle.rfull 181 | axilsingle.roskid_ready 182 | axilsingle.roskid_valid 183 | @22 184 | axilsingle.rout_addr[29:0] 185 | axilsingle.rout_valids[8:0] 186 | @200 187 | - 188 | @22 189 | [color] 1 190 | axilsingle.count_awr_outstanding[3:0] 191 | [color] 1 192 | axilsingle.count_rd_outstanding[3:0] 193 | @200 194 | - 195 | @22 196 | axilsingle.f_axi_awr_outstanding[3:0] 197 | axilsingle.f_axi_rd_outstanding[3:0] 198 | axilsingle.f_axi_wr_outstanding[3:0] 199 | @28 200 | axilsingle.f_past_valid 201 | axilsingle.unused 202 | [pattern_trace] 1 203 | [pattern_trace] 0 204 | -------------------------------------------------------------------------------- /bench/formal/axilsingle.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 14 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc boolector 13 | 14 | [script] 15 | read -formal axilsingle.v 16 | read -formal faxil_slave.v 17 | read -formal faxil_master.v 18 | read -formal sfifo.v 19 | read -formal skidbuffer.v 20 | prep -top axilsingle 21 | 22 | [files] 23 | ../../rtl/sfifo.v 24 | ../../rtl/skidbuffer.v 25 | ../../rtl/axilsingle.v 26 | faxil_slave.v 27 | faxil_master.v 28 | -------------------------------------------------------------------------------- /bench/formal/axilupsz.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Wed Feb 3 21:06:28 2021 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1870 987 8 | [pos] -1 -1 9 | *-5.010530 34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] axilupsz. 11 | [treeopen] axilupsz.axil_slave. 12 | [sst_width] 329 13 | [signals_width] 230 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 266 16 | @28 17 | axilupsz.S_AXI_ACLK 18 | axilupsz.S_AXI_ARESETN 19 | @200 20 | - 21 | @800200 22 | -Slave 23 | @28 24 | [color] 3 25 | axilupsz.S_AXIL_AWVALID 26 | [color] 2 27 | axilupsz.S_AXIL_AWREADY 28 | [color] 3 29 | axilupsz.S_AXIL_AWPROT[2:0] 30 | @22 31 | [color] 3 32 | axilupsz.S_AXIL_AWADDR[31:0] 33 | @200 34 | - 35 | @28 36 | [color] 3 37 | axilupsz.S_AXIL_WVALID 38 | [color] 2 39 | axilupsz.S_AXIL_WREADY 40 | @22 41 | [color] 3 42 | axilupsz.S_AXIL_WDATA[31:0] 43 | [color] 3 44 | axilupsz.S_AXIL_WSTRB[3:0] 45 | @200 46 | - 47 | @28 48 | [color] 2 49 | axilupsz.S_AXIL_BVALID 50 | [color] 3 51 | axilupsz.S_AXIL_BREADY 52 | [color] 2 53 | axilupsz.S_AXIL_BRESP[1:0] 54 | @200 55 | - 56 | @28 57 | [color] 3 58 | axilupsz.S_AXIL_ARVALID 59 | [color] 2 60 | axilupsz.S_AXIL_ARREADY 61 | @22 62 | [color] 3 63 | axilupsz.S_AXIL_ARADDR[31:0] 64 | @28 65 | [color] 3 66 | axilupsz.S_AXIL_ARPROT[2:0] 67 | @200 68 | - 69 | @28 70 | [color] 2 71 | axilupsz.S_AXIL_RVALID 72 | [color] 3 73 | axilupsz.S_AXIL_RREADY 74 | @22 75 | [color] 2 76 | axilupsz.S_AXIL_RDATA[31:0] 77 | @28 78 | [color] 2 79 | axilupsz.S_AXIL_RRESP[1:0] 80 | @1000200 81 | -Slave 82 | @28 83 | axilupsz.wskd_valid 84 | axilupsz.wskd_ready 85 | axilupsz.rskd_ready 86 | @200 87 | - 88 | @22 89 | axilupsz.rskd_data[63:0] 90 | @28 91 | axilupsz.rskd_valid 92 | axilupsz.rskd_ready 93 | axilupsz.rskd_resp[1:0] 94 | @c00022 95 | axilupsz.rfifo_fill[5:0] 96 | @28 97 | (0)axilupsz.rfifo_fill[5:0] 98 | (1)axilupsz.rfifo_fill[5:0] 99 | (2)axilupsz.rfifo_fill[5:0] 100 | (3)axilupsz.rfifo_fill[5:0] 101 | (4)axilupsz.rfifo_fill[5:0] 102 | (5)axilupsz.rfifo_fill[5:0] 103 | @1401200 104 | -group_end 105 | @800200 106 | -Master 107 | @28 108 | [color] 2 109 | axilupsz.M_AXIL_AWVALID 110 | [color] 3 111 | axilupsz.M_AXIL_AWREADY 112 | @22 113 | [color] 2 114 | axilupsz.M_AXIL_AWADDR[31:0] 115 | @28 116 | [color] 2 117 | axilupsz.M_AXIL_AWPROT[2:0] 118 | @200 119 | - 120 | @28 121 | [color] 2 122 | axilupsz.M_AXIL_WVALID 123 | [color] 3 124 | axilupsz.M_AXIL_WREADY 125 | @22 126 | [color] 2 127 | axilupsz.M_AXIL_WDATA[63:0] 128 | [color] 2 129 | axilupsz.M_AXIL_WSTRB[7:0] 130 | @200 131 | - 132 | @28 133 | [color] 3 134 | axilupsz.M_AXIL_BVALID 135 | [color] 2 136 | axilupsz.M_AXIL_BREADY 137 | [color] 3 138 | axilupsz.M_AXIL_BRESP[1:0] 139 | @200 140 | - 141 | @28 142 | [color] 2 143 | axilupsz.M_AXIL_ARVALID 144 | [color] 3 145 | axilupsz.M_AXIL_ARREADY 146 | @22 147 | [color] 2 148 | axilupsz.M_AXIL_ARADDR[31:0] 149 | @28 150 | [color] 2 151 | axilupsz.M_AXIL_ARPROT[2:0] 152 | @200 153 | - 154 | @28 155 | [color] 3 156 | axilupsz.M_AXIL_RVALID 157 | [color] 2 158 | axilupsz.M_AXIL_RREADY 159 | @22 160 | [color] 3 161 | axilupsz.M_AXIL_RDATA[63:0] 162 | @28 163 | [color] 3 164 | axilupsz.M_AXIL_RRESP[1:0] 165 | @1000200 166 | -Master 167 | @28 168 | [color] 2 169 | axilupsz.rfifo_full 170 | @200 171 | - 172 | @23 173 | axilupsz.fslv_awr_outstanding[6:0] 174 | @22 175 | axilupsz.fslv_wr_outstanding[6:0] 176 | axilupsz.fslv_rd_outstanding[6:0] 177 | @200 178 | - 179 | @22 180 | axilupsz.fmst_awr_outstanding[6:0] 181 | axilupsz.fmst_rd_outstanding[6:0] 182 | axilupsz.fmst_wr_outstanding[6:0] 183 | @200 184 | - 185 | @22 186 | axilupsz.axil_slave.CHECK_STALL_COUNT.f_axi_awstall[4:0] 187 | axilupsz.axil_slave.CHECK_STALL_COUNT.f_axi_wstall[4:0] 188 | axilupsz.axil_slave.CHECK_STALL_COUNT.f_axi_arstall[4:0] 189 | [pattern_trace] 1 190 | [pattern_trace] 0 191 | -------------------------------------------------------------------------------- /bench/formal/axilupsz.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfz prf opt_lowpower 4 | cvr 5 | 6 | [options] 7 | prf: mode prove 8 | prf: depth 11 9 | cvr: mode cover 10 | cvr: depth 40 11 | 12 | [engines] 13 | smtbmc boolector 14 | 15 | [script] 16 | read -formal axilupsz.v 17 | read -formal faxil_slave.v 18 | read -formal faxil_master.v 19 | read -formal sfifo.v 20 | read -formal skidbuffer.v 21 | opt_lowpower: hierarchy -top axilupsz -chparam OPT_LOWPOWER 1 22 | ~opt_lowpower: hierarchy -top axilupsz -chparam OPT_LOWPOWER 0 23 | prep -top axilupsz 24 | 25 | [files] 26 | ../../rtl/sfifo.v 27 | ../../rtl/skidbuffer.v 28 | ../../rtl/axilupsz.v 29 | faxil_slave.v 30 | faxil_master.v 31 | -------------------------------------------------------------------------------- /bench/formal/axilwr2wbsp.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Mon Apr 26 17:11:38 2021 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1257 907 8 | [pos] 3044 -638 9 | *-3.908651 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] axilwr2wbsp. 11 | [sst_width] 329 12 | [signals_width] 238 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 238 15 | @28 16 | axilwr2wbsp.i_clk 17 | axilwr2wbsp.i_axi_reset_n 18 | @200 19 | - 20 | @28 21 | [color] 3 22 | axilwr2wbsp.i_axi_awvalid 23 | [color] 2 24 | axilwr2wbsp.o_axi_awready 25 | @22 26 | [color] 3 27 | axilwr2wbsp.i_axi_awaddr[27:0] 28 | @28 29 | [color] 3 30 | axilwr2wbsp.i_axi_awprot[2:0] 31 | axilwr2wbsp.r_awvalid 32 | @200 33 | - 34 | @28 35 | [color] 3 36 | axilwr2wbsp.i_axi_wvalid 37 | [color] 2 38 | axilwr2wbsp.o_axi_wready 39 | @22 40 | [color] 3 41 | axilwr2wbsp.i_axi_wdata[31:0] 42 | [color] 3 43 | axilwr2wbsp.i_axi_wstrb[3:0] 44 | @28 45 | axilwr2wbsp.r_wvalid 46 | @200 47 | - 48 | @28 49 | [color] 2 50 | axilwr2wbsp.o_axi_bvalid 51 | [color] 3 52 | axilwr2wbsp.i_axi_bready 53 | [color] 2 54 | axilwr2wbsp.o_axi_bresp[1:0] 55 | @200 56 | - 57 | @28 58 | [color] 2 59 | axilwr2wbsp.o_wb_cyc 60 | [color] 2 61 | axilwr2wbsp.o_wb_stb 62 | @22 63 | [color] 2 64 | axilwr2wbsp.o_wb_addr[25:0] 65 | [color] 2 66 | axilwr2wbsp.o_wb_data[31:0] 67 | [color] 2 68 | axilwr2wbsp.o_wb_sel[3:0] 69 | @28 70 | [color] 3 71 | axilwr2wbsp.i_wb_stall 72 | [color] 3 73 | axilwr2wbsp.i_wb_ack 74 | [color] 3 75 | axilwr2wbsp.i_wb_err 76 | @200 77 | - 78 | @22 79 | axilwr2wbsp.f_axi_awr_outstanding[3:0] 80 | axilwr2wbsp.f_axi_rd_outstanding[3:0] 81 | axilwr2wbsp.f_axi_wr_outstanding[3:0] 82 | [pattern_trace] 1 83 | [pattern_trace] 0 84 | -------------------------------------------------------------------------------- /bench/formal/axilwr2wbsp.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 5 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D AXILWR2WBSP axilwr2wbsp.v 16 | read -formal -D AXILWR2WBSP faxil_slave.v 17 | read -formal -D AXILWR2WBSP fwb_master.v 18 | prep -top axilwr2wbsp 19 | 20 | [files] 21 | ../../rtl/axilwr2wbsp.v 22 | faxil_slave.v 23 | fwb_master.v 24 | -------------------------------------------------------------------------------- /bench/formal/axilxbar.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf4x8_lp nxm opt_lowpower 3 | prf4x8 nxm 4 | cvr4x8_lp nxl opt_lowpower cvr 5 | cvr4x8 nxl cvr 6 | prf1x8_lp oxm opt_lowpower 7 | prf1x8 oxm 8 | cvr1x3_lp oxl opt_lowpower cvr 9 | cvr1x3 oxl cvr 10 | 11 | prf4x1_lp nxo opt_lowpower 12 | prf4x1 nxo 13 | cvr4x1_lp nxo opt_lowpower cvr 14 | cvr4x1 nxo cvr 15 | 16 | [options] 17 | ~cvr: mode prove 18 | ~cvr: depth 4 19 | cvr: mode cover 20 | cvr: depth 64 21 | 22 | [engines] 23 | smtbmc boolector 24 | # smtbmc 25 | # smtbmc z3 26 | 27 | 28 | [script] 29 | read -formal addrdecode.v 30 | read -formal skidbuffer.v 31 | read -formal axilxbar.v 32 | read -formal faxil_slave.v 33 | read -formal faxil_master.v 34 | --pycode-begin-- 35 | cmd = "hierarchy -top axilxbar" 36 | if ("nxm" in tags): 37 | cmd += " -chparam NM 4 -chparam NS 8" 38 | if ("oxm" in tags): 39 | cmd += " -chparam NM 1 -chparam NS 8" 40 | if ("oxl" in tags): 41 | cmd += " -chparam NM 1 -chparam NS 3" 42 | if ("nxl" in tags): 43 | cmd += " -chparam NM 3 -chparam NS 3" 44 | if ("nxo" in tags): 45 | cmd += " -chparam NM 4 -chparam NS 1" 46 | cmd += " -chparam C_AXI_ADDR_WIDTH 16" 47 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 48 | output(cmd) 49 | --pycode-end-- 50 | prep -top axilxbar 51 | 52 | [files] 53 | ../../rtl/skidbuffer.v 54 | ../../rtl/addrdecode.v 55 | ../../rtl/axilxbar.v 56 | faxil_slave.v 57 | faxil_master.v 58 | -------------------------------------------------------------------------------- /bench/formal/axilxbar_4x1.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Dec 12 18:40:05 2019 4 | [*] 5 | [dumpfile_mtime] "Thu Dec 12 18:30:15 2019" 6 | [dumpfile_size] 197418 7 | [timestart] 0 8 | [size] 1920 1029 9 | [pos] -1 -429 10 | *-5.474993 38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 196 12 | [signals_width] 182 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 306 15 | @28 16 | axilxbar.S_AXI_ACLK 17 | axilxbar.S_AXI_ARESETN 18 | @200 19 | - 20 | @800200 21 | -Slave interface 22 | @22 23 | [color] 3 24 | axilxbar.S_AXI_AWVALID[3:0] 25 | @23 26 | [color] 2 27 | axilxbar.S_AXI_AWREADY[3:0] 28 | @22 29 | [color] 3 30 | axilxbar.S_AXI_AWADDR[63:0] 31 | [color] 3 32 | axilxbar.S_AXI_AWPROT[11:0] 33 | @200 34 | - 35 | @22 36 | [color] 3 37 | axilxbar.S_AXI_WVALID[3:0] 38 | @23 39 | [color] 2 40 | axilxbar.S_AXI_WREADY[3:0] 41 | @22 42 | [color] 3 43 | axilxbar.S_AXI_WDATA[127:0] 44 | [color] 3 45 | axilxbar.S_AXI_WSTRB[15:0] 46 | @200 47 | - 48 | @22 49 | [color] 2 50 | axilxbar.S_AXI_BVALID[3:0] 51 | [color] 3 52 | axilxbar.S_AXI_BREADY[3:0] 53 | [color] 2 54 | axilxbar.S_AXI_BRESP[7:0] 55 | @200 56 | - 57 | @22 58 | [color] 3 59 | axilxbar.S_AXI_ARVALID[3:0] 60 | [color] 2 61 | axilxbar.S_AXI_ARREADY[3:0] 62 | [color] 3 63 | axilxbar.S_AXI_ARADDR[63:0] 64 | [color] 3 65 | axilxbar.S_AXI_ARPROT[11:0] 66 | @200 67 | - 68 | @22 69 | [color] 2 70 | axilxbar.S_AXI_RVALID[3:0] 71 | [color] 3 72 | axilxbar.S_AXI_RREADY[3:0] 73 | [color] 2 74 | axilxbar.S_AXI_RDATA[127:0] 75 | [color] 2 76 | axilxbar.S_AXI_RRESP[7:0] 77 | @1000200 78 | -Slave interface 79 | @c00200 80 | -Master interface 81 | @28 82 | axilxbar.M_AXI_AWVALID 83 | axilxbar.M_AXI_AWREADY 84 | @22 85 | axilxbar.M_AXI_AWADDR[15:0] 86 | @28 87 | axilxbar.M_AXI_AWPROT[2:0] 88 | @200 89 | - 90 | @28 91 | axilxbar.M_AXI_WVALID 92 | axilxbar.M_AXI_WREADY 93 | @22 94 | axilxbar.M_AXI_WDATA[31:0] 95 | axilxbar.M_AXI_WSTRB[3:0] 96 | @200 97 | - 98 | @28 99 | axilxbar.M_AXI_BVALID 100 | axilxbar.M_AXI_BREADY 101 | axilxbar.M_AXI_BRESP[1:0] 102 | @200 103 | - 104 | @28 105 | axilxbar.M_AXI_ARVALID 106 | axilxbar.M_AXI_ARREADY 107 | @22 108 | axilxbar.M_AXI_ARADDR[15:0] 109 | @28 110 | axilxbar.M_AXI_ARPROT[2:0] 111 | @200 112 | - 113 | @28 114 | axilxbar.M_AXI_RVALID 115 | axilxbar.M_AXI_RREADY 116 | @22 117 | axilxbar.M_AXI_RDATA[31:0] 118 | @28 119 | axilxbar.M_AXI_RRESP[1:0] 120 | @1401200 121 | -Master interface 122 | @200 123 | - 124 | - 125 | [pattern_trace] 1 126 | [pattern_trace] 0 127 | -------------------------------------------------------------------------------- /bench/formal/axilxbar_cvr1x3.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Dec 12 18:45:50 2019 4 | [*] 5 | [dumpfile_mtime] "Thu Dec 12 18:22:49 2019" 6 | [dumpfile_size] 187868 7 | [timestart] 0 8 | [size] 1920 1029 9 | [pos] 3839 0 10 | *-6.088337 260 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] axilxbar. 12 | [sst_width] 196 13 | [signals_width] 230 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 324 16 | @28 17 | axilxbar.S_AXI_ACLK 18 | axilxbar.S_AXI_ARESETN 19 | @800200 20 | -Master write 21 | @28 22 | axilxbar.S_AXI_WVALID 23 | @22 24 | axilxbar.S_AXI_AWADDR[15:0] 25 | @28 26 | axilxbar.S_AXI_AWPROT[2:0] 27 | axilxbar.S_AXI_AWREADY 28 | axilxbar.S_AXI_AWVALID 29 | axilxbar.S_AXI_BREADY 30 | axilxbar.S_AXI_BRESP[1:0] 31 | axilxbar.S_AXI_BVALID 32 | @22 33 | axilxbar.S_AXI_WDATA[31:0] 34 | @28 35 | axilxbar.S_AXI_WREADY 36 | @22 37 | axilxbar.S_AXI_WSTRB[3:0] 38 | @200 39 | - 40 | - 41 | @1000200 42 | -Master write 43 | @800200 44 | -Master read 45 | @29 46 | axilxbar.S_AXI_ARVALID 47 | @22 48 | axilxbar.S_AXI_ARADDR[15:0] 49 | @28 50 | axilxbar.S_AXI_ARPROT[2:0] 51 | axilxbar.S_AXI_ARREADY 52 | @200 53 | - 54 | @28 55 | axilxbar.S_AXI_RVALID 56 | axilxbar.S_AXI_RREADY 57 | @22 58 | axilxbar.S_AXI_RDATA[31:0] 59 | @28 60 | axilxbar.S_AXI_RRESP[1:0] 61 | @1000200 62 | -Master read 63 | @800200 64 | -Slave write 65 | @28 66 | axilxbar.M_AXI_AWVALID[2:0] 67 | axilxbar.M_AXI_AWREADY[2:0] 68 | @22 69 | axilxbar.M_AXI_AWADDR[47:0] 70 | axilxbar.M_AXI_AWPROT[8:0] 71 | @200 72 | - 73 | @22 74 | axilxbar.M_AXI_WDATA[95:0] 75 | @28 76 | axilxbar.M_AXI_WREADY[2:0] 77 | @22 78 | axilxbar.M_AXI_WSTRB[11:0] 79 | @28 80 | axilxbar.M_AXI_WVALID[2:0] 81 | @200 82 | - 83 | @28 84 | axilxbar.M_AXI_BVALID[2:0] 85 | axilxbar.M_AXI_BREADY[2:0] 86 | @22 87 | axilxbar.M_AXI_BRESP[5:0] 88 | @1000200 89 | -Slave write 90 | @800200 91 | -Slave read 92 | @28 93 | axilxbar.M_AXI_ARVALID[2:0] 94 | axilxbar.M_AXI_ARREADY[2:0] 95 | @22 96 | axilxbar.M_AXI_ARADDR[47:0] 97 | axilxbar.M_AXI_ARPROT[8:0] 98 | @200 99 | - 100 | @22 101 | axilxbar.M_AXI_RDATA[95:0] 102 | @28 103 | axilxbar.M_AXI_RREADY[2:0] 104 | @22 105 | axilxbar.M_AXI_RRESP[5:0] 106 | @28 107 | axilxbar.M_AXI_RVALID[2:0] 108 | @1000200 109 | -Slave read 110 | @200 111 | - 112 | @28 113 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.err_wr_return 114 | @22 115 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.r_returns[3:0] 116 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.w_returns[3:0] 117 | @28 118 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.was_revery 119 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.was_wevery 120 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.err_wr_return 121 | @22 122 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.r_returns[3:0] 123 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.w_returns[3:0] 124 | @28 125 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.was_revery 126 | axilxbar.COVER_CONNECTIVITY_FROM_MASTER<0>.was_wevery 127 | [pattern_trace] 1 128 | [pattern_trace] 0 129 | -------------------------------------------------------------------------------- /bench/formal/axilxbar_prf1x8.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Apr 10 17:07:04 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Wed Apr 10 16:32:28 2019" 7 | [dumpfile_size] 94139 8 | [timestart] 0 9 | [size] 1920 1054 10 | [pos] -1 -1 11 | *-4.270011 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [treeopen] axilxbar. 13 | [sst_width] 196 14 | [signals_width] 270 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 315 17 | @28 18 | axilxbar.S_AXI_ACLK 19 | axilxbar.S_AXI_ARESETN 20 | @c00200 21 | -Master write 22 | @28 23 | [color] 3 24 | axilxbar.M_AXI_AWVALID 25 | [color] 2 26 | axilxbar.M_AXI_AWREADY 27 | @22 28 | [color] 3 29 | axilxbar.M_AXI_AWADDR[31:0] 30 | @28 31 | [color] 3 32 | axilxbar.M_AXI_AWPROT[2:0] 33 | @200 34 | - 35 | @28 36 | [color] 3 37 | axilxbar.M_AXI_WVALID 38 | [color] 2 39 | axilxbar.M_AXI_WREADY 40 | @22 41 | [color] 3 42 | axilxbar.M_AXI_WDATA[31:0] 43 | [color] 3 44 | axilxbar.M_AXI_WSTRB[3:0] 45 | @200 46 | - 47 | @28 48 | [color] 2 49 | axilxbar.M_AXI_BVALID 50 | [color] 3 51 | axilxbar.M_AXI_BREADY 52 | [color] 2 53 | axilxbar.M_AXI_BRESP[1:0] 54 | @1401200 55 | -Master write 56 | @800200 57 | -Master read 58 | @29 59 | [color] 3 60 | axilxbar.M_AXI_ARVALID 61 | @28 62 | [color] 2 63 | axilxbar.M_AXI_ARREADY 64 | @22 65 | [color] 3 66 | axilxbar.M_AXI_ARADDR[31:0] 67 | @28 68 | [color] 3 69 | axilxbar.M_AXI_ARPROT[2:0] 70 | @200 71 | - 72 | @28 73 | [color] 2 74 | axilxbar.M_AXI_RVALID 75 | [color] 3 76 | axilxbar.M_AXI_RREADY 77 | @22 78 | [color] 2 79 | axilxbar.M_AXI_RDATA[31:0] 80 | @28 81 | [color] 2 82 | axilxbar.M_AXI_RRESP[1:0] 83 | @1000200 84 | -Master read 85 | @22 86 | axilxbar.fm_awr_outstanding<0>[5:0] 87 | axilxbar.fm_wr_outstanding<0>[5:0] 88 | axilxbar.fm_rd_outstanding<0>[5:0] 89 | @28 90 | axilxbar.slave_awaccepts 91 | axilxbar.slave_raccepts 92 | axilxbar.slave_waccepts 93 | @800200 94 | -Slave write 95 | @22 96 | [color] 2 97 | axilxbar.S_AXI_AWVALID[7:0] 98 | [color] 3 99 | axilxbar.S_AXI_AWREADY[7:0] 100 | [color] 2 101 | axilxbar.S_AXI_AWADDR[255:0] 102 | [color] 2 103 | axilxbar.S_AXI_AWPROT[23:0] 104 | @200 105 | - 106 | @22 107 | [color] 2 108 | axilxbar.S_AXI_WVALID[7:0] 109 | [color] 3 110 | axilxbar.S_AXI_WREADY[7:0] 111 | [color] 2 112 | axilxbar.S_AXI_WDATA[255:0] 113 | [color] 2 114 | axilxbar.S_AXI_WSTRB[31:0] 115 | @200 116 | - 117 | @22 118 | [color] 3 119 | axilxbar.S_AXI_BVALID[7:0] 120 | [color] 2 121 | axilxbar.S_AXI_BREADY[7:0] 122 | [color] 3 123 | axilxbar.S_AXI_BRESP[15:0] 124 | @1000200 125 | -Slave write 126 | @200 127 | - 128 | @800200 129 | -Slave reads 130 | @22 131 | [color] 2 132 | axilxbar.S_AXI_ARVALID[7:0] 133 | [color] 3 134 | axilxbar.S_AXI_ARREADY[7:0] 135 | [color] 2 136 | axilxbar.S_AXI_RDATA[255:0] 137 | [color] 2 138 | axilxbar.S_AXI_ARPROT[23:0] 139 | @200 140 | - 141 | @22 142 | [color] 3 143 | axilxbar.S_AXI_RVALID[7:0] 144 | [color] 2 145 | axilxbar.S_AXI_RREADY[7:0] 146 | [color] 3 147 | axilxbar.S_AXI_RRESP[15:0] 148 | axilxbar.S_AXI_ARADDR[255:0] 149 | @1000200 150 | -Slave reads 151 | @28 152 | axilxbar.mrgrant 153 | @22 154 | axilxbar.mrindex<0>[3:0] 155 | @28 156 | axilxbar.WRITE_RETURN_CHANNEL<0>.r_bvalid 157 | axilxbar.WRITE_RETURN_CHANNEL<0>.r_bresp[1:0] 158 | axilxbar.WRITE_RETURN_CHANNEL<0>.axi_bvalid 159 | @22 160 | axilxbar.rgrant<0>[8:0] 161 | axilxbar.rrequest<0>[8:0] 162 | @28 163 | axilxbar.mrempty 164 | axilxbar.ARBITRATE_READ_REQUESTS<0>.leave_channel 165 | axilxbar.ARBITRATE_READ_REQUESTS<0>.requested_channel_is_available 166 | axilxbar.ARBITRATE_READ_REQUESTS<0>.stay_on_channel 167 | @200 168 | - 169 | @28 170 | axilxbar.mwgrant 171 | @22 172 | axilxbar.mwindex<0>[3:0] 173 | axilxbar.w_mwpending<0>[4:0] 174 | axilxbar.wrequest<0>[8:0] 175 | axilxbar.wgrant<0>[8:0] 176 | @28 177 | axilxbar.mwempty 178 | axilxbar.ARBITRATE_WRITE_REQUESTS<0>.stay_on_channel 179 | axilxbar.ARBITRATE_WRITE_REQUESTS<0>.leave_channel 180 | axilxbar.ARBITRATE_WRITE_REQUESTS<0>.requested_channel_is_available 181 | [pattern_trace] 1 182 | [pattern_trace] 0 183 | -------------------------------------------------------------------------------- /bench/formal/axim2wbsp.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D AXIM2WBSP -formal ../../rtl/axim2wbsp.v 2 | read_verilog -D AXIM2WBSP -formal ../../rtl/aximwr2wbsp.v 3 | read_verilog -D AXIM2WBSP -formal ../../rtl/aximrd2wbsp.v 4 | read_verilog -D AXIM2WBSP -formal ../../rtl/wbarbiter.v 5 | read_verilog -D AXIM2WBSP -formal fwb_master.v 6 | read_verilog -D AXIM2WBSP -formal fwb_slave.v 7 | read_verilog -D AXIM2WBSP -formal faxi_slave.v 8 | read_verilog -D AXIM2WBSP -formal f_order.v 9 | prep -top axim2wbsp -nordff 10 | write_smt2 -wires axim2wbsp.smt2 11 | -------------------------------------------------------------------------------- /bench/formal/aximrd2wbsp.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Fri Jan 25 20:03:10 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1355 914 8 | [pos] -1 -1 9 | *-6.024491 180 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] tmpaximrd. 11 | [sst_width] 196 12 | [signals_width] 174 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 265 15 | @28 16 | tmpaximrd.i_axi_reset_n 17 | tmpaximrd.i_axi_clk 18 | @200 19 | - 20 | @28 21 | [color] 3 22 | tmpaximrd.i_axi_arvalid 23 | [color] 1 24 | tmpaximrd.o_axi_arready 25 | @22 26 | [color] 3 27 | tmpaximrd.i_axi_araddr[27:0] 28 | @28 29 | [color] 3 30 | tmpaximrd.i_axi_arburst[1:0] 31 | @22 32 | [color] 3 33 | tmpaximrd.i_axi_arcache[3:0] 34 | [color] 3 35 | tmpaximrd.i_axi_arid[5:0] 36 | [color] 3 37 | tmpaximrd.i_axi_arlen[7:0] 38 | @28 39 | [color] 3 40 | tmpaximrd.i_axi_arlock 41 | [color] 3 42 | tmpaximrd.i_axi_arprot[2:0] 43 | @22 44 | [color] 3 45 | tmpaximrd.i_axi_arqos[3:0] 46 | @28 47 | [color] 3 48 | tmpaximrd.i_axi_arsize[2:0] 49 | @200 50 | - 51 | @28 52 | tmpaximrd.o_wb_cyc 53 | tmpaximrd.o_wb_stb 54 | @22 55 | tmpaximrd.o_wb_addr[25:0] 56 | @200 57 | - 58 | @28 59 | [color] 2 60 | tmpaximrd.i_wb_stall 61 | [color] 2 62 | tmpaximrd.i_wb_ack 63 | @22 64 | [color] 2 65 | tmpaximrd.i_wb_data[31:0] 66 | @28 67 | [color] 2 68 | tmpaximrd.i_wb_err 69 | @200 70 | - 71 | @28 72 | [color] 3 73 | tmpaximrd.o_axi_rvalid 74 | @29 75 | [color] 1 76 | tmpaximrd.i_axi_rready 77 | @22 78 | [color] 3 79 | tmpaximrd.o_axi_rid[5:0] 80 | [color] 3 81 | tmpaximrd.o_axi_rdata[31:0] 82 | @28 83 | [color] 3 84 | tmpaximrd.o_axi_rresp[1:0] 85 | [color] 3 86 | tmpaximrd.o_axi_rlast 87 | [pattern_trace] 1 88 | [pattern_trace] 0 89 | -------------------------------------------------------------------------------- /bench/formal/aximrd2wbsp.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | cvr: mode cover 8 | depth 40 9 | 10 | [engines] 11 | smtbmc boolector 12 | 13 | [script] 14 | read -formal skidbuffer.v 15 | read -formal sfifo.v 16 | read -formal axi_addr.v 17 | read -formal aximrd2wbsp.v 18 | read -formal fwb_master.v 19 | read -formal faxi_slave.v 20 | prep -top aximrd2wbsp 21 | 22 | 23 | [files] 24 | ../../rtl/sfifo.v 25 | ../../rtl/skidbuffer.v 26 | ../../rtl/axi_addr.v 27 | ../../rtl/aximrd2wbsp.v 28 | fwb_master.v 29 | faxi_slave.v 30 | -------------------------------------------------------------------------------- /bench/formal/axiperf.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 3 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal axiperf.v 16 | read -formal skidbuffer.v 17 | read -formal faxil_slave.v 18 | prep -top axiperf 19 | 20 | [files] 21 | ../../rtl/axiperf.v 22 | ../../rtl/skidbuffer.v 23 | faxil_slave.v 24 | -------------------------------------------------------------------------------- /bench/formal/axisbroadcast.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | prf: depth 4 7 | # cvr: mode cover 8 | # cvr: depth 40 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal sfifo.v 15 | read -formal skidbuffer.v 16 | read -formal axisbroadcast.v 17 | prep -top axisbroadcast 18 | 19 | [files] 20 | ../../rtl/axisbroadcast.v 21 | ../../rtl/sfifo.v 22 | ../../rtl/skidbuffer.v 23 | -------------------------------------------------------------------------------- /bench/formal/axisgfsm.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Fri Aug 28 23:47:05 2020 4 | [*] 5 | [dumpfile_mtime] "Fri Aug 28 22:59:36 2020" 6 | [dumpfile_size] 11128 7 | [timestart] 0 8 | [size] 1587 600 9 | [pos] -1 -1 10 | *-4.628906 50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] axisgfsm. 12 | [sst_width] 196 13 | [signals_width] 174 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 155 16 | @28 17 | axisgfsm.S_AXI_ACLK 18 | axisgfsm.S_AXI_ARESETN 19 | axisgfsm.i_start 20 | axisgfsm.i_abort 21 | axisgfsm.o_busy 22 | axisgfsm.dma_err 23 | @800200 24 | -Prefetch 25 | @28 26 | axisgfsm.o_pf_clear_cache 27 | axisgfsm.o_new_pc 28 | @22 29 | axisgfsm.o_pf_pc[29:0] 30 | @28 31 | [color] 3 32 | axisgfsm.i_pf_valid 33 | [color] 2 34 | axisgfsm.o_pf_ready 35 | @22 36 | [color] 3 37 | axisgfsm.i_pf_insn[31:0] 38 | [color] 3 39 | axisgfsm.o_pf_pc[29:0] 40 | @28 41 | [color] 3 42 | axisgfsm.i_pf_illegal 43 | @1000200 44 | -Prefetch 45 | @23 46 | axisgfsm.o_tbl_addr[29:0] 47 | @22 48 | axisgfsm.f_pc[29:0] 49 | @800200 50 | -DMA Control 51 | @22 52 | axisgfsm.f_tbladdr[29:0] 53 | @28 54 | axisgfsm.o_dmac_wvalid 55 | axisgfsm.i_dmac_wready 56 | @22 57 | axisgfsm.o_dmac_waddr[4:0] 58 | axisgfsm.o_dmac_wdata[31:0] 59 | axisgfsm.o_dmac_wstrb[3:0] 60 | axisgfsm.i_dmac_rdata[31:0] 61 | @1000200 62 | -DMA Control 63 | @22 64 | axisgfsm.SMALL_ADDRESS_SPACE.f_dma_seq[5:0] 65 | @c00022 66 | axisgfsm.f_tblentry[95:0] 67 | @28 68 | (0)axisgfsm.f_tblentry[95:0] 69 | (1)axisgfsm.f_tblentry[95:0] 70 | (2)axisgfsm.f_tblentry[95:0] 71 | (3)axisgfsm.f_tblentry[95:0] 72 | (4)axisgfsm.f_tblentry[95:0] 73 | (5)axisgfsm.f_tblentry[95:0] 74 | (6)axisgfsm.f_tblentry[95:0] 75 | (7)axisgfsm.f_tblentry[95:0] 76 | (8)axisgfsm.f_tblentry[95:0] 77 | (9)axisgfsm.f_tblentry[95:0] 78 | (10)axisgfsm.f_tblentry[95:0] 79 | (11)axisgfsm.f_tblentry[95:0] 80 | (12)axisgfsm.f_tblentry[95:0] 81 | (13)axisgfsm.f_tblentry[95:0] 82 | (14)axisgfsm.f_tblentry[95:0] 83 | (15)axisgfsm.f_tblentry[95:0] 84 | (16)axisgfsm.f_tblentry[95:0] 85 | (17)axisgfsm.f_tblentry[95:0] 86 | (18)axisgfsm.f_tblentry[95:0] 87 | (19)axisgfsm.f_tblentry[95:0] 88 | (20)axisgfsm.f_tblentry[95:0] 89 | (21)axisgfsm.f_tblentry[95:0] 90 | (22)axisgfsm.f_tblentry[95:0] 91 | (23)axisgfsm.f_tblentry[95:0] 92 | (24)axisgfsm.f_tblentry[95:0] 93 | (25)axisgfsm.f_tblentry[95:0] 94 | (26)axisgfsm.f_tblentry[95:0] 95 | (27)axisgfsm.f_tblentry[95:0] 96 | (28)axisgfsm.f_tblentry[95:0] 97 | (29)axisgfsm.f_tblentry[95:0] 98 | (30)axisgfsm.f_tblentry[95:0] 99 | (31)axisgfsm.f_tblentry[95:0] 100 | (32)axisgfsm.f_tblentry[95:0] 101 | (33)axisgfsm.f_tblentry[95:0] 102 | (34)axisgfsm.f_tblentry[95:0] 103 | (35)axisgfsm.f_tblentry[95:0] 104 | (36)axisgfsm.f_tblentry[95:0] 105 | (37)axisgfsm.f_tblentry[95:0] 106 | (38)axisgfsm.f_tblentry[95:0] 107 | (39)axisgfsm.f_tblentry[95:0] 108 | (40)axisgfsm.f_tblentry[95:0] 109 | (41)axisgfsm.f_tblentry[95:0] 110 | (42)axisgfsm.f_tblentry[95:0] 111 | (43)axisgfsm.f_tblentry[95:0] 112 | (44)axisgfsm.f_tblentry[95:0] 113 | (45)axisgfsm.f_tblentry[95:0] 114 | (46)axisgfsm.f_tblentry[95:0] 115 | (47)axisgfsm.f_tblentry[95:0] 116 | (48)axisgfsm.f_tblentry[95:0] 117 | (49)axisgfsm.f_tblentry[95:0] 118 | (50)axisgfsm.f_tblentry[95:0] 119 | (51)axisgfsm.f_tblentry[95:0] 120 | (52)axisgfsm.f_tblentry[95:0] 121 | (53)axisgfsm.f_tblentry[95:0] 122 | (54)axisgfsm.f_tblentry[95:0] 123 | (55)axisgfsm.f_tblentry[95:0] 124 | (56)axisgfsm.f_tblentry[95:0] 125 | (57)axisgfsm.f_tblentry[95:0] 126 | (58)axisgfsm.f_tblentry[95:0] 127 | (59)axisgfsm.f_tblentry[95:0] 128 | (60)axisgfsm.f_tblentry[95:0] 129 | (61)axisgfsm.f_tblentry[95:0] 130 | (62)axisgfsm.f_tblentry[95:0] 131 | (63)axisgfsm.f_tblentry[95:0] 132 | (64)axisgfsm.f_tblentry[95:0] 133 | (65)axisgfsm.f_tblentry[95:0] 134 | (66)axisgfsm.f_tblentry[95:0] 135 | (67)axisgfsm.f_tblentry[95:0] 136 | (68)axisgfsm.f_tblentry[95:0] 137 | (69)axisgfsm.f_tblentry[95:0] 138 | (70)axisgfsm.f_tblentry[95:0] 139 | (71)axisgfsm.f_tblentry[95:0] 140 | (72)axisgfsm.f_tblentry[95:0] 141 | (73)axisgfsm.f_tblentry[95:0] 142 | (74)axisgfsm.f_tblentry[95:0] 143 | (75)axisgfsm.f_tblentry[95:0] 144 | (76)axisgfsm.f_tblentry[95:0] 145 | (77)axisgfsm.f_tblentry[95:0] 146 | (78)axisgfsm.f_tblentry[95:0] 147 | (79)axisgfsm.f_tblentry[95:0] 148 | (80)axisgfsm.f_tblentry[95:0] 149 | (81)axisgfsm.f_tblentry[95:0] 150 | (82)axisgfsm.f_tblentry[95:0] 151 | (83)axisgfsm.f_tblentry[95:0] 152 | (84)axisgfsm.f_tblentry[95:0] 153 | (85)axisgfsm.f_tblentry[95:0] 154 | (86)axisgfsm.f_tblentry[95:0] 155 | (87)axisgfsm.f_tblentry[95:0] 156 | (88)axisgfsm.f_tblentry[95:0] 157 | (89)axisgfsm.f_tblentry[95:0] 158 | (90)axisgfsm.f_tblentry[95:0] 159 | (91)axisgfsm.f_tblentry[95:0] 160 | (92)axisgfsm.f_tblentry[95:0] 161 | (93)axisgfsm.f_tblentry[95:0] 162 | (94)axisgfsm.f_tblentry[95:0] 163 | (95)axisgfsm.f_tblentry[95:0] 164 | @1401200 165 | -group_end 166 | @28 167 | axisgfsm.f_dma_busy 168 | axisgfsm.dma_abort 169 | axisgfsm.dma_busy 170 | axisgfsm.dma_done 171 | axisgfsm.dma_err 172 | axisgfsm.o_busy 173 | axisgfsm.o_done 174 | axisgfsm.o_err 175 | axisgfsm.o_int 176 | axisgfsm.f_dma_complete 177 | axisgfsm.i_dma_complete 178 | @200 179 | - 180 | @28 181 | axisgfsm.sgstate[2:0] 182 | @200 183 | - 184 | @28 185 | axisgfsm.f_dma_busy 186 | axisgfsm.f_dma_complete 187 | axisgfsm.f_past_valid 188 | axisgfsm.i_dma_complete 189 | axisgfsm.i_pf_illegal 190 | @22 191 | axisgfsm.i_pf_insn[31:0] 192 | @28 193 | axisgfsm.i_pf_valid 194 | @c00028 195 | axisgfsm.i_prot[2:0] 196 | @28 197 | (0)axisgfsm.i_prot[2:0] 198 | (1)axisgfsm.i_prot[2:0] 199 | (2)axisgfsm.i_prot[2:0] 200 | @1401200 201 | -group_end 202 | @22 203 | axisgfsm.i_qos[3:0] 204 | axisgfsm.r_pf_pc[59:0] 205 | @28 206 | axisgfsm.tbl_int_enable 207 | axisgfsm.tbl_last 208 | [pattern_trace] 1 209 | [pattern_trace] 0 210 | -------------------------------------------------------------------------------- /bench/formal/axisgfsm.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 4 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal axisgfsm.v 16 | read -formal faxil_master.v 17 | # --pycode-begin-- 18 | # cmd = "hierarchy -top easyaxil" 19 | # cmd += " -chparam OPT_SKIDBUFFER %d" % (1 if "opt_skidbuffer" in tags else 0) 20 | # cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 21 | # output(cmd); 22 | # --pycode-end-- 23 | prep -top axisgfsm 24 | 25 | [files] 26 | ../../rtl/axisgfsm.v 27 | faxil_master.v 28 | -------------------------------------------------------------------------------- /bench/formal/axispacker.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Mon Jun 28 12:15:13 2021 4 | [*] 5 | [dumpfile_mtime] "Mon Jun 28 02:19:53 2021" 6 | [dumpfile_size] 6992 7 | [timestart] 0 8 | [size] 1719 900 9 | [pos] 2837 -591 10 | *-6.075490 400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 329 12 | [signals_width] 220 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 248 15 | @28 16 | axispacker.S_AXI_ACLK 17 | axispacker.S_AXI_ARESETN 18 | @200 19 | - 20 | @28 21 | axispacker.S_AXIS_TVALID 22 | axispacker.S_AXIS_TREADY 23 | @22 24 | axispacker.S_AXIS_TDATA[31:0] 25 | axispacker.S_AXIS_TSTRB[3:0] 26 | axispacker.S_AXIS_TKEEP[3:0] 27 | @28 28 | axispacker.S_AXIS_TLAST 29 | @200 30 | - 31 | @28 32 | axispacker.M_AXIS_TVALID 33 | axispacker.M_AXIS_TREADY 34 | @22 35 | axispacker.M_AXIS_TDATA[31:0] 36 | axispacker.M_AXIS_TSTRB[3:0] 37 | axispacker.M_AXIS_TKEEP[3:0] 38 | @28 39 | axispacker.M_AXIS_TLAST 40 | @200 41 | - 42 | @28 43 | axispacker.pre_tvalid 44 | axispacker.pre_tready 45 | @22 46 | axispacker.pre_tdata[31:0] 47 | axispacker.pre_tstrb[3:0] 48 | axispacker.pre_tkeep[3:0] 49 | @29 50 | axispacker.pre_tlast 51 | @200 52 | - 53 | @22 54 | axispacker.pck_tdata[31:0] 55 | axispacker.pck_tkeep[3:0] 56 | axispacker.pck_tstrb[3:0] 57 | @28 58 | axispacker.pck_tlast 59 | @200 60 | - 61 | @22 62 | axispacker.mid_fill[3:0] 63 | axispacker.mid_keep[3:0] 64 | axispacker.mid_data[31:0] 65 | axispacker.mid_strb[3:0] 66 | @28 67 | axispacker.mid_last 68 | @200 69 | - 70 | @22 71 | axispacker.w_packed_data[63:0] 72 | axispacker.w_packed_keep[7:0] 73 | axispacker.w_packed_strb[7:0] 74 | @200 75 | - 76 | @22 77 | axispacker.skd_data[31:0] 78 | axispacker.skd_keep[3:0] 79 | @28 80 | axispacker.skd_last 81 | @22 82 | axispacker.skd_strb[3:0] 83 | @28 84 | axispacker.skd_valid 85 | [pattern_trace] 1 86 | [pattern_trace] 0 87 | -------------------------------------------------------------------------------- /bench/formal/axispacker.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 4 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | # read -formal skidbuffer.v 16 | read -formal axispacker.v 17 | prep -top axispacker 18 | 19 | [files] 20 | ../../rtl/axispacker.v 21 | # ../../rtl/skidbuffer.v 22 | -------------------------------------------------------------------------------- /bench/formal/axisrandom.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | prf: depth 3 7 | # cvr: mode cover 8 | # cvr: depth 40 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal axisrandom.v 15 | prep -top axisrandom 16 | 17 | [files] 18 | ../../rtl/axisrandom.v 19 | -------------------------------------------------------------------------------- /bench/formal/axissafety.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Sat Sep 26 21:22:11 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1468 599 7 | [pos] -1 -1 8 | *-6.594141 56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [treeopen] axissafety. 10 | [sst_width] 196 11 | [signals_width] 206 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 155 14 | @28 15 | axissafety.S_AXI_ACLK 16 | axissafety.S_AXI_ARESETN 17 | @800200 18 | -Incoming slave 19 | @28 20 | axissafety.S_AXIS_TVALID 21 | axissafety.S_AXIS_TREADY 22 | @22 23 | axissafety.S_AXIS_TDATA[7:0] 24 | @28 25 | axissafety.S_AXIS_TLAST 26 | axissafety.S_AXIS_TUSER 27 | @1000200 28 | -Incoming slave 29 | @c00200 30 | -Skid buffer 31 | @28 32 | axissafety.skd_valid 33 | axissafety.skd_ready 34 | @22 35 | axissafety.skd_data[7:0] 36 | @28 37 | axissafety.skd_last 38 | axissafety.skd_user 39 | axissafety.skdr_valid 40 | @1401200 41 | -Skid buffer 42 | @800200 43 | -Outgoing master 44 | @28 45 | axissafety.M_AXIS_TVALID 46 | axissafety.M_AXIS_TREADY 47 | @22 48 | axissafety.M_AXIS_TDATA[7:0] 49 | @28 50 | axissafety.M_AXIS_TLAST 51 | axissafety.M_AXIS_TUSER 52 | @1000200 53 | -Outgoing master 54 | @28 55 | axissafety.m_end_of_packet 56 | @c00200 57 | -Faults 58 | @28 59 | axissafety.r_stalled 60 | axissafety.change_fault 61 | axissafety.packet_fault 62 | axissafety.stall_fault 63 | axissafety.o_fault 64 | @1401200 65 | -Faults 66 | @28 67 | axissafety.fm_packet_counter[2:0] 68 | axissafety.fs_packet_counter[2:0] 69 | axissafety.m_packet_count[2:0] 70 | axissafety.s_packet_counter[2:0] 71 | [pattern_trace] 1 72 | [pattern_trace] 0 73 | -------------------------------------------------------------------------------- /bench/formal/axissafety.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfr prf opt_reset 4 | prfrpkt prf opt_reset opt_packet 5 | prfpkt prf opt_packet 6 | prfs prf opt_mxstall 7 | prfrs prf opt_reset opt_mxstall 8 | prfrpkts prf opt_reset opt_packet opt_mxstall 9 | prfpkts prf opt_packet opt_mxstall 10 | fault prf 11 | faultr fault prf opt_reset 12 | faultrpkt fault prf opt_reset opt_packet 13 | faultpkt fault prf opt_packet 14 | faults fault prf opt_mxstall 15 | faultrs fault prf opt_reset opt_mxstall 16 | faultrpkts fault prf opt_reset opt_packet opt_mxstall 17 | faultpkts fault prf opt_packet opt_mxstall 18 | cvr fault opt_reset opt_packet opt_mxstall 19 | cvrnopkt cvr fault opt_reset opt_mxstall 20 | 21 | [options] 22 | prf: mode prove 23 | prf: depth 4 24 | cvr: mode cover 25 | cvr: depth 32 26 | 27 | [engines] 28 | smtbmc 29 | 30 | [script] 31 | read -formal axissafety.v 32 | --pycode-begin-- 33 | cmd = "hierarchy -top axissafety" 34 | cmd += " -chparam F_OPT_FAULTLESS %d" % ( 0 if "fault" in tags else 1) 35 | cmd += " -chparam OPT_SELF_RESET %d" % ( 1 if "opt_reset" in tags else 0) 36 | cmd += " -chparam OPT_PACKET_LENGTH %d" % ( 5 if "opt_packet" in tags else 0) 37 | cmd += " -chparam OPT_MAX_STALL %d" % (10 if "opt_mxstall" in tags else 0) 38 | output(cmd) 39 | --pycode-end-- 40 | prep -top axissafety 41 | 42 | [files] 43 | ../../rtl/axissafety.v 44 | -------------------------------------------------------------------------------- /bench/formal/axisswitch.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Aug 27 22:04:38 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [size] 1303 600 7 | [pos] -1 -1 8 | *-4.190785 35 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 196 10 | [signals_width] 198 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 155 13 | @28 14 | axisswitch.S_AXI_ACLK 15 | axisswitch.S_AXI_ARESETN 16 | @800200 17 | -Outgoing stream 18 | @28 19 | axisswitch.M_AXIS_TVALID 20 | axisswitch.M_AXIS_TREADY 21 | @22 22 | axisswitch.M_AXIS_TDATA[31:0] 23 | @28 24 | axisswitch.M_AXIS_TLAST 25 | @1000200 26 | -Outgoing stream 27 | @800200 28 | -Incoming streams 29 | @22 30 | axisswitch.S_AXIS_TVALID[3:0] 31 | axisswitch.S_AXIS_TREADY[3:0] 32 | axisswitch.S_AXIS_TDATA[127:0] 33 | axisswitch.S_AXIS_TLAST[3:0] 34 | @1000200 35 | -Incoming streams 36 | @c00201 37 | -AXI-Lite control 38 | @28 39 | axisswitch.S_AXI_AWVALID 40 | axisswitch.S_AXI_AWREADY 41 | @200 42 | - 43 | @28 44 | axisswitch.S_AXI_WVALID 45 | axisswitch.S_AXI_WREADY 46 | @22 47 | axisswitch.S_AXI_WDATA[31:0] 48 | axisswitch.S_AXI_WSTRB[3:0] 49 | @28 50 | axisswitch.S_AXI_BREADY 51 | axisswitch.S_AXI_BVALID 52 | @200 53 | - 54 | @28 55 | axisswitch.S_AXI_ARVALID 56 | axisswitch.S_AXI_ARREADY 57 | @200 58 | - 59 | @28 60 | axisswitch.S_AXI_RVALID 61 | axisswitch.S_AXI_RREADY 62 | @22 63 | axisswitch.S_AXI_RDATA[31:0] 64 | @1401201 65 | -AXI-Lite control 66 | @22 67 | axisswitch.skd_valid[3:0] 68 | axisswitch.skd_switch_ready[3:0] 69 | @28 70 | axisswitch.r_index[1:0] 71 | axisswitch.switch_index[1:0] 72 | axisswitch.f_const_index[1:0] 73 | axisswitch.f_this_index[1:0] 74 | @22 75 | axisswitch.f_count[3:0] 76 | axisswitch.f_recount[3:0] 77 | @28 78 | axisswitch.f_accepts 79 | axisswitch.f_delivers 80 | [pattern_trace] 1 81 | [pattern_trace] 0 82 | -------------------------------------------------------------------------------- /bench/formal/axisswitch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | # cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 3 8 | # cvr: mode cover 9 | # cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal axisswitch.v 16 | read -formal skidbuffer.v 17 | read -formal faxil_slave.v 18 | # --pycode-begin-- 19 | # cmd = "hierarchy -top easyaxil" 20 | # cmd += " -chparam OPT_SKIDBUFFER %d" % (1 if "opt_skidbuffer" in tags else 0) 21 | # cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 22 | # output(cmd); 23 | # --pycode-end-- 24 | prep -top axisswitch 25 | 26 | [files] 27 | ../../rtl/axisswitch.v 28 | ../../rtl/skidbuffer.v 29 | faxil_slave.v 30 | -------------------------------------------------------------------------------- /bench/formal/axlite2wbsp.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Fri Dec 28 11:45:02 2018 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1021 8 | [pos] -1 -1 9 | *-6.124164 160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] axlite2wbsp. 11 | [treeopen] axlite2wbsp.ARB_WB. 12 | [treeopen] axlite2wbsp.AXI_RD. 13 | [treeopen] axlite2wbsp.AXI_RD.axi_read_decoder. 14 | [treeopen] axlite2wbsp.AXI_WR. 15 | [treeopen] axlite2wbsp.AXI_WR.axi_write_decoder. 16 | [sst_width] 270 17 | [signals_width] 210 18 | [sst_expanded] 1 19 | [sst_vpaned_height] 290 20 | @28 21 | [color] 3 22 | axlite2wbsp.i_axi_reset_n 23 | [color] 3 24 | axlite2wbsp.o_reset 25 | [color] 3 26 | axlite2wbsp.i_clk 27 | @200 28 | - 29 | @28 30 | [color] 2 31 | axlite2wbsp.i_axi_awvalid 32 | [color] 2 33 | axlite2wbsp.o_axi_awready 34 | @22 35 | [color] 2 36 | axlite2wbsp.i_axi_awaddr[27:0] 37 | @c00022 38 | [color] 2 39 | axlite2wbsp.i_axi_awcache[3:0] 40 | @28 41 | (0)axlite2wbsp.i_axi_awcache[3:0] 42 | (1)axlite2wbsp.i_axi_awcache[3:0] 43 | (2)axlite2wbsp.i_axi_awcache[3:0] 44 | (3)axlite2wbsp.i_axi_awcache[3:0] 45 | @1401200 46 | -group_end 47 | @28 48 | [color] 2 49 | axlite2wbsp.i_axi_awprot[2:0] 50 | @200 51 | - 52 | @28 53 | [color] 2 54 | axlite2wbsp.i_axi_wvalid 55 | [color] 2 56 | axlite2wbsp.o_axi_wready 57 | @22 58 | [color] 2 59 | axlite2wbsp.i_axi_wdata[31:0] 60 | [color] 2 61 | axlite2wbsp.i_axi_wstrb[3:0] 62 | @28 63 | [color] 2 64 | axlite2wbsp.AXI_WR.axi_write_decoder.err_state 65 | @200 66 | - 67 | @28 68 | [color] 3 69 | axlite2wbsp.o_axi_bvalid 70 | [color] 3 71 | axlite2wbsp.i_axi_bready 72 | [color] 3 73 | axlite2wbsp.o_axi_bresp[1:0] 74 | @200 75 | - 76 | @28 77 | axlite2wbsp.i_axi_arvalid 78 | axlite2wbsp.o_axi_arready 79 | @22 80 | axlite2wbsp.i_axi_araddr[27:0] 81 | axlite2wbsp.i_axi_arcache[3:0] 82 | @28 83 | axlite2wbsp.i_axi_arprot[2:0] 84 | @200 85 | - 86 | @28 87 | [color] 2 88 | axlite2wbsp.o_axi_rvalid 89 | [color] 2 90 | axlite2wbsp.i_axi_rready 91 | @22 92 | [color] 2 93 | axlite2wbsp.o_axi_rdata[31:0] 94 | @28 95 | [color] 2 96 | axlite2wbsp.o_axi_rresp[1:0] 97 | [color] 2 98 | axlite2wbsp.AXI_RD.axi_read_decoder.err_state 99 | @200 100 | - 101 | @28 102 | axlite2wbsp.o_wb_cyc 103 | axlite2wbsp.o_wb_stb 104 | axlite2wbsp.o_wb_we 105 | @22 106 | axlite2wbsp.o_wb_addr[25:0] 107 | axlite2wbsp.o_wb_data[31:0] 108 | axlite2wbsp.o_wb_sel[3:0] 109 | @28 110 | [color] 2 111 | axlite2wbsp.i_wb_stall 112 | [color] 2 113 | axlite2wbsp.i_wb_ack 114 | @22 115 | [color] 2 116 | axlite2wbsp.i_wb_data[31:0] 117 | @28 118 | [color] 2 119 | axlite2wbsp.i_wb_err 120 | [pattern_trace] 1 121 | [pattern_trace] 0 122 | -------------------------------------------------------------------------------- /bench/formal/axlite2wbsp.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr 3 | prf 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 5 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D AXLITE2WBSP axlite2wbsp.v 16 | read -formal -D AXLITE2WBSP axilrd2wbsp.v 17 | read -formal -D AXLITE2WBSP axilwr2wbsp.v 18 | read -formal -D AXLITE2WBSP wbarbiter.v 19 | read -formal -D AXLITE2WBSP faxil_slave.v 20 | read -formal -D AXLITE2WBSP fwb_master.v 21 | read -formal -D AXLITE2WBSP fwb_slave.v 22 | prep -top axlite2wbsp 23 | 24 | [files] 25 | ../../rtl/axlite2wbsp.v 26 | ../../rtl/axilrd2wbsp.v 27 | ../../rtl/axilwr2wbsp.v 28 | ../../rtl/wbarbiter.v 29 | faxil_slave.v 30 | fwb_master.v 31 | fwb_slave.v 32 | -------------------------------------------------------------------------------- /bench/formal/demoaxi.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Wed Dec 26 15:57:11 2018 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Wed Dec 26 15:51:31 2018" 7 | [dumpfile_size] 26484 8 | [timestart] 0 9 | [size] 1600 600 10 | [pos] -1 -1 11 | *-6.254814 180 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [sst_width] 270 13 | [signals_width] 200 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 143 16 | @29 17 | [color] 3 18 | demoaxi.S_AXI_ARESETN 19 | [color] 3 20 | demoaxi.S_AXI_ACLK 21 | @200 22 | - 23 | @28 24 | demoaxi.S_AXI_AWVALID 25 | demoaxi.S_AXI_AWREADY 26 | @22 27 | demoaxi.S_AXI_AWADDR[7:0] 28 | @28 29 | demoaxi.S_AXI_AWPROT[2:0] 30 | @200 31 | - 32 | @28 33 | demoaxi.S_AXI_WVALID 34 | demoaxi.S_AXI_WREADY 35 | @22 36 | demoaxi.S_AXI_WDATA[31:0] 37 | demoaxi.S_AXI_WSTRB[3:0] 38 | @200 39 | - 40 | @28 41 | [color] 2 42 | demoaxi.S_AXI_BVALID 43 | [color] 2 44 | demoaxi.S_AXI_BREADY 45 | [color] 2 46 | demoaxi.S_AXI_BRESP[1:0] 47 | @200 48 | - 49 | @28 50 | demoaxi.S_AXI_ARVALID 51 | demoaxi.S_AXI_ARREADY 52 | @22 53 | demoaxi.S_AXI_ARADDR[7:0] 54 | @28 55 | demoaxi.S_AXI_ARPROT[2:0] 56 | @200 57 | - 58 | @28 59 | [color] 2 60 | demoaxi.S_AXI_RVALID 61 | [color] 2 62 | demoaxi.S_AXI_RREADY 63 | @22 64 | [color] 2 65 | demoaxi.S_AXI_RDATA[31:0] 66 | @28 67 | [color] 2 68 | demoaxi.S_AXI_RRESP[1:0] 69 | [pattern_trace] 1 70 | [pattern_trace] 0 71 | -------------------------------------------------------------------------------- /bench/formal/demoaxi.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 14 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal demoaxi.v 16 | read -formal faxil_slave.v 17 | prep -top demoaxi 18 | 19 | [files] 20 | ../../rtl/demoaxi.v 21 | faxil_slave.v 22 | -------------------------------------------------------------------------------- /bench/formal/easyaxil.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Thu Mar 5 18:47:26 2020 4 | [*] 5 | [dumpfile_mtime] "Thu Mar 5 18:41:39 2020" 6 | [dumpfile_size] 18650 7 | [timestart] 0 8 | [size] 1920 1021 9 | [pos] -919 -1 10 | *-5.333901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 270 12 | [signals_width] 200 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 287 15 | @28 16 | easyaxil.S_AXI_ACLK 17 | easyaxil.S_AXI_ARESETN 18 | @200 19 | - 20 | @28 21 | [color] 3 22 | easyaxil.S_AXI_AWVALID 23 | [color] 2 24 | easyaxil.S_AXI_AWREADY 25 | @22 26 | [color] 3 27 | easyaxil.S_AXI_AWADDR[3:0] 28 | [color] 3 29 | easyaxil.S_AXI_AWPROT[3:0] 30 | @200 31 | - 32 | @28 33 | [color] 3 34 | easyaxil.S_AXI_WVALID 35 | [color] 2 36 | easyaxil.S_AXI_WREADY 37 | @22 38 | [color] 3 39 | easyaxil.S_AXI_WDATA[31:0] 40 | [color] 3 41 | easyaxil.S_AXI_WSTRB[3:0] 42 | @200 43 | - 44 | @28 45 | [color] 2 46 | easyaxil.S_AXI_BVALID 47 | [color] 3 48 | easyaxil.S_AXI_BREADY 49 | [color] 2 50 | easyaxil.S_AXI_BRESP[1:0] 51 | @200 52 | - 53 | @28 54 | [color] 3 55 | easyaxil.S_AXI_ARVALID 56 | [color] 2 57 | easyaxil.S_AXI_ARREADY 58 | @22 59 | [color] 3 60 | easyaxil.S_AXI_ARADDR[3:0] 61 | [color] 3 62 | easyaxil.S_AXI_ARPROT[3:0] 63 | @200 64 | - 65 | @28 66 | [color] 2 67 | easyaxil.S_AXI_RVALID 68 | [color] 3 69 | easyaxil.S_AXI_RREADY 70 | @22 71 | [color] 2 72 | easyaxil.S_AXI_RDATA[31:0] 73 | @28 74 | [color] 2 75 | easyaxil.S_AXI_RRESP[1:0] 76 | @201 77 | - 78 | @28 79 | easyaxil.axil_read_ready 80 | easyaxil.axil_write_ready 81 | [pattern_trace] 1 82 | [pattern_trace] 0 83 | -------------------------------------------------------------------------------- /bench/formal/easyaxil.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prfreg prf 3 | cvrreg cvr 4 | prfskd prf opt_skidbuffer 5 | cvrskd cvr opt_skidbuffer 6 | prfreglp prf opt_lowpower 7 | prfskdlp prf opt_skidbuffer opt_lowpower 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 3 12 | cvr: mode cover 13 | cvr: depth 40 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | read -formal easyaxil.v 20 | opt_skidbuffer: read -formal skidbuffer.v 21 | read -formal faxil_register.v 22 | read -formal faxil_slave.v 23 | --pycode-begin-- 24 | cmd = "hierarchy -top easyaxil" 25 | cmd += " -chparam OPT_SKIDBUFFER %d" % (1 if "opt_skidbuffer" in tags else 0) 26 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 27 | output(cmd); 28 | --pycode-end-- 29 | prep -top easyaxil 30 | 31 | [files] 32 | ../../rtl/easyaxil.v 33 | opt_skidbuffer: ../../rtl/skidbuffer.v 34 | faxil_slave.v 35 | faxil_register.v 36 | -------------------------------------------------------------------------------- /bench/formal/faxi_addr.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/formal/faxi_addr.v 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: The AXI (full) standard has some rather complicated addressing 8 | // modes, where the address can either be FIXED, INCRementing, or 9 | // even where it can WRAP around some boundary. When in either INCR or 10 | // WRAP modes, the next address must always be aligned. In WRAP mode, 11 | // the next address calculation needs to wrap around a given value, and 12 | // that value is dependent upon the burst size (i.e. bytes per beat) and 13 | // length (total numbers of beats). Since this calculation can be 14 | // non-trivial, and since it needs to be done multiple times, the logic 15 | // below captures it for every time it might be needed. 16 | // 17 | // Creator: Dan Gisselquist, Ph.D. 18 | // Gisselquist Technology, LLC 19 | // 20 | //////////////////////////////////////////////////////////////////////////////// 21 | // }}} 22 | // Copyright (C) 2019-2025, Gisselquist Technology, LLC 23 | // {{{ 24 | // This file is part of the WB2AXIP project. 25 | // 26 | // The WB2AXIP project contains free software and gateware, licensed under the 27 | // Apache License, Version 2.0 (the "License"). You may not use this project, 28 | // or this file, except in compliance with the License. You may obtain a copy 29 | // of the License at 30 | // }}} 31 | // http://www.apache.org/licenses/LICENSE-2.0 32 | // {{{ 33 | // Unless required by applicable law or agreed to in writing, software 34 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 35 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 36 | // License for the specific language governing permissions and limitations 37 | // under the License. 38 | // 39 | //////////////////////////////////////////////////////////////////////////////// 40 | // 41 | `default_nettype none 42 | // }}} 43 | module faxi_addr #( 44 | // {{{ 45 | parameter AW=32 46 | // }}} 47 | ) ( 48 | // {{{ 49 | input wire [AW-1:0] i_last_addr, 50 | input wire [2:0] i_size, // 1b, 2b, 4b, 8b, etc 51 | input wire [1:0] i_burst, // fixed, incr, wrap, reserved 52 | input wire [7:0] i_len, 53 | output reg [7:0] o_incr, 54 | output reg [AW-1:0] o_next_addr 55 | // }}} 56 | ); 57 | 58 | (* keep *) reg [AW-1:0] wrap_mask, increment; 59 | 60 | // increment 61 | // {{{ 62 | always @(*) 63 | begin 64 | increment = 0; 65 | if (i_burst != 0) 66 | begin 67 | // verilator lint_off WIDTH 68 | case(i_size) 69 | 0: increment = 1; 70 | 1: increment = 2; 71 | 2: increment = 4; 72 | 3: increment = 8; 73 | 4: increment = 16; 74 | 5: increment = 32; 75 | 6: increment = 64; 76 | 7: increment = 128; 77 | default: increment = 0; 78 | endcase 79 | // verilator lint_on WIDTH 80 | end 81 | end 82 | // }}} 83 | 84 | // wrap_mask 85 | // {{{ 86 | always @(*) 87 | begin 88 | wrap_mask = 0; 89 | if (i_burst == 2'b10) 90 | begin 91 | if (i_len == 1) 92 | wrap_mask = (1<<(i_size+1)); 93 | else if (i_len == 3) 94 | wrap_mask = (1<<(i_size+2)); 95 | else if (i_len == 7) 96 | wrap_mask = (1<<(i_size+3)); 97 | else if (i_len == 15) 98 | wrap_mask = (1<<(i_size+4)); 99 | wrap_mask = wrap_mask - 1; 100 | end 101 | end 102 | // }}} 103 | 104 | // o_next_addr 105 | // {{{ 106 | always @(*) 107 | begin 108 | o_next_addr = i_last_addr + increment; 109 | if (i_burst != 2'b00) 110 | begin 111 | // Align any subsequent address 112 | // verilator lint_off SELRANGE 113 | if(i_size == 1) 114 | o_next_addr[0] = 0; 115 | else if ((i_size == 2)&&(AW>=2)) 116 | o_next_addr[1:0] = 0; 117 | else if ((i_size == 3)&&(AW>=3)) 118 | o_next_addr[2:0] = 0; 119 | else if ((i_size == 4)&&(AW>=4)) 120 | o_next_addr[3:0] = 0; 121 | else if ((i_size == 5)&&(AW>=5)) 122 | o_next_addr[4:0] = 0; 123 | else if ((i_size == 6)&&(AW>=6)) 124 | o_next_addr[((AW>6)?5:AW-1):0] = 0; 125 | else if ((i_size == 7)&&(AW>=7)) 126 | o_next_addr[((AW>7)?6:AW-1):0] = 0; 127 | // verilator lint_on SELRANGE 128 | end 129 | if (i_burst == 2'b10) 130 | begin 131 | // WRAP! 132 | o_next_addr[AW-1:0] = (i_last_addr & ~wrap_mask) 133 | | (o_next_addr & wrap_mask); 134 | end 135 | end 136 | // }}} 137 | 138 | // o_incr 139 | // {{{ 140 | always @(*) 141 | begin 142 | o_incr = 0; 143 | o_incr[((AW>7)?7:AW-1):0] = increment[((AW>7)?7:AW-1):0]; 144 | end 145 | // }}} 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /bench/formal/fwb_register.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/formal/fwb_register.v 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: While it may be fairly easy to verify that a core follows the 8 | // bus protocol, it's another thing to prove that the answers it 9 | // returns are the right ones. 10 | // 11 | // This core is meant to be a complement to the fwb_slave logic, for slaves 12 | // that consist of a series of registers. This core will test whether a 13 | // register can be written to using Wishbone, and/or read back properly 14 | // later. It assumes a register having a single clock latency. 15 | // 16 | // Creator: Dan Gisselquist, Ph.D. 17 | // Gisselquist Technology, LLC 18 | // 19 | //////////////////////////////////////////////////////////////////////////////// 20 | // }}} 21 | // Copyright (C) 2019-2025, Gisselquist Technology, LLC 22 | // {{{ 23 | // This file is part of the WB2AXIP project. 24 | // 25 | // The WB2AXIP project contains free software and gateware, licensed under the 26 | // Apache License, Version 2.0 (the "License"). You may not use this project, 27 | // or this file, except in compliance with the License. You may obtain a copy 28 | // of the License at 29 | // }}} 30 | // http://www.apache.org/licenses/LICENSE-2.0 31 | // {{{ 32 | // Unless required by applicable law or agreed to in writing, software 33 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 34 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 35 | // License for the specific language governing permissions and limitations 36 | // under the License. 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | `default_nettype none 41 | // }}} 42 | module fwb_register #( 43 | // {{{ 44 | parameter AW = 4, 45 | parameter DW = 32, 46 | parameter [AW-1:0] ADDR = 0, 47 | parameter [DW-1:0] MASK = -1 48 | // }}} 49 | ) ( 50 | // {{{ 51 | input wire i_clk, i_reset, 52 | // 53 | input wire i_wb_stb, i_wb_we, 54 | input wire [AW-1:0] i_wb_addr, 55 | input wire [DW-1:0] i_wb_data, 56 | input wire [DW/8-1:0] i_wb_sel, 57 | input wire i_wb_ack, 58 | input wire [DW-1:0] i_wb_return, 59 | input wire [DW-1:0] i_register 60 | // }}} 61 | ); 62 | 63 | // Local register, reset assumption 64 | // {{{ 65 | reg f_past_valid; 66 | reg [31:0] freg; 67 | 68 | initial f_past_valid = 0; 69 | always @(posedge i_clk) 70 | f_past_valid <= 1; 71 | 72 | always @(*) 73 | if (!f_past_valid) 74 | assume(i_reset); 75 | // }}} 76 | 77 | // freg 78 | // {{{ 79 | always @(posedge i_clk or posedge i_reset) 80 | if (i_reset) 81 | freg <= i_register; 82 | else if (i_wb_stb && i_wb_we && i_wb_addr == ADDR) 83 | begin 84 | if (i_wb_sel[0]) 85 | freg[ 7: 0] <= i_wb_data[ 7: 0]; 86 | if (i_wb_sel[1]) 87 | freg[15: 8] <= i_wb_data[15: 8]; 88 | if (i_wb_sel[2]) 89 | freg[23:16] <= i_wb_data[23:16]; 90 | if (i_wb_sel[3]) 91 | freg[31:24] <= i_wb_data[31:24]; 92 | end 93 | // }}} 94 | 95 | // Comparing freg against i_register 96 | // {{{ 97 | always @(posedge i_clk) 98 | if (!i_reset) 99 | assert(((freg ^ i_register) & MASK) == 0); 100 | // }}} 101 | 102 | // Verifying wb_ack 103 | // {{{ 104 | always @(posedge i_clk) 105 | if (!i_reset && $past(!i_reset && i_wb_stb)) 106 | assert(i_wb_ack); 107 | else if (!i_reset) 108 | assert(!i_wb_ack); 109 | // }}} 110 | 111 | // Verifying i_wb_return 112 | // {{{ 113 | always @(posedge i_clk) 114 | if (!i_reset && $past(!i_reset && i_wb_stb && !i_wb_we 115 | && i_wb_addr == ADDR)) 116 | assert(i_wb_return == $past(i_register)); 117 | // }}} 118 | 119 | endmodule 120 | -------------------------------------------------------------------------------- /bench/formal/passcheck.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ################################################################################ 3 | ## 4 | ## Filename: passcheck.sh 5 | ## 6 | ## Project: WB2AXIPSP: bus bridges and other odds and ends 7 | ## 8 | ## Purpose: This script simply checks for failing proofs of any type, 9 | ## printing out the files associated with any such failing proofs. 10 | ## 11 | ## Creator: Dan Gisselquist, Ph.D. 12 | ## Gisselquist Technology, LLC 13 | ## 14 | ################################################################################ 15 | ## 16 | ## This simple bash script is herein donated to the public domain 17 | ## 18 | ################################################################################ 19 | ## 20 | ## 21 | ## Sort these results to give them a consistent order 22 | ## 23 | find . -name FAIL | sort 24 | find . -name UNKNOWN | sort 25 | find . -name ERROR | sort 26 | -------------------------------------------------------------------------------- /bench/formal/sfifo.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf prf 3 | prf_r prf opt_read_on_empty 4 | prf_w prf opt_write_on_full 5 | prf_wr prf opt_read_on_empty opt_write_on_full 6 | prf_a prf opt_async_read 7 | prf_ar prf opt_async_read opt_read_on_empty 8 | prf_aw prf opt_async_read opt_write_on_full 9 | prf_awr prf opt_async_read opt_read_on_empty opt_write_on_full 10 | cvr 11 | 12 | [options] 13 | cvr: mode cover 14 | cvr: depth 22 15 | prf: mode prove 16 | prf: depth 4 17 | 18 | [engines] 19 | smtbmc 20 | 21 | [script] 22 | read -define SFIFO 23 | read -formal sfifo.v 24 | --pycode-begin-- 25 | cmd = "hierarchy -top sfifo" 26 | cmd += " -chparam OPT_ASYNC_READ %d" % ( 1 if "opt_async_read" in tags else 0) 27 | cmd += " -chparam OPT_WRITE_ON_FULL %d" % ( 1 if "opt_write_on_full" in tags else 0) 28 | cmd += " -chparam OPT_READ_ON_EMPTY %d" % ( 1 if "opt_read_on_empty" in tags else 0) 29 | output(cmd) 30 | --pycode-end-- 31 | prep -top sfifo 32 | 33 | [files] 34 | ../../rtl/sfifo.v 35 | -------------------------------------------------------------------------------- /bench/formal/skidbuffer.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Tue May 14 23:56:06 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Tue May 14 23:30:00 2019" 7 | [dumpfile_size] 3009 8 | [timestart] 0 9 | [size] 1177 600 10 | [pos] -1 -1 11 | *-5.436488 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [sst_width] 270 13 | [signals_width] 170 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 143 16 | @28 17 | skidbuffer.i_clk 18 | skidbuffer.i_reset 19 | @200 20 | - 21 | @28 22 | [color] 3 23 | skidbuffer.i_valid 24 | [color] 2 25 | skidbuffer.o_ready 26 | @22 27 | [color] 3 28 | skidbuffer.i_data[7:0] 29 | @200 30 | - 31 | @28 32 | skidbuffer.r_valid 33 | @22 34 | skidbuffer.r_data[7:0] 35 | @200 36 | - 37 | @22 38 | skidbuffer.next_data[7:0] 39 | @200 40 | - 41 | @28 42 | [color] 2 43 | skidbuffer.o_valid 44 | @29 45 | [color] 3 46 | skidbuffer.i_ready 47 | @22 48 | [color] 2 49 | skidbuffer.o_data[7:0] 50 | [pattern_trace] 1 51 | [pattern_trace] 0 52 | -------------------------------------------------------------------------------- /bench/formal/skidbuffer.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prfc prf 3 | prfo prf opt_outreg 4 | lpc prf opt_lowpower 5 | lpo prf opt_lowpower opt_outreg 6 | cvr 7 | 8 | [options] 9 | prf: mode prove 10 | prf: depth 12 11 | cvr: mode cover 12 | cvr: depth 20 13 | 14 | [engines] 15 | smtbmc 16 | 17 | [script] 18 | read -define SKIDBUFFER 19 | read -formal skidbuffer.v 20 | --pycode-begin-- 21 | cmd = "hierarchy -top skidbuffer" 22 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 23 | cmd += " -chparam OPT_OUTREG %d" % (1 if "opt_outreg" in tags else 0) 24 | output(cmd); 25 | --pycode-end-- 26 | prep -top skidbuffer 27 | 28 | [files] 29 | ../../rtl/skidbuffer.v 30 | -------------------------------------------------------------------------------- /bench/formal/wbarbiter.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Fri Dec 28 02:53:33 2018 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Fri Dec 28 02:48:56 2018" 7 | [dumpfile_size] 13681 8 | [timestart] 0 9 | [size] 1441 600 10 | [pos] -1 -1 11 | *-4.552812 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [sst_width] 270 13 | [signals_width] 160 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 143 16 | @28 17 | wbarbiter.i_clk 18 | wbarbiter.i_reset 19 | @200 20 | - 21 | @28 22 | wbarbiter.i_a_cyc 23 | wbarbiter.i_a_stb 24 | wbarbiter.i_a_we 25 | @22 26 | wbarbiter.i_a_adr[31:0] 27 | wbarbiter.i_a_dat[31:0] 28 | wbarbiter.i_a_sel[3:0] 29 | @29 30 | [color] 2 31 | wbarbiter.o_a_stall 32 | [color] 2 33 | wbarbiter.o_a_ack 34 | [color] 2 35 | wbarbiter.o_a_err 36 | @200 37 | - 38 | @28 39 | wbarbiter.i_b_cyc 40 | wbarbiter.i_b_stb 41 | wbarbiter.i_b_we 42 | @22 43 | wbarbiter.i_b_adr[31:0] 44 | wbarbiter.i_b_dat[31:0] 45 | wbarbiter.i_b_sel[3:0] 46 | @28 47 | [color] 2 48 | wbarbiter.o_b_stall 49 | [color] 2 50 | wbarbiter.o_b_ack 51 | [color] 2 52 | wbarbiter.o_b_err 53 | @200 54 | - 55 | @28 56 | wbarbiter.o_cyc 57 | wbarbiter.o_stb 58 | wbarbiter.o_we 59 | @22 60 | wbarbiter.o_adr[31:0] 61 | wbarbiter.o_dat[31:0] 62 | wbarbiter.o_sel[3:0] 63 | @28 64 | [color] 2 65 | wbarbiter.i_ack 66 | [color] 2 67 | wbarbiter.i_stall 68 | [color] 2 69 | wbarbiter.i_err 70 | [pattern_trace] 1 71 | [pattern_trace] 0 72 | -------------------------------------------------------------------------------- /bench/formal/wbarbiter.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 4 8 | cvr: mode cover 9 | cvr: depth 32 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D WBARBITER wbarbiter.v 16 | read -formal -D WBARBITER fwb_slave.v 17 | read -formal -D WBARBITER fwb_master.v 18 | prep -top wbarbiter 19 | 20 | [files] 21 | ../../rtl/wbarbiter.v 22 | fwb_slave.v 23 | fwb_master.v 24 | -------------------------------------------------------------------------------- /bench/formal/wbc2pipeline.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Tue Oct 13 02:43:36 2020 4 | [*] 5 | [dumpfile_mtime] "Wed Mar 25 13:05:01 2020" 6 | [dumpfile_size] 14972 7 | [timestart] 0 8 | [size] 1208 600 9 | [pos] 2629 19 10 | *-5.270011 60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 196 12 | [signals_width] 134 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 155 15 | @28 16 | wbc2pipeline.i_clk 17 | wbc2pipeline.i_reset 18 | @200 19 | - 20 | @28 21 | [color] 3 22 | wbc2pipeline.i_mcyc 23 | [color] 3 24 | wbc2pipeline.i_mstb 25 | [color] 3 26 | wbc2pipeline.i_mwe 27 | [color] 3 28 | wbc2pipeline.i_mbte[1:0] 29 | [color] 3 30 | wbc2pipeline.i_mcti[2:0] 31 | @22 32 | [color] 3 33 | wbc2pipeline.i_maddr[11:0] 34 | [color] 3 35 | wbc2pipeline.i_mdata[31:0] 36 | [color] 3 37 | wbc2pipeline.i_msel[3:0] 38 | @29 39 | [color] 2 40 | wbc2pipeline.o_mack 41 | @23 42 | [color] 2 43 | wbc2pipeline.o_mdata[31:0] 44 | @29 45 | [color] 2 46 | wbc2pipeline.o_merr 47 | @200 48 | - 49 | @28 50 | [color] 2 51 | wbc2pipeline.o_scyc 52 | [color] 2 53 | wbc2pipeline.o_sstb 54 | [color] 2 55 | wbc2pipeline.o_swe 56 | @22 57 | [color] 2 58 | wbc2pipeline.o_saddr[11:0] 59 | [color] 2 60 | wbc2pipeline.o_sdata[31:0] 61 | [color] 2 62 | wbc2pipeline.o_ssel[3:0] 63 | @28 64 | [color] 3 65 | wbc2pipeline.i_sstall 66 | [color] 3 67 | wbc2pipeline.i_sack 68 | @22 69 | [color] 3 70 | wbc2pipeline.i_sdata[31:0] 71 | @28 72 | [color] 3 73 | wbc2pipeline.i_serr 74 | wbc2pipeline.last_stb 75 | [pattern_trace] 1 76 | [pattern_trace] 0 77 | -------------------------------------------------------------------------------- /bench/formal/wbc2pipeline.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 14 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal wbc2pipeline.v 16 | read -formal fwb_master.v 17 | read -formal fwbc_slave.v 18 | prep -top wbc2pipeline 19 | 20 | [files] 21 | ../../rtl/wbc2pipeline.v 22 | fwb_master.v 23 | fwbc_slave.v 24 | -------------------------------------------------------------------------------- /bench/formal/wbm2axilite.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 18 8 | cvr: mode cover 9 | cvr: depth 32 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D AXILRD2WBSP wbm2axilite.v 16 | read -formal -D AXILRD2WBSP faxil_master.v 17 | read -formal -D AXILRD2WBSP fwb_slave.v 18 | prep -top wbm2axilite 19 | 20 | [files] 21 | ../../rtl/wbm2axilite.v 22 | faxil_master.v 23 | fwb_slave.v 24 | -------------------------------------------------------------------------------- /bench/formal/wbm2axisp.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr cvrw32x32 wb32 axi32 3 | prfx8 prf wb8 axi8 4 | prfx16 prf wb8 axi16 5 | prfw16x32 prf wb16 axi32 6 | cvrw16x32 cvr wb16 axi32 7 | prfe32 prf wb8 axi32 8 | prfx32 prf wb32 axi32 9 | prfx64 prf wb32 axi64 10 | prfx128 prf wb32 axi128 11 | prfx256 prf wb32 axi256 12 | prfx512 prf wb32 axi512 13 | prfx1024 prf wb32 axi1024 14 | cvrle cvr opt_little_endian cvrw32x32 wb32 axi32 15 | prfx8le prf opt_little_endian wb8 axi8 16 | prfx16le prf opt_little_endian wb8 axi16 17 | prfw16x32le prf opt_little_endian wb16 axi32 18 | cvrw16x32le cvr opt_little_endian wb16 axi32 19 | prfe32le prf opt_little_endian wb8 axi32 20 | prfx32le prf opt_little_endian wb32 axi32 21 | prfx64le prf opt_little_endian wb32 axi64 22 | prfx128le prf opt_little_endian wb32 axi128 23 | prfx256le prf opt_little_endian wb32 axi256 24 | prfx512le prf opt_little_endian wb32 axi512 25 | prfx1024le prf opt_little_endian wb32 axi1024 26 | 27 | [options] 28 | prf: mode prove 29 | # prf: depth 3 30 | prf: depth 8 31 | cvr: mode cover 32 | cvr: depth 48 33 | 34 | [engines] 35 | smtbmc 36 | 37 | [script] 38 | read -formal -D WBM2AXISP wbm2axisp.v 39 | read -formal -D WBM2AXISP skidbuffer.v 40 | read -formal -D WBM2AXISP faxi_master.v 41 | read -formal -D WBM2AXISP faxi_addr.v 42 | read -formal -D WBM2AXISP faxi_wstrb.v 43 | read -formal -D WBM2AXISP faxi_valaddr.v 44 | read -formal -D WBM2AXISP fwb_slave.v 45 | --pycode-begin-- 46 | cmd = "hierarchy -top wbm2axisp" 47 | cmd += " -chparam C_AXI_ADDR_WIDTH 21" 48 | cmd += " -chparam OPT_LITTLE_ENDIAN %d" % (1 if "opt_little_endian" in tags else 0) 49 | if ("wb8" in tags): 50 | cmd += " -chparam DW 8 -chparam AW 21" 51 | elif ("wb16" in tags): 52 | cmd += " -chparam DW 16 -chparam AW 20" 53 | else: 54 | cmd += " -chparam DW 32 -chparam AW 19" 55 | if ("axi8" in tags): 56 | cmd += " -chparam C_AXI_DATA_WIDTH 8" 57 | elif ("axi16" in tags): 58 | cmd += " -chparam C_AXI_DATA_WIDTH 16" 59 | elif ("axi32" in tags): 60 | cmd += " -chparam C_AXI_DATA_WIDTH 32" 61 | elif ("axi64" in tags): 62 | cmd += " -chparam C_AXI_DATA_WIDTH 64" 63 | elif ("axi128" in tags): 64 | cmd += " -chparam C_AXI_DATA_WIDTH 128" 65 | elif ("axi256" in tags): 66 | cmd += " -chparam C_AXI_DATA_WIDTH 256" 67 | elif ("axi512" in tags): 68 | cmd += " -chparam C_AXI_DATA_WIDTH 512" 69 | else: 70 | cmd += " -chparam C_AXI_DATA_WIDTH 1024" 71 | output(cmd) 72 | --pycode-end-- 73 | # 74 | prep -top wbm2axisp 75 | 76 | [files] 77 | ../../rtl/wbm2axisp.v 78 | ../../rtl/skidbuffer.v 79 | faxi_master.v 80 | faxi_addr.v 81 | faxi_valaddr.v 82 | faxi_wstrb.v 83 | fwb_slave.v 84 | -------------------------------------------------------------------------------- /bench/formal/wbm2axisp.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D WBM2AXISP -formal ../../rtl/wbm2axisp.v 2 | read_verilog -D WBM2AXISP -formal faxi_master.v 3 | read_verilog -D WBM2AXISP -formal fwb_slave.v 4 | prep -top wbm2axisp -nordff 5 | opt -share_all 6 | write_smt2 -wires wbm2axisp.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/wbp2classic.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Apr 24 17:19:47 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Wed Apr 24 17:13:31 2019" 7 | [dumpfile_size] 14390 8 | [timestart] 0 9 | [size] 1673 812 10 | [pos] -1 -213 11 | *-5.270011 130 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [sst_width] 196 13 | [signals_width] 134 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 230 16 | @28 17 | wbp2classic.i_clk 18 | wbp2classic.i_reset 19 | @200 20 | - 21 | @28 22 | [color] 3 23 | wbp2classic.i_mcyc 24 | [color] 3 25 | wbp2classic.i_mstb 26 | [color] 3 27 | wbp2classic.i_mwe 28 | @22 29 | [color] 3 30 | wbp2classic.i_maddr[11:0] 31 | [color] 3 32 | wbp2classic.i_mdata[31:0] 33 | [color] 3 34 | wbp2classic.i_msel[3:0] 35 | @200 36 | - 37 | @28 38 | [color] 2 39 | wbp2classic.o_mstall 40 | [color] 2 41 | wbp2classic.o_mack 42 | @22 43 | [color] 2 44 | wbp2classic.o_mdata[31:0] 45 | @28 46 | [color] 2 47 | wbp2classic.o_merr 48 | @200 49 | - 50 | @28 51 | [color] 3 52 | wbp2classic.o_scyc 53 | [color] 3 54 | wbp2classic.o_sstb 55 | [color] 3 56 | wbp2classic.o_swe 57 | @22 58 | [color] 3 59 | wbp2classic.o_saddr[11:0] 60 | [color] 3 61 | wbp2classic.o_sdata[31:0] 62 | @23 63 | [color] 3 64 | wbp2classic.o_ssel[3:0] 65 | @200 66 | - 67 | @28 68 | [color] 2 69 | wbp2classic.i_sack 70 | @22 71 | [color] 2 72 | wbp2classic.i_sdata[31:0] 73 | @28 74 | [color] 2 75 | wbp2classic.i_serr 76 | @200 77 | - 78 | @28 79 | wbp2classic.o_sbti[1:0] 80 | wbp2classic.o_scti[2:0] 81 | [pattern_trace] 1 82 | [pattern_trace] 0 83 | -------------------------------------------------------------------------------- /bench/formal/wbp2classic.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 14 8 | cvr: mode cover 9 | cvr: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal wbp2classic.v 16 | read -formal fwb_slave.v 17 | read -formal fwbc_master.v 18 | prep -top wbp2classic 19 | 20 | [files] 21 | ../../rtl/wbp2classic.v 22 | fwb_slave.v 23 | fwbc_master.v 24 | -------------------------------------------------------------------------------- /bench/formal/wbsafety.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Feb 20 19:41:28 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1054 8 | [pos] -1 -1 9 | *-4.567505 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] wbsafety. 11 | [treeopen] wbsafety.wbs. 12 | [sst_width] 196 13 | [signals_width] 198 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 315 16 | @28 17 | wbsafety.i_clk 18 | wbsafety.i_reset 19 | @200 20 | - 21 | @28 22 | [color] 3 23 | wbsafety.i_wb_cyc 24 | [color] 3 25 | wbsafety.i_wb_stb 26 | [color] 3 27 | wbsafety.i_wb_we 28 | @22 29 | [color] 3 30 | wbsafety.i_wb_addr[27:0] 31 | [color] 3 32 | wbsafety.i_wb_data[31:0] 33 | [color] 3 34 | wbsafety.i_wb_sel[3:0] 35 | @28 36 | wbsafety.o_wb_stall 37 | wbsafety.o_wb_ack 38 | @22 39 | wbsafety.o_wb_idata[31:0] 40 | @28 41 | wbsafety.o_wb_err 42 | @201 43 | - 44 | @22 45 | wbsafety.fwbs_nacks[3:0] 46 | wbsafety.fwbs_nreqs[3:0] 47 | wbsafety.fwbs_outstanding[3:0] 48 | @200 49 | - 50 | @28 51 | wbsafety.o_wb_cyc 52 | wbsafety.o_wb_stb 53 | wbsafety.o_wb_we 54 | @22 55 | wbsafety.o_wb_addr[27:0] 56 | wbsafety.o_wb_data[31:0] 57 | wbsafety.o_wb_sel[3:0] 58 | @28 59 | [color] 2 60 | wbsafety.i_wb_stall 61 | [color] 2 62 | wbsafety.i_wb_ack 63 | @22 64 | [color] 2 65 | wbsafety.i_wb_idata[31:0] 66 | @28 67 | [color] 2 68 | wbsafety.i_wb_err 69 | @200 70 | - 71 | @28 72 | [color] 1 73 | wbsafety.o_fault 74 | [color] 1 75 | wbsafety.o_reset 76 | @200 77 | - 78 | @22 79 | wbsafety.stall_timer[3:0] 80 | wbsafety.wait_timer[3:0] 81 | @200 82 | - 83 | @28 84 | wbsafety.timeout 85 | @200 86 | - 87 | @22 88 | wbsafety.expected_returns[3:0] 89 | @28 90 | wbsafety.none_expected 91 | wbsafety.faulty_return 92 | [pattern_trace] 1 93 | [pattern_trace] 0 94 | -------------------------------------------------------------------------------- /bench/formal/wbsafety.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr fault opt_reset 4 | fault prf 5 | prfr prf opt_reset 6 | faultr fault prf opt_reset 7 | 8 | [options] 9 | prf: mode prove 10 | prf: depth 6 11 | cvr: mode cover 12 | cvr: depth 32 13 | 14 | [engines] 15 | smtbmc 16 | 17 | [script] 18 | read -formal wbsafety.v 19 | read -formal skidbuffer.v 20 | read -formal fwb_slave.v 21 | read -formal fwb_master.v 22 | --pycode-begin-- 23 | cmd = "hierarchy -top wbsafety" 24 | cmd += " -chparam F_OPT_FAULTLESS %d" % (0 if "fault" in tags else 1) 25 | cmd += " -chparam OPT_SELF_RESET %d" % (1 if "opt_reset" in tags else 0) 26 | cmd += " -chparam OPT_TIMEOUT 10" 27 | output(cmd) 28 | --pycode-end-- 29 | prep -top wbsafety 30 | 31 | [files] 32 | ../../rtl/skidbuffer.v 33 | ../../rtl/wbsafety.v 34 | fwb_slave.v 35 | fwb_master.v 36 | -------------------------------------------------------------------------------- /bench/formal/wbxbar.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf4x8_buflp nxm opt_dblbuffer opt_lowpower 3 | prf4x8_buf nxm opt_dblbuffer 4 | prf4x8_lp nxm opt_lowpower 5 | prf4x8_cheap nxm 6 | cvr4x8_buflp nxm opt_dblbuffer opt_lowpower cvr 7 | cvr4x8_buf nxm opt_dblbuffer cvr 8 | cvr4x8_lp nxm opt_lowpower cvr 9 | cvr4x8_cheap nxm cvr 10 | prf4x8_buflpko nxm opt_dblbuffer opt_lowpower opt_timeout 11 | prf4x8_bufko nxm opt_dblbuffer opt_timeout 12 | prf4x8_lpko nxm opt_lowpower opt_timeout 13 | prf4x8_cheapko nxm opt_timeout 14 | prf4x8_buflpkos nxm opt_dblbuffer opt_lowpower opt_timeout opt_starvation 15 | prf4x8_bufkos nxm opt_dblbuffer opt_timeout opt_starvation 16 | prf4x8_lpkos nxm opt_lowpower opt_timeout opt_starvation 17 | prf4x8_cheapkos nxm opt_timeout opt_starvation 18 | prf1x8_buflp oxm opt_dblbuffer opt_lowpower 19 | prf1x8_buf oxm opt_dblbuffer 20 | prf1x8_lp oxm opt_lowpower 21 | prf1x8_cheap oxm 22 | cvr1x3_buflp oxl opt_dblbuffer opt_lowpower cvr 23 | cvr1x3_buf oxl opt_dblbuffer cvr 24 | cvr1x3_lp oxl opt_lowpower cvr 25 | cvr1x3_cheap oxl cvr 26 | prf1x8_buflpko oxm opt_dblbuffer opt_lowpower opt_timeout 27 | prf1x8_bufko oxm opt_dblbuffer opt_timeout 28 | prf1x8_lpko oxm opt_lowpower opt_timeout 29 | prf1x8_cheapko oxm opt_timeout 30 | prf1x8_buflpkos oxm opt_dblbuffer opt_lowpower opt_timeout opt_starvation 31 | prf1x8_bufkos oxm opt_dblbuffer opt_timeout opt_starvation 32 | prf1x8_lpkos oxm opt_lowpower opt_timeout opt_starvation 33 | prf1x8_cheapkos oxm opt_timeout opt_starvation 34 | prf4x1_buflp nxo opt_dblbuffer opt_lowpower 35 | prf4x1_buf nxo opt_dblbuffer 36 | prf4x1_lp nxo opt_lowpower 37 | prf4x1_cheap nxo 38 | cvr4x1_buflp nxo opt_dblbuffer opt_lowpower cvr 39 | cvr4x1_buf nxo opt_dblbuffer cvr 40 | cvr4x1_lp nxo opt_lowpower cvr 41 | cvr4x1_cheap nxo cvr 42 | prf4x1_buflpko nxo opt_dblbuffer opt_lowpower opt_timeout 43 | prf4x1_bufko nxo opt_dblbuffer opt_timeout 44 | prf4x1_lpko nxo opt_lowpower opt_timeout 45 | prf4x1_cheapko nxo opt_timeout 46 | prf4x1_buflpkos nxo opt_dblbuffer opt_lowpower opt_timeout opt_starvation 47 | prf4x1_bufkos nxo opt_dblbuffer opt_timeout opt_starvation 48 | prf4x1_lpkos nxo opt_lowpower opt_timeout opt_starvation 49 | prf4x1_cheapkos nxo opt_timeout opt_starvation 50 | 51 | [options] 52 | ~cvr: mode prove 53 | ~cvr: depth 6 54 | cvr: mode cover 55 | cvr: depth 64 56 | 57 | [engines] 58 | smtbmc boolector 59 | # smtbmc yices 60 | # smtbmc z3 61 | 62 | 63 | [script] 64 | read -formal addrdecode.v 65 | read -formal skidbuffer.v 66 | read -formal wbxbar.v 67 | read -formal fwb_slave.v 68 | read -formal fwb_master.v 69 | --pycode-begin-- 70 | cmd = "hierarchy -top wbxbar" 71 | if ("nxm" in tags): 72 | cmd += " -chparam NM 4 -chparam NS 8" 73 | if ("oxm" in tags): 74 | cmd += " -chparam NM 1 -chparam NS 8" 75 | if ("oxl" in tags): 76 | cmd += " -chparam NM 1 -chparam NS 3" 77 | if ("nxo" in tags): 78 | cmd += " -chparam NM 4 -chparam NS 1" 79 | cmd += " -chparam OPT_DBLBUFFER %d" % (1 if "opt_dblbuffer" in tags else 0) 80 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 81 | cmd += " -chparam OPT_TIMEOUT %d" % (20 if "opt_timeout" in tags else 0) 82 | cmd += " -chparam OPT_STARVATION_TIMEOUT %d" % (1 if "opt_starvation" in tags else 0) 83 | output(cmd) 84 | --pycode-end-- 85 | proc -norom 86 | prep -top wbxbar 87 | 88 | [files] 89 | ../../rtl/skidbuffer.v 90 | ../../rtl/addrdecode.v 91 | ../../rtl/wbxbar.v 92 | fwb_slave.v 93 | fwb_master.v 94 | -------------------------------------------------------------------------------- /bench/formal/wbxclk.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Mon May 4 03:06:56 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1021 8 | [pos] -1 -1 9 | *-5.552812 130 130 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] wbxclk. 11 | [treeopen] wbxclk.reqfifo. 12 | [sst_width] 270 13 | [signals_width] 240 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 290 16 | @28 17 | wbxclk.i_reset 18 | wbxclk.i_wb_clk 19 | @200 20 | - 21 | @800200 22 | -Upstream WB 23 | @28 24 | [color] 3 25 | wbxclk.i_wb_cyc 26 | [color] 3 27 | wbxclk.i_wb_stb 28 | [color] 3 29 | wbxclk.i_wb_we 30 | @22 31 | [color] 3 32 | wbxclk.i_wb_addr[31:0] 33 | [color] 3 34 | wbxclk.i_wb_data[31:0] 35 | [color] 3 36 | wbxclk.i_wb_sel[3:0] 37 | @28 38 | [color] 2 39 | wbxclk.o_wb_stall 40 | [color] 2 41 | wbxclk.o_wb_ack 42 | @22 43 | [color] 2 44 | wbxclk.o_wb_data[31:0] 45 | @28 46 | [color] 2 47 | wbxclk.o_wb_err 48 | @22 49 | wbxclk.fwb_outstanding[5:0] 50 | @28 51 | wbxclk.wb_active 52 | @1000200 53 | -Upstream WB 54 | @28 55 | wbxclk.i_xclk_clk 56 | wbxclk.xck_reset 57 | wbxclk.bus_abort 58 | @800200 59 | -Downstream 60 | @28 61 | [color] 2 62 | wbxclk.o_xclk_cyc 63 | [color] 2 64 | wbxclk.o_xclk_stb 65 | [color] 2 66 | wbxclk.o_xclk_we 67 | @22 68 | [color] 2 69 | wbxclk.o_xclk_addr[31:0] 70 | [color] 2 71 | wbxclk.o_xclk_data[31:0] 72 | [color] 2 73 | wbxclk.o_xclk_sel[3:0] 74 | @28 75 | [color] 3 76 | wbxclk.i_xclk_stall 77 | [color] 3 78 | wbxclk.i_xclk_ack 79 | @22 80 | [color] 3 81 | wbxclk.i_xclk_data[31:0] 82 | @28 83 | [color] 1 84 | wbxclk.i_xclk_err 85 | @22 86 | wbxclk.fxck_outstanding[5:0] 87 | @29 88 | wbxclk.xclk_err_state 89 | @1000200 90 | -Downstream 91 | @800200 92 | -Req FIFO 93 | @28 94 | wbxclk.reqfifo.i_wclk 95 | wbxclk.reqfifo.i_wr_reset_n 96 | wbxclk.reqfifo.i_wr 97 | @22 98 | wbxclk.reqfifo.i_wr_data[69:0] 99 | @28 100 | wbxclk.reqfifo.o_wr_full 101 | @22 102 | wbxclk.reqfifo.wr_addr[5:0] 103 | @200 104 | - 105 | @28 106 | wbxclk.reqfifo.i_rclk 107 | wbxclk.reqfifo.i_rd_reset_n 108 | wbxclk.reqfifo.i_rd 109 | @22 110 | wbxclk.reqfifo.o_rd_data[69:0] 111 | @28 112 | wbxclk.reqfifo.o_rd_empty 113 | @22 114 | wbxclk.reqfifo.rd_addr[5:0] 115 | wbxclk.reqfifo_fill[5:0] 116 | @200 117 | - 118 | @22 119 | wbxclk.reqfifo.rd_addr[5:0] 120 | wbxclk.reqfifo.wr_addr[5:0] 121 | @1000200 122 | -Req FIFO 123 | @c00200 124 | -ACK FIFO 125 | @28 126 | wbxclk.ackfifo.i_wclk 127 | wbxclk.ackfifo.i_wr_reset_n 128 | wbxclk.ackfifo.i_wr 129 | @22 130 | wbxclk.ackfifo.i_wr_data[33:0] 131 | @28 132 | wbxclk.ackfifo.o_wr_full 133 | @200 134 | - 135 | @28 136 | wbxclk.ackfifo.i_rclk 137 | wbxclk.ackfifo.i_rd 138 | wbxclk.ackfifo.i_rd_reset_n 139 | @22 140 | wbxclk.ackfifo.o_rd_data[33:0] 141 | @28 142 | wbxclk.ackfifo.o_rd_empty 143 | @22 144 | wbxclk.ackfifo_fill[5:0] 145 | @1401200 146 | -ACK FIFO 147 | [pattern_trace] 1 148 | [pattern_trace] 0 149 | -------------------------------------------------------------------------------- /bench/formal/wbxclk.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | bmc 3 | prf 4 | cvr 5 | 6 | [options] 7 | bmc: mode bmc 8 | bmc: depth 50 9 | prf: mode prove 10 | prf: depth 17 11 | cvr: mode cover 12 | cvr: depth 90 # 72 should be sufficient 13 | multiclock on 14 | 15 | [engines] 16 | smtbmc 17 | 18 | [script] 19 | ~prf: read -formal -DBMC wbxclk.v 20 | prf: read -formal wbxclk.v 21 | read -formal afifo.v 22 | read -formal fwb_slave.v 23 | read -formal fwb_master.v 24 | cvr: hierarchy -top wbxclk -chparam LGFIFO 3 25 | prep -top wbxclk 26 | 27 | [files] 28 | ../../rtl/afifo.v 29 | ../../rtl/wbxclk.v 30 | fwb_slave.v 31 | fwb_master.v 32 | -------------------------------------------------------------------------------- /bench/formal/xlnxdemo.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Dec 27 16:19:38 2018 4 | [*] 5 | [dumpfile] "(null)" 6 | [dumpfile_mtime] "Thu Dec 27 03:40:12 2018" 7 | [dumpfile_size] 68959 8 | [timestart] 0 9 | [size] 1473 600 10 | [pos] -474 -1 11 | *-6.470208 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 12 | [sst_width] 196 13 | [signals_width] 166 14 | [sst_expanded] 1 15 | [sst_vpaned_height] 155 16 | @29 17 | [color] 3 18 | xlnxdemo.S_AXI_ARESETN 19 | [color] 3 20 | xlnxdemo.S_AXI_ACLK 21 | @200 22 | - 23 | @28 24 | xlnxdemo.S_AXI_AWVALID 25 | xlnxdemo.S_AXI_AWREADY 26 | @22 27 | xlnxdemo.S_AXI_AWADDR[6:0] 28 | @200 29 | - 30 | @28 31 | xlnxdemo.S_AXI_WVALID 32 | xlnxdemo.S_AXI_WREADY 33 | @22 34 | xlnxdemo.S_AXI_WSTRB[3:0] 35 | xlnxdemo.S_AXI_WDATA[31:0] 36 | @200 37 | - 38 | @28 39 | [color] 2 40 | xlnxdemo.S_AXI_BVALID 41 | [color] 2 42 | xlnxdemo.S_AXI_BREADY 43 | @200 44 | - 45 | @28 46 | xlnxdemo.S_AXI_ARVALID 47 | xlnxdemo.S_AXI_ARREADY 48 | @22 49 | xlnxdemo.S_AXI_ARADDR[6:0] 50 | @200 51 | - 52 | @28 53 | [color] 2 54 | xlnxdemo.S_AXI_RVALID 55 | [color] 2 56 | xlnxdemo.S_AXI_RREADY 57 | @22 58 | [color] 2 59 | xlnxdemo.S_AXI_RDATA[31:0] 60 | [pattern_trace] 1 61 | [pattern_trace] 0 62 | -------------------------------------------------------------------------------- /bench/formal/xlnxdemo.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr 3 | prf 4 | 5 | [options] 6 | cvr: mode cover 7 | cvr: depth 60 8 | prf: mode prove 9 | prf: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal xlnxdemo.v 16 | read -formal faxil_slave.v 17 | cvr: hierarchy -top xlnxdemo -chparam OPT_ASSUME_NO_ERRORS 1 18 | prep -top xlnxdemo 19 | 20 | [files] 21 | xlnxdemo.v 22 | faxil_slave.v 23 | -------------------------------------------------------------------------------- /bench/formal/xlnxstream_2018_3.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Fri Apr 26 10:36:20 2019 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1021 8 | [pos] -1 -1 9 | *-5.403065 200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] xlnxstream_2018_3. 11 | [sst_width] 270 12 | [signals_width] 240 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 290 15 | @29 16 | xlnxstream_2018_3.f_past_valid 17 | @28 18 | xlnxstream_2018_3.M_AXIS_ACLK 19 | xlnxstream_2018_3.M_AXIS_ARESETN 20 | @200 21 | - 22 | @28 23 | [color] 3 24 | xlnxstream_2018_3.M_AXIS_TVALID 25 | [color] 2 26 | xlnxstream_2018_3.M_AXIS_TREADY 27 | @22 28 | [color] 3 29 | xlnxstream_2018_3.M_AXIS_TDATA[31:0] 30 | [color] 3 31 | xlnxstream_2018_3.M_AXIS_TSTRB[3:0] 32 | @28 33 | [color] 3 34 | xlnxstream_2018_3.M_AXIS_TLAST 35 | @200 36 | - 37 | @28 38 | xlnxstream_2018_3.axis_tvalid 39 | xlnxstream_2018_3.axis_tlast 40 | @200 41 | - 42 | @28 43 | xlnxstream_2018_3.axis_tvalid_delay 44 | xlnxstream_2018_3.axis_tlast_delay 45 | @200 46 | - 47 | @22 48 | xlnxstream_2018_3.count[4:0] 49 | @28 50 | xlnxstream_2018_3.mst_exec_state[1:0] 51 | @22 52 | xlnxstream_2018_3.read_pointer[3:0] 53 | xlnxstream_2018_3.stream_data_out[31:0] 54 | @28 55 | xlnxstream_2018_3.tx_done 56 | xlnxstream_2018_3.tx_en 57 | @200 58 | - 59 | @28 60 | xlnxstream_2018_3.f_routecheck[1:0] 61 | @22 62 | xlnxstream_2018_3.f_bytecount[5:0] 63 | @200 64 | - 65 | @22 66 | xlnxstream_2018_3.axi_stream_check.i_tkeep[3:0] 67 | xlnxstream_2018_3.axi_stream_check.i_tstrb[3:0] 68 | xlnxstream_2018_3.axi_stream_check.f_vbytes[5:0] 69 | [pattern_trace] 1 70 | [pattern_trace] 0 71 | -------------------------------------------------------------------------------- /bench/formal/xlnxstream_2018_3.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 120 8 | prf: expect FAIL 9 | cvr: mode cover 10 | cvr: depth 60 11 | 12 | [engines] 13 | smtbmc 14 | 15 | [script] 16 | read -formal faxis_master.v 17 | read -formal xlnxstream_2018_3.v 18 | prep -top xlnxstream_2018_3 19 | chformal -assert -skip 2 20 | 21 | [files] 22 | faxis_master.v 23 | xlnxstream_2018_3.v 24 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/.gitignore: -------------------------------------------------------------------------------- 1 | database 2 | quickcheck 3 | tasks 4 | *.tgz 5 | faxil_slave.v 6 | faxil_register.v 7 | easyaxil.v 8 | notes.txt 9 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: bench/mcy/easyaxil/Makefile 4 | ## {{{ 5 | ## Project: WB2AXIPSP: bus bridges and other odds and ends 6 | ## 7 | ## Purpose: 8 | ## 9 | ## Creator: Dan Gisselquist, Ph.D. 10 | ## Gisselquist Technology, LLC 11 | ## 12 | ################################################################################ 13 | ## }}} 14 | ## Copyright (C) 2019-2025, Gisselquist Technology, LLC 15 | ## {{{ 16 | ## This file is part of the WB2AXIP project. 17 | ## 18 | ## The WB2AXIP project contains free software and gateware, licensed under the 19 | ## Apache License, Version 2.0 (the "License"). You may not use this project, 20 | ## or this file, except in compliance with the License. You may obtain a copy 21 | ## of the License at 22 | ## }}} 23 | ## http://www.apache.org/licenses/LICENSE-2.0 24 | ## {{{ 25 | ## Unless required by applicable law or agreed to in writing, software 26 | ## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 27 | ## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 28 | ## License for the specific language governing permissions and limitations 29 | ## under the License. 30 | ## 31 | ################################################################################ 32 | ## 33 | ## 34 | YYMMDD:= `date +%Y%m%d` 35 | .PHONY: archive 36 | # archive: $(YYMMDD)-easyaxil.tgz 37 | 38 | FILES := $(wildcard *.sv) $(wildcard *.v) $(wildcard *.cpp) $(wildcard *.h) $(wildcard *.sh) $(wildcard *.mcy) test_fm.sby 39 | 40 | archive: $(FILES) 41 | tar -cvzhf $(YYMMDD)-easyaxil.tgz --exclude tasks --exclude database --transform "sm^m./$(YYMMDD)-easyaxil/m" $(FILES) 42 | ## }}} 43 | easyaxil.v: 44 | @bash -c "if [ ! -e easyaxil.v ]; then ln -s ../../../rtl/easyaxil.v .; fi" 45 | 46 | faxil_slave.v: 47 | @bash -c "if [ ! -e faxil_slave.v ]; then ln -s ../../../bench/formal/faxil_slave.v; fi" 48 | 49 | .PHONY: mcy 50 | mcy: config.mcy easyaxil.v faxil_slave.v test_eq.sh test_sim.sh test_fm.sh test_fm.sby easyaxil_tb.cpp easyaxil_tb.sv 51 | rm -rf database/ 52 | rm -rf tasks/ 53 | mcy init 54 | mcy run -j4 55 | 56 | .PHONY: clean 57 | clean: 58 | rm -rf easyaxil.v faxil_slave.v 59 | rm -rf database/ tasks/ 60 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/config.mcy: -------------------------------------------------------------------------------- 1 | [options] 2 | size 1000 3 | tags COVERED UNCOVERED NOCHANGE EQGAP FMONLY 4 | 5 | [script] 6 | read -sv easyaxil.v 7 | prep -top easyaxil 8 | 9 | [files] 10 | easyaxil.v 11 | 12 | [logic] 13 | use_formal = True 14 | 15 | tb_okay = (result("test_sim") == "PASS") 16 | eq_okay = (result("test_eq") == "PASS") 17 | 18 | if tb_okay and use_formal: 19 | tb_okay = (result("test_fm") == "PASS") 20 | if not tb_okay: 21 | tag("FMONLY") 22 | 23 | if tb_okay and not eq_okay: 24 | tag("UNCOVERED") 25 | elif not tb_okay and not eq_okay: 26 | tag("COVERED") 27 | elif tb_okay and eq_okay: 28 | tag("NOCHANGE") 29 | elif not tb_okay and eq_okay: 30 | tag("EQGAP") 31 | else: 32 | assert 0 33 | 34 | [report] 35 | if tags("EQGAP"): 36 | print("Found %d mutations exposing a formal equivalence gap!" % tags("EQGAP")) 37 | if tags("COVERED")+tags("UNCOVERED"): 38 | print("Coverage: %.2f%%" % (100.0*tags("COVERED")/(tags("COVERED")+tags("UNCOVERED")))) 39 | 40 | [test test_sim] 41 | maxbatchsize 10 42 | expect PASS FAIL 43 | run bash $PRJDIR/test_sim.sh 44 | 45 | [test test_eq] 46 | expect PASS FAIL 47 | run bash $PRJDIR/test_eq.sh 48 | 49 | [test test_fm] 50 | expect PASS FAIL 51 | run bash $PRJDIR/test_fm.sh 52 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/devbus.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/mcy/easyaxil/devbus.h 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: The purpose of this file is to document an interface which 8 | // any device with a bus, whether it be implemented over a UART, 9 | // an ethernet, or a PCI express bus, must implement. This describes 10 | // only an interface, and not how that interface is to be accomplished. 11 | // 12 | // The neat part of this interface is that, if programs are designed to 13 | // work with it, than the implementation details may be changed later 14 | // and any program that once worked with the interface should be able 15 | // to continue to do so. (i.e., switch from a UART controlled bus to a 16 | // PCI express controlled bus, with minimal change to the software of 17 | // interest.) 18 | // 19 | // 20 | // Creator: Dan Gisselquist, Ph.D. 21 | // Gisselquist Technology, LLC 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | // }}} 25 | // Copyright (C) 2019-2025, Gisselquist Technology, LLC 26 | // {{{ 27 | // This file is part of the WB2AXIP project. 28 | // 29 | // The WB2AXIP project contains free software and gateware, licensed under the 30 | // Apache License, Version 2.0 (the "License"). You may not use this project, 31 | // or this file, except in compliance with the License. You may obtain a copy 32 | // of the License at 33 | // }}} 34 | // http://www.apache.org/licenses/LICENSE-2.0 35 | // {{{ 36 | // Unless required by applicable law or agreed to in writing, software 37 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 38 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 39 | // License for the specific language governing permissions and limitations 40 | // under the License. 41 | // 42 | //////////////////////////////////////////////////////////////////////////////// 43 | // 44 | #ifndef DEVBUS_H 45 | #define DEVBUS_H 46 | // }}} 47 | #include 48 | #include 49 | 50 | typedef unsigned int uint32; 51 | 52 | class BUSERR { 53 | public: 54 | uint32 addr; 55 | BUSERR(const uint32 a) : addr(a) {}; 56 | }; 57 | 58 | class DEVBUS { 59 | public: 60 | typedef uint32 BUSW; 61 | 62 | virtual void kill(void) = 0; 63 | virtual void close(void) = 0; 64 | 65 | // Write a single value to a single address 66 | // a is the address of the value to be read as it exists on the 67 | // wishbone bus within the FPGA. 68 | // v is the singular value to write to this address 69 | virtual void writeio(const BUSW a, const BUSW v) = 0; 70 | 71 | // Read a single value to a single address 72 | // a is the address of the value to be read as it exists on the 73 | // wishbone bus within the FPGA. 74 | // This function returns the value read from the device wishbone 75 | // at address a. 76 | virtual BUSW readio(const BUSW a) = 0; 77 | 78 | // Read a series of values from values from a block of memory 79 | // a is the address of the value to be read as it exists on the 80 | // wishbone bus within the FPGA. 81 | // len is the number of words to read 82 | // buf is a pointer to a place to store the words once read. 83 | // This is equivalent to: 84 | // for(int i=0; i 35 | #include 36 | #include 37 | #include 38 | // }}} 39 | #include "verilated.h" 40 | #include "Veasyaxil.h" 41 | 42 | #include "testb.h" 43 | #include "axi_tb.h" 44 | 45 | typedef AXI_TB > EASYAXIL_TB; 46 | 47 | bool checkreg(EASYAXIL_TB *tb, int reg) { 48 | // Convert to an address 49 | unsigned addr = reg * 4; 50 | 51 | // Check that we can write to each individual bit 52 | for(int b=0; b<32; b++) { 53 | uint32_t v, c; 54 | 55 | v = (1<writeio(addr, v); 57 | c = tb->readio(addr); 58 | 59 | if (v != c) 60 | return false; 61 | printf("CHECK-bit %d: 0x%08x == 0x%08x\n", b, v, c); 62 | } 63 | 64 | // Let's try writing some random data 65 | for(int b=0; b<32; b++) { 66 | uint32_t v, c; 67 | 68 | v = rand(); 69 | tb->writeio(addr, v); 70 | c = tb->readio(addr); 71 | 72 | if (v != c) 73 | return false; 74 | printf("CHECK-rand %d: 0x%08x == 0x%08x\n", b, v, c); 75 | } 76 | 77 | // Success 78 | return true; 79 | } 80 | 81 | void usage(void) { 82 | fprintf(stderr, "USAGE: easyaxil_tb \n"); 83 | fprintf(stderr, "\t\tControls which mutation we examin\n"); 84 | } 85 | 86 | int main(int argc, char **argv) { 87 | const char *trace_file = NULL; // "trace.vcd"; 88 | Verilated::commandArgs(argc, argv); 89 | EASYAXIL_TB *tb = new EASYAXIL_TB; 90 | bool failed = false; 91 | 92 | if (argc > 2) { 93 | fprintf(stderr, "ERR: Too many arguments\n"); 94 | usage(); 95 | exit(EXIT_FAILURE); 96 | } 97 | 98 | int index = 0; 99 | if (argc > 1) 100 | index = atoi(argv[1]); 101 | 102 | if (trace_file) 103 | tb->opentrace(trace_file); 104 | 105 | tb->m_tb->m_core->mutsel = index; 106 | tb->reset(); 107 | 108 | if (!failed) failed = !checkreg(tb, 0); 109 | if (!failed) failed = !checkreg(tb, 1); 110 | if (!failed) failed = !checkreg(tb, 2); 111 | if (!failed) failed = !checkreg(tb, 3); 112 | 113 | if (failed) { 114 | printf("TEST FAIL!\n"); 115 | return EXIT_FAILURE; 116 | } 117 | printf("SUCCESS!\n"); 118 | return EXIT_SUCCESS; 119 | } 120 | 121 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/test_eq.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | exec 2>&1 4 | set -ex 5 | 6 | export SCRIPT=/home/dan/work/rnd/opencores/tools/mcy/scripts/create_mutated.sh 7 | # create_mutated.sh -c 8 | . ${SCRIPT} -c 9 | ## create yosys script with instructions how to export the mutated design 10 | # { 11 | # # read synthesized design 12 | # echo "read_ilang ../../database/design.il" 13 | # while read -r idx mut; do 14 | # # add mutation to the design, to be enabled by value ${idx} on 8-bit input `mutsel` added to the module 15 | # echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" 16 | # done < input.txt 17 | # # export design to RTLIL 18 | # echo "write_ilang mutated.il" 19 | # echo "write_verilog mutated.v" 20 | #} > mutate.ys 21 | 22 | ## run the above script to create mutated.il 23 | yosys -ql mutate.log mutate.ys 24 | 25 | ## run formal property check 26 | ln -s ../../test_eq.sv . 27 | ln -s ../../test_fm.sby . 28 | ln -s ../../faxil_register.v . 29 | ln -s ../../faxil_slave.v . 30 | ln -s ../../easyaxil_tb.sv . 31 | # sed -e '1,$s/easyaxil/goldenaxil/' < ../../easyaxil.v > goldenaxil.v 32 | 33 | sby -f test_fm.sby bmc 34 | 35 | ## obtain result 36 | gawk "{ print 1, \$1; }" test_fm_bmc/status >> output.txt 37 | 38 | exit 0 39 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/test_fm.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | bmc 4 | 5 | [options] 6 | prf: mode prove 7 | bmc: mode bmc 8 | bmc: depth 15 9 | prf: depth 5 10 | expect pass,fail,unknown 11 | 12 | [engines] 13 | smtbmc boolector 14 | 15 | [script] 16 | read -formal faxil_slave.v 17 | read -formal faxil_register.v 18 | bmc: read -formal easyaxil_tb.sv 19 | read -sv mutated.v 20 | bmc: prep -top easyaxil_tb 21 | bmc: fmcombine easyaxil_tb gold uut 22 | prf: read -formal easyprops.sv 23 | prf: prep -top easyaxil 24 | 25 | [files] 26 | faxil_register.v 27 | faxil_slave.v 28 | mutated.v 29 | bmc: easyaxil_tb.sv 30 | prf: easyprops.sv 31 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/test_fm.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | exec 2>&1 4 | set -ex 5 | 6 | export SCRIPT=/home/dan/work/rnd/opencores/tools/mcy/scripts/create_mutated.sh 7 | # create_mutated.sh 8 | . ${SCRIPT} 9 | 10 | ## create yosys script with instructions how to export the mutated design 11 | # { 12 | # # read synthesized design 13 | # echo "read_ilang ../../database/design.il" 14 | # # apply mutation 15 | # # First line is numbered one, two, etc. 16 | # # This cust off the '1' in the beginning, keeps the rest of the 17 | # # mutate command 18 | # cut -f2- -d' ' input.txt 19 | # # export design to RTLIL 20 | # echo "write_ilang mutated.il" 21 | # echo "write_verilog mutated.v" 22 | #} > mutate.ys 23 | 24 | ## run the above script to create mutated.il 25 | yosys -ql mutate.log mutate.ys 26 | 27 | ## run formal property check 28 | ln -s ../../test_fm.sby . 29 | ln -s ../../faxil_slave.v . 30 | ln -s ../../faxil_register.v . 31 | ln -s ../../easyprops.sv . 32 | 33 | sby -f test_fm.sby prf 34 | 35 | ## obtain result 36 | gawk "{ print 1, \$1; }" test_fm_prf/status | sed -e "s/UNKNOWN/FAIL/" >> output.txt 37 | 38 | exit 0 39 | -------------------------------------------------------------------------------- /bench/mcy/easyaxil/test_sim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Pipe standard error stream to stdout 4 | exec 2>&1 5 | 6 | # Exit on any non-zero error code along the way 7 | set -ex 8 | 9 | export SCRIPT=${HOME}/work/rnd/opencores/tools/mcy/scripts/create_mutated.sh 10 | . ${SCRIPT} -c 11 | 12 | VROOT=/usr/local/share/verilator 13 | VINC=${VROOT}/include 14 | INCFILES="-I${VROOT}/include -Iobj_dir" 15 | CFLAGS="-Wall -O3" 16 | # CPPDIR="../../../cpp" 17 | CPPDIR="../.." 18 | OBJ=obj_dir 19 | 20 | # { 21 | # echo "read_ilang ../../database/design.il" 22 | # while read -r idx mut; do 23 | # echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" 24 | # # One line goes into input.txt 25 | # done < input.txt 26 | # echo "write_verilog -attr2comment mutated.v" 27 | #} > mutate.ys 28 | 29 | yosys -ql mutate.log mutate.ys 30 | cp ${CPPDIR}/easyaxil_tb.cpp . 31 | cp ${CPPDIR}/axi_tb.h . 32 | cp ${CPPDIR}/devbus.h . 33 | cp ${CPPDIR}/testb.h . 34 | 35 | cp mutated.v easyaxil.v 36 | verilator -O3 --trace -Wno-UNOPTFLAT -Wno-CASEOVERLAP -Wno-WIDTH -cc easyaxil.v 37 | g++ ${CFLAGS} ${INCFILES} -DMCY -c easyaxil_tb.cpp -o ${OBJ}/easyaxil.o 38 | g++ ${CFLAGS} ${INCFILES} -c ${VINC}/verilated.cpp -o ${OBJ}/verilated.o 39 | g++ ${CFLAGS} ${INCFILES} -c ${VINC}/verilated_vcd_c.cpp -o ${OBJ}/verilated_vcd.o 40 | cd obj_dir 41 | make -f Veasyaxil.mk 42 | g++ easyaxil.o verilated.o verilated_vcd.o Veasyaxil__ALL.a -o ../easyaxil_tb 43 | cd .. 44 | 45 | ./easyaxil_tb 0 > goodsim.out || true 46 | good_sum=$(md5sum goodsim.out | awk '{ print $1; }') 47 | while read idx mut; do 48 | 49 | ./easyaxil_tb ${idx} > sim_${idx}.out || true 50 | this_sum=$(md5sum sim_${idx}.out | awk '{ print $1; }') 51 | echo "SUM " $this_sum 52 | if [ $good_sum = $this_sum ]; then 53 | echo "$idx PASS" >> output.txt 54 | else 55 | echo "$idx FAIL" >> output.txt 56 | fi 57 | done < input.txt 58 | exit 0 59 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | *.aux 2 | *.dvi 3 | *.bm 4 | *.log 5 | *.toc 6 | orconf2019.ps 7 | nup.ps 8 | *.vrb 9 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: doc/Makefile 4 | ## {{{ 5 | ## Project: WB2AXIPSP: bus bridges and other odds and ends 6 | ## 7 | ## Purpose: To coordinate the build of documentation PDFs from their 8 | ## LaTeX sources. 9 | ## 10 | ## Targets include: 11 | ## all Builds all documents 12 | ## 13 | ## spec.pdf Builds the specification for the SDSPI 14 | ## controller. 15 | ## 16 | ## Creator: Dan Gisselquist, Ph.D. 17 | ## Gisselquist Technology, LLC 18 | ## 19 | ################################################################################ 20 | ## }}} 21 | ## Copyright (C) 2015-2025, Gisselquist Technology, LLC 22 | ## {{{ 23 | ## This file is part of the WB2AXIP project. 24 | ## 25 | ## The WB2AXIP project contains free software and gateware, licensed under the 26 | ## Apache License, Version 2.0 (the "License"). You may not use this project, 27 | ## or this file, except in compliance with the License. You may obtain a copy 28 | ## of the License at 29 | ## }}} 30 | ## http://www.apache.org/licenses/LICENSE-2.0 31 | ## {{{ 32 | ## Unless required by applicable law or agreed to in writing, software 33 | ## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 34 | ## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 35 | ## License for the specific language governing permissions and limitations 36 | ## under the License. 37 | ## 38 | ################################################################################ 39 | ## 40 | ## 41 | all: 42 | echo "See the comments internal to the various RTL files for any documentation" 43 | 44 | pdf: spec 45 | DSRC := src 46 | ## }}} 47 | 48 | .PHONY: spec 49 | ## {{{ 50 | spec: spec.pdf 51 | 52 | spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps 53 | cd $(DSRC)/; latex spec.tex 54 | cd $(DSRC)/; latex spec.tex 55 | cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../spec.ps spec.dvi 56 | ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf 57 | -grep -i warning $(DSRC)/spec.log 58 | @rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log 59 | @rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc 60 | @rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof 61 | @rm -f $(DSRC)/spec.out spec.ps 62 | ## }}} 63 | 64 | .PHONY: clean 65 | ## {{{ 66 | clean: 67 | rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log 68 | rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc 69 | rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof 70 | rm -f $(DSRC)/spec.out spec.ps spec.pdf 71 | rm -f $(LICENSE).pdf 72 | ## }}} 73 | -------------------------------------------------------------------------------- /doc/axi-multiwrite.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/axi-multiwrite.dia -------------------------------------------------------------------------------- /doc/axi-multiwrite.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/axi-multiwrite.png -------------------------------------------------------------------------------- /doc/axis2mm_mb.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'P..............'}, 3 | {}, 4 | {name: 'cmd_start', wave: '010............'}, 5 | {name: 'cmd_length', wave: '2..............', data: ['9']}, 6 | {name: 'cmd_threshold', wave: '2..............', data: ['4']}, 7 | {name: 'fifo_fill', wave: '2.34......5....', data: ['2','3','4','3']}, 8 | {name: 'r_busy', wave: '0.1...........0'}, 9 | {name: 'done_interrupt',wave: '0.............1'}, 10 | {}, 11 | {name: 'M_AXI_AWVALID', wave: '0...10..10.10..'}, 12 | {name: 'M_AXI_AWLEN', wave: 'x...2x..2x.2xx.', data: ['3','2','1']}, 13 | {}, 14 | {name: 'S_AXI_WVALID', wave: '0...1........0.'}, 15 | {name: 'S_AXI_WDATA', wave: 'x...234523452x.'}, 16 | {name: 'S_AXI_WLAST', wave: 'x...0..10.101x.'}, 17 | {}, 18 | {name: 'S_AXI_BVALID', wave: '0.........101.0'} 19 | ]} -------------------------------------------------------------------------------- /doc/axis2mm_mb.png: -------------------------------------------------------------------------------- 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'0.......1........0.'}, 15 | {name: 'S_AXI_WDATA', wave: 'x.......234523452x.'}, 16 | {name: 'S_AXI_WLAST', wave: 'x.......0.......1x.'}, 17 | {}, 18 | {name: 'S_AXI_BVALID', wave: '0................10'} 19 | ]} -------------------------------------------------------------------------------- /doc/axis2mm_sb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/axis2mm_sb.png -------------------------------------------------------------------------------- /doc/axisafety.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/axisafety.dia -------------------------------------------------------------------------------- /doc/axisafety.png: -------------------------------------------------------------------------------- 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'wb_stall', wave: 'x.0x'}, 11 | {}, 12 | {name: 'axi_avalid', wave: '0..1'}, 13 | {name: 'axi_awaddr[31:0]', wave: 'x..3', data: ['h..3']}, 14 | {name: 'axi_wvalid', wave: '0..1'}, 15 | {name: 'axi_wstrb[3:0]', wave: 'x..3', data: ['1']} 16 | ]} -------------------------------------------------------------------------------- /doc/gfx/axi-bad-wstrb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axi-bad-wstrb.png -------------------------------------------------------------------------------- /doc/gfx/axi-fault-isolator.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axi-fault-isolator.dia -------------------------------------------------------------------------------- /doc/gfx/axi-gpio-reads.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'p..............'}, 3 | {name: 'S_AXI_ARESETN',wave: '0.1............'}, 4 | {}, 5 | {name: 'S_AXI_ARVALID',wave: '0..1....x1....x'}, 6 | {name: 'S_AXI_ARREADY',wave: '0......10....10'}, 7 | {}, 8 | {name: 'S_AXI_RVALID', wave: '0.......10....1'}, 9 | ]} -------------------------------------------------------------------------------- /doc/gfx/axi-gpio-reads.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axi-gpio-reads.png -------------------------------------------------------------------------------- /doc/gfx/axi-gpio-writes.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'p....................'}, 3 | {name: 'S_AXI_ARESETN',wave: '0.1..................'}, 4 | {}, 5 | {name: 'S_AXI_AWVALID',wave: '0..1................x'}, 6 | {name: 'S_AXI_AWREADY',wave: '0......10....10....10', data: ['A','B','C','D','E','F','G','H']}, 7 | {}, 8 | {name: 'S_AXI_WVALID', wave: '0..1................x'}, 9 | {name: 'S_AXI_WREADY', wave: '0......10....10....10', data: ['A','B','C','D','E','F','G','H']}, 10 | {name: 'S_AXI_WDATA', wave: 'x..0....3.....4.....x'}, 11 | {}, 12 | {name: 'S_AXI_BVALID', wave: '0......10.....10....1'}, 13 | {name: 'o_gpio', wave: 'x.....0.....3......4.'} 14 | ]} -------------------------------------------------------------------------------- /doc/gfx/axi-gpio-writes.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axi-gpio-writes.png -------------------------------------------------------------------------------- /doc/gfx/axi-handshake-ref.png: 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instead of 8 | %% \includegraphics{.pdf} 9 | %% To scale the image, write 10 | %% \def\svgwidth{} 11 | %% \input{.pdf_tex} 12 | %% instead of 13 | %% \includegraphics[width=]{.pdf} 14 | %% 15 | %% Images with a different path to the parent latex file can 16 | %% be accessed with the `import' package (which may need to be 17 | %% installed) using 18 | %% \usepackage{import} 19 | %% in the preamble, and then including the image with 20 | %% \import{}{.pdf_tex} 21 | %% Alternatively, one can specify 22 | %% \graphicspath{{/}} 23 | %% 24 | %% For more information, please see info/svg-inkscape on CTAN: 25 | %% http://tug.ctan.org/tex-archive/info/svg-inkscape 26 | %% 27 | \begingroup% 28 | \makeatletter% 29 | \providecommand\color[2][]{% 30 | \errmessage{(Inkscape) Color is used for the text in Inkscape, but the package 'color.sty' is not loaded}% 31 | \renewcommand\color[2][]{}% 32 | }% 33 | \providecommand\transparent[1]{% 34 | \errmessage{(Inkscape) Transparency is used (non-zero) for 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-------------------------------------------------------------------------------- /doc/gfx/axifull-wlast.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'p........'}, 3 | {name: 'S_AXI_ARESETN', wave: '01.......'}, 4 | {}, 5 | {name: 'S_AXI_AWVALID', wave: '0.1.0....'}, 6 | {name: 'S_AXI_AWREADY', wave: '0..10....'}, 7 | {name: 'S_AXI_AWLEN', wave: 'x.2.x....', data: ['8']}, 8 | {}, 9 | {name: 'S_AXI_WVALID', wave: '0..1.01..'}, 10 | {name: 'S_AXI_WREADY', wave: '0...1.0..'}, 11 | {name: 'S_AXI_WDATA', wave: '0...2x3..'}, 12 | {name: 'S_AXI_WLAST', wave: 'x..0.10..'}, 13 | ]} -------------------------------------------------------------------------------- /doc/gfx/axifull-wlast.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axifull-wlast.png -------------------------------------------------------------------------------- /doc/gfx/axifull-wr.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'p......p...'}, 3 | {}, 4 | {name: 'S_AXI_AWVALID', wave: '01.0.......'}, 5 | {name: 'S_AXI_AWREADY', wave: '0.10.......'}, 6 | {name: 'S_AXI_AWLEN', wave: 'x2.x.......', data: ['5']}, 7 | {}, 8 | {name: 'S_AXI_WVALID', wave: '0.1......0.'}, 9 | {name: 'S_AXI_WREADY', wave: '0..1.....0.'}, 10 | {name: 'S_AXI_WDATA', wave: '0.2.345230.'}, 11 | {name: 'S_AXI_WLAST', wave: 'x.0.....1x.'}, 12 | {}, 13 | {name: 'S_AXI_BVALID', wave: '0........10'}, 14 | {}, 15 | {name: 'axi_awv_awr_flag', wave: '0..1.....0.'}, 16 | ]} -------------------------------------------------------------------------------- /doc/gfx/axifull-wr.png: -------------------------------------------------------------------------------- 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'P..........'}, 3 | {name: 'S_AXI_ARESETN', wave: '01.........'}, 4 | {}, 5 | {name: 'S_AXI_ARVALID', wave: '0.1....0...', data:[]}, 6 | {name: 'S_AXI_ARREADY', wave: '01.0101....', data:[]}, 7 | {name: 'S_AXI_ARID', wave: 'x.3.4.5x...', data:['I0','I1','I2']}, 8 | {name: 'S_AXI_ARADDR', wave: 'x.3.4.5x...', data:['A0','A1','A2']}, 9 | {name: 'S_AXI_ARLEN', wave: 'x.3.4.5x...', data:['1','1','1']}, 10 | {}, 11 | {name: 'o_cyc', wave: 'x0.1.....0.', data:['A0']}, 12 | {name: 'o_stb', wave: 'x0.1.....0.', data:['A0']}, 13 | {name: 'o_addr', wave: 'x0.3344550.', data:['A0','','A1','','A2']}, 14 | {name: 'i_ack', wave: 'x0.1.....0.'}, 15 | {name: 'i_data', wave: 'x..3344550.', data:['D0','D1','D2','D3','D4','D5']}, 16 | {}, 17 | {name: 'S_AXI_RVALID', wave: '0...1.....0'}, 18 | {name: 'S_AXI_RREADY', wave: 'x1.........'}, 19 | {name: 'S_AXI_RID', wave: 'x...3.4.5.x', data:['I0','I1','I2']}, 20 | {name: 'S_AXI_RDATA', wave: 'x...334455x', data:['D0','D1','D2','D3','D4','D5']}, 21 | {name: 'S_AXI_RLAST', wave: 'x...010101x'}, 22 | ]} -------------------------------------------------------------------------------- /doc/gfx/aximrd2wbsp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/aximrd2wbsp.png -------------------------------------------------------------------------------- /doc/gfx/aximwr2wbsp-burst.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'p............'}, 3 | {name: 'S_AXI_ARESETN',wave: '01...........'}, 4 | {}, 5 | {name: 'S_AXI_AWVALID',wave: '0.1....0.....'}, 6 | {name: 'S_AXI_AWREADY',wave: '01.010101....'}, 7 | {name: 'S_AXI_AWID', wave: 'x.2....x.....', data: ['Constant ID']}, 8 | {name: 'S_AXI_AWADDR', wave: 'x.34.5.x.....', data: ['A0','A1','A2']}, 9 | {name: 'S_AXI_AWLEN', wave: 'x.34.5.x.....', data: ['1','1','1']}, 10 | {}, 11 | {name: 'S_AXI_WVALID', wave: '0.1.....0....'}, 12 | {name: 'S_AXI_WREADY', wave: '01...........'}, 13 | {name: 'S_AXI_WDATA', wave: 'x.334455x....', data: ['D0','D1','D2','D3','D4','D5']}, 14 | {name: 'S_AXI_WLAST', wave: 'x.010101x....', data: ['0']}, 15 | {}, 16 | {name: 'o_wb_stb', wave: '0..1.....0...'}, 17 | {name: 'o_wb_addr', wave: 'x..334455x...', data: ['A0','','A1','','A2']}, 18 | {name: 'o_wb_data', wave: 'x..334455x...', data: ['D0','D1','D2','D3','D4','D5']}, 19 | {name: 'i_wb_ack', wave: '0..1.....0...'}, 20 | {}, 21 | {name: 'S_AXI_BVALID', wave: '0......304050'}, 22 | {name: 'S_AXI_BREADY', wave: 'x......1x1x1x'}, 23 | {name: 'S_AXI_BID', wave: 'x......2....x', data: ['Same constant ID']}, 24 | ]} -------------------------------------------------------------------------------- /doc/gfx/aximwr2wbsp-burst.png: -------------------------------------------------------------------------------- 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{name: 'o_wb_stb', wave: '0..1..01.'}, 17 | {name: 'o_wb_addr', wave: 'x..345.6.', data: ['A0','A1','A2','A3']}, 18 | {name: 'o_wb_data', wave: 'x..345x6x', data: ['D0','D1','D2','D3','D4','D5']}, 19 | {name: 'i_wb_stall',wave: '0......1.'}, 20 | {name: 'i_wb_ack', wave: '0..1..0.1'}, 21 | {}, 22 | {name: 'S_AXI_BVALID', wave: '0.....345'}, 23 | {name: 'S_AXI_BREADY', wave: 'x.....1..'}, 24 | {name: 'S_AXI_BID', wave: 'x.....2..', data: ['2']}, 25 | ]} -------------------------------------------------------------------------------- /doc/gfx/aximwr2wbsp-single.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/aximwr2wbsp-single.png -------------------------------------------------------------------------------- /doc/gfx/axisafety-fault.dia: -------------------------------------------------------------------------------- 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'0........3..4..5..6..7..8..9..3..4..5..6..7'}, 9 | {name: 'M_AXI_ARLEN', wave: 'x........2.................................', data: ['5']}, 10 | {}, 11 | {name: 'M_AXI_RVALID', wave: '0.........1........................01....01'}, 12 | {name: 'M_AXI_RDATA', wave: 'x.........3333334444445555556666667x77777x8'}, 13 | {name: 'M_AXI_RLAST', wave: 'x.........0....30....40....50....60x0...7x0'}, 14 | {}, 15 | {name: 'M_AXIS_TVALID', wave: '0..........1........................01....0'}, 16 | {name: 'M_AXIS_TDATA', wave: 'x..........3333334444445555556666667x77777x'}, 17 | {name: 'H-LAST', wave: 'x..........0....10....10....10....10.....1x'}, 18 | {name: 'V-LAST', wave: 'x..........0.............................1x'}, 19 | ]} -------------------------------------------------------------------------------- /doc/gfx/axivdma.png: -------------------------------------------------------------------------------- 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['0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16','17','18','19','20','21','22','23','24']}, 10 | {name: 'M_AXI_AWVALID', wave: '0...........10......10......10......10..'}, 11 | {name: 'M_AXI_WVALID', wave: '0...........2345678923456789234567892345'}, 12 | {name: 'M_AXI_WLAST', wave: 'x...........0......10......10......10...', data: ['A0','A1','A2','A3','A4','A5','A6','A7','A8','A9']}, 13 | {name: 'M_AXI_BVALID', wave: '0...................10......10......10..'}, 14 | {}, 15 | {name: 'M_AXI_ARVALID',wave: '0....................10......10......10.'}, 16 | {name: 'M_AXI_RVALID', wave: '0.....................23456789234567890.'}, 17 | {name: 'M_AXI_RLAST', wave: 'x.....................0......10......1x.', data: ['D0','D1','D2','D3','d1','d2','d3','d4']}, 18 | {}, 19 | {name: 'ofifo_fill', wave: '0......................2...............0', data: ['1']}, 20 | {name: 'M_AXI_TVALID',wave: '0......................11111111111111110', data: ['D0','D1','D2','D3','d1','d2','d3','d4']}, 21 | ]} -------------------------------------------------------------------------------- /doc/gfx/axivfifo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axivfifo.png -------------------------------------------------------------------------------- /doc/gfx/axixbar-latency.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/axixbar-latency.png -------------------------------------------------------------------------------- /doc/gfx/brken-axilite.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/brken-axilite.dia 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-------------------------------------------------------------------------------- /doc/gfx/wbaxi-bridge-rresp-fail.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'S_AXI_ACLK', wave: 'P...........'}, 3 | {name: 'S_AXI_ARESETN', wave: '01..........'}, 4 | {}, 5 | {name: 'WB_CYC', wave: '0.1.........'}, 6 | {name: 'WB_STB', wave: '0.10.10.10..'}, 7 | {name: 'WB_WE', wave: 'x.0x.0x.0x..'}, 8 | {name: 'WB_STALL', wave: 'x.0xx0xx0xx.'}, 9 | {name: 'WB_ACK', wave: '0...........'}, 10 | {name: 'WB_ERR', wave: '0...........'}, 11 | {}, 12 | {name: 'S_AXI_ARVALID', wave: '0..10.10.10.'}, 13 | {name: 'S_AXI_RVALID', wave: 'x0..10.10.10'}, 14 | {name: 'S_AXI_RRESP', wave: 'x...2.......', data: ['2b11']}, 15 | ]} -------------------------------------------------------------------------------- /doc/gfx/wbaxi-bridge-rresp-fail.png: -------------------------------------------------------------------------------- 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'1.0....................................................'}, 3 | {name: 'i_wb_clk', wave: '0.1010101.0101010.1010101.0101010.1010101.0101010.10101'}, 4 | {name: 'i_wb_cyc', wave: '0.....1.............................................0..'}, 5 | {name: 'i_wb_stb', wave: '0.....1.1..1.1.1..1.0.1.0..1.1.1..0....................'}, 6 | {name: 'i_wb_addr', wave: '0.....3.4..5.6.7..8.0.9.0..3.4.5..0....................', data: ['A0','A1','A2','A3','A4','A5','A6','A7','A8','A9']}, 7 | {name: 'o_wb_ack', wave: '0..........................1.1.1..1.0.1.1..1.1.1..1.0..'}, 8 | {name: 'o_wb_data', wave: '0..........................3.4.5..6.0.7.8..9.3.4..5.0..', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9']}, 9 | {}, 10 | {name: 'i_xclk_clk',wave: '0.101.010.101.010.101.010.101.010.101.010.101.010.101.0'}, 11 | {name: 'o_xclk_cyc',wave: '0.................1....................................'}, 12 | {name: 'o_xclk_stb',wave: '0.................1.1..1..1.1..1..1.1..1..1.0..0..0.0..', data: ['D0','D1','D2','D3','d1','d2','d3','d4']}, 13 | {name: 'i_xclk_ack',wave: '0.................1.1..1..1.1..1..1.1..1..1.0..0..0.0..', data: ['D0','D1','D2','D3','d1','d2','d3','d4']}, 14 | {name: 'i_xclk_data',wave:'0.................3.4..5..6.7..8..9.3..4..5.0..0..0.0..', data: ['D0','D1','D2','D3','D4','D5','D6','D7','D8','D9']} 15 | ]} -------------------------------------------------------------------------------- /doc/gfx/wbxclk.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/wbxclk.png -------------------------------------------------------------------------------- /doc/gfx/xilinx-axilite2axi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/xilinx-axilite2axi.png -------------------------------------------------------------------------------- /doc/gfx/xlnxstream.json: -------------------------------------------------------------------------------- 1 | {signal: [ 2 | {name: 'M_AXIS_ACLK', wave: 'P.|..........'}, 3 | {name: 'M_AXIS_ARESETN', wave: '01|..........'}, 4 | {}, 5 | {name: 'M_AXIS_TVALID', wave: '0.|.1.......0', data: ['S1','S2']}, 6 | {name: 'M_AXIS_TREADY', wave: 'x.|x1.....010', data: ['S1','S2']}, 7 | {name: 'M_AXIS_TDATA', wave: 'x.|x3456723.x', data: ['D1','D2','D3','D4','D5','D6','D7']}, 8 | {name: 'M_AXIS_TLAST', wave: '0.|........10'}, 9 | ]} 10 | -------------------------------------------------------------------------------- /doc/gfx/xlnxstream.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/xlnxstream.png -------------------------------------------------------------------------------- /doc/gfx/xlnxstream_trace.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gfx/xlnxstream_trace.png -------------------------------------------------------------------------------- /doc/gpl-3.0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/gpl-3.0.pdf -------------------------------------------------------------------------------- /doc/orconf2019.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/wb2axip/70f9d2b041742fb1823208c4ff4b0a099e669b5e/doc/orconf2019.pdf -------------------------------------------------------------------------------- /rtl/.gitignore: -------------------------------------------------------------------------------- 1 | *.ys 2 | ivcheck 3 | -------------------------------------------------------------------------------- /rtl/axisrandom.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtl/axisrandom.v 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: An AXI-stream based pseudorandom noise generator 8 | // 9 | // Creator: Dan Gisselquist, Ph.D. 10 | // Gisselquist Technology, LLC 11 | // 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // }}} 14 | // Copyright (C) 2019-2025, Gisselquist Technology, LLC 15 | // {{{ 16 | // This file is part of the WB2AXIP project. 17 | // 18 | // The WB2AXIP project contains free software and gateware, licensed under the 19 | // Apache License, Version 2.0 (the "License"). You may not use this project, 20 | // or this file, except in compliance with the License. You may obtain a copy 21 | // of the License at 22 | // }}} 23 | // http://www.apache.org/licenses/LICENSE-2.0 24 | // {{{ 25 | // Unless required by applicable law or agreed to in writing, software 26 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 27 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 28 | // License for the specific language governing permissions and limitations 29 | // under the License. 30 | // 31 | //////////////////////////////////////////////////////////////////////////////// 32 | // 33 | `default_nettype none 34 | // }}} 35 | module axisrandom #( 36 | // {{{ 37 | localparam C_AXIS_DATA_WIDTH = 32 38 | // }}} 39 | ) ( 40 | // {{{ 41 | input wire S_AXI_ACLK, 42 | input wire S_AXI_ARESETN, 43 | // 44 | output reg M_AXIS_TVALID, 45 | input wire M_AXIS_TREADY, 46 | output reg [C_AXIS_DATA_WIDTH-1:0] M_AXIS_TDATA 47 | // }}} 48 | ); 49 | 50 | localparam INITIAL_FILL = { 1'b1, {(C_AXIS_DATA_WIDTH-1){1'b0}} }; 51 | localparam LGPOLY = 31; 52 | localparam [LGPOLY-1:0] CORE_POLY = { 31'h00_00_20_01 }; 53 | localparam [C_AXIS_DATA_WIDTH-1:0] POLY 54 | = { CORE_POLY, {(C_AXIS_DATA_WIDTH-31){1'b0}} }; 55 | 56 | // M_AXIS_TVALID 57 | // {{{ 58 | initial M_AXIS_TVALID = 1'b0; 59 | always @(posedge S_AXI_ACLK) 60 | if (!S_AXI_ARESETN) 61 | M_AXIS_TVALID <= 1'b0; 62 | else 63 | M_AXIS_TVALID <= 1'b1; 64 | // }}} 65 | 66 | // M_AXIS_TDATA 67 | // {{{ 68 | // 69 | // Note--this setup is *FAR* from cryptographically random. 70 | // 71 | initial M_AXIS_TDATA = INITIAL_FILL; 72 | always @(posedge S_AXI_ACLK) 73 | if (!S_AXI_ARESETN) 74 | M_AXIS_TDATA <= INITIAL_FILL; 75 | else if (M_AXIS_TREADY) 76 | begin 77 | M_AXIS_TDATA <= M_AXIS_TDATA >> 1; 78 | M_AXIS_TDATA[C_AXIS_DATA_WIDTH-1] <= ^(M_AXIS_TDATA & POLY); 79 | end 80 | // }}} 81 | 82 | // Verilator lint_off UNUSED 83 | // {{{ 84 | wire unused; 85 | assign unused = &{ 1'b0 }; 86 | // Verilator lint_on UNUSED 87 | // }}} 88 | //////////////////////////////////////////////////////////////////////////////// 89 | //////////////////////////////////////////////////////////////////////////////// 90 | //////////////////////////////////////////////////////////////////////////////// 91 | // 92 | // Formal properties used in verfiying this core 93 | // {{{ 94 | //////////////////////////////////////////////////////////////////////////////// 95 | //////////////////////////////////////////////////////////////////////////////// 96 | //////////////////////////////////////////////////////////////////////////////// 97 | `ifdef FORMAL 98 | reg f_past_valid; 99 | 100 | initial f_past_valid = 1'b0; 101 | always @(posedge S_AXI_ACLK) 102 | f_past_valid <= 1'b1; 103 | 104 | always @(*) 105 | if (!f_past_valid) 106 | assume(!S_AXI_ARESETN); 107 | 108 | // Make certain this polynomial will never degenerate, and so that 109 | // this random number stream will go on for ever--eventually repeating 110 | // after 2^LGPOLY-1 (hopefully) elements. 111 | always @(*) 112 | assert(M_AXIS_TDATA[C_AXIS_DATA_WIDTH-1 113 | :C_AXIS_DATA_WIDTH-LGPOLY] != 0); 114 | 115 | // AXI stream has only one significant property 116 | // {{{ 117 | // Here we'll modify it slightly for our purposes 118 | always @(posedge S_AXI_ACLK) 119 | if (!f_past_valid || $past(!S_AXI_ARESETN)) 120 | assert(!M_AXIS_TVALID); 121 | else begin 122 | assert(M_AXIS_TVALID); 123 | if ($past(M_AXIS_TVALID && !M_AXIS_TREADY)) 124 | // Normally I'd assesrt M_AXIS_TVALID here, not above, 125 | // but this core *ALWAYS* produces data 126 | assert($stable(M_AXIS_TDATA)); 127 | else if ($past(M_AXIS_TVALID)) 128 | // Insist that the data always changes otherwise 129 | assert($changed(M_AXIS_TDATA)); 130 | end 131 | // }}} 132 | `endif 133 | // }}} 134 | endmodule 135 | -------------------------------------------------------------------------------- /rtl/axlite_wrapper.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- Filename: axlite_wrapper.vhd 4 | -- 5 | -- Project: WB2AXIPSP: bus bridges and other odds and ends 6 | -- 7 | -- Purpose: When wrapped with this wrapper, the axlite2wbsp.v core was 8 | -- verified to work in FPGA silicon via Vivado. 9 | -- 10 | -- Thank you Ambroz for donating this code! 11 | -- 12 | -- Creator: Ambroz Bizjak 13 | -- 14 | -------------------------------------------------------------------------------- 15 | -- 16 | -- Copyright (C) 2019-2023, Gisselquist Technology, LLC 17 | -- 18 | -- This file is part of the WB2AXIP project. 19 | -- 20 | -- The WB2AXIP project contains free software and gateware, licensed under the 21 | -- Apache License, Version 2.0 (the "License"). You may not use this project, 22 | -- or this file, except in compliance with the License. You may obtain a copy 23 | -- of the License at 24 | -- 25 | -- http://www.apache.org/licenses/LICENSE-2.0 26 | -- 27 | -- Unless required by applicable law or agreed to in writing, software 28 | -- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 29 | -- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 30 | -- License for the specific language governing permissions and limitations 31 | -- under the License. 32 | -- 33 | -------------------------------------------------------------------------------- 34 | -- 35 | -- 36 | library IEEE; 37 | use IEEE.STD_LOGIC_1164.ALL; 38 | 39 | entity axlite2wbsp_wrapper is 40 | generic ( 41 | C_AXI_ADDR_WIDTH : integer := 28; 42 | LGFIFO : integer := 4; 43 | F_MAXSTALL : integer := 3; 44 | F_MAXDELAY : integer := 3; 45 | 46 | --- Must not be changed. 47 | C_AXI_DATA_WIDTH : integer := 32 48 | ); 49 | port ( 50 | s_axi_aclk : in std_logic; 51 | s_axi_aresetn : in std_logic; 52 | 53 | s_axi_awready : out std_logic; 54 | s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); 55 | s_axi_awcache : in std_logic_vector(3 downto 0); 56 | s_axi_awprot : in std_logic_vector(2 downto 0); 57 | s_axi_awvalid : in std_logic; 58 | s_axi_wready : out std_logic; 59 | s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); 60 | s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0); 61 | s_axi_wvalid : in std_logic; 62 | s_axi_bresp : out std_logic_vector(1 downto 0); 63 | s_axi_bvalid : out std_logic; 64 | s_axi_bready : in std_logic; 65 | s_axi_arready : out std_logic; 66 | s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); 67 | s_axi_arcache : in std_logic_vector(3 downto 0); 68 | s_axi_arprot : in std_logic_vector(2 downto 0); 69 | s_axi_arvalid : in std_logic; 70 | s_axi_rresp : out std_logic_vector(1 downto 0); 71 | s_axi_rvalid : out std_logic; 72 | s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); 73 | s_axi_rready : in std_logic; 74 | 75 | m_wb_reset : out std_logic; 76 | m_wb_cyc : out std_logic; 77 | m_wb_stb : out std_logic; 78 | m_wb_we : out std_logic; 79 | m_wb_adr : out std_logic_vector(C_AXI_ADDR_WIDTH-2-1 downto 0); 80 | m_wb_dat_w : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); 81 | m_wb_sel : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0); 82 | m_wb_ack : in std_logic; 83 | m_wb_stall : in std_logic; 84 | m_wb_dat_r : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); 85 | m_wb_err : in std_logic 86 | ); 87 | end axlite2wbsp_wrapper; 88 | 89 | architecture Behavioral of axlite2wbsp_wrapper is 90 | 91 | begin 92 | axlite2wbsp : entity work.axlite2wbsp 93 | generic map ( 94 | C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH, 95 | LGFIFO => LGFIFO, 96 | F_MAXSTALL => F_MAXSTALL, 97 | F_MAXDELAY => F_MAXDELAY 98 | ) 99 | port map ( 100 | i_clk => s_axi_aclk, 101 | i_axi_reset_n => s_axi_aresetn, 102 | o_axi_awready => s_axi_awready, 103 | i_axi_awaddr => s_axi_awaddr, 104 | i_axi_awcache => s_axi_awcache, 105 | i_axi_awprot => s_axi_awprot, 106 | i_axi_awvalid => s_axi_awvalid, 107 | o_axi_wready => s_axi_wready, 108 | i_axi_wdata => s_axi_wdata, 109 | i_axi_wstrb => s_axi_wstrb, 110 | i_axi_wvalid => s_axi_wvalid, 111 | o_axi_bresp => s_axi_bresp, 112 | o_axi_bvalid => s_axi_bvalid, 113 | i_axi_bready => s_axi_bready, 114 | o_axi_arready => s_axi_arready, 115 | i_axi_araddr => s_axi_araddr, 116 | i_axi_arcache => s_axi_arcache, 117 | i_axi_arprot => s_axi_arprot, 118 | i_axi_arvalid => s_axi_arvalid, 119 | o_axi_rresp => s_axi_rresp, 120 | o_axi_rvalid => s_axi_rvalid, 121 | o_axi_rdata => s_axi_rdata, 122 | i_axi_rready => s_axi_rready, 123 | o_reset => m_wb_reset, 124 | o_wb_cyc => m_wb_cyc, 125 | o_wb_stb => m_wb_stb, 126 | o_wb_we => m_wb_we, 127 | o_wb_addr => m_wb_adr, 128 | o_wb_data => m_wb_dat_w, 129 | o_wb_sel => m_wb_sel, 130 | i_wb_ack => m_wb_ack, 131 | i_wb_stall => m_wb_stall, 132 | i_wb_data => m_wb_dat_r, 133 | i_wb_err => m_wb_err 134 | ); 135 | 136 | end Behavioral; 137 | -------------------------------------------------------------------------------- /rtl/sfifothresh.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtl/sfifothresh.v 4 | // {{{ 5 | // Project: WB2AXIPSP: bus bridges and other odds and ends 6 | // 7 | // Purpose: A synchronous data FIFO, generated from sfifo.v. This 8 | // particular version extends the FIFO interface with a threshold 9 | // calculator, to create an interrupt/signal when the FIFO has greater 10 | // than the threshold elements within it. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2019-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This file is part of the WB2AXIP project. 20 | // 21 | // The WB2AXIP project contains free software and gateware, licensed under the 22 | // Apache License, Version 2.0 (the "License"). You may not use this project, 23 | // or this file, except in compliance with the License. You may obtain a copy 24 | // of the License at 25 | // }}} 26 | // http://www.apache.org/licenses/LICENSE-2.0 27 | // {{{ 28 | // Unless required by applicable law or agreed to in writing, software 29 | // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 30 | // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 31 | // License for the specific language governing permissions and limitations 32 | // under the License. 33 | // 34 | //////////////////////////////////////////////////////////////////////////////// 35 | // 36 | `default_nettype none 37 | // }}} 38 | module sfifothresh(i_clk, i_reset, 39 | i_wr, i_data, o_full, o_fill, 40 | i_rd, o_data, o_empty, 41 | i_threshold, o_int); 42 | parameter BW=8; // Byte/data width 43 | parameter LGFLEN=4; 44 | parameter [0:0] OPT_ASYNC_READ = 1'b1; 45 | localparam FLEN=(1<= i_threshold); 82 | 2'b10: o_int <= (o_fill+1 >= i_threshold); 83 | default: o_int <= o_fill >= i_threshold; 84 | endcase 85 | 86 | `ifdef FORMAL 87 | reg f_past_valid; 88 | 89 | initial f_past_valid = 0; 90 | always @(posedge i_clk) 91 | f_past_valid <= 1'b1; 92 | 93 | always @(posedge i_clk) 94 | if (!f_past_valid || $past(i_reset)) 95 | assert(!o_int); 96 | else 97 | assert(o_int == (o_fill >= $past(i_threshold))); 98 | `endif 99 | endmodule 100 | -------------------------------------------------------------------------------- /wb2axip.core: -------------------------------------------------------------------------------- 1 | CAPI=1 2 | [main] 3 | description = Pipelined Wishbone to AXI converter 4 | 5 | [fileset rtl] 6 | files = rtl/wbm2axisp.v 7 | file_type = verilogSource 8 | 9 | [provider] 10 | name=github 11 | user=ZipCPU 12 | repo=wb2axip 13 | version = master 14 | --------------------------------------------------------------------------------