├── .gitignore ├── INSTALL.md ├── Makefile ├── README.md ├── bench ├── .gitignore ├── asm │ ├── .gitignore │ ├── Makefile │ ├── cmptest.s │ ├── hellosim.s │ ├── nstrtest.s │ ├── simscript.ld │ ├── simtest.s │ └── simuart.s ├── cpp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── dcache_tb.cpp │ ├── helloworld.c │ ├── memsim.cpp │ ├── memsim.h │ └── mpyraw.c ├── formal │ ├── .gitignore │ ├── Makefile │ ├── abs_div.v │ ├── abs_mpy.v │ ├── axidcache.gtkw │ ├── axidcache.sby │ ├── axiicache.gtkw │ ├── axiicache.sby │ ├── axilfetch.gtkw │ ├── axilfetch.sby │ ├── axilfetch64.gtkw │ ├── axilops.gtkw │ ├── axilops.sby │ ├── axilperiphs.sby │ ├── axilpipe.gtkw │ ├── axilpipe.sby │ ├── axiops.gtkw │ ├── axiops.sby │ ├── axipipe.gtkw │ ├── axipipe.sby │ ├── busdelay.gtkw │ ├── busdelay.sby │ ├── busdelay.ys │ ├── cpuops.sby │ ├── cpuops.ys │ ├── dblfetch.gtkw │ ├── dblfetch.sby │ ├── dblfetch.ys │ ├── dblfetchlogic.ys │ ├── dcache.gtkw │ ├── dcache.sby │ ├── dcache.ys │ ├── div.gtkw │ ├── div.sby │ ├── div.ys │ ├── f_idecode.v │ ├── fdebug.v │ ├── fetchlogic.ys │ ├── ffetch.v │ ├── fmem.v │ ├── genreport.pl │ ├── icontrol.gtkw │ ├── icontrol.sby │ ├── icontrol.ys │ ├── idecode.gtkw │ ├── idecode.sby │ ├── memdev.sby │ ├── memlogic.ys │ ├── memops.gtkw │ ├── memops.sby │ ├── pfcache.gtkw │ ├── pfcache.sby │ ├── pfcache.ys │ ├── pffifo.sby │ ├── pipefetch.sby │ ├── pipemem.gtkw │ ├── pipemem.sby │ ├── pipemem.ys │ ├── prefetch.gtkw │ ├── prefetch.sby │ ├── prefetch.ys │ ├── report.html │ ├── wbdblpriarb.sby │ ├── wbdblpriarb.ys │ ├── wbdmac.sby │ ├── wbdmac.ys │ ├── wbpriarbiter.sby │ ├── wbpriarbiter.ys │ ├── wbwatchdog.sby │ ├── wbwatchdog.ys │ ├── zipaxi.sby │ ├── zipaxil.sby │ ├── zipbones.gtkw │ ├── zipbones.sby │ ├── zipcore.gtkw │ ├── zipcore.sby │ ├── zipcounter.sby │ ├── zipcounter.ys │ ├── zipcpu.gtkw │ ├── zipcpu.ys │ ├── zipdma_mm2s.gtkw │ ├── zipdma_mm2s.sby │ ├── zipdma_rxgears.gtkw │ ├── zipdma_rxgears.sby │ ├── zipdma_s2mm.gtkw │ ├── zipdma_s2mm.sby │ ├── zipdma_txgears.gtkw │ ├── zipdma_txgears.sby │ ├── zipjiffies.sby │ ├── zipjiffies.ys │ ├── zipmmu.gtkw │ ├── zipmmu.sby │ ├── zipmmu.ys │ ├── ziptimer.sby │ └── ziptimer.ys ├── mcy │ ├── .gitignore │ └── zipcpu │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── config.mcy │ │ ├── eq_bmc.sby │ │ ├── eq_bmc.sh │ │ ├── eq_sim3.sby │ │ ├── eq_sim3.sh │ │ ├── miter.sv │ │ ├── sim_verilator.sh │ │ ├── zipbones.v │ │ └── zipcpu.cpp ├── rtl │ ├── Makefile │ ├── memdev.v │ └── zipmmu_tb.v └── zipsim.ld ├── doc ├── .gitignore ├── Makefile ├── gfx │ ├── .gitignore │ ├── 20220720-betterdma.png │ ├── 20220720-dmaregs.png │ ├── 20220720-oldlimits.png │ ├── 20220720-priordma.png │ ├── 20220720-sgdma.png │ ├── axidcache-reads.png │ ├── axiicache.png │ ├── axilfetch_dbl.png │ ├── axilfetch_dbl64.png │ ├── axilfetch_fifo.png │ ├── axilfetch_fifo64.png │ ├── axilfetch_raw.png │ ├── axilfetch_raw64.png │ ├── axilpipe-reads.png │ ├── axilpipe-ureads.png │ ├── bc.eps │ ├── bcmem.eps │ ├── bdbroken.eps │ ├── bdly.eps │ ├── bra.eps │ ├── bus-structure.png │ ├── cpu.eps │ ├── cpu.png │ ├── fullpline.eps │ ├── memrd.eps │ ├── memwr.eps │ ├── mstld.eps │ ├── pfmiss.eps │ ├── pfmissn.eps │ ├── read-hazard-fixed.png │ ├── read-hazard.png │ ├── regset.eps │ ├── regset.png │ ├── sleep.eps │ ├── stacking.eps │ ├── stuttra.eps │ ├── stuttrb.eps │ ├── system.eps │ ├── system.png │ ├── zipbones.eps │ ├── zipbones.png │ └── zipdma-blocks.png ├── gpl-3.0.pdf ├── memsurvey.png ├── nextgen.html ├── nextgen.png ├── orconf.pdf ├── orconf2017.pdf ├── orconf2018.pdf ├── spec.pdf ├── src │ ├── GT.eps │ ├── gpl-3.0.tex │ ├── gqtekspec.cls │ └── spec.tex ├── usage.pdf ├── usage.tex └── wbspec_b4.pdf ├── rtl ├── .gitignore ├── Makefile ├── README.md ├── core │ ├── .gitignore │ ├── README.md │ ├── axidcache.v │ ├── axiicache.v │ ├── axilfetch.v │ ├── axilops.v │ ├── axilpipe.v │ ├── axiops.v │ ├── axipipe.v │ ├── cpuops.v │ ├── dblfetch.v │ ├── dcache.v │ ├── div.v │ ├── idecode.v │ ├── iscachable.v │ ├── memops.v │ ├── mpyop.v │ ├── pfcache.v │ ├── pffifo.v │ ├── pipefetch.v │ ├── pipemem.v │ ├── prefetch.v │ ├── slowmpy.v │ ├── zipcore.v │ └── zipwb.v ├── ex │ ├── busdelay.v │ ├── fwb_counter.v │ ├── fwb_master.v │ ├── fwb_slave.v │ ├── sfifo.v │ ├── skidbuffer.v │ ├── wbarbiter.v │ ├── wbdblpriarb.v │ └── wbpriarbiter.v ├── peripherals │ ├── README.md │ ├── axilperiphs.v │ ├── icontrol.v │ ├── wbdmac.v │ ├── wbwatchdog.v │ ├── zipcounter.v │ ├── zipjiffies.v │ ├── zipmmu.v │ └── ziptimer.v ├── usage-1-baseline.txt ├── usage-2-verific.txt ├── usage-3-locache.txt ├── usage.pl ├── usage.txt ├── zipaxi.v ├── zipaxil.v ├── zipbones.v ├── zipdma │ ├── zipdma.v │ ├── zipdma_ctrl.v │ ├── zipdma_fsm.v │ ├── zipdma_mm2s.v │ ├── zipdma_rxgears.v │ ├── zipdma_s2mm.v │ └── zipdma_txgears.v └── zipsystem.v ├── sim ├── .gitignore ├── Makefile ├── cpp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── twoc.cpp │ ├── twoc.h │ ├── zipelf.cpp │ ├── zipelf.h │ └── zsim.cpp ├── rtl │ ├── addrdecode.v │ ├── axi2axilite.v │ ├── axi2axilsub.v │ ├── axi_addr.v │ ├── axi_tb.v │ ├── axiempty.v │ ├── axilcon.v │ ├── axilempty.v │ ├── axilite2axi.v │ ├── axilscope.v │ ├── axilxbar.v │ ├── axixbar.v │ ├── demofull.v │ ├── iscachable.v │ ├── memdev.v │ ├── sim_axfiles.txt │ ├── sim_wbfiles.txt │ ├── wb_tb.v │ ├── wbdown.v │ ├── wbscope.v │ ├── wbxbar.v │ └── zipdma_check.v ├── sim_run.pl ├── sim_testcases.txt ├── verilator │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── axilmemsim.cpp │ ├── axilmemsim.h │ ├── byteswap.cpp │ ├── byteswap.h │ ├── div_tb.cpp │ ├── memsim.cpp │ ├── memsim.h │ ├── mkhex.cpp │ ├── mpy_tb.cpp │ ├── pdump.cpp │ ├── pfcache_tb.cpp │ ├── testb.h │ ├── twoc.cpp │ ├── twoc.h │ ├── vbare_tb.cpp │ ├── vversion.sh │ ├── zipaxil_tb.cpp │ ├── zipcpu_tb.cpp │ ├── zipelf.cpp │ ├── zipelf.h │ └── zipmmu_tb.cpp ├── zip-sim.exp └── zipsw │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── board.h │ ├── board.ld │ ├── clkgatechk.c │ ├── cputest.c │ ├── dmatest.c │ ├── hello.c │ ├── hellosim.s │ ├── hellostep.c │ ├── lockcheck.c │ ├── stepchk.c │ ├── txfns.c │ ├── txfns.h │ └── zlib │ ├── Makefile │ ├── README.md │ ├── bootloader.h │ ├── crt0.c │ ├── syscalls.c │ ├── udiv.c │ ├── umod.c │ ├── zipcpu.h │ └── zipsys.h ├── sw ├── .gitignore ├── Makefile ├── README.md ├── binutils-2.27.tar.bz2 ├── gas-script.sh ├── gas-zippatch.patch ├── gcc-script.sh ├── gcc-zippatch.patch ├── nlib-script.sh ├── nlib-zippatch.patch ├── zasm │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── asmdata.cpp │ ├── asmdata.h │ ├── test.S │ ├── twoc.cpp │ ├── twoc.h │ ├── zasm.l │ ├── zasm.y │ ├── zdump.cpp │ ├── zopcodes.cpp │ ├── zopcodes.h │ ├── zparser.cpp │ ├── zparser.h │ └── zpp.l └── zipdbg │ ├── README │ ├── devbus.h │ ├── regdefs.h │ └── zipdbg.cpp └── zip.vim /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/.gitignore -------------------------------------------------------------------------------- /INSTALL.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/INSTALL.md -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/README.md -------------------------------------------------------------------------------- /bench/.gitignore: -------------------------------------------------------------------------------- 1 | /dhrystone/ 2 | -------------------------------------------------------------------------------- /bench/asm/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/.gitignore -------------------------------------------------------------------------------- /bench/asm/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/Makefile -------------------------------------------------------------------------------- /bench/asm/cmptest.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/cmptest.s -------------------------------------------------------------------------------- /bench/asm/hellosim.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/hellosim.s -------------------------------------------------------------------------------- /bench/asm/nstrtest.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/nstrtest.s -------------------------------------------------------------------------------- /bench/asm/simscript.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/simscript.ld -------------------------------------------------------------------------------- /bench/asm/simtest.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/simtest.s -------------------------------------------------------------------------------- /bench/asm/simuart.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/asm/simuart.s -------------------------------------------------------------------------------- /bench/cpp/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/.gitignore -------------------------------------------------------------------------------- /bench/cpp/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/Makefile -------------------------------------------------------------------------------- /bench/cpp/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/README.md -------------------------------------------------------------------------------- /bench/cpp/dcache_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/dcache_tb.cpp -------------------------------------------------------------------------------- /bench/cpp/helloworld.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/helloworld.c -------------------------------------------------------------------------------- /bench/cpp/memsim.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/memsim.cpp -------------------------------------------------------------------------------- /bench/cpp/memsim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/memsim.h -------------------------------------------------------------------------------- /bench/cpp/mpyraw.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/cpp/mpyraw.c -------------------------------------------------------------------------------- /bench/formal/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/.gitignore -------------------------------------------------------------------------------- /bench/formal/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/Makefile -------------------------------------------------------------------------------- /bench/formal/abs_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/abs_div.v -------------------------------------------------------------------------------- /bench/formal/abs_mpy.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/abs_mpy.v -------------------------------------------------------------------------------- /bench/formal/axidcache.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axidcache.gtkw -------------------------------------------------------------------------------- /bench/formal/axidcache.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axidcache.sby -------------------------------------------------------------------------------- /bench/formal/axiicache.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axiicache.gtkw -------------------------------------------------------------------------------- /bench/formal/axiicache.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axiicache.sby -------------------------------------------------------------------------------- /bench/formal/axilfetch.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilfetch.gtkw -------------------------------------------------------------------------------- /bench/formal/axilfetch.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilfetch.sby -------------------------------------------------------------------------------- /bench/formal/axilfetch64.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilfetch64.gtkw -------------------------------------------------------------------------------- /bench/formal/axilops.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilops.gtkw -------------------------------------------------------------------------------- /bench/formal/axilops.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilops.sby -------------------------------------------------------------------------------- /bench/formal/axilperiphs.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilperiphs.sby -------------------------------------------------------------------------------- /bench/formal/axilpipe.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilpipe.gtkw -------------------------------------------------------------------------------- /bench/formal/axilpipe.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axilpipe.sby -------------------------------------------------------------------------------- /bench/formal/axiops.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axiops.gtkw -------------------------------------------------------------------------------- /bench/formal/axiops.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axiops.sby -------------------------------------------------------------------------------- /bench/formal/axipipe.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axipipe.gtkw -------------------------------------------------------------------------------- /bench/formal/axipipe.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/axipipe.sby -------------------------------------------------------------------------------- /bench/formal/busdelay.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/busdelay.gtkw -------------------------------------------------------------------------------- /bench/formal/busdelay.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/busdelay.sby -------------------------------------------------------------------------------- /bench/formal/busdelay.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/busdelay.ys -------------------------------------------------------------------------------- /bench/formal/cpuops.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/cpuops.sby -------------------------------------------------------------------------------- /bench/formal/cpuops.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/cpuops.ys -------------------------------------------------------------------------------- /bench/formal/dblfetch.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dblfetch.gtkw -------------------------------------------------------------------------------- /bench/formal/dblfetch.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dblfetch.sby -------------------------------------------------------------------------------- /bench/formal/dblfetch.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dblfetch.ys -------------------------------------------------------------------------------- /bench/formal/dblfetchlogic.ys: -------------------------------------------------------------------------------- 1 | read_verilog ../../rtl/core/dblfetch.v 2 | synth_ice40 3 | -------------------------------------------------------------------------------- /bench/formal/dcache.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dcache.gtkw -------------------------------------------------------------------------------- /bench/formal/dcache.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dcache.sby -------------------------------------------------------------------------------- /bench/formal/dcache.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/dcache.ys -------------------------------------------------------------------------------- /bench/formal/div.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/div.gtkw -------------------------------------------------------------------------------- /bench/formal/div.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/div.sby -------------------------------------------------------------------------------- /bench/formal/div.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/div.ys -------------------------------------------------------------------------------- /bench/formal/f_idecode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/f_idecode.v -------------------------------------------------------------------------------- /bench/formal/fdebug.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/fdebug.v -------------------------------------------------------------------------------- /bench/formal/fetchlogic.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/fetchlogic.ys -------------------------------------------------------------------------------- /bench/formal/ffetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/ffetch.v -------------------------------------------------------------------------------- /bench/formal/fmem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/fmem.v -------------------------------------------------------------------------------- /bench/formal/genreport.pl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/genreport.pl -------------------------------------------------------------------------------- /bench/formal/icontrol.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/icontrol.gtkw -------------------------------------------------------------------------------- /bench/formal/icontrol.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/icontrol.sby -------------------------------------------------------------------------------- /bench/formal/icontrol.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/icontrol.ys -------------------------------------------------------------------------------- /bench/formal/idecode.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/idecode.gtkw -------------------------------------------------------------------------------- /bench/formal/idecode.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/idecode.sby -------------------------------------------------------------------------------- /bench/formal/memdev.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/memdev.sby -------------------------------------------------------------------------------- /bench/formal/memlogic.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/memlogic.ys -------------------------------------------------------------------------------- /bench/formal/memops.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/memops.gtkw -------------------------------------------------------------------------------- /bench/formal/memops.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/memops.sby -------------------------------------------------------------------------------- /bench/formal/pfcache.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pfcache.gtkw -------------------------------------------------------------------------------- /bench/formal/pfcache.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pfcache.sby -------------------------------------------------------------------------------- /bench/formal/pfcache.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pfcache.ys -------------------------------------------------------------------------------- /bench/formal/pffifo.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pffifo.sby -------------------------------------------------------------------------------- /bench/formal/pipefetch.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pipefetch.sby -------------------------------------------------------------------------------- /bench/formal/pipemem.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pipemem.gtkw -------------------------------------------------------------------------------- /bench/formal/pipemem.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pipemem.sby -------------------------------------------------------------------------------- /bench/formal/pipemem.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/pipemem.ys -------------------------------------------------------------------------------- /bench/formal/prefetch.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/prefetch.gtkw -------------------------------------------------------------------------------- /bench/formal/prefetch.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/prefetch.sby -------------------------------------------------------------------------------- /bench/formal/prefetch.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/prefetch.ys -------------------------------------------------------------------------------- /bench/formal/report.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/report.html -------------------------------------------------------------------------------- /bench/formal/wbdblpriarb.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbdblpriarb.sby -------------------------------------------------------------------------------- /bench/formal/wbdblpriarb.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbdblpriarb.ys -------------------------------------------------------------------------------- /bench/formal/wbdmac.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbdmac.sby -------------------------------------------------------------------------------- /bench/formal/wbdmac.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbdmac.ys -------------------------------------------------------------------------------- /bench/formal/wbpriarbiter.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbpriarbiter.sby -------------------------------------------------------------------------------- /bench/formal/wbpriarbiter.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbpriarbiter.ys -------------------------------------------------------------------------------- /bench/formal/wbwatchdog.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbwatchdog.sby -------------------------------------------------------------------------------- /bench/formal/wbwatchdog.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/wbwatchdog.ys -------------------------------------------------------------------------------- /bench/formal/zipaxi.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipaxi.sby -------------------------------------------------------------------------------- /bench/formal/zipaxil.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipaxil.sby -------------------------------------------------------------------------------- /bench/formal/zipbones.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipbones.gtkw -------------------------------------------------------------------------------- /bench/formal/zipbones.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipbones.sby -------------------------------------------------------------------------------- /bench/formal/zipcore.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcore.gtkw -------------------------------------------------------------------------------- /bench/formal/zipcore.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcore.sby -------------------------------------------------------------------------------- /bench/formal/zipcounter.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcounter.sby -------------------------------------------------------------------------------- /bench/formal/zipcounter.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcounter.ys -------------------------------------------------------------------------------- /bench/formal/zipcpu.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcpu.gtkw -------------------------------------------------------------------------------- /bench/formal/zipcpu.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipcpu.ys -------------------------------------------------------------------------------- /bench/formal/zipdma_mm2s.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_mm2s.gtkw -------------------------------------------------------------------------------- /bench/formal/zipdma_mm2s.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_mm2s.sby -------------------------------------------------------------------------------- /bench/formal/zipdma_rxgears.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_rxgears.gtkw -------------------------------------------------------------------------------- /bench/formal/zipdma_rxgears.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_rxgears.sby -------------------------------------------------------------------------------- /bench/formal/zipdma_s2mm.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_s2mm.gtkw -------------------------------------------------------------------------------- /bench/formal/zipdma_s2mm.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_s2mm.sby -------------------------------------------------------------------------------- /bench/formal/zipdma_txgears.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_txgears.gtkw -------------------------------------------------------------------------------- /bench/formal/zipdma_txgears.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipdma_txgears.sby -------------------------------------------------------------------------------- /bench/formal/zipjiffies.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipjiffies.sby -------------------------------------------------------------------------------- /bench/formal/zipjiffies.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipjiffies.ys -------------------------------------------------------------------------------- /bench/formal/zipmmu.gtkw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipmmu.gtkw -------------------------------------------------------------------------------- /bench/formal/zipmmu.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipmmu.sby -------------------------------------------------------------------------------- /bench/formal/zipmmu.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/zipmmu.ys -------------------------------------------------------------------------------- /bench/formal/ziptimer.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/ziptimer.sby -------------------------------------------------------------------------------- /bench/formal/ziptimer.ys: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/formal/ziptimer.ys -------------------------------------------------------------------------------- /bench/mcy/.gitignore: -------------------------------------------------------------------------------- 1 | ziptimer 2 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/.gitignore -------------------------------------------------------------------------------- /bench/mcy/zipcpu/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/Makefile -------------------------------------------------------------------------------- /bench/mcy/zipcpu/config.mcy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/config.mcy -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_bmc.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/eq_bmc.sby -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_bmc.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/eq_bmc.sh -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_sim3.sby: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/eq_sim3.sby -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_sim3.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/eq_sim3.sh -------------------------------------------------------------------------------- /bench/mcy/zipcpu/miter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/miter.sv -------------------------------------------------------------------------------- /bench/mcy/zipcpu/sim_verilator.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/sim_verilator.sh -------------------------------------------------------------------------------- /bench/mcy/zipcpu/zipbones.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/zipbones.v -------------------------------------------------------------------------------- /bench/mcy/zipcpu/zipcpu.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/mcy/zipcpu/zipcpu.cpp -------------------------------------------------------------------------------- /bench/rtl/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/rtl/Makefile -------------------------------------------------------------------------------- /bench/rtl/memdev.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/rtl/memdev.v -------------------------------------------------------------------------------- /bench/rtl/zipmmu_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/rtl/zipmmu_tb.v -------------------------------------------------------------------------------- /bench/zipsim.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/bench/zipsim.ld -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/.gitignore -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/Makefile -------------------------------------------------------------------------------- /doc/gfx/.gitignore: -------------------------------------------------------------------------------- 1 | Makefile 2 | inkscape-notes.txt 3 | bus-structure.eps 4 | topng.sh 5 | -------------------------------------------------------------------------------- /doc/gfx/20220720-betterdma.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/20220720-betterdma.png -------------------------------------------------------------------------------- /doc/gfx/20220720-dmaregs.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/20220720-dmaregs.png -------------------------------------------------------------------------------- /doc/gfx/20220720-oldlimits.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/20220720-oldlimits.png -------------------------------------------------------------------------------- /doc/gfx/20220720-priordma.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/20220720-priordma.png -------------------------------------------------------------------------------- /doc/gfx/20220720-sgdma.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/20220720-sgdma.png -------------------------------------------------------------------------------- /doc/gfx/axidcache-reads.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axidcache-reads.png -------------------------------------------------------------------------------- /doc/gfx/axiicache.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axiicache.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_dbl.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_dbl.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_dbl64.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_dbl64.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_fifo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_fifo.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_fifo64.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_fifo64.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_raw.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_raw.png -------------------------------------------------------------------------------- /doc/gfx/axilfetch_raw64.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilfetch_raw64.png -------------------------------------------------------------------------------- /doc/gfx/axilpipe-reads.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilpipe-reads.png -------------------------------------------------------------------------------- /doc/gfx/axilpipe-ureads.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/axilpipe-ureads.png -------------------------------------------------------------------------------- /doc/gfx/bc.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bc.eps -------------------------------------------------------------------------------- /doc/gfx/bcmem.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bcmem.eps -------------------------------------------------------------------------------- /doc/gfx/bdbroken.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bdbroken.eps -------------------------------------------------------------------------------- /doc/gfx/bdly.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bdly.eps -------------------------------------------------------------------------------- /doc/gfx/bra.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bra.eps -------------------------------------------------------------------------------- /doc/gfx/bus-structure.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/bus-structure.png -------------------------------------------------------------------------------- /doc/gfx/cpu.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/cpu.eps -------------------------------------------------------------------------------- /doc/gfx/cpu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/cpu.png -------------------------------------------------------------------------------- /doc/gfx/fullpline.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/fullpline.eps -------------------------------------------------------------------------------- /doc/gfx/memrd.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/memrd.eps -------------------------------------------------------------------------------- /doc/gfx/memwr.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/memwr.eps -------------------------------------------------------------------------------- /doc/gfx/mstld.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/mstld.eps -------------------------------------------------------------------------------- /doc/gfx/pfmiss.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/pfmiss.eps -------------------------------------------------------------------------------- /doc/gfx/pfmissn.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/pfmissn.eps -------------------------------------------------------------------------------- /doc/gfx/read-hazard-fixed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/read-hazard-fixed.png -------------------------------------------------------------------------------- /doc/gfx/read-hazard.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/read-hazard.png -------------------------------------------------------------------------------- /doc/gfx/regset.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/regset.eps -------------------------------------------------------------------------------- /doc/gfx/regset.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/regset.png -------------------------------------------------------------------------------- /doc/gfx/sleep.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/sleep.eps -------------------------------------------------------------------------------- /doc/gfx/stacking.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/stacking.eps -------------------------------------------------------------------------------- /doc/gfx/stuttra.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/stuttra.eps -------------------------------------------------------------------------------- /doc/gfx/stuttrb.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/stuttrb.eps -------------------------------------------------------------------------------- /doc/gfx/system.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/system.eps -------------------------------------------------------------------------------- /doc/gfx/system.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/system.png -------------------------------------------------------------------------------- /doc/gfx/zipbones.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/zipbones.eps -------------------------------------------------------------------------------- /doc/gfx/zipbones.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/zipbones.png -------------------------------------------------------------------------------- /doc/gfx/zipdma-blocks.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gfx/zipdma-blocks.png -------------------------------------------------------------------------------- /doc/gpl-3.0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/gpl-3.0.pdf -------------------------------------------------------------------------------- /doc/memsurvey.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/memsurvey.png -------------------------------------------------------------------------------- /doc/nextgen.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/nextgen.html -------------------------------------------------------------------------------- /doc/nextgen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/nextgen.png -------------------------------------------------------------------------------- /doc/orconf.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/orconf.pdf -------------------------------------------------------------------------------- /doc/orconf2017.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/orconf2017.pdf -------------------------------------------------------------------------------- /doc/orconf2018.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/orconf2018.pdf -------------------------------------------------------------------------------- /doc/spec.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/spec.pdf -------------------------------------------------------------------------------- /doc/src/GT.eps: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/src/GT.eps -------------------------------------------------------------------------------- /doc/src/gpl-3.0.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/src/gpl-3.0.tex -------------------------------------------------------------------------------- /doc/src/gqtekspec.cls: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/src/gqtekspec.cls -------------------------------------------------------------------------------- /doc/src/spec.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/src/spec.tex -------------------------------------------------------------------------------- /doc/usage.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/usage.pdf -------------------------------------------------------------------------------- /doc/usage.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/usage.tex -------------------------------------------------------------------------------- /doc/wbspec_b4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/doc/wbspec_b4.pdf -------------------------------------------------------------------------------- /rtl/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/.gitignore -------------------------------------------------------------------------------- /rtl/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/Makefile -------------------------------------------------------------------------------- /rtl/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/README.md -------------------------------------------------------------------------------- /rtl/core/.gitignore: -------------------------------------------------------------------------------- 1 | *.ys 2 | -------------------------------------------------------------------------------- /rtl/core/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/README.md -------------------------------------------------------------------------------- /rtl/core/axidcache.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axidcache.v -------------------------------------------------------------------------------- /rtl/core/axiicache.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axiicache.v -------------------------------------------------------------------------------- /rtl/core/axilfetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axilfetch.v -------------------------------------------------------------------------------- /rtl/core/axilops.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axilops.v -------------------------------------------------------------------------------- /rtl/core/axilpipe.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axilpipe.v -------------------------------------------------------------------------------- /rtl/core/axiops.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axiops.v -------------------------------------------------------------------------------- /rtl/core/axipipe.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/axipipe.v -------------------------------------------------------------------------------- /rtl/core/cpuops.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/cpuops.v -------------------------------------------------------------------------------- /rtl/core/dblfetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/dblfetch.v -------------------------------------------------------------------------------- /rtl/core/dcache.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/dcache.v -------------------------------------------------------------------------------- /rtl/core/div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/div.v -------------------------------------------------------------------------------- /rtl/core/idecode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/idecode.v -------------------------------------------------------------------------------- /rtl/core/iscachable.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/iscachable.v -------------------------------------------------------------------------------- /rtl/core/memops.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/memops.v -------------------------------------------------------------------------------- /rtl/core/mpyop.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/mpyop.v -------------------------------------------------------------------------------- /rtl/core/pfcache.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/pfcache.v -------------------------------------------------------------------------------- /rtl/core/pffifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/pffifo.v -------------------------------------------------------------------------------- /rtl/core/pipefetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/pipefetch.v -------------------------------------------------------------------------------- /rtl/core/pipemem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/pipemem.v -------------------------------------------------------------------------------- /rtl/core/prefetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/prefetch.v -------------------------------------------------------------------------------- /rtl/core/slowmpy.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/slowmpy.v -------------------------------------------------------------------------------- /rtl/core/zipcore.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/zipcore.v -------------------------------------------------------------------------------- /rtl/core/zipwb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/core/zipwb.v -------------------------------------------------------------------------------- /rtl/ex/busdelay.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/busdelay.v -------------------------------------------------------------------------------- /rtl/ex/fwb_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/fwb_counter.v -------------------------------------------------------------------------------- /rtl/ex/fwb_master.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/fwb_master.v -------------------------------------------------------------------------------- /rtl/ex/fwb_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/fwb_slave.v -------------------------------------------------------------------------------- /rtl/ex/sfifo.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/sfifo.v -------------------------------------------------------------------------------- /rtl/ex/skidbuffer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/skidbuffer.v -------------------------------------------------------------------------------- /rtl/ex/wbarbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/wbarbiter.v -------------------------------------------------------------------------------- /rtl/ex/wbdblpriarb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/wbdblpriarb.v -------------------------------------------------------------------------------- /rtl/ex/wbpriarbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/ex/wbpriarbiter.v -------------------------------------------------------------------------------- /rtl/peripherals/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/README.md -------------------------------------------------------------------------------- /rtl/peripherals/axilperiphs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/axilperiphs.v -------------------------------------------------------------------------------- /rtl/peripherals/icontrol.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/icontrol.v -------------------------------------------------------------------------------- /rtl/peripherals/wbdmac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/wbdmac.v -------------------------------------------------------------------------------- /rtl/peripherals/wbwatchdog.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/wbwatchdog.v -------------------------------------------------------------------------------- /rtl/peripherals/zipcounter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/zipcounter.v -------------------------------------------------------------------------------- /rtl/peripherals/zipjiffies.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/zipjiffies.v -------------------------------------------------------------------------------- /rtl/peripherals/zipmmu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/zipmmu.v -------------------------------------------------------------------------------- /rtl/peripherals/ziptimer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/peripherals/ziptimer.v -------------------------------------------------------------------------------- /rtl/usage-1-baseline.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/usage-1-baseline.txt -------------------------------------------------------------------------------- /rtl/usage-2-verific.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/usage-2-verific.txt -------------------------------------------------------------------------------- /rtl/usage-3-locache.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/usage-3-locache.txt -------------------------------------------------------------------------------- /rtl/usage.pl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/usage.pl -------------------------------------------------------------------------------- /rtl/usage.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/usage.txt -------------------------------------------------------------------------------- /rtl/zipaxi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipaxi.v -------------------------------------------------------------------------------- /rtl/zipaxil.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipaxil.v -------------------------------------------------------------------------------- /rtl/zipbones.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipbones.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_ctrl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_ctrl.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_fsm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_fsm.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_mm2s.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_mm2s.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_rxgears.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_rxgears.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_s2mm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_s2mm.v -------------------------------------------------------------------------------- /rtl/zipdma/zipdma_txgears.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipdma/zipdma_txgears.v -------------------------------------------------------------------------------- /rtl/zipsystem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/rtl/zipsystem.v -------------------------------------------------------------------------------- /sim/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/.gitignore -------------------------------------------------------------------------------- /sim/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/Makefile -------------------------------------------------------------------------------- /sim/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | zsim 2 | -------------------------------------------------------------------------------- /sim/cpp/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/Makefile -------------------------------------------------------------------------------- /sim/cpp/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/README.md -------------------------------------------------------------------------------- /sim/cpp/twoc.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/twoc.cpp -------------------------------------------------------------------------------- /sim/cpp/twoc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/twoc.h -------------------------------------------------------------------------------- /sim/cpp/zipelf.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/zipelf.cpp -------------------------------------------------------------------------------- /sim/cpp/zipelf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/zipelf.h -------------------------------------------------------------------------------- /sim/cpp/zsim.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/cpp/zsim.cpp -------------------------------------------------------------------------------- /sim/rtl/addrdecode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/addrdecode.v -------------------------------------------------------------------------------- /sim/rtl/axi2axilite.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axi2axilite.v -------------------------------------------------------------------------------- /sim/rtl/axi2axilsub.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axi2axilsub.v -------------------------------------------------------------------------------- /sim/rtl/axi_addr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axi_addr.v -------------------------------------------------------------------------------- /sim/rtl/axi_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axi_tb.v -------------------------------------------------------------------------------- /sim/rtl/axiempty.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axiempty.v -------------------------------------------------------------------------------- /sim/rtl/axilcon.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axilcon.v -------------------------------------------------------------------------------- /sim/rtl/axilempty.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axilempty.v -------------------------------------------------------------------------------- /sim/rtl/axilite2axi.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axilite2axi.v -------------------------------------------------------------------------------- /sim/rtl/axilscope.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axilscope.v -------------------------------------------------------------------------------- /sim/rtl/axilxbar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axilxbar.v -------------------------------------------------------------------------------- /sim/rtl/axixbar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/axixbar.v -------------------------------------------------------------------------------- /sim/rtl/demofull.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/demofull.v -------------------------------------------------------------------------------- /sim/rtl/iscachable.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/iscachable.v -------------------------------------------------------------------------------- /sim/rtl/memdev.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/memdev.v -------------------------------------------------------------------------------- /sim/rtl/sim_axfiles.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/sim_axfiles.txt -------------------------------------------------------------------------------- /sim/rtl/sim_wbfiles.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/sim_wbfiles.txt -------------------------------------------------------------------------------- /sim/rtl/wb_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/wb_tb.v -------------------------------------------------------------------------------- /sim/rtl/wbdown.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/wbdown.v -------------------------------------------------------------------------------- /sim/rtl/wbscope.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/wbscope.v -------------------------------------------------------------------------------- /sim/rtl/wbxbar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/wbxbar.v -------------------------------------------------------------------------------- /sim/rtl/zipdma_check.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/rtl/zipdma_check.v -------------------------------------------------------------------------------- /sim/sim_run.pl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/sim_run.pl -------------------------------------------------------------------------------- /sim/sim_testcases.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/sim_testcases.txt -------------------------------------------------------------------------------- /sim/verilator/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/.gitignore -------------------------------------------------------------------------------- /sim/verilator/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/Makefile -------------------------------------------------------------------------------- /sim/verilator/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/README.md -------------------------------------------------------------------------------- /sim/verilator/axilmemsim.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/axilmemsim.cpp -------------------------------------------------------------------------------- /sim/verilator/axilmemsim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/axilmemsim.h -------------------------------------------------------------------------------- /sim/verilator/byteswap.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/byteswap.cpp -------------------------------------------------------------------------------- /sim/verilator/byteswap.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/byteswap.h -------------------------------------------------------------------------------- /sim/verilator/div_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/div_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/memsim.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/memsim.cpp -------------------------------------------------------------------------------- /sim/verilator/memsim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/memsim.h -------------------------------------------------------------------------------- /sim/verilator/mkhex.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/mkhex.cpp -------------------------------------------------------------------------------- /sim/verilator/mpy_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/mpy_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/pdump.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/pdump.cpp -------------------------------------------------------------------------------- /sim/verilator/pfcache_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/pfcache_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/testb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/testb.h -------------------------------------------------------------------------------- /sim/verilator/twoc.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/twoc.cpp -------------------------------------------------------------------------------- /sim/verilator/twoc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/twoc.h -------------------------------------------------------------------------------- /sim/verilator/vbare_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/vbare_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/vversion.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/vversion.sh -------------------------------------------------------------------------------- /sim/verilator/zipaxil_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/zipaxil_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/zipcpu_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/zipcpu_tb.cpp -------------------------------------------------------------------------------- /sim/verilator/zipelf.cpp: -------------------------------------------------------------------------------- 1 | ../cpp/zipelf.cpp -------------------------------------------------------------------------------- /sim/verilator/zipelf.h: -------------------------------------------------------------------------------- 1 | ../cpp/zipelf.h -------------------------------------------------------------------------------- /sim/verilator/zipmmu_tb.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/verilator/zipmmu_tb.cpp -------------------------------------------------------------------------------- /sim/zip-sim.exp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zip-sim.exp -------------------------------------------------------------------------------- /sim/zipsw/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/.gitignore -------------------------------------------------------------------------------- /sim/zipsw/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/Makefile -------------------------------------------------------------------------------- /sim/zipsw/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/README.md -------------------------------------------------------------------------------- /sim/zipsw/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/board.h -------------------------------------------------------------------------------- /sim/zipsw/board.ld: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/board.ld -------------------------------------------------------------------------------- /sim/zipsw/clkgatechk.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/clkgatechk.c -------------------------------------------------------------------------------- /sim/zipsw/cputest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/cputest.c -------------------------------------------------------------------------------- /sim/zipsw/dmatest.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/dmatest.c -------------------------------------------------------------------------------- /sim/zipsw/hello.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/hello.c -------------------------------------------------------------------------------- /sim/zipsw/hellosim.s: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/hellosim.s -------------------------------------------------------------------------------- /sim/zipsw/hellostep.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/hellostep.c -------------------------------------------------------------------------------- /sim/zipsw/lockcheck.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/lockcheck.c -------------------------------------------------------------------------------- /sim/zipsw/stepchk.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/stepchk.c -------------------------------------------------------------------------------- /sim/zipsw/txfns.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/txfns.c -------------------------------------------------------------------------------- /sim/zipsw/txfns.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/txfns.h -------------------------------------------------------------------------------- /sim/zipsw/zlib/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/Makefile -------------------------------------------------------------------------------- /sim/zipsw/zlib/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/README.md -------------------------------------------------------------------------------- /sim/zipsw/zlib/bootloader.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/bootloader.h -------------------------------------------------------------------------------- /sim/zipsw/zlib/crt0.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/crt0.c -------------------------------------------------------------------------------- /sim/zipsw/zlib/syscalls.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/syscalls.c -------------------------------------------------------------------------------- /sim/zipsw/zlib/udiv.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/udiv.c -------------------------------------------------------------------------------- /sim/zipsw/zlib/umod.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/umod.c -------------------------------------------------------------------------------- /sim/zipsw/zlib/zipcpu.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/zipcpu.h -------------------------------------------------------------------------------- /sim/zipsw/zlib/zipsys.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sim/zipsw/zlib/zipsys.h -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/.gitignore -------------------------------------------------------------------------------- /sw/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/Makefile -------------------------------------------------------------------------------- /sw/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/README.md -------------------------------------------------------------------------------- /sw/binutils-2.27.tar.bz2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/binutils-2.27.tar.bz2 -------------------------------------------------------------------------------- /sw/gas-script.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/gas-script.sh -------------------------------------------------------------------------------- /sw/gas-zippatch.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/gas-zippatch.patch -------------------------------------------------------------------------------- /sw/gcc-script.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/gcc-script.sh -------------------------------------------------------------------------------- /sw/gcc-zippatch.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/gcc-zippatch.patch -------------------------------------------------------------------------------- /sw/nlib-script.sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/nlib-script.sh -------------------------------------------------------------------------------- /sw/nlib-zippatch.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/nlib-zippatch.patch -------------------------------------------------------------------------------- /sw/zasm/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/.gitignore -------------------------------------------------------------------------------- /sw/zasm/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/Makefile -------------------------------------------------------------------------------- /sw/zasm/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/README.md -------------------------------------------------------------------------------- /sw/zasm/asmdata.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/asmdata.cpp -------------------------------------------------------------------------------- /sw/zasm/asmdata.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/asmdata.h -------------------------------------------------------------------------------- /sw/zasm/test.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/test.S -------------------------------------------------------------------------------- /sw/zasm/twoc.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/twoc.cpp -------------------------------------------------------------------------------- /sw/zasm/twoc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/twoc.h -------------------------------------------------------------------------------- /sw/zasm/zasm.l: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zasm.l -------------------------------------------------------------------------------- /sw/zasm/zasm.y: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zasm.y -------------------------------------------------------------------------------- /sw/zasm/zdump.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zdump.cpp -------------------------------------------------------------------------------- /sw/zasm/zopcodes.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zopcodes.cpp -------------------------------------------------------------------------------- /sw/zasm/zopcodes.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zopcodes.h -------------------------------------------------------------------------------- /sw/zasm/zparser.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zparser.cpp -------------------------------------------------------------------------------- /sw/zasm/zparser.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zparser.h -------------------------------------------------------------------------------- /sw/zasm/zpp.l: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zasm/zpp.l -------------------------------------------------------------------------------- /sw/zipdbg/README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zipdbg/README -------------------------------------------------------------------------------- /sw/zipdbg/devbus.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zipdbg/devbus.h -------------------------------------------------------------------------------- /sw/zipdbg/regdefs.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zipdbg/regdefs.h -------------------------------------------------------------------------------- /sw/zipdbg/zipdbg.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/sw/zipdbg/zipdbg.cpp -------------------------------------------------------------------------------- /zip.vim: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/HEAD/zip.vim --------------------------------------------------------------------------------