├── .gitignore ├── INSTALL.md ├── Makefile ├── README.md ├── bench ├── asm │ ├── .gitignore │ ├── Makefile │ ├── cmptest.s │ ├── hellosim.s │ ├── nstrtest.s │ ├── simscript.ld │ ├── simtest.s │ └── simuart.s ├── cpp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── dcache_tb.cpp │ ├── helloworld.c │ ├── memsim.cpp │ ├── memsim.h │ └── mpyraw.c ├── formal │ ├── .gitignore │ ├── Makefile │ ├── abs_div.v │ ├── abs_mpy.v │ ├── axidcache.gtkw │ ├── axidcache.sby │ ├── axiicache.gtkw │ ├── axiicache.sby │ ├── axilfetch.gtkw │ ├── axilfetch.sby │ ├── axilfetch64.gtkw │ ├── axilops.gtkw │ ├── axilops.sby │ ├── axilperiphs.sby │ ├── axilpipe.gtkw │ ├── axilpipe.sby │ ├── axiops.gtkw │ ├── axiops.sby │ ├── axipipe.gtkw │ ├── axipipe.sby │ ├── busdelay.gtkw │ ├── busdelay.sby │ ├── busdelay.ys │ ├── cpuops.sby │ ├── cpuops.ys │ ├── dblfetch.gtkw │ ├── dblfetch.sby │ ├── dblfetch.ys │ ├── dblfetchlogic.ys │ ├── dcache.gtkw │ ├── dcache.sby │ ├── dcache.ys │ ├── div.gtkw │ ├── div.sby │ ├── div.ys │ ├── f_idecode.v │ ├── fdebug.v │ ├── fetchlogic.ys │ ├── ffetch.v │ ├── fmem.v │ ├── genreport.pl │ ├── icontrol.gtkw │ ├── icontrol.sby │ ├── icontrol.ys │ ├── idecode.gtkw │ ├── idecode.sby │ ├── memdev.sby │ ├── memlogic.ys │ ├── memops.gtkw │ ├── memops.sby │ ├── pfcache.gtkw │ ├── pfcache.sby │ ├── pfcache.ys │ ├── pffifo.sby │ ├── pipefetch.sby │ ├── pipemem.gtkw │ ├── pipemem.sby │ ├── pipemem.ys │ ├── prefetch.gtkw │ ├── prefetch.sby │ ├── prefetch.ys │ ├── report.html │ ├── wbdblpriarb.sby │ ├── wbdblpriarb.ys │ ├── wbdmac.sby │ ├── wbdmac.ys │ ├── wbpriarbiter.sby │ ├── wbpriarbiter.ys │ ├── wbwatchdog.sby │ ├── wbwatchdog.ys │ ├── zipaxi.sby │ ├── zipaxil.sby │ ├── zipbones.gtkw │ ├── zipbones.sby │ ├── zipcore.gtkw │ ├── zipcore.sby │ ├── zipcounter.sby │ ├── zipcounter.ys │ ├── zipcpu.gtkw │ ├── zipcpu.ys │ ├── zipdma_mm2s.gtkw │ ├── zipdma_mm2s.sby │ ├── zipdma_rxgears.gtkw │ ├── zipdma_rxgears.sby │ ├── zipdma_s2mm.gtkw │ ├── zipdma_s2mm.sby │ ├── zipdma_txgears.gtkw │ ├── zipdma_txgears.sby │ ├── zipjiffies.sby │ ├── zipjiffies.ys │ ├── zipmmu.gtkw │ ├── zipmmu.sby │ ├── zipmmu.ys │ ├── ziptimer.sby │ └── ziptimer.ys ├── mcy │ ├── .gitignore │ └── zipcpu │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── config.mcy │ │ ├── eq_bmc.sby │ │ ├── eq_bmc.sh │ │ ├── eq_sim3.sby │ │ ├── eq_sim3.sh │ │ ├── miter.sv │ │ ├── sim_verilator.sh │ │ ├── zipbones.v │ │ └── zipcpu.cpp ├── rtl │ ├── Makefile │ ├── memdev.v │ └── zipmmu_tb.v └── zipsim.ld ├── doc ├── .gitignore ├── Makefile ├── gfx │ ├── .gitignore │ ├── 20220720-betterdma.png │ ├── 20220720-dmaregs.png │ ├── 20220720-oldlimits.png │ ├── 20220720-priordma.png │ ├── 20220720-sgdma.png │ ├── axidcache-reads.png │ ├── axiicache.png │ ├── axilfetch_dbl.png │ ├── axilfetch_dbl64.png │ ├── axilfetch_fifo.png │ ├── axilfetch_fifo64.png │ ├── axilfetch_raw.png │ ├── axilfetch_raw64.png │ ├── axilpipe-reads.png │ ├── axilpipe-ureads.png │ ├── bc.eps │ ├── bcmem.eps │ ├── bdbroken.eps │ ├── bdly.eps │ ├── bra.eps │ ├── bus-structure.png │ ├── cpu.eps │ ├── cpu.png │ ├── fullpline.eps │ ├── memrd.eps │ ├── memwr.eps │ ├── mstld.eps │ ├── pfmiss.eps │ ├── pfmissn.eps │ ├── read-hazard-fixed.png │ ├── read-hazard.png │ ├── regset.eps │ ├── regset.png │ ├── sleep.eps │ ├── stacking.eps │ ├── stuttra.eps │ ├── stuttrb.eps │ ├── system.eps │ ├── system.png │ ├── zipbones.eps │ ├── zipbones.png │ └── zipdma-blocks.png ├── gpl-3.0.pdf ├── memsurvey.png ├── nextgen.html ├── nextgen.png ├── orconf.pdf ├── orconf2017.pdf ├── orconf2018.pdf ├── spec.pdf ├── src │ ├── GT.eps │ ├── gpl-3.0.tex │ ├── gqtekspec.cls │ └── spec.tex ├── usage.pdf ├── usage.tex └── wbspec_b4.pdf ├── rtl ├── .gitignore ├── Makefile ├── README.md ├── core │ ├── .gitignore │ ├── README.md │ ├── axidcache.v │ ├── axiicache.v │ ├── axilfetch.v │ ├── axilops.v │ ├── axilpipe.v │ ├── axiops.v │ ├── axipipe.v │ ├── cpuops.v │ ├── dblfetch.v │ ├── dcache.v │ ├── div.v │ ├── idecode.v │ ├── iscachable.v │ ├── memops.v │ ├── mpyop.v │ ├── pfcache.v │ ├── pffifo.v │ ├── pipefetch.v │ ├── pipemem.v │ ├── prefetch.v │ ├── slowmpy.v │ ├── zipcore.v │ └── zipwb.v ├── ex │ ├── busdelay.v │ ├── fwb_counter.v │ ├── fwb_master.v │ ├── fwb_slave.v │ ├── sfifo.v │ ├── skidbuffer.v │ ├── wbarbiter.v │ ├── wbdblpriarb.v │ └── wbpriarbiter.v ├── peripherals │ ├── README.md │ ├── axilperiphs.v │ ├── icontrol.v │ ├── wbdmac.v │ ├── wbwatchdog.v │ ├── zipcounter.v │ ├── zipjiffies.v │ ├── zipmmu.v │ └── ziptimer.v ├── usage-1-baseline.txt ├── usage-2-verific.txt ├── usage-3-locache.txt ├── usage.pl ├── usage.txt ├── zipaxi.v ├── zipaxil.v ├── zipbones.v ├── zipdma │ ├── zipdma.v │ ├── zipdma_ctrl.v │ ├── zipdma_fsm.v │ ├── zipdma_mm2s.v │ ├── zipdma_rxgears.v │ ├── zipdma_s2mm.v │ └── zipdma_txgears.v └── zipsystem.v ├── sim ├── .gitignore ├── Makefile ├── cpp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── twoc.cpp │ ├── twoc.h │ ├── zipelf.cpp │ ├── zipelf.h │ └── zsim.cpp ├── rtl │ ├── addrdecode.v │ ├── axi2axilite.v │ ├── axi2axilsub.v │ ├── axi_addr.v │ ├── axi_tb.v │ ├── axiempty.v │ ├── axilcon.v │ ├── axilempty.v │ ├── axilite2axi.v │ ├── axilscope.v │ ├── axilxbar.v │ ├── axixbar.v │ ├── demofull.v │ ├── iscachable.v │ ├── memdev.v │ ├── sim_axfiles.txt │ ├── sim_wbfiles.txt │ ├── wb_tb.v │ ├── wbdown.v │ ├── wbscope.v │ ├── wbxbar.v │ └── zipdma_check.v ├── sim_run.pl ├── sim_testcases.txt ├── verilator │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── axilmemsim.cpp │ ├── axilmemsim.h │ ├── byteswap.cpp │ ├── byteswap.h │ ├── div_tb.cpp │ ├── memsim.cpp │ ├── memsim.h │ ├── mkhex.cpp │ ├── mpy_tb.cpp │ ├── pdump.cpp │ ├── pfcache_tb.cpp │ ├── testb.h │ ├── twoc.cpp │ ├── twoc.h │ ├── vbare_tb.cpp │ ├── vversion.sh │ ├── zipaxil_tb.cpp │ ├── zipcpu_tb.cpp │ ├── zipelf.cpp │ ├── zipelf.h │ └── zipmmu_tb.cpp ├── zip-sim.exp └── zipsw │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── board.h │ ├── board.ld │ ├── clkgatechk.c │ ├── cputest.c │ ├── dmatest.c │ ├── hello.c │ ├── hellosim.s │ ├── hellostep.c │ ├── lockcheck.c │ ├── stepchk.c │ ├── txfns.c │ ├── txfns.h │ └── zlib │ ├── Makefile │ ├── README.md │ ├── bootloader.h │ ├── crt0.c │ ├── syscalls.c │ ├── udiv.c │ ├── umod.c │ ├── zipcpu.h │ └── zipsys.h ├── sw ├── .gitignore ├── Makefile ├── README.md ├── binutils-2.27.tar.bz2 ├── gas-script.sh ├── gas-zippatch.patch ├── gcc-script.sh ├── gcc-zippatch.patch ├── nlib-script.sh ├── nlib-zippatch.patch ├── zasm │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── asmdata.cpp │ ├── asmdata.h │ ├── test.S │ ├── twoc.cpp │ ├── twoc.h │ ├── zasm.l │ ├── zasm.y │ ├── zdump.cpp │ ├── zopcodes.cpp │ ├── zopcodes.h │ ├── zparser.cpp │ ├── zparser.h │ └── zpp.l └── zipdbg │ ├── README │ ├── devbus.h │ ├── regdefs.h │ └── zipdbg.cpp └── zip.vim /.gitignore: -------------------------------------------------------------------------------- 1 | legal.txt 2 | .svn 3 | xilinx 4 | obj_dir 5 | obj-pc 6 | obj-zip 7 | a.out 8 | *.o 9 | *.a 10 | *.vcd 11 | .swp 12 | .*.swp 13 | .*.swo 14 | svn-commit* 15 | *_tb 16 | *_tb.dbl 17 | *dbg.txt 18 | *dump.txt 19 | *debug.txt 20 | stmp 21 | tags 22 | cpudefs.h 23 | legal.txt 24 | build-gas 25 | build-gcc 26 | install 27 | binutils-2.25 28 | gcc-5.3.0-zip 29 | gcc-6.2.0-zip 30 | bitrev.v 31 | flashcache.v 32 | oldtimer.v 33 | popcount.v 34 | wbcordic.v 35 | zipport.v 36 | ziptrap.v 37 | genzipops 38 | doc/gfx/*.dia 39 | doc/gfx/*.json 40 | doc/gfx/*.svg 41 | coverage.dat 42 | coverage_lcov.dat 43 | verilated_cov_2_lcov.py 44 | coverage.lcov.dat 45 | annotated/ 46 | -------------------------------------------------------------------------------- /INSTALL.md: -------------------------------------------------------------------------------- 1 | # Welcome to the ZipCPU! 2 | ## Installation instructions 3 | 4 | The ZipCPU repository contains a couple of very basic cabilities, some very necessary to any user, some only necessary to the hard core users, some not so much. 5 | 6 | - It contains the [binutils](sw/binutils-2.27-zip) and [GCC compiler with ZipCPU backend](sw/gcc-6.2.0-zip) used by all implementations of the ZipCPU. *This is very necessary.* 7 | 8 | - It contains a copy of [newlib](sw/newlib-2.5.0-zip). However, the [libgloss](sw/newlib-2.5.0-zip/libgloss/zip) directory within it is specific to the ZBasic architecture. Right now, the answer is to roll your own libgloss for any new architecture. 9 | 10 | - It contains a [specification document](doc/spec.pdf), describing the CPU and its instruction set, together with the sources files to build that specification. This is different from a user's guide, or a specification document for your particular board implementation. (The ZipCPU is *very* generic, allowing you to build your bus and place items within it at any address of your choosing.) 11 | 12 | - It contains a copy of the Verilog RTL describing the ZipCPU. This is useful should you ever wish to build your own project using the ZipCPU. However, if you are just trying to use an existing SoC implementation, you can safely ignore this directory. 13 | 14 | - It contains two simulators: [one](sim/cpp) independent of the RTL, the [second](sim/verilator) based upon the RTL. Neither of these simulators is as good as a proper simulator of a SoC, but they remain here for ... whatever reasons. 15 | 16 | - It contains my first attempt at building an Assembler. Well, it does until I eventually remove it from the repository as unnecessary ... 17 | 18 | - It also contains the source code for an example assembly level [debugger](sw/zipdbg). This will probably be replaced in time with an implementation of gdb, but it remains for the time being. 19 | 20 | ## Dependencies 21 | 22 | Prior to building within the ZipCPU repository directory, you will need to make certain you have a number of prerequisites. These include: texinfo, gcc-dev, g++, flex, bison, libbison-dev, verilator (v5.007 or later, installled from source), libgmp10, libgmp-dev, libmpfr-dev, libmpc-dev, libelf-dev, bc, exuberant-ctags, and libncurses-dev. 23 | 24 | These dependencies can be installed using: 25 | 26 | > sudo apt install texinfo gcc-dev g++ flex bison libbison-dev verilator libgmp10 libgmp-dev libmpfr-dev libmpc-dev libelf-dev bc exuberant-ctags libncurses-dev python3 autoconf help2man 27 | > git clone https://github.com/verilator/verilator 28 | > cd verilator 29 | > autoconf ; ./configure; make ; sudo make install 30 | 31 | ## Installation instructions 32 | To build all of the above, type _make_ in the main repository directory. This will build the tools and place them into a [local install directory](sw/install/cross-tools/bin). Sadly, this process will currently fail about halfway through. To get past this, add the [install directory](sw/install/cross-tools/bin) to your path and restart. _make_ will then pick up where it left off and finish the task. 33 | 34 | The ZipCPU build process does not yet install anything into your local system. All of the tools generated (currently) will be left in the local [install directory](sw/install). 35 | -------------------------------------------------------------------------------- /bench/asm/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.txt 3 | *.dmp 4 | z.out 5 | 6 | asmtest 7 | cmptest 8 | hellosim 9 | simtest 10 | simuart 11 | 12 | asmtest.s 13 | asmtest.S 14 | cachetest.S 15 | cputest.c 16 | haltbusy.S 17 | halttest.S 18 | hellosim.s 19 | helloworld.S 20 | itest.c 21 | itest.s 22 | itst.S 23 | ivec.S 24 | jmpfir.S 25 | lfsr.S 26 | lodsto.S 27 | nullpc.s 28 | pcpc.S 29 | poptest.s 30 | quiktest.S 31 | rtuhalt.S 32 | stack.S 33 | sys.i 34 | testdiv.S 35 | test.sh 36 | tst.c 37 | tst.S 38 | wdt.S 39 | zipdhry.S 40 | zipsys.h 41 | -------------------------------------------------------------------------------- /bench/asm/cmptest.s: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; Filename: cmptest.s 4 | ;; {{{ 5 | ;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ;; 7 | ;; Purpose: To test how the CPU handles comparisons near the CPUs limits. 8 | ;; 9 | ;; 10 | ;; Creator: Dan Gisselquist, Ph.D. 11 | ;; Gisselquist Technology, LLC 12 | ;; 13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 14 | ;; }}} 15 | ;; Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | ;; {{{ 17 | ;; This program is free software (firmware): you can redistribute it and/or 18 | ;; modify it under the terms of the GNU General Public License as published 19 | ;; by the Free Software Foundation, either version 3 of the License, or (at 20 | ;; your option) any later version. 21 | ;; 22 | ;; This program is distributed in the hope that it will be useful, but WITHOUT 23 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | ;; for more details. 26 | ;; 27 | ;; You should have received a copy of the GNU General Public License along 28 | ;; with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | ;; target there if the PDF file isn't present.) If not, see 30 | ;; for a copy. 31 | ;; }}} 32 | ;; License: GPL, v3, as defined and found on www.gnu.org, 33 | ;; {{{ 34 | ;; http://www.gnu.org/licenses/gpl.html 35 | ;; 36 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 37 | ;; 38 | ;; }}} 39 | .section .start,"ax" 40 | .global _start 41 | _start: 42 | NOUT 'E' 43 | NOUT 'n' 44 | NOUT 't' 45 | NOUT 'r' 46 | NOUT 'y' 47 | NOUT '\r' 48 | NOUT '\n' 49 | LDI _top_of_stack,R0 50 | MOV R0,uSP 51 | LDI user_task,R0 52 | MOV R0,uPC 53 | RTU 54 | CMP 0,R0 55 | BNZ _test_failure 56 | NOUT 'P' 57 | NOUT 'A' 58 | NOUT 'S' 59 | NOUT 'S' 60 | NOUT '!' 61 | NOUT '\r' 62 | NOUT '\n' 63 | NEXIT 0 64 | HALT 65 | _test_failure: 66 | NOUT 'F' 67 | NOUT 'A' 68 | NOUT 'I' 69 | NOUT 'L' 70 | NOUT '\r' 71 | NOUT '\n' 72 | NEXIT -1 73 | HALT 74 | 75 | user_task: 76 | NOUT 'U' 77 | NOUT 's' 78 | NOUT 'e' 79 | NOUT 'r' 80 | NOUT '\r' 81 | NOUT '\n' 82 | ; Clear our registers, so we start out with a clean slate 83 | LDI 0x0fff,R0 84 | LDI 0x0fff,R1 85 | LDI 0x0fff,R2 86 | LDI 0x0fff,R3 87 | LDI 0x0fff,R4 88 | LDI 0x0fff,R5 89 | LDI 0x0fff,R6 90 | LDI 0x0fff,R7 91 | LDI 0x0fff,R8 92 | LDI 0x0fff,R9 93 | LDI 0x0fff,R10 94 | LDI 0x0fff,R11 95 | LDI 0x0fff,R12 96 | CLR R0 97 | CLR R1 98 | CLR R2 99 | CLR R3 100 | CLR R4 101 | CLR R5 102 | CLR R6 103 | CLR R7 104 | CLR R8 105 | CLR R9 106 | CLR R10 107 | CLR R11 108 | CLR R12 109 | JSR test_function 110 | ; On return, return back to user mode 111 | TRAP 112 | 113 | test_function: 114 | NOUT 'T' 115 | NOUT 'e' 116 | NOUT 's' 117 | NOUT 't' 118 | NOUT '\r' 119 | NOUT '\n' 120 | LDI 0x7fffffff,R1 121 | LDI 0x80000000,R2 122 | CMP R2,R1 123 | MOV CC,R3 124 | AND 0x0f,R3 125 | NDUMP R3 126 | RETN 127 | -------------------------------------------------------------------------------- /bench/asm/hellosim.s: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; Filename: hellosim.s 4 | ;; {{{ 5 | ;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ;; 7 | ;; Purpose: Hello World, only using the SIM instructions, as an initial 8 | ;; test of whether or not the special SIM instructions even work. 9 | ;; 10 | ;; 11 | ;; Creator: Dan Gisselquist, Ph.D. 12 | ;; Gisselquist Technology, LLC 13 | ;; 14 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 15 | ;; }}} 16 | ;; Copyright (C) 2017-2024, Gisselquist Technology, LLC 17 | ;; {{{ 18 | ;; This program is free software (firmware): you can redistribute it and/or 19 | ;; modify it under the terms of the GNU General Public License as published 20 | ;; by the Free Software Foundation, either version 3 of the License, or (at 21 | ;; your option) any later version. 22 | ;; 23 | ;; This program is distributed in the hope that it will be useful, but WITHOUT 24 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | ;; for more details. 27 | ;; }}} 28 | ;; License: GPL, v3, as defined and found on www.gnu.org, 29 | ;; {{{ 30 | ;; http://www.gnu.org/licenses/gpl.html 31 | ;; 32 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 33 | ;; 34 | ;; }}} 35 | .section .start, "ax" 36 | .global _start 37 | _start: 38 | SOUT 'H' 39 | SOUT 'e' 40 | SOUT 'l' 41 | SOUT 'l' 42 | SOUT 'o' 43 | SOUT ' ' 44 | SOUT 'W' 45 | SOUT 'o' 46 | SOUT 'r' 47 | SOUT 'l' 48 | SOUT 'd' 49 | SOUT '!' 50 | SOUT '\r' 51 | SOUT '\n' 52 | SEXIT 0 53 | ;; And in case someone tries to run this on a *real* ZipCPU, as 54 | ;; opposed to just the simulator, we'll just halt here. 55 | HALT 56 | -------------------------------------------------------------------------------- /bench/asm/nstrtest.s: -------------------------------------------------------------------------------- 1 | NSTR "Hello, World!\r\n" 2 | NEXIT 0 3 | SSTR "Hello, World!\r\n" 4 | SEXIT 0 5 | NSTR "Special characters include \',\",\t,\f,\a,\b\r\n" 6 | NEXIT 0 7 | -------------------------------------------------------------------------------- /bench/asm/simscript.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Filename: simscript.ld 4 | * {{{ 5 | * Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | * 7 | * Purpose: This script provides a description of the memory found within 8 | * the ZipCPU simulator, zippy_tb, for the purposes of where to 9 | * place text and data sections when linking. 10 | * 11 | * Creator: Dan Gisselquist, Ph.D. 12 | * Gisselquist Technology, LLC 13 | * 14 | ******************************************************************************** 15 | * }}} 16 | * Copyright (C) 2016-2024, Gisselquist Technology, LLC 17 | * {{{ 18 | * This program is free software (firmware): you can redistribute it and/or 19 | * modify it under the terms of the GNU General Public License as published 20 | * by the Free Software Foundation, either version 3 of the License, or (at 21 | * your option) any later version. 22 | * 23 | * This program is distributed in the hope that it will be useful, but WITHOUT 24 | * ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | * for more details. 27 | * }}} 28 | * License: GPL, v3, as defined and found on www.gnu.org, 29 | * {{{ 30 | * http://www.gnu.org/licenses/gpl.html 31 | * 32 | * }}} 33 | *******************************************************************************/ 34 | 35 | ENTRY(_start) 36 | 37 | MEMORY 38 | { 39 | ram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000000 40 | } 41 | 42 | _top_of_stack = ORIGIN(ram) + LENGTH(ram); 43 | 44 | SECTIONS 45 | { 46 | .everything ORIGIN(ram) : ALIGN(4) { 47 | *(.start) *(.text) *(.rodata) *(.strings) 48 | *(.fixdata) *(.data) *(COMMON) *(.bss) 49 | } > ram 50 | _top_of_heap = .; 51 | } 52 | -------------------------------------------------------------------------------- /bench/asm/simuart.s: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; Filename: simuart.s 4 | ;; {{{ 5 | ;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ;; 7 | ;; Purpose: 8 | ;; 9 | ;; 10 | ;; Creator: Dan Gisselquist, Ph.D. 11 | ;; Gisselquist Technology, LLC 12 | ;; 13 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 14 | ;; }}} 15 | ;; Copyright (C) 2015-2024, Gisselquist Technology, LLC 16 | ;; {{{ 17 | ;; This program is free software (firmware): you can redistribute it and/or 18 | ;; modify it under the terms of the GNU General Public License as published 19 | ;; by the Free Software Foundation, either version 3 of the License, or (at 20 | ;; your option) any later version. 21 | ;; 22 | ;; This program is distributed in the hope that it will be useful, but WITHOUT 23 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | ;; for more details. 26 | ;; }}} 27 | ;; License: GPL, v3, as defined and found on www.gnu.org, 28 | ;; {{{ 29 | ;; http://www.gnu.org/licenses/gpl.html 30 | ;; 31 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 32 | ;; 33 | ;; }}} 34 | .section .start,"ax",@progbits 35 | .global _start 36 | .equ uart, 0x150 37 | _start: 38 | ldi string,r2 39 | ldi uart,r3 40 | 41 | next_char: 42 | LB (r2),R4 43 | TST R4 44 | BZ all_done 45 | keep_waiting: 46 | LW 12(r3),R5 47 | TST 1,R5 48 | BNZ keep_waiting 49 | SW r4,12(r3) 50 | ADD 1,r2 51 | BRA next_char 52 | 53 | all_done: 54 | SEXIT 0 55 | HALT 56 | string: 57 | .string "Hello, World!\r\n" 58 | -------------------------------------------------------------------------------- /bench/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | div_tb 2 | mpy_tb 3 | pdump 4 | pdump.txt 5 | pfile.bin 6 | zipmmu_tb 7 | zipmmu_tb.vcd 8 | zippy_tb 9 | -------------------------------------------------------------------------------- /bench/cpp/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: bench/cpp/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: To direct and simplify the build of a variety of simple test 8 | ## programs which will use one (or both) of the ZipCPU simulators. 9 | ## 10 | ## Targets include: 11 | ## 12 | ## helloworld 13 | ## 14 | ## 15 | ## 16 | ## Creator: Dan Gisselquist, Ph.D. 17 | ## Gisselquist Technology, LLC 18 | ## 19 | ################################################################################ 20 | ## }}} 21 | ## Copyright (C) 2017-2025, Gisselquist Technology, LLC 22 | ## {{{ 23 | ## This program is free software (firmware): you can redistribute it and/or 24 | ## modify it under the terms of the GNU General Public License as published 25 | ## by the Free Software Foundation, either version 3 of the License, or (at 26 | ## your option) any later version. 27 | ## 28 | ## This program is distributed in the hope that it will be useful, but WITHOUT 29 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 30 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 31 | ## for more details. 32 | ## 33 | ## You should have received a copy of the GNU General Public License along 34 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 35 | ## target there if the PDF file isn't present.) If not, see 36 | ## for a copy. 37 | ## }}} 38 | ## License: GPL, v3, as defined and found on www.gnu.org, 39 | ## {{{ 40 | ## http://www.gnu.org/licenses/gpl.html 41 | ## 42 | ################################################################################ 43 | ## 44 | ## }}} 45 | .PHONY: all 46 | all: helloworld 47 | 48 | CC := zip-gcc 49 | OBJDUMP := zip-objdump 50 | OBJDIR := obj-zip 51 | CFLAGS := -O3 52 | LIBD := ../../sw/install/cross-tools/zip/lib 53 | LIBS := -L$(LIBD) -lzipbasic 54 | SOURCES:= helloworld.c 55 | LDSCRIPT:= ../zipsim.ld 56 | 57 | $(OBJDIR)/%.o: %.c 58 | $(CC) $(CFLAGS) -c $< -o $@ 59 | 60 | helloworld: $(OBJDIR)/helloworld.o 61 | $(CC) -T $(LDSCRIPT) $(CFLAGS) $(LIBD)/crt0.o $(LIBS) $< -o $@ 62 | 63 | helloworld.txt: helloworld 64 | $(OBJDUMP) -dr $< > $@ 65 | 66 | define build-depends 67 | $(CC) $(CFLAGS) -MM $(SOURCES) > $(OBJDIR)/xdepends.txt 68 | sed -e 's/^.*.o: /$(OBJDIR)\/&/' < $(OBJDIR)/xdepends.txt > $(OBJDIR)/depends.txt 69 | @rm -f $(OBJDIR)/xdepends.txt 70 | endef 71 | 72 | tags: $(SOURCES) 73 | @ctags $(SOURCES) 74 | 75 | .PHONY: depends 76 | depends: $(OBJDIR)/ 77 | $(build-depends) 78 | 79 | $(OBJDIR)/: 80 | @bash -c "if [[ ! -e $(OBJDIR) ]]; then mkdir -p $(OBJDIR)/; fi" 81 | 82 | .PHONY: clean 83 | clean: 84 | rm -rf helloworld 85 | -------------------------------------------------------------------------------- /bench/cpp/README.md: -------------------------------------------------------------------------------- 1 | At one time, this was the directory containing the ZipCPU bench simulation. 2 | 3 | That simulation has now moved to the [sim/verilator](sim/verilator) directory. 4 | 5 | Therefore, I expect to remove this directory in the future--it's not really 6 | serving a purpose anymore. 7 | -------------------------------------------------------------------------------- /bench/cpp/helloworld.c: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: helloworld.c 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: The original Helllo World program. If everything works, this 8 | // will print Hello World to the UART, and then halt the CPU--if 9 | // run with no O/S. 10 | // 11 | // 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // 14 | // Gisselquist Technology asserts no ownership rights over this particular 15 | // hello world program. 16 | // 17 | //////////////////////////////////////////////////////////////////////////////// 18 | // 19 | // }}} 20 | #include 21 | 22 | int main(int argc, char **argv) { 23 | printf("Hello, World!\r\n"); 24 | return 0; 25 | } 26 | 27 | -------------------------------------------------------------------------------- /bench/cpp/memsim.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/cpp/memsim.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: This creates a memory like device to act on a WISHBONE bus. 8 | // It doesn't exercise the bus thoroughly, but does give some 9 | // exercise to the bus to see whether or not the bus master can control it. 10 | // 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // }}} 40 | #ifndef MEMSIM_H 41 | #define MEMSIM_H 42 | 43 | class MEMSIM { 44 | public: 45 | typedef unsigned int BUSW; 46 | typedef unsigned char uchar; 47 | 48 | BUSW *m_mem, m_len, m_mask; 49 | int m_nxt_ack; 50 | BUSW m_nxt_data; 51 | 52 | 53 | MEMSIM(const unsigned int nwords); 54 | ~MEMSIM(void); 55 | void load(const char *fname); 56 | void apply(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, 57 | const uchar wb_we, 58 | const BUSW wb_addr, const BUSW wb_data, 59 | uchar &o_ack, uchar &o_stall, BUSW &o_data); 60 | void operator()(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, const uchar wb_we, 61 | const BUSW wb_addr, const BUSW wb_data, 62 | uchar &o_ack, uchar &o_stall, BUSW &o_data) { 63 | apply(clk, wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data); 64 | } 65 | BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; } 66 | }; 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /bench/cpp/mpyraw.c: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: bench/cpp/mpyraw.c 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: To test GCC's multiply "instructions", and see if they work 8 | // properly. 9 | // 10 | // 11 | // Creator: Dan Gisselquist, Ph.D. 12 | // Gisselquist Technology, LLC 13 | // 14 | //////////////////////////////////////////////////////////////////////////////// 15 | // }}} 16 | // Copyright (C) 2017-2025, Gisselquist Technology, LLC 17 | // {{{ 18 | // This program is free software (firmware): you can redistribute it and/or 19 | // modify it under the terms of the GNU General Public License as published 20 | // by the Free Software Foundation, either version 3 of the License, or (at 21 | // your option) any later version. 22 | // 23 | // This program is distributed in the hope that it will be useful, but WITHOUT 24 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | // for more details. 27 | // 28 | // You should have received a copy of the GNU General Public License along 29 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 30 | // target there if the PDF file isn't present.) If not, see 31 | // for a copy. 32 | // }}} 33 | // License: GPL, v3, as defined and found on www.gnu.org, 34 | // {{{ 35 | // http://www.gnu.org/licenses/gpl.html 36 | // 37 | //////////////////////////////////////////////////////////////////////////////// 38 | // 39 | // }}} 40 | #include 41 | 42 | asm("\t.section\t.start,\"ax\",@progbits\n" 43 | "\t.global\t_start\n" 44 | "_start:\n" 45 | "\tLDI\t_top_of_stack,SP\n" 46 | "\tJSR\tentry\n" 47 | "_halt_cpu:\n" 48 | "\tNOOP\n" 49 | "\tNEXIT 0\n" 50 | "\tHALT\n"); 51 | 52 | long mpysquare(long a) { 53 | return a * a; 54 | } 55 | 56 | long mpypair(long a, long b) { 57 | return a * b; 58 | } 59 | 60 | void entry(void) { 61 | uint32_t fill, taps; 62 | 63 | fill = 1; 64 | taps = 0x4597f; 65 | 66 | for(int i=0; i<50; i++) { 67 | long r; uint32_t hi, lo; 68 | r = mpypair(0x271828314159l + (unsigned)fill, 0x3415928l); 69 | lo = (uint32_t)r; 70 | hi = (uint32_t)(r>>32); 71 | asm("NDUMP %0" : : "r"(lo)); 72 | asm("NDUMP %0" : : "r"(hi)); 73 | 74 | r = mpysquare(0x271828314159l + (unsigned)fill); 75 | lo = (uint32_t)r; 76 | hi = (uint32_t)(r>>32); 77 | asm("NDUMP %0" : : "r"(lo)); 78 | asm("NDUMP %0" : : "r"(hi)); 79 | 80 | if (fill&1) { 81 | fill = (fill >> 1)^taps; 82 | } else fill = fill >> 1; 83 | } 84 | } 85 | -------------------------------------------------------------------------------- /bench/formal/.gitignore: -------------------------------------------------------------------------------- 1 | ## Bus property sets, not included in repo 2 | ## 3 | faxi_addr.v 4 | faxi_slave.v 5 | faxi_master.v 6 | faxi_valaddr.v 7 | faxi_wstrb.v 8 | # 9 | faxil_slave.v 10 | faxil_master.v 11 | 12 | ## Wrappers 13 | zipaxi*/ 14 | zipbones*/ 15 | zipaxil*/ 16 | 17 | ## Core 18 | zipcore*/ 19 | zipcpu*/ 20 | 21 | ## Fetch 22 | axilfetch*/ 23 | axiicache*/ 24 | dblfetch*/ 25 | pfcache*/ 26 | pffifo*/ 27 | prefetch*/ 28 | 29 | ## Memory 30 | dcache*/ 31 | axiops*/ 32 | axilops*/ 33 | axilpipe*/ 34 | axidcache*/ 35 | axipipe*/ 36 | memops*/ 37 | pipemem*/ 38 | memdev*/ 39 | 40 | ## Peripherals 41 | axilperiphs*/ 42 | zipcounter*/ 43 | ziptimer*/ 44 | zipjiffies*/ 45 | icontrol*/ 46 | wbwatchdog*/ 47 | 48 | ## ZipDMA 49 | zipdma_mm2s*/ 50 | zipdma_rxgears*/ 51 | zipdma_txgears*/ 52 | zipdma_s2mm*/ 53 | wbdmac*/ 54 | 55 | ## Other 56 | div*/ 57 | idecode*/ 58 | busdelay*/ 59 | cpuops*/ 60 | wbdblpriarb*/ 61 | wbpriarbiter*/ 62 | zipmmu*/ 63 | -------------------------------------------------------------------------------- /bench/formal/axidcache.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Sat Apr 3 12:28:25 2021 4 | [*] 5 | [dumpfile_mtime] "Sat Apr 3 12:24:54 2021" 6 | [dumpfile_size] 112565 7 | [timestart] 0 8 | [size] 1628 843 9 | [pos] -1 -1 10 | *-4.910860 60 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [sst_width] 270 12 | [signals_width] 210 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 228 15 | @28 16 | axidcache.S_AXI_ACLK 17 | axidcache.S_AXI_ARESETN 18 | @200 19 | - 20 | - 21 | @28 22 | axidcache.state[1:0] 23 | @c00200 24 | -CPU Interface 25 | @28 26 | [color] 3 27 | axidcache.i_cpu_reset 28 | [color] 3 29 | axidcache.i_clear 30 | [color] 3 31 | axidcache.i_pipe_stb 32 | [color] 2 33 | axidcache.o_pipe_stalled 34 | @22 35 | [color] 3 36 | axidcache.i_addr[31:0] 37 | [color] 3 38 | axidcache.i_data[31:0] 39 | @28 40 | [color] 3 41 | axidcache.i_op[2:0] 42 | @22 43 | [color] 3 44 | axidcache.i_oreg[4:0] 45 | @200 46 | - 47 | @28 48 | axidcache.o_valid 49 | axidcache.o_busy 50 | axidcache.o_rdbusy 51 | axidcache.o_err 52 | @22 53 | axidcache.o_data[31:0] 54 | axidcache.o_wreg[4:0] 55 | @28 56 | axidcache.i_lock 57 | @22 58 | axidcache.i_caddr[5:0] 59 | @28 60 | axidcache.i_cline[2:0] 61 | @22 62 | axidcache.i_ctag[23:0] 63 | @1401200 64 | -CPU Interface 65 | @800200 66 | -AXI Writes 67 | @28 68 | [color] 2 69 | axidcache.M_AXI_AWVALID 70 | [color] 3 71 | axidcache.M_AXI_AWREADY 72 | @22 73 | [color] 2 74 | axidcache.M_AXI_AWADDR[31:0] 75 | [color] 2 76 | axidcache.M_AXI_AWLEN[7:0] 77 | @28 78 | [color] 2 79 | axidcache.M_AXI_AWBURST[1:0] 80 | [color] 2 81 | axidcache.M_AXI_AWSIZE[2:0] 82 | [color] 2 83 | axidcache.M_AXI_AWPROT[2:0] 84 | @22 85 | [color] 2 86 | axidcache.M_AXI_AWCACHE[3:0] 87 | @200 88 | - 89 | @28 90 | [color] 2 91 | axidcache.M_AXI_WVALID 92 | [color] 3 93 | axidcache.M_AXI_WREADY 94 | @22 95 | [color] 2 96 | axidcache.M_AXI_WDATA[31:0] 97 | [color] 2 98 | axidcache.M_AXI_WSTRB[3:0] 99 | @28 100 | [color] 2 101 | axidcache.M_AXI_WLAST 102 | @200 103 | - 104 | @28 105 | [color] 3 106 | axidcache.M_AXI_BVALID 107 | [color] 2 108 | axidcache.M_AXI_BREADY 109 | [color] 3 110 | axidcache.M_AXI_BRESP[1:0] 111 | @1000200 112 | -AXI Writes 113 | @c00200 114 | -AXI Reads 115 | @28 116 | [color] 2 117 | axidcache.M_AXI_ARVALID 118 | [color] 3 119 | axidcache.M_AXI_ARREADY 120 | @22 121 | [color] 2 122 | axidcache.M_AXI_ARADDR[31:0] 123 | [color] 2 124 | axidcache.M_AXI_ARLEN[7:0] 125 | @28 126 | [color] 2 127 | axidcache.M_AXI_ARSIZE[2:0] 128 | [color] 2 129 | axidcache.M_AXI_ARBURST[1:0] 130 | [color] 2 131 | axidcache.M_AXI_ARPROT[2:0] 132 | @22 133 | [color] 2 134 | axidcache.M_AXI_ARCACHE[3:0] 135 | @200 136 | - 137 | @28 138 | [color] 3 139 | axidcache.M_AXI_RVALID 140 | [color] 2 141 | axidcache.M_AXI_RREADY 142 | @22 143 | [color] 3 144 | axidcache.M_AXI_RDATA[31:0] 145 | @28 146 | [color] 3 147 | axidcache.M_AXI_RLAST 148 | [color] 3 149 | axidcache.M_AXI_RRESP[1:0] 150 | @1401200 151 | -AXI Reads 152 | [pattern_trace] 1 153 | [pattern_trace] 0 154 | -------------------------------------------------------------------------------- /bench/formal/axidcache.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prflk prf opt_lock 4 | prflp prf opt_lowpower 5 | prflplk prf opt_lowpower opt_lock 6 | prf64 prf bus64 7 | prf64lk prf bus64 opt_lock 8 | prfs prf swap_wstrb 9 | prfs64 prf bus64 swap_wstrb 10 | prfsw prf swap_wstrb opt_wrap 11 | prfs64w prf bus64 swap_wstrb opt_wrap 12 | cvr 13 | prfp prf opt_pipe 14 | prfplk prf opt_pipe opt_lock 15 | prfplp prf opt_pipe opt_lowpower 16 | prf64p prf bus64 opt_pipe 17 | prfsp prf swap_wstrb opt_pipe 18 | prfs64p prf bus64 swap_wstrb opt_pipe 19 | prfspw prf swap_wstrb opt_pipe opt_wrap 20 | prfs64pw prf bus64 swap_wstrb opt_pipe opt_wrap 21 | prfspwlk prf swap_wstrb opt_pipe opt_wrap opt_lock 22 | prfs64pwlk prf bus64 swap_wstrb opt_pipe opt_wrap opt_lock 23 | cvrp cvr opt_pipe 24 | 25 | [options] 26 | prf: mode prove 27 | prf: depth 10 28 | cvr: mode cover 29 | cvr: depth 35 30 | 31 | [engines] 32 | # prf: smtbmc 33 | smtbmc boolector 34 | 35 | [script] 36 | read -formal faxi_valaddr.v 37 | read -formal faxi_wstrb.v 38 | read -formal faxi_addr.v 39 | read -formal faxi_master.v 40 | read -formal fmem.v 41 | read -formal axidcache.v 42 | read -formal iscachable.v 43 | --pycode-begin-- 44 | cmd = "hierarchy -top axidcache" 45 | cmd += " -chparam LGCACHELEN %d" % (7 if "bus64" in tags else 6) 46 | cmd += " -chparam LGNLINES %d" % (3 if "cvr" in tags else 3) 47 | cmd += " -chparam SWAP_WSTRB %d" % (1 if "swap_wstrb" in tags else 0) 48 | cmd += " -chparam OPT_SIGN_EXTEND %d" % (1 if "sign_extend" in tags else 0) 49 | cmd += " -chparam OPT_PIPE %d" % (1 if "opt_pipe" in tags else 0) 50 | cmd += " -chparam OPT_WRAP %d" % (1 if "opt_wrap" in tags else 0) 51 | cmd += " -chparam OPT_LOCK %d" % (1 if "opt_lock" in tags else 0) 52 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 53 | if ("bus64" in tags): 54 | cmd += " -chparam C_AXI_DATA_WIDTH 64" 55 | else: 56 | cmd += " -chparam C_AXI_DATA_WIDTH 32" 57 | output(cmd) 58 | --pycode-end-- 59 | proc -norom 60 | prep -top axidcache 61 | 62 | [files] 63 | ffetch.v 64 | ../../rtl/core/axidcache.v 65 | ../../rtl/core/iscachable.v 66 | fmem.v 67 | faxi_master.v 68 | faxi_valaddr.v 69 | faxi_wstrb.v 70 | faxi_addr.v 71 | -------------------------------------------------------------------------------- /bench/formal/axiicache.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Jun 10 20:21:04 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1699 903 8 | [pos] -1 -1 9 | *-4.696020 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 196 11 | [signals_width] 198 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 261 14 | @28 15 | axiicache.S_AXI_ACLK 16 | axiicache.S_AXI_ARESETN 17 | @200 18 | - 19 | @800200 20 | -CPU Interface 21 | @28 22 | [color] 3 23 | axiicache.i_cpu_reset 24 | [color] 3 25 | axiicache.i_clear_cache 26 | [color] 3 27 | axiicache.i_new_pc 28 | @22 29 | [color] 3 30 | axiicache.i_pc[31:0] 31 | @28 32 | [color] 3 33 | axiicache.i_ready 34 | axiicache.o_valid 35 | @22 36 | axiicache.o_pc[31:0] 37 | axiicache.o_insn[31:0] 38 | @28 39 | axiicache.o_illegal 40 | @1000200 41 | -CPU Interface 42 | @800200 43 | -AXI Read Interface 44 | @28 45 | [color] 2 46 | axiicache.M_AXI_ARVALID 47 | [color] 3 48 | axiicache.M_AXI_ARREADY 49 | [color] 2 50 | axiicache.M_AXI_ARID 51 | @22 52 | [color] 2 53 | axiicache.M_AXI_ARADDR[31:0] 54 | [color] 2 55 | axiicache.M_AXI_ARLEN[7:0] 56 | @28 57 | [color] 2 58 | axiicache.M_AXI_ARBURST[1:0] 59 | @22 60 | [color] 2 61 | axiicache.M_AXI_ARCACHE[3:0] 62 | @28 63 | [color] 2 64 | axiicache.M_AXI_ARLOCK 65 | [color] 2 66 | axiicache.M_AXI_ARPROT[2:0] 67 | @22 68 | [color] 2 69 | axiicache.M_AXI_ARQOS[3:0] 70 | @28 71 | [color] 2 72 | axiicache.M_AXI_ARSIZE[2:0] 73 | @200 74 | - 75 | @28 76 | [color] 3 77 | axiicache.M_AXI_RVALID 78 | [color] 2 79 | axiicache.M_AXI_RREADY 80 | [color] 3 81 | axiicache.M_AXI_RID 82 | @22 83 | [color] 3 84 | axiicache.M_AXI_RDATA[31:0] 85 | @28 86 | [color] 3 87 | axiicache.M_AXI_RLAST 88 | [color] 3 89 | axiicache.M_AXI_RRESP[1:0] 90 | @22 91 | axiicache.faxi_awr_nbursts[9:0] 92 | @1000200 93 | -AXI Read Interface 94 | @28 95 | axiicache.void_access 96 | axiicache.bus_abort 97 | axiicache.request_pending 98 | [pattern_trace] 1 99 | [pattern_trace] 0 100 | -------------------------------------------------------------------------------- /bench/formal/axiicache.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prf64 prf bus64 4 | prfw prf opt_wrap 5 | prfw64 prf bus64 opt_wrap 6 | cvr 7 | cvrw cvr opt_wrap 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 10 12 | prfw: depth 19 13 | prfw64: depth 19 14 | cvr: mode cover 15 | cvr: depth 40 16 | cvrw: depth 28 17 | 18 | [engines] 19 | smtbmc yices 20 | ## ~cvr: smtbmc boolector 21 | 22 | [script] 23 | read -formal faxi_valaddr.v 24 | read -formal faxi_wstrb.v 25 | read -formal faxi_addr.v 26 | read -formal faxi_master.v 27 | read -formal ffetch.v 28 | read -formal axiicache.v 29 | --pycode-begin-- 30 | cmd = "hierarchy -top axiicache" 31 | cmd += " -chparam LGCACHESZ 9" 32 | cmd += " -chparam LGLINESZ 2" 33 | cmd += " -chparam OPT_WRAP %d" % (1 if "opt_wrap" in tags else 0) 34 | if ("bus64" in tags): 35 | cmd += " -chparam C_AXI_DATA_WIDTH 64" 36 | elif ("bus128" in tags): 37 | cmd += " -chparam C_AXI_DATA_WIDTH 128" 38 | elif ("bus256" in tags): 39 | cmd += " -chparam C_AXI_DATA_WIDTH 256" 40 | elif ("bus512" in tags): 41 | cmd += " -chparam C_AXI_DATA_WIDTH 512" 42 | else: 43 | cmd += " -chparam C_AXI_DATA_WIDTH 32" 44 | output(cmd) 45 | --pycode-end-- 46 | proc -norom 47 | prep -top axiicache 48 | 49 | [files] 50 | ffetch.v 51 | ../../rtl/core/axiicache.v 52 | faxi_master.v 53 | faxi_valaddr.v 54 | faxi_wstrb.v 55 | faxi_addr.v 56 | -------------------------------------------------------------------------------- /bench/formal/axilfetch.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Jun 11 14:47:27 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1001 547 7 | [pos] -1 473 8 | *-6.357261 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 39 10 | [signals_width] 250 11 | [sst_expanded] 0 12 | [sst_vpaned_height] 200 13 | @28 14 | axilfetch.S_AXI_ACLK 15 | axilfetch.S_AXI_ARESETN 16 | @200 17 | - 18 | @28 19 | axilfetch.i_cpu_reset 20 | axilfetch.i_new_pc 21 | axilfetch.i_clear_cache 22 | @22 23 | axilfetch.i_pc[31:0] 24 | @28 25 | [color] 2 26 | axilfetch.o_valid 27 | axilfetch.i_ready 28 | @22 29 | [color] 2 30 | axilfetch.o_pc[31:0] 31 | [color] 2 32 | axilfetch.o_insn[31:0] 33 | @29 34 | [color] 2 35 | axilfetch.o_illegal 36 | @200 37 | - 38 | @800200 39 | -AXI-Lite 40 | @28 41 | [color] 2 42 | axilfetch.M_AXI_ARVALID 43 | [color] 3 44 | axilfetch.M_AXI_ARREADY 45 | @22 46 | [color] 2 47 | axilfetch.M_AXI_ARADDR[31:0] 48 | @200 49 | - 50 | @28 51 | [color] 3 52 | axilfetch.M_AXI_RVALID 53 | [color] 2 54 | axilfetch.M_AXI_RREADY 55 | [color] 3 56 | axilfetch.M_AXI_RRESP[1:0] 57 | @1000200 58 | -AXI-Lite 59 | [pattern_trace] 1 60 | [pattern_trace] 0 61 | -------------------------------------------------------------------------------- /bench/formal/axilfetch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf bus32 3 | cvr bus32 4 | prfdbl prf opt_double bus32 5 | cvrdbl cvr opt_double bus32 6 | prff prf opt_fifo bus32 7 | cvrf cvr opt_fifo bus32 8 | prf64 prf bus64 9 | cvr64 cvr bus64 10 | prfdbl64 prf opt_double bus64 11 | cvrdbl64 cvr opt_double bus64 12 | prff64 prf opt_fifo bus64 13 | cvrf64 cvr opt_fifo bus64 14 | 15 | [options] 16 | prf: mode prove 17 | prf: depth 5 18 | opt_fifo: depth 6 19 | cvr: mode cover 20 | cvr: depth 30 21 | 22 | [engines] 23 | prf: smtbmc 24 | cvr: smtbmc 25 | 26 | [script] 27 | read -define AXILOPS 28 | read -define F_PEEK 29 | read -formal axilfetch.v 30 | read -formal sfifo.v 31 | read -formal faxil_master.v 32 | read -formal ffetch.v 33 | --pycode-begin-- 34 | cmd = "hierarchy -top axilfetch" 35 | 36 | if ("bus64" in tags): 37 | cmd +=" -chparam C_AXI_DATA_WIDTH 64" 38 | else: 39 | cmd +=" -chparam C_AXI_DATA_WIDTH 32" 40 | 41 | if ("opt_double" in tags): 42 | cmd +=" -chparam FETCH_LIMIT 2" 43 | elif ("opt_fifo" in tags): 44 | cmd +=" -chparam FETCH_LIMIT 8" 45 | else: 46 | cmd +=" -chparam FETCH_LIMIT 1" 47 | 48 | output(cmd) 49 | --pycode-end-- 50 | 51 | prep -top axilfetch 52 | 53 | [files] 54 | ../../rtl/core/axilfetch.v 55 | faxil_master.v 56 | ../../rtl/ex/sfifo.v 57 | ffetch.v 58 | -------------------------------------------------------------------------------- /bench/formal/axilfetch64.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Thu Jun 11 14:48:45 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1111 600 7 | [pos] -1 -1 8 | *-5.654441 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 196 10 | [signals_width] 174 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 155 13 | @28 14 | axilfetch.S_AXI_ACLK 15 | axilfetch.S_AXI_ARESETN 16 | @200 17 | - 18 | @800200 19 | -CPU Interface 20 | @28 21 | axilfetch.i_cpu_reset 22 | axilfetch.i_new_pc 23 | axilfetch.i_clear_cache 24 | @22 25 | axilfetch.i_pc[31:0] 26 | @28 27 | [color] 2 28 | axilfetch.o_valid 29 | axilfetch.i_ready 30 | @22 31 | [color] 2 32 | axilfetch.o_pc[31:0] 33 | [color] 2 34 | axilfetch.o_insn[31:0] 35 | @28 36 | [color] 2 37 | axilfetch.o_illegal 38 | @1000200 39 | -CPU Interface 40 | @800200 41 | -AXI-Lite 42 | @28 43 | [color] 2 44 | axilfetch.M_AXI_ARVALID 45 | [color] 3 46 | axilfetch.M_AXI_ARREADY 47 | @22 48 | [color] 2 49 | axilfetch.M_AXI_ARADDR[31:0] 50 | @200 51 | - 52 | @28 53 | [color] 3 54 | axilfetch.M_AXI_RVALID 55 | [color] 2 56 | axilfetch.M_AXI_RREADY 57 | @22 58 | [color] 3 59 | axilfetch.M_AXI_RDATA[63:0] 60 | @28 61 | [color] 3 62 | axilfetch.M_AXI_RRESP[1:0] 63 | @1000200 64 | -AXI-Lite 65 | [pattern_trace] 1 66 | [pattern_trace] 0 67 | -------------------------------------------------------------------------------- /bench/formal/axilops.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Tue May 19 21:13:00 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1920 1029 7 | [pos] -1 -1 8 | *-4.909014 102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 196 10 | [signals_width] 246 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 306 13 | @28 14 | axilops.S_AXI_ACLK 15 | axilops.S_AXI_ARESETN 16 | @200 17 | - 18 | @28 19 | axilops.i_stb 20 | @22 21 | axilops.i_addr[29:0] 22 | axilops.i_data[31:0] 23 | @28 24 | axilops.i_op[2:0] 25 | @22 26 | axilops.i_oreg[4:0] 27 | @200 28 | - 29 | @28 30 | axilops.o_busy 31 | axilops.o_valid 32 | axilops.o_err 33 | axilops.o_rdbusy 34 | @22 35 | axilops.o_result[31:0] 36 | axilops.o_wreg[4:0] 37 | @200 38 | - 39 | @800200 40 | -Writes 41 | @28 42 | [color] 2 43 | axilops.M_AXI_AWVALID 44 | [color] 3 45 | axilops.M_AXI_AWREADY 46 | @22 47 | [color] 2 48 | axilops.M_AXI_AWADDR[29:0] 49 | @28 50 | [color] 2 51 | axilops.M_AXI_AWPROT[2:0] 52 | @200 53 | - 54 | @28 55 | [color] 2 56 | axilops.M_AXI_WVALID 57 | [color] 3 58 | axilops.M_AXI_WREADY 59 | @22 60 | [color] 2 61 | axilops.M_AXI_WDATA[31:0] 62 | axilops.M_AXI_WSTRB[3:0] 63 | @200 64 | - 65 | @28 66 | [color] 3 67 | axilops.M_AXI_BVALID 68 | [color] 2 69 | axilops.M_AXI_BREADY 70 | [color] 3 71 | axilops.M_AXI_BRESP[1:0] 72 | @200 73 | - 74 | @28 75 | axilops.faxil_awr_outstanding[1:0] 76 | axilops.faxil_wr_outstanding[1:0] 77 | @1000200 78 | -Writes 79 | @800200 80 | -Reads 81 | @28 82 | [color] 2 83 | axilops.M_AXI_ARVALID 84 | [color] 3 85 | axilops.M_AXI_ARREADY 86 | @22 87 | [color] 2 88 | axilops.M_AXI_ARADDR[29:0] 89 | @28 90 | [color] 2 91 | axilops.M_AXI_ARPROT[2:0] 92 | @200 93 | - 94 | @28 95 | [color] 3 96 | axilops.M_AXI_RVALID 97 | [color] 2 98 | axilops.M_AXI_RREADY 99 | @22 100 | [color] 3 101 | axilops.M_AXI_RDATA[31:0] 102 | @28 103 | [color] 3 104 | axilops.M_AXI_RRESP[1:0] 105 | @200 106 | - 107 | @28 108 | axilops.faxil_rd_outstanding[1:0] 109 | @1000200 110 | -Reads 111 | @200 112 | - 113 | - 114 | @28 115 | axilops.w_misaligned 116 | @29 117 | axilops.misaligned_request 118 | @28 119 | axilops.misaligned_aw_request 120 | axilops.misaligned_read 121 | axilops.misaligned_response_pending 122 | @200 123 | - 124 | [pattern_trace] 1 125 | [pattern_trace] 0 126 | -------------------------------------------------------------------------------- /bench/formal/axilops.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf bus32 3 | prfu prf opt_realignment bus32 4 | prf64 prf bus64 5 | prfu64 prf opt_realignment bus64 6 | prflp prf bus32 opt_lowpower 7 | prfulp prf opt_realignment bus32 opt_lowpower 8 | prf64lp prf bus64 opt_lowpower 9 | prfu64lp prf opt_realignment bus64 opt_lowpower 10 | 11 | cvr bus32 12 | cvr64 cvr bus64 opt_lowpower 13 | 14 | [options] 15 | prf: mode prove 16 | prf: depth 3 17 | prfu: depth 3 18 | cvr: mode cover 19 | 20 | [engines] 21 | cvr: smtbmc 22 | # prf: abc pdr 23 | prf: smtbmc 24 | 25 | [script] 26 | read -define AXILOPS 27 | read -formal axilops.v 28 | read -formal faxil_master.v 29 | read -formal fmem.v 30 | --pycode-begin-- 31 | cmd = "hierarchy -top axilops" 32 | cmd +=" -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 33 | cmd +=" -chparam OPT_ALIGNMENT_ERR %d" % (0 if "opt_realignment" in tags else 1) 34 | if ("bus64" in tags): 35 | cmd +=" -chparam C_AXI_DATA_WIDTH 64" 36 | else: 37 | cmd +=" -chparam C_AXI_DATA_WIDTH 32" 38 | output(cmd) 39 | --pycode-end-- 40 | prep -top axilops 41 | 42 | [files] 43 | ../../rtl/core/axilops.v 44 | faxil_master.v 45 | fmem.v 46 | -------------------------------------------------------------------------------- /bench/formal/axilperiphs.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | # cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 5 8 | # cvr: mode cover 9 | # cvr: depth 20 10 | 11 | [engines] 12 | prf: smtbmc 13 | # cvr: smtbmc 14 | 15 | [script] 16 | read -formal ziptimer.v 17 | read -formal zipjiffies.v 18 | read -formal icontrol.v 19 | read -formal skidbuffer.v 20 | read -formal faxil_slave.v 21 | read -formal fwb_slave.v 22 | read -formal axilperiphs.v 23 | prep -top axilperiphs 24 | 25 | [files] 26 | ../../rtl/peripherals/axilperiphs.v 27 | ../../rtl/peripherals/ziptimer.v 28 | ../../rtl/peripherals/icontrol.v 29 | ../../rtl/peripherals/zipjiffies.v 30 | faxil_slave.v 31 | ../../rtl/ex/fwb_slave.v 32 | ../../rtl/ex/skidbuffer.v 33 | ../../rtl/ex/sfifo.v 34 | -------------------------------------------------------------------------------- /bench/formal/axilpipe.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr bus32 3 | cvru cvr opt_realignment bus32 4 | prf bus32 5 | prfu prf opt_realignment bus32 6 | cvr64 cvr bus64 7 | prf64 prf bus64 8 | prfu64 prf opt_realignment bus64 9 | # bmc 10 | bmcu bmc opt_realignemnt 11 | bmc64 bmc bus64 12 | bmcu64 bmc opt_realignemnt bus64 13 | 14 | [options] 15 | prf: mode prove 16 | prf: depth 13 17 | prfu: depth 20 18 | bmc: mode bmc 19 | # bmc: depth 13 20 | bmcu: depth 40 21 | cvr: mode cover 22 | cvr: depth 30 23 | cvru: depth 42 24 | 25 | [engines] 26 | cvr: smtbmc 27 | # prf: abc pdr 28 | bmc: smtbmc 29 | prf: smtbmc 30 | 31 | [script] 32 | read -define AXILPIPE 33 | bmc: read -define BMC_ASSERT=assert 34 | read -formal axilpipe.v 35 | read -formal faxil_master.v 36 | read -formal fmem.v 37 | --pycode-begin-- 38 | cmd = "hierarchy -top axilpipe" 39 | cmd +=" -chparam OPT_ALIGNMENT_ERR %d" % (0 if "opt_realignment" in tags else 1) 40 | if ("bus64" in tags): 41 | cmd +=" -chparam C_AXI_DATA_WIDTH 64" 42 | else: 43 | cmd +=" -chparam C_AXI_DATA_WIDTH 32" 44 | output(cmd) 45 | --pycode-end-- 46 | 47 | prep -top axilpipe 48 | cvr: chformal -assert -remove 49 | 50 | [files] 51 | ../../rtl/core/axilpipe.v 52 | faxil_master.v 53 | fmem.v 54 | -------------------------------------------------------------------------------- /bench/formal/axiops.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr bus32 3 | prf bus32 4 | prfs prf bus32 swap_strb 5 | prfu prf opt_realignment bus32 6 | prfsu prf opt_realignment bus32 swap_strb 7 | cvr64 cvr bus64 opt_lowpower 8 | prf64 prf bus64 9 | prfs64 prf bus64 swap_strb 10 | prfu64 prf opt_realignment bus64 11 | prfsu64 prf opt_realignment bus64 swap_strb 12 | prflp prf bus32 opt_lowpower 13 | prfulp prf opt_realignment bus32 opt_lowpower 14 | prf64lp prf bus64 opt_lowpower 15 | prfu64lp prf opt_realignment bus64 opt_lowpower 16 | 17 | [options] 18 | prf: mode prove 19 | prf: depth 7 20 | cvr: mode cover 21 | cvr: depth 40 22 | 23 | [engines] 24 | cvr: smtbmc 25 | # prf: abc pdr 26 | prf: smtbmc 27 | 28 | [script] 29 | read -define AXIOPS 30 | read -formal axiops.v 31 | read -formal faxi_master.v 32 | read -formal faxi_wstrb.v 33 | read -formal faxi_valaddr.v 34 | read -formal faxi_addr.v 35 | read -formal fmem.v 36 | --pycode-begin-- 37 | cmd = "hierarchy -top axiops" 38 | cmd +=" -chparam OPT_LOCK 1" 39 | cmd +=" -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 40 | cmd +=" -chparam OPT_ALIGNMENT_ERR %d" % (0 if "opt_realignment" in tags else 1) 41 | cmd +=" -chparam SWAP_WSTRB %d" % (1 if "swap_wstrb" in tags else 0) 42 | if ("bus64" in tags): 43 | cmd +=" -chparam C_AXI_DATA_WIDTH 64" 44 | else: 45 | cmd +=" -chparam C_AXI_DATA_WIDTH 32" 46 | output(cmd) 47 | --pycode-end-- 48 | prep -top axiops 49 | 50 | [files] 51 | ../../rtl/core/axiops.v 52 | faxi_master.v 53 | faxi_wstrb.v 54 | faxi_valaddr.v 55 | faxi_addr.v 56 | fmem.v 57 | -------------------------------------------------------------------------------- /bench/formal/axipipe.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr bus32 opt_lock 3 | cvru cvr opt_realignment bus32 opt_lock 4 | prf bus32 opt_lock 5 | prfu prf opt_realignment bus32 opt_lock 6 | prfs prf bus32 opt_lock swap_wstrb 7 | prfsu prf opt_realignment bus32 opt_lock swap_wstrb 8 | cvr64 cvr bus64 opt_lock 9 | prf64 prf bus64 opt_lock 10 | prfu64 prf opt_realignment bus64 opt_lock 11 | prfs64 prf bus64 opt_lock swap_wstrb 12 | prfsu64 prf opt_realignment bus64 opt_lock swap_wstrb 13 | # bmc 14 | bmcu bmc opt_realignemnt opt_lock 15 | bmc64 bmc bus64 opt_lock 16 | bmcu64 bmc opt_realignemnt bus64 opt_lock 17 | 18 | [options] 19 | prf: mode prove 20 | prf: depth 10 21 | bmc: mode bmc 22 | # bmc: depth 13 23 | bmcu: depth 40 24 | cvr: mode cover 25 | cvr: depth 30 26 | cvru: depth 42 27 | 28 | [engines] 29 | cvr: smtbmc 30 | # prf: abc pdr 31 | bmc: smtbmc 32 | prf: smtbmc 33 | 34 | [script] 35 | read -define AXILPIPE 36 | bmc: read -define BMC_ASSERT=assert 37 | read -formal axipipe.v 38 | read -formal faxi_master.v 39 | read -formal faxi_addr.v 40 | read -formal faxi_valaddr.v 41 | read -formal faxi_wstrb.v 42 | read -formal fmem.v 43 | --pycode-begin-- 44 | cmd = "hierarchy -top axipipe" 45 | cmd +=" -chparam OPT_ALIGNMENT_ERR %d" % (0 if "opt_realignment" in tags else 1) 46 | if ("bus64" in tags): 47 | cmd +=" -chparam C_AXI_DATA_WIDTH 64" 48 | else: 49 | cmd +=" -chparam C_AXI_DATA_WIDTH 32" 50 | cmd +=" -chparam OPT_LOCK %d" % (1 if "opt_lock" in tags else 0) 51 | cmd +=" -chparam SWAP_WSTRB %d" % (1 if "swap_wstrb" in tags else 0) 52 | cmd +=" -chparam OPT_LOWPOWER 0" 53 | output(cmd) 54 | --pycode-end-- 55 | 56 | prep -top axipipe 57 | cvr: chformal -assert -remove 58 | 59 | [files] 60 | ../../rtl/core/axipipe.v 61 | faxi_master.v 62 | faxi_addr.v 63 | faxi_valaddr.v 64 | faxi_wstrb.v 65 | fmem.v 66 | -------------------------------------------------------------------------------- /bench/formal/busdelay.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 3 | [*] Mon Mar 1 16:06:49 2021 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1920 1054 8 | [pos] -1 -1 9 | *-3.908651 25 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] busdelay. 11 | [sst_width] 329 12 | [signals_width] 206 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 290 15 | @28 16 | busdelay.i_clk 17 | busdelay.i_reset 18 | @200 19 | - 20 | @28 21 | [color] 3 22 | busdelay.i_wb_cyc 23 | [color] 3 24 | busdelay.i_wb_stb 25 | [color] 3 26 | busdelay.i_wb_we 27 | @22 28 | [color] 3 29 | busdelay.i_wb_addr[31:0] 30 | [color] 3 31 | busdelay.i_wb_data[31:0] 32 | [color] 3 33 | busdelay.i_wb_sel[3:0] 34 | @28 35 | busdelay.o_wb_stall 36 | busdelay.o_wb_ack 37 | @22 38 | busdelay.o_wb_data[31:0] 39 | @28 40 | [color] 1 41 | busdelay.o_wb_err 42 | @200 43 | - 44 | @28 45 | busdelay.o_dly_cyc 46 | busdelay.o_dly_stb 47 | busdelay.o_dly_we 48 | @22 49 | busdelay.o_dly_addr[31:0] 50 | busdelay.o_dly_data[31:0] 51 | busdelay.o_dly_sel[3:0] 52 | @28 53 | [color] 3 54 | busdelay.i_dly_stall 55 | [color] 3 56 | busdelay.i_dly_ack 57 | @22 58 | [color] 3 59 | busdelay.i_dly_data[31:0] 60 | @28 61 | [color] 1 62 | busdelay.i_dly_err 63 | @200 64 | - 65 | - 66 | @22 67 | busdelay.f_wb_request[69:0] 68 | busdelay.f_pending[69:0] 69 | busdelay.f_dly_request[69:0] 70 | @200 71 | - 72 | @22 73 | busdelay.f_wb_outstanding[3:0] 74 | busdelay.f_dly_outstanding[3:0] 75 | @201 76 | - 77 | @28 78 | busdelay.f_never 79 | @22 80 | busdelay.f_nvr_request[69:0] 81 | [pattern_trace] 1 82 | [pattern_trace] 0 83 | -------------------------------------------------------------------------------- /bench/formal/busdelay.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfd prf opt_delay_stall 4 | prflp prf opt_lowpower 5 | prfdlp prf opt_delay_stall opt_lowpower 6 | 7 | [options] 8 | prf: mode prove 9 | depth 14 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -D BUSDELAY busdelay.v 16 | read -formal -D BUSDELAY fwb_slave.v 17 | read -formal -D BUSDELAY fwb_master.v 18 | --pycode-begin-- 19 | cmd = "hierarchy -top busdelay" 20 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 21 | cmd += " -chparam DELAY_STALL %d" % (1 if "opt_delay_stall" in tags else 0) 22 | output(cmd) 23 | --pycode-end-- 24 | prep -top busdelay 25 | 26 | [files] 27 | ../../rtl/ex/busdelay.v 28 | ../../rtl/ex/fwb_slave.v 29 | ../../rtl/ex/fwb_master.v 30 | -------------------------------------------------------------------------------- /bench/formal/busdelay.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D BUSDELAY -formal ../../rtl/ex/busdelay.v 2 | read_verilog -D BUSDELAY -formal ../../rtl/ex/fwb_slave.v 3 | read_verilog -D BUSDELAY -formal ../../rtl/ex/fwb_master.v 4 | prep -top busdelay -nordff 5 | opt -share_all 6 | write_smt2 -wires busdelay.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/cpuops.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | mode prove 6 | depth 4 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal -D CPUOPS cpuops.v 13 | # read -formal -D CPUOPS mpyop.v 14 | read -formal -D CPUOPS abs_mpy.v 15 | chparam -set IMPLYMENT_MPY 3 cpuops.v 16 | prep -top cpuops 17 | 18 | [files] 19 | ../../rtl/core/cpuops.v 20 | ../../rtl/core/mpyop.v 21 | abs_mpy.v 22 | 23 | 24 | -------------------------------------------------------------------------------- /bench/formal/cpuops.ys: -------------------------------------------------------------------------------- 1 | read_verilog -I../../rtl -D CPUOPS -formal ../../rtl/core/cpuops.v 2 | # read_verilog -D CPUOPS -formal ../../rtl/core/mpyop.v 3 | read_verilog -D CPUOPS -formal abs_mpy.v 4 | prep -top cpuops -nordff 5 | chparam -set IMPLYMENT_MPY 3 cpuops.v 6 | write_smt2 -wires cpuops.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/dblfetch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf insn32 bus32 3 | cvr insn32 bus32 4 | prf8b prf insn8 bus32 5 | prf8ble prf insn8 bus32 lilend 6 | prf64b prf insn32 bus64 7 | prf128b prf insn32 bus128 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 8 12 | prf128b: depth 13 13 | 14 | cvr: mode cover 15 | cvr: depth 8 16 | 17 | [engines] 18 | smtbmc 19 | 20 | [script] 21 | read -formal fwb_master.v 22 | read -formal ffetch.v 23 | read -formal dblfetch.v 24 | --pycode-begin-- 25 | cmd = "hierarchy -top dblfetch" 26 | if ("insn8" in tags): 27 | cmd += " -chparam INSN_WIDTH 8" 28 | elif ("insn32" in tags): 29 | cmd += " -chparam INSN_WIDTH 32" 30 | if ("bus32" in tags): 31 | cmd += " -chparam DATA_WIDTH 32" 32 | elif ("bus64" in tags): 33 | cmd += " -chparam DATA_WIDTH 64" 34 | elif ("bus128" in tags): 35 | cmd += " -chparam DATA_WIDTH 128" 36 | cmd += " -chparam OPT_LITTLE_ENDIAN %d" % (1 if "lilend" in tags else 0) 37 | output(cmd) 38 | --pycode-end-- 39 | prep -top dblfetch 40 | 41 | [files] 42 | ffetch.v 43 | ../../rtl/core/dblfetch.v 44 | ../../rtl/ex/fwb_master.v 45 | -------------------------------------------------------------------------------- /bench/formal/dblfetch.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D DBLFETCH -formal ../../rtl/core/dblfetch.v 2 | read_verilog -D DBLFETCH -formal ../../rtl/ex/fwb_master.v 3 | prep -top dblfetch -nordff 4 | opt -share_all 5 | write_smt2 -wires dblfetch.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/dblfetchlogic.ys: -------------------------------------------------------------------------------- 1 | read_verilog ../../rtl/core/dblfetch.v 2 | synth_ice40 3 | -------------------------------------------------------------------------------- /bench/formal/dcache.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.98 (w)1999-2018 BSI 3 | [*] Sat Dec 8 19:23:32 2018 4 | [*] 5 | [timestart] 0 6 | [size] 1918 1021 7 | [pos] -1 -1 8 | *-4.957688 50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [treeopen] dcache. 10 | [sst_width] 196 11 | [signals_width] 240 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 378 14 | @28 15 | dcache.i_reset 16 | dcache.i_clk 17 | dcache.i_lock 18 | dcache.r_svalid 19 | dcache.r_dvalid 20 | dcache.i_pipe_stb 21 | dcache.o_pipe_stalled 22 | dcache.o_busy 23 | [color] 1 24 | dcache.state[1:0] 25 | dcache.i_op[2:0] 26 | @22 27 | dcache.i_oreg[4:0] 28 | dcache.i_addr[31:0] 29 | dcache.i_data[31:0] 30 | @200 31 | - 32 | @22 33 | dcache.o_wreg[4:0] 34 | dcache.o_data[31:0] 35 | @28 36 | dcache.o_err 37 | dcache.o_valid 38 | @200 39 | - 40 | @28 41 | [color] 3 42 | dcache.o_wb_cyc_gbl 43 | [color] 3 44 | dcache.o_wb_stb_gbl 45 | @200 46 | - 47 | @28 48 | [color] 3 49 | dcache.o_wb_cyc_lcl 50 | [color] 3 51 | dcache.o_wb_stb_lcl 52 | @200 53 | - 54 | @28 55 | [color] 3 56 | dcache.o_wb_we 57 | @22 58 | [color] 3 59 | dcache.o_wb_addr[29:0] 60 | [color] 3 61 | dcache.o_wb_data[31:0] 62 | [color] 3 63 | dcache.o_wb_sel[3:0] 64 | @200 65 | - 66 | @28 67 | [color] 2 68 | dcache.i_wb_stall 69 | [color] 2 70 | dcache.i_wb_ack 71 | @22 72 | [color] 2 73 | dcache.i_wb_data[31:0] 74 | @28 75 | [color] 2 76 | dcache.i_wb_err 77 | @200 78 | - 79 | @22 80 | [color] 3 81 | dcache.c_v[15:0] 82 | @28 83 | [color] 3 84 | dcache.c_wr 85 | @22 86 | [color] 3 87 | dcache.c_wdata[31:0] 88 | @28 89 | dcache.cache_miss_inow 90 | @22 91 | dcache.cached_idata[31:0] 92 | dcache.cached_rdata[31:0] 93 | dcache.f_cache_waddr[29:0] 94 | @200 95 | - 96 | @22 97 | dcache.f_const_tag[28:0] 98 | dcache.f_const_tag_addr[3:0] 99 | dcache.f_const_addr[30:0] 100 | @28 101 | dcache.f_const_buserr 102 | @200 103 | - 104 | @23 105 | dcache.f_ctag_here[28:0] 106 | @22 107 | dcache.f_cmem_here[31:0] 108 | @200 109 | - 110 | @28 111 | dcache.f_this_return 112 | @22 113 | [color] 3 114 | dcache.f_const_data[31:0] 115 | @28 116 | dcache.f_cyc 117 | dcache.f_cachable_r_addr 118 | dcache.f_wb_cachable 119 | dcache.f_cachable_last_tag 120 | dcache.f_past_valid 121 | dcache.f_stb 122 | dcache.f_this_cache_waddr 123 | dcache.f_wb_cachable 124 | dcache.in_cache 125 | @200 126 | - 127 | @28 128 | dcache.last_ack 129 | dcache.last_line_stb 130 | dcache.end_of_line 131 | @200 132 | - 133 | @22 134 | dcache.last_tag[28:0] 135 | @28 136 | dcache.last_tag_valid 137 | @22 138 | dcache.r_ctag[28:0] 139 | @200 140 | - 141 | @22 142 | dcache.f_cmem_here[31:0] 143 | dcache.f_const_data[31:0] 144 | @200 145 | - 146 | @28 147 | dcache.lock_gbl 148 | dcache.lock_lcl 149 | @22 150 | dcache.r_addr[29:0] 151 | @28 152 | dcache.r_cachable 153 | dcache.r_cache_miss 154 | dcache.r_iv 155 | dcache.r_rd 156 | [color] 1 157 | dcache.r_rd_pending 158 | dcache.r_wb_cyc_gbl 159 | dcache.r_wb_cyc_lcl 160 | dcache.stb 161 | dcache.w_cachable 162 | dcache.raw_cachable_address 163 | dcache.wr_cstb 164 | dcache.cyc 165 | [pattern_trace] 1 166 | [pattern_trace] 0 167 | -------------------------------------------------------------------------------- /bench/formal/dcache.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | full bus32 system lock dualread 3 | full_single bus32 system lock 4 | bare bus32 nolocal lock dualread 5 | nolock_nolocal bus32 nolocal nolock dualread 6 | nolock_system bus32 system nolock dualread 7 | piped bus32 system lock dualread 8 | cover bus32 system lock dualread 9 | cover_pipe bus32 system lock dualread cover piped 10 | piped_lp bus32 system lock dualread opt_lowpower 11 | prf64 bus64 system lock dualread 12 | prf64lp bus64 system lock dualread opt_lowpower 13 | prf128 bus128 system lock dualread 14 | prf128lp bus128 system lock dualread opt_lowpower 15 | 16 | [options] 17 | ~cover: mode prove 18 | cover: mode cover 19 | depth 16 20 | full: depth 9 21 | full_single: depth 9 22 | bare: depth 9 23 | nolock_nolocal: depth 9 24 | nolock_system: depth 9 25 | piped: depth 9 26 | cover: depth 24 27 | cover_pipe: depth 45 28 | 29 | [engines] 30 | # smtbmc yices 31 | smtbmc boolector 32 | # abc pdr 33 | # aiger suprove 34 | # aiger avy 35 | 36 | [script] 37 | read -formal fwb_master.v 38 | read -formal iscachable.v 39 | read -formal fmem.v 40 | read -formal -D DCACHE dcache.v 41 | --pycode-begin-- 42 | cmd = "hierarchy -top dcache" 43 | cmd += " -chparam OPT_PIPE %d" % (1 if "piped" in tags else 0) 44 | cmd += " -chparam OPT_DUAL_READ_PORT %d" % (1 if "dualread" in tags else 0) 45 | cmd += " -chparam OPT_LOCK %d" % (1 if "lock" in tags else 0) 46 | cmd += " -chparam OPT_LOCAL_BUS %d" % (1 if "system" in tags else 0) 47 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 48 | if ("bus32" in tags): 49 | cmd += " -chparam BUS_WIDTH 32" 50 | elif ("bus64" in tags): 51 | cmd += " -chparam BUS_WIDTH 64" 52 | elif ("bus128" in tags): 53 | cmd += " -chparam BUS_WIDTH 128" 54 | elif ("bus256" in tags): 55 | cmd += " -chparam BUS_WIDTH 256" 56 | elif ("bus512" in tags): 57 | cmd += " -chparam BUS_WIDTH 512" 58 | output(cmd) 59 | --pycode-end-- 60 | proc -norom 61 | prep -top dcache 62 | 63 | [files] 64 | ../../rtl/core/dcache.v 65 | ../../rtl/core/iscachable.v 66 | ../../rtl/ex/fwb_master.v 67 | fmem.v 68 | # 69 | -------------------------------------------------------------------------------- /bench/formal/dcache.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D DCACHE -formal ../../rtl/core/dcache.v 2 | read_verilog -D DCACHE -formal ../../rtl/ex/fwb_master.v 3 | prep -top dcache -nordff 4 | opt 5 | clean 6 | write_smt2 -wires dcache.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/div.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Sat Aug 11 16:11:56 2018 4 | [*] 5 | [timestart] 0 6 | [size] 1698 819 7 | [pos] -1 -1 8 | *-4.333802 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 270 10 | [signals_width] 220 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 221 13 | @28 14 | smt_clock 15 | div.i_clk 16 | div.i_reset 17 | @200 18 | - 19 | @28 20 | [color] 2 21 | div.i_wr 22 | [color] 2 23 | div.i_signed 24 | @22 25 | [color] 2 26 | div.i_numerator[31:0] 27 | [color] 2 28 | div.i_denominator[31:0] 29 | @200 30 | - 31 | @28 32 | [color] 3 33 | div.o_busy 34 | [color] 3 35 | div.o_valid 36 | @22 37 | [color] 3 38 | div.o_flags[3:0] 39 | [color] 3 40 | div.o_quotient[31:0] 41 | @28 42 | [color] 3 43 | div.o_err 44 | @200 45 | - 46 | @22 47 | div.r_bit[4:0] 48 | @28 49 | div.pre_sign 50 | div.r_busy 51 | div.r_sign 52 | @29 53 | div.last_bit 54 | @22 55 | div.diff[32:0] 56 | div.r_dividend[62:0] 57 | div.r_divisor[31:0] 58 | @28 59 | div.r_c 60 | div.r_z 61 | div.w_n 62 | div.zero_divisor 63 | @22 64 | div.f_bits_set[32:0] 65 | [pattern_trace] 1 66 | [pattern_trace] 0 67 | -------------------------------------------------------------------------------- /bench/formal/div.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prflp prf opt_lowpower 4 | 5 | [options] 6 | prf: mode prove 7 | depth 5 8 | 9 | [engines] 10 | smtbmc 11 | 12 | [script] 13 | read -formal -DDIV div.v 14 | opt_lowpower: hierarchy -top div -chparam OPT_LOWPOWER 1 15 | prep -top div 16 | 17 | [files] 18 | ../../rtl/core/div.v 19 | -------------------------------------------------------------------------------- /bench/formal/div.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D DIV -formal ../../rtl/core/div.v 2 | prep -top div -nordff 3 | opt -share_all 4 | clean 5 | write_smt2 -wires div.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/fetchlogic.ys: -------------------------------------------------------------------------------- 1 | # read_verilog ../../rtl/core/prefetch.v 2 | read_verilog ../../rtl/core/dblfetch.v 3 | # read_verilog ../../rtl/core/pfcache.v 4 | # proc 5 | # read_verilog old/prefetch.v 6 | # read_verilog /home/dan/work/rnd/opencores/zbasic/trunk/rtl/cpu/prefetch.v 7 | # read_verilog old/dblfetch.v 8 | # read_verilog /home/dan/work/rnd/opencores/s6soc/trunk/rtl/cpu/dblfetch.v 9 | # opt -share_all 10 | synth_xilinx 11 | # synth_ice40 12 | # write_blif prefetch.blif 13 | -------------------------------------------------------------------------------- /bench/formal/icontrol.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Sat Mar 30 19:34:36 2019 4 | [*] 5 | [timestart] 0 6 | [size] 1809 1016 7 | [pos] -810 -417 8 | *-2.795382 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 270 10 | [signals_width] 210 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 289 13 | @28 14 | icontrol.f_past_valid 15 | icontrol.i_reset 16 | icontrol.i_clk 17 | @200 18 | - 19 | @28 20 | [color] 3 21 | icontrol.i_wb_cyc 22 | [color] 3 23 | icontrol.i_wb_stb 24 | [color] 3 25 | icontrol.i_wb_we 26 | @22 27 | [color] 3 28 | icontrol.i_wb_data[31:0] 29 | @28 30 | [color] 2 31 | icontrol.o_wb_ack 32 | @22 33 | [color] 2 34 | icontrol.o_wb_data[31:0] 35 | @28 36 | [color] 2 37 | icontrol.o_wb_stall 38 | @200 39 | - 40 | @22 41 | [color] 3 42 | icontrol.i_brd_ints[11:0] 43 | @28 44 | [color] 3 45 | icontrol.w_any 46 | [color] 2 47 | icontrol.o_interrupt 48 | @22 49 | icontrol.r_int_enable[11:0] 50 | icontrol.r_int_state[11:0] 51 | @28 52 | icontrol.r_mie 53 | @200 54 | - 55 | @29 56 | [color] 1 57 | icontrol.wb_write 58 | [color] 1 59 | icontrol.disable_ints 60 | [color] 1 61 | icontrol.enable_ints 62 | @200 63 | - 64 | @28 65 | icontrol.f_nacks[1:0] 66 | icontrol.f_nreqs[1:0] 67 | icontrol.f_outstanding[1:0] 68 | [pattern_trace] 1 69 | [pattern_trace] 0 70 | -------------------------------------------------------------------------------- /bench/formal/icontrol.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 5 8 | cvr: mode cover 9 | cvr: depth 15 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal -DICONTROL icontrol.v 16 | read -formal -DICONTROL fwb_slave.v 17 | prep -top icontrol 18 | 19 | [files] 20 | ../../rtl/peripherals/icontrol.v 21 | ../../rtl/ex/fwb_slave.v 22 | -------------------------------------------------------------------------------- /bench/formal/icontrol.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ICONTROL -formal ../../rtl/peripherals/icontrol.v 2 | prep -top icontrol -nordff 3 | opt -share_all 4 | write_smt2 -wires icontrol.smt2 5 | -------------------------------------------------------------------------------- /bench/formal/idecode.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Sun Dec 2 03:08:39 2018 4 | [*] 5 | [size] 1665 600 6 | [pos] -1 -1 7 | *-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 | [sst_width] 270 9 | [signals_width] 230 10 | [sst_expanded] 1 11 | [sst_vpaned_height] 143 12 | @28 13 | idecode.i_ce 14 | idecode.i_clk 15 | idecode.i_gie 16 | idecode.i_pf_valid 17 | idecode.i_illegal 18 | @22 19 | idecode.i_instruction[31:0] 20 | idecode.i_pc[25:0] 21 | @28 22 | idecode.i_reset 23 | idecode.i_stalled 24 | @22 25 | idecode.iword[30:0] 26 | @200 27 | - 28 | @29 29 | idecode.o_valid 30 | @22 31 | idecode.o_dcdA[6:0] 32 | idecode.o_dcdB[6:0] 33 | @28 34 | idecode.o_ALU 35 | idecode.o_DV 36 | idecode.o_FP 37 | @22 38 | idecode.o_I[31:0] 39 | @28 40 | idecode.o_M 41 | @22 42 | idecode.o_branch_pc[25:0] 43 | @28 44 | idecode.o_break 45 | @22 46 | idecode.o_cond[3:0] 47 | @28 48 | idecode.o_early_branch 49 | idecode.o_early_branch_stb 50 | idecode.o_illegal 51 | idecode.o_ljmp 52 | idecode.o_lock 53 | @22 54 | idecode.o_op[3:0] 55 | idecode.o_pc[25:0] 56 | @28 57 | idecode.o_phase 58 | idecode.o_pipe 59 | @22 60 | idecode.o_preA[4:0] 61 | idecode.o_preB[4:0] 62 | @28 63 | idecode.o_rA 64 | idecode.o_rB 65 | idecode.o_sim 66 | @22 67 | idecode.o_sim_immv[22:0] 68 | @28 69 | idecode.o_wF 70 | idecode.o_wR 71 | idecode.o_zI 72 | @22 73 | idecode.f_hidden_state[31:0] 74 | idecode.f_insn_word[31:0] 75 | @28 76 | idecode.f_last_insn 77 | idecode.f_new_insn 78 | idecode.f_past_valid 79 | @22 80 | idecode.f_result[127:0] 81 | idecode.f_this_pipe_I[20:0] 82 | @28 83 | idecode.fc_ALU 84 | idecode.fc_DV 85 | idecode.fc_FP 86 | @22 87 | idecode.fc_I[31:0] 88 | @28 89 | idecode.fc_M 90 | idecode.fc_break 91 | @22 92 | idecode.fc_cond[3:0] 93 | idecode.fc_dcdA[6:0] 94 | idecode.fc_dcdB[6:0] 95 | idecode.fc_dcdR[6:0] 96 | @28 97 | idecode.fc_illegal 98 | idecode.fc_lock 99 | @22 100 | idecode.fc_op[3:0] 101 | @28 102 | idecode.fc_rA 103 | idecode.fc_rB 104 | idecode.fc_sim 105 | @22 106 | idecode.fc_sim_immv[22:0] 107 | @28 108 | idecode.fc_wF 109 | idecode.fc_wR 110 | idecode.pf_valid 111 | @22 112 | idecode.possibly_unused[5:0] 113 | idecode.r_I[22:0] 114 | @28 115 | idecode.r_valid 116 | idecode.w_ALU 117 | @22 118 | idecode.w_I[22:0] 119 | @28 120 | idecode.w_Iz 121 | idecode.w_add 122 | idecode.w_break 123 | idecode.w_brev 124 | @22 125 | idecode.w_cis_op[4:0] 126 | @28 127 | idecode.w_cmptst 128 | @22 129 | idecode.w_cond[3:0] 130 | idecode.w_dcdA[4:0] 131 | @28 132 | idecode.w_dcdA_cc 133 | idecode.w_dcdA_pc 134 | @22 135 | idecode.w_dcdB[4:0] 136 | @28 137 | idecode.w_dcdB_cc 138 | idecode.w_dcdB_pc 139 | @22 140 | idecode.w_dcdR[4:0] 141 | @28 142 | idecode.w_dcdR_cc 143 | idecode.w_dcdR_pc 144 | idecode.w_div 145 | idecode.w_fpu 146 | @22 147 | idecode.w_fullI[22:0] 148 | @28 149 | idecode.w_ldi 150 | idecode.w_ldilo 151 | idecode.w_ljmp 152 | idecode.w_ljmp_dly 153 | idecode.w_lock 154 | idecode.w_mem 155 | idecode.w_mov 156 | idecode.w_mpy 157 | idecode.w_noop 158 | @22 159 | idecode.w_op[4:0] 160 | @28 161 | idecode.w_rA 162 | idecode.w_rB 163 | idecode.w_sim 164 | idecode.w_special 165 | idecode.w_sto 166 | idecode.w_wF 167 | idecode.w_wR 168 | idecode.w_wR_n 169 | [pattern_trace] 1 170 | [pattern_trace] 0 171 | -------------------------------------------------------------------------------- /bench/formal/idecode.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | pipe_div_mpy_cis_opipe pipelind div mpy cis pipemem 3 | pipe_div_mpy_cis_nopipe pipelind div mpy cis nopipemem 4 | pipe_div_mpy_nocis_pipe pipelind div mpy nocis pipemem 5 | pipe_div_mpy_nocis_nopipe pipelind div mpy nocis nopipemem 6 | pipe_div_nompy_nocis_nopipe pipelind div nompy nocis nopipemem 7 | pipe_nodiv_nompy_nocis_nopipe pipelind nodiv nompy nocis nopipemem 8 | nopipe_nodiv_nompy_nocis_nopipe nopipelind nodiv nompy nocis nopipemem 9 | 10 | [options] 11 | mode prove 12 | depth 10 13 | 14 | [engines] 15 | smtbmc 16 | 17 | [script] 18 | read -formal -D IDECODE idecode.v 19 | read -formal -D IDECODE f_idecode.v 20 | --pycode-begin-- 21 | cmd = "hierarchy -top idecode" 22 | cmd += " -chparam OPT_PIPELINED %d" % (1 if "pipelind" in tags else 0) 23 | cmd += " -chparam OPT_DIVIDE %d" % (1 if "div" in tags else 0) 24 | cmd += " -chparam OPT_MPY %d" % (1 if "mpy" in tags else 0) 25 | cmd += " -chparam OPT_CIS %d" % (1 if "cis" in tags else 0) 26 | cmd += " -chparam OPT_OPIPE %d" % (1 if "pipemem" in tags else 0) 27 | output(cmd) 28 | --pycode-end-- 29 | proc -norom 30 | prep -top idecode 31 | 32 | [files] 33 | ../../rtl/core/idecode.v 34 | f_idecode.v 35 | -------------------------------------------------------------------------------- /bench/formal/memdev.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | mem 3 | extra opt_extra 4 | rom opt_rom 5 | 6 | [options] 7 | mode prove 8 | depth 5 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal fwb_slave.v 15 | read -formal memdev.v 16 | --pycode-begin-- 17 | cmd = "hierarchy -top memdev" 18 | cmd += " -chparam OPT_ROM %d " % (1 if "opt_rom" in tags else 0) 19 | cmd += " -chparam EXTRACLOCK %d " % (1 if "opt_extra" in tags else 0) 20 | output(cmd) 21 | --pycode-end-- 22 | prep 23 | 24 | [files] 25 | ../../sim/rtl/memdev.v 26 | ../../rtl/ex/fwb_slave.v 27 | -------------------------------------------------------------------------------- /bench/formal/memlogic.ys: -------------------------------------------------------------------------------- 1 | read_verilog ../../rtl/core/memops.v 2 | # read_verilog /home/dan/work/rnd/opencores/zbasic/trunk/rtl/cpu/memops.v 3 | # read_verilog ../../rtl/core/pipemem.v 4 | # read_verilog /home/dan/work/rnd/opencores/zbasic/trunk/rtl/cpu/pipemem.v 5 | synth_xilinx 6 | write_blif memops.blif 7 | -------------------------------------------------------------------------------- /bench/formal/memops.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Thu May 21 13:30:02 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1920 1021 7 | [pos] -1 -1 8 | *-3.760617 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [treeopen] memops. 10 | [sst_width] 270 11 | [signals_width] 180 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 290 14 | @28 15 | memops.i_clk 16 | memops.i_reset 17 | @200 18 | - 19 | @28 20 | memops.i_stb 21 | memops.o_busy 22 | memops.i_op[2:0] 23 | memops.i_lock 24 | @22 25 | memops.i_addr[31:0] 26 | memops.i_data[31:0] 27 | memops.i_oreg[4:0] 28 | @28 29 | memops.o_valid 30 | memops.o_err 31 | memops.f_done 32 | @22 33 | memops.o_wreg[4:0] 34 | memops.o_result[31:0] 35 | @200 36 | - 37 | @29 38 | memops.fmemi.i_rdbusy 39 | @200 40 | - 41 | @28 42 | memops.o_wb_cyc_gbl 43 | memops.o_wb_cyc_lcl 44 | memops.o_wb_stb_gbl 45 | memops.o_wb_stb_lcl 46 | memops.o_wb_we 47 | @22 48 | memops.o_wb_addr[29:0] 49 | memops.o_wb_data[31:0] 50 | memops.o_wb_sel[3:0] 51 | @28 52 | memops.i_wb_stall 53 | memops.i_wb_ack 54 | @22 55 | memops.i_wb_data[31:0] 56 | @28 57 | memops.i_wb_err 58 | [pattern_trace] 1 59 | [pattern_trace] 0 60 | -------------------------------------------------------------------------------- /bench/formal/memops.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr bus32 3 | prf bus32 4 | prflp prf bus32 opt_lowpower 5 | prflck prf bus32 opt_lock 6 | prflcklp prf bus32 opt_lowpower opt_lock 7 | prflcl prf bus32 opt_local 8 | prflplcl prf bus32 opt_lowpower opt_local 9 | prflcklcl prf bus32 opt_lock opt_local 10 | prflcklplcl prf bus32 opt_lowpower opt_lock opt_local 11 | prf64 prf bus64 12 | prf64lcl prf bus64 13 | prf64lp prf bus64 opt_lowpower opt_local 14 | prf64lplcl prf bus64 opt_lowpower opt_local 15 | prf128 prf bus128 16 | prf128lp prf bus128 17 | prf128lck prf bus128 op_lock 18 | prf128lcl prf bus128 opt_lowpower op_local 19 | prf128lplcl prf bus128 opt_lowpower op_local 20 | 21 | [options] 22 | prf: mode prove 23 | prf: depth 3 24 | cvr: mode cover 25 | 26 | [engines] 27 | smtbmc 28 | 29 | [script] 30 | read -define MEMOPS 31 | read -formal memops.v 32 | read -formal fmem.v 33 | read -formal fwb_master.v 34 | --pycode-begin-- 35 | cmd = "hierarchy -top memops" 36 | cmd += " -chparam OPT_LOCK %d" % (1 if "opt_lock" in tags else 0) 37 | cmd += " -chparam WITH_LOCAL_BUS %d" % (1 if "opt_local" in tags else 0) 38 | cmd += " -chparam OPT_LOWPOWER %d" % (1 if "opt_lowpower" in tags else 0) 39 | cmd += " -chparam OPT_ALIGNMENT_ERR %d" % (1 if "opt_aligned" in tags else 0) 40 | if ("bus32" in tags): 41 | cmd += " -chparam BUS_WIDTH 32" 42 | elif ("bus64" in tags): 43 | cmd += " -chparam BUS_WIDTH 64" 44 | elif ("bus128" in tags): 45 | cmd += " -chparam BUS_WIDTH 128" 46 | elif ("bus256" in tags): 47 | cmd += " -chparam BUS_WIDTH 256" 48 | elif ("bus512" in tags): 49 | cmd += " -chparam BUS_WIDTH 512" 50 | output(cmd) 51 | --pycode-end-- 52 | prep -top memops 53 | 54 | [files] 55 | ../../rtl/core/memops.v 56 | ../../rtl/ex/fwb_master.v 57 | fmem.v 58 | -------------------------------------------------------------------------------- /bench/formal/pfcache.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Mon Dec 10 22:22:31 2018 4 | [*] 5 | [timestart] 0 6 | [size] 1762 600 7 | [pos] -1 -1 8 | *-4.197481 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 270 10 | [signals_width] 254 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 143 13 | @28 14 | pfcache.f_past_valid 15 | pfcache.i_reset 16 | pfcache.i_clear_cache 17 | pfcache.i_clk 18 | pfcache.i_new_pc 19 | @22 20 | pfcache.i_pc[31:0] 21 | @28 22 | pfcache.i_stall_n 23 | pfcache.o_valid 24 | pfcache.o_illegal 25 | @22 26 | pfcache.o_insn[31:0] 27 | pfcache.o_pc[31:0] 28 | @200 29 | - 30 | @28 31 | [color] 2 32 | pfcache.o_wb_cyc 33 | [color] 2 34 | pfcache.o_wb_stb 35 | [color] 2 36 | pfcache.o_wb_we 37 | @22 38 | [color] 2 39 | pfcache.o_wb_addr[29:0] 40 | [color] 2 41 | pfcache.o_wb_data[31:0] 42 | @28 43 | [color] 2 44 | pfcache.i_wb_stall 45 | [color] 2 46 | pfcache.i_wb_ack 47 | @22 48 | [color] 2 49 | pfcache.i_wb_data[31:0] 50 | @28 51 | [color] 2 52 | pfcache.i_wb_err 53 | @200 54 | - 55 | @22 56 | pfcache.f_const_addr[30:0] 57 | pfcache.f_const_insn[31:0] 58 | @28 59 | [color] 3 60 | pfcache.f_this_ack 61 | [color] 3 62 | pfcache.f_this_line 63 | [color] 3 64 | pfcache.f_this_tag 65 | @200 66 | - 67 | @28 68 | [color] 3 69 | pfcache.f_this_pc 70 | [color] 3 71 | pfcache.f_this_data 72 | [color] 3 73 | pfcache.f_this_insn 74 | @200 75 | - 76 | @22 77 | pfcache.f_nreqs[3:0] 78 | pfcache.f_nacks[3:0] 79 | pfcache.f_outstanding[3:0] 80 | @200 81 | - 82 | @28 83 | pfcache.illegal_valid 84 | @22 85 | pfcache.illegal_cache[26:0] 86 | @200 87 | - 88 | @28 89 | pfcache.delay[1:0] 90 | pfcache.bus_abort 91 | pfcache.f_next_pc_v 92 | @22 93 | pfcache.f_cpu_delay[4:0] 94 | pfcache.f_newpc_sreg[11:0] 95 | pfcache.f_next_pc[31:0] 96 | @28 97 | pfcache.isrc 98 | pfcache.last_ack 99 | pfcache.last_addr 100 | @22 101 | pfcache.lastpc[31:0] 102 | pfcache.lasttag[26:0] 103 | @28 104 | pfcache.needload 105 | @22 106 | pfcache.r_last_cache[31:0] 107 | pfcache.r_lastpc[31:0] 108 | @28 109 | pfcache.r_new_request 110 | @22 111 | pfcache.r_pc[31:0] 112 | pfcache.r_pc_cache[31:0] 113 | @28 114 | pfcache.r_v 115 | pfcache.r_v_from_last 116 | pfcache.r_v_from_pc 117 | pfcache.rvsrc 118 | pfcache.saddr[1:0] 119 | pfcache.svmask 120 | @22 121 | pfcache.tagval[24:0] 122 | pfcache.tagvalipc[24:0] 123 | pfcache.tagvallst[24:0] 124 | pfcache.valid_mask[3:0] 125 | @28 126 | pfcache.w_invalidate_result 127 | pfcache.w_v_from_last 128 | pfcache.w_v_from_pc 129 | @23 130 | pfcache.wraddr[4:0] 131 | [pattern_trace] 1 132 | [pattern_trace] 0 133 | -------------------------------------------------------------------------------- /bench/formal/pfcache.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf bus32 3 | prf64 prf bus64 4 | prf128 prf bus128 5 | cvr bus32 6 | 7 | [options] 8 | prf: mode prove 9 | prf: depth 5 10 | cvr: mode cover 11 | cvr: depth 60 12 | 13 | [engines] 14 | smtbmc 15 | 16 | [script] 17 | read -formal fwb_master.v 18 | read -formal ffetch.v 19 | read -formal -DPFCACHE pfcache.v 20 | --pycode-begin-- 21 | cmd = "hierarchy -top pfcache" 22 | if ("bus32" in tags): 23 | cmd += " -chparam BUS_WIDTH 32" 24 | elif ("bus64" in tags): 25 | cmd += " -chparam BUS_WIDTH 64" 26 | elif ("bus128" in tags): 27 | cmd += " -chparam BUS_WIDTH 128" 28 | elif ("bus256" in tags): 29 | cmd += " -chparam BUS_WIDTH 256" 30 | elif ("bus512" in tags): 31 | cmd += " -chparam BUS_WIDTH 512" 32 | output(cmd) 33 | --pycode-end-- 34 | prep -top pfcache 35 | 36 | [files] 37 | ffetch.v 38 | ../../rtl/core/pfcache.v 39 | ../../rtl/ex/fwb_master.v 40 | -------------------------------------------------------------------------------- /bench/formal/pfcache.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D PFCACHE -formal ../../rtl/core/pfcache.v 2 | read_verilog -D PFCACHE -formal ../../rtl/ex/fwb_master.v 3 | prep -top pfcache -nordff 4 | opt -share_all 5 | clean 6 | write_smt2 -wires pfcache.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/pffifo.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf insn32 bus32 3 | cvr insn32 bus32 4 | prf8b prf insn8 bus32 5 | prf8ble prf insn8 bus32 lilend 6 | prf64b prf insn32 bus64 7 | prf128b prf insn32 bus128 8 | 9 | [options] 10 | prf: mode prove 11 | prf: depth 5 12 | 13 | cvr: mode cover 14 | cvr: depth 20 15 | 16 | [engines] 17 | smtbmc 18 | 19 | [script] 20 | read -define F_PEEK 21 | read -formal fwb_master.v 22 | read -formal ffetch.v 23 | read -formal pffifo.v 24 | read -formal sfifo.v 25 | --pycode-begin-- 26 | cmd = "hierarchy -top pffifo" 27 | if ("insn8" in tags): 28 | cmd += " -chparam INSN_WIDTH 8" 29 | elif ("insn32" in tags): 30 | cmd += " -chparam INSN_WIDTH 32" 31 | if ("bus32" in tags): 32 | cmd += " -chparam BUS_WIDTH 32" 33 | elif ("bus64" in tags): 34 | cmd += " -chparam BUS_WIDTH 64" 35 | elif ("bus128" in tags): 36 | cmd += " -chparam BUS_WIDTH 128" 37 | cmd += " -chparam OPT_LITTLE_ENDIAN %d" % (1 if "lilend" in tags else 0) 38 | output(cmd) 39 | --pycode-end-- 40 | prep -top pffifo 41 | 42 | [files] 43 | ffetch.v 44 | ../../rtl/core/pffifo.v 45 | ../../rtl/ex/fwb_master.v 46 | ../../rtl/ex/sfifo.v 47 | -------------------------------------------------------------------------------- /bench/formal/pipefetch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 8 8 | prf: depth 48 9 | 10 | cvr: mode cover 11 | cvr: depth 8 12 | 13 | [engines] 14 | smtbmc 15 | 16 | [script] 17 | read -formal fwb_master.v 18 | read -formal ffetch.v 19 | read -formal pipefetch.v 20 | prep -top pipefetch 21 | 22 | [files] 23 | ffetch.v 24 | ../../rtl/core/pipefetch.v 25 | ../../rtl/ex/fwb_master.v 26 | -------------------------------------------------------------------------------- /bench/formal/pipemem.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI 3 | [*] Wed Jun 10 11:33:14 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1920 1021 7 | [pos] -919 -417 8 | *-4.075490 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 270 10 | [signals_width] 180 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 290 13 | @28 14 | pipemem.i_clk 15 | pipemem.i_reset 16 | @200 17 | - 18 | @28 19 | pipemem.i_pipe_stb 20 | pipemem.o_pipe_stalled 21 | @22 22 | pipemem.i_addr[31:0] 23 | pipemem.i_data[31:0] 24 | @28 25 | pipemem.i_lock 26 | pipemem.i_op[2:0] 27 | @22 28 | pipemem.i_oreg[4:0] 29 | @28 30 | pipemem.o_busy 31 | pipemem.o_valid 32 | @22 33 | pipemem.o_wreg[4:0] 34 | pipemem.o_result[31:0] 35 | @28 36 | pipemem.o_err 37 | @200 38 | - 39 | @28 40 | pipemem.o_wb_cyc_gbl 41 | pipemem.o_wb_stb_gbl 42 | pipemem.o_wb_cyc_lcl 43 | pipemem.o_wb_stb_lcl 44 | @22 45 | pipemem.o_wb_addr[29:0] 46 | pipemem.o_wb_data[31:0] 47 | pipemem.o_wb_sel[3:0] 48 | @28 49 | pipemem.o_wb_we 50 | @29 51 | pipemem.i_wb_stall 52 | pipemem.i_wb_ack 53 | @23 54 | pipemem.i_wb_data[31:0] 55 | @29 56 | pipemem.i_wb_err 57 | @201 58 | - 59 | @28 60 | pipemem.r_wb_cyc_gbl 61 | pipemem.r_wb_cyc_lcl 62 | pipemem.misaligned 63 | [pattern_trace] 1 64 | [pattern_trace] 0 65 | -------------------------------------------------------------------------------- /bench/formal/pipemem.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf bus32 nolocal_bus alignment_err nolock 3 | prflck prf bus32 nolocal_bus alignment_err lock 4 | prflcl prf bus32 local_bus alignment_err nolock 5 | prflcllck prf bus32 local_bus alignment_err lock 6 | lcl_noaligned_lock prf bus32 local_bus noalignment_err lock 7 | lcl_noaligned_nolock prf bus32 local_bus noalignment_err nolock 8 | nolcl_noaligned_lock prf bus32 nolocal_bus noalignment_err lock 9 | nolcl_noaligned_nolock prf bus32 nolocal_bus noalignment_err nolock 10 | prf64 prf bus64 nolocal_bus alignment_err nolock 11 | prf128 prf bus128 nolocal_bus alignment_err nolock 12 | 13 | [options] 14 | prf: mode prove 15 | depth 4 16 | bus64: depth 16 17 | 18 | [engines] 19 | smtbmc 20 | 21 | [script] 22 | read -formal -DPIPEMEM fwb_master.v 23 | read -formal -DPIPEMEM fmem.v 24 | read -formal -DPIPEMEM pipemem.v 25 | --pycode-begin-- 26 | cmd = "hierarchy -top pipemem" 27 | cmd += " -chparam WITH_LOCAL_BUS %d" % (1 if "local_bus" in tags else 0) 28 | cmd += " -chparam OPT_ALIGNMENT_ERR %d" % (1 if "alignment_err" in tags else 0) 29 | cmd += " -chparam OPT_LOCK %d" % (1 if "lock" in tags else 0) 30 | if ("bus32" in tags): 31 | cmd += " -chparam BUS_WIDTH 32" 32 | elif ("bus64" in tags): 33 | cmd += " -chparam BUS_WIDTH 64" 34 | elif ("bus128" in tags): 35 | cmd += " -chparam BUS_WIDTH 128" 36 | output(cmd) 37 | --pycode-end-- 38 | prep -top pipemem 39 | 40 | [files] 41 | fmem.v 42 | ../../rtl/core/pipemem.v 43 | ../../rtl/ex/fwb_master.v 44 | -------------------------------------------------------------------------------- /bench/formal/pipemem.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D PIPEMEM -formal ../../rtl/core/pipemem.v 2 | read_verilog -D PIPEMEM -formal ../../rtl/ex/fwb_master.v 3 | prep -top pipemem -nordff 4 | opt -share_all 5 | write_smt2 -wires pipemem.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/prefetch.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Mon Jul 13 18:59:11 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1396 600 7 | [pos] -397 -1 8 | *-3.909014 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 9 | [sst_width] 196 10 | [signals_width] 150 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 155 13 | @28 14 | prefetch.i_clk 15 | prefetch.i_reset 16 | @200 17 | - 18 | @28 19 | prefetch.i_new_pc 20 | prefetch.i_clear_cache 21 | @22 22 | prefetch.i_pc[31:0] 23 | @28 24 | prefetch.i_stalled_n 25 | prefetch.o_valid 26 | prefetch.o_illegal 27 | @22 28 | prefetch.o_insn[31:0] 29 | prefetch.o_pc[31:0] 30 | @200 31 | - 32 | @28 33 | prefetch.o_wb_cyc 34 | prefetch.o_wb_stb 35 | prefetch.o_wb_we 36 | @22 37 | prefetch.o_wb_addr[29:0] 38 | prefetch.o_wb_data[31:0] 39 | @29 40 | prefetch.i_wb_stall 41 | @28 42 | prefetch.i_wb_ack 43 | @22 44 | prefetch.i_wb_data[31:0] 45 | @28 46 | prefetch.i_wb_err 47 | [pattern_trace] 1 48 | [pattern_trace] 0 49 | -------------------------------------------------------------------------------- /bench/formal/prefetch.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf insn32 bus32 3 | prf8b prf insn8 bus32 4 | prf8ble prf insn8 bus32 lilend 5 | prf64b prf insn32 bus64 6 | prf128b prf insn32 bus128 7 | 8 | [options] 9 | prf: mode prove 10 | depth 8 11 | prf128b: depth 14 12 | 13 | [engines] 14 | smtbmc 15 | 16 | [script] 17 | read -formal fwb_master.v 18 | read -formal ffetch.v 19 | read -formal -DPREFETCH prefetch.v 20 | --pycode-begin-- 21 | cmd = "hierarchy -top prefetch" 22 | if ("insn8" in tags): 23 | cmd += " -chparam INSN_WIDTH 8" 24 | elif ("insn32" in tags): 25 | cmd += " -chparam INSN_WIDTH 32" 26 | if ("bus32" in tags): 27 | cmd += " -chparam DATA_WIDTH 32" 28 | elif ("bus64" in tags): 29 | cmd += " -chparam DATA_WIDTH 64" 30 | elif ("bus128" in tags): 31 | cmd += " -chparam DATA_WIDTH 128" 32 | cmd += " -chparam OPT_LITTLE_ENDIAN %d" % (1 if "lilend" in tags else 0) 33 | output(cmd) 34 | --pycode-end-- 35 | prep -top prefetch 36 | 37 | [files] 38 | ffetch.v 39 | ../../rtl/core/prefetch.v 40 | ../../rtl/ex/fwb_master.v 41 | -------------------------------------------------------------------------------- /bench/formal/prefetch.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D PREFETCH -formal ../../rtl/ex/fwb_master.v 2 | read_verilog -D PREFETCH -formal ../../rtl/core/prefetch.v 3 | prep -top prefetch -nordff 4 | opt -share_all 5 | write_smt2 -wires prefetch.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/wbdblpriarb.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 4 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal -D WBDBLPRIARB wbdblpriarb.v 13 | read -formal -D WBDBLPRIARB fwb_master.v 14 | read -formal -D WBDBLPRIARB fwb_slave.v 15 | prep -top wbdblpriarb 16 | 17 | [files] 18 | ../../rtl/ex/wbdblpriarb.v 19 | ../../rtl/ex/fwb_master.v 20 | ../../rtl/ex/fwb_slave.v 21 | -------------------------------------------------------------------------------- /bench/formal/wbdblpriarb.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D WBDBLPRIARB -formal ../../rtl/ex/wbdblpriarb.v 2 | read_verilog -D WBDBLPRIARB -formal ../../rtl/ex/fwb_master.v 3 | read_verilog -D WBDBLPRIARB -formal ../../rtl/ex/fwb_slave.v 4 | prep -top wbdblpriarb -nordff 5 | opt -share_all 6 | write_smt2 -wires wbdblpriarb.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/wbdmac.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf bus32 3 | prf64 prf bus64 4 | prf128 prf bus128 5 | 6 | [options] 7 | prf: mode prove 8 | depth 12 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal wbdmac.v 15 | read -formal fwb_master.v 16 | read -formal fwb_slave.v 17 | --pycode-begin-- 18 | cmd = "hierarchy -top wbdmac" 19 | if ("bus32" in tags): 20 | cmd += " -chparam BUS_WIDTH 32" 21 | elif ("bus64" in tags): 22 | cmd += " -chparam BUS_WIDTH 64" 23 | elif ("bus128" in tags): 24 | cmd += " -chparam BUS_WIDTH 128" 25 | output(cmd) 26 | --pycode-end-- 27 | prep -top wbdmac 28 | 29 | [files] 30 | ../../rtl/peripherals/wbdmac.v 31 | ../../rtl/ex/fwb_master.v 32 | ../../rtl/ex/fwb_slave.v 33 | -------------------------------------------------------------------------------- /bench/formal/wbdmac.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D WBDMAC -formal ../../rtl/peripherals/wbdmac.v 2 | read_verilog -D WBDMAC -formal ../../rtl/ex/fwb_master.v 3 | read_verilog -D WBDMAC -formal ../../rtl/ex/fwb_slave.v 4 | prep -top wbdmac -nordff 5 | opt -share_all 6 | write_smt2 -wires wbdmac.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/wbpriarbiter.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 5 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal -D WBPRIARBITER wbpriarbiter.v 13 | read -formal -D WBPRIARBITER fwb_master.v 14 | read -formal -D WBPRIARBITER fwb_slave.v 15 | prep -top wbpriarbiter 16 | 17 | [files] 18 | ../../rtl/ex/wbpriarbiter.v 19 | ../../rtl/ex/fwb_master.v 20 | ../../rtl/ex/fwb_slave.v 21 | 22 | -------------------------------------------------------------------------------- /bench/formal/wbpriarbiter.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D WBPRIARBITER -formal ../../rtl/ex/wbpriarbiter.v 2 | read_verilog -D WBPRIARBITER -formal ../../rtl/ex/fwb_master.v 3 | read_verilog -D WBPRIARBITER -formal ../../rtl/ex/fwb_slave.v 4 | prep -top wbpriarbiter -nordff 5 | opt -share_all 6 | write_smt2 -wires wbpriarbiter.smt2 7 | -------------------------------------------------------------------------------- /bench/formal/wbwatchdog.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 5 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal wbwatchdog.v 13 | read -formal fwb_slave.v 14 | prep -top wbwatchdog 15 | 16 | 17 | [files] 18 | ../../rtl/peripherals/wbwatchdog.v 19 | ../../rtl/ex/fwb_slave.v 20 | -------------------------------------------------------------------------------- /bench/formal/wbwatchdog.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPTIMER -formal ../../rtl/peripherals/wbwatchdog.v 2 | prep -top wbwatchdog -nordff 3 | opt -share_all 4 | write_smt2 -wires wbwatchdog.smt2 5 | -------------------------------------------------------------------------------- /bench/formal/zipaxi.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | # cvr 4 | 5 | [options] 6 | prf: mode prove 7 | # cvr: mode cover 8 | depth 10 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal zipaxi.v 15 | read -formal fdebug.v 16 | read -formal skidbuffer.v 17 | # read -formal axilfetch.v 18 | read -formal faxil_slave.v 19 | hierarchy -top zipaxi -chparam OPT_CLKGATE 0 20 | prep -top zipaxi 21 | 22 | [files] 23 | ../../rtl/zipaxi.v 24 | ../../rtl/ex/skidbuffer.v 25 | faxil_slave.v 26 | fdebug.v 27 | -------------------------------------------------------------------------------- /bench/formal/zipaxil.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | # cvr 4 | 5 | [options] 6 | prf: mode prove 7 | # cvr: mode cover 8 | depth 10 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal zipaxil.v 15 | read -formal fdebug.v 16 | read -formal skidbuffer.v 17 | # read -formal axilfetch.v 18 | read -formal faxil_slave.v 19 | prep -top zipaxil 20 | 21 | [files] 22 | ../../rtl/zipaxil.v 23 | ../../rtl/ex/skidbuffer.v 24 | faxil_slave.v 25 | fdebug.v 26 | -------------------------------------------------------------------------------- /bench/formal/zipbones.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Tue Nov 17 20:36:17 2020 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1625 600 8 | [pos] -1 -1 9 | *-4.190785 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [treeopen] zipbones. 11 | [sst_width] 196 12 | [signals_width] 190 13 | [sst_expanded] 1 14 | [sst_vpaned_height] 155 15 | @28 16 | zipbones.i_reset 17 | zipbones.i_clk 18 | zipbones.cmd_reset 19 | @c00200 20 | -Debug interface 21 | @28 22 | zipbones.i_dbg_cyc 23 | zipbones.i_dbg_stb 24 | zipbones.i_dbg_we 25 | @22 26 | zipbones.i_dbg_addr[5:0] 27 | zipbones.i_dbg_data[31:0] 28 | zipbones.i_dbg_sel[3:0] 29 | @28 30 | zipbones.o_dbg_stall 31 | zipbones.o_dbg_ack 32 | @c00022 33 | zipbones.o_dbg_data[31:0] 34 | @28 35 | (0)zipbones.o_dbg_data[31:0] 36 | (1)zipbones.o_dbg_data[31:0] 37 | (2)zipbones.o_dbg_data[31:0] 38 | (3)zipbones.o_dbg_data[31:0] 39 | (4)zipbones.o_dbg_data[31:0] 40 | (5)zipbones.o_dbg_data[31:0] 41 | (6)zipbones.o_dbg_data[31:0] 42 | (7)zipbones.o_dbg_data[31:0] 43 | (8)zipbones.o_dbg_data[31:0] 44 | (9)zipbones.o_dbg_data[31:0] 45 | (10)zipbones.o_dbg_data[31:0] 46 | (11)zipbones.o_dbg_data[31:0] 47 | (12)zipbones.o_dbg_data[31:0] 48 | (13)zipbones.o_dbg_data[31:0] 49 | (14)zipbones.o_dbg_data[31:0] 50 | (15)zipbones.o_dbg_data[31:0] 51 | (16)zipbones.o_dbg_data[31:0] 52 | (17)zipbones.o_dbg_data[31:0] 53 | (18)zipbones.o_dbg_data[31:0] 54 | (19)zipbones.o_dbg_data[31:0] 55 | (20)zipbones.o_dbg_data[31:0] 56 | (21)zipbones.o_dbg_data[31:0] 57 | (22)zipbones.o_dbg_data[31:0] 58 | (23)zipbones.o_dbg_data[31:0] 59 | (24)zipbones.o_dbg_data[31:0] 60 | (25)zipbones.o_dbg_data[31:0] 61 | (26)zipbones.o_dbg_data[31:0] 62 | (27)zipbones.o_dbg_data[31:0] 63 | (28)zipbones.o_dbg_data[31:0] 64 | (29)zipbones.o_dbg_data[31:0] 65 | (30)zipbones.o_dbg_data[31:0] 66 | (31)zipbones.o_dbg_data[31:0] 67 | @1401200 68 | -group_end 69 | -Debug interface 70 | @28 71 | zipbones.i_ext_int 72 | zipbones.o_ext_int 73 | @c00200 74 | -Wishbone (unused) 75 | @28 76 | zipbones.o_wb_cyc 77 | zipbones.o_wb_stb 78 | zipbones.o_wb_we 79 | @22 80 | zipbones.o_wb_addr[29:0] 81 | zipbones.o_wb_data[31:0] 82 | zipbones.o_wb_sel[3:0] 83 | @28 84 | zipbones.i_wb_stall 85 | zipbones.i_wb_ack 86 | @22 87 | zipbones.i_wb_data[31:0] 88 | @28 89 | zipbones.i_wb_err 90 | @1401200 91 | -Wishbone (unused) 92 | @28 93 | zipbones.cpu_break 94 | zipbones.f_cpu_break 95 | zipbones.cmd_halt 96 | zipbones.cpu_halt 97 | zipbones.cmd_clear_cache 98 | @29 99 | zipbones.fdbg.i_dbg_we 100 | [pattern_trace] 1 101 | [pattern_trace] 0 102 | -------------------------------------------------------------------------------- /bench/formal/zipbones.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | # cvr 4 | 5 | [options] 6 | prf: mode prove 7 | # cvr: mode cover 8 | depth 10 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal zipbones.v 15 | read -formal fdebug.v 16 | read -formal fwb_slave.v 17 | prep -top zipbones 18 | 19 | [files] 20 | ../../rtl/zipbones.v 21 | ../../rtl/ex/fwb_slave.v 22 | fdebug.v 23 | -------------------------------------------------------------------------------- /bench/formal/zipcore.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Tue Nov 17 13:00:10 2020 4 | [*] 5 | [timestart] 0 6 | [size] 1221 600 7 | [treeopen] zipcore. 8 | [treeopen] zipcore.instruction_decoder. 9 | [sst_width] 196 10 | [signals_width] 222 11 | [sst_expanded] 1 12 | [sst_vpaned_height] 155 13 | @800200 14 | -External Inputs 15 | @28 16 | [color] 2 17 | zipcore.i_reset 18 | [color] 2 19 | zipcore.i_clk 20 | [color] 2 21 | zipcore.i_halt 22 | @22 23 | [color] 2 24 | zipcore.i_dbg_data[31:0] 25 | [color] 2 26 | zipcore.i_dbg_reg[4:0] 27 | @28 28 | [color] 2 29 | zipcore.i_dbg_we 30 | @22 31 | [color] 2 32 | zipcore.ipc[31:0] 33 | @28 34 | [color] 2 35 | zipcore.i_interrupt 36 | zipcore.o_dbg_stall 37 | @29 38 | zipcore.o_dbg_cc[2:0] 39 | @23 40 | zipcore.o_dbg_reg[31:0] 41 | @1000200 42 | -External Inputs 43 | @c00200 44 | -CE 45 | @28 46 | zipcore.dcd_ce 47 | zipcore.op_ce 48 | zipcore.master_ce 49 | zipcore.adf_ce_unconditional 50 | zipcore.alu_ce 51 | zipcore.div_ce 52 | zipcore.fpu_ce 53 | zipcore.mem_ce 54 | zipcore.o_mem_ce 55 | @1401200 56 | -CE 57 | @c00200 58 | -Valid 59 | @28 60 | zipcore.i_pf_valid 61 | zipcore.dcd_valid 62 | zipcore.w_op_valid 63 | zipcore.op_valid 64 | zipcore.op_valid_alu 65 | zipcore.op_valid_div 66 | zipcore.op_valid_fpu 67 | zipcore.op_valid_mem 68 | zipcore.div_valid 69 | zipcore.alu_valid 70 | zipcore.i_mem_valid 71 | zipcore.mem_pc_valid 72 | zipcore.alu_pc_valid 73 | @1401200 74 | -Valid 75 | @c00200 76 | -Stall 77 | @28 78 | zipcore.dcd_A_stall 79 | zipcore.dcd_B_stall 80 | zipcore.dcd_F_stall 81 | zipcore.dcd_stalled 82 | zipcore.op_stall 83 | zipcore.master_stall 84 | zipcore.alu_stall 85 | zipcore.mem_stalled 86 | zipcore.i_mem_pipe_stalled 87 | @1401200 88 | -Stall 89 | @c00200 90 | -Busy 91 | @28 92 | zipcore.alu_busy 93 | zipcore.div_busy 94 | zipcore.i_mem_busy 95 | zipcore.i_mem_rdbusy 96 | @22 97 | zipcore.f_mem_outstanding[3:0] 98 | @1401200 99 | -Busy 100 | @800200 101 | -f_instruction 102 | @22 103 | zipcore.f_dcd_insn_word[31:0] 104 | zipcore.f_op_insn_word[31:0] 105 | zipcore.f_alu_insn_word[31:0] 106 | @1000200 107 | -f_instruction 108 | @c00200 109 | -Prefetch 110 | @22 111 | zipcore.pf_pc[31:0] 112 | @1401200 113 | -Prefetch 114 | @22 115 | zipcore.op_opn[3:0] 116 | zipcore.op_Aid[4:0] 117 | zipcore.op_Bid[4:0] 118 | @28 119 | zipcore.f_op_branch 120 | zipcore.dcd_early_branch 121 | zipcore.dcd_early_branch_stb 122 | @22 123 | zipcore.dcd_opn[3:0] 124 | @28 125 | zipcore.instruction_decoder.w_noop 126 | zipcore.instruction_decoder.w_special 127 | zipcore.instruction_decoder.w_cis_ljmp 128 | zipcore.instruction_decoder.w_div 129 | @22 130 | zipcore.instruction_decoder.w_cis_op[4:0] 131 | @28 132 | zipcore.instruction_decoder.w_cmptst 133 | zipcore.instruction_decoder.o_illegal 134 | @22 135 | zipcore.instruction_decoder.w_dcdA[4:0] 136 | @28 137 | zipcore.dcd_illegal 138 | zipcore.op_illegal 139 | zipcore.alu_illegal 140 | zipcore.pending_sreg_write 141 | zipcore.clear_pipeline 142 | zipcore.op_wR 143 | zipcore.set_cond 144 | zipcore.alu_wR 145 | zipcore.dcd_gie 146 | zipcore.gie 147 | zipcore.ill_err_i 148 | zipcore.alu_illegal 149 | zipcore.clear_pipeline 150 | zipcore.new_pc 151 | zipcore.wr_reg_ce 152 | @22 153 | zipcore.wr_reg_id[4:0] 154 | [pattern_trace] 1 155 | [pattern_trace] 0 156 | -------------------------------------------------------------------------------- /bench/formal/zipcore.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | piped prf lock pipelined mpy div cis pipelined earlybranching 3 | pipedbk prf lock pipelined mpy div cis pipelined earlybranching bkregs 4 | nopipe prf lock nopipe cis 5 | lowlogic prf lock nopipe 6 | ice40 prf lock nopipe mpy div cis bkregs 7 | 8 | pipedlp piped prf lock pipelined mpy div cis earlybranching opt_lowpower 9 | nopipelp nopipe prf lock nopipe cis opt_lowpower 10 | lowlogiclp lowlogic prf lock nopipe opt_lowpower 11 | 12 | pipedlpck piped prf lock pipelined mpy div cis earlybranching opt_lowpower opt_ckgate 13 | pipedlpckh piped prf lock pipelined mpy div cis earlybranching opt_lowpower opt_halted opt_ckgate 14 | pipedckh piped prf lock pipelined mpy div cis earlybranching opt_halted opt_ckgate 15 | lowlogiclpck lowlogic prf lock nopipe opt_lowpower opt_ckgate 16 | lowlogiclpckh lowlogic prf lock nopipe opt_lowpower opt_ckgate opt_halted 17 | 18 | cvr lock pipelined mpy div cis earlybranching opt_lock 19 | 20 | [options] 21 | prf: mode prove 22 | cvr: mode cover 23 | depth 18 24 | piped: depth 5 25 | nopipe: depth 4 26 | lowlogic: depth 4 27 | ice40: depth 5 28 | pipedbk: depth 5 29 | cvr: depth 35 30 | 31 | [engines] 32 | smtbmc boolector 33 | 34 | [script] 35 | read -define -DZIPCPU 36 | # 37 | read -formal -D ZIPCPU cpuops.v 38 | read -formal -D ZIPCPU fmem.v 39 | read -formal -D ZIPCPU iscachable.v 40 | read -formal -D ZIPCPU idecode.v 41 | # 42 | read -formal -D ZIPCPU f_idecode.v 43 | read -formal -D ZIPCPU ffetch.v 44 | read -formal -D ZIPCPU abs_div.v 45 | read -formal -D ZIPCPU abs_mpy.v 46 | read -formal -D ZIPCPU fdebug.v 47 | # 48 | read -formal zipcore.v 49 | --pycode-begin-- 50 | cmd = "hierarchy -top zipcore" 51 | cmd += " -chparam IMPLEMENT_FPU 0" 52 | cmd += " -chparam OPT_LOCK %d" % ( 1 if "lock" in tags else 0) 53 | cmd += " -chparam OPT_MPY %d" % ( 1 if "mpy" in tags else 0) 54 | cmd += " -chparam OPT_DIV %d" % ( 1 if "div" in tags else 0) 55 | cmd += " -chparam OPT_CIS %d" % ( 1 if "cis" in tags else 0) 56 | cmd += " -chparam OPT_PIPELINED %d" % ( 1 if "pipelined" in tags else 0) 57 | cmd += " -chparam OPT_EARLY_BRANCHING %d" % ( 1 if "earlybranching" in tags else 0) 58 | cmd += " -chparam OPT_LOWPOWER %d" % ( 1 if "opt_lowpower" in tags else 0) 59 | cmd += " -chparam OPT_CLKGATE %d" % ( 1 if "opt_ckgate" in tags else 0) 60 | cmd += " -chparam OPT_START_HALTED %d" % (1 if "opt_halted" in tags else 0) 61 | cmd += " -chparam OPT_DISTRIBUTED_REGS %d" % (0 if "bkregs" in tags else 1) 62 | output(cmd) 63 | --pycode-end-- 64 | proc -norom 65 | prep -top zipcore 66 | 67 | [files] 68 | ../../rtl/core/zipcore.v 69 | ../../rtl/core/cpuops.v 70 | ../../rtl/core/iscachable.v 71 | ../../rtl/core/idecode.v 72 | ../../rtl/ex/wbdblpriarb.v 73 | # 74 | ../../rtl/ex/fwb_counter.v 75 | ../../rtl/ex/fwb_master.v 76 | ../../rtl/ex/fwb_slave.v 77 | # 78 | f_idecode.v 79 | ffetch.v 80 | fmem.v 81 | fdebug.v 82 | abs_div.v 83 | abs_mpy.v 84 | # 85 | -------------------------------------------------------------------------------- /bench/formal/zipcounter.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 5 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal -DZIPCOUNTER zipcounter.v 13 | read -formal -DZIPCOUNTER fwb_slave.v 14 | prep -top zipcounter 15 | 16 | [files] 17 | ../../rtl/peripherals/zipcounter.v 18 | ../../rtl/ex/fwb_slave.v 19 | -------------------------------------------------------------------------------- /bench/formal/zipcounter.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPCOUNTER -formal ../../rtl/peripherals/zipcounter.v 2 | read_verilog -D ZIPCOUNTER -formal ../../rtl/ex/fwb_slave.v 3 | prep -top zipcounter -nordff 4 | opt -share_all 5 | write_smt2 -wires zipcounter.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/zipcpu.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/core/zipcpu.v 2 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/core/cpuops.v 3 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/core/memops.v 4 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/core/pipemem.v 5 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/core/idecode.v 6 | read_verilog -D ZIPCPU -I ../../rtl -formal ../../rtl/ex/wbdblpriarb.v 7 | # 8 | read_verilog -D ZIPCPU -formal ../../rtl/ex/fwb_counter.v 9 | read_verilog -D ZIPCPU -formal ../../rtl/ex/fwb_master.v 10 | read_verilog -D ZIPCPU -formal ../../rtl/ex/fwb_slave.v 11 | read_verilog -D ZIPCPU -formal f_idecode.v 12 | read_verilog -D ZIPCPU -formal abs_prefetch.v 13 | read_verilog -D ZIPCPU -formal abs_div.v 14 | read_verilog -D ZIPCPU -formal abs_mpy.v 15 | # 16 | prep -top zipcpu -nordff 17 | opt -share_all 18 | clean 19 | write_smt2 -wires zipcpu.smt2 20 | -------------------------------------------------------------------------------- /bench/formal/zipdma_mm2s.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | cvr: mode cover 8 | prf: depth 10 9 | prf: depth 5 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal zipdma_mm2s.v 16 | read -formal fwb_master.v 17 | --pycode-begin-- 18 | cmd = "hierarchy -top zipdma_mm2s" 19 | output(cmd) 20 | --pycode-end-- 21 | prep -top zipdma_mm2s 22 | 23 | [files] 24 | ../../rtl/ex/fwb_master.v 25 | ../../rtl/zipdma/zipdma_mm2s.v 26 | -------------------------------------------------------------------------------- /bench/formal/zipdma_rxgears.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Fri Aug 26 01:42:34 2022 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1455 600 8 | [pos] -1 -1 9 | *-5.294694 41 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 296 11 | [signals_width] 142 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 160 14 | @28 15 | zipdma_rxgears.i_clk 16 | zipdma_rxgears.i_reset 17 | zipdma_rxgears.S_VALID 18 | zipdma_rxgears.S_READY 19 | @22 20 | zipdma_rxgears.S_DATA[63:0] 21 | zipdma_rxgears.S_BYTES[3:0] 22 | @28 23 | zipdma_rxgears.S_LAST 24 | @200 25 | - 26 | @28 27 | zipdma_rxgears.M_VALID 28 | zipdma_rxgears.M_READY 29 | @22 30 | zipdma_rxgears.M_DATA[63:0] 31 | zipdma_rxgears.M_BYTES[3:0] 32 | @28 33 | zipdma_rxgears.M_LAST 34 | @200 35 | - 36 | @28 37 | zipdma_rxgears.r_last 38 | @22 39 | zipdma_rxgears.next_fill[4:0] 40 | zipdma_rxgears.fill[4:0] 41 | @23 42 | zipdma_rxgears.f_rcvd[15:0] 43 | [pattern_trace] 1 44 | [pattern_trace] 0 45 | -------------------------------------------------------------------------------- /bench/formal/zipdma_rxgears.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfw prf bus64 4 | cvr 5 | 6 | [options] 7 | prf: mode prove 8 | prf: depth 4 9 | cvr: mode cover 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal zipdma_rxgears.v 16 | --pycode-begin-- 17 | cmd = "hierarchy -top zipdma_rxgears" 18 | if ("bus64" in tags): 19 | cmd += " -chparam BUS_WIDTH 64" 20 | else: 21 | cmd += " -chparam BUS_WIDTH 32" 22 | output(cmd) 23 | --pycode-end-- 24 | prep -top zipdma_rxgears 25 | 26 | [files] 27 | ../../rtl/zipdma/zipdma_rxgears.v 28 | -------------------------------------------------------------------------------- /bench/formal/zipdma_s2mm.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Sep 28 13:00:52 2022 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1917 850 8 | [pos] -1 -1 9 | *-5.157785 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 362 11 | [signals_width] 198 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 244 14 | @28 15 | zipdma_s2mm.i_clk 16 | zipdma_s2mm.i_reset 17 | @c00200 18 | -Config 19 | @28 20 | zipdma_s2mm.i_inc 21 | zipdma_s2mm.i_request 22 | @22 23 | zipdma_s2mm.i_addr[29:0] 24 | @28 25 | zipdma_s2mm.i_size[1:0] 26 | zipdma_s2mm.o_busy 27 | [color] 1 28 | zipdma_s2mm.o_err 29 | @200 30 | - 31 | @28 32 | zipdma_s2mm.r_inc 33 | zipdma_s2mm.r_size[1:0] 34 | @22 35 | zipdma_s2mm.r_addr[29:0] 36 | @1401200 37 | -Config 38 | @800201 39 | -AXI-Stream 40 | @29 41 | zipdma_s2mm.S_VALID 42 | zipdma_s2mm.S_READY 43 | @23 44 | zipdma_s2mm.S_DATA[63:0] 45 | zipdma_s2mm.S_BYTES[3:0] 46 | @29 47 | zipdma_s2mm.S_LAST 48 | @201 49 | - 50 | @29 51 | zipdma_s2mm.r_last 52 | @1000201 53 | -AXI-Stream 54 | @800200 55 | -Wishbone 56 | @28 57 | zipdma_s2mm.o_wr_cyc 58 | zipdma_s2mm.o_wr_stb 59 | @22 60 | zipdma_s2mm.o_wr_addr[26:0] 61 | zipdma_s2mm.o_wr_data[63:0] 62 | zipdma_s2mm.o_wr_sel[7:0] 63 | @28 64 | zipdma_s2mm.i_wr_stall 65 | zipdma_s2mm.i_wr_ack 66 | zipdma_s2mm.i_wr_err 67 | @200 68 | - 69 | @22 70 | zipdma_s2mm.r_data[63:0] 71 | zipdma_s2mm.r_sel[7:0] 72 | @28 73 | zipdma_s2mm.subaddr[2:0] 74 | @1000200 75 | -Wishbone 76 | @22 77 | zipdma_s2mm.fwb_addr[30:0] 78 | @200 79 | - 80 | @22 81 | zipdma_s2mm.fc_posn[30:0] 82 | @c00022 83 | zipdma_s2mm.fc_byte[7:0] 84 | @28 85 | (0)zipdma_s2mm.fc_byte[7:0] 86 | (1)zipdma_s2mm.fc_byte[7:0] 87 | (2)zipdma_s2mm.fc_byte[7:0] 88 | (3)zipdma_s2mm.fc_byte[7:0] 89 | (4)zipdma_s2mm.fc_byte[7:0] 90 | (5)zipdma_s2mm.fc_byte[7:0] 91 | (6)zipdma_s2mm.fc_byte[7:0] 92 | (7)zipdma_s2mm.fc_byte[7:0] 93 | @1401200 94 | -group_end 95 | @200 96 | - 97 | @28 98 | [color] 3 99 | zipdma_s2mm.fin_check 100 | zipdma_s2mm.f_shift[2:0] 101 | @22 102 | zipdma_s2mm.f_posn[30:0] 103 | zipdma_s2mm.fc_partial[63:0] 104 | @200 105 | - 106 | @28 107 | [color] 3 108 | zipdma_s2mm.fwb_check 109 | @22 110 | zipdma_s2mm.fwb_posn[30:0] 111 | @28 112 | zipdma_s2mm.fwb_shift[2:0] 113 | @22 114 | zipdma_s2mm.fc_partial_wb[127:0] 115 | zipdma_s2mm.fc_partial_sel[15:0] 116 | @28 117 | zipdma_s2mm.f_sum[2:0] 118 | [pattern_trace] 1 119 | [pattern_trace] 0 120 | -------------------------------------------------------------------------------- /bench/formal/zipdma_s2mm.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 8 8 | cvr: mode cover 9 | 10 | [engines] 11 | smtbmc 12 | 13 | [script] 14 | read -formal zipdma_s2mm.v 15 | read -formal fwb_master.v 16 | --pycode-begin-- 17 | cmd = "hierarchy -top zipdma_s2mm" 18 | output(cmd) 19 | --pycode-end-- 20 | prep -top zipdma_s2mm 21 | 22 | [files] 23 | ../../rtl/ex/fwb_master.v 24 | ../../rtl/zipdma/zipdma_s2mm.v 25 | -------------------------------------------------------------------------------- /bench/formal/zipdma_txgears.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Wed Sep 28 15:50:30 2022 4 | [*] 5 | [dumpfile] "(null)" 6 | [timestart] 0 7 | [size] 1741 792 8 | [pos] -1 -1 9 | *-4.379821 45 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 | [sst_width] 343 11 | [signals_width] 166 12 | [sst_expanded] 1 13 | [sst_vpaned_height] 233 14 | @28 15 | zipdma_txgears.i_clk 16 | zipdma_txgears.i_reset 17 | zipdma_txgears.i_size[1:0] 18 | @200 19 | - 20 | @28 21 | zipdma_txgears.S_VALID 22 | zipdma_txgears.S_READY 23 | @22 24 | zipdma_txgears.S_DATA[63:0] 25 | zipdma_txgears.S_BYTES[3:0] 26 | @28 27 | zipdma_txgears.S_LAST 28 | @200 29 | - 30 | @28 31 | zipdma_txgears.M_VALID 32 | zipdma_txgears.M_READY 33 | @22 34 | zipdma_txgears.M_DATA[63:0] 35 | zipdma_txgears.M_BYTES[3:0] 36 | @28 37 | zipdma_txgears.M_LAST 38 | @200 39 | - 40 | @28 41 | zipdma_txgears.r_last 42 | @22 43 | zipdma_txgears.fill[3:0] 44 | zipdma_txgears.sreg[63:0] 45 | @28 46 | zipdma_txgears.r_next 47 | zipdma_txgears.f_mid_packet[1:0] 48 | @200 49 | - 50 | @28 51 | zipdma_txgears.fc_check 52 | @22 53 | zipdma_txgears.fc_posn[15:0] 54 | zipdma_txgears.fc_byte[7:0] 55 | @200 56 | - 57 | @28 58 | zipdma_txgears.fs_check 59 | @22 60 | zipdma_txgears.f_rcvd[15:0] 61 | @28 62 | zipdma_txgears.fs_shift[2:0] 63 | @22 64 | zipdma_txgears.fs_shifted[63:0] 65 | @200 66 | - 67 | @28 68 | zipdma_txgears.fm_check 69 | @22 70 | zipdma_txgears.f_sent[15:0] 71 | @28 72 | zipdma_txgears.fm_shift[2:0] 73 | @23 74 | zipdma_txgears.fm_shifted[63:0] 75 | [pattern_trace] 1 76 | [pattern_trace] 0 77 | -------------------------------------------------------------------------------- /bench/formal/zipdma_txgears.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfw prf bus64 4 | cvr 5 | cvrw cvr bus64 6 | 7 | [options] 8 | prf: mode prove 9 | prf: depth 4 10 | cvr: mode cover 11 | cvr: depth 40 12 | 13 | [engines] 14 | smtbmc 15 | 16 | [script] 17 | read -formal zipdma_txgears.v 18 | --pycode-begin-- 19 | cmd = "hierarchy -top zipdma_txgears" 20 | if ("bus64" in tags): 21 | cmd += " -chparam BUS_WIDTH 64" 22 | else: 23 | cmd += " -chparam BUS_WIDTH 32" 24 | output(cmd) 25 | --pycode-end-- 26 | prep -top zipdma_txgears 27 | 28 | [files] 29 | ../../rtl/zipdma/zipdma_txgears.v 30 | -------------------------------------------------------------------------------- /bench/formal/zipjiffies.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 5 7 | 8 | [engines] 9 | smtbmc 10 | 11 | [script] 12 | read -formal -DZIPJIFFIES zipjiffies.v 13 | read -formal -DZIPJIFFIES fwb_slave.v 14 | prep -top zipjiffies 15 | 16 | [files] 17 | ../../rtl/peripherals/zipjiffies.v 18 | ../../rtl/ex/fwb_slave.v 19 | -------------------------------------------------------------------------------- /bench/formal/zipjiffies.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPTIMER -formal ../../rtl/peripherals/zipjiffies.v 2 | read_verilog -D ZIPTIMER -formal ../../rtl/ex/fwb_slave.v 3 | prep -top zipjiffies -nordff 4 | opt -share_all 5 | write_smt2 -wires zipjiffies.smt2 6 | -------------------------------------------------------------------------------- /bench/formal/zipmmu.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | 4 | [options] 5 | prf: mode prove 6 | depth 23 7 | 8 | [engines] 9 | smtbmc boolector 10 | 11 | [script] 12 | read -formal -D ZIPMMU zipmmu.v 13 | read -formal -D ZIPMMU fwb_slave.v 14 | read -formal -D ZIPMMU fwb_master.v 15 | prep -top zipmmu 16 | 17 | [files] 18 | ../../rtl/peripherals/zipmmu.v 19 | ../../rtl/ex/fwb_slave.v 20 | ../../rtl/ex/fwb_master.v 21 | -------------------------------------------------------------------------------- /bench/formal/zipmmu.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPMMU -formal ../../rtl/peripherals/zipmmu.v 2 | read_verilog -D ZIPMMU -formal ../../rtl/ex/fwb_slave.v 3 | read_verilog -D ZIPMMU -formal ../../rtl/ex/fwb_master.v 4 | prep -top zipmmu -nordff 5 | opt -share_all 6 | clean 7 | write_smt2 -wires zipmmu.smt2 8 | -------------------------------------------------------------------------------- /bench/formal/ziptimer.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | prfr prf opt_reload 4 | 5 | [options] 6 | prf: mode prove 7 | depth 3 8 | 9 | [engines] 10 | smtbmc 11 | smtbmc boolector 12 | 13 | [script] 14 | read -formal -DZIPTIMER ziptimer.v 15 | read -formal -DZIPTIMER fwb_slave.v 16 | opt_reload: hierarchy -top ziptimer -chparam RELOADABLE 1 17 | ~opt_reload: hierarchy -top ziptimer -chparam RELOADABLE 0 18 | prep -top ziptimer 19 | 20 | [files] 21 | ../../rtl/peripherals/ziptimer.v 22 | ../../rtl/ex/fwb_slave.v 23 | -------------------------------------------------------------------------------- /bench/formal/ziptimer.ys: -------------------------------------------------------------------------------- 1 | read_verilog -D ZIPTIMER -formal ../../rtl/peripherals/ziptimer.v 2 | read_verilog -D ZIPTIMER -formal ../../rtl/ex/fwb_slave.v 3 | prep -top ziptimer -nordff 4 | opt -share_all 5 | write_smt2 -wires ziptimer.smt2 6 | -------------------------------------------------------------------------------- /bench/mcy/.gitignore: -------------------------------------------------------------------------------- 1 | ziptimer 2 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/.gitignore: -------------------------------------------------------------------------------- 1 | tasks/ 2 | database/ 3 | byteswap.cpp 4 | byteswap.h 5 | cpudefs.h 6 | cpudefs.v 7 | cpuops.v 8 | dblfetch.v 9 | dcache.v 10 | div.v 11 | fwb_master.v 12 | idecode.v 13 | iscachable.v 14 | memops.v 15 | memsim.cpp 16 | memsim.h 17 | mpyop.v 18 | pfcache.v 19 | pipefetch.v 20 | pipemem.v 21 | prefetch.v 22 | simtest 23 | slowmpy.v 24 | testb.h 25 | twoc.cpp 26 | twoc.h 27 | vversion.sh 28 | wbdblpriarb.v 29 | zipcpu.v 30 | zipelf.cpp 31 | zipelf.h 32 | zopcodes.cpp 33 | zopcodes.h 34 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/config.mcy: -------------------------------------------------------------------------------- 1 | [options] 2 | size 800 3 | weight_pq_s 500 4 | weight_pq_ms 500 5 | weight_cover 500 6 | pick_cover_prcnt 90 7 | tags COVERED UNCOVERED PROBE GAP NOC 8 | 9 | [script] 10 | read -sv zipcpu.v 11 | read -sv dblfetch.v 12 | read -sv dcache.v 13 | read -sv div.v 14 | read -sv idecode.v 15 | read -sv iscachable.v 16 | read -sv memops.v 17 | read -sv mpyop.v 18 | read -sv pfcache.v 19 | read -sv pipefetch.v 20 | read -sv pipemem.v 21 | read -sv prefetch.v 22 | read -sv slowmpy.v 23 | read -sv wbdblpriarb.v 24 | read -sv cpuops.v 25 | prep -top zipcpu 26 | 27 | [files] 28 | zipcpu.v 29 | dblfetch.v 30 | dcache.v 31 | div.v 32 | idecode.v 33 | iscachable.v 34 | memops.v 35 | mpyop.v 36 | pfcache.v 37 | pipefetch.v 38 | pipemem.v 39 | prefetch.v 40 | slowmpy.v 41 | cpudefs.v 42 | wbdblpriarb.v 43 | 44 | [logic] 45 | if result("sim_verilator") == "FAIL": 46 | tag("COVERED") 47 | if rng(100) < 20: 48 | tag("PROBE") 49 | t1 = result("eq_bmc") == "FAIL" 50 | t2 = result("eq_sim3 600") == "FAIL" 51 | if not t1 and not t2: 52 | tag("GAP") 53 | return 54 | 55 | if result("eq_sim3 60") == "FAIL": 56 | tag("UNCOVERED") 57 | return 58 | 59 | if result("eq_bmc") == "FAIL": 60 | tag("UNCOVERED") 61 | return 62 | 63 | if result("eq_sim3 600") == "FAIL": 64 | tag("UNCOVERED") 65 | return 66 | 67 | tag("NOC") 68 | 69 | [report] 70 | if tags("!NOC"): 71 | print("Coverage: %.2f%%" % (100.0*tags("COVERED")/tags("!NOC"))) 72 | if tags(): 73 | print("Noc percentage: %.2f%%" % (100.0*tags("NOC")/tags())) 74 | if tags("PROBE"): 75 | print("Gap percentage: %.2f%%" % (100.0*tags("GAP")/tags("PROBE"))) 76 | 77 | [test sim_verilator] 78 | maxbatchsize 10 79 | expect PASS FAIL 80 | run bash $PRJDIR/sim_verilator.sh 81 | 82 | [test eq_bmc] 83 | expect TIMEOUT PASS FAIL 84 | run bash $PRJDIR/eq_bmc.sh 85 | 86 | [test eq_sim3] 87 | expect TIMEOUT FAIL 88 | run bash $PRJDIR/eq_sim3.sh 89 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_bmc.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | depth 50 4 | expect timeout,fail 5 | timeout 600 6 | aigsmt none 7 | 8 | [engines] 9 | smtbmc boolector 10 | 11 | [script] 12 | --pycode-begin-- 13 | output("verilog_defines -Dmutidx=%s" % task) 14 | --pycode-end-- 15 | read_verilog -sv miter.sv 16 | read_ilang mutated.il 17 | chtype -map $mul $add 18 | prep -top miter 19 | fmcombine miter refi uut 20 | flatten 21 | opt -fast 22 | 23 | [files] 24 | ../../miter.sv 25 | mutated.il 26 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_bmc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | exec 2>&1 4 | set -ex 5 | 6 | { 7 | echo "read_ilang ../../database/design.il" 8 | while read -r idx mut; do 9 | echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" 10 | done < input.txt 11 | echo "write_ilang mutated.il" 12 | } > mutate.ys 13 | 14 | yosys -ql mutate.log mutate.ys 15 | cp ../../miter.sv ../../eq_bmc.sby . 16 | 17 | while read idx mut; do 18 | sby -f eq_bmc.sby ${idx} 19 | gawk "{ print $idx, \$1; }" eq_bmc_${idx}/status >> output.txt 20 | done < input.txt 21 | 22 | exit 0 23 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_sim3.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | depth 50 4 | expect timeout,fail 5 | timeout @TIMEOUT@ 6 | aigsmt none 7 | 8 | [engines] 9 | abc sim3 10 | 11 | [script] 12 | --pycode-begin-- 13 | output("verilog_defines -Dmutidx=%s" % task) 14 | --pycode-end-- 15 | read_verilog -sv miter.sv 16 | read_ilang mutated.il 17 | chtype -map $mul $add 18 | prep -top miter 19 | fmcombine miter refi uut 20 | flatten 21 | opt -fast 22 | 23 | [files] 24 | ../../miter.sv 25 | mutated.il 26 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/eq_sim3.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | exec 2>&1 4 | set -ex 5 | 6 | { 7 | echo "read_ilang ../../database/design.il" 8 | while read -r idx mut; do 9 | echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" 10 | done < input.txt 11 | echo "write_ilang mutated.il" 12 | } > mutate.ys 13 | 14 | yosys -ql mutate.log mutate.ys 15 | cp ../../miter.sv ../../eq_sim3.sby . 16 | sed -i "s/@TIMEOUT@/$1/" eq_sim3.sby 17 | 18 | if [ "$KEEPDIR" = 1 ]; then 19 | sed -i "/^aigsmt / d;" eq_sim3.sby 20 | fi 21 | 22 | while read idx mut; do 23 | sby -f eq_sim3.sby ${idx} 24 | gawk "{ print $idx, \$1; }" eq_sim3_${idx}/status >> output.txt 25 | done < input.txt 26 | 27 | exit 0 28 | -------------------------------------------------------------------------------- /bench/mcy/zipcpu/sim_verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Pipe standard error stream to stdout 4 | exec 2>&1 5 | 6 | # Exit on any non-zero error code along the way 7 | set -ex 8 | 9 | VROOT=/usr/local/share/verilator 10 | VINC=${VROOT}/include 11 | INCFILES="-I${VROOT}/include -Iobj_dir" 12 | CFLAGS="-Wall -O3" 13 | # CPPDIR="../../../cpp" 14 | CPPDIR="../.." 15 | OBJ=obj_dir 16 | 17 | { 18 | echo "read_ilang ../../database/design.il" 19 | while read -r idx mut; do 20 | echo "mutate -ctrl mutsel 8 ${idx} ${mut#* }" 21 | done < input.txt 22 | echo "write_verilog -attr2comment mutated.v" 23 | } > mutate.ys 24 | 25 | yosys -ql mutate.log mutate.ys 26 | cp ${CPPDIR}/zipcpu.cpp . 27 | cp ${CPPDIR}/memsim.h . 28 | cp ${CPPDIR}/memsim.cpp . 29 | cp ${CPPDIR}/byteswap.cpp . 30 | cp ${CPPDIR}/byteswap.h . 31 | cp ${CPPDIR}/twoc.cpp . 32 | cp ${CPPDIR}/twoc.h . 33 | cp ${CPPDIR}/zipelf.cpp . 34 | cp ${CPPDIR}/zipelf.h . 35 | cp ${CPPDIR}/testb.h . 36 | cp ${CPPDIR}/zopcodes.h . 37 | cp ${CPPDIR}/zopcodes.cpp . 38 | cp ../../zipbones.v . 39 | ls ../../../../../ 40 | cp ../../cpudefs.v . 41 | cp ../../cpudefs.h . 42 | cp ../../simtest . 43 | 44 | echo "// verilator lint_off UNOPTFLAT" > zipcpu.v 45 | echo "// verilator lint_off CASEOVERLAP" >> zipcpu.v 46 | echo "// verilator lint_off WIDTH" >> zipcpu.v 47 | cat mutated.v >> zipcpu.v 48 | verilator -O3 --trace -cc zipbones.v 49 | g++ ${CFLAGS} ${INCFILES} -DMCY -DZIPBONES -c zipcpu.cpp -o ${OBJ}/zipcpu.o 50 | g++ ${CFLAGS} ${INCFILES} -c ${VINC}/verilated.cpp -o ${OBJ}/verilated.o 51 | g++ ${CFLAGS} ${INCFILES} -c ${VINC}/verilated_vcd_c.cpp -o ${OBJ}/verilated_vcd.o 52 | g++ ${CFLAGS} ${INCFILES} -c memsim.cpp -o ${OBJ}/memsim.o 53 | g++ ${CFLAGS} ${INCFILES} -c twoc.cpp -o ${OBJ}/twoc.o 54 | g++ ${CFLAGS} ${INCFILES} -c zipelf.cpp -o ${OBJ}/zipelf.o 55 | g++ ${CFLAGS} ${INCFILES} -c byteswap.cpp -o ${OBJ}/byteswap.o 56 | g++ ${CFLAGS} ${INCFILES} -c zopcodes.cpp -o ${OBJ}/zopcodes.o 57 | cd obj_dir 58 | make -f Vzipbones.mk 59 | g++ zipcpu.o memsim.o twoc.o zipelf.o byteswap.o zopcodes.o verilated.o verilated_vcd.o Vzipbones__ALL.a -lelf -o ../zipcpu_tb 60 | cd .. 61 | 62 | zipcpu_tb 0 ../../simtest > goodsim_${idx}.out || true 63 | good_sum=$(md5sum goodsim_${idx}.out | awk '{ print $1; }') 64 | while read idx mut; do 65 | 66 | zipcpu_tb ${idx} ../../simtest > sim_${idx}.out || true 67 | this_sum=$(md5sum sim_${idx}.out | awk '{ print $1; }') 68 | echo "SUM " $this_sum 69 | if [ $good_sum = $this_sum ]; then 70 | echo "$idx PASS" >> output.txt 71 | else 72 | echo "$idx FAIL" >> output.txt 73 | fi 74 | done < input.txt 75 | exit 0 76 | -------------------------------------------------------------------------------- /bench/rtl/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: bench/rtl/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: This makefile builds a verilator simulation of the rtl 8 | ## testbenches necessary to test certain components of the 9 | ## ZipSystem using Verilator. It does not make the system within Icarus, 10 | ## Vivado or Quartus. 11 | ## 12 | ## 13 | ## Creator: Dan Gisselquist, Ph.D. 14 | ## Gisselquist Technology, LLC 15 | ## 16 | ################################################################################ 17 | ## }}} 18 | ## Copyright (C) 2015-2025, Gisselquist Technology, LLC 19 | ## {{{ 20 | ## This program is free software (firmware): you can redistribute it and/or 21 | ## modify it under the terms of the GNU General Public License as published 22 | ## by the Free Software Foundation, either version 3 of the License, or (at 23 | ## your option) any later version. 24 | ## 25 | ## This program is distributed in the hope that it will be useful, but WITHOUT 26 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 27 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 28 | ## for more details. 29 | ## 30 | ## You should have received a copy of the GNU General Public License along 31 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 32 | ## target there if the PDF file isn't present.) If not, see 33 | ## for a copy. 34 | ## }}} 35 | ## License: GPL, v3, as defined and found on www.gnu.org, 36 | ## {{{ 37 | ## http://www.gnu.org/licenses/gpl.html 38 | ## 39 | ################################################################################ 40 | ## }}} 41 | .PHONY: all 42 | all: zipmmu_tb 43 | 44 | CORED:= ../../rtl/core 45 | PRPHD:= ../../rtl/peripherals 46 | VOBJ := obj_dir 47 | VERILATOR := verilator 48 | VFLAGS := -Wall -MMD -trace -y $(PRPHD) -cc 49 | SUBMAKE := $(MAKE) --no-print-directory -C 50 | 51 | $(VOBJ)/Vzipmmu_tb.cpp: $(PRPHD)/zipmmu.v zipmmu_tb.v memdev.v 52 | $(VERILATOR) $(VFLAGS) -DVZIPMMU_TB zipmmu_tb.v 53 | $(VOBJ)/Vzipmmu_tb.h: $(VOBJ)/Vzipmmu_tb.cpp 54 | 55 | $(VOBJ)/Vzipmmu_tb__ALL.a: $(VOBJ)/Vzipmmu_tb.cpp $(VOBJ)/Vzipmmu_tb.h 56 | $(SUBMAKE) $(VOBJ) -f Vzipmmu_tb.mk 57 | 58 | .PHONY: zipmmu_tb 59 | zipmmu_tb: $(VOBJ)/Vzipmmu_tb__ALL.a 60 | 61 | .PHONY: clean 62 | clean: 63 | rm -rf $(VOBJ) 64 | 65 | 66 | DEPS := $(wildcard $(VOBJ)/*.d) 67 | ifneq ($(DEPS),) 68 | include $(DEPS) 69 | endif 70 | -------------------------------------------------------------------------------- /bench/zipsim.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Filename: zipsim.ld 4 | * {{{ 5 | * Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | * 7 | * Purpose: This linker script provides a memory layout used by some 8 | * of the ZipCPU's tests. It is not expected to be the desired 9 | * memory layout for FPGA builds. 10 | * 11 | * Creator: Dan Gisselquist, Ph.D. 12 | * Gisselquist Technology, LLC 13 | * 14 | ******************************************************************************** 15 | * }}} 16 | * Copyright (C) 2017-2023, Gisselquist Technology, LLC 17 | * {{{ 18 | * This program is free software (firmware): you can redistribute it and/or 19 | * modify it under the terms of the GNU General Public License as published 20 | * by the Free Software Foundation, either version 3 of the License, or (at 21 | * your option) any later version. 22 | * 23 | * This program is distributed in the hope that it will be useful, but WITHOUT 24 | * ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | * for more details. 27 | * 28 | * You should have received a copy of the GNU General Public License along 29 | * with this program. (It's in the $(ROOT)/doc directory. Run make with no 30 | * target there if the PDF file isn't present.) If not, see 31 | * for a copy. 32 | * }}} 33 | * License: GPL, v3, as defined and found on www.gnu.org, 34 | * {{{ 35 | * http://www.gnu.org/licenses/gpl.html 36 | * 37 | * }}} 38 | *******************************************************************************/ 39 | 40 | ENTRY(_start) 41 | 42 | MEMORY 43 | { 44 | flash (wx) : ORIGIN = 0x01000000, LENGTH = 0x01000000 /* 2^24 = 16MB */ 45 | sdram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000000 /* 2^28 = 256MB */ 46 | } 47 | 48 | _flash = ORIGIN(flash); 49 | _blkram = 0; 50 | _sdram = ORIGIN(sdram); 51 | _top_of_stack = ORIGIN(sdram) + LENGTH(sdram) - 4; 52 | 53 | SECTIONS 54 | { 55 | .rocode ORIGIN(flash) : { 56 | _boot_address = .; 57 | *(.start) 58 | } > flash 59 | _kernel_image_start = . ; 60 | _kernel_image_end = . ; 61 | _sdram_image_start = . ; 62 | .ramcode ORIGIN(sdram) : { 63 | *(.kernel) 64 | *(.text.startup) 65 | *(.text) 66 | *(.rodata*) *(.strings) 67 | *(.data) *(COMMON) 68 | }> sdram AT> flash 69 | _sdram_image_end = . ; 70 | .bss : { 71 | *(.bss) 72 | _bss_image_end = . ; 73 | } > sdram 74 | _top_of_heap = .; 75 | } 76 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | src/zipos.tex 2 | zipos.pdf 3 | *.aux 4 | *.dvi 5 | *.log 6 | *.out 7 | usage.ps 8 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: doc/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: 8 | ## 9 | ## 10 | ## Creator: Dan Gisselquist, Ph.D. 11 | ## Gisselquist Technology, LLC 12 | ## 13 | ################################################################################ 14 | ## }}} 15 | ## Copyright (C) 2015-2025, Gisselquist Technology, LLC 16 | ## {{{ 17 | ## This program is free software (firmware): you can redistribute it and/or 18 | ## modify it under the terms of the GNU General Public License as published 19 | ## by the Free Software Foundation, either version 3 of the License, or (at 20 | ## your option) any later version. 21 | ## 22 | ## This program is distributed in the hope that it will be useful, but WITHOUT 23 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | ## for more details. 26 | ## 27 | ## You should have received a copy of the GNU General Public License along 28 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | ## target there if the PDF file isn't present.) If not, see 30 | ## for a copy. 31 | ## }}} 32 | ## License: GPL, v3, as defined and found on www.gnu.org, 33 | ## {{{ 34 | ## http://www.gnu.org/licenses/gpl.html 35 | ## 36 | ################################################################################ 37 | ## 38 | ## }}} 39 | all: pdftex gpl-3.0.pdf spec.pdf 40 | DSRC := src 41 | 42 | ## gpl-3.0.pdf 43 | ## {{{ 44 | gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex 45 | latex $(DSRC)/gpl-3.0.tex 46 | latex $(DSRC)/gpl-3.0.tex 47 | dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi 48 | ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf 49 | rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps 50 | ## }}} 51 | 52 | .PHONY: pdftex 53 | ## {{{ 54 | pdftex: 55 | @cd gfx; bash -c "if [[ -e Makefile ]]; then make --no-print-directory; fi" 56 | ## }}} 57 | 58 | ## spec.pdf 59 | ## {{{ 60 | spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps 61 | cd $(DSRC)/; latex spec.tex 62 | cd $(DSRC)/; latex spec.tex 63 | cd $(DSRC)/; latex spec.tex 64 | cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../spec.ps spec.dvi 65 | ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf 66 | grep -i warning $(DSRC)/spec.log 67 | rm $(DSRC)/spec.dvi $(DSRC)/spec.log 68 | rm $(DSRC)/spec.aux $(DSRC)/spec.toc 69 | rm $(DSRC)/spec.lot $(DSRC)/spec.lof 70 | rm $(DSRC)/spec.out spec.ps 71 | ## }}} 72 | 73 | ## zipos.pdf 74 | ## {{{ 75 | zipos.pdf: $(DSRC)/zipos.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps 76 | cd $(DSRC)/; latex zipos.tex 77 | cd $(DSRC)/; latex zipos.tex 78 | cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../zipos.ps zipos.dvi 79 | ps2pdf -dAutoRotatePages=/All zipos.ps zipos.pdf 80 | rm $(DSRC)/zipos.dvi $(DSRC)/zipos.log 81 | rm $(DSRC)/zipos.aux $(DSRC)/zipos.toc 82 | rm $(DSRC)/zipos.lot $(DSRC)/zipos.lof 83 | rm $(DSRC)/zipos.out zipos.ps 84 | ## }}} 85 | -------------------------------------------------------------------------------- /doc/gfx/.gitignore: -------------------------------------------------------------------------------- 1 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Gisselquist, Ph.D.} 5 | \usepackage{xcolor} 6 | \usepackage{hyperref} 7 | \definecolor{dkblue}{rgb}{0,0,0.6} 8 | \hypersetup{colorlinks=true,linkcolor=black,citecolor=dkblue} 9 | \newcommand{\defined}{\triangleq} 10 | \newcommand{\MP}{M_{\mbox{\tiny P}}} 11 | \newcommand{\ML}{M_{\mbox{\tiny L}}} 12 | \newcommand{\CPI}{{\mbox{\tt CPI}}} 13 | \newcommand{\CPISNGL}{{\mbox{\tt CPI}}_{\mbox{\tiny SNGL}}} 14 | \newcommand{\CPIDBL}{{\mbox{\tt CPI}}_{\mbox{\tiny DBLFETCH}}} 15 | \newcommand{\CPM}{{\mbox{\tt CPM}}} 16 | \newcommand{\PMEM}{P_{\mbox{\tiny MEM}}} 17 | \newcommand{\PBr}{P_{\mbox{\tiny BRANCH}}} 18 | \newcommand{\PB}{P_{\mbox{\tiny BR}}} 19 | \newcommand{\zhref}[2]{\href{#1}{\textcolor{dkblue}{#2}}} 20 | \begin{document} 21 | \maketitle 22 | 23 | \begin{center}\begin{tabular}{|l|r|r|}\hline 24 | & \multicolumn{1}{c}{iCE40} & \multicolumn{1}{|c|}{Xilinx 7} \\ 25 | ZipBones & \multicolumn{1}{c}{4-LUTs} & \multicolumn{1}{|c|}{6-LUTs}\\\hline\hline 26 | ASM & 1114 & 581 \\\hline 27 | Trap & 1655 & 962 \\\hline 28 | Minimum & 2691 & 1456 \\\hline 29 | Pipelined & 3578 & 1983 \\\hline 30 | Cached & 5407 & 3217 \\\hline 31 | Low power & 5381 & 3167 \\\hline 32 | \end{tabular}\end{center} 33 | 34 | 35 | \begin{center}\begin{tabular}{|l|r|r|}\hline 36 | & \multicolumn{1}{c}{iCE40} & \multicolumn{1}{|c|}{Xilinx 7} \\ 37 | ZipSystem &\multicolumn{1}{c}{4-LUTs} & \multicolumn{1}{|c|}{6-LUTs}\\\hline\hline 38 | ASM & 3358 & 1652 \\\hline 39 | Trap & 4037 & 2209 \\\hline 40 | Minimum & 5157 & 2678 \\\hline 41 | Pipelined & 6348 & 3431 \\\hline 42 | Cached & 8089 & 4507 \\\hline 43 | Low power & 8126 & 4539 \\\hline 44 | \end{tabular}\end{center} 45 | 46 | 47 | \begin{center}\begin{tabular}{|l|r|r|}\hline 48 | & \multicolumn{1}{c}{iCE40} & \multicolumn{1}{c|}{Xilinx 7} \\ 49 | ZipAXI-Lite & \multicolumn{1}{c}{4-LUTs} & \multicolumn{1}{|c|}{6-LUTs}\\\hline\hline 50 | ASM & 1477 & 876 \\\hline 51 | Trap & 2124 & 1161 \\\hline 52 | Minimum & 3166 & 1669 \\\hline 53 | Pipelined & 4193 & 2322 \\\hline 54 | \end{tabular}\end{center} 55 | 56 | \begin{center}\begin{tabular}{|l|r|r|}\hline 57 | & \multicolumn{1}{c|}{iCE40} & \multicolumn{1}{|c|}{Xilinx 7} \\ 58 | ZipAXI & \multicolumn{1}{c|}{4-LUTs} & \multicolumn{1}{|c|}{6-LUTs}\\\hline\hline 59 | ASM & 1471 & 878 \\\hline 60 | Trap & 2042 & 1228 \\\hline 61 | Minimum & 3116 & 1702 \\\hline 62 | Pipelined & 4181 & 2250 \\\hline 63 | Cached & 5225 & 2908 \\\hline 64 | Low power & 5362 & 3060 \\\hline 65 | \end{tabular}\end{center} 66 | 67 | 68 | \begin{center}\begin{tabular}{|l|r|r|r|}\hline 69 | Bus, 6-Luts & \multicolumn{1}{|c|}{Wishbone} & \multicolumn{1}{|c|}{AXI4-Lite} 70 | & \multicolumn{1}{|c|}{AXI4} \\\hline\hline 71 | Minimum & 1456 & 1669 & 1701 \\\hline 72 | Pipelined & 1983 & 2322 & 2250 \\\hline 73 | 4kB Caches, I+D & 3217 & --- & 2908 \\\hline 74 | Low power option & 3167 & --- & 3060 \\\hline 75 | \end{tabular}\end{center} 76 | 77 | \end{document} 78 | -------------------------------------------------------------------------------- /doc/wbspec_b4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/8f12b101e3d9e8963395fd13bbd7f4d77f0b8e2b/doc/wbspec_b4.pdf -------------------------------------------------------------------------------- /rtl/.gitignore: -------------------------------------------------------------------------------- 1 | zipsys_coverage/ 2 | pipefetch.m 3 | export 4 | *.log 5 | usage.ys 6 | yosys.ys 7 | -------------------------------------------------------------------------------- /rtl/README.md: -------------------------------------------------------------------------------- 1 | This directory contains three sub-directories: 2 | 3 | - [core](core), where all of the actual components to the CPU proper are contained 4 | - [peripherals](peripherals), where several common CPU peripherals are kept. These aren't really external peripherals per se, although they may be implemented as such. Rather, these peripherals are components that are important to the CPU's functionality. As such, they are often distributed with the CPU proper, and used internally by supervisor programs. 5 | - [ex](ex), where some general wishbone cores are kept, such as arbiters, delays, and even where I keep a copy of the formal wishbone properties. 6 | 7 | Within this ZipCPU RTL directory are four bus wrappers for the [core of the 8 | ZipCPU](core/zipcore.v). Two of these are Wishbone wrappers: 9 | [ZipBones](zipbones.v) and [ZipSystem](zipsystem.v). Another two are AXI-lite 10 | and AXI wrappers respectively: [ZipAXIL](zipaxil.v) and [ZipAXI](zipaxi.v). 11 | These wrappers connect an external wishbone or AXI-lite slave interface to 12 | the debugging port of the CPU, so that the CPU can be reset, started, stopped, 13 | stepped, and in general debugged. 14 | 15 | The [ZipBones](./zipbones.v) would be the appropriate wrapper if you want the 16 | CPU to fit in the tightest space possible (Ex: Digilent's [CMod 17 | S6](https://github.com/ZipCPU/s6soc)). 18 | 19 | Use the [ZipSystem](./zipsystem.v) if you want to couple some peripherals 20 | tightly to the CPU. These peripherals include: 21 | 22 | - 2x [Interrupt controllers](./peripherals/icontrol.v) 23 | - [Timers](peripherals/ziptimer), and an [experimental timer called zipjiffies](peripherals/zipjiffies.v) that's been with the CPU for some time 24 | - [Performance counters](peripherals/zipcounter.v), to measure your performance 25 | - A [Direct Memory Access Controller](./peripherals/wbdmac.v) 26 | - Or even the [Memory Management Unit](./peripherals/zipmmu.v) 27 | 28 | Neither [ZipBones](zipbones.v), [ZipAXIL](zipaxil.v), nor [ZipAXI](zipaxi.v) 29 | contain these peripherals. If you would like to use these peripherals with 30 | these wrappers, they'll need to be located external to the CPU and connected 31 | via your bus interconnect. 32 | 33 | If you are just looking for the CPU's code itself, check out 34 | [zipcore.v](core/zipcore.v) within the [core](core) subdirectory. 35 | That's of the main core of the ZipCPU itself. 36 | -------------------------------------------------------------------------------- /rtl/core/.gitignore: -------------------------------------------------------------------------------- 1 | *.ys 2 | -------------------------------------------------------------------------------- /rtl/core/iscachable.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: rtl/core/iscachable.v 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: A helper function to both dcache and its formal properties, 8 | // used to determine when a particular address is cachable. This 9 | // module must be built of entirely combinatorial logic and nothing more. 10 | // 11 | // Creator: Dan Gisselquist, Ph.D. 12 | // Gisselquist Technology, LLC 13 | // 14 | //////////////////////////////////////////////////////////////////////////////// 15 | // }}} 16 | // Copyright (C) 2018-2025, Gisselquist Technology, LLC 17 | // {{{ 18 | // This program is free software (firmware): you can redistribute it and/or 19 | // modify it under the terms of the GNU General Public License as published 20 | // by the Free Software Foundation, either version 3 of the License, or (at 21 | // your option) any later version. 22 | // 23 | // This program is distributed in the hope that it will be useful, but WITHOUT 24 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | // for more details. 27 | // 28 | // You should have received a copy of the GNU General Public License along 29 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 30 | // target there if the PDF file isn't present.) If not, see 31 | // for a copy. 32 | // }}} 33 | // License: GPL, v3, as defined and found on www.gnu.org, 34 | // {{{ 35 | // http://www.gnu.org/licenses/gpl.html 36 | // 37 | //////////////////////////////////////////////////////////////////////////////// 38 | // 39 | `default_nettype none 40 | // }}} 41 | module iscachable #( 42 | // {{{ 43 | parameter ADDRESS_WIDTH=32, 44 | localparam AW = ADDRESS_WIDTH, // Just for ease of notation below 45 | parameter [AW-1:0] SDRAM_ADDR = 0, SDRAM_MASK = 0, 46 | parameter [AW-1:0] BKRAM_ADDR = 32'h10000000, 47 | BKRAM_MASK = 32'h10000000, 48 | parameter [AW-1:0] FLASH_ADDR = 0, FLASH_MASK = 0 49 | // }}} 50 | ) ( 51 | // {{{ 52 | input wire [AW-1:0] i_addr, 53 | output reg o_cachable 54 | // }}} 55 | ); 56 | 57 | 58 | always @(*) 59 | begin 60 | o_cachable = 1'b0; 61 | if ((SDRAM_ADDR !=0)&&((i_addr & SDRAM_MASK)== SDRAM_ADDR)) 62 | o_cachable = 1'b1; 63 | else if ((FLASH_ADDR !=0)&&((i_addr & FLASH_MASK)== FLASH_ADDR)) 64 | o_cachable = 1'b1; 65 | else if ((BKRAM_ADDR !=0)&&((i_addr & BKRAM_MASK)== BKRAM_ADDR)) 66 | o_cachable = 1'b1; 67 | end 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /rtl/peripherals/README.md: -------------------------------------------------------------------------------- 1 | # ZipCPU Peripherals 2 | 3 | These are not your normal peripherals, per se, but rather peripherals that 4 | get tightly integrated with the CPU when built with the ZipSystem. These 5 | include: 6 | 7 | - [icontrol.v](./icontrol.v), an interrupt controller 8 | 9 | - [zipcounter.v](./zipcounter.v), a *really* simple counter, for estimating CPU performance. The counter will interrupt the CPU if/when it ever rolls over. 10 | 11 | - [ziptimer.v](./ziptimer.v), a similarly simple timer. It just counts down and creates an interrupt 12 | 13 | - [zipjiffies.v](./zipjiffies.v). Modeled after the Jiffies used within the Linux Kernel, the zipjiffies peripheral counts up one count per clock. Numbers written to it request an interrupt when the clock gets to the number written. Hence, you can get really fine grained timing control using this peripheral. 14 | 15 | - [wbdmac.v](./wbdmac.v), a direct memory access controller. This can be used to copy memory, or even copy memory on an interrupt. Source and destination addresses may or may not increment depending upon how the controller is set. As of today, though, this controller only handles 32-bit transfers. 16 | 17 | - [zipmmu.v](./zipmmu.v), an experimental MMU. Has only been tested offline. 18 | An implementation exists which integrates this MMU, however that integration 19 | has not been tested so there are certainly some integration bugs remaining. 20 | 21 | *All of these peripherals* have been formally proven. 22 | 23 | If you are looking for the more normal peripherals, block RAM, SDRAM, etc., 24 | feel free to examine some of the distributions that use the ZipCPU. 25 | 26 | 27 | -------------------------------------------------------------------------------- /rtl/usage-1-baseline.txt: -------------------------------------------------------------------------------- 1 | iCE40 X7-s 2 | Wrapper Config 4LUT 6LUT 3 | ---------------------------- 4 | ZipBones ASM: 1103 575 5 | ZipBones TRAP: 1606 977 6 | ZipBones MIN: 2662 1442 7 | ZipBones PIPE: 3527 1934 8 | ZipBones CACHE: 5163 2713 9 | ZipBones LWPWR: 5178 2716 10 | ZipSystem ASM: 3346 1657 11 | ZipSystem TRAP: 4050 2152 12 | ZipSystem MIN: 5137 2628 13 | ZipSystem PIPE: 6309 3258 14 | ZipSystem CACHE: 7909 4204 15 | ZipSystem LWPWR: 7955 4253 16 | ZipAXI-L ASM: 1490 821 17 | ZipAXI-L TRAP: 2200 1218 18 | ZipAXI-L MIN: 3143 1675 19 | ZipAXI-L PIPE: 4185 2228 20 | ZipAXI ASM: 1485 842 21 | ZipAXI TRAP: 2055 1229 22 | ZipAXI MIN: 3073 1664 23 | ZipAXI PIPE: 4152 2244 24 | ZipAXI CACHE: 4936 2829 25 | ZipAXI LWPWR: 5053 2820 26 | WB-MEMOPS : 94 68 27 | WB-PIPEMEM : 228 88 28 | WB-DCACHE : 1311 652 29 | AXI-DCACHE : 974 642 30 | WB-DMA : 1310 556 31 | WB-PREFETCH : 122 66 32 | WB-DBLFETCH : 204 106 33 | WB-ICACHE : 3024 1725 34 | AXI-ICACHE : 652 464 35 | -------------------------------------------------------------------------------- /rtl/usage-2-verific.txt: -------------------------------------------------------------------------------- 1 | iCE40 X7-s 2 | Wrapper Config 4LUT 6LUT 3 | ---------------------------- 4 | ZipBones ASM: 1124 567 5 | ZipBones TRAP: 1670 981 6 | ZipBones MIN: 2623 1483 7 | ZipBones PIPE: 3508 1891 8 | ZipBones CACHE: 61982 28294 9 | ZipBones LWPWR: 61506 28187 10 | ZipSystem ASM: 3109 1637 11 | ZipSystem TRAP: 3722 2127 12 | ZipSystem MIN: 4688 2577 13 | ZipSystem PIPE: 5713 3140 14 | ZipSystem CACHE: 64132 29280 15 | ZipSystem LWPWR: 63873 29421 16 | ZipAXI-L ASM: 1502 840 17 | ZipAXI-L TRAP: 2060 1139 18 | ZipAXI-L MIN: 3017 1739 19 | ZipAXI-L PIPE: 4031 2245 20 | ZipAXI ASM: 1504 859 21 | ZipAXI TRAP: 2101 1210 22 | ZipAXI MIN: 3039 1689 23 | ZipAXI PIPE: 4066 2252 24 | ZipAXI CACHE: 61284 28535 25 | ZipAXI LWPWR: 61422 30065 26 | WB-MEMOPS : 109 68 27 | WB-PIPEMEM : 243 91 28 | WB-DCACHE : 233073 114668 29 | AXI-DCACHE : 57377 28943 30 | WB-DMA : 1195 558 31 | WB-PREFETCH : 70 66 32 | WB-DBLFETCH : 151 105 33 | WB-ICACHE : 3095 1733 34 | AXI-ICACHE : 627 481 35 | -------------------------------------------------------------------------------- /rtl/usage-3-locache.txt: -------------------------------------------------------------------------------- 1 | iCE40 X7-s 2 | Wrapper Config 4LUT 6LUT 3 | ---------------------------- 4 | ZipBones ASM: 1071 572 5 | ZipBones TRAP: 1582 922 6 | ZipBones MIN: 2540 1472 7 | ZipBones PIPE: 3436 1929 8 | ZipBones CACHE: 5053 2679 9 | ZipBones LWPWR: 5010 2734 10 | ZipSystem ASM: 3083 1786 11 | ZipSystem TRAP: 3637 2114 12 | ZipSystem MIN: 4636 2653 13 | ZipSystem PIPE: 5649 3264 14 | ZipSystem CACHE: 7365 4158 15 | ZipSystem LWPWR: 7304 4251 16 | ZipAXI-L ASM: 1450 827 17 | ZipAXI-L TRAP: 2171 1197 18 | ZipAXI-L MIN: 3022 1737 19 | ZipAXI-L PIPE: 4015 2219 20 | ZipAXI ASM: 1454 841 21 | ZipAXI TRAP: 1992 1243 22 | ZipAXI MIN: 2969 1675 23 | ZipAXI PIPE: 3956 2231 24 | ZipAXI CACHE: 4797 2780 25 | ZipAXI LWPWR: 4974 2872 26 | WB-MEMOPS : 94 68 27 | WB-PIPEMEM : 227 87 28 | WB-DCACHE : 1235 658 29 | AXI-DCACHE : 967 642 30 | WB-DMA : 1219 554 31 | WB-PREFETCH : 70 66 32 | WB-DBLFETCH : 152 106 33 | WB-ICACHE : 819 523 34 | AXI-ICACHE : 628 464 35 | -------------------------------------------------------------------------------- /rtl/usage.txt: -------------------------------------------------------------------------------- 1 | iCE40 X7-s RAW 2 | Wrapper Config 4LUT 6LUT NANDs 3 | ----------------------------------- 4 | ZipBones ASM: 1170 583 3100 5 | ZipBones TRAP: 1711 988 5936 6 | ZipBones MIN: 2841 1498 9338 7 | ZipBones PIPE: 3715 2015 10568 8 | ZipBones CACHE: 5869 3302 245536 9 | ZipBones LWPWR: 6383 3430 237239 10 | ZipSystem ASM: 4372 2342 17235 11 | ZipSystem TRAP: 5112 2673 20786 12 | ZipSystem MIN: 6252 3217 25261 13 | ZipSystem PIPE: 7562 3845 26596 14 | ZipSystem CACHE: 9605 5182 285245 15 | ZipSystem LWPWR: 10093 5238 259176 16 | ZipAXI-L ASM: 1540 869 4247 17 | ZipAXI-L TRAP: 2176 1175 6772 18 | ZipAXI-L MIN: 3283 1683 10675 19 | ZipAXI-L PIPE: 4410 2300 12132 20 | ZipAXI ASM: 1528 861 3798 21 | ZipAXI TRAP: 2102 1215 6331 22 | ZipAXI MIN: 3208 1764 10297 23 | ZipAXI PIPE: 4383 2290 11941 24 | ZipAXI CACHE: 5751 2982 202922 25 | ZipAXI LWPWR: 6265 3358 178478 26 | 27 | WB-MEMOPS : 131 77 219 28 | WB-PIPEMEM : 279 89 341 29 | WB-DCACHE : 1591 729 114673 30 | AXIL-OPS : 230 129 329 31 | AXI-OPS : 320 205 554 32 | AXIL-PIPE : 393 157 663 33 | AXI-PIPE : 447 145 719 34 | AXI-DCACHE : 1266 736 110730 35 | 36 | WB-PREFETCH : 122 66 208 37 | WB-DBLFETCH : 202 106 325 38 | WB-FIFOFETCH: 353 129 961 39 | WB-ICACHE : 1070 610 109144 40 | AXILFETCH-BSC: 220 90 317 41 | AXILFETCH-PIP: 270 128 443 42 | AXI-ICACHE : 899 534 52625 43 | 44 | WB-DMAC(OLD): 799 340 62152 45 | ZIP-DMA/ 32 : 1872 1024 20125 46 | ZIP-DMA/ 64 : 2808 1729 20423 47 | ZIP-DMA/512 : 17593 12638 36681 48 | -------------------------------------------------------------------------------- /sim/.gitignore: -------------------------------------------------------------------------------- 1 | test/ 2 | logs/ 3 | ## 4 | ## 5 | axmincheck 6 | axpipecheck 7 | axcachecheck 8 | axlpwrcheck 9 | # 10 | axlmincheck 11 | axlpipecheck 12 | # 13 | console.txt 14 | # 15 | wbmincheck 16 | wbpipecheck 17 | wbcachecheck 18 | wblpwrcheck 19 | # 20 | wbbmincheck 21 | wbbpipecheck 22 | wbbcachecheck 23 | wbblpwrcheck 24 | # 25 | # 26 | # 27 | axminhello 28 | axpipehello 29 | axcachehello 30 | axlpwrhello 31 | # 32 | axlminhello 33 | axlpipehello 34 | # 35 | console.txt 36 | # 37 | wbminhello 38 | wbpipehello 39 | wbcachehello 40 | wblpwrhello 41 | # 42 | wbbminhello 43 | wbbpipehello 44 | wbbcachehello 45 | wbblpwrhello 46 | # 47 | # 48 | axmincklock 49 | axpipecklock 50 | axcachecklock 51 | axlpwrcklock 52 | # 53 | axlmincklock 54 | axlpipecklock 55 | # 56 | wbmincklock 57 | wbpipecklock 58 | wbcachecklock 59 | wblpwrcklock 60 | # 61 | wbbmincklock 62 | wbbpipecklock 63 | wbbcachecklock 64 | wbblpwrcklock 65 | # 66 | -------------------------------------------------------------------------------- /sim/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: sim/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: 8 | ## 9 | ## Targets include: 10 | ## 11 | ## test Run all simulation tests 12 | ## 13 | ## 14 | ## Creator: Dan Gisselquist, Ph.D. 15 | ## Gisselquist Technology, LLC 16 | ## 17 | ################################################################################ 18 | ## }}} 19 | ## Copyright (C) 2023-2025, Gisselquist Technology, LLC 20 | ## {{{ 21 | ## This program is free software (firmware): you can redistribute it and/or 22 | ## modify it under the terms of the GNU General Public License as published 23 | ## by the Free Software Foundation, either version 3 of the License, or (at 24 | ## your option) any later version. 25 | ## 26 | ## This program is distributed in the hope that it will be useful, but WITHOUT 27 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 28 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 29 | ## for more details. 30 | ## 31 | ## You should have received a copy of the GNU General Public License along 32 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 33 | ## target there if the PDF file isn't present.) If not, see 34 | ## for a copy. 35 | ## }}} 36 | ## License: GPL, v3, as defined and found on www.gnu.org, 37 | ## {{{ 38 | ## http://www.gnu.org/licenses/gpl.html 39 | ## 40 | ################################################################################ 41 | ## 42 | ## }}} 43 | .PHONY: all 44 | all: test 45 | 46 | .PHONY: host 47 | host: 48 | make -C verilator 49 | make -C verilator test 50 | 51 | .PHONY: zipsw 52 | zipsw: host 53 | make -C zipsw 54 | 55 | .PHONY: test 56 | test: zipsw 57 | perl sim_run.pl verilator all 58 | -------------------------------------------------------------------------------- /sim/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | zsim 2 | -------------------------------------------------------------------------------- /sim/cpp/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: sim/cpp/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: 8 | ## 9 | ## Targets: 10 | ## 11 | ## 12 | ## Creator: Dan Gisselquist, Ph.D. 13 | ## Gisselquist Technology, LLC 14 | ## 15 | ################################################################################ 16 | ## }}} 17 | ## Copyright (C) 2017-2025, Gisselquist Technology, LLC 18 | ## {{{ 19 | ## This program is free software (firmware): you can redistribute it and/or 20 | ## modify it under the terms of the GNU General Public License as published 21 | ## by the Free Software Foundation, either version 3 of the License, or (at 22 | ## your option) any later version. 23 | ## 24 | ## This program is distributed in the hope that it will be useful, but WITHOUT 25 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | ## for more details. 28 | ## 29 | ## You should have received a copy of the GNU General Public License along 30 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | ## target there if the PDF file isn't present.) If not, see 32 | ## for a copy. 33 | ## }}} 34 | ## License: GPL, v3, as defined and found on www.gnu.org, 35 | ## {{{ 36 | ## http://www.gnu.org/licenses/gpl.html 37 | ## 38 | ################################################################################ 39 | ## 40 | ## }}} 41 | all: zsim 42 | 43 | CXX := g++ 44 | FLAGS := -Wall -g 45 | INCS := 46 | SOURCES := zsim.cpp twoc.cpp zipelf.cpp 47 | LIBS := -lelf 48 | TESTF := $(ZASM)/z.out 49 | DHRYSTONEF := ../asm/zipdhry.z 50 | 51 | zsim: $(SOURCES) zipelf.h twoc.h 52 | $(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@ 53 | 54 | .PHONY: clean 55 | clean: 56 | rm -f zsim 57 | -------------------------------------------------------------------------------- /sim/cpp/README.md: -------------------------------------------------------------------------------- 1 | ## The C++ Simulator 2 | 3 | This simulator was written as part of the last instruction set change. 4 | 5 | It is now pretty much abandonware. 6 | 7 | One problem with this simulation is that it was very difficult to integrate 8 | peripherals and interrupts into it--more difficult than it is to integrate 9 | these things into a Verilog design tested with Verilator. As a result, 10 | there's not much useful here. 11 | -------------------------------------------------------------------------------- /sim/cpp/twoc.cpp: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/cpp/twoc.cpp 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: Some various two's complement related C++ helper routines. 8 | // Specifically, these help extract signed numbers from 9 | // packed bitfields, while guaranteeing that the upper bits are properly 10 | // sign extended (or not) as desired. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #include "twoc.h" 42 | 43 | long sbits(const long val, const int bits) { 44 | long r; 45 | 46 | r = val & ((1l< for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #ifndef TWOC_H 42 | #define TWOC_H 43 | 44 | extern long sbits(const long val, const int bits); 45 | extern unsigned long ubits(const long val, const int bits); 46 | 47 | #endif 48 | 49 | -------------------------------------------------------------------------------- /sim/cpp/zipelf.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/cpp/zipelf.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: 8 | // 9 | // 10 | // Creator: Dan Gisselquist, Ph.D. 11 | // Gisselquist Technology, LLC 12 | // 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // }}} 15 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 16 | // {{{ 17 | // This program is free software (firmware): you can redistribute it and/or 18 | // modify it under the terms of the GNU General Public License as published 19 | // by the Free Software Foundation, either version 3 of the License, or (at 20 | // your option) any later version. 21 | // 22 | // This program is distributed in the hope that it will be useful, but WITHOUT 23 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | // for more details. 26 | // 27 | // You should have received a copy of the GNU General Public License along 28 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | // target there if the PDF file isn't present.) If not, see 30 | // for a copy. 31 | // }}} 32 | // License: GPL, v3, as defined and found on www.gnu.org, 33 | // {{{ 34 | // http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // }}} 39 | #ifndef ZIPELF_H 40 | #define ZIPELF_H 41 | 42 | #include 43 | 44 | class ELFSECTION { 45 | public: 46 | uint32_t m_start, m_len, m_vaddr; 47 | char m_data[4]; 48 | }; 49 | 50 | bool iself(const char *fname); 51 | void elfread(const char *fname, uint32_t &entry, ELFSECTION **§ions); 52 | 53 | #endif 54 | -------------------------------------------------------------------------------- /sim/rtl/iscachable.v: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/rtl/iscachable.v 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: A helper function to both dcache and its formal properties, 8 | // used to determine when a particular address is cachable. This 9 | // module must be built of entirely combinatorial logic and nothing more. 10 | // 11 | // This particular version is taylored to the test bench configuration 12 | // of the ZipCPU. 13 | // 14 | // Creator: Dan Gisselquist, Ph.D. 15 | // Gisselquist Technology, LLC 16 | // 17 | //////////////////////////////////////////////////////////////////////////////// 18 | // }}} 19 | // Copyright (C) 2018-2025, Gisselquist Technology, LLC 20 | // {{{ 21 | // This program is free software (firmware): you can redistribute it and/or 22 | // modify it under the terms of the GNU General Public License as published 23 | // by the Free Software Foundation, either version 3 of the License, or (at 24 | // your option) any later version. 25 | // 26 | // This program is distributed in the hope that it will be useful, but WITHOUT 27 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 28 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 29 | // for more details. 30 | // 31 | // You should have received a copy of the GNU General Public License along 32 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 33 | // target there if the PDF file isn't present.) If not, see 34 | // for a copy. 35 | // }}} 36 | // License: GPL, v3, as defined and found on www.gnu.org, 37 | // {{{ 38 | // http://www.gnu.org/licenses/gpl.html 39 | // 40 | //////////////////////////////////////////////////////////////////////////////// 41 | // 42 | `default_nettype none 43 | // }}} 44 | module iscachable #( 45 | // {{{ 46 | parameter ADDRESS_WIDTH=28, 47 | localparam AW = ADDRESS_WIDTH, // Just for ease of notation below 48 | parameter [AW-1:0] MEM_ADDR = {4'b0100, {(ADDRESS_WIDTH-4){1'b0}} }, 49 | parameter [AW-1:0] MEM_MASK = {4'b1111, {(ADDRESS_WIDTH-4){1'b0}} } 50 | // }}} 51 | ) ( 52 | // {{{ 53 | input wire [AW-1:0] i_addr, 54 | output reg o_cachable 55 | // }}} 56 | ); 57 | 58 | 59 | always @(*) 60 | begin 61 | o_cachable = 1'b0; 62 | if ((MEM_ADDR !=0)&&((i_addr & MEM_MASK)== MEM_ADDR)) 63 | o_cachable = 1'b1; 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /sim/rtl/sim_axfiles.txt: -------------------------------------------------------------------------------- 1 | rtl/axi_tb.v 2 | rtl/memdev.v 3 | rtl/addrdecode.v 4 | rtl/axiempty.v 5 | rtl/axixbar.v 6 | rtl/axilxbar.v 7 | rtl/axilite2axi.v 8 | rtl/axi2axilsub.v 9 | rtl/axi2axilite.v 10 | rtl/axilscope.v 11 | rtl/axilcon.v 12 | rtl/axi_addr.v 13 | rtl/demofull.v 14 | rtl/iscachable.v 15 | ../rtl/zipaxi.v 16 | ../rtl/zipaxil.v 17 | ../rtl/core/axilfetch.v 18 | ../rtl/core/axiicache.v 19 | ../rtl/core/axilops.v 20 | ../rtl/core/axiops.v 21 | ../rtl/core/axilpipe.v 22 | ../rtl/core/axipipe.v 23 | ../rtl/core/axidcache.v 24 | ../rtl/core/cpuops.v 25 | ../rtl/core/div.v 26 | ../rtl/core/idecode.v 27 | ../rtl/core/memops.v 28 | ../rtl/core/mpyop.v 29 | ../rtl/core/slowmpy.v 30 | ../rtl/core/zipcore.v 31 | ../rtl/ex/sfifo.v 32 | ../rtl/ex/skidbuffer.v 33 | ../rtl/peripherals/axilperiphs.v 34 | ../rtl/peripherals/icontrol.v 35 | ../rtl/peripherals/zipcounter.v 36 | ../rtl/peripherals/zipjiffies.v 37 | ../rtl/peripherals/ziptimer.v 38 | -------------------------------------------------------------------------------- /sim/rtl/sim_wbfiles.txt: -------------------------------------------------------------------------------- 1 | rtl/wb_tb.v 2 | rtl/memdev.v 3 | rtl/addrdecode.v 4 | rtl/wbxbar.v 5 | rtl/wbdown.v 6 | rtl/wbscope.v 7 | rtl/iscachable.v 8 | ../rtl/zipbones.v 9 | ../rtl/zipsystem.v 10 | ../rtl/core/cpuops.v 11 | ../rtl/core/dblfetch.v 12 | ../rtl/core/dcache.v 13 | ../rtl/core/div.v 14 | ../rtl/core/idecode.v 15 | ../rtl/core/memops.v 16 | ../rtl/core/mpyop.v 17 | ../rtl/core/pfcache.v 18 | ../rtl/core/pffifo.v 19 | ../rtl/core/pipefetch.v 20 | ../rtl/core/pipemem.v 21 | ../rtl/core/prefetch.v 22 | ../rtl/core/slowmpy.v 23 | ../rtl/core/zipcore.v 24 | ../rtl/core/zipwb.v 25 | ../rtl/ex/busdelay.v 26 | ../rtl/ex/fwb_counter.v 27 | ../rtl/ex/fwb_master.v 28 | ../rtl/ex/fwb_slave.v 29 | ../rtl/ex/sfifo.v 30 | ../rtl/ex/skidbuffer.v 31 | ../rtl/ex/wbarbiter.v 32 | ../rtl/ex/wbdblpriarb.v 33 | ../rtl/ex/wbpriarbiter.v 34 | ../rtl/peripherals/icontrol.v 35 | ../rtl/zipdma/zipdma.v 36 | ../rtl/zipdma/zipdma_ctrl.v 37 | ../rtl/zipdma/zipdma_fsm.v 38 | ../rtl/zipdma/zipdma_mm2s.v 39 | ../rtl/zipdma/zipdma_rxgears.v 40 | ../rtl/zipdma/zipdma_txgears.v 41 | ../rtl/zipdma/zipdma_s2mm.v 42 | ../rtl/peripherals/wbwatchdog.v 43 | ../rtl/peripherals/zipcounter.v 44 | ../rtl/peripherals/zipjiffies.v 45 | ../rtl/peripherals/ziptimer.v 46 | -------------------------------------------------------------------------------- /sim/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | zipsys_coverage/ 2 | div_tb 3 | mpy_tb 4 | *debug.txt 5 | *dump.txt 6 | pdump 7 | mkhex 8 | zippy_tb 9 | pfcache_tb 10 | zipmmu_tb 11 | pfile.bin 12 | *.info 13 | vlt_coverage.dat 14 | -------------------------------------------------------------------------------- /sim/verilator/README.md: -------------------------------------------------------------------------------- 1 | ## The ZipCPU's Simulator 2 | 3 | This directory contains the basic ZipCPU simulator. 4 | 5 | Ok, even this isn't the *best* simulator of the ZipCPU. While this simulator 6 | *is* fully functional, it only simulates the 7 | [ZipCPU](../../rtl/core/zipcpu.v), encased in either the 8 | [ZipSystem](../../rtl/zipsystem.v) 9 | or the [ZipBones](../../rtl/zipbones.v), 10 | plus [memory](memsim.cpp). This simulator doesn't handle any interactions 11 | with the 12 | [flash](http://opencores.org/project,qspiflash), the 13 | [serial port](https://github.com/ZipCPU/wbuart32), the 14 | [SD-card](https://github.com/ZipCPU/sdspi), etc. All of these interactions 15 | (and more) are available from the 16 | [simulator](https://github.com/ZipCPU/zbasic/tree/master/sim/verilated) 17 | within the 18 | [ZBasic repository](https://github.com/ZipCPU/zbasic). 19 | 20 | However, this simulator *is* very basic to the CPU's functionality. If you 21 | just want to know if the CPU works by itself, if it can properly execute the 22 | instructions given to it--even to the point of testing 23 | interrupts etc, then this simulation will work. It's just not fully 24 | functional for testing all of the other peripheral components necessary 25 | to make a CPU useful. 26 | -------------------------------------------------------------------------------- /sim/verilator/byteswap.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/verilator/byteswap.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: To convert between little endian and big endian byte orders, 8 | // and to handle conversions between character strings and 9 | // bit-endian words made from those characters. 10 | // 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #ifndef BYTESWAP_H 42 | #define BYTESWAP_H 43 | 44 | #include 45 | 46 | /* 47 | * The byte swapping routines below are designed to support conversions from a 48 | * little endian machine/host (such as my PC) to the big endian byte order used 49 | * on the ZipCPU. If the current machine is already little endian, no byte 50 | * swapping is required. 51 | */ 52 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 53 | /* 54 | * byteswap 55 | * 56 | * Given a big (or little) endian word, return a little (or big) endian word. 57 | */ 58 | extern uint32_t 59 | byteswap(uint32_t v); 60 | 61 | /* 62 | * byteswapbuf 63 | * 64 | * To swap from the byte order of every 32-bit word in the given buffer. 65 | */ 66 | extern void byteswapbuf(int ln, uint32_t *buf); 67 | 68 | #else 69 | #define byteswap(A) (A) 70 | #define byteswapbuf(A, B) 71 | #endif 72 | 73 | /* 74 | * buildword 75 | * 76 | * Given a pointer within an array of characters, build a 32-bit big-endian 77 | * word from those characters. Does not require the character pointer to be 78 | * aligned. 79 | */ 80 | extern uint32_t buildword(const unsigned char *p); 81 | 82 | /* 83 | * buildswap 84 | * 85 | * Same as buildword, except that we build a little endian word from the 86 | * characters given to us. Hence the first character is the low order octet 87 | * of the word. 88 | */ 89 | extern uint32_t buildswap(const unsigned char *p); 90 | 91 | #endif 92 | -------------------------------------------------------------------------------- /sim/verilator/memsim.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/verilator/memsim.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: This creates a memory like device to act on a WISHBONE bus. 8 | // It doesn't exercise the bus thoroughly, but does give some 9 | // exercise to the bus to see whether or not the bus master can control it. 10 | // 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #ifndef MEMSIM_H 42 | #define MEMSIM_H 43 | 44 | class MEMSIM { 45 | public: 46 | typedef unsigned int BUSW; 47 | typedef unsigned char uchar; 48 | 49 | BUSW *m_mem, m_len, m_mask; 50 | int m_nxt_ack; 51 | BUSW m_nxt_data; 52 | 53 | 54 | MEMSIM(const unsigned int nwords); 55 | ~MEMSIM(void); 56 | void load(const char *fname); 57 | void load(const unsigned addr, const char *buf,const unsigned len); 58 | void apply(const uchar wb_cyc, const uchar wb_stb, 59 | const uchar wb_we, 60 | const BUSW wb_addr, const BUSW wb_data, 61 | const uchar wb_sel, 62 | uchar &o_ack, uchar &o_stall, BUSW &o_data); 63 | void operator()(const uchar wb_cyc, const uchar wb_stb, 64 | const uchar wb_we, 65 | const BUSW wb_addr, const BUSW wb_data, 66 | const uchar wb_sel, 67 | uchar &o_ack, uchar &o_stall, BUSW &o_data) { 68 | apply(wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel, o_ack, o_stall, o_data); 69 | } 70 | BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; } 71 | }; 72 | 73 | #endif 74 | -------------------------------------------------------------------------------- /sim/verilator/twoc.cpp: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/verilator/twoc.cpp 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: Some various two's complement related C++ helper routines. 8 | // Specifically, these help extract signed numbers from 9 | // packed bitfields, while guaranteeing that the upper bits are properly 10 | // sign extended (or not) as desired. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #include "twoc.h" 42 | 43 | // sbits 44 | // {{{ 45 | long sbits(const long val, const int bits) { 46 | long r; 47 | 48 | r = val & ((1l< for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #ifndef TWOC_H 42 | #define TWOC_H 43 | 44 | extern long sbits(const long val, const int bits); 45 | extern unsigned long ubits(const long val, const int bits); 46 | 47 | #endif 48 | 49 | -------------------------------------------------------------------------------- /sim/verilator/vversion.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ################################################################################ 3 | ## 4 | ## Filename: sim/verilator/vversion.sh 5 | ## {{{ 6 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 7 | ## 8 | ## Purpose: To determine whether or not the verilator prefix for internal 9 | ## variables is v__DOT__ or the name of the top level followed by 10 | ## __DOT__. If it is the later, output -DNEW_VERILATOR, else be silent. 11 | ## 12 | ## 13 | ## Creator: Dan Gisselquist, Ph.D. 14 | ## Gisselquist Technology, LLC 15 | ## 16 | ################################################################################ 17 | ## }}} 18 | ## Copyright (C) 2017-2025, Gisselquist Technology, LLC 19 | ## {{{ 20 | ## This program is free software (firmware): you can redistribute it and/or 21 | ## modify it under the terms of the GNU General Public License as published 22 | ## by the Free Software Foundation, either version 3 of the License, or (at 23 | ## your option) any later version. 24 | ## 25 | ## This program is distributed in the hope that it will be useful, but WITHOUT 26 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 27 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 28 | ## for more details. 29 | ## 30 | ## You should have received a copy of the GNU General Public License along 31 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 32 | ## target there if the PDF file isn't present.) If not, see 33 | ## for a copy. 34 | ## }}} 35 | ## License: GPL, v3, as defined and found on www.gnu.org, 36 | ## {{{ 37 | ## http://www.gnu.org/licenses/gpl.html 38 | ## 39 | ################################################################################ 40 | ## 41 | ## }}} 42 | if [[ x${VERILATOR_ROOT} != "x" && -x ${VERILATOR_ROOT}/bin/verilator ]]; 43 | then 44 | export VERILATOR=${VERILATOR_ROOT}/bin/verilator 45 | fi 46 | if [[ ! -x ${VERILATOR} ]]; 47 | then 48 | export VERILATOR=verilator 49 | fi 50 | if [[ ! -x `which ${VERILATOR}` ]]; 51 | then 52 | echo "Verilator not found in environment or in path" 53 | exit -1 54 | fi 55 | 56 | VVERLINE=`${VERILATOR} -V | grep -i ^Verilator` 57 | VVER=`echo ${VVERLINE} | cut -d " " -f 2` 58 | LATER=`echo $VVER \>= 3.9 | bc` 59 | if [[ $LATER > 0 ]]; 60 | then 61 | RLATER=`echo $VVER \>= 4.2 | bc` 62 | if [[ $RLATER > 0 ]]; 63 | then 64 | ## I'm not quite certain when Verilator started requiring a further 65 | ## subreference through rootp-> and including the Vdesgin___024root.h 66 | ## include file. My best guess is that it is Verilator 4.2, but I don't 67 | ## know that for certain. What I do know is that on the development 68 | ## verrsion 4.211, it requires different semantics to peek at register 69 | ## names. This is our attempt to capture that dependency. 70 | echo "-DROOT_VERILATOR" 71 | else 72 | echo "-DNEW_VERILATOR" 73 | fi 74 | else 75 | echo "-DOLD_VERILATOR" 76 | fi 77 | exit 0 78 | -------------------------------------------------------------------------------- /sim/verilator/zipelf.cpp: -------------------------------------------------------------------------------- 1 | ../cpp/zipelf.cpp -------------------------------------------------------------------------------- /sim/verilator/zipelf.h: -------------------------------------------------------------------------------- 1 | ../cpp/zipelf.h -------------------------------------------------------------------------------- /sim/zip-sim.exp: -------------------------------------------------------------------------------- 1 | # 2 | set_board_info target_install "{zip}" 3 | 4 | # Load the generic configuration for the board. This will define a basic 5 | # set of routines needed by the tool to communicate with the board. 6 | load_generic_config "sim" 7 | 8 | 9 | # basic-sim.exp is a basic description for the standard Cygnus simulator 10 | load_base_board_description "basic-sim" 11 | 12 | # zip is the name of the sim subdir 13 | setup_sim zip 14 | 15 | # No multilib options needed by default 16 | process_multilib_options "" 17 | 18 | # The compiler used to build for this board. This has *nothing* to do with what 19 | # compiler is tested if we're testing gcc. 20 | set_board_info compiler "[find_gcc]" 21 | 22 | # We only support newlib on this targte. 23 | # However, we include libgloss so we can find the linker scripts 24 | set_board_info cflags "[newlib_include_flags] [libgloss_include_flags]" 25 | set_board_info ldflags "[newlib_link_flags] -lzipbasic" 26 | 27 | # For now, the simulator won't return an exit status and we'll need to indicate 28 | # this, the standard GCC wrapper will work with this target. 29 | set_board_info needs_status_wrapper 1 30 | 31 | # The linker script for this board 32 | set_board_info ldscript "-Tzipsim.ld" 33 | 34 | # Can't pass arguments to this target 35 | set_board_info noargs 1 36 | 37 | # No signals 38 | set_board_info gdb,nosignals 1 39 | # Cant return results 40 | set_board_info gdb,noresults 1 41 | # Doesnt do inferiori 42 | set_board_info gdb,noinferiorio 1 43 | 44 | # And it can't call functions 45 | set_board_info gdb,cannot_call_functions 1 46 | 47 | 48 | # 49 | # 50 | # Okay, so some of my own fields here 51 | # 52 | # First, the command to run the ZipCPU simulator 53 | set_board_info sim zip-sim 54 | set_board_info objcopy zip-objcopy 55 | set_board_info is_simulator 1 56 | set_board_info gdb,reload_on_run 1 57 | 58 | 59 | -------------------------------------------------------------------------------- /sim/zipsw/.gitignore: -------------------------------------------------------------------------------- 1 | *.hex 2 | cputest 3 | dmatest 4 | hello 5 | hellosim 6 | hellpsmp 7 | hellostep 8 | lockcheck 9 | locksmp 10 | clkgatechk 11 | stepchk 12 | *.txt 13 | -------------------------------------------------------------------------------- /sim/zipsw/README.md: -------------------------------------------------------------------------------- 1 | ## ZipCPU Simulation Software 2 | 3 | This directory contains a set of files that may be used when running simulation 4 | based tests on the CPU. These tests include: 5 | 6 | - [cputest.c](cputest.c): The primary CPU smoke testing program, designed to 7 | exercise all features of the CPU in any current configuration. 8 | 9 | - [hellosim.s](hellosim.s): Tests the SOUT/NOUT instruction set of the ZipCPU. 10 | A very basic program. This will likely succeed and pass even if the 11 | [cputest.c](cputest.c) does not. 12 | 13 | - [hello.c](hello.c): You basic "Hello World" program. This offers a basic 14 | (although not complete) test of the C-library. 15 | 16 | - [hellostep.c](hellostep.c): A modified "Hello, World" program designed to test 17 | if the stepping mode of the CPU works. Specifically, when running this test, 18 | the supervisor will step the Hello World program one instruction at a time. 19 | If the program still works, we'll assume stepping worked as designed. 20 | 21 | - [lockcheck.c](lockcheck.c): Designed to test the ZipCPU's "LOCK" instruction, 22 | this test creates a set of ZipCPU tasks, and then tries to execute those 23 | tasks one instruction at a time. Each task attempts to grab a MUTEX, and 24 | then enter a MUTEX controlled section, increment a counter, and then release 25 | the MUTEX. Each task is stepped one instruction at a time as an attempt to 26 | stress this capability. 27 | 28 | -------------------------------------------------------------------------------- /sim/zipsw/board.ld: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * 3 | * Filename: bkram.ld 4 | * {{{ 5 | * Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | * 7 | * Creator: Dan Gisselquist, Ph.D. 8 | * Gisselquist Technology, LLC 9 | * 10 | /******************************************************************************* 11 | * }}} 12 | * Copyright (C) 2017-2024, Gisselquist Technology, LLC 13 | * {{{ 14 | * This program is free software (firmware): you can redistribute it and/or 15 | * modify it under the terms of the GNU General Public License as published 16 | * by the Free Software Foundation, either version 3 of the License, or (at 17 | * your option) any later version. 18 | * 19 | * This program is distributed in the hope that it will be useful, but WITHOUT 20 | * ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 22 | * for more details. 23 | * 24 | * You should have received a copy of the GNU General Public License along 25 | * with this program. (It's in the $(ROOT)/doc directory. Run make with no 26 | * target there if the PDF file isn't present.) If not, see 27 | * for a copy. 28 | * }}} 29 | * License: GPL, v3, as defined and found on www.gnu.org, 30 | * {{{ 31 | * http://www.gnu.org/licenses/gpl.html 32 | * 33 | /******************************************************************************* 34 | * 35 | * }}} 36 | */ 37 | ENTRY(_start) 38 | 39 | MEMORY 40 | { 41 | /* To be listed here, a slave must be of type MEMORY. If the slave 42 | * has a defined name in its @LD.NAME tag, it will be listed here 43 | * under that name, otherwise it will be listed under it's 44 | * @$(PREFIX) tag with an underscore prepended to it. The permissions 45 | * are given by the @LD.PERM tag. Allowable permissions include 46 | * 'r' (read only), 'rx' (read and execute, but no writes), 47 | * 'wx' (read, write, and execute). If no permission tag exists, a 48 | * permission of 'r' will be assumed. 49 | */ 50 | bkram(wx) : ORIGIN = 0x04000000, LENGTH = 0x04000000 51 | } 52 | 53 | /* For each defined memory peripheral, we also define a pointer to that 54 | * memory. The name of this pointer is given by the @LD.NAME tag within 55 | * the memory peripheral's configuration 56 | */ 57 | _bkram = ORIGIN(bkram); 58 | /* LD.DEFNS from mem_bkram_only */ 59 | _kram = 0; /* No high-speed kernel RAM */ 60 | _ram = ORIGIN(bkram); 61 | _rom = 0; 62 | _top_of_stack = ORIGIN(bkram) + LENGTH(bkram); 63 | 64 | 65 | /* LD.SCRIPT from mem_bkram_only */ 66 | SECTIONS 67 | { 68 | .ramcode ORIGIN(bkram) : ALIGN(4) { 69 | _boot_address = .; 70 | _kram_start = .; 71 | _kram_end = .; 72 | _ram_image_start = . ; 73 | *(.start) *(.boot) 74 | *(.kernel) 75 | *(.text.startup) 76 | *(.text*) 77 | *(.rodata*) *(.strings) 78 | *(.data) *(COMMON) 79 | }> bkram 80 | _ram_image_end = . ; 81 | .bss : ALIGN_WITH_INPUT { 82 | *(.bss) 83 | _bss_image_end = . ; 84 | } > bkram 85 | _top_of_heap = .; 86 | } 87 | 88 | -------------------------------------------------------------------------------- /sim/zipsw/hello.c: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/zipsw/hello.c 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: The original Helllo World program. If everything works, this 8 | // will print Hello World to the UART, and then halt the CPU--if 9 | // run with no O/S. 10 | // 11 | // 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // }}} 14 | // Gisselquist Technology asserts no ownership rights over this particular 15 | // hello world program. 16 | // {{{ 17 | //////////////////////////////////////////////////////////////////////////////// 18 | // 19 | // }}} 20 | #include 21 | 22 | int main(int argc, char **argv) { 23 | printf("Hello, World!\n"); 24 | } 25 | -------------------------------------------------------------------------------- /sim/zipsw/hellosim.s: -------------------------------------------------------------------------------- 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2 | ;; 3 | ;; Filename: sim/zipsw/hellosim.s 4 | ;; {{{ 5 | ;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ;; 7 | ;; Purpose: Hello World, only using the SIM instructions, as an initial 8 | ;; test of whether or not the special SIM instructions even work. 9 | ;; 10 | ;; 11 | ;; Creator: Dan Gisselquist, Ph.D. 12 | ;; Gisselquist Technology, LLC 13 | ;; 14 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 15 | ;; }}} 16 | ;; Copyright (C) 2017-2022, Gisselquist Technology, LLC 17 | ;; {{{ 18 | ;; This program is free software (firmware): you can redistribute it and/or 19 | ;; modify it under the terms of the GNU General Public License as published 20 | ;; by the Free Software Foundation, either version 3 of the License, or (at 21 | ;; your option) any later version. 22 | ;; 23 | ;; This program is distributed in the hope that it will be useful, but WITHOUT 24 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | ;; for more details. 27 | ;; 28 | ;; You should have received a copy of the GNU General Public License along 29 | ;; with this program. (It's in the $(ROOT)/doc directory. Run make with no 30 | ;; target there if the PDF file isn't present.) If not, see 31 | ;; for a copy. 32 | ;; }}} 33 | ;; License: GPL, v3, as defined and found on www.gnu.org, 34 | ;; {{{ 35 | ;; http://www.gnu.org/licenses/gpl.html 36 | ;; 37 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 38 | ;; 39 | ;; }}} 40 | .section .start, "ax" 41 | .global _start 42 | _start: 43 | NOUT 'H' 44 | NOUT 'e' 45 | NOUT 'l' 46 | NOUT 'l' 47 | NOUT 'o' 48 | NOUT ' ' 49 | NOUT 'W' 50 | NOUT 'o' 51 | NOUT 'r' 52 | NOUT 'l' 53 | NOUT 'd' 54 | NOUT '!' 55 | NOUT '\r' 56 | NOUT '\n' 57 | NEXIT 0 58 | HALT 59 | BUSY 60 | -------------------------------------------------------------------------------- /sim/zipsw/hellostep.c: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/zipsw/hellostep.c 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: This is a modified version of the original hello world. As 8 | // with the original, if all goes well this program will print 9 | // Hello World to the UART, and then halt the CPU. Behind the scenes, 10 | // what makes this program special is that the supervisor is stepping 11 | // through the Hello World program, one instruction at a time. Thus, this 12 | // program is a test of the ZipCPU's stepping capabilities. 13 | // 14 | // Creator: Dan Gisselquist, Ph.D. 15 | // Gisselquist Technology, LLC 16 | // 17 | //////////////////////////////////////////////////////////////////////////////// 18 | // }}} 19 | // Copyright (C) 2021-2025, Gisselquist Technology, LLC 20 | // {{{ 21 | // This program is free software (firmware): you can redistribute it and/or 22 | // modify it under the terms of the GNU General Public License as published 23 | // by the Free Software Foundation, either version 3 of the License, or (at 24 | // your option) any later version. 25 | // 26 | // This program is distributed in the hope that it will be useful, but WITHOUT 27 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 28 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 29 | // for more details. 30 | // 31 | // You should have received a copy of the GNU General Public License along 32 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 33 | // target there if the PDF file isn't present.) If not, see 34 | // for a copy. 35 | // }}} 36 | // License: GPL, v3, as defined and found on www.gnu.org, 37 | // {{{ 38 | // http://www.gnu.org/licenses/gpl.html 39 | // 40 | //////////////////////////////////////////////////////////////////////////////// 41 | // 42 | // }}} 43 | #include 44 | #include "zipcpu.h" 45 | #include "txfns.h" 46 | 47 | void user_main(void) { 48 | printf("Hello, World!\n"); 49 | zip_syscall(); 50 | } 51 | 52 | int main(int argc, char **argv) { 53 | int done = 0, success = 1; 54 | unsigned user_regs[16]; 55 | unsigned user_stack[512]; 56 | 57 | for(unsigned k=0; k<16; k++) 58 | user_regs[k] = 0; 59 | user_regs[15] = (unsigned)user_main; 60 | user_regs[14] = CC_STEP; 61 | user_regs[13] = (unsigned)&user_stack[512]; 62 | zip_restore_context(user_regs); 63 | 64 | while(!done) { 65 | unsigned ucc; 66 | 67 | zip_rtu(); 68 | 69 | ucc = zip_ucc(); 70 | if (ucc & CC_EXCEPTION) { 71 | txstr("\r\nEXCEPTION: CC = ");txhex(ucc); txstr("\r\n"); 72 | txstr("\r\n"); 73 | while((_uart->u_fifo & 0x010000) == 0) 74 | ; 75 | done = 1; 76 | success = 0; 77 | } if (ucc & CC_TRAP) 78 | done = 1; 79 | else if ((ucc & CC_STEP) == 0) { 80 | success = 0; 81 | txstr("\r\nCC & STEP == 0 ?? CC = "); txhex(ucc); 82 | txstr("\r\n"); 83 | while((_uart->u_fifo & 0x010000) == 0) 84 | ; 85 | } 86 | } 87 | 88 | if (success) 89 | txstr("\r\n\r\nSUCCESS!\r\n"); 90 | } 91 | -------------------------------------------------------------------------------- /sim/zipsw/txfns.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/zipsw/txfns.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: These are some *very* simple UART routines, designed to support 8 | // a program before the C-library is up and running. Once the 9 | // C-library is running on a device, it is anticipated that these routines 10 | // will no longer be needed or used--since they access the raw hardware 11 | // device(s). 12 | // 13 | // Creator: Dan Gisselquist, Ph.D. 14 | // Gisselquist Technology, LLC 15 | // 16 | //////////////////////////////////////////////////////////////////////////////// 17 | // }}} 18 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 19 | // {{{ 20 | // This program is free software (firmware): you can redistribute it and/or 21 | // modify it under the terms of the GNU General Public License as published 22 | // by the Free Software Foundation, either version 3 of the License, or (at 23 | // your option) any later version. 24 | // 25 | // This program is distributed in the hope that it will be useful, but WITHOUT 26 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 27 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 28 | // for more details. 29 | // 30 | // You should have received a copy of the GNU General Public License along 31 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 32 | // target there if the PDF file isn't present.) If not, see 33 | // for a copy. 34 | // }}} 35 | // License: GPL, v3, as defined and found on www.gnu.org, 36 | // {{{ 37 | // http://www.gnu.org/licenses/gpl.html 38 | // 39 | //////////////////////////////////////////////////////////////////////////////// 40 | // 41 | // }}} 42 | #ifndef TXFNS_H 43 | #define TXFNS_H 44 | 45 | #include "board.h" 46 | 47 | extern void txchr(char ch); 48 | extern void txstr(const char *str); 49 | extern void txhex(unsigned val); 50 | extern void txdecimal(int val); 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /sim/zipsw/zlib/Makefile: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | ## 3 | ## Filename: sim/zipsw/zlib/Makefile 4 | ## {{{ 5 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | ## 7 | ## Purpose: To guide/direct the build of the board-specific portion of 8 | ## newlib. In this case, the "board" is the test bench we are 9 | ## testing with. 10 | ## 11 | ## Targets: 12 | ## 13 | ################################################################################ 14 | ## }}} 15 | ## Copyright (C) 2017-2025, Gisselquist Technology, LLC 16 | ## {{{ 17 | ## This program is free software (firmware): you can redistribute it and/or 18 | ## modify it under the terms of the GNU General Public License as published 19 | ## by the Free Software Foundation, either version 3 of the License, or (at 20 | ## your option) any later version. 21 | ## 22 | ## This program is distributed in the hope that it will be useful, but WITHOUT 23 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | ## for more details. 26 | ## 27 | ## You should have received a copy of the GNU General Public License along 28 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | ## target there if the PDF file isn't present.) If not, see 30 | ## for a copy. 31 | ## }}} 32 | ## License: GPL, v3, as defined and found on www.gnu.org, 33 | ## {{{ 34 | ## http://www.gnu.org/licenses/gpl.html 35 | ## 36 | ################################################################################ 37 | ## 38 | ## }}} 39 | CC := zip-gcc 40 | AR := zip-ar 41 | OBJDIR := obj-zip 42 | INCS := -I. -I.. 43 | CFLAGS := -O3 $(INCS) 44 | LIBSRCS := udiv.c umod.c syscalls.c crt0.c 45 | LIBOBJS := $(addprefix $(OBJDIR)/,$(subst .c,.o,$(LIBSRCS))) 46 | ZIPLIB := libziptb.a 47 | all: $(ZIPLIB) 48 | 49 | $(OBJDIR)/%.o: %.c 50 | $(mk-objdir) 51 | $(CC) $(CFLAGS) -c $< -o $@ 52 | 53 | $(OBJDIR)/%.s: %.c 54 | $(mk-objdir) 55 | $(CC) $(CFLAGS) -fdump-rtl-all -S $< -o $@ 56 | 57 | $(OBJDIR)/crt0.o: crt0.c 58 | $(mk-objdir) 59 | $(CC) $(CFLAGS) -ffreestanding -c $< -o $@ 60 | 61 | $(ZIPLIB): $(LIBOBJS) 62 | $(AR) -cru $@ $(LIBOBJS) 63 | 64 | clean: 65 | rm -rf $(ZIPLIB) $(OBJDIR)/ 66 | 67 | define mk-objdir 68 | @bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi" 69 | endef 70 | 71 | define build-depends 72 | @echo "Building dependency file(s)" 73 | $(mk-objdir) 74 | @$(CC) $(CFLAGS) -MM $(LIBSRCS) > $(OBJDIR)/xdepends.txt 75 | @sed -e 's/^.*.o: /$(OBJDIR)\/&/' < $(OBJDIR)/xdepends.txt > $(OBJDIR)/depends.txt 76 | @rm $(OBJDIR)/xdepends.txt 77 | endef 78 | 79 | tags: $(LIBSRCS) $(HEADERS) 80 | @echo "Generating tags" 81 | @ctags $(LIBSRCS) $(HEADERS) 82 | 83 | 84 | .PHONY: depends 85 | depends: tags 86 | $(build-depends) 87 | 88 | $(OBJDIR)/depends.txt: $(SOURCES) $(HEADERS) 89 | $(build-depends) 90 | 91 | -include $(OBJDIR)/depends.txt 92 | -------------------------------------------------------------------------------- /sim/zipsw/zlib/README.md: -------------------------------------------------------------------------------- 1 | ## C-Library, CPU Specific Glue Logic 2 | 3 | The CPU library requires some CPU specific glue logic. This directory 4 | contains that glue logic. Most of the logic is specific to the *board* 5 | or *design*, rather than the CPU. When porting to a new design, two 6 | files need to be adjusted: 7 | 8 | - [syscalls.c](syscalls.c): Needs to be adjusted for the location and details 9 | of the console, and any other external peripherals which may be connected 10 | to the CPU. 11 | 12 | - [bootloader.h](bootloader.h): While this file doesn't need to be updated 13 | per se, the values within it need to be address locations by the linker 14 | script--not included here--in order for the CPU loader, 15 | [crt0.c](crt0.c), to work. 16 | 17 | -------------------------------------------------------------------------------- /sim/zipsw/zlib/bootloader.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/zipsw/zlib/bootloader.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: 8 | // 9 | // 10 | // Creator: Dan Gisselquist, Ph.D. 11 | // Gisselquist Technology, LLC 12 | // 13 | //////////////////////////////////////////////////////////////////////////////// 14 | // }}} 15 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 16 | // {{{ 17 | // This program is free software (firmware): you can redistribute it and/or 18 | // modify it under the terms of the GNU General Public License as published 19 | // by the Free Software Foundation, either version 3 of the License, or (at 20 | // your option) any later version. 21 | // 22 | // This program is distributed in the hope that it will be useful, but WITHOUT 23 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 24 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 | // for more details. 26 | // 27 | // You should have received a copy of the GNU General Public License along 28 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 29 | // target there if the PDF file isn't present.) If not, see 30 | // for a copy. 31 | // }}} 32 | // License: GPL, v3, as defined and found on www.gnu.org, 33 | // {{{ 34 | // http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////////////////////// 37 | // 38 | // }}} 39 | #ifndef BOOTLOADER_H 40 | #define BOOTLOADER_H 41 | 42 | extern int _top_of_heap[1], _top_of_stack[1]; 43 | extern int _boot_address[1]; 44 | 45 | extern int _ram[1], _rom[1], _kram[1]; 46 | 47 | extern int _boot_address[1], 48 | _kram_start[1], _kram_end[1], 49 | _ram_image_start[1], _ram_image_end[1], 50 | _bss_image_end[1]; 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /sim/zipsw/zlib/umod.c: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sim/zipsw/zlib/umod.c 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: This is a temporary file--a crutch if you will--until a similar 8 | // capability is merged into GCC. Right now, GCC has no way of 9 | // taking the module of two 64-bit numbers, and this routine provides that 10 | // capability. 11 | // 12 | // This routine is required by and used by newlib's printf in order to 13 | // print decimal numbers (%d) to an IO stream. 14 | // 15 | // Once gcc is properly patched, this will be removed from the 16 | // repository. 17 | // 18 | // Creator: Dan Gisselquist, Ph.D. 19 | // Gisselquist Technology, LLC 20 | // 21 | //////////////////////////////////////////////////////////////////////////////// 22 | // }}} 23 | // Copyright (C) 2017-2025, Gisselquist Technology, LLC 24 | // {{{ 25 | // This program is free software (firmware): you can redistribute it and/or 26 | // modify it under the terms of the GNU General Public License as published 27 | // by the Free Software Foundation, either version 3 of the License, or (at 28 | // your option) any later version. 29 | // 30 | // This program is distributed in the hope that it will be useful, but WITHOUT 31 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 32 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 33 | // for more details. 34 | // 35 | // You should have received a copy of the GNU General Public License along 36 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 37 | // target there if the PDF file isn't present.) If not, see 38 | // for a copy. 39 | // }}} 40 | // License: GPL, v3, as defined and found on www.gnu.org, 41 | // {{{ 42 | // http://www.gnu.org/licenses/gpl.html 43 | // 44 | //////////////////////////////////////////////////////////////////////////////// 45 | // 46 | // }}} 47 | #include 48 | 49 | 50 | unsigned long __udivdi3(unsigned long, unsigned long); 51 | 52 | __attribute((noinline)) 53 | unsigned long __umoddi3(unsigned long a, unsigned long b) { 54 | unsigned long r; 55 | 56 | // Return a modulo b, or a%b in C syntax 57 | r = __udivdi3(a, b); 58 | r = r * b; 59 | r = a - r; 60 | return r; 61 | } 62 | 63 | -------------------------------------------------------------------------------- /sw/.gitignore: -------------------------------------------------------------------------------- 1 | install/ 2 | binutils-2.25/ 3 | binutils-2.27/ 4 | binutils-2.27-zip/ 5 | build-gas/ 6 | build-gcc/ 7 | build-nlib/ 8 | gcc-6.2.0/ 9 | gcc-6.2.0-zip/ 10 | gcc-10.3.0/ 11 | gcc-10.3.0-zip/ 12 | gcc-*.tar.*z 13 | newlib-2.5.0/ 14 | newlib-2.5.0-zip/ 15 | newlib-4.1.0/ 16 | newlib-4.1.0-zip/ 17 | newlib-*.tar.*z 18 | 2017*.patch 19 | lib/ 20 | zipos/ 21 | zlibc/ 22 | -------------------------------------------------------------------------------- /sw/README.md: -------------------------------------------------------------------------------- 1 | This directory contains the source code for the ZipCPU tool-chain--the 2 | GCC back end, assembler, and linker. The directory also has the patches 3 | necessary to build the C-library, newlib. This tool-chain is kept in a series 4 | of patch files--primarily because I found the patch files for the eco32 5 | CPU *very* helpful to me when I needed to know where to start when building 6 | the back end for the ZipCPU. 7 | 8 | You'll also find within this directory the [Makefile](Makefile) used to 9 | direct the build of this tool-chain, together with basic scripts for building 10 | [GCC](gcc-script.sh), [binutils](gas-script.sh), and [newlib](nlib-script.sh). 11 | 12 | If you run into trouble building these components, know this: the 13 | [Makefile](Makefile) works off of the existence of nonce.txt files to know 14 | how to proceed from one step to the next. Hence, as an example, when building 15 | the binutils components, it will start by applying patches to the binutils 16 | repository found within here. Once completed, it will place a nonce.txt 17 | file into the resulting (patched) directory. It will then attempt to 18 | configure binutils. Once done, there will be a `build-gas` directory with 19 | a `nonce.txt` file within it. This will be `make`s indication to move forward 20 | and build the compiler. If you have any problems with building, or if you want 21 | to start the build over, feel free to either remove the patched directories, 22 | or even to just remove the (empty) `nonce.txt` files and have `make` 23 | start over. 24 | 25 | ## Common problems building the toolchain 26 | 27 | The most common problem people have had is the result of not having the 28 | pre-requisites properly installed on your computer. Sadly, in this case, 29 | the makefile will exit with some confusing error. You'll need to find the 30 | `config.log` file of the component that didn't build to find out what is 31 | missing. 32 | 33 | Another common error is that GCC needs the cross-built GCC to build it's 34 | libraries. Hence, you may need to make certain that the install'ed binary 35 | directory is in your path. I've tried to clean this up so that the 36 | tool-chain Makefile doesn't require this, but certainly the builds of any 37 | assembly or C related files will require it. 38 | 39 | ## Installed location 40 | 41 | Currently, the tool-chain as configured does not install into your system 42 | directories, but rather into an `install` directory that will be built as a 43 | subset of this one. This behavior is controlled by the `prefix` flags within 44 | the various build scripts, which in turn is set by a Makefile variable. 45 | Should you wish to change this behavior, just remember that the install 46 | to the system directory will require sys-admin privileges, and it may also 47 | require you to build the various components manually rather than via the 48 | make script. (It's not something I've tested.) 49 | 50 | -------------------------------------------------------------------------------- /sw/binutils-2.27.tar.bz2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ZipCPU/zipcpu/8f12b101e3d9e8963395fd13bbd7f4d77f0b8e2b/sw/binutils-2.27.tar.bz2 -------------------------------------------------------------------------------- /sw/gas-script.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ################################################################################ 3 | ## 4 | ## Filename: sw/gas-script.sh 5 | ## {{{ 6 | ## Project: Zip CPU -- a small, lightweight, RISC CPU soft core 7 | ## 8 | ## Purpose: To configure binutils to properly build the binutils portion of 9 | ## the ZipCPU toolchain. 10 | ## 11 | ## Creator: Dan Gisselquist, Ph.D. 12 | ## Gisselquist Technology, LLC 13 | ## 14 | ################################################################################ 15 | ## }}} 16 | ## Copyright (C) 2016-2025, Gisselquist Technology, LLC 17 | ## {{{ 18 | ## This program is free software (firmware): you can redistribute it and/or 19 | ## modify it under the terms of the GNU General Public License as published 20 | ## by the Free Software Foundation, either version 3 of the License, or (at 21 | ## your option) any later version. 22 | ## 23 | ## This program is distributed in the hope that it will be useful, but WITHOUT 24 | ## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 25 | ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 26 | ## for more details. 27 | ## 28 | ## You should have received a copy of the GNU General Public License along 29 | ## with this program. (It's in the $(ROOT)/doc directory. Run make with no 30 | ## target there if the PDF file isn't present.) If not, see 31 | ## for a copy. 32 | ## }}} 33 | ## License: GPL, v3, as defined and found on www.gnu.org, 34 | ## {{{ 35 | ## http://www.gnu.org/licenses/gpl.html 36 | ## 37 | ################################################################################ 38 | ## 39 | ## }}} 40 | VERSION=binutils-2.27 41 | 42 | ## Patch the original version 43 | ## {{{ 44 | if [[ ! -d $VERSION-zip/ ]] 45 | then 46 | tar -xjf ./$VERSION.tar.bz2 --transform s,$VERSION,$VERSION-zip, 47 | if [[ -e gas-zippatch.patch ]] 48 | then 49 | cd $VERSION-zip 50 | patch -p1 <../gas-zippatch.patch 51 | cd .. 52 | else 53 | echo "ZipCPU binutils patch not found" 54 | fi 55 | fi 56 | ## }}} 57 | 58 | ## Set up a install directory 59 | ## {{{ 60 | set +h 61 | set -e 62 | CLFS_HOST=$MACHTYPE 63 | CLFS_TARGET="zip" 64 | if [[ -z "$INSTALLD" ]] 65 | then 66 | INSTALLD=`pwd`/install 67 | fi 68 | INSTALL_BASE=${INSTALLD} 69 | mkdir -p ${INSTALL_BASE}/cross-tools 70 | ## }}} 71 | 72 | ## Setup a build directory 73 | ## {{{ 74 | mkdir -p build-gas 75 | echo ../$VERSION-zip/configure 76 | cd build-gas 77 | ## }}} 78 | 79 | ## Configure binutils 80 | ## {{{ 81 | AR=ar AS=as \ 82 | ../$VERSION-zip/configure --with-gas \ 83 | --prefix=${INSTALL_BASE}/cross-tools \ 84 | --target=${CLFS_TARGET} \ 85 | --disable-nls --disable-multilib \ 86 | --enable-plugins --enable-threads \ 87 | --disable-werror 88 | ## }}} 89 | -------------------------------------------------------------------------------- /sw/zasm/.gitignore: -------------------------------------------------------------------------------- 1 | zpp 2 | zdump 3 | zasm 4 | tags 5 | obj-pc/* 6 | optest.cpp 7 | sys.i 8 | -------------------------------------------------------------------------------- /sw/zasm/README.md: -------------------------------------------------------------------------------- 1 | # ZASM 2 | 3 | This directory contains the remains of the original ZipCPU assembler. This 4 | assembler has since been replaced by the GNU assembler as a part of the ZipCPU 5 | integration into binutils. 6 | 7 | Other than the zopcodes file remaining within this directory, these sources are 8 | no longer used. The zopcodes file, however, is used to support the disassembly 9 | capability within the debugger. 10 | -------------------------------------------------------------------------------- /sw/zasm/twoc.h: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sw/zasm/twoc.h 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: Some various two's complement related C++ helper routines. 8 | // Specifically, these help extract signed numbers from 9 | // packed bitfields, while guaranteeing that the upper bits 10 | // are properly sign extended (or not) as desired. 11 | // 12 | // Creator: Dan Gisselquist, Ph.D. 13 | // Gisselquist Technology, LLC 14 | // 15 | //////////////////////////////////////////////////////////////////////////////// 16 | // }}} 17 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 18 | // {{{ 19 | // This program is free software (firmware): you can redistribute it and/or 20 | // modify it under the terms of the GNU General Public License as published 21 | // by the Free Software Foundation, either version 3 of the License, or (at 22 | // your option) any later version. 23 | // 24 | // This program is distributed in the hope that it will be useful, but WITHOUT 25 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 26 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 | // for more details. 28 | // 29 | // You should have received a copy of the GNU General Public License along 30 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 31 | // target there if the PDF file isn't present.) If not, see 32 | // for a copy. 33 | // }}} 34 | // License: GPL, v3, as defined and found on www.gnu.org, 35 | // {{{ 36 | // http://www.gnu.org/licenses/gpl.html 37 | // 38 | //////////////////////////////////////////////////////////////////////////////// 39 | // 40 | // }}} 41 | #ifndef TWOC_H 42 | #define TWOC_H 43 | 44 | extern long sbits(const long val, const int bits); 45 | extern unsigned long ubits(const long val, const int bits); 46 | extern unsigned long rndbits(const long val, const int bi, const int bo); 47 | 48 | #endif 49 | 50 | -------------------------------------------------------------------------------- /sw/zasm/zdump.cpp: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // Filename: sw/zasm/zdump.cpp 4 | // {{{ 5 | // Project: Zip CPU -- a small, lightweight, RISC CPU soft core 6 | // 7 | // Purpose: Disassemble machine code files onto the stdout file. 8 | // 9 | // Creator: Dan Gisselquist, Ph.D. 10 | // Gisselquist Technology, LLC 11 | // 12 | //////////////////////////////////////////////////////////////////////////////// 13 | // }}} 14 | // Copyright (C) 2015-2025, Gisselquist Technology, LLC 15 | // {{{ 16 | // This program is free software (firmware): you can redistribute it and/or 17 | // modify it under the terms of the GNU General Public License as published 18 | // by the Free Software Foundation, either version 3 of the License, or (at 19 | // your option) any later version. 20 | // 21 | // This program is distributed in the hope that it will be useful, but WITHOUT 22 | // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 23 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 24 | // for more details. 25 | // 26 | // You should have received a copy of the GNU General Public License along 27 | // with this program. (It's in the $(ROOT)/doc directory. Run make with no 28 | // target there if the PDF file isn't present.) If not, see 29 | // for a copy. 30 | // }}} 31 | // License: GPL, v3, as defined and found on www.gnu.org, 32 | // {{{ 33 | // http://www.gnu.org/licenses/gpl.html 34 | // 35 | //////////////////////////////////////////////////////////////////////////////// 36 | // }}} 37 | #include 38 | #include 39 | #include 40 | 41 | #include "zopcodes.h" 42 | 43 | void dump_file(const bool bigend, const char *fn) { 44 | const int NZIP = 4096; 45 | char ln[NZIP], lb[NZIP]; 46 | ZIPI ibuf[NZIP]; 47 | FILE *fp; 48 | int nr; 49 | int addr=0x08000; 50 | 51 | fp = fopen(fn, "r"); 52 | if (!fp) 53 | return; 54 | printf("%s:\n", fn); 55 | while((nr=fread(ibuf, sizeof(ZIPI), NZIP, fp))>0) { 56 | for(int i=0; i>= 8; 60 | bei |= lei&0x0ff; bei<<=8; lei>>= 8; 61 | bei |= lei&0x0ff; bei<<=8; lei>>= 8; 62 | bei |= lei&0x0ff; 63 | ibuf[i] = bei; 64 | } 65 | zipi_to_string(ibuf[i], ln, lb); 66 | // printf("%s\n", ln); 67 | printf("%08x: (0x%08x %c%c%c%c) %s\n", addr++, 68 | ibuf[i], 69 | isgraph((ibuf[i]>>24)&0x0ff)?((ibuf[i]>>24)&0x0ff) : '.', 70 | isgraph((ibuf[i]>>16)&0x0ff)?((ibuf[i]>>16)&0x0ff) : '.', 71 | isgraph((ibuf[i]>> 8)&0x0ff)?((ibuf[i]>> 8)&0x0ff) : '.', 72 | isgraph((ibuf[i] )&0x0ff)?((ibuf[i] )&0x0ff) : '.', 73 | ln); 74 | if (lb[0]) 75 | printf("%28s%s\n", "", lb); 76 | } 77 | } fclose(fp); 78 | } 79 | 80 | int main(int argc, char **argv) { 81 | bool bigend = false; 82 | for(int argn=1; argn for a copy. 37 | // }}} 38 | // License: GPL, v3, as defined and found on www.gnu.org, 39 | // {{{ 40 | // http://www.gnu.org/licenses/gpl.html 41 | // 42 | //////////////////////////////////////////////////////////////////////////////// 43 | // 44 | // }}} 45 | #ifndef REGDEFS_H 46 | #define REGDEFS_H 47 | 48 | // Zip CPU Control and Debug registers 49 | #define R_ZIPCTRL 0x00000060 50 | #define R_ZIPREGS (R_ZIPCTRL+32) 51 | #define R_ZIPUSER (R_ZIPREGS+16) 52 | #define R_ZIPSYSTEM (R_ZIPCTRL+64) 53 | 54 | #define CPU_GO 0x000 55 | #define CPU_HALT 0x001 56 | #define CPU_STEP 0x004 57 | #define CPU_RESET 0x008 58 | #define CPU_CLRCACHE 0x010 59 | // 60 | #define R_ZIPS0 32 61 | #define R_ZIPSSP 45 62 | #define R_ZIPSCC 46 63 | #define R_ZIPSPC 47 64 | #define R_ZIPU0 48 65 | #define R_ZIPUSP 61 66 | #define R_ZIPUCC 62 67 | #define R_ZIPUPC 63 68 | 69 | #endif 70 | --------------------------------------------------------------------------------