├── CC2500ATTiny85Demo ├── CC2500ATTiny85Demo.ino ├── SPI85.cpp ├── SPI85.h ├── cc2500_REG.h └── cc2500_VAL.h ├── CC2500UnoDemo ├── CC2500UnoDemo.ino ├── cc2500_REG.h └── cc2500_VAL.h ├── README.md ├── Uno CC2500 Back.jpg └── Uno CC2500 Front.jpg /CC2500ATTiny85Demo/CC2500ATTiny85Demo.ino: -------------------------------------------------------------------------------- 1 | /** 2 | */ 3 | #include "cc2500_REG.h" 4 | #include "cc2500_VAL.h" 5 | #include "SPI85.h" 6 | 7 | #define CC2500_IDLE 0x36 // Exit RX / TX, turn 8 | #define CC2500_TX 0x35 // Enable TX. If in RX state, only enable TX if CCA passes 9 | #define CC2500_RX 0x34 // Enable RX. Perform calibration if enabled 10 | #define CC2500_FTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states 11 | #define CC2500_FRX 0x3A // Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states 12 | #define CC2500_TXFIFO 0x3F 13 | #define CC2500_RXFIFO 0x3F 14 | #define No_of_Bytes 6 15 | 16 | const static uint8_t MISO = PB0; 17 | const static uint8_t MOSI = PB1; 18 | const static uint8_t SCK = PB2; 19 | const static uint8_t SS = PB4; 20 | 21 | long previousMillis = 0; // will store last time data was sent 22 | long sendInterval = 400; // in milliseconds 23 | 24 | void setup(){ 25 | // Setup 26 | SPI85.begin(); 27 | SPI85.setDataMode(SPI_MODE0); 28 | SPI85.setClockDivider(SPI_2XCLOCK_MASK); 29 | pinMode(SS, OUTPUT); 30 | digitalWrite(SS, LOW); 31 | init_CC2500(); 32 | } 33 | 34 | void loop(){ 35 | unsigned long currentMillis = millis(); 36 | if(currentMillis - previousMillis > sendInterval) { 37 | previousMillis = currentMillis; 38 | sendPacket(); 39 | } 40 | //listenForPacket(); 41 | delay(20); 42 | } 43 | 44 | void listenForPacket() { 45 | SendStrobe(CC2500_RX); 46 | unsigned long currentMillis = millis(); 47 | 48 | if (digitalRead(MISO) == HIGH) { 49 | char PacketLength = ReadReg(CC2500_RXFIFO); 50 | if(No_of_Bytes == PacketLength) { 51 | char recvPacket[6]; 52 | for(int i = 1; i < PacketLength; i++){ 53 | recvPacket[i] = ReadReg(CC2500_RXFIFO); 54 | } 55 | //Serial.println(); 56 | if(recvPacket[1] == 'H' && 57 | recvPacket[2] == 'e' && 58 | recvPacket[3] == 'l' && 59 | recvPacket[4] == 'l' && 60 | recvPacket[5] == 'o') { 61 | // HELLO WORLD! 62 | } 63 | } 64 | 65 | // Make sure that the radio is in IDLE state before flushing the FIFO 66 | // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point) 67 | SendStrobe(CC2500_IDLE); 68 | // Flush RX FIFO 69 | SendStrobe(CC2500_FRX); 70 | } else { 71 | } 72 | } 73 | 74 | void sendPacket() { 75 | // Make sure that the radio is in IDLE state before flushing the FIFO 76 | SendStrobe(CC2500_IDLE); 77 | // Flush TX FIFO 78 | SendStrobe(CC2500_FTX); 79 | // prepare Packet 80 | int length = 6; 81 | unsigned char packet[length]; 82 | // First Byte = Length Of Packet 83 | packet[0] = length; 84 | packet[1] = 'H'; 85 | packet[2] = 'e'; 86 | packet[3] = 'l'; 87 | packet[4] = 'l'; 88 | packet[5] = 'o'; 89 | 90 | // SIDLE: exit RX/TX 91 | SendStrobe(CC2500_IDLE); 92 | 93 | //Serial.println("Transmitting "); 94 | for(int i = 0; i < length; i++) 95 | { 96 | WriteReg(CC2500_TXFIFO,packet[i]); 97 | } 98 | // STX: enable TX 99 | SendStrobe(CC2500_TX); 100 | // Wait for GDO0 to be set -> sync transmitted 101 | while (!digitalRead(MISO)) { 102 | } 103 | 104 | // Wait for GDO0 to be cleared -> end of packet 105 | while (digitalRead(MISO)) { 106 | } 107 | //Serial.println("Finished sending"); 108 | SendStrobe(CC2500_IDLE); 109 | } 110 | 111 | void unstick() { 112 | digitalWrite(SS,LOW); 113 | } 114 | 115 | void WriteReg(char addr, char value){ 116 | digitalWrite(SS,LOW); 117 | SPI85.transfer(addr); 118 | delay(10); 119 | SPI85.transfer(value); 120 | digitalWrite(SS,HIGH); 121 | } 122 | 123 | char ReadReg(char addr){ 124 | addr = addr + 0x80; 125 | digitalWrite(SS,LOW); 126 | char x = SPI85.transfer(addr); 127 | delay(10); 128 | char y = SPI85.transfer(0); 129 | digitalWrite(SS,HIGH); 130 | return y; 131 | } 132 | 133 | char SendStrobe(char strobe){ 134 | digitalWrite(SS,LOW); 135 | char result = SPI85.transfer(strobe); 136 | digitalWrite(SS,HIGH); 137 | delay(10); 138 | return result; 139 | } 140 | 141 | void init_CC2500(){ 142 | WriteReg(REG_IOCFG2,0x06); 143 | WriteReg(REG_IOCFG1,0x06); 144 | WriteReg(REG_IOCFG0,0x01); 145 | WriteReg(REG_FIFOTHR, 0x02); 146 | WriteReg(REG_SYNC1,VAL_SYNC1); 147 | WriteReg(REG_SYNC0,VAL_SYNC0); 148 | WriteReg(REG_PKTLEN,VAL_PKTLEN); 149 | WriteReg(REG_PKTCTRL1,0x8C); 150 | WriteReg(REG_PKTCTRL0, 0x0D); 151 | 152 | WriteReg(REG_ADDR,VAL_ADDR); 153 | WriteReg(REG_CHANNR,VAL_CHANNR); 154 | WriteReg(REG_FSCTRL1,VAL_FSCTRL1); 155 | WriteReg(REG_FSCTRL0,VAL_FSCTRL0); 156 | WriteReg(REG_FREQ2,VAL_FREQ2); 157 | WriteReg(REG_FREQ1,VAL_FREQ1); 158 | WriteReg(REG_FREQ0,VAL_FREQ0); 159 | WriteReg(REG_MDMCFG4,VAL_MDMCFG4); 160 | WriteReg(REG_MDMCFG3,VAL_MDMCFG3); 161 | WriteReg(REG_MDMCFG2,VAL_MDMCFG2); 162 | WriteReg(REG_MDMCFG1,VAL_MDMCFG1); 163 | WriteReg(REG_MDMCFG0,VAL_MDMCFG0); 164 | WriteReg(REG_DEVIATN,VAL_DEVIATN); 165 | WriteReg(REG_MCSM2,VAL_MCSM2); 166 | WriteReg(REG_MCSM1,VAL_MCSM1); 167 | WriteReg(REG_MCSM0,VAL_MCSM0); 168 | WriteReg(REG_FOCCFG,VAL_FOCCFG); 169 | 170 | WriteReg(REG_BSCFG,VAL_BSCFG); 171 | WriteReg(REG_AGCCTRL2,0x00); 172 | WriteReg(REG_AGCCTRL1,0x40); 173 | WriteReg(REG_AGCCTRL0,VAL_AGCCTRL0); 174 | WriteReg(REG_WOREVT1,VAL_WOREVT1); 175 | WriteReg(REG_WOREVT0,VAL_WOREVT0); 176 | WriteReg(REG_WORCTRL,VAL_WORCTRL); 177 | WriteReg(REG_FREND1,VAL_FREND1); 178 | WriteReg(REG_FREND0,VAL_FREND0); 179 | WriteReg(REG_FSCAL3,VAL_FSCAL3); 180 | WriteReg(REG_FSCAL2,VAL_FSCAL2); 181 | WriteReg(REG_FSCAL1,VAL_FSCAL1); 182 | WriteReg(REG_FSCAL0,VAL_FSCAL0); 183 | WriteReg(REG_RCCTRL1,VAL_RCCTRL1); 184 | WriteReg(REG_RCCTRL0,VAL_RCCTRL0); 185 | WriteReg(REG_FSTEST,VAL_FSTEST); 186 | WriteReg(REG_PTEST,VAL_PTEST); 187 | WriteReg(REG_AGCTEST,VAL_AGCTEST); 188 | WriteReg(REG_TEST2,VAL_TEST2); 189 | WriteReg(REG_TEST1,VAL_TEST1); 190 | WriteReg(REG_TEST0,VAL_TEST0); 191 | } 192 | 193 | -------------------------------------------------------------------------------- /CC2500ATTiny85Demo/SPI85.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * This file is free software; you can redistribute it and/or modify 4 | * it under the terms of either the GNU General Public License version 2 5 | * or the GNU Lesser General Public License version 2.1, both as 6 | * published by the Free Software Foundation. 7 | 8 | Added to github repository by Stanley Seow 9 | for Nordic nRF24L01 wireless modules 10 | 11 | Date : 10 Apr 2013 12 | e-mail : stanleyseow@gmail.com 13 | github : https://hithub.com/stanleyseow/attiny-nRF24L01 14 | Desc : This SPI 85 is for attiny85/x5 and attiny84/x4 15 | 16 | Date : 24 July 2013 17 | Desc : Updates pin mapping based on arduino-tiny-cores 18 | https://code.google.com/p/arduino-tiny/ 19 | 20 | Date : 11 Aug 2013 21 | Desc : Renamed SPI MOSI/MISO to USI_DO/ USI_DI to prevent confusion with SPI 22 | 23 | Pls refer to page 61 of attiny84 datasheet 24 | 25 | */ 26 | 27 | #include "pins_arduino.h" 28 | #include "SPI85.h" 29 | 30 | #if defined( __AVR_ATtiny85__ ) 31 | const static uint8_t SS = PB4; 32 | const static uint8_t USI_DO = PB1; 33 | const static uint8_t USI_DI = PB0; 34 | const static uint8_t SCK = PB2; 35 | #endif 36 | 37 | // attiny84 tested working using Arduino Digital Pins below 38 | #if defined( __AVR_ATtiny84__ ) 39 | const static uint8_t SS = 3; 40 | const static uint8_t USI_DO = 5; 41 | const static uint8_t USI_DI = 4; 42 | const static uint8_t SCK = 6; 43 | #endif 44 | 45 | SPI85Class SPI85; 46 | 47 | void SPI85Class::begin() { 48 | // Set direction register for SCK and USI_DO pin. 49 | // USI_DI pin automatically overrides to INPUT. 50 | // When the SS pin is set as OUTPUT, it can be used as 51 | // a general purpose output port (it doesn't influence 52 | // SPI operations). 53 | 54 | pinMode(SCK, OUTPUT); 55 | pinMode(USI_DO, OUTPUT); 56 | pinMode(USI_DI,INPUT); 57 | 58 | digitalWrite(USI_DI,HIGH); 59 | digitalWrite(SCK, LOW); 60 | digitalWrite(USI_DO, LOW); 61 | 62 | } 63 | 64 | void SPI85Class::end() { 65 | pinMode(SCK, INPUT); 66 | pinMode(USI_DO, INPUT); 67 | pinMode(USI_DI,INPUT); 68 | } 69 | 70 | 71 | 72 | void SPI85Class::setDataMode(uint8_t mode) 73 | { 74 | //SPCR = (SPCR & ~SPI_MODE_MASK) | mode; //FOR 328 NOT TINY 75 | } 76 | 77 | void SPI85Class::setClockDivider(uint8_t rate) 78 | { 79 | // SPCR = (SPCR & ~SPI_CLOCK_MASK) | (rate & SPI_CLOCK_MASK); 80 | // SPSR = (SPSR & ~SPI_2XCLOCK_MASK) | ((rate >> 2) & SPI_2XCLOCK_MASK); 81 | } 82 | -------------------------------------------------------------------------------- /CC2500ATTiny85Demo/SPI85.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2010 by Cristian Maglie 3 | * SPI Master library for arduino. 4 | * 5 | * This file is free software; you can redistribute it and/or modify 6 | * it under the terms of either the GNU General Public License version 2 7 | * or the GNU Lesser General Public License version 2.1, both as 8 | * published by the Free Software Foundation. 9 | 10 | 11 | MODIFIED BY RICH FEDOR, AUG2,2012 12 | WORKS WITH NRF24L01 MODULE, SPI MODE0 13 | 14 | Added to github repository by Stanley Seow 15 | for Nordic nRF24L01 wireless modules 16 | 17 | Date : 10 Apr 2013 18 | e-mail : stanleyseow@gmail.com 19 | github : https://hithub.com/stanleyseow/attiny-nRF24L01 20 | Desc : This SPI 85 is for attiny85/x5 and attiny84/x4 21 | 22 | Date : 24 July 2013 23 | Desc : Changes the transfer using bitwise operator | instead of + 24 | 25 | */ 26 | 27 | #ifndef _SPI85_H_INCLUDED 28 | #define _SPI85_H_INCLUDED 29 | 30 | #include 31 | #include 32 | #include 33 | 34 | #define SPI_CLOCK_DIV4 0x00 35 | #define SPI_CLOCK_DIV16 0x01 36 | #define SPI_CLOCK_DIV64 0x02 37 | #define SPI_CLOCK_DIV128 0x03 38 | #define SPI_CLOCK_DIV2 0x04 39 | #define SPI_CLOCK_DIV8 0x05 40 | #define SPI_CLOCK_DIV32 0x06 41 | //#define SPI_CLOCK_DIV64 0x07 42 | 43 | #define SPI_MODE0 0x00 44 | #define SPI_MODE1 0x04 45 | #define SPI_MODE2 0x08 46 | #define SPI_MODE3 0x0C 47 | 48 | #define SPI_MODE_MASK 0x0C // CPOL = bit 3, CPHA = bit 2 on SPCR 49 | #define SPI_CLOCK_MASK 0x03 // SPR1 = bit 1, SPR0 = bit 0 on SPCR 50 | #define SPI_2XCLOCK_MASK 0x01 // SPI2X = bit 0 on SPSR 51 | 52 | class SPI85Class { 53 | public: 54 | inline static byte transfer(byte _data); 55 | 56 | // SPI Configuration methods 57 | 58 | static void begin(); // Default 59 | static void end(); 60 | 61 | static void setDataMode(uint8_t); 62 | static void setClockDivider(uint8_t); 63 | }; 64 | 65 | extern SPI85Class SPI85; 66 | 67 | uint8_t SPI85Class::transfer(uint8_t _data) { 68 | USIDR = _data; 69 | USISR = _BV(USIOIF); 70 | 71 | while((USISR & _BV(USIOIF)) == 0){ 72 | USICR = _BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC); 73 | } 74 | return USIDR; 75 | } 76 | #endif 77 | -------------------------------------------------------------------------------- /CC2500ATTiny85Demo/cc2500_REG.h: -------------------------------------------------------------------------------- 1 | /* Sync word qualifier mode = 30/32 sync word bits detected */ 2 | /* CRC autoflush = false */ 3 | /* Channel spacing = 199.951172 */ 4 | /* Data format = Normal mode */ 5 | /* Data rate = 2.39897 */ 6 | /* RX filter BW = 203.125000 */ 7 | /* Preamble count = 4 */ 8 | /* Whitening = false */ 9 | /* Address config = No address check */ 10 | /* Carrier frequency = 2432.999908 */ 11 | /* Device address = 0 */ 12 | /* TX power = 0 */ 13 | /* Manchester enable = false */ 14 | /* CRC enable = true */ 15 | /* Deviation = 38.085938 */ 16 | /* Packet length mode = Variable packet length mode. Packet length configured by the first byte after sync word */ 17 | /* Packet length = 255 */ 18 | /* Modulation format = 2-FSK */ 19 | /* Base frequency = 2432.999908 */ 20 | /* Modulated = true */ 21 | /* Channel number = 0 */ 22 | /* PA table */ 23 | #define PA_TABLE {0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,} 24 | /*************************************************************** 25 | * SmartRF Studio(tm) Export 26 | * 27 | * Radio register settings specifed with C-code 28 | * compatible #define statements. 29 | * 30 | * RF device: CC2500 31 | * 32 | ***************************************************************/ 33 | 34 | #define REG_IOCFG2 0x0000 35 | #define REG_IOCFG1 0x0001 36 | #define REG_IOCFG0 0x0002 37 | #define REG_FIFOTHR 0x0003 38 | #define REG_SYNC1 0x0004 39 | #define REG_SYNC0 0x0005 40 | #define REG_PKTLEN 0x0006 41 | #define REG_PKTCTRL1 0x0007 42 | #define REG_PKTCTRL0 0x0008 43 | #define REG_ADDR 0x0009 44 | #define REG_CHANNR 0x000A 45 | #define REG_FSCTRL1 0x000B 46 | #define REG_FSCTRL0 0x000C 47 | #define REG_FREQ2 0x000D 48 | #define REG_FREQ1 0x000E 49 | #define REG_FREQ0 0x000F 50 | #define REG_MDMCFG4 0x0010 51 | #define REG_MDMCFG3 0x0011 52 | #define REG_MDMCFG2 0x0012 53 | #define REG_MDMCFG1 0x0013 54 | #define REG_MDMCFG0 0x0014 55 | #define REG_DEVIATN 0x0015 56 | #define REG_MCSM2 0x0016 57 | #define REG_MCSM1 0x0017 58 | #define REG_MCSM0 0x0018 59 | #define REG_FOCCFG 0x0019 60 | #define REG_BSCFG 0x001A 61 | #define REG_AGCCTRL2 0x001B 62 | #define REG_AGCCTRL1 0x001C 63 | #define REG_AGCCTRL0 0x001D 64 | #define REG_WOREVT1 0x001E 65 | #define REG_WOREVT0 0x001F 66 | #define REG_WORCTRL 0x0020 67 | #define REG_FREND1 0x0021 68 | #define REG_FREND0 0x0022 69 | #define REG_FSCAL3 0x0023 70 | #define REG_FSCAL2 0x0024 71 | #define REG_FSCAL1 0x0025 72 | #define REG_FSCAL0 0x0026 73 | #define REG_RCCTRL1 0x0027 74 | #define REG_RCCTRL0 0x0028 75 | #define REG_FSTEST 0x0029 76 | #define REG_PTEST 0x002A 77 | #define REG_AGCTEST 0x002B 78 | #define REG_TEST2 0x002C 79 | #define REG_TEST1 0x002D 80 | #define REG_TEST0 0x002E 81 | #define REG_PARTNUM 0x0030 82 | #define REG_VERSION 0x0031 83 | #define REG_FREQEST 0x0032 84 | #define REG_LQI 0x0033 85 | #define REG_RSSI 0x0034 86 | #define REG_MARCSTATE 0x0035 87 | #define REG_WORTIME1 0x0036 88 | #define REG_WORTIME0 0x0037 89 | #define REG_PKTSTATUS 0x0038 90 | #define REG_VCO_VC_DAC 0x0039 91 | #define REG_TXBYTES 0x003A 92 | #define REG_RXBYTES 0x003B 93 | #define REG_RCCTRL1_STATUS 0x003C 94 | #define REG_RCCTRL0_STATUS 0x003D 95 | -------------------------------------------------------------------------------- /CC2500ATTiny85Demo/cc2500_VAL.h: -------------------------------------------------------------------------------- 1 | /* Sync word qualifier mode = 30/32 sync word bits detected */ 2 | /* CRC autoflush = false */ 3 | /* Channel spacing = 199.951172 */ 4 | /* Data format = Normal mode */ 5 | /* Data rate = 2.39897 */ 6 | /* RX filter BW = 203.125000 */ 7 | /* Preamble count = 4 */ 8 | /* Whitening = false */ 9 | /* Address config = No address check */ 10 | /* Carrier frequency = 2432.999908 */ 11 | /* Device address = 0 */ 12 | /* TX power = 0 */ 13 | /* Manchester enable = false */ 14 | /* CRC enable = true */ 15 | /* Deviation = 38.085938 */ 16 | /* Packet length mode = Variable packet length mode. Packet length configured by the first byte after sync word */ 17 | /* Packet length = 255 */ 18 | /* Modulation format = 2-FSK */ 19 | /* Base frequency = 2432.999908 */ 20 | /* Modulated = true */ 21 | /* Channel number = 0 */ 22 | /* PA table */ 23 | #define PA_TABLE {0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,} 24 | /*************************************************************** 25 | * SmartRF Studio(tm) Export 26 | * 27 | * Radio register settings specifed with C-code 28 | * compatible #define statements. 29 | * 30 | * RF device: CC2500 31 | * 32 | ***************************************************************/ 33 | 34 | #define VAL_IOCFG2 0x29 35 | #define VAL_IOCFG1 0x2E 36 | #define VAL_IOCFG0 0x06 37 | #define VAL_FIFOTHR 0x07 38 | #define VAL_SYNC1 0xD3 39 | #define VAL_SYNC0 0x91 40 | #define VAL_PKTLEN 0xFF 41 | #define VAL_PKTCTRL1 0x04 42 | #define VAL_PKTCTRL0 0x05 43 | #define VAL_ADDR 0x00 44 | #define VAL_CHANNR 0x00 45 | #define VAL_FSCTRL1 0x08 46 | #define VAL_FSCTRL0 0x00 47 | #define VAL_FREQ2 0x5D 48 | #define VAL_FREQ1 0x93 49 | #define VAL_FREQ0 0xB1 50 | #define VAL_MDMCFG4 0x86 51 | #define VAL_MDMCFG3 0x83 52 | #define VAL_MDMCFG2 0x03 53 | #define VAL_MDMCFG1 0x22 54 | #define VAL_MDMCFG0 0xF8 55 | #define VAL_DEVIATN 0x44 56 | #define VAL_MCSM2 0x07 57 | #define VAL_MCSM1 0x30 58 | #define VAL_MCSM0 0x18 59 | #define VAL_FOCCFG 0x16 60 | #define VAL_BSCFG 0x6C 61 | #define VAL_AGCCTRL2 0x03 62 | #define VAL_AGCCTRL1 0x40 63 | #define VAL_AGCCTRL0 0x91 64 | #define VAL_WOREVT1 0x87 65 | #define VAL_WOREVT0 0x6B 66 | #define VAL_WORCTRL 0xF8 67 | #define VAL_FREND1 0x56 68 | #define VAL_FREND0 0x10 69 | #define VAL_FSCAL3 0xA9 70 | #define VAL_FSCAL2 0x0A 71 | #define VAL_FSCAL1 0x00 72 | #define VAL_FSCAL0 0x11 73 | #define VAL_RCCTRL1 0x41 74 | #define VAL_RCCTRL0 0x00 75 | #define VAL_FSTEST 0x59 76 | #define VAL_PTEST 0x7F 77 | #define VAL_AGCTEST 0x3F 78 | #define VAL_TEST2 0x88 79 | #define VAL_TEST1 0x31 80 | #define VAL_TEST0 0x0B 81 | #define VAL_PARTNUM 0x80 82 | #define VAL_VERSION 0x03 83 | #define VAL_FREQEST 0x00 84 | #define VAL_LQI 0x00 85 | #define VAL_RSSI 0x00 86 | #define VAL_MARCSTATE 0x00 87 | #define VAL_WORTIME1 0x00 88 | #define VAL_WORTIME0 0x00 89 | #define VAL_PKTSTATUS 0x00 90 | #define VAL_VCO_VC_DAC 0x00 91 | #define VAL_TXBYTES 0x00 92 | #define VAL_RXBYTES 0x00 93 | #define VAL_RCCTRL1_STATUS 0x00 94 | #define VAL_RCCTRL0_STATUS 0x00 95 | -------------------------------------------------------------------------------- /CC2500UnoDemo/CC2500UnoDemo.ino: -------------------------------------------------------------------------------- 1 | /** 2 | * CC2500 Sample transceiver code 3 | * This will send a packet containing the length and "Hello" 4 | * Every 400ms, then go into receive mode. 5 | * Adapted from https://github.com/yasiralijaved/Arduino-CC2500-Library 6 | * Written by Zohan SonZohan@gmail.com 7 | * 8 | * Hardware SPI: 9 | * MISO -> 12 10 | * MOSI -> 11 11 | * SCLK/SCK -> 13 12 | * CSN/SS - > 10 13 | */ 14 | #include "cc2500_REG.h" 15 | #include "cc2500_VAL.h" 16 | 17 | #include 18 | 19 | #define CC2500_IDLE 0x36 // Exit RX / TX, turn 20 | #define CC2500_TX 0x35 // Enable TX. If in RX state, only enable TX if CCA passes 21 | #define CC2500_RX 0x34 // Enable RX. Perform calibration if enabled 22 | #define CC2500_FTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states 23 | #define CC2500_FRX 0x3A // Flush the RX FIFO buffer. Only issue SFRX in IDLE or RXFIFO_OVERFLOW states 24 | #define CC2500_SWOR 0x38 25 | #define CC2500_TXFIFO 0x3F 26 | #define CC2500_RXFIFO 0x3F 27 | 28 | #define TX_TIMEOUT 10 // Timeouts are added 29 | long previousTXTimeoutMillis = 0; 30 | long previousMillis = 0; 31 | long sendInterval = 400; // in milliseconds 32 | 33 | void setup(){ 34 | Serial.begin(9600); 35 | 36 | // Setup 37 | pinMode(SS,OUTPUT); 38 | SPI.begin(); 39 | digitalWrite(SS,HIGH); 40 | Serial.println("Initializing Wireless.."); 41 | init_CC2500(); 42 | Read_Config_Regs(); 43 | } 44 | 45 | void loop(){ 46 | unsigned long currentMillis = millis(); 47 | if(currentMillis - previousMillis > sendInterval) { 48 | previousMillis = currentMillis; 49 | sendPacket(); 50 | } 51 | listenForPacket(); 52 | } 53 | 54 | void listenForPacket() { 55 | SendStrobe(CC2500_RX); 56 | // Switch MISO to output if a packet has been received or not 57 | WriteReg(REG_IOCFG1,0x01); 58 | delay(20); 59 | unsigned long currentMillis = millis(); 60 | if (digitalRead(MISO)) { 61 | char PacketLength = ReadReg(CC2500_RXFIFO); 62 | char recvPacket[PacketLength]; 63 | if(PacketLength == 6) { 64 | Serial.println("Packet Received!"); 65 | Serial.print("Packet Length: "); 66 | Serial.println(PacketLength, DEC); 67 | Serial.print("Data: "); 68 | for(int i = 1; i < PacketLength; i++){ 69 | recvPacket[i] = ReadReg(CC2500_RXFIFO); 70 | Serial.print(recvPacket[i], DEC); 71 | Serial.print(" "); 72 | } 73 | Serial.println(" "); 74 | // Print quality information 75 | byte rssi = ReadReg(CC2500_RXFIFO); 76 | byte lqi = ReadReg(CC2500_RXFIFO); 77 | Serial.print("RSSI: "); 78 | Serial.println(rssi); 79 | Serial.print("LQI: "); 80 | Serial.println(lqi); 81 | } 82 | 83 | // Make sure that the radio is in IDLE state before flushing the FIFO 84 | // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point) 85 | SendStrobe(CC2500_IDLE); 86 | // Flush RX FIFO 87 | SendStrobe(CC2500_FRX); 88 | } else { 89 | 90 | } 91 | } 92 | 93 | void sendPacket() { 94 | WriteReg(REG_IOCFG1,0x06); 95 | // Make sure that the radio is in IDLE state before flushing the FIFO 96 | SendStrobe(CC2500_IDLE); 97 | // Flush TX FIFO 98 | SendStrobe(CC2500_FTX); 99 | // prepare Packet 100 | int length = 6; 101 | unsigned char packet[length]; 102 | // First Byte = Length Of Packet 103 | packet[0] = length; 104 | packet[1] = 'H'; 105 | packet[2] = 'e'; 106 | packet[3] = 'l'; 107 | packet[4] = 'l'; 108 | packet[5] = 'o'; 109 | 110 | // SIDLE: exit RX/TX 111 | SendStrobe(CC2500_IDLE); 112 | 113 | Serial.println("Transmitting "); 114 | for(int i = 0; i < length; i++) 115 | { 116 | WriteReg(CC2500_TXFIFO,packet[i]); 117 | } 118 | // STX: enable TX 119 | SendStrobe(CC2500_TX); 120 | // Wait for GDO0 to be set -> sync transmitted 121 | previousTXTimeoutMillis = millis(); 122 | while (!digitalRead(MISO) && (millis() - previousTXTimeoutMillis) <= TX_TIMEOUT) { 123 | //Serial.println("GDO0 = 0"); 124 | } 125 | 126 | // Wait for GDO0 to be cleared -> end of packet 127 | previousTXTimeoutMillis = millis(); 128 | while (digitalRead(MISO) && (millis() - previousTXTimeoutMillis) <= TX_TIMEOUT) { 129 | //Serial.println("GDO0 = 1"); 130 | } 131 | Serial.println("Finished sending"); 132 | SendStrobe(CC2500_IDLE); 133 | } 134 | 135 | void WriteReg(char addr, char value){ 136 | digitalWrite(SS,LOW); 137 | 138 | while (digitalRead(MISO) == HIGH) { 139 | }; 140 | 141 | SPI.transfer(addr); 142 | delay(10); 143 | SPI.transfer(value); 144 | digitalWrite(SS,HIGH); 145 | } 146 | 147 | char ReadReg(char addr){ 148 | addr = addr + 0x80; 149 | digitalWrite(SS,LOW); 150 | while (digitalRead(MISO) == HIGH) { 151 | }; 152 | char x = SPI.transfer(addr); 153 | delay(10); 154 | char y = SPI.transfer(0); 155 | digitalWrite(SS,HIGH); 156 | return y; 157 | } 158 | 159 | char SendStrobe(char strobe){ 160 | digitalWrite(SS,LOW); 161 | 162 | while (digitalRead(MISO) == HIGH) { 163 | }; 164 | 165 | char result = SPI.transfer(strobe); 166 | digitalWrite(SS,HIGH); 167 | delay(10); 168 | return result; 169 | } 170 | 171 | void init_CC2500(){ 172 | WriteReg(REG_IOCFG2,0x06); 173 | WriteReg(REG_IOCFG0,0x01); 174 | WriteReg(REG_IOCFG1,0x06); 175 | 176 | WriteReg(REG_FIFOTHR, 0x02); 177 | WriteReg(REG_SYNC1,VAL_SYNC1); 178 | WriteReg(REG_SYNC0,VAL_SYNC0); 179 | WriteReg(REG_PKTLEN,VAL_PKTLEN); 180 | WriteReg(REG_PKTCTRL1,0x8C); 181 | WriteReg(REG_PKTCTRL0, 0x0D); 182 | 183 | WriteReg(REG_ADDR,VAL_ADDR); 184 | WriteReg(REG_CHANNR,VAL_CHANNR); 185 | WriteReg(REG_FSCTRL1,VAL_FSCTRL1); 186 | WriteReg(REG_FSCTRL0,VAL_FSCTRL0); 187 | WriteReg(REG_FREQ2,VAL_FREQ2); 188 | WriteReg(REG_FREQ1,VAL_FREQ1); 189 | WriteReg(REG_FREQ0,VAL_FREQ0); 190 | WriteReg(REG_MDMCFG4,VAL_MDMCFG4); 191 | WriteReg(REG_MDMCFG3,VAL_MDMCFG3); 192 | WriteReg(REG_MDMCFG2,VAL_MDMCFG2); 193 | WriteReg(REG_MDMCFG1,VAL_MDMCFG1); 194 | WriteReg(REG_MDMCFG0,VAL_MDMCFG0); 195 | WriteReg(REG_DEVIATN,VAL_DEVIATN); 196 | WriteReg(REG_MCSM2,VAL_MCSM2); 197 | WriteReg(REG_MCSM1,VAL_MCSM1); 198 | WriteReg(REG_MCSM0,VAL_MCSM0); 199 | WriteReg(REG_FOCCFG,VAL_FOCCFG); 200 | 201 | WriteReg(REG_BSCFG,VAL_BSCFG); 202 | WriteReg(REG_AGCCTRL2,0x00); 203 | WriteReg(REG_AGCCTRL1,0x40); 204 | WriteReg(REG_AGCCTRL0,VAL_AGCCTRL0); 205 | WriteReg(REG_WOREVT1,VAL_WOREVT1); 206 | WriteReg(REG_WOREVT0,VAL_WOREVT0); 207 | WriteReg(REG_WORCTRL,0x78); 208 | WriteReg(REG_FREND1,VAL_FREND1); 209 | WriteReg(REG_FREND0,VAL_FREND0); 210 | WriteReg(REG_FSCAL3,VAL_FSCAL3); 211 | WriteReg(REG_FSCAL2,VAL_FSCAL2); 212 | WriteReg(REG_FSCAL1,VAL_FSCAL1); 213 | WriteReg(REG_FSCAL0,VAL_FSCAL0); 214 | WriteReg(REG_RCCTRL1,VAL_RCCTRL1); 215 | WriteReg(REG_RCCTRL0,VAL_RCCTRL0); 216 | WriteReg(REG_FSTEST,VAL_FSTEST); 217 | WriteReg(REG_PTEST,VAL_PTEST); 218 | WriteReg(REG_AGCTEST,VAL_AGCTEST); 219 | WriteReg(REG_TEST2,VAL_TEST2); 220 | WriteReg(REG_TEST1,VAL_TEST1); 221 | WriteReg(REG_TEST0,VAL_TEST0); 222 | } 223 | 224 | void Read_Config_Regs(void){ 225 | Serial.println(ReadReg(REG_IOCFG2),HEX); 226 | delay(10); 227 | Serial.println(ReadReg(REG_IOCFG1),HEX); 228 | delay(10); 229 | Serial.println(ReadReg(REG_IOCFG0),HEX); 230 | delay(10); 231 | /* Serial.println(ReadReg(REG_FIFOTHR),HEX); 232 | delay(10); 233 | Serial.println(ReadReg(REG_SYNC1),HEX); 234 | delay(10); 235 | Serial.println(ReadReg(REG_SYNC0),HEX); 236 | delay(10); 237 | Serial.println(ReadReg(REG_PKTLEN),HEX); 238 | delay(10); 239 | Serial.println(ReadReg(REG_PKTCTRL1),HEX); 240 | delay(10); 241 | Serial.println(ReadReg(REG_PKTCTRL0),HEX); 242 | delay(10); 243 | Serial.println(ReadReg(REG_ADDR),HEX); 244 | delay(10); 245 | Serial.println(ReadReg(REG_CHANNR),HEX); 246 | delay(10); 247 | Serial.println(ReadReg(REG_FSCTRL1),HEX); 248 | delay(10); 249 | Serial.println(ReadReg(REG_FSCTRL0),HEX); 250 | delay(10); 251 | Serial.println(ReadReg(REG_FREQ2),HEX); 252 | delay(10); 253 | Serial.println(ReadReg(REG_FREQ1),HEX); 254 | delay(10); 255 | Serial.println(ReadReg(REG_FREQ0),HEX); 256 | delay(10); 257 | Serial.println(ReadReg(REG_MDMCFG4),HEX); 258 | delay(10); 259 | Serial.println(ReadReg(REG_MDMCFG3),HEX); 260 | delay(10); 261 | Serial.println(ReadReg(REG_MDMCFG2),HEX); 262 | delay(10); 263 | Serial.println(ReadReg(REG_MDMCFG1),HEX); 264 | delay(10); 265 | Serial.println(ReadReg(REG_MDMCFG0),HEX); 266 | delay(10); 267 | Serial.println(ReadReg(REG_DEVIATN),HEX); 268 | delay(10); 269 | Serial.println(ReadReg(REG_MCSM2),HEX); 270 | delay(10); 271 | Serial.println(ReadReg(REG_MCSM1),HEX); 272 | delay(10); 273 | Serial.println(ReadReg(REG_MCSM0),HEX); 274 | delay(10); 275 | Serial.println(ReadReg(REG_FOCCFG),HEX); 276 | delay(10); 277 | 278 | Serial.println(ReadReg(REG_BSCFG),HEX); 279 | delay(10); 280 | Serial.println(ReadReg(REG_AGCCTRL2),HEX); 281 | delay(10); 282 | Serial.println(ReadReg(REG_AGCCTRL1),HEX); 283 | delay(10); 284 | Serial.println(ReadReg(REG_AGCCTRL0),HEX); 285 | delay(10); 286 | Serial.println(ReadReg(REG_WOREVT1),HEX); 287 | delay(10); 288 | Serial.println(ReadReg(REG_WOREVT0),HEX); 289 | delay(10); 290 | Serial.println(ReadReg(REG_WORCTRL),HEX); 291 | delay(10); 292 | Serial.println(ReadReg(REG_FREND1),HEX); 293 | delay(10); 294 | Serial.println(ReadReg(REG_FREND0),HEX); 295 | delay(10); 296 | Serial.println(ReadReg(REG_FSCAL3),HEX); 297 | delay(10); 298 | Serial.println(ReadReg(REG_FSCAL2),HEX); 299 | delay(10); 300 | Serial.println(ReadReg(REG_FSCAL1),HEX); 301 | delay(10); 302 | Serial.println(ReadReg(REG_FSCAL0),HEX); 303 | delay(10); 304 | Serial.println(ReadReg(REG_RCCTRL1),HEX); 305 | delay(10); 306 | Serial.println(ReadReg(REG_RCCTRL0),HEX); 307 | delay(10); 308 | Serial.println(ReadReg(REG_FSTEST),HEX); 309 | delay(10); 310 | Serial.println(ReadReg(REG_PTEST),HEX); 311 | delay(10); 312 | Serial.println(ReadReg(REG_AGCTEST),HEX); 313 | delay(10); 314 | Serial.println(ReadReg(REG_TEST2),HEX); 315 | delay(10); 316 | Serial.println(ReadReg(REG_TEST1),HEX); 317 | delay(10); 318 | Serial.println(ReadReg(REG_TEST0),HEX); 319 | delay(10); 320 | /* 321 | Serial.println(ReadReg(REG_PARTNUM),HEX); 322 | delay(1000); 323 | Serial.println(ReadReg(REG_VERSION),HEX); 324 | delay(1000); 325 | Serial.println(ReadReg(REG_FREQEST),HEX); 326 | delay(1000); 327 | Serial.println(ReadReg(REG_LQI),HEX); 328 | delay(1000); 329 | Serial.println(ReadReg(REG_RSSI),HEX); 330 | delay(1000); 331 | Serial.println(ReadReg(REG_MARCSTATE),HEX); 332 | delay(1000); 333 | Serial.println(ReadReg(REG_WORTIME1),HEX); 334 | delay(1000); 335 | Serial.println(ReadReg(REG_WORTIME0),HEX); 336 | delay(1000); 337 | Serial.println(ReadReg(REG_PKTSTATUS),HEX); 338 | delay(1000); 339 | Serial.println(ReadReg(REG_VCO_VC_DAC),HEX); 340 | delay(1000); 341 | Serial.println(ReadReg(REG_TXBYTES),HEX); 342 | delay(1000); 343 | Serial.println(ReadReg(REG_RXBYTES),HEX); 344 | delay(1000); 345 | Serial.println(ReadReg(REG_RCCTRL1_STATUS),HEX); 346 | delay(1000); 347 | Serial.println(ReadReg(REG_RCCTRL0_STATUS),HEX); 348 | delay(1000); 349 | */ 350 | } 351 | 352 | 353 | -------------------------------------------------------------------------------- /CC2500UnoDemo/cc2500_REG.h: -------------------------------------------------------------------------------- 1 | /* Sync word qualifier mode = 30/32 sync word bits detected */ 2 | /* CRC autoflush = false */ 3 | /* Channel spacing = 199.951172 */ 4 | /* Data format = Normal mode */ 5 | /* Data rate = 2.39897 */ 6 | /* RX filter BW = 203.125000 */ 7 | /* Preamble count = 4 */ 8 | /* Whitening = false */ 9 | /* Address config = No address check */ 10 | /* Carrier frequency = 2432.999908 */ 11 | /* Device address = 0 */ 12 | /* TX power = 0 */ 13 | /* Manchester enable = false */ 14 | /* CRC enable = true */ 15 | /* Deviation = 38.085938 */ 16 | /* Packet length mode = Variable packet length mode. Packet length configured by the first byte after sync word */ 17 | /* Packet length = 255 */ 18 | /* Modulation format = 2-FSK */ 19 | /* Base frequency = 2432.999908 */ 20 | /* Modulated = true */ 21 | /* Channel number = 0 */ 22 | /* PA table */ 23 | #define PA_TABLE {0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,} 24 | /*************************************************************** 25 | * SmartRF Studio(tm) Export 26 | * 27 | * Radio register settings specifed with C-code 28 | * compatible #define statements. 29 | * 30 | * RF device: CC2500 31 | * 32 | ***************************************************************/ 33 | 34 | #define REG_IOCFG2 0x0000 35 | #define REG_IOCFG1 0x0001 36 | #define REG_IOCFG0 0x0002 37 | #define REG_FIFOTHR 0x0003 38 | #define REG_SYNC1 0x0004 39 | #define REG_SYNC0 0x0005 40 | #define REG_PKTLEN 0x0006 41 | #define REG_PKTCTRL1 0x0007 42 | #define REG_PKTCTRL0 0x0008 43 | #define REG_ADDR 0x0009 44 | #define REG_CHANNR 0x000A 45 | #define REG_FSCTRL1 0x000B 46 | #define REG_FSCTRL0 0x000C 47 | #define REG_FREQ2 0x000D 48 | #define REG_FREQ1 0x000E 49 | #define REG_FREQ0 0x000F 50 | #define REG_MDMCFG4 0x0010 51 | #define REG_MDMCFG3 0x0011 52 | #define REG_MDMCFG2 0x0012 53 | #define REG_MDMCFG1 0x0013 54 | #define REG_MDMCFG0 0x0014 55 | #define REG_DEVIATN 0x0015 56 | #define REG_MCSM2 0x0016 57 | #define REG_MCSM1 0x0017 58 | #define REG_MCSM0 0x0018 59 | #define REG_FOCCFG 0x0019 60 | #define REG_BSCFG 0x001A 61 | #define REG_AGCCTRL2 0x001B 62 | #define REG_AGCCTRL1 0x001C 63 | #define REG_AGCCTRL0 0x001D 64 | #define REG_WOREVT1 0x001E 65 | #define REG_WOREVT0 0x001F 66 | #define REG_WORCTRL 0x0020 67 | #define REG_FREND1 0x0021 68 | #define REG_FREND0 0x0022 69 | #define REG_FSCAL3 0x0023 70 | #define REG_FSCAL2 0x0024 71 | #define REG_FSCAL1 0x0025 72 | #define REG_FSCAL0 0x0026 73 | #define REG_RCCTRL1 0x0027 74 | #define REG_RCCTRL0 0x0028 75 | #define REG_FSTEST 0x0029 76 | #define REG_PTEST 0x002A 77 | #define REG_AGCTEST 0x002B 78 | #define REG_TEST2 0x002C 79 | #define REG_TEST1 0x002D 80 | #define REG_TEST0 0x002E 81 | #define REG_PARTNUM 0x0030 82 | #define REG_VERSION 0x0031 83 | #define REG_FREQEST 0x0032 84 | #define REG_LQI 0x0033 85 | #define REG_RSSI 0x0034 86 | #define REG_MARCSTATE 0x0035 87 | #define REG_WORTIME1 0x0036 88 | #define REG_WORTIME0 0x0037 89 | #define REG_PKTSTATUS 0x0038 90 | #define REG_VCO_VC_DAC 0x0039 91 | #define REG_TXBYTES 0x003A 92 | #define REG_RXBYTES 0x003B 93 | #define REG_RCCTRL1_STATUS 0x003C 94 | #define REG_RCCTRL0_STATUS 0x003D 95 | -------------------------------------------------------------------------------- /CC2500UnoDemo/cc2500_VAL.h: -------------------------------------------------------------------------------- 1 | /* Sync word qualifier mode = 30/32 sync word bits detected */ 2 | /* CRC autoflush = false */ 3 | /* Channel spacing = 199.951172 */ 4 | /* Data format = Normal mode */ 5 | /* Data rate = 2.39897 */ 6 | /* RX filter BW = 203.125000 */ 7 | /* Preamble count = 4 */ 8 | /* Whitening = false */ 9 | /* Address config = No address check */ 10 | /* Carrier frequency = 2432.999908 */ 11 | /* Device address = 0 */ 12 | /* TX power = 0 */ 13 | /* Manchester enable = false */ 14 | /* CRC enable = true */ 15 | /* Deviation = 38.085938 */ 16 | /* Packet length mode = Variable packet length mode. Packet length configured by the first byte after sync word */ 17 | /* Packet length = 255 */ 18 | /* Modulation format = 2-FSK */ 19 | /* Base frequency = 2432.999908 */ 20 | /* Modulated = true */ 21 | /* Channel number = 0 */ 22 | /* PA table */ 23 | #define PA_TABLE {0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,} 24 | /*************************************************************** 25 | * SmartRF Studio(tm) Export 26 | * 27 | * Radio register settings specifed with C-code 28 | * compatible #define statements. 29 | * 30 | * RF device: CC2500 31 | * 32 | ***************************************************************/ 33 | 34 | #define VAL_IOCFG2 0x29 35 | #define VAL_IOCFG1 0x2E 36 | #define VAL_IOCFG0 0x06 37 | #define VAL_FIFOTHR 0x07 38 | #define VAL_SYNC1 0xD3 39 | #define VAL_SYNC0 0x91 40 | #define VAL_PKTLEN 0xFF 41 | #define VAL_PKTCTRL1 0x04 42 | #define VAL_PKTCTRL0 0x05 43 | #define VAL_ADDR 0x00 44 | #define VAL_CHANNR 0x00 45 | #define VAL_FSCTRL1 0x08 46 | #define VAL_FSCTRL0 0x00 47 | #define VAL_FREQ2 0x5D 48 | #define VAL_FREQ1 0x93 49 | #define VAL_FREQ0 0xB1 50 | #define VAL_MDMCFG4 0x86 51 | #define VAL_MDMCFG3 0x83 52 | #define VAL_MDMCFG2 0x03 53 | #define VAL_MDMCFG1 0x22 54 | #define VAL_MDMCFG0 0xF8 55 | #define VAL_DEVIATN 0x44 56 | #define VAL_MCSM2 0x07 57 | #define VAL_MCSM1 0x30 58 | #define VAL_MCSM0 0x18 59 | #define VAL_FOCCFG 0x16 60 | #define VAL_BSCFG 0x6C 61 | #define VAL_AGCCTRL2 0x03 62 | #define VAL_AGCCTRL1 0x40 63 | #define VAL_AGCCTRL0 0x91 64 | #define VAL_WOREVT1 0x87 65 | #define VAL_WOREVT0 0x6B 66 | #define VAL_WORCTRL 0xF8 67 | #define VAL_FREND1 0x56 68 | #define VAL_FREND0 0x10 69 | #define VAL_FSCAL3 0xA9 70 | #define VAL_FSCAL2 0x0A 71 | #define VAL_FSCAL1 0x00 72 | #define VAL_FSCAL0 0x11 73 | #define VAL_RCCTRL1 0x41 74 | #define VAL_RCCTRL0 0x00 75 | #define VAL_FSTEST 0x59 76 | #define VAL_PTEST 0x7F 77 | #define VAL_AGCTEST 0x3F 78 | #define VAL_TEST2 0x88 79 | #define VAL_TEST1 0x31 80 | #define VAL_TEST0 0x0B 81 | #define VAL_PARTNUM 0x80 82 | #define VAL_VERSION 0x03 83 | #define VAL_FREQEST 0x00 84 | #define VAL_LQI 0x00 85 | #define VAL_RSSI 0x00 86 | #define VAL_MARCSTATE 0x00 87 | #define VAL_WORTIME1 0x00 88 | #define VAL_WORTIME0 0x00 89 | #define VAL_PKTSTATUS 0x00 90 | #define VAL_VCO_VC_DAC 0x00 91 | #define VAL_TXBYTES 0x00 92 | #define VAL_RXBYTES 0x00 93 | #define VAL_RCCTRL1_STATUS 0x00 94 | #define VAL_RCCTRL0_STATUS 0x00 95 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ArduinoCC2500Demo 2 | ================= 3 | 4 | A demo of the Arduino communicating with a CC2500. 5 | This uses the minimum amount of pins on the most minimal amount of hardware needed to get the system functioning. 6 | 7 | Pinouts CC2500->Arduino 8 | 9 | MISO -> 12 10 | 11 | MOSI -> 11 12 | 13 | SCLK/SCK -> 13 14 | 15 | CSN/SS - > 10 16 | 17 | VCC -> 3.3v 18 | 19 | GND - > GND 20 | 21 | -------------------------------------------------------------------------------- /Uno CC2500 Back.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Zohan/ArduinoCC2500Demo/d4688bdcceaeea4683a57da30bc0080278d9e918/Uno CC2500 Back.jpg -------------------------------------------------------------------------------- /Uno CC2500 Front.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Zohan/ArduinoCC2500Demo/d4688bdcceaeea4683a57da30bc0080278d9e918/Uno CC2500 Front.jpg --------------------------------------------------------------------------------