├── LICENSE ├── Pics ├── CTS_Debuger.png ├── Critical Path.png ├── FFT.png ├── FFT_DC.png ├── GDS.png ├── Post_CTS.png ├── SIMULATION.png ├── SYN_Results.png ├── SYN_Results_2.png ├── design.png ├── inspuctor of critical path.png ├── nc_verilog.png ├── radix.png ├── shift.png └── snap_shoot.png ├── Pnr ├── innovus ├── innovus.cmd ├── innovus.log ├── output │ ├── FFT.gds │ ├── FFT.sdf │ ├── FFT.v │ ├── FFT_CHIP.gds │ └── streamOut.map └── scripts │ ├── Clock.ctstch │ ├── Default.globals │ ├── MMMC.tcl │ └── pnr.tcl ├── README.md ├── RTL ├── FFT.v ├── ROM_16.v ├── ROM_2.v ├── ROM_4.v ├── ROM_8.v ├── radix2.v ├── shift_1.v ├── shift_16.v ├── shift_2.v ├── shift_4.v └── shift_8.v ├── SIM ├── FFT.c ├── FFT.py ├── FFT_tb.v ├── FFT_test.c ├── Test_cases │ ├── IN_imag_pattern01.txt │ ├── IN_imag_pattern02.txt │ ├── IN_imag_pattern03.txt │ ├── IN_imag_pattern04.txt │ ├── IN_imag_pattern05.txt │ ├── IN_real_pattern01.txt │ ├── IN_real_pattern02.txt │ ├── IN_real_pattern03.txt │ ├── IN_real_pattern04.txt │ ├── IN_real_pattern05.txt │ ├── OUT_imag_16_pattern01.txt │ ├── OUT_imag_16_pattern02.txt │ ├── OUT_imag_16_pattern03.txt │ ├── OUT_imag_16_pattern04.txt │ ├── OUT_imag_16_pattern05.txt │ ├── OUT_real_16_pattern01.txt │ ├── OUT_real_16_pattern02.txt │ ├── OUT_real_16_pattern03.txt │ ├── OUT_real_16_pattern04.txt │ └── OUT_real_16_pattern05.txt ├── pre_Synthesis.cr.mti ├── pre_Synthesis.mpf ├── twiddle_gen.py ├── vsim.wlf └── work │ ├── @_opt │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ ├── _lib2_0.qdb │ ├── _lib2_0.qpg │ ├── _lib2_0.qtl │ ├── _lib3_0.qdb │ ├── _lib3_0.qtl │ ├── _lib4_0.qdb │ ├── _lib4_0.qpg │ └── _lib4_0.qtl │ ├── @_opt1 │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ ├── _lib2_0.qdb │ ├── _lib2_0.qpg │ ├── _lib2_0.qtl │ ├── _lib3_0.qdb │ ├── _lib3_0.qtl │ ├── _lib4_0.qdb │ ├── _lib4_0.qpg │ └── _lib4_0.qtl │ ├── _info │ ├── _lib.qdb │ ├── _lib1_2.qdb │ ├── _lib1_2.qpg │ ├── _lib1_2.qtl │ ├── _lib1_3.qdb │ ├── _lib1_3.qpg │ ├── _lib1_3.qtl │ └── _vmake └── SYN ├── command.log ├── cons └── cons.tcl ├── default.svf ├── output ├── FFT.ddc ├── FFT.sdc ├── FFT.sdf └── FFT.v ├── report ├── synth_area.rpt ├── synth_cells.rpt ├── synth_power.rpt ├── synth_qor.rpt ├── synth_resources.rpt └── synth_timing.rpt ├── run ├── scripts └── syn.tcl ├── syn.log └── work ├── FFT-verilog.pvl ├── FFT-verilog.syn ├── FFT.mr ├── RADIX2.mr ├── ROM_16-verilog.pvl ├── ROM_16-verilog.syn ├── ROM_16.mr ├── ROM_2-verilog.pvl ├── ROM_2-verilog.syn ├── ROM_2.mr ├── ROM_4-verilog.pvl ├── ROM_4-verilog.syn ├── ROM_4.mr ├── ROM_8-verilog.pvl ├── ROM_8-verilog.syn ├── ROM_8.mr ├── SHIFT_1.mr ├── SHIFT_16.mr ├── SHIFT_2.mr ├── SHIFT_4.mr ├── SHIFT_8.mr ├── radix2-verilog.pvl ├── radix2-verilog.syn ├── shift_1-verilog.pvl ├── shift_1-verilog.syn ├── shift_16-verilog.pvl ├── shift_16-verilog.syn ├── shift_2-verilog.pvl ├── shift_2-verilog.syn ├── shift_4-verilog.pvl ├── shift_4-verilog.syn ├── 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