├── LICENSE ├── Pics ├── CTS_Debuger.png ├── Critical Path.png ├── FFT.png ├── FFT_DC.png ├── GDS.png ├── Post_CTS.png ├── SIMULATION.png ├── SYN_Results.png ├── SYN_Results_2.png ├── design.png ├── inspuctor of critical path.png ├── nc_verilog.png ├── radix.png ├── shift.png └── snap_shoot.png ├── Pnr ├── innovus ├── innovus.cmd ├── innovus.log ├── output │ ├── FFT.gds │ ├── FFT.sdf │ ├── FFT.v │ ├── FFT_CHIP.gds │ └── streamOut.map └── scripts │ ├── Clock.ctstch │ ├── Default.globals │ ├── MMMC.tcl │ └── pnr.tcl ├── README.md ├── RTL ├── FFT.v ├── ROM_16.v ├── ROM_2.v ├── ROM_4.v ├── ROM_8.v ├── radix2.v ├── shift_1.v ├── shift_16.v ├── shift_2.v ├── shift_4.v └── shift_8.v ├── SIM ├── FFT.c ├── FFT.py ├── FFT_tb.v ├── FFT_test.c ├── Test_cases │ ├── IN_imag_pattern01.txt │ ├── IN_imag_pattern02.txt │ ├── IN_imag_pattern03.txt │ ├── IN_imag_pattern04.txt │ ├── IN_imag_pattern05.txt │ ├── IN_real_pattern01.txt │ ├── IN_real_pattern02.txt │ ├── IN_real_pattern03.txt │ ├── IN_real_pattern04.txt │ ├── IN_real_pattern05.txt │ ├── OUT_imag_16_pattern01.txt │ ├── OUT_imag_16_pattern02.txt │ ├── OUT_imag_16_pattern03.txt │ ├── OUT_imag_16_pattern04.txt │ ├── OUT_imag_16_pattern05.txt │ ├── OUT_real_16_pattern01.txt │ ├── OUT_real_16_pattern02.txt │ ├── OUT_real_16_pattern03.txt │ ├── OUT_real_16_pattern04.txt │ └── OUT_real_16_pattern05.txt ├── pre_Synthesis.cr.mti ├── pre_Synthesis.mpf ├── twiddle_gen.py ├── vsim.wlf └── work │ ├── @_opt │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ ├── _lib2_0.qdb │ ├── _lib2_0.qpg │ ├── _lib2_0.qtl │ ├── _lib3_0.qdb │ ├── _lib3_0.qtl │ ├── _lib4_0.qdb │ ├── _lib4_0.qpg │ └── _lib4_0.qtl │ ├── @_opt1 │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ ├── _lib2_0.qdb │ ├── _lib2_0.qpg │ ├── _lib2_0.qtl │ ├── _lib3_0.qdb │ ├── _lib3_0.qtl │ ├── _lib4_0.qdb │ ├── _lib4_0.qpg │ └── _lib4_0.qtl │ ├── _info │ ├── _lib.qdb │ ├── _lib1_2.qdb │ ├── _lib1_2.qpg │ ├── _lib1_2.qtl │ ├── _lib1_3.qdb │ ├── _lib1_3.qpg │ ├── _lib1_3.qtl │ └── _vmake └── SYN ├── command.log ├── cons └── cons.tcl ├── default.svf ├── output ├── FFT.ddc ├── FFT.sdc ├── FFT.sdf └── FFT.v ├── report ├── synth_area.rpt ├── synth_cells.rpt ├── synth_power.rpt ├── synth_qor.rpt ├── synth_resources.rpt └── synth_timing.rpt ├── run ├── scripts └── syn.tcl ├── syn.log └── work ├── FFT-verilog.pvl ├── FFT-verilog.syn ├── FFT.mr ├── RADIX2.mr ├── ROM_16-verilog.pvl ├── ROM_16-verilog.syn ├── ROM_16.mr ├── ROM_2-verilog.pvl ├── ROM_2-verilog.syn ├── ROM_2.mr ├── ROM_4-verilog.pvl ├── ROM_4-verilog.syn ├── ROM_4.mr ├── ROM_8-verilog.pvl ├── ROM_8-verilog.syn ├── ROM_8.mr ├── SHIFT_1.mr ├── SHIFT_16.mr ├── SHIFT_2.mr ├── SHIFT_4.mr ├── SHIFT_8.mr ├── radix2-verilog.pvl ├── radix2-verilog.syn ├── shift_1-verilog.pvl ├── shift_1-verilog.syn ├── shift_16-verilog.pvl ├── shift_16-verilog.syn ├── shift_2-verilog.pvl ├── shift_2-verilog.syn ├── shift_4-verilog.pvl ├── shift_4-verilog.syn ├── shift_8-verilog.pvl └── shift_8-verilog.syn /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Ahmed Abdelazeem 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Pics/CTS_Debuger.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor/89ce7665eca8b77a0c48e610dab11928108566b6/Pics/CTS_Debuger.png -------------------------------------------------------------------------------- /Pics/Critical Path.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor/89ce7665eca8b77a0c48e610dab11928108566b6/Pics/Critical Path.png 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LEFOBS 10 0 11 | NAME metal1/NET 11 0 12 | NAME metal1/SPNET 12 0 13 | NAME metal1/PIN 13 0 14 | NAME metal1/LEFPIN 14 0 15 | via PIN 15 0 16 | via LEFPIN 16 0 17 | via FILL 17 0 18 | via FILLOPC 18 0 19 | via VIA 19 0 20 | via VIAFILL 20 0 21 | via VIAFILLOPC 21 0 22 | metal2 NET 22 0 23 | metal2 SPNET 23 0 24 | metal2 PIN 24 0 25 | metal2 LEFPIN 25 0 26 | metal2 FILL 26 0 27 | metal2 FILLOPC 27 0 28 | metal2 VIA 28 0 29 | metal2 VIAFILL 29 0 30 | metal2 VIAFILLOPC 30 0 31 | metal2 LEFOBS 31 0 32 | NAME metal2/NET 32 0 33 | NAME metal2/SPNET 33 0 34 | NAME metal2/PIN 34 0 35 | NAME metal2/LEFPIN 35 0 36 | via2 PIN 36 0 37 | via2 LEFPIN 37 0 38 | via2 FILL 38 0 39 | via2 FILLOPC 39 0 40 | via2 VIA 40 0 41 | via2 VIAFILL 41 0 42 | via2 VIAFILLOPC 42 0 43 | metal3 NET 43 0 44 | metal3 SPNET 44 0 45 | metal3 PIN 45 0 46 | metal3 LEFPIN 46 0 47 | metal3 FILL 47 0 48 | metal3 FILLOPC 48 0 49 | metal3 VIA 49 0 50 | metal3 VIAFILL 50 0 51 | metal3 VIAFILLOPC 51 0 52 | metal3 LEFOBS 52 0 53 | NAME metal3/NET 53 0 54 | NAME metal3/SPNET 54 0 55 | NAME metal3/PIN 55 0 56 | NAME metal3/LEFPIN 56 0 57 | via3 PIN 57 0 58 | via3 LEFPIN 58 0 59 | via3 FILL 59 0 60 | via3 FILLOPC 60 0 61 | via3 VIA 61 0 62 | via3 VIAFILL 62 0 63 | via3 VIAFILLOPC 63 0 64 | metal4 NET 64 0 65 | metal4 SPNET 65 0 66 | metal4 PIN 66 0 67 | metal4 LEFPIN 67 0 68 | metal4 FILL 68 0 69 | metal4 FILLOPC 69 0 70 | metal4 VIA 70 0 71 | metal4 VIAFILL 71 0 72 | metal4 VIAFILLOPC 72 0 73 | metal4 LEFOBS 73 0 74 | NAME metal4/NET 74 0 75 | NAME metal4/SPNET 75 0 76 | NAME metal4/PIN 76 0 77 | NAME metal4/LEFPIN 77 0 78 | via4 PIN 78 0 79 | via4 LEFPIN 79 0 80 | via4 FILL 80 0 81 | via4 FILLOPC 81 0 82 | via4 VIA 82 0 83 | via4 VIAFILL 83 0 84 | via4 VIAFILLOPC 84 0 85 | metal5 NET 85 0 86 | metal5 SPNET 86 0 87 | metal5 PIN 87 0 88 | metal5 LEFPIN 88 0 89 | metal5 FILL 89 0 90 | metal5 FILLOPC 90 0 91 | metal5 VIA 91 0 92 | metal5 VIAFILL 92 0 93 | metal5 VIAFILLOPC 93 0 94 | metal5 LEFOBS 94 0 95 | NAME metal5/NET 95 0 96 | NAME metal5/SPNET 96 0 97 | NAME metal5/PIN 97 0 98 | NAME metal5/LEFPIN 98 0 99 | via5 PIN 99 0 100 | via5 LEFPIN 100 0 101 | via5 FILL 101 0 102 | via5 FILLOPC 102 0 103 | via5 VIA 103 0 104 | via5 VIAFILL 104 0 105 | via5 VIAFILLOPC 105 0 106 | metal6 NET 106 0 107 | metal6 SPNET 107 0 108 | metal6 PIN 108 0 109 | metal6 LEFPIN 109 0 110 | metal6 FILL 110 0 111 | metal6 FILLOPC 111 0 112 | metal6 VIA 112 0 113 | metal6 VIAFILL 113 0 114 | metal6 VIAFILLOPC 114 0 115 | metal6 LEFOBS 115 0 116 | NAME metal6/NET 116 0 117 | NAME metal6/SPNET 117 0 118 | NAME metal6/PIN 118 0 119 | NAME metal6/LEFPIN 119 0 120 | via6 PIN 120 0 121 | via6 LEFPIN 121 0 122 | via6 FILL 122 0 123 | via6 FILLOPC 123 0 124 | via6 VIA 124 0 125 | via6 VIAFILL 125 0 126 | via6 VIAFILLOPC 126 0 127 | metal7 NET 127 0 128 | metal7 SPNET 128 0 129 | metal7 PIN 129 0 130 | metal7 LEFPIN 130 0 131 | metal7 FILL 131 0 132 | metal7 FILLOPC 132 0 133 | metal7 VIA 133 0 134 | metal7 VIAFILL 134 0 135 | metal7 VIAFILLOPC 135 0 136 | metal7 LEFOBS 136 0 137 | NAME metal7/NET 137 0 138 | NAME metal7/SPNET 138 0 139 | NAME metal7/PIN 139 0 140 | NAME metal7/LEFPIN 140 0 141 | via7 PIN 141 0 142 | via7 LEFPIN 142 0 143 | via7 FILL 143 0 144 | via7 FILLOPC 144 0 145 | via7 VIA 145 0 146 | via7 VIAFILL 146 0 147 | via7 VIAFILLOPC 147 0 148 | metal8 NET 148 0 149 | metal8 SPNET 149 0 150 | metal8 PIN 150 0 151 | metal8 LEFPIN 151 0 152 | metal8 FILL 152 0 153 | metal8 FILLOPC 153 0 154 | metal8 VIA 154 0 155 | metal8 VIAFILL 155 0 156 | metal8 VIAFILLOPC 156 0 157 | metal8 LEFOBS 157 0 158 | NAME metal8/NET 158 0 159 | NAME metal8/SPNET 159 0 160 | NAME metal8/PIN 160 0 161 | NAME metal8/LEFPIN 161 0 162 | NAME COMP 162 0 163 | COMP ALL 163 0 164 | DIEAREA ALL 164 0 165 | -------------------------------------------------------------------------------- /Pnr/scripts/Clock.ctstch: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # Generated by: Cadence First Encounter 08.10-p004_1 3 | # OS: Linux i686(Host ID localhost.localdomain) 4 | # Generated on: Wed Jul 12 14:03:21 2017 5 | # Command: clockDesign -genSpecOnly Clock.ctstch 6 | ############################################################### 7 | # 8 | # FirstEncounter(TM) Clock Synthesis Technology File Format 9 | # 10 | 11 | #-- MacroModel -- 12 | #MacroModel pin 13 | 14 | #-- Special Route Type -- 15 | #RouteTypeName specialRoute 16 | #TopPreferredLayer 4 17 | #BottomPreferredLayer 3 18 | #PreferredExtraSpace 1 19 | #End 20 | 21 | #-- Regular Route Type -- 22 | #RouteTypeName regularRoute 23 | #TopPreferredLayer 4 24 | #BottomPreferredLayer 3 25 | #PreferredExtraSpace 1 26 | #End 27 | 28 | #-- Clock Group -- 29 | #ClkGroup 30 | #+ 31 | 32 | #------------------------------------------------------------ 33 | # Clock Root : clk 34 | # Clock Name : clk 35 | # Clock Period : 10ns 36 | #------------------------------------------------------------ 37 | AutoCTSRootPin clk 38 | Period 10ns 39 | MaxDelay 1ns # default value 40 | MinDelay 0ns # default value 41 | MaxSkew 0.1ns # default value 42 | SinkMaxTran 0.8ns # default value 43 | BufMaxTran 0.8ns # default value 44 | Buffer BUFCKEHD BUFCHD BUFCKGHD 45 | NoGating NO 46 | DetailReport YES 47 | #SetDPinAsSync NO 48 | #SetIoPinAsSync NO 49 | #SetASyncSRPinAsSync NO 50 | #SetTriStEnPinAsSync NO 51 | #SetBBoxPinAsSync NO 52 | RouteClkNet YES 53 | #PostOpt YES 54 | #OptAddBuffer NO 55 | #RouteType specialRoute 56 | #LeafRouteType regularRoute 57 | ThroughPin 58 | END 59 | 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /Pnr/scripts/Default.globals: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # Generated by: Cadence Innovus 17.11-s080_1 3 | # OS: Linux x86_64(Host ID localhost.localdomain) 4 | # Generated on: Thu Jan 6 11:46:05 2022 5 | # Design: 6 | # Command: save_global Default.globals 7 | ############################################################### 8 | # 9 | # Version 1.1 10 | # 11 | 12 | set ::TimeLib::tsgMarkCellLatchConstructFlag 1 13 | set conf_qxconf_file {NULL} 14 | set conf_qxlib_file {NULL} 15 | set defHierChar {/} 16 | set distributed_client_message_echo {1} 17 | set distributed_mmmc_disable_reports_auto_redirection {0} 18 | set eco_post_client_restore_command {update_timing ; write_eco_opt_db ;} 19 | set enc_enable_print_mode_command_reset_options 1 20 | set init_gnd_net {GND} 21 | set init_lef_file {../UMC130nm/lef/StdCells/header8m2t_V55.lef ../UMC130nm/lef/StdCells/fsc0h_d_generic_core.lef ../UMC130nm/lef/StdCells/FSC0H_D_GENERIC_CORE_ANT_V55.8m2t.lef} 22 | set init_mmmc_file {MMMC.tcl} 23 | set init_pwr_net {VCC} 24 | set init_top_cell {FFT} 25 | set init_verilog {../syn/output/FFT.v} 26 | set latch_time_borrow_mode max_borrow 27 | set pegDefaultResScaleFactor 1 28 | set pegDetailResScaleFactor 1 29 | set report_inactive_arcs_format {from to when arc_type sense reason} 30 | set tso_post_client_restore_command {update_timing ; write_eco_opt_db ;} 31 | 32 | -------------------------------------------------------------------------------- /Pnr/scripts/MMMC.tcl: -------------------------------------------------------------------------------- 1 | # Version:1.0 MMMC View Definition File 2 | # Do Not Remove Above Line 3 | create_rc_corner -name FF -T {-40} -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0} 4 | create_rc_corner -name SS -T {125} -preRoute_res {1.0} -preRoute_cap {1.0} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.0} -postRoute_cap {1.0} -postRoute_xcap {1.0} -postRoute_clkres {0.0} -postRoute_clkcap {0.0} 5 | create_op_cond -name WCCOM -library_file {../UMC130nm/lib/StdCell/fsc0h_d_generic_core_ss1p08v125c.lib} -P {1} -V {1.08} -T {125} 6 | create_op_cond -name BCCOM -library_file {../UMC130nm/lib/StdCell/fsc0h_d_generic_core_ff1p32vm40c.lib} -P {1.0} -V {1.32} -T {-40} 7 | create_library_set -name FF -timing {../UMC130nm/lib/StdCell/fsc0h_d_generic_core_ff1p32vm40c.lib ../UMC130nm/lib/IO/foc0h_a33_t33_generic_io_ff1p32vm40c.lib} 8 | create_library_set -name SS -timing {../UMC130nm/lib/StdCell/fsc0h_d_generic_core_ss1p08v125c.lib ../UMC130nm/lib/IO/foc0h_a33_t33_generic_io_ss1p08v125c.lib} 9 | create_constraint_mode -name FFT -sdc_files {../syn/output/FFT.sdc} 10 | create_delay_corner -name FF -library_set {FF} -opcond_library {/home/abdelhay_ali/Desktop/Abdelazeem/FFT_Processor/UMC130nm/lib/StdCell/fsc0h_d_generic_core_ff1p32vm40c.lib} -opcond {BCCOM} -rc_corner {FF} 11 | create_delay_corner -name SS -library_set {SS} -opcond_library {/home/abdelhay_ali/Desktop/Abdelazeem/FFT_Processor/UMC130nm/lib/StdCell/fsc0h_d_generic_core_ss1p08v125c.lib} -opcond {WCCOM} -rc_corner {SS} 12 | create_analysis_view -name FF -constraint_mode {FFT} -delay_corner {FF} 13 | create_analysis_view -name SS -constraint_mode {FFT} -delay_corner {SS} 14 | set_analysis_view -setup {SS} -hold {FF} 15 | -------------------------------------------------------------------------------- /Pnr/scripts/pnr.tcl: -------------------------------------------------------------------------------- 1 | 2 | loadConfig ./Default.conf 3 | commitConfig 4 | source ./MMMC.tcl 5 | setDesignMode -process 130 6 | 7 | floorPlan -r 1 0.7 20.0 20.0 20.0 20.0 8 | #loadIoFile FFT.io 9 | 10 | addRing -nets {VCC GND} -follow core -stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 -layer {bottom metal1 top metal1 right metal2 left metal2} -width 3 -spacing 1 11 | addStripe -nets {VCC GND} -layer metal8 -width 4 -direction Horizontal -set_to_set_distance 22 -spacing 2 -extend_to design_boundary -start_y 2 -stop_y 48 12 | addStripe -nets {VCC GND} -layer metal7 -width 4 -direction Vertical -set_to_set_distance 20 -spacing 2 -extend_to design_boundary -start_x 7 -stop_x 98 13 | 14 | sroute -allowLayerChange 1 -blockPinTarget nearestTarget -crossoverViaBottomLayer M1 -crossoverViaTopLayer M4 -layerChangeRange {M1 M4} -nets {VCC VGND} 15 | 16 | #addWellTap -cell -fixedGap 30 17 | addEndCap -precap FILLER4EHD -postcap FILLER4EHD -prefix EndCap 18 | saveDesign ./saving/FFT_power.enc 19 | timeDesign -prePlace -idealClock -drvReports -outDir ./reports/preplace_timing 20 | timeDesign -prePlace -idealClock -hold -outDir ./reports/preplace_timing 21 | 22 | setPlaceMode -clkGateAware true -congEffort medium -ignoreScan -timingDriven true 23 | placeDesign 24 | timeDesign -preCTS -idealClock -drvReports -outDir ./reports/place_timing 25 | timeDesign -preCTS -idealClock -hold -outDir ./reports/place_timing 26 | 27 | optDesign -preCTS 28 | saveDesign ./saving/FFT_Placed.enc 29 | timeDesign -preCTS -idealClock -drvReports -outDir ./reports/postplace_timing 30 | timeDesign -preCTS -idealClock -hold -outDir ./reports/postplace_timing 31 | 32 | setCTSMode -moveGate true -opt true -optArea true -optLatency true -routeClkNet true -routeBottomPreferredLayer 1 -routeTopPreferredLayer 4 33 | clockDesign -specFile ./Clock.ctstch 34 | timeDesign -postCTS -drvReports -outDir ./reports/cts_timing 35 | timeDesign -postCTS -hold -outDir ./reports/cts_timing 36 | 37 | optDesign -postCTS 38 | saveDesign ./saving/FFT_cts.enc 39 | timeDesign -postCTS -drvReports -outDir ./reports/postcts_timing 40 | timeDesign -postCTS -hold -outDir ./reports/postcts_timing 41 | 42 | routeDesign -globalDetail -viaOpt -wireOpt 43 | timeDesign -postRoute -drvReports -outDir ./reports/route_timing 44 | timeDesign -postRoute -hold -outDir ./reports/route_timing 45 | 46 | optDesign -postRoute 47 | optDesign -postRoute -hold 48 | saveDesign ./saving/FFT_route.enc 49 | timeDesign -postRoute -drvReports -outDir ./reports/postroute_timing 50 | timeDesign -postRoute -hold -outDir ./reports/postroute_timing 51 | 52 | addFiller -cell {FILLER1HD FILLER2HD FILLER3HD FILLER4EHD FILLER8EHD FILLER16EHD FILLER32EHD FILLER64EHD} 53 | 54 | extractRC -outfile ./FFT_rc 55 | write_sdf FFT.sdf 56 | saveNetlist ./FFT.v -includePowerGround 57 | report_power -leakage -outfile FFT.pwr 58 | saveDesign ./saving/FFT.enc 59 | set map /home/abdelhay_ali/Desktop/Abdelazeem/FFT_Processor/UMC130nm/dfii/streamOut.map 60 | streamOut ./FFT.gds -units 100 -mapFile $map 61 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## *Overview* 2 | This repository contains the design and implementation of a 32-point Fast Fourier Transform (FFT) processor utilizing a pipelined architecture based on the radix-2 Decimation-In-Frequency (DIF) algorithm. 3 | 4 | ## *Introduction:* 5 | I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage. 6 | 7 | 8 | 9 | 10 | Building a 32-point pipelined FFT processor involves breaking down the FFT computation into stages and implementing those stages in a pipelined manner to optimize throughput. This README provides an overview of the algorithm, architecture, and implementation steps for creating such a processor. 11 | 12 | ## *Radix-2 DIF FFT* 13 | 14 | The radix-2 DIF FFT algorithm is a recursive process that divides the input data into smaller Discrete Fourier Transforms (DFTs) and combines them to form larger DFTs. For a 32-point FFT, the process involves sequential stages: 15 | 16 | __1. Stage 1:__ Divide the 32-point input into two sets of 16-point sequences. 17 | 18 | __2. Stage 2:__ Further divide each 16-point sequence into two 8-point sequences. 19 | 20 | __3. Stage 3:__ Divide each 8-point sequence into four 4-point sequences. 21 | 22 | __4. Stage 4:__ Continue this process down to two-point sequences and then single-point sequences. 23 | 24 | ## *Pipelined Architecture* 25 | 26 | A pipelined architecture executes multiple operations simultaneously by breaking down the computation into stages. This significantly increases throughput but introduces a delay due to pipelining. 27 | 28 | - __Single-Path Delay:__ The processor operates on a single path for input data through the entire pipeline, simplifying complexity but requiring careful control signal handling and synchronization. 29 | 30 | ## *Implementation Steps* 31 | Creating a 32-point pipelined FFT processor involves several essential steps: 32 | 33 | __1. Stage Decomposition:__ Break down the FFT computation into its individual stages following the radix-2 DIF algorithm. 34 | 35 | __2. Pipeline Register Insertion:__ Introduce pipeline registers between stages to enable concurrent operation. 36 | 37 | __3. Control Logic:__ Implement logic to manage data flow between pipeline stages and address potential hazards. 38 | 39 | __4. Arithmetic Units:__ Design efficient hardware for complex arithmetic operations (multiplication and addition) within each pipeline stage. 40 | 41 | __5. Memory and Buffering:__ Implement memory units and buffers for storing intermediate results. 42 | 43 | __6. Testing and Verification:__ Validate the functionality of the processor by testing it with various input patterns and verifying the output against expected results. 44 | 45 | ## *Pre-Synthesis Simulation using QuestaSim* 46 | 47 | 48 | 49 | ## *Synthesize using Design Compiler:* 50 | 51 | I have succeeded synthesis the design and met my constraints. 52 | 53 | ## Design Specification 54 | |Spec | value | 55 | |----------- | ------------- | 56 | |Cycle time | (10) ns | 57 | |Total area | 202213.12 µm^2| 58 | |Power | 9.9519 mW | 59 | |Techonlogy | UMC 130nm | 60 | 61 | 62 | 63 | *1- Delay Block:* 64 | 65 | The delay blocks are is simply a FIFO shift register. It will shift 24 bits every cycle. For delay 16, the shift register size is 16x24 = 384. 66 | 67 | 68 | 69 | *2- RADIX-2 BUTTERFLY* 70 | While entering the first radix-2 butterfly, din is extended to 24bits to match the twiddle factor. The radix-2 butterfly is the core processor of this circuit. It contains three states : 71 | 1. Waiting: In waiting state, we cannot do any calculation. For instance, we have to wait for x[16] in the first state to do x[0]+x[16], so x[0]~x[15] will be in waiting state. 72 | 2. First Half: In the first half, the output will be the summation of two index, e.g. x[0]+x[16]. We will output x[0]-x[16] to delay module simultaneously. 73 | 3. Second Half: In the last state, we multiply the delay signal, which is the signal we output to the delay module in the first half state, with our twiddle factor. Same as above, the input (din_a_r and din_b_r) will be output to the delay module. The complex number multiplication is transformed from 4 multiplication and 2 summation to 3 multiplication 5 summation. 74 | 75 | 76 | 77 | *4- ROM AND STATE CONTROL MODULE* 78 | The ROM is where the twiddle factors are stored. When it receives the valid signal from the front stage, it sets a counter. Based on the counter, it will output a state control output signal to the radix2 butterfly module. For the second half state where multiplication takes place, it will provide the needed twiddle factor. 79 | 80 | *5- SORT MODULE* 81 | Since we know the output signal order, we can simply control the order by directing the signal to a 2D array and place the value in the right place. For instance, the 2nd output is X[15], we can store it into result[15]. It will take 32 cycles to sort. To add on, the input of sort module is the most significant 16 bits of the output of the last radix-2 butterfly. 82 | 83 | ## *PnR using Innovus:* 84 | 85 | I have succeeded to meet my time constraints, and all the test-bench data passed, meaning that our functionality of layout works fine. 86 | 87 | 88 | 89 | The CMOS 0.13 μm is used to design Application Specific Integrated Circuit (ASIC) for the proposed FFT processor and it works with an input size of 32 bits at the operating frequency of 100 MHz, occupies an area of 1.27 mm and consumes 28 mW, at an operating voltage of 1.2V.Obtained results are compared with existing methods in terms of input word length, throughput, power dissipation and it shows that the proposed architecture gives high throughput, uses 3x more word length and 2x less power dissipation. 90 | 91 | ## *Conclusion* 92 | Building a 32-point pipelined FFT processor demands a profound understanding of FFT algorithms, hardware design, pipelining techniques, and control logic. The process typically involves using hardware description languages (VHDL or Verilog), simulation, synthesis, and implementation on suitable hardware (FPGAs or ASICs). Factors such as timing, power, and area constraints are crucial based on the target platform. 93 | -------------------------------------------------------------------------------- /RTL/FFT.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: FFT module 8 | // Dependencies: 9 | // Since: 2021-12-24 15:16:50 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-17-18 15:16:50 12 | // ******************************************************************** 13 | // Module Function 14 | `include "shift_16.v" 15 | `include "shift_8.v" 16 | `include "shift_4.v" 17 | `include "shift_2.v" 18 | `include "shift_1.v" 19 | `include "radix2.v" 20 | `include "ROM_16.v" 21 | `include "ROM_8.v" 22 | `include "ROM_4.v" 23 | `include "ROM_2.v" 24 | 25 | module FFT( 26 | input wire clk, 27 | input wire reset, 28 | input wire in_valid, 29 | input wire signed [11:0] din_r, 30 | input wire signed [11:0] din_i, 31 | output wire out_valid, 32 | output reg signed [15:0] dout_r, 33 | output reg signed [15:0] dout_i 34 | ); 35 | 36 | integer i; 37 | reg signed [15:0] result_r[0:31]; 38 | reg signed [15:0] result_i[0:31]; 39 | reg signed [15:0] result_r_ns[0:31]; 40 | reg signed [15:0] result_i_ns[0:31]; 41 | reg signed [15:0] next_dout_r; 42 | reg signed [15:0] next_dout_i; 43 | reg [5:0] count_y; 44 | reg [5:0] next_count_y; 45 | 46 | reg signed [23:0] din_r_reg,din_i_reg; 47 | reg in_valid_reg,r4_valid,next_r4_valid; 48 | reg [1:0] no5_state; 49 | reg s5_count,next_s5_count; 50 | reg next_over,over; 51 | reg assign_out; 52 | reg next_out_valid; 53 | reg [4:0]y_1_delay; 54 | 55 | wire [23:0] out_r,out_i; 56 | wire [4:0] y_1; 57 | wire [23:0] din_r_wire,din_i_wire; 58 | 59 | assign out_valid = assign_out; 60 | assign y_1 = (count_y>5'd0)? (count_y - 5'd1) : count_y; 61 | assign din_r_wire = din_r_reg; 62 | assign din_i_wire = din_i_reg; 63 | 64 | wire [1:0] rom16_state; 65 | wire [23:0]rom16_w_r,rom16_w_i; 66 | wire [23:0]shift_16_dout_r,shift_16_dout_i; 67 | wire [23:0] radix_no1_delay_r,radix_no1_delay_i; 68 | 69 | wire [1:0] rom8_state; 70 | wire [23:0]rom8_w_r,rom8_w_i; 71 | wire [23:0]shift_8_dout_r,shift_8_dout_i; 72 | wire [23:0]radix_no2_delay_r,radix_no2_delay_i; 73 | wire [23:0]radix_no1_op_r,radix_no1_op_i; 74 | wire [23:0]radix_no2_op_r,radix_no2_op_i; 75 | wire radix_no1_outvalid,radix_no2_outvalid; 76 | 77 | wire [1:0] rom4_state; 78 | wire [23:0]rom4_w_r,rom4_w_i; 79 | wire [23:0]shift_4_dout_r,shift_4_dout_i; 80 | wire [23:0]radix_no3_delay_r,radix_no3_delay_i; 81 | wire [23:0]radix_no3_op_r,radix_no3_op_i; 82 | wire radix_no3_outvalid; 83 | 84 | wire [1:0] rom2_state; 85 | wire [23:0]rom2_w_r,rom2_w_i; 86 | wire [23:0]shift_2_dout_r,shift_2_dout_i; 87 | wire [23:0]radix_no4_delay_r,radix_no4_delay_i; 88 | wire [23:0]radix_no4_op_r,radix_no4_op_i; 89 | wire radix_no4_outvalid; 90 | 91 | wire [23:0]shift_1_dout_r,shift_1_dout_i; 92 | wire [23:0]radix_no5_delay_r,radix_no5_delay_i; 93 | wire [23:0]radix_no5_op_r,radix_no5_op_i; 94 | 95 | radix2 radix_no1( 96 | .state(rom16_state),//state ctrl 97 | .din_a_r(shift_16_dout_r),//fb 98 | .din_a_i(shift_16_dout_i),//fb 99 | .din_b_r(din_r_wire),//input 100 | .din_b_i(din_i_wire),//input 101 | .w_r(rom16_w_r),//twindle_r 102 | .w_i(rom16_w_i),//twindle_i 103 | .op_r(radix_no1_op_r), 104 | .op_i(radix_no1_op_i), 105 | .delay_r(radix_no1_delay_r), 106 | .delay_i(radix_no1_delay_i), 107 | .outvalid(radix_no1_outvalid) 108 | ); 109 | 110 | shift_16 shift_16( 111 | .clk(clk),.reset(reset), 112 | .in_valid(in_valid_reg), 113 | .din_r(radix_no1_delay_r), 114 | .din_i(radix_no1_delay_i), 115 | .dout_r(shift_16_dout_r), 116 | .dout_i(shift_16_dout_i) 117 | ); 118 | 119 | ROM_16 rom16( 120 | .clk(clk), 121 | .in_valid(in_valid_reg), 122 | .reset(reset), 123 | .w_r(rom16_w_r), 124 | .w_i(rom16_w_i), 125 | .state(rom16_state) 126 | ); 127 | 128 | radix2 radix_no2( 129 | .state(rom8_state),//state ctrl 130 | .din_a_r(shift_8_dout_r),//fb 131 | .din_a_i(shift_8_dout_i),//fb 132 | .din_b_r(radix_no1_op_r),//input 133 | .din_b_i(radix_no1_op_i),//input 134 | .w_r(rom8_w_r),//twindle 135 | .w_i(rom8_w_i),//d 136 | .op_r(radix_no2_op_r), 137 | .op_i(radix_no2_op_i), 138 | .delay_r(radix_no2_delay_r), 139 | .delay_i(radix_no2_delay_i), 140 | .outvalid(radix_no2_outvalid) 141 | ); 142 | 143 | shift_8 shift_8( 144 | .clk(clk),.reset(reset), 145 | .in_valid(radix_no1_outvalid), 146 | .din_r(radix_no2_delay_r), 147 | .din_i(radix_no2_delay_i), 148 | .dout_r(shift_8_dout_r), 149 | .dout_i(shift_8_dout_i) 150 | ); 151 | 152 | ROM_8 rom8( 153 | .clk(clk), 154 | .in_valid(radix_no1_outvalid), 155 | .reset(reset), 156 | .w_r(rom8_w_r), 157 | .w_i(rom8_w_i), 158 | .state(rom8_state) 159 | ); 160 | 161 | 162 | radix2 radix_no3( 163 | .state(rom4_state),//state ctrl 164 | .din_a_r(shift_4_dout_r),//fb 165 | .din_a_i(shift_4_dout_i),//fb 166 | .din_b_r(radix_no2_op_r),//input 167 | .din_b_i(radix_no2_op_i),//input 168 | .w_r(rom4_w_r),//twindle 169 | .w_i(rom4_w_i),//d 170 | .op_r(radix_no3_op_r), 171 | .op_i(radix_no3_op_i), 172 | .delay_r(radix_no3_delay_r), 173 | .delay_i(radix_no3_delay_i), 174 | .outvalid(radix_no3_outvalid) 175 | ); 176 | 177 | shift_4 shift_4( 178 | .clk(clk),.reset(reset), 179 | .in_valid(radix_no2_outvalid), 180 | .din_r(radix_no3_delay_r), 181 | .din_i(radix_no3_delay_i), 182 | .dout_r(shift_4_dout_r), 183 | .dout_i(shift_4_dout_i) 184 | ); 185 | 186 | ROM_4 rom4( 187 | .clk(clk), 188 | .in_valid(radix_no2_outvalid), 189 | .reset(reset), 190 | .w_r(rom4_w_r), 191 | .w_i(rom4_w_i), 192 | .state(rom4_state) 193 | ); 194 | 195 | 196 | radix2 radix_no4( 197 | .state(rom2_state),//state ctrl 198 | .din_a_r(shift_2_dout_r),//fb 199 | .din_a_i(shift_2_dout_i),//fb 200 | .din_b_r(radix_no3_op_r),//input 201 | .din_b_i(radix_no3_op_i),//input 202 | .w_r(rom2_w_r),//twindle 203 | .w_i(rom2_w_i),//d 204 | .op_r(radix_no4_op_r), 205 | .op_i(radix_no4_op_i), 206 | .delay_r(radix_no4_delay_r), 207 | .delay_i(radix_no4_delay_i), 208 | .outvalid(radix_no4_outvalid) 209 | ); 210 | 211 | shift_2 shift_2( 212 | .clk(clk),.reset(reset), 213 | .in_valid(radix_no3_outvalid), 214 | .din_r(radix_no4_delay_r), 215 | .din_i(radix_no4_delay_i), 216 | .dout_r(shift_2_dout_r), 217 | .dout_i(shift_2_dout_i) 218 | ); 219 | 220 | ROM_2 rom2( 221 | .clk(clk), 222 | .in_valid(radix_no3_outvalid), 223 | .reset(reset), 224 | .w_r(rom2_w_r), 225 | .w_i(rom2_w_i), 226 | .state(rom2_state) 227 | ); 228 | 229 | 230 | radix2 radix_no5( 231 | .state(no5_state),//state ctrl 232 | .din_a_r(shift_1_dout_r),//fb 233 | .din_a_i(shift_1_dout_i),//fb 234 | .din_b_r(radix_no4_op_r),//input 235 | .din_b_i(radix_no4_op_i),//input 236 | .w_r(24'd256),//twindle 237 | .w_i(24'd0),//d 238 | .op_r(out_r), 239 | .op_i(out_i), 240 | .delay_r(radix_no5_delay_r), 241 | .delay_i(radix_no5_delay_i), 242 | .outvalid() 243 | ); 244 | 245 | shift_1 shift_1( 246 | .clk(clk),.reset(reset), 247 | .in_valid(radix_no4_outvalid), 248 | .din_r(radix_no5_delay_r), 249 | .din_i(radix_no5_delay_i), 250 | .dout_r(shift_1_dout_r), 251 | .dout_i(shift_1_dout_i) 252 | ); 253 | 254 | always@(posedge clk or posedge reset)begin 255 | if(reset)begin 256 | din_r_reg <= 0; 257 | din_i_reg <= 0; 258 | in_valid_reg <= 0; 259 | s5_count <= 0; 260 | r4_valid <= 0; 261 | count_y <= 0; 262 | assign_out <= 0; 263 | over <= 0; 264 | dout_r <= 0; 265 | dout_i <= 0; 266 | y_1_delay <= 0; 267 | for (i=0;i<=31;i=i+1) begin 268 | result_r[i] <= 0; 269 | result_i[i] <= 0; 270 | end 271 | end 272 | else begin 273 | din_r_reg <= {{4{din_r[11]}},din_r,8'b0}; 274 | din_i_reg <= {{4{din_i[11]}},din_i,8'b0}; 275 | in_valid_reg <= in_valid; 276 | s5_count <= next_s5_count; 277 | r4_valid <= next_r4_valid; 278 | count_y <= next_count_y; 279 | assign_out <= next_out_valid; 280 | over <= next_over; 281 | y_1_delay <= y_1; 282 | dout_r <= next_dout_r; 283 | dout_i <= next_dout_i; 284 | for (i=0;i<=31;i=i+1) begin 285 | result_r[i] <= result_r_ns[i]; 286 | result_i[i] <= result_i_ns[i]; 287 | end 288 | end 289 | end 290 | always@(*)begin 291 | 292 | next_r4_valid = radix_no4_outvalid; 293 | if (r4_valid)next_s5_count = s5_count + 1; 294 | else next_s5_count = s5_count; 295 | 296 | if(r4_valid && s5_count == 1'b0)no5_state = 2'b01; 297 | else if(r4_valid && s5_count == 1'b1)no5_state = 2'b10; 298 | else no5_state = 2'b00; 299 | 300 | if(radix_no4_outvalid) next_count_y = count_y + 5'd1; 301 | else next_count_y = count_y; 302 | 303 | if(next_out_valid) begin 304 | next_dout_r = result_r[y_1_delay]; 305 | next_dout_i = result_i[y_1_delay]; 306 | end 307 | else begin 308 | next_dout_r = dout_r; 309 | next_dout_i = dout_i; 310 | end 311 | end 312 | 313 | always @(*) begin 314 | 315 | next_over = over; 316 | for (i=0;i<=31;i=i+1) begin 317 | result_r_ns[i] = result_r[i]; 318 | result_i_ns[i] = result_i[i]; 319 | end 320 | if(next_over==1'b1)next_out_valid = 1'b1; 321 | else next_out_valid = assign_out; 322 | 323 | if(over!=1'b1) begin 324 | case((y_1)) 325 | 5'd0 : begin 326 | result_r_ns[31] = out_r[23:8]; 327 | result_i_ns[31] = out_i[23:8]; 328 | 329 | end 330 | 5'd1 : begin 331 | result_r_ns[15] = out_r[23:8]; 332 | result_i_ns[15] = out_i[23:8]; 333 | end 334 | 5'd2 : begin 335 | result_r_ns[7 ] = out_r[23:8]; 336 | result_i_ns[7 ] = out_i[23:8]; 337 | end 338 | 5'd3 : begin 339 | result_r_ns[23] = out_r[23:8]; 340 | result_i_ns[23] = out_i[23:8]; 341 | end 342 | 5'd4 : begin 343 | result_r_ns[3 ] = out_r[23:8]; 344 | result_i_ns[3 ] = out_i[23:8]; 345 | end 346 | 5'd5 : begin 347 | result_r_ns[19] = out_r[23:8]; 348 | result_i_ns[19] = out_i[23:8]; 349 | end 350 | 5'd6 : begin 351 | result_r_ns[11] = out_r[23:8]; 352 | result_i_ns[11] = out_i[23:8]; 353 | end 354 | 5'd7 : begin 355 | result_r_ns[27] = out_r[23:8]; 356 | result_i_ns[27] = out_i[23:8]; 357 | end 358 | 5'd8: begin 359 | result_r_ns[1 ] = out_r[23:8]; 360 | result_i_ns[1 ] = out_i[23:8]; 361 | end 362 | 5'd9: begin 363 | result_r_ns[17] = out_r[23:8]; 364 | result_i_ns[17] = out_i[23:8]; 365 | end 366 | 5'd10: begin 367 | result_r_ns[9] = out_r[23:8]; 368 | result_i_ns[9] = out_i[23:8]; 369 | end 370 | 5'd11: begin 371 | result_r_ns[25] = out_r[23:8]; 372 | result_i_ns[25] = out_i[23:8]; 373 | end 374 | 5'd12: begin 375 | result_r_ns[5 ] = out_r[23:8]; 376 | result_i_ns[5 ] = out_i[23:8]; 377 | end 378 | 5'd13: begin 379 | result_r_ns[21] = out_r[23:8]; 380 | result_i_ns[21] = out_i[23:8]; 381 | end 382 | 5'd14: begin 383 | result_r_ns[13] = out_r[23:8]; 384 | result_i_ns[13] = out_i[23:8]; 385 | end 386 | 5'd15: begin 387 | result_r_ns[29] = out_r[23:8]; 388 | result_i_ns[29] = out_i[23:8]; 389 | end 390 | 5'd16: begin 391 | result_r_ns[0 ] = out_r[23:8]; 392 | result_i_ns[0 ] = out_i[23:8]; 393 | end 394 | 5'd17: begin 395 | result_r_ns[16] = out_r[23:8]; 396 | result_i_ns[16] = out_i[23:8]; 397 | end 398 | 5'd18: begin 399 | result_r_ns[8 ] = out_r[23:8]; 400 | result_i_ns[8 ] = out_i[23:8]; 401 | end 402 | 5'd19: begin 403 | result_r_ns[24] = out_r[23:8]; 404 | result_i_ns[24] = out_i[23:8]; 405 | end 406 | 5'd20: begin 407 | result_r_ns[4 ] = out_r[23:8]; 408 | result_i_ns[4 ] = out_i[23:8]; 409 | end 410 | 5'd21: begin 411 | result_r_ns[20] = out_r[23:8]; 412 | result_i_ns[20] = out_i[23:8]; 413 | end 414 | 5'd22: begin 415 | result_r_ns[12] = out_r[23:8]; 416 | result_i_ns[12] = out_i[23:8]; 417 | end 418 | 5'd23: begin 419 | result_r_ns[28] = out_r[23:8]; 420 | result_i_ns[28] = out_i[23:8]; 421 | end 422 | 5'd24: begin 423 | result_r_ns[2 ] = out_r[23:8]; 424 | result_i_ns[2 ] = out_i[23:8]; 425 | end 426 | 5'd25: begin 427 | result_r_ns[18] = out_r[23:8]; 428 | result_i_ns[18] = out_i[23:8]; 429 | end 430 | 5'd26: begin 431 | result_r_ns[10] = out_r[23:8]; 432 | result_i_ns[10] = out_i[23:8]; 433 | end 434 | 5'd27: begin 435 | result_r_ns[26] = out_r[23:8]; 436 | result_i_ns[26] = out_i[23:8]; 437 | end 438 | 5'd28: begin 439 | result_r_ns[6 ] = out_r[23:8]; 440 | result_i_ns[6 ] = out_i[23:8]; 441 | end 442 | 5'd29: begin 443 | result_r_ns[22] = out_r[23:8]; 444 | result_i_ns[22] = out_i[23:8]; 445 | end 446 | 5'd30 : begin 447 | result_r_ns[14] = out_r[23:8]; 448 | result_i_ns[14] = out_i[23:8]; 449 | end 450 | 5'd31 : begin 451 | result_r_ns[30] = out_r[23:8]; 452 | result_i_ns[30] = out_i[23:8]; 453 | next_over = 1'b1; 454 | end 455 | 456 | endcase 457 | end 458 | end 459 | 460 | endmodule 461 | -------------------------------------------------------------------------------- /RTL/ROM_16.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: ROM_16 module 8 | // Dependencies: 9 | // Since: 2021-12-20 1:19:2 10 | // ******************************************************************** 11 | // Module Function 12 | module ROM_16( 13 | input wire clk, 14 | input wire in_valid, 15 | input wire reset, 16 | output reg [23:0] w_r, 17 | output reg [23:0] w_i, 18 | output reg[1:0] state 19 | ); 20 | 21 | reg valid,next_valid; 22 | reg [5:0] count,next_count; 23 | 24 | always@(posedge clk or posedge reset)begin 25 | if(reset)begin 26 | count <= 0; 27 | valid <= 0; 28 | end 29 | else if(in_valid) 30 | begin 31 | count <= next_count; 32 | valid <= in_valid; 33 | end 34 | else if (valid) 35 | begin 36 | count <= next_count; 37 | valid <= next_valid; 38 | end 39 | end 40 | 41 | always @(*) begin 42 | if(in_valid || valid)next_count = count + 1; 43 | else next_count = count; 44 | 45 | if (count<6'd16) 46 | state = 2'd0; 47 | else if (count >= 6'd16 && count < 6'd32) 48 | state = 2'd1; 49 | else if (count >= 6'd32 && count < 6'd48) 50 | state = 2'd2; 51 | else state = 2'd3; 52 | case(count) 53 | 6'd32: begin 54 | w_r = 24'b 00000000_00000001_00000000; 55 | w_i = 24'b 00000000_00000000_00000000; 56 | next_valid = 1'b1; 57 | end 58 | 6'd33: begin 59 | w_r = 24'b 00000000_00000000_11111011; 60 | w_i = 24'b 11111111_11111111_11001110; 61 | next_valid = 1'b1; 62 | end 63 | 6'd34: begin 64 | w_r = 24'b 00000000_00000000_11101101; 65 | w_i = 24'b 11111111_11111111_10011110; 66 | next_valid = 1'b1; 67 | end 68 | 6'd35: begin 69 | w_r = 24'b 00000000_00000000_11010101; 70 | w_i = 24'b 11111111_11111111_01110010; 71 | next_valid = 1'b1; 72 | end 73 | 6'd36: begin 74 | w_r = 24'b 00000000_00000000_10110101; 75 | w_i = 24'b 11111111_11111111_01001011; 76 | next_valid = 1'b1; 77 | end 78 | 6'd37: begin 79 | w_r = 24'b 00000000_00000000_10001110; 80 | w_i = 24'b 11111111_11111111_00101011; 81 | next_valid = 1'b1; 82 | end 83 | 6'd38: begin 84 | w_r = 24'b 00000000_00000000_01100010; 85 | w_i = 24'b 11111111_11111111_00010011; 86 | next_valid = 1'b1; 87 | end 88 | 6'd39: begin 89 | w_r = 24'b 00000000_00000000_00110010; 90 | w_i = 24'b 11111111_11111111_00000101; 91 | next_valid = 1'b1; 92 | end 93 | 6'd40: begin 94 | w_r = 24'b 00000000_00000000_00000000; 95 | w_i = 24'b 11111111_11111111_00000000; 96 | next_valid = 1'b1; 97 | end 98 | 6'd41: begin 99 | w_r = 24'b 11111111_11111111_11001110; 100 | w_i = 24'b 11111111_11111111_00000101; 101 | next_valid = 1'b1; 102 | end 103 | 6'd42: begin 104 | w_r = 24'b 11111111_11111111_10011110; 105 | w_i = 24'b 11111111_11111111_00010011; 106 | next_valid = 1'b1; 107 | end 108 | 6'd43: begin 109 | w_r = 24'b 11111111_11111111_01110010; 110 | w_i = 24'b 11111111_11111111_00101011; 111 | next_valid = 1'b1; 112 | end 113 | 6'd44: begin 114 | w_r = 24'b 11111111_11111111_01001011; 115 | w_i = 24'b 11111111_11111111_01001011; 116 | next_valid = 1'b1; 117 | end 118 | 6'd45: begin 119 | w_r = 24'b 11111111_11111111_00101011; 120 | w_i = 24'b 11111111_11111111_01110010; 121 | next_valid = 1'b1; 122 | end 123 | 6'd46: begin 124 | w_r = 24'b 11111111_11111111_00010011; 125 | w_i = 24'b 11111111_11111111_10011110; 126 | next_valid = 1'b1; 127 | end 128 | 6'd47: begin 129 | w_r = 24'b 11111111_11111111_00000101; 130 | w_i = 24'b 11111111_11111111_11001110; 131 | next_valid = 1'b0; 132 | end 133 | default: begin 134 | w_r = 24'b 00000000_00000001_00000000; 135 | w_i = 24'b 00000000_00000000_00000000; 136 | next_valid = 1'b1; 137 | end 138 | endcase 139 | end 140 | endmodule 141 | -------------------------------------------------------------------------------- /RTL/ROM_2.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: ROM_2 module 8 | // Dependencies: 9 | // Since: 2021-12-20 05:06:05 10 | // ******************************************************************** 11 | // Module Function 12 | module ROM_2( 13 | input wire clk, 14 | input wire in_valid, 15 | input wire reset, 16 | output reg [23:0] w_r, 17 | output reg [23:0] w_i, 18 | output reg[1:0] state 19 | ); 20 | 21 | reg valid,next_valid; 22 | reg [5:0] count,next_count; 23 | reg [1:0] s_count,next_s_count; 24 | 25 | always@(posedge clk or posedge reset)begin 26 | if(reset)begin 27 | count <= 0; 28 | s_count <= 0; 29 | end 30 | else begin 31 | count <= next_count; 32 | s_count <= next_s_count; 33 | end 34 | end 35 | 36 | always @(*) begin 37 | state = 2'd0; 38 | if(in_valid || valid) 39 | begin 40 | next_count = count + 1; 41 | next_s_count = s_count; 42 | end 43 | else begin 44 | next_count = count; 45 | next_s_count = s_count; 46 | end 47 | 48 | if (count<6'd2) 49 | state = 2'd0; 50 | else if (count >= 6'd2 && s_count < 2'd2)begin 51 | state = 2'd1; 52 | next_s_count = s_count + 1; 53 | end else if (count >= 6'd2 && s_count >= 2'd2)begin 54 | state = 2'd2; 55 | next_s_count = s_count + 1; 56 | end 57 | case(s_count) 58 | 2'd2: begin 59 | w_r = 24'b 00000000_00000001_00000000; 60 | w_i = 24'b 00000000_00000000_00000000; 61 | end 62 | 2'd3: begin 63 | w_r = 24'b 00000000_00000000_00000000; 64 | w_i = 24'b 11111111_11111111_00000000; 65 | end 66 | default: begin 67 | w_r = 24'b 00000000_00000001_00000000; 68 | w_i = 24'b 00000000_00000000_00000000; 69 | end 70 | endcase 71 | end 72 | endmodule 73 | -------------------------------------------------------------------------------- /RTL/ROM_4.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: ROM_4 module 8 | // Dependencies: 9 | // Since: 2021-12-20 07:10:20 10 | // ******************************************************************** 11 | // Module Function 12 | module ROM_4( 13 | input wire clk, 14 | input wire in_valid, 15 | input wire reset, 16 | output reg [23:0] w_r, 17 | output reg [23:0] w_i, 18 | output reg[1:0] state 19 | ); 20 | 21 | reg valid,next_valid; 22 | reg [5:0] count,next_count; 23 | reg [2:0] s_count,next_s_count; 24 | 25 | always@(posedge clk or posedge reset)begin 26 | if(reset)begin 27 | count <= 0; 28 | s_count <= 0; 29 | end 30 | else begin 31 | count <= next_count; 32 | s_count <= next_s_count; 33 | end 34 | end 35 | 36 | always @(*) begin 37 | if(in_valid || valid) 38 | begin 39 | next_count = count + 1; 40 | next_s_count = s_count; 41 | end 42 | else begin 43 | next_count = count; 44 | next_s_count = s_count; 45 | end 46 | 47 | if (count<6'd4) 48 | state = 2'd0; 49 | else if (count >= 6'd4 && s_count < 3'd4)begin 50 | state = 2'd1; 51 | next_s_count = s_count + 1; 52 | end 53 | else if (count >= 6'd4 && s_count >= 3'd4)begin 54 | state = 2'd2; 55 | next_s_count = s_count + 1; 56 | end 57 | case(s_count) 58 | 3'd4: begin 59 | w_r = 24'b 00000000_00000001_00000000; 60 | w_i = 24'b 00000000_00000000_00000000; 61 | end 62 | 3'd5: begin 63 | w_r = 24'b 00000000_00000000_10110101; 64 | w_i = 24'b 11111111_11111111_01001011; 65 | end 66 | 3'd6: begin 67 | w_r = 24'b 00000000_00000000_00000000; 68 | w_i = 24'b 11111111_11111111_00000000; 69 | end 70 | 3'd7: begin 71 | w_r = 24'b 11111111_11111111_01001011; 72 | w_i = 24'b 11111111_11111111_01001011; 73 | end 74 | default: begin 75 | w_r = 24'b 00000000_00000001_00000000; 76 | w_i = 24'b 00000000_00000000_00000000; 77 | end 78 | endcase 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /RTL/ROM_8.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: ROM_8 module 8 | // Dependencies: 9 | // Since: 2021-12-20 17:17:12 10 | // LastEditors: 2021-12-20 17:17:12 11 | // ******************************************************************** 12 | // Module Function 13 | module ROM_8( 14 | input wire clk, 15 | input wire in_valid, 16 | input wire reset, 17 | output reg [23:0] w_r, 18 | output reg [23:0] w_i, 19 | output reg[1:0] state 20 | ); 21 | 22 | reg valid,next_valid; 23 | reg [5:0] count,next_count; 24 | reg [3:0] s_count,next_s_count; 25 | 26 | always@(posedge clk or posedge reset)begin 27 | if(reset)begin 28 | count <= 0; 29 | s_count <= 0; 30 | end 31 | else begin 32 | count <= next_count; 33 | s_count <= next_s_count; 34 | end 35 | end 36 | 37 | always @(*) begin 38 | if(in_valid || valid) 39 | begin 40 | next_count = count + 1; 41 | next_s_count = s_count; 42 | end 43 | else begin 44 | next_count = count; 45 | next_s_count = s_count; 46 | end 47 | 48 | if (count<6'd8) 49 | state = 2'd0; 50 | else if (count >= 6'd8 && s_count < 4'd8)begin 51 | state = 2'd1; 52 | next_s_count = s_count + 1; 53 | end 54 | else if (count >= 6'd8 && s_count >= 4'd8)begin 55 | state = 2'd2; 56 | next_s_count = s_count + 1; 57 | end 58 | case(s_count) 59 | 4'd8: begin 60 | w_r = 24'b 00000000_00000001_00000000; 61 | w_i = 24'b 00000000_00000000_00000000; 62 | end 63 | 4'd9: begin 64 | w_r = 24'b 00000000_00000000_11101101; 65 | w_i = 24'b 11111111_11111111_10011110; 66 | end 67 | 4'd10: begin 68 | w_r = 24'b 00000000_00000000_10110101; 69 | w_i = 24'b 11111111_11111111_01001011; 70 | end 71 | 4'd11: begin 72 | w_r = 24'b 00000000_00000000_01100010; 73 | w_i = 24'b 11111111_11111111_00010011; 74 | end 75 | 4'd12: begin 76 | w_r = 24'b 00000000_00000000_00000000; 77 | w_i = 24'b 11111111_11111111_00000000; 78 | end 79 | 4'd13: begin 80 | w_r = 24'b 11111111_11111111_10011110; 81 | w_i = 24'b 11111111_11111111_00010011; 82 | end 83 | 4'd14: begin 84 | w_r = 24'b 11111111_11111111_01001011; 85 | w_i = 24'b 11111111_11111111_01001011; 86 | end 87 | 4'd15: begin 88 | w_r = 24'b 11111111_11111111_00010011; 89 | w_i = 24'b 11111111_11111111_10011110; 90 | end 91 | default: begin 92 | w_r = 24'b 00000000_00000001_00000000; 93 | w_i = 24'b 00000000_00000000_00000000; 94 | end 95 | endcase 96 | end 97 | endmodule 98 | -------------------------------------------------------------------------------- /RTL/radix2.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: radix2 module 8 | // Dependencies: 9 | // Since: 2021-12-24 05:10:50 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-24 05:10:50 12 | // ******************************************************************** 13 | // Module Function 14 | module radix2( 15 | input wire [1:0] state, 16 | input wire signed [23:0] din_a_r, 17 | input wire signed [23:0] din_a_i, 18 | input wire signed [23:0] din_b_r,//a 19 | input wire signed [23:0] din_b_i,//b 20 | input wire signed [23:0] w_r,//c 21 | input wire signed [23:0] w_i,//d 22 | output reg signed[23:0] op_r, 23 | output reg signed[23:0] op_i, 24 | output reg signed[23:0] delay_r, 25 | output reg signed[23:0] delay_i, 26 | output reg outvalid 27 | ); 28 | 29 | reg signed [41:0] inter,mul_r,mul_i;//was 27 30 | reg signed [23:0] a,b,c,d; 31 | 32 | always@(*)begin 33 | op_r = 0; 34 | op_i = 0; 35 | delay_r = din_b_r; 36 | delay_i = din_b_i; 37 | case(state) 38 | 2'b00:begin 39 | //waiting 40 | delay_r = din_b_r; 41 | delay_i = din_b_i; 42 | outvalid = 1'b0; 43 | end 44 | 2'b01:begin 45 | //first half 46 | a = din_a_r + din_b_r; 47 | b = din_a_i + din_b_i; 48 | 49 | c = (din_a_r - din_b_r);//a-b 50 | d = (din_a_i - din_b_i);//a-b 51 | 52 | op_r = a; 53 | op_i = b; 54 | delay_r = c; 55 | delay_i = d; 56 | outvalid = 1'b1; 57 | end 58 | 2'b10:begin 59 | //second half 60 | a = din_a_r; 61 | b = din_a_i; 62 | delay_r = din_b_r; 63 | delay_i = din_b_i; 64 | 65 | inter = b * (w_r - w_i); //b(c-d) 66 | mul_r = w_r * (a - b) + inter; 67 | mul_i = w_i * (a + b) + inter; 68 | 69 | op_r = (mul_r[31:8]); 70 | op_i = (mul_i[31:8]); 71 | outvalid = 1'b1; 72 | end 73 | 2'b11:begin 74 | //disable 75 | outvalid = 1'b0; 76 | end 77 | default:begin 78 | delay_r = din_b_r; 79 | delay_i = din_b_i; 80 | end 81 | endcase 82 | 83 | end 84 | 85 | 86 | endmodule 87 | -------------------------------------------------------------------------------- /RTL/shift_1.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: shift_1 module 8 | // Dependencies: 9 | // Since: 2021-12-22 10:12:13 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-2 10:12:53 12 | // ******************************************************************** 13 | // Module Function 14 | module shift_1( 15 | input wire clk, 16 | input wire reset, 17 | input wire in_valid, 18 | input signed [23:0] din_r, 19 | input signed [23:0] din_i, 20 | output signed [23:0] dout_r, 21 | output signed [23:0] dout_i 22 | ); 23 | integer i ; 24 | reg [23:0] shift_reg_r ; 25 | reg [23:0] shift_reg_i ; 26 | reg [23:0] tmp_reg_r ; 27 | reg [23:0] tmp_reg_i ; 28 | reg [1:0] counter_1,next_counter_1; 29 | reg valid,next_valid; 30 | 31 | assign dout_r = shift_reg_r[23:0]; 32 | assign dout_i = shift_reg_i[23:0]; 33 | 34 | always@(posedge clk or posedge reset)begin 35 | if(reset)begin 36 | shift_reg_r <= 0; 37 | shift_reg_i <= 0; 38 | counter_1 <= 0; 39 | valid <= 0; 40 | end 41 | else 42 | if (in_valid)begin 43 | counter_1 <= next_counter_1; 44 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 45 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 46 | valid <= in_valid; 47 | end else if(valid)begin 48 | counter_1 <= next_counter_1; 49 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 50 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 51 | valid <= next_valid; 52 | end 53 | end 54 | 55 | always@(*)begin 56 | next_counter_1 = counter_1 + 2'd1; 57 | tmp_reg_r = shift_reg_r; 58 | tmp_reg_i = shift_reg_i; 59 | next_valid = valid; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /RTL/shift_16.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: shift_16 module 8 | // Dependencies: 9 | // Since: 2021-12-22 2:22:03 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-22 2:22:03 12 | // ******************************************************************** 13 | // Module Function 14 | module shift_16( 15 | input wire clk, 16 | input wire reset, 17 | input wire in_valid, 18 | input wire signed [23:0] din_r, 19 | input wire signed [23:0] din_i, 20 | output wire signed [23:0] dout_r, 21 | output wire signed [23:0] dout_i 22 | ); 23 | integer i ; 24 | reg [383:0] shift_reg_r ; 25 | reg [383:0] shift_reg_i ; 26 | reg [383:0] tmp_reg_r ; 27 | reg [383:0] tmp_reg_i ; 28 | reg [5:0] counter_16,next_counter_16; 29 | reg valid,next_valid; 30 | 31 | assign dout_r = shift_reg_r[383:360]; 32 | assign dout_i = shift_reg_i[383:360]; 33 | 34 | always@(posedge clk or posedge reset)begin 35 | if(reset)begin 36 | shift_reg_r <= 0; 37 | shift_reg_i <= 0; 38 | counter_16 <= 0; 39 | valid <= 0; 40 | end 41 | else 42 | if (in_valid)begin 43 | counter_16 <= next_counter_16; 44 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 45 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 46 | valid <= in_valid; 47 | end 48 | else if (valid)begin 49 | counter_16 <= next_counter_16; 50 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 51 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 52 | valid <= next_valid; 53 | end 54 | end 55 | 56 | 57 | always@(*)begin 58 | next_counter_16 = counter_16 + 5'd1; 59 | tmp_reg_r = shift_reg_r; 60 | tmp_reg_i = shift_reg_i; 61 | next_valid = valid; 62 | end 63 | 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /RTL/shift_2.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: shift_2 module 8 | // Dependencies: 9 | // Since: 2021-12-22 5:16:18 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-22 5:16:18 12 | // ******************************************************************** 13 | // Module Function 14 | module shift_2( 15 | input wire clk, 16 | input wire reset, 17 | input wire in_valid, 18 | input wire signed [23:0] din_r, 19 | input wire signed [23:0] din_i, 20 | output wire signed [23:0] dout_r, 21 | output wire signed [23:0] dout_i 22 | ); 23 | integer i ; 24 | reg [47:0] shift_reg_r ; 25 | reg [47:0] shift_reg_i ; 26 | reg [47:0] tmp_reg_r ; 27 | reg [47:0] tmp_reg_i ; 28 | reg [2:0] counter_2,next_counter_2; 29 | reg valid,next_valid; 30 | 31 | assign dout_r = shift_reg_r[47:24]; 32 | assign dout_i = shift_reg_i[47:24]; 33 | 34 | always@(posedge clk or posedge reset)begin 35 | if(reset)begin 36 | shift_reg_r <= 0; 37 | shift_reg_i <= 0; 38 | counter_2 <= 0; 39 | valid <= 0; 40 | end 41 | else 42 | if (in_valid)begin 43 | counter_2 <= next_counter_2; 44 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 45 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 46 | valid <= in_valid; 47 | end else if(valid)begin 48 | counter_2 <= next_counter_2; 49 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 50 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 51 | valid <= next_valid; 52 | end 53 | end 54 | 55 | always@(*)begin 56 | next_counter_2 = counter_2 + 2'd1; 57 | tmp_reg_r = shift_reg_r; 58 | tmp_reg_i = shift_reg_i; 59 | next_valid = valid; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /RTL/shift_4.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: shift_4 module 8 | // Dependencies: 9 | // Since: 2021-12-23 01:14:14 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-13 01:14:14 12 | // ******************************************************************** 13 | // Module Function 14 | module shift_4( 15 | input wire clk, 16 | input wire reset, 17 | input wire in_valid, 18 | input wire signed [23:0] din_r, 19 | input wire signed [23:0] din_i, 20 | output wire signed [23:0] dout_r, 21 | output wire signed [23:0] dout_i 22 | ); 23 | integer i ; 24 | reg [95:0] shift_reg_r ; 25 | reg [95:0] shift_reg_i ; 26 | reg [95:0] tmp_reg_r ; 27 | reg [95:0] tmp_reg_i ; 28 | reg [3:0] counter_4,next_counter_4; 29 | reg valid,next_valid; 30 | 31 | assign dout_r = shift_reg_r[95:72]; 32 | assign dout_i = shift_reg_i[95:72]; 33 | 34 | always@(posedge clk or posedge reset)begin 35 | if(reset)begin 36 | shift_reg_r <= 0; 37 | shift_reg_i <= 0; 38 | counter_4 <= 0; 39 | valid <= 0; 40 | end 41 | else 42 | if (in_valid)begin 43 | counter_4 <= next_counter_4; 44 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 45 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 46 | valid <= in_valid; 47 | end else if(valid)begin 48 | counter_4 <= next_counter_4; 49 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 50 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 51 | valid <= next_valid; 52 | end 53 | end 54 | 55 | always@(*)begin 56 | next_counter_4 = counter_4 + 3'd1; 57 | tmp_reg_r = shift_reg_r; 58 | tmp_reg_i = shift_reg_i; 59 | next_valid = valid; 60 | end 61 | 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /RTL/shift_8.v: -------------------------------------------------------------------------------- 1 | // -------------------------------------------------------------------- 2 | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | // -------------------------------------------------------------------- 4 | // Author: Ahmed Abdelazeem 5 | // Github: https://github.com/abdelazeem201 6 | // Email: ahmed_abdelazeem@outlook.com 7 | // Description: shift_1 module 8 | // Dependencies: 9 | // Since: 2021-12-23 10:18:53 10 | // LastEditors: ahmed abdelazeem 11 | // LastEditTime: 2021-12-23 10:18:53 12 | // ******************************************************************** 13 | // Module Function 14 | module shift_8( 15 | input wire clk, 16 | input wire reset, 17 | input wire in_valid, 18 | input wire signed [23:0] din_r, 19 | input wire signed [23:0] din_i, 20 | output wire signed [23:0] dout_r, 21 | output wire signed [23:0] dout_i 22 | ); 23 | integer i ; 24 | reg [191:0] shift_reg_r ; 25 | reg [191:0] shift_reg_i ; 26 | reg [191:0] tmp_reg_r ; 27 | reg [191:0] tmp_reg_i ; 28 | reg [4:0] counter_8,next_counter_8; 29 | reg valid,next_valid; 30 | 31 | assign dout_r = shift_reg_r[191:168]; 32 | assign dout_i = shift_reg_i[191:168]; 33 | 34 | always@(posedge clk or posedge reset)begin 35 | if(reset)begin 36 | shift_reg_r <= 0; 37 | shift_reg_i <= 0; 38 | counter_8 <= 0; 39 | valid <= 0; 40 | end 41 | else 42 | if (in_valid)begin 43 | counter_8 <= next_counter_8; 44 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 45 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 46 | valid <= in_valid; 47 | end else if(valid)begin 48 | counter_8 <= next_counter_8; 49 | shift_reg_r <= (tmp_reg_r<<24) + din_r; 50 | shift_reg_i <= (tmp_reg_i<<24) + din_i; 51 | valid <= next_valid; 52 | end 53 | end 54 | 55 | 56 | always@(*)begin 57 | next_counter_8 = counter_8 + 4'd1; 58 | tmp_reg_r = shift_reg_r; 59 | tmp_reg_i = shift_reg_i; 60 | next_valid = valid; 61 | end 62 | endmodule 63 | -------------------------------------------------------------------------------- /SIM/FFT.c: -------------------------------------------------------------------------------- 1 | #include "fft.h" 2 | 3 | #include 4 | 5 | #include 6 | #include 7 | 8 | 9 | 10 | /* ===== In-Place FFT ======================================================= */ 11 | 12 | 13 | 14 | void ffti_f(complex_f data[], unsigned log2_N, fft_dir direction) 15 | { 16 | ffti_shuffle_f(data, log2_N); 17 | ffti_evaluate_f(data, log2_N, direction); 18 | } 19 | 20 | 21 | 22 | void ffti_copy_shuffle_f(complex_f src[], complex_f dst[], unsigned log2_N) 23 | { 24 | /* 25 | * Basic Bit-Reversal Scheme: 26 | * 27 | * The incrementing pattern operations used here correspond 28 | * to the logic operations of a synchronous counter. 29 | * 30 | * Incrementing a binary number simply flips a sequence of 31 | * least-significant bits, for example from 0111 to 1000. 32 | * So in order to compute the next bit-reversed index, we 33 | * have to flip a sequence of most-significant bits. 34 | */ 35 | 36 | unsigned N = 1 << log2_N; /* N */ 37 | unsigned Nd2 = N >> 1; /* N/2 = number range midpoint */ 38 | unsigned Nm1 = N - 1; /* N-1 = digit mask */ 39 | unsigned i; /* index for source element */ 40 | unsigned j; /* index for next destination element */ 41 | 42 | for (i = 0, j = 0; i < N; i++) { 43 | dst[j] = src[i]; 44 | 45 | /* 46 | * Find least significant zero bit 47 | */ 48 | 49 | unsigned lszb = ~i & (i + 1); 50 | 51 | /* 52 | * Use division to bit-reverse the single bit so that we now have 53 | * the most significant zero bit 54 | * 55 | * N = 2^r = 2^(m+1) 56 | * Nd2 = N/2 = 2^m 57 | * if lszb = 2^k, where k is within the range of 0...m, then 58 | * mszb = Nd2 / lszb 59 | * = 2^m / 2^k 60 | * = 2^(m-k) 61 | * = bit-reversed value of lszb 62 | */ 63 | 64 | unsigned mszb = Nd2 / lszb; 65 | 66 | /* 67 | * Toggle bits with bit-reverse mask 68 | */ 69 | 70 | unsigned bits = Nm1 & ~(mszb - 1); 71 | j ^= bits; 72 | } 73 | } 74 | 75 | 76 | 77 | void ffti_shuffle_f(complex_f data[], unsigned log2_N) 78 | { 79 | /* 80 | * Basic Bit-Reversal Scheme: 81 | * 82 | * The incrementing pattern operations used here correspond 83 | * to the logic operations of a synchronous counter. 84 | * 85 | * Incrementing a binary number simply flips a sequence of 86 | * least-significant bits, for example from 0111 to 1000. 87 | * So in order to compute the next bit-reversed index, we 88 | * have to flip a sequence of most-significant bits. 89 | */ 90 | 91 | unsigned N = 1 << log2_N; /* N */ 92 | unsigned Nd2 = N >> 1; /* N/2 = number range midpoint */ 93 | unsigned Nm1 = N - 1; /* N-1 = digit mask */ 94 | unsigned i; /* index for array elements */ 95 | unsigned j; /* index for next element swap location */ 96 | 97 | for (i = 0, j = 0; i < N; i++) { 98 | if (j > i) { 99 | complex_f tmp = data[i]; 100 | data[i] = data[j]; 101 | data[j] = tmp; 102 | } 103 | 104 | /* 105 | * Find least significant zero bit 106 | */ 107 | 108 | unsigned lszb = ~i & (i + 1); 109 | 110 | /* 111 | * Use division to bit-reverse the single bit so that we now have 112 | * the most significant zero bit 113 | * 114 | * N = 2^r = 2^(m+1) 115 | * Nd2 = N/2 = 2^m 116 | * if lszb = 2^k, where k is within the range of 0...m, then 117 | * mszb = Nd2 / lszb 118 | * = 2^m / 2^k 119 | * = 2^(m-k) 120 | * = bit-reversed value of lszb 121 | */ 122 | 123 | unsigned mszb = Nd2 / lszb; 124 | 125 | /* 126 | * Toggle bits with bit-reverse mask 127 | */ 128 | 129 | unsigned bits = Nm1 & ~(mszb - 1); 130 | j ^= bits; 131 | } 132 | } 133 | 134 | 135 | 136 | void ffti_evaluate_f(complex_f data[], unsigned log2_N, fft_dir direction) 137 | { 138 | /* 139 | * In-place FFT butterfly algorithm 140 | * 141 | * input: 142 | * A[] = array of N shuffled complex values where N is a power of 2 143 | * output: 144 | * A[] = the DFT of input A[] 145 | * 146 | * for r = 1 to log2(N) 147 | * m = 2^r 148 | * Wm = exp(−j2π/m) 149 | * for n = 0 to N-1 by m 150 | * Wmk = 1 151 | * for k = 0 to m/2 - 1 152 | * u = A[n + k] 153 | * t = Wmk * A[n + k + m/2] 154 | * A[n + k] = u + t 155 | * A[n + k + m/2] = u - t 156 | * Wmk = Wmk * Wm 157 | * 158 | * For inverse FFT, use Wm = exp(+j2π/m) 159 | */ 160 | 161 | unsigned N; 162 | unsigned r; 163 | unsigned m, md2; 164 | unsigned n, k; 165 | unsigned i_e, i_o; 166 | double theta_2pi; 167 | double theta; /* Use double for precision */ 168 | complex_d Wm, Wmk; /* Use double for precision */ 169 | complex_d u, t; /* Use double for precision */ 170 | 171 | N = 1 << log2_N; 172 | theta_2pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 173 | theta_2pi *= 2; 174 | 175 | for (r = 1; r <= log2_N; r++) 176 | { 177 | m = 1 << r; 178 | md2 = m >> 1; 179 | theta = theta_2pi / m; 180 | Wm.re = cos(theta); 181 | Wm.im = sin(theta); 182 | for (n = 0; n < N; n += m) 183 | { 184 | Wmk.re = 1.f; 185 | Wmk.im = 0.f; 186 | for (k = 0; k < md2; k++) 187 | { 188 | i_e = n + k; 189 | i_o = i_e + md2; 190 | u.re = data[i_e].re; 191 | u.im = data[i_e].im; 192 | t.re = complex_mul_re(Wmk.re, Wmk.im, data[i_o].re, data[i_o].im); 193 | t.im = complex_mul_im(Wmk.re, Wmk.im, data[i_o].re, data[i_o].im); 194 | data[i_e].re = u.re + t.re; 195 | data[i_e].im = u.im + t.im; 196 | data[i_o].re = u.re - t.re; 197 | data[i_o].im = u.im - t.im; 198 | t.re = complex_mul_re(Wmk.re, Wmk.im, Wm.re, Wm.im); 199 | t.im = complex_mul_im(Wmk.re, Wmk.im, Wm.re, Wm.im); 200 | Wmk = t; 201 | } 202 | } 203 | } 204 | } 205 | 206 | 207 | 208 | /* ===== Recursive FFT ====================================================== */ 209 | 210 | 211 | 212 | void fftr_f(complex_f data[], unsigned log2_N, fft_dir direction) 213 | { 214 | /* 215 | * fft(A[], N): 216 | * if N == 1 217 | * return 218 | * for k = 0 to N/2-1 219 | * e[k] = A[2*k] 220 | * o[k] = A[2*k+1] 221 | * fft(e, N/2) 222 | * fft(o, N/2); 223 | * WN = exp(−j2π/N) 224 | * WNk = 1 225 | * for k = 0 to N/2-1 226 | * A[k] = e[k] + WNk * o[k] 227 | * A[k+N/2] = e[k] - WNk * o[k] 228 | * WNk = WNk * WN 229 | * 230 | * For inverse FFT, use Wm = exp(+j2π/N) 231 | */ 232 | 233 | if (log2_N > 0) 234 | { 235 | unsigned log2_Nd2; 236 | unsigned Nd2; 237 | unsigned k; 238 | unsigned kpNd2; 239 | complex_f *evn, *odd; 240 | double theta_pi; 241 | double theta; /* Use double for precision */ 242 | complex_d WN, WNk; /* Use double for precision */ 243 | complex_d u, t; /* Use double for precision */ 244 | 245 | log2_Nd2 = log2_N - 1; 246 | Nd2 = 1 << log2_Nd2; 247 | 248 | evn = malloc(Nd2 * sizeof(complex_f)); 249 | odd = malloc(Nd2 * sizeof(complex_f)); 250 | 251 | for (k = 0; k < Nd2; k++) 252 | { 253 | evn[k] = data[2*k]; 254 | odd[k] = data[2*k+1]; 255 | } 256 | 257 | fftr_f(evn, log2_Nd2, direction); 258 | fftr_f(odd, log2_Nd2, direction); 259 | 260 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 261 | theta = theta_pi / Nd2; /* - (2 * M_PI) / N */ 262 | WN.re = cos(theta); 263 | WN.im = sin(theta); 264 | 265 | WNk.re = 1.f; 266 | WNk.im = 0.f; 267 | for (k = 0; k < Nd2; k++) 268 | { 269 | kpNd2 = k + Nd2; 270 | 271 | u.re = evn[k].re; 272 | u.im = evn[k].im; 273 | t.re = complex_mul_re(WNk.re, WNk.im, odd[k].re, odd[k].im); 274 | t.im = complex_mul_im(WNk.re, WNk.im, odd[k].re, odd[k].im); 275 | data[k].re = u.re + t.re; 276 | data[k].im = u.im + t.im; 277 | data[kpNd2].re = u.re - t.re; 278 | data[kpNd2].im = u.im - t.im; 279 | 280 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 281 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 282 | WNk = t; 283 | } 284 | 285 | free(evn); 286 | free(odd); 287 | } 288 | } 289 | 290 | 291 | 292 | /* ===== Recursive FFT, user-supplied scratchpad buffer ===================== */ 293 | 294 | 295 | 296 | #if 0 297 | 298 | 299 | 300 | /* 301 | * A more efficient version of the fftr_f() implementation, where a 302 | * user-supplied buffer is used to hold the even/odd decompositions 303 | */ 304 | 305 | void fftrb_f(complex_f data[], unsigned log2_N, fft_dir direction, complex_f scratch[]) 306 | { 307 | /* 308 | * fft(A[], N): 309 | * if N == 1 310 | * return 311 | * for k = 0 to N/2-1 312 | * e[k] = A[2*k] 313 | * o[k] = A[2*k+1] 314 | * fft(e, N/2) 315 | * fft(o, N/2); 316 | * WN = exp(−j2π/N) 317 | * WNk = 1 318 | * for k = 0 to N/2-1 319 | * A[k] = e[k] + WNk * o[k] 320 | * A[k+N/2] = e[k] - WNk * o[k] 321 | * WNk = WNk * WN 322 | * 323 | * For inverse FFT, use Wm = exp(+j2π/N) 324 | */ 325 | 326 | if (log2_N > 0) 327 | { 328 | unsigned log2_Nd2; 329 | unsigned Nd2; 330 | unsigned k; 331 | unsigned kpNd2; 332 | complex_f *evn, *odd; 333 | double theta_pi; 334 | double theta; /* Use double for precision */ 335 | complex_d WN, WNk; /* Use double for precision */ 336 | complex_d u, t; /* Use double for precision */ 337 | 338 | log2_Nd2 = log2_N - 1; 339 | Nd2 = 1 << log2_Nd2; 340 | 341 | evn = scratch; 342 | odd = scratch + Nd2; 343 | 344 | for (k = 0; k < Nd2; k++) 345 | { 346 | evn[k] = data[2*k]; 347 | odd[k] = data[2*k+1]; 348 | } 349 | 350 | fftr_f(evn, log2_Nd2, direction); 351 | fftr_f(odd, log2_Nd2, direction); 352 | 353 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 354 | theta = theta_pi / Nd2; /* - (2 * M_PI) / N */ 355 | WN.re = cos(theta); 356 | WN.im = sin(theta); 357 | 358 | WNk.re = 1.f; 359 | WNk.im = 0.f; 360 | for (k = 0; k < Nd2; k++) 361 | { 362 | kpNd2 = k + Nd2; 363 | 364 | u.re = evn[k].re; 365 | u.im = evn[k].im; 366 | t.re = complex_mul_re(WNk.re, WNk.im, odd[k].re, odd[k].im); 367 | t.im = complex_mul_im(WNk.re, WNk.im, odd[k].re, odd[k].im); 368 | data[k].re = u.re + t.re; 369 | data[k].im = u.im + t.im; 370 | data[kpNd2].re = u.re - t.re; 371 | data[kpNd2].im = u.im - t.im; 372 | 373 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 374 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 375 | WNk = t; 376 | } 377 | } 378 | } 379 | 380 | 381 | 382 | #else 383 | 384 | 385 | 386 | /* 387 | * A much more efficient version of the recursive FFT algorithm, where 388 | * the data and scratch buffers are commutated throughout the recursion 389 | * sequence, and index mapping is used to locate the correct values 390 | */ 391 | 392 | void _fftrb_f(complex_f data[], complex_f scratch[], int N, double theta_pi, int stride) 393 | { 394 | if (stride < N) 395 | { 396 | unsigned stride2; 397 | unsigned k; 398 | unsigned k_e, k_o; 399 | unsigned kd2, kpNd2; 400 | double theta; /* Use double for precision */ 401 | complex_d WN, WNk; /* Use double for precision */ 402 | complex_d u, t; /* Use double for precision */ 403 | 404 | stride2 = 2 * stride; 405 | 406 | /* Notice that the order of data and scratch buffers is swapped! */ 407 | _fftrb_f(scratch , data , N, theta_pi, stride2); 408 | _fftrb_f(scratch + stride, data + stride, N, theta_pi, stride2); 409 | 410 | theta = (stride2 * theta_pi) / N; 411 | WN.re = cos(theta); 412 | WN.im = sin(theta); 413 | 414 | WNk.re = 1.f; 415 | WNk.im = 0.f; 416 | for (k = 0; k < N; k += stride2) 417 | { 418 | k_e = k; 419 | k_o = k + stride; 420 | kd2 = k >> 1; 421 | kpNd2 = (k + N) >> 1; 422 | 423 | u.re = scratch[k_e].re; 424 | u.im = scratch[k_e].im; 425 | t.re = complex_mul_re(WNk.re, WNk.im, scratch[k_o].re, scratch[k_o].im); 426 | t.im = complex_mul_im(WNk.re, WNk.im, scratch[k_o].re, scratch[k_o].im); 427 | 428 | data[kd2].re = u.re + t.re; 429 | data[kd2].im = u.im + t.im; 430 | data[kpNd2].re = u.re - t.re; 431 | data[kpNd2].im = u.im - t.im; 432 | 433 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 434 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 435 | WNk = t; 436 | } 437 | } 438 | } 439 | 440 | 441 | 442 | void fftrb_f(complex_f data[], unsigned log2_N, fft_dir direction, complex_f scratch[]) 443 | { 444 | unsigned N; 445 | unsigned k; 446 | double theta_pi; 447 | 448 | N = 1 << log2_N; 449 | for (k = 0; k < N; k++) 450 | scratch[k] = data[k]; 451 | 452 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 453 | 454 | _fftrb_f(data, scratch, N, theta_pi, 1); 455 | } 456 | -------------------------------------------------------------------------------- /SIM/FFT.py: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------- 2 | # >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | # -------------------------------------------------------------------- 4 | # Author: Ahmed Abdelazeem 5 | # Github: https://github.com/abdelazeem201 6 | # Email: ahmed_abdelazeem@outlook.com 7 | # Description: FFT.py 8 | # Dependencies: 9 | # Since: 2021-12-2 5:16:50 10 | # LastEditors: ahmed abdelazeem 11 | # LastEditTime: 2021-12-2 5:16:50 12 | 13 | # Description 14 | # I've implemented a multi-stage computation using the radix-2 FFT (Fast Fourier Transform) algorithm. Each stage performs specific operations on the input data and generates output. The process is sequential and iterative, resulting in a final set of computed values. 15 | 16 | # Here's a general summary of what each stage appears to do: 17 | # 1. Stage 1: Computes additions and subtractions based on the input data (mem and img) and applies multiplication by complex twiddle factors (w and w_i). 18 | # 2. Stages 2-5: Repeat similar computations but with different grouping and computation arrangements. 19 | # The code follows a common structure seen in FFT algorithms where data is sequentially manipulated through stages, each refining the frequency domain representation of the input data. 20 | # The final output seems to be stored in final_ans_r and final_ans_i, which are arrays holding the computed real and imaginary parts of the FFT result. 21 | # 22 | 23 | # ******************************************************************** 24 | # Module Function 25 | n = 0 26 | mem = [] 27 | img = [] 28 | stage1_r = [] 29 | stage1_i = [] 30 | minus_r = [] 31 | minus_i = [] 32 | 33 | w = [0 for i in range(16)] 34 | w_i = [0 for i in range(16)] 35 | 36 | with open("IN_real_pattern01.txt") as f: 37 | for line_terminated in f: 38 | line = line_terminated.rstrip('\n') 39 | tmpStr = '' 40 | for i in range(0,len(line)): 41 | tmpStr+=line[i] 42 | mem.append(tmpStr) 43 | 44 | with open("IN_imag_pattern01.txt") as f: 45 | for line_terminated in f: 46 | line = line_terminated.rstrip('\n') 47 | tmpStr = '' 48 | for i in range(0,len(line)): 49 | tmpStr+=line[i] 50 | img.append(tmpStr) 51 | w[0] = 1 52 | w[1] = 0.98078 53 | w[2] = 0.92397 54 | w[3] = 0.83147 55 | w[4] = 0.7071 56 | w[5] = 0.5555 57 | w[6] = 0.3826 58 | w[7] = 0.1951 59 | w[8] = 0 60 | for i in range(1,8): 61 | w[8+i] = (w[8-i]*(-1)) 62 | 63 | w_i[0] = 0 64 | w_i[1] = -0.1950 65 | w_i[2] = -0.3826 66 | w_i[3] = -0.555 67 | w_i[4] = -0.707 68 | w_i[5] = -0.831 69 | w_i[6] = -0.9238 70 | w_i[7] = -0.9807 71 | w_i[8] = -1 72 | for i in range(1,8): 73 | w_i[8+i] = w_i[8-i] 74 | 75 | print('-------------stage 1 answers------------- ') 76 | for i in range(0,16): 77 | stage1_r.append(float(mem[i])+float(mem[i+16])) 78 | stage1_i.append(float(img[i])+float(img[i+16])) 79 | 80 | for j in range(0,16): 81 | minus_r.append(((float(mem[j])-float(mem[j+16])))) 82 | minus_i.append(((float(img[j])-float(img[j+16])))) 83 | 84 | for i in range(0,16): 85 | stage1_r.append((float(minus_r[i])*float(w[i])) - (float(minus_i[i])*float(w_i[i]))) 86 | stage1_i.append((float(minus_i[i])*float(w[i])) + (float(minus_r[i])*float(w_i[i]))) 87 | 88 | for i in range(len(stage1_r)): 89 | print(i,' : ',int(stage1_r[i]*64)) 90 | ''' 91 | with open("Output.txt", "w") as text_file: 92 | for i in ans: 93 | text_file.write(str(i*64)) 94 | text_file.write('\n') 95 | ''' 96 | 97 | #result saved in stage1_r and stage1_i 98 | 99 | stage2_r = [] 100 | stage2_i = [] 101 | minus2_r = [] 102 | minus2_i = [] 103 | for x in range(2): 104 | for i in range(0,8): 105 | stage2_r.append(float(stage1_r[i+(16*x)])+float(stage1_r[i+8+(16*x)])) 106 | stage2_i.append(float(stage1_i[i+(16*x)])+float(stage1_i[i+8+(16*x)])) 107 | 108 | for j in range(0,8): 109 | minus2_r.append(((float(stage1_r[j+(16*x)])-float(stage1_r[j+8+(16*x)])))) 110 | minus2_i.append(((float(stage1_i[j+(16*x)])-float(stage1_i[j+8+(16*x)])))) 111 | 112 | for i in range(0,8): 113 | stage2_r.append((float(minus2_r[i+(8*x)])*float(w[(i*2)])) - (float(minus2_i[i+(8*x)])*float(w_i[(i*2)]))) 114 | stage2_i.append((float(minus2_i[i+(8*x)])*float(w[(i*2)])) + (float(minus2_r[i+(8*x)])*float(w_i[(i*2)]))) 115 | 116 | print('-------------stage 2 answers------------- ') 117 | 118 | for i in range(len(stage2_r)): 119 | print(i,' : ',int(stage2_r[i]*64),int(stage2_i[i]*64),'i') 120 | 121 | stage3_r = [] 122 | stage3_i = [] 123 | minus3_r = [] 124 | minus3_i = [] 125 | 126 | for x in range(4): 127 | for i in range(0,4): 128 | stage3_r.append(float(stage2_r[i+(8*x)])+float(stage2_r[i+4+(8*x)])) 129 | stage3_i.append(float(stage2_i[i+(8*x)])+float(stage2_i[i+4+(8*x)])) 130 | 131 | for j in range(0,4): 132 | minus3_r.append(((float(stage2_r[j+(8*x)])-float(stage2_r[j+4+(8*x)])))) 133 | minus3_i.append(((float(stage2_i[j+(8*x)])-float(stage2_i[j+4+(8*x)])))) 134 | 135 | for i in range(0,4): 136 | stage3_r.append((float(minus3_r[i+(4*x)])*float(w[(i*4)])) - (float(minus3_i[i+(4*x)])*float(w_i[(i*4)]))) 137 | stage3_i.append((float(minus3_i[i+(4*x)])*float(w[(i*4)])) + (float(minus3_r[i+(4*x)])*float(w_i[(i*4)]))) 138 | print('-------------stage 3 answers------------- ') 139 | 140 | for i in range(len(stage3_r)): 141 | print(i,' : ',int(stage3_r[i]*64),int(stage3_i[i]*64),'i') 142 | 143 | stage4_r = [] 144 | stage4_i = [] 145 | minus4_r = [] 146 | minus4_i = [] 147 | 148 | for x in range(8): 149 | for i in range(0,2): 150 | stage4_r.append(float(stage3_r[i+(4*x)])+float(stage3_r[i+2+(4*x)])) 151 | stage4_i.append(float(stage3_i[i+(4*x)])+float(stage3_i[i+2+(4*x)])) 152 | 153 | for j in range(0,2): 154 | minus4_r.append(((float(stage3_r[j+(4*x)])-float(stage3_r[j+2+(4*x)])))) 155 | minus4_i.append(((float(stage3_i[j+(4*x)])-float(stage3_i[j+2+(4*x)])))) 156 | 157 | for i in range(0,2): 158 | stage4_r.append((float(minus4_r[i+(2*x)])*float(w[(i*8)])) - (float(minus4_i[i+(2*x)])*float(w_i[(i*8)]))) 159 | stage4_i.append((float(minus4_i[i+(2*x)])*float(w[(i*8)])) + (float(minus4_r[i+(2*x)])*float(w_i[(i*8)]))) 160 | print('-------------stage 4 answers------------- ') 161 | 162 | for i in range(len(stage4_r)): 163 | print(i,' : ',int(stage4_r[i]*64),int(stage4_i[i]*64),'i') 164 | 165 | stage5_r = [] 166 | stage5_i = [] 167 | minus5_r = [] 168 | minus5_i = [] 169 | final_ans_r = [0 for i in range(32)] 170 | final_ans_i = [0 for i in range(32)] 171 | for x in range(16): 172 | for i in range(0,1): 173 | stage5_r.append(float(stage4_r[i+(2*x)])+float(stage4_r[i+1+(2*x)])) 174 | stage5_i.append(float(stage4_i[i+(2*x)])+float(stage4_i[i+1+(2*x)])) 175 | 176 | for j in range(0,1): 177 | minus5_r.append(((float(stage4_r[j+(2*x)])-float(stage4_r[j+1+(2*x)])))) 178 | minus5_i.append(((float(stage4_i[j+(2*x)])-float(stage4_i[j+1+(2*x)])))) 179 | 180 | for i in range(0,1): 181 | stage5_r.append((float(minus5_r[i+(x)])*float(w[(i*16)])) - (float(minus5_i[i+(x)])*float(w_i[(i*16)]))) 182 | stage5_i.append((float(minus5_i[i+(x)])*float(w[(i*16)])) + (float(minus5_r[i+(x)])*float(w_i[(i*16)]))) 183 | 184 | print('-------------stage 5 answers------------- ') 185 | 186 | for i in range(len(stage5_r)): 187 | print(i,' : ',int(stage5_r[i]*64),int(stage5_i[i]*64),'i') 188 | 189 | print('-------------final answers------------- ') 190 | for i in range(len(stage5_r)): 191 | r = int('{:05b}'.format(i)[::-1], 2) 192 | final_ans_r[r] = stage5_r[i] 193 | final_ans_i[r] = stage5_i[i] 194 | 195 | for i in range(len(stage5_r)): 196 | print(i,' : ',int(final_ans_r[i]),int(final_ans_i[i]),'i') 197 | -------------------------------------------------------------------------------- /SIM/FFT_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/10ps 3 | 4 | module TESTBED; 5 | 6 | integer i, j, latency, latency_total; 7 | integer fp_r, fp_i, int_r, int_i; 8 | integer SNR_ratio; 9 | 10 | parameter FFT_size = 32; 11 | parameter dataset = 5; 12 | parameter IN_width = 12; 13 | parameter OUT_width = 16; 14 | parameter latency_limit = 68; 15 | 16 | parameter cycle = 10.0; 17 | 18 | reg clk, rst_n, in_valid; 19 | wire out_valid; 20 | reg signed [IN_width-1:0] din_r, din_i; 21 | wire signed [OUT_width-1:0] dout_r, dout_i; 22 | reg signed [OUT_width:0] gold_r, gold_i; 23 | 24 | reg signed [31:0] noise, signal; 25 | reg [31:0] noise_energy, signal_energy; 26 | 27 | always #(cycle/2.0) clk = ~clk; 28 | 29 | initial begin 30 | 31 | `ifdef RTL 32 | $fsdbDumpfile("FFT_RTL.fsdb"); 33 | $fsdbDumpvars(0, FFT_CORE); 34 | `elsif GATE 35 | $sdf_annotate("FFT_SYN.sdf",FFT_CORE); 36 | 37 | `ifdef VCD 38 | $dumpfile("FFT_GATE.vcd"); 39 | $dumpvars(); 40 | `elsif FSDB 41 | $fsdbDumpfile("FFT_GATE.fsdb"); 42 | $fsdbDumpvars(0, FFT_CORE); 43 | `endif 44 | `endif 45 | end 46 | 47 | initial begin 48 | 49 | clk = 0; 50 | rst_n = 1; 51 | in_valid = 0; 52 | signal_energy = 0; 53 | noise_energy = 0; 54 | latency = 0; 55 | latency_total = 0; 56 | 57 | for(i=0;i latency_limit) begin 113 | $display("Latency too long (> %0d cycles)", latency_limit); 114 | $finish; 115 | end 116 | end 117 | 118 | // Read golden data 119 | case(i) 120 | 0: begin 121 | fp_r = $fopen("../Test_pattern/output/OUT_real_16_pattern01.txt", "r"); 122 | fp_i = $fopen("../Test_pattern/output/OUT_imag_16_pattern01.txt", "r"); 123 | end 124 | 1: begin 125 | fp_r = $fopen("../Test_pattern/output/OUT_real_16_pattern02.txt", "r"); 126 | fp_i = $fopen("../Test_pattern/output/OUT_imag_16_pattern02.txt", "r"); 127 | end 128 | 2: begin 129 | fp_r = $fopen("../Test_pattern/output/OUT_real_16_pattern03.txt", "r"); 130 | fp_i = $fopen("../Test_pattern/output/OUT_imag_16_pattern03.txt", "r"); 131 | end 132 | 3: begin 133 | fp_r = $fopen("../Test_pattern/output/OUT_real_16_pattern04.txt", "r"); 134 | fp_i = $fopen("../Test_pattern/output/OUT_imag_16_pattern04.txt", "r"); 135 | end 136 | 4: begin 137 | fp_r = $fopen("../Test_pattern/output/OUT_real_16_pattern05.txt", "r"); 138 | fp_i = $fopen("../Test_pattern/output/OUT_imag_16_pattern05.txt", "r"); 139 | end 140 | default: begin 141 | $display("Wrong dataset!? No Way!"); 142 | $finish; 143 | end 144 | endcase 145 | 146 | for(j=0;j latency_limit) begin 151 | $display("Total latency too long (> %0d cycles)", latency_limit); 152 | $finish; 153 | end 154 | end 155 | 156 | int_r = $fscanf(fp_r, "%d", gold_r); 157 | int_i = $fscanf(fp_i, "%d", gold_i); 158 | 159 | signal = gold_r; 160 | signal_energy = signal_energy + signal*signal; 161 | signal = gold_i; 162 | signal_energy = signal_energy + signal*signal; 163 | 164 | 165 | noise = gold_r - dout_r; 166 | noise_energy = noise_energy + noise*noise; 167 | noise = gold_i - dout_i; 168 | noise_energy = noise_energy + noise*noise; 169 | @(negedge clk); 170 | end 171 | 172 | if(noise_energy == 0) begin 173 | $display(" ---------- SNR = infinity"); 174 | $display(" ---------- dataset %2d pass!!\n", i+1); 175 | end 176 | else begin 177 | 178 | SNR_ratio = signal_energy/noise_energy; 179 | $display(" ---------- SNR = %2.2f", $log10(SNR_ratio)*10.0); 180 | 181 | if(SNR_ratio >= 10000) $display(" ---------- dataset %2d passed!!\n", i+1); 182 | else begin 183 | $display(" ---------- dataset %2d failed!! Bye\n", i+1); 184 | $finish; 185 | end 186 | end 187 | 188 | $fclose(fp_r); 189 | $fclose(fp_i); 190 | 191 | latency_total = latency_total + latency; 192 | 193 | end 194 | 195 | $display("\033[1;33m********************************\033[m"); 196 | $display("\033[1;33mWell Done \033[m"); 197 | $display("\033[1;33m********************************\033[m"); 198 | $display("\033[1;35m ▒~▒▒ \033[m"); 199 | $display("\033[1;35m ▒x▒x \033[m"); 200 | $display("\033[1;35m▒i▒X▒X▒}▒▒▒X▒▒ \033[m"); 201 | $display("\033[1;35m▒i ▒X▒X▒▒ \033[m"); 202 | $display("\033[1;35m▒i ▒@ ▒X▒X▒▒ You have passed all patterns!!\033[m"); 203 | $display("\033[1;35m▒i▒š▒ ▒X▒X▒▒ \033[m"); 204 | $display("\033[1;35m▒i ▒▒▒X▒X▒▒ \033[m"); 205 | $display("\033[1;35m \033[m"); 206 | $display("\033[1;32m********************************\033[m"); 207 | $display("\033[1;32m********************************\033[m"); 208 | $display("Clk period = %2.2f ns", cycle); 209 | $display("Average latency = %2.2f cycles", latency_total/dataset); 210 | $display("Bye\n\n"); 211 | 212 | $finish; 213 | 214 | 215 | end 216 | 217 | FFT FFT_CORE( 218 | .clk(clk), 219 | .rst_n(rst_n), 220 | .in_valid(in_valid), 221 | .din_r(din_r), 222 | .din_i(din_i), 223 | .out_valid(out_valid), 224 | .dout_r(dout_r), 225 | .dout_i(dout_i) 226 | ); 227 | 228 | endmodule 229 | 230 | -------------------------------------------------------------------------------- /SIM/FFT_test.c: -------------------------------------------------------------------------------- 1 | #include "fft.h" 2 | 3 | #include 4 | 5 | #include 6 | #include 7 | 8 | 9 | 10 | /* ===== In-Place FFT ======================================================= */ 11 | 12 | 13 | 14 | void ffti_f(complex_f data[], unsigned log2_N, fft_dir direction) 15 | { 16 | ffti_shuffle_f(data, log2_N); 17 | ffti_evaluate_f(data, log2_N, direction); 18 | } 19 | 20 | 21 | 22 | void ffti_copy_shuffle_f(complex_f src[], complex_f dst[], unsigned log2_N) 23 | { 24 | /* 25 | * Basic Bit-Reversal Scheme: 26 | * 27 | * The incrementing pattern operations used here correspond 28 | * to the logic operations of a synchronous counter. 29 | * 30 | * Incrementing a binary number simply flips a sequence of 31 | * least-significant bits, for example from 0111 to 1000. 32 | * So in order to compute the next bit-reversed index, we 33 | * have to flip a sequence of most-significant bits. 34 | */ 35 | 36 | unsigned N = 1 << log2_N; /* N */ 37 | unsigned Nd2 = N >> 1; /* N/2 = number range midpoint */ 38 | unsigned Nm1 = N - 1; /* N-1 = digit mask */ 39 | unsigned i; /* index for source element */ 40 | unsigned j; /* index for next destination element */ 41 | 42 | for (i = 0, j = 0; i < N; i++) { 43 | dst[j] = src[i]; 44 | 45 | /* 46 | * Find least significant zero bit 47 | */ 48 | 49 | unsigned lszb = ~i & (i + 1); 50 | 51 | /* 52 | * Use division to bit-reverse the single bit so that we now have 53 | * the most significant zero bit 54 | * 55 | * N = 2^r = 2^(m+1) 56 | * Nd2 = N/2 = 2^m 57 | * if lszb = 2^k, where k is within the range of 0...m, then 58 | * mszb = Nd2 / lszb 59 | * = 2^m / 2^k 60 | * = 2^(m-k) 61 | * = bit-reversed value of lszb 62 | */ 63 | 64 | unsigned mszb = Nd2 / lszb; 65 | 66 | /* 67 | * Toggle bits with bit-reverse mask 68 | */ 69 | 70 | unsigned bits = Nm1 & ~(mszb - 1); 71 | j ^= bits; 72 | } 73 | } 74 | 75 | 76 | 77 | void ffti_shuffle_f(complex_f data[], unsigned log2_N) 78 | { 79 | /* 80 | * Basic Bit-Reversal Scheme: 81 | * 82 | * The incrementing pattern operations used here correspond 83 | * to the logic operations of a synchronous counter. 84 | * 85 | * Incrementing a binary number simply flips a sequence of 86 | * least-significant bits, for example from 0111 to 1000. 87 | * So in order to compute the next bit-reversed index, we 88 | * have to flip a sequence of most-significant bits. 89 | */ 90 | 91 | unsigned N = 1 << log2_N; /* N */ 92 | unsigned Nd2 = N >> 1; /* N/2 = number range midpoint */ 93 | unsigned Nm1 = N - 1; /* N-1 = digit mask */ 94 | unsigned i; /* index for array elements */ 95 | unsigned j; /* index for next element swap location */ 96 | 97 | for (i = 0, j = 0; i < N; i++) { 98 | if (j > i) { 99 | complex_f tmp = data[i]; 100 | data[i] = data[j]; 101 | data[j] = tmp; 102 | } 103 | 104 | /* 105 | * Find least significant zero bit 106 | */ 107 | 108 | unsigned lszb = ~i & (i + 1); 109 | 110 | /* 111 | * Use division to bit-reverse the single bit so that we now have 112 | * the most significant zero bit 113 | * 114 | * N = 2^r = 2^(m+1) 115 | * Nd2 = N/2 = 2^m 116 | * if lszb = 2^k, where k is within the range of 0...m, then 117 | * mszb = Nd2 / lszb 118 | * = 2^m / 2^k 119 | * = 2^(m-k) 120 | * = bit-reversed value of lszb 121 | */ 122 | 123 | unsigned mszb = Nd2 / lszb; 124 | 125 | /* 126 | * Toggle bits with bit-reverse mask 127 | */ 128 | 129 | unsigned bits = Nm1 & ~(mszb - 1); 130 | j ^= bits; 131 | } 132 | } 133 | 134 | 135 | 136 | void ffti_evaluate_f(complex_f data[], unsigned log2_N, fft_dir direction) 137 | { 138 | /* 139 | * In-place FFT butterfly algorithm 140 | * 141 | * input: 142 | * A[] = array of N shuffled complex values where N is a power of 2 143 | * output: 144 | * A[] = the DFT of input A[] 145 | * 146 | * for r = 1 to log2(N) 147 | * m = 2^r 148 | * Wm = exp(−j2π/m) 149 | * for n = 0 to N-1 by m 150 | * Wmk = 1 151 | * for k = 0 to m/2 - 1 152 | * u = A[n + k] 153 | * t = Wmk * A[n + k + m/2] 154 | * A[n + k] = u + t 155 | * A[n + k + m/2] = u - t 156 | * Wmk = Wmk * Wm 157 | * 158 | * For inverse FFT, use Wm = exp(+j2π/m) 159 | */ 160 | 161 | unsigned N; 162 | unsigned r; 163 | unsigned m, md2; 164 | unsigned n, k; 165 | unsigned i_e, i_o; 166 | double theta_2pi; 167 | double theta; /* Use double for precision */ 168 | complex_d Wm, Wmk; /* Use double for precision */ 169 | complex_d u, t; /* Use double for precision */ 170 | 171 | N = 1 << log2_N; 172 | theta_2pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 173 | theta_2pi *= 2; 174 | 175 | for (r = 1; r <= log2_N; r++) 176 | { 177 | m = 1 << r; 178 | md2 = m >> 1; 179 | theta = theta_2pi / m; 180 | Wm.re = cos(theta); 181 | Wm.im = sin(theta); 182 | for (n = 0; n < N; n += m) 183 | { 184 | Wmk.re = 1.f; 185 | Wmk.im = 0.f; 186 | for (k = 0; k < md2; k++) 187 | { 188 | i_e = n + k; 189 | i_o = i_e + md2; 190 | u.re = data[i_e].re; 191 | u.im = data[i_e].im; 192 | t.re = complex_mul_re(Wmk.re, Wmk.im, data[i_o].re, data[i_o].im); 193 | t.im = complex_mul_im(Wmk.re, Wmk.im, data[i_o].re, data[i_o].im); 194 | data[i_e].re = u.re + t.re; 195 | data[i_e].im = u.im + t.im; 196 | data[i_o].re = u.re - t.re; 197 | data[i_o].im = u.im - t.im; 198 | t.re = complex_mul_re(Wmk.re, Wmk.im, Wm.re, Wm.im); 199 | t.im = complex_mul_im(Wmk.re, Wmk.im, Wm.re, Wm.im); 200 | Wmk = t; 201 | } 202 | } 203 | } 204 | } 205 | 206 | 207 | 208 | /* ===== Recursive FFT ====================================================== */ 209 | 210 | 211 | 212 | void fftr_f(complex_f data[], unsigned log2_N, fft_dir direction) 213 | { 214 | /* 215 | * fft(A[], N): 216 | * if N == 1 217 | * return 218 | * for k = 0 to N/2-1 219 | * e[k] = A[2*k] 220 | * o[k] = A[2*k+1] 221 | * fft(e, N/2) 222 | * fft(o, N/2); 223 | * WN = exp(−j2π/N) 224 | * WNk = 1 225 | * for k = 0 to N/2-1 226 | * A[k] = e[k] + WNk * o[k] 227 | * A[k+N/2] = e[k] - WNk * o[k] 228 | * WNk = WNk * WN 229 | * 230 | * For inverse FFT, use Wm = exp(+j2π/N) 231 | */ 232 | 233 | if (log2_N > 0) 234 | { 235 | unsigned log2_Nd2; 236 | unsigned Nd2; 237 | unsigned k; 238 | unsigned kpNd2; 239 | complex_f *evn, *odd; 240 | double theta_pi; 241 | double theta; /* Use double for precision */ 242 | complex_d WN, WNk; /* Use double for precision */ 243 | complex_d u, t; /* Use double for precision */ 244 | 245 | log2_Nd2 = log2_N - 1; 246 | Nd2 = 1 << log2_Nd2; 247 | 248 | evn = malloc(Nd2 * sizeof(complex_f)); 249 | odd = malloc(Nd2 * sizeof(complex_f)); 250 | 251 | for (k = 0; k < Nd2; k++) 252 | { 253 | evn[k] = data[2*k]; 254 | odd[k] = data[2*k+1]; 255 | } 256 | 257 | fftr_f(evn, log2_Nd2, direction); 258 | fftr_f(odd, log2_Nd2, direction); 259 | 260 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 261 | theta = theta_pi / Nd2; /* - (2 * M_PI) / N */ 262 | WN.re = cos(theta); 263 | WN.im = sin(theta); 264 | 265 | WNk.re = 1.f; 266 | WNk.im = 0.f; 267 | for (k = 0; k < Nd2; k++) 268 | { 269 | kpNd2 = k + Nd2; 270 | 271 | u.re = evn[k].re; 272 | u.im = evn[k].im; 273 | t.re = complex_mul_re(WNk.re, WNk.im, odd[k].re, odd[k].im); 274 | t.im = complex_mul_im(WNk.re, WNk.im, odd[k].re, odd[k].im); 275 | data[k].re = u.re + t.re; 276 | data[k].im = u.im + t.im; 277 | data[kpNd2].re = u.re - t.re; 278 | data[kpNd2].im = u.im - t.im; 279 | 280 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 281 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 282 | WNk = t; 283 | } 284 | 285 | free(evn); 286 | free(odd); 287 | } 288 | } 289 | 290 | 291 | 292 | /* ===== Recursive FFT, user-supplied scratchpad buffer ===================== */ 293 | 294 | 295 | 296 | #if 0 297 | 298 | 299 | 300 | /* 301 | * A more efficient version of the fftr_f() implementation, where a 302 | * user-supplied buffer is used to hold the even/odd decompositions 303 | */ 304 | 305 | void fftrb_f(complex_f data[], unsigned log2_N, fft_dir direction, complex_f scratch[]) 306 | { 307 | /* 308 | * fft(A[], N): 309 | * if N == 1 310 | * return 311 | * for k = 0 to N/2-1 312 | * e[k] = A[2*k] 313 | * o[k] = A[2*k+1] 314 | * fft(e, N/2) 315 | * fft(o, N/2); 316 | * WN = exp(−j2π/N) 317 | * WNk = 1 318 | * for k = 0 to N/2-1 319 | * A[k] = e[k] + WNk * o[k] 320 | * A[k+N/2] = e[k] - WNk * o[k] 321 | * WNk = WNk * WN 322 | * 323 | * For inverse FFT, use Wm = exp(+j2π/N) 324 | */ 325 | 326 | if (log2_N > 0) 327 | { 328 | unsigned log2_Nd2; 329 | unsigned Nd2; 330 | unsigned k; 331 | unsigned kpNd2; 332 | complex_f *evn, *odd; 333 | double theta_pi; 334 | double theta; /* Use double for precision */ 335 | complex_d WN, WNk; /* Use double for precision */ 336 | complex_d u, t; /* Use double for precision */ 337 | 338 | log2_Nd2 = log2_N - 1; 339 | Nd2 = 1 << log2_Nd2; 340 | 341 | evn = scratch; 342 | odd = scratch + Nd2; 343 | 344 | for (k = 0; k < Nd2; k++) 345 | { 346 | evn[k] = data[2*k]; 347 | odd[k] = data[2*k+1]; 348 | } 349 | 350 | fftr_f(evn, log2_Nd2, direction); 351 | fftr_f(odd, log2_Nd2, direction); 352 | 353 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 354 | theta = theta_pi / Nd2; /* - (2 * M_PI) / N */ 355 | WN.re = cos(theta); 356 | WN.im = sin(theta); 357 | 358 | WNk.re = 1.f; 359 | WNk.im = 0.f; 360 | for (k = 0; k < Nd2; k++) 361 | { 362 | kpNd2 = k + Nd2; 363 | 364 | u.re = evn[k].re; 365 | u.im = evn[k].im; 366 | t.re = complex_mul_re(WNk.re, WNk.im, odd[k].re, odd[k].im); 367 | t.im = complex_mul_im(WNk.re, WNk.im, odd[k].re, odd[k].im); 368 | data[k].re = u.re + t.re; 369 | data[k].im = u.im + t.im; 370 | data[kpNd2].re = u.re - t.re; 371 | data[kpNd2].im = u.im - t.im; 372 | 373 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 374 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 375 | WNk = t; 376 | } 377 | } 378 | } 379 | 380 | 381 | 382 | #else 383 | 384 | 385 | 386 | /* 387 | * A much more efficient version of the recursive FFT algorithm, where 388 | * the data and scratch buffers are commutated throughout the recursion 389 | * sequence, and index mapping is used to locate the correct values 390 | */ 391 | 392 | void _fftrb_f(complex_f data[], complex_f scratch[], int N, double theta_pi, int stride) 393 | { 394 | if (stride < N) 395 | { 396 | unsigned stride2; 397 | unsigned k; 398 | unsigned k_e, k_o; 399 | unsigned kd2, kpNd2; 400 | double theta; /* Use double for precision */ 401 | complex_d WN, WNk; /* Use double for precision */ 402 | complex_d u, t; /* Use double for precision */ 403 | 404 | stride2 = 2 * stride; 405 | 406 | /* Notice that the order of data and scratch buffers is swapped! */ 407 | _fftrb_f(scratch , data , N, theta_pi, stride2); 408 | _fftrb_f(scratch + stride, data + stride, N, theta_pi, stride2); 409 | 410 | theta = (stride2 * theta_pi) / N; 411 | WN.re = cos(theta); 412 | WN.im = sin(theta); 413 | 414 | WNk.re = 1.f; 415 | WNk.im = 0.f; 416 | for (k = 0; k < N; k += stride2) 417 | { 418 | k_e = k; 419 | k_o = k + stride; 420 | kd2 = k >> 1; 421 | kpNd2 = (k + N) >> 1; 422 | 423 | u.re = scratch[k_e].re; 424 | u.im = scratch[k_e].im; 425 | t.re = complex_mul_re(WNk.re, WNk.im, scratch[k_o].re, scratch[k_o].im); 426 | t.im = complex_mul_im(WNk.re, WNk.im, scratch[k_o].re, scratch[k_o].im); 427 | 428 | data[kd2].re = u.re + t.re; 429 | data[kd2].im = u.im + t.im; 430 | data[kpNd2].re = u.re - t.re; 431 | data[kpNd2].im = u.im - t.im; 432 | 433 | t.re = complex_mul_re(WNk.re, WNk.im, WN.re, WN.im); 434 | t.im = complex_mul_im(WNk.re, WNk.im, WN.re, WN.im); 435 | WNk = t; 436 | } 437 | } 438 | } 439 | 440 | 441 | 442 | void fftrb_f(complex_f data[], unsigned log2_N, fft_dir direction, complex_f scratch[]) 443 | { 444 | unsigned N; 445 | unsigned k; 446 | double theta_pi; 447 | 448 | N = 1 << log2_N; 449 | for (k = 0; k < N; k++) 450 | scratch[k] = data[k]; 451 | 452 | theta_pi = (direction == FFT_FORWARD) ? -M_PI : M_PI; 453 | 454 | _fftrb_f(data, scratch, N, theta_pi, 1); 455 | } 456 | 457 | 458 | 459 | #endif 460 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_imag_pattern01.txt: -------------------------------------------------------------------------------- 1 | -1884 2 | 1674 3 | 262 4 | 1052 5 | -6 6 | 1818 7 | -36 8 | -1932 9 | -203 10 | -1591 11 | -1760 12 | 47 13 | -1397 14 | -145 15 | -24 16 | -743 17 | 116 18 | 1596 19 | -98 20 | -1501 21 | 681 22 | 1002 23 | -1492 24 | -1465 25 | 121 26 | 86 27 | 393 28 | -49 29 | -1910 30 | 621 31 | 672 32 | 2032 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_imag_pattern02.txt: -------------------------------------------------------------------------------- 1 | -1427 2 | -973 3 | 1864 4 | 1620 5 | 488 6 | -1410 7 | 1042 8 | 1644 9 | -1037 10 | 1093 11 | 865 12 | 46 13 | 1805 14 | -1718 15 | 1519 16 | 1587 17 | 1748 18 | -1915 19 | -1195 20 | -1887 21 | -1765 22 | 553 23 | 970 24 | 1382 25 | -167 26 | -1769 27 | -950 28 | -1066 29 | -1922 30 | -1630 31 | -1256 32 | -608 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_imag_pattern03.txt: -------------------------------------------------------------------------------- 1 | -970 2 | 989 3 | -117 4 | -1907 5 | 1494 6 | 482 7 | -1976 8 | 1125 9 | 1713 10 | 192 11 | -606 12 | 45 13 | 1423 14 | 805 15 | -1033 16 | 844 17 | -715 18 | -1842 19 | 1292 20 | 1822 21 | 398 22 | 616 23 | -1689 24 | -891 25 | -455 26 | -40 27 | -1782 28 | 2014 29 | 1651 30 | -298 31 | 1423 32 | 849 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_imag_pattern04.txt: -------------------------------------------------------------------------------- 1 | -229 2 | 1969 3 | 940 4 | -1111 5 | -308 6 | -1132 7 | -1181 8 | 609 9 | 1296 10 | -258 11 | -1854 12 | -1748 13 | 720 14 | 19 15 | -261 16 | -39 17 | 1637 18 | 754 19 | -1304 20 | 1373 21 | 711 22 | 904 23 | -714 24 | -2027 25 | 1449 26 | 824 27 | 1899 28 | -1055 29 | -403 30 | 113 31 | -1589 32 | -983 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_imag_pattern05.txt: -------------------------------------------------------------------------------- 1 | 1080 2 | -932 3 | 1991 4 | 755 5 | -1953 6 | 137 7 | -1979 8 | 401 9 | 655 10 | 713 11 | 732 12 | 95 13 | 1489 14 | 1233 15 | 561 16 | -950 17 | -987 18 | 1705 19 | -1129 20 | -1034 21 | -984 22 | 1646 23 | -1368 24 | 1262 25 | 924 26 | 1515 27 | 440 28 | 177 29 | -306 30 | 544 31 | -722 32 | -1629 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_real_pattern01.txt: -------------------------------------------------------------------------------- 1 | 0 2 | -1700 3 | -1605 4 | 412 5 | 1363 6 | -115 7 | -209 8 | 277 9 | 381 10 | 736 11 | -1086 12 | 42 13 | 1346 14 | 1889 15 | -978 16 | 96 17 | -227 18 | -1409 19 | 1979 20 | -477 21 | 299 22 | -751 23 | 1563 24 | -968 25 | -1552 26 | -723 27 | -484 28 | -1781 29 | 2043 30 | -527 31 | -701 32 | 1502 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_real_pattern02.txt: -------------------------------------------------------------------------------- 1 | 1536 2 | 592 3 | -1210 4 | 1962 5 | -205 6 | 638 7 | -93 8 | -475 9 | 1753 10 | -2022 11 | 709 12 | -752 13 | -949 14 | 1926 15 | 1124 16 | 592 17 | 556 18 | -1268 19 | 1717 20 | -12 21 | -1852 22 | 1560 23 | 1590 24 | 93 25 | -955 26 | -1710 27 | 1889 28 | -1212 29 | -286 30 | 912 31 | 1079 32 | -605 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_real_pattern03.txt: -------------------------------------------------------------------------------- 1 | -1024 2 | -700 3 | -1327 4 | -71 5 | -1773 6 | 1390 7 | -490 8 | -715 9 | -971 10 | -172 11 | -1081 12 | -1546 13 | 1877 14 | 1451 15 | -870 16 | 577 17 | -1733 18 | -616 19 | 1967 20 | -570 21 | 93 22 | 288 23 | 1618 24 | 1155 25 | 153 26 | 1911 27 | -858 28 | -642 29 | -1590 30 | -1745 31 | -725 32 | 1385 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_real_pattern04.txt: -------------------------------------------------------------------------------- 1 | 1536 2 | -1858 3 | 918 4 | 704 5 | -765 6 | 1766 7 | 80 8 | 701 9 | 1763 10 | 498 11 | -440 12 | -663 13 | 730 14 | 1470 15 | 182 16 | 825 17 | 706 18 | 1247 19 | 1836 20 | 1455 21 | 1065 22 | -348 23 | -160 24 | 405 25 | -1084 26 | 1161 27 | -1719 28 | 1691 29 | 1341 30 | 1279 31 | 1957 32 | -1972 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/IN_real_pattern05.txt: -------------------------------------------------------------------------------- 1 | -512 2 | -1658 3 | 1998 4 | -826 5 | 1987 6 | 1351 7 | -898 8 | 93 9 | 878 10 | -708 11 | 1507 12 | 556 13 | 17 14 | -256 15 | 511 16 | -922 17 | 917 18 | -1257 19 | -317 20 | 924 21 | 1536 22 | 679 23 | 261 24 | 1444 25 | -743 26 | 1176 27 | 1995 28 | 485 29 | 1639 30 | 523 31 | -1017 32 | -1791 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_imag_16_pattern01.txt: -------------------------------------------------------------------------------- 1 | -4063 2 | 978 3 | 9398 4 | 66 5 | 3855 6 | 3915 7 | 1432 8 | 2356 9 | -696 10 | -5620 11 | -473 12 | 2992 13 | 6622 14 | -9291 15 | -2363 16 | -14366 17 | -9067 18 | 994 19 | -11113 20 | 434 21 | -550 22 | 1611 23 | -20540 24 | -1041 25 | -4102 26 | -16518 27 | 2351 28 | -1406 29 | -6801 30 | -7538 31 | 7817 32 | 10425 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_imag_16_pattern02.txt: -------------------------------------------------------------------------------- 1 | -4469 2 | -5743 3 | -5032 4 | 612 5 | 11709 6 | -14370 7 | 2130 8 | 661 9 | -6173 10 | -9145 11 | -133 12 | 488 13 | 2129 14 | -11981 15 | -1432 16 | -5520 17 | 5633 18 | -2814 19 | 12274 20 | 5718 21 | -9498 22 | 5775 23 | 4638 24 | 6016 25 | -4099 26 | -12785 27 | 2278 28 | -7302 29 | -2298 30 | 3994 31 | -2526 32 | -4413 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_imag_16_pattern03.txt: -------------------------------------------------------------------------------- 1 | 4856 2 | 6515 3 | -1466 4 | -5354 5 | -1847 6 | 12165 7 | -5771 8 | 9831 9 | 6793 10 | -3152 11 | 261 12 | -13230 13 | -183 14 | -6432 15 | 3353 16 | -671 17 | -4754 18 | 2585 19 | 2788 20 | 6534 21 | -7276 22 | -8970 23 | -22322 24 | -2329 25 | 11261 26 | -3257 27 | -5489 28 | -1740 29 | -12268 30 | 7495 31 | 5098 32 | -4076 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_imag_16_pattern04.txt: -------------------------------------------------------------------------------- 1 | -979 2 | -3583 3 | 2132 4 | 5010 5 | 7284 6 | 6488 7 | -7004 8 | -8221 9 | 6868 10 | -2952 11 | 4722 12 | -1153 13 | -574 14 | -10161 15 | -4939 16 | 2889 17 | 2597 18 | -1960 19 | -5589 20 | 4200 21 | 2509 22 | -4828 23 | -2508 24 | -1252 25 | 11006 26 | -9514 27 | 469 28 | 8827 29 | 4511 30 | -11198 31 | 2017 32 | -2457 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_imag_16_pattern05.txt: -------------------------------------------------------------------------------- 1 | 4082 2 | 1448 3 | -6505 4 | 1673 5 | -2221 6 | -4764 7 | -2426 8 | -6388 9 | 1505 10 | -3303 11 | -5589 12 | 14992 13 | 12507 14 | 8215 15 | 5421 16 | 9216 17 | -7194 18 | -5 19 | 6626 20 | 5980 21 | -3580 22 | -3528 23 | 1880 24 | 5597 25 | 1279 26 | -864 27 | -7946 28 | 3235 29 | 6996 30 | 6365 31 | -3353 32 | -4805 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_real_16_pattern01.txt: -------------------------------------------------------------------------------- 1 | -1365 2 | -5006 3 | 6210 4 | 3677 5 | -7306 6 | -3351 7 | -7292 8 | 1732 9 | 12794 10 | 1805 11 | 9432 12 | -6277 13 | -5414 14 | -1654 15 | -2289 16 | -812 17 | 5629 18 | -1496 19 | 1189 20 | -5769 21 | -6239 22 | 1193 23 | 1843 24 | 7566 25 | -2446 26 | 8795 27 | 2872 28 | 5098 29 | -6839 30 | -1067 31 | -4415 32 | -811 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_real_16_pattern02.txt: -------------------------------------------------------------------------------- 1 | 6622 2 | 12508 3 | 8765 4 | 12634 5 | -5746 6 | 4378 7 | 912 8 | 4018 9 | -17694 10 | 5387 11 | 846 12 | 7351 13 | 11531 14 | -10622 15 | -2269 16 | -3423 17 | 6184 18 | 1510 19 | -6917 20 | 4246 21 | 14727 22 | -5202 23 | 9493 24 | 8319 25 | 3280 26 | 4480 27 | -2160 28 | -6452 29 | 4214 30 | -11564 31 | 1677 32 | -11897 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_real_16_pattern03.txt: -------------------------------------------------------------------------------- 1 | -5354 2 | -5397 3 | -7528 4 | -4692 5 | 1301 6 | 10351 7 | -2880 8 | 3575 9 | -6199 10 | 4257 11 | -4160 12 | 7833 13 | -8861 14 | 8154 15 | -1310 16 | -8892 17 | -8114 18 | -3741 19 | 385 20 | 3793 21 | -1542 22 | -7179 23 | 873 24 | -9318 25 | -205 26 | 3758 27 | -1184 28 | 4767 29 | 372 30 | 12808 31 | 287 32 | -8742 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_real_16_pattern04.txt: -------------------------------------------------------------------------------- 1 | 16307 2 | -7908 3 | 6307 4 | -4671 5 | 1810 6 | 9238 7 | -7301 8 | 1709 9 | 10812 10 | 2321 11 | 1524 12 | 1233 13 | 3934 14 | 4323 15 | 13250 16 | 5119 17 | -415 18 | 3409 19 | 6434 20 | 20913 21 | 6141 22 | 946 23 | -474 24 | -7467 25 | -5536 26 | 1730 27 | -7671 28 | -9803 29 | -9687 30 | -8647 31 | 431 32 | 827 33 | -------------------------------------------------------------------------------- /SIM/Test_cases/OUT_real_16_pattern05.txt: -------------------------------------------------------------------------------- 1 | 9572 2 | -1362 3 | -15042 4 | 3732 5 | -3841 6 | -180 7 | 5475 8 | -3630 9 | 9163 10 | -6318 11 | 3021 12 | -8469 13 | -4943 14 | -2850 15 | 14317 16 | -1543 17 | 9946 18 | 5786 19 | 7 20 | 2406 21 | 5646 22 | -779 23 | 750 24 | 4913 25 | -5805 26 | 3300 27 | -3388 28 | -5838 29 | -15420 30 | -11184 31 | -2984 32 | -855 33 | -------------------------------------------------------------------------------- /SIM/pre_Synthesis.cr.mti: -------------------------------------------------------------------------------- 1 | C:/Users/Abdelazeem/Downloads/Compressed/Test/src/radix2.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/radix2.v 2 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 3 | Start time: 01:36:14 on Apr 23,2022 4 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/radix2.v 5 | -- Compiling module radix2 6 | 7 | Top level modules: 8 | radix2 9 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 10 | Errors: 0, Warnings: 0 11 | 12 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/TESTBED.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/TESTBED.v 13 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 14 | Start time: 01:36:15 on Apr 23,2022 15 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/TESTBED.v 16 | -- Compiling module TESTBED 17 | 18 | Top level modules: 19 | TESTBED 20 | End time: 01:36:15 on Apr 23,2022, Elapsed time: 0:00:00 21 | Errors: 0, Warnings: 0 22 | 23 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_16.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_16.v 24 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 25 | Start time: 01:36:15 on Apr 23,2022 26 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_16.v 27 | -- Compiling module shift_16 28 | 29 | Top level modules: 30 | shift_16 31 | End time: 01:36:15 on Apr 23,2022, Elapsed time: 0:00:00 32 | Errors: 0, Warnings: 0 33 | 34 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_8.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_8.v 35 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 36 | Start time: 01:36:15 on Apr 23,2022 37 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_8.v 38 | -- Compiling module shift_8 39 | 40 | Top level modules: 41 | shift_8 42 | End time: 01:36:15 on Apr 23,2022, Elapsed time: 0:00:00 43 | Errors: 0, Warnings: 0 44 | 45 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_2.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_2.v 46 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 47 | Start time: 01:36:14 on Apr 23,2022 48 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_2.v 49 | -- Compiling module ROM_2 50 | 51 | Top level modules: 52 | ROM_2 53 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 54 | Errors: 0, Warnings: 0 55 | 56 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/FFT.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/FFT.v 57 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 58 | Start time: 01:36:14 on Apr 23,2022 59 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/FFT.v 60 | -- Compiling module shift_16 61 | -- Compiling module shift_8 62 | -- Compiling module shift_4 63 | -- Compiling module shift_2 64 | -- Compiling module shift_1 65 | -- Compiling module radix2 66 | -- Compiling module ROM_16 67 | -- Compiling module ROM_8 68 | -- Compiling module ROM_4 69 | -- Compiling module ROM_2 70 | -- Compiling module FFT 71 | 72 | Top level modules: 73 | FFT 74 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 75 | Errors: 0, Warnings: 0 76 | 77 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_4.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_4.v 78 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 79 | Start time: 01:36:14 on Apr 23,2022 80 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_4.v 81 | -- Compiling module ROM_4 82 | 83 | Top level modules: 84 | ROM_4 85 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 86 | Errors: 0, Warnings: 0 87 | 88 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_16.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_16.v 89 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 90 | Start time: 01:36:14 on Apr 23,2022 91 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_16.v 92 | -- Compiling module ROM_16 93 | 94 | Top level modules: 95 | ROM_16 96 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 97 | Errors: 0, Warnings: 0 98 | 99 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_8.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_8.v 100 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 101 | Start time: 01:36:14 on Apr 23,2022 102 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/ROM_8.v 103 | -- Compiling module ROM_8 104 | 105 | Top level modules: 106 | ROM_8 107 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 108 | Errors: 0, Warnings: 0 109 | 110 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_1.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_1.v 111 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 112 | Start time: 01:36:14 on Apr 23,2022 113 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_1.v 114 | -- Compiling module shift_1 115 | 116 | Top level modules: 117 | shift_1 118 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 119 | Errors: 0, Warnings: 0 120 | 121 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_2.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_2.v 122 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 123 | Start time: 01:36:14 on Apr 23,2022 124 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_2.v 125 | -- Compiling module shift_2 126 | 127 | Top level modules: 128 | shift_2 129 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 130 | Errors: 0, Warnings: 0 131 | 132 | } {} {}} C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_4.v {1 {vlog -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_4.v 133 | QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018 134 | Start time: 01:36:14 on Apr 23,2022 135 | vlog -reportprogress 300 -work work -vopt C:/Users/Abdelazeem/Downloads/Compressed/Test/src/shift_4.v 136 | -- Compiling module shift_4 137 | 138 | Top level modules: 139 | shift_4 140 | End time: 01:36:14 on Apr 23,2022, Elapsed time: 0:00:00 141 | Errors: 0, Warnings: 0 142 | 143 | } {} {}} 144 | -------------------------------------------------------------------------------- /SIM/twiddle_gen.py: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------- 2 | # >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 3 | # -------------------------------------------------------------------- 4 | # Author: Ahmed Abdelazeem 5 | # Github: https://github.com/abdelazeem201 6 | # Email: ahmed_abdelazeem@outlook.com 7 | # Description: twiddle_gen.py 8 | # Dependencies: 9 | # Since: 2021-12-2 10:10:59 10 | # LastEditors: ahmed abdelazeem 11 | # LastEditTime: 2021-12-2 10:10:59 12 | 13 | # This code generates a 16-point complex twiddle factor sequence, representing the real and imaginary parts, and then saves them into separate text files. 14 | 15 | # Here's a quick breakdown of the code: 16 | 17 | # It initializes arrays for real and imaginary components, each with 16 elements. 18 | # Calculates the values for the real and imaginary components of the twiddle factors using trigonometric functions (math.cos and math.sin). 19 | # Rounds the values and scales them by 256, likely for fixed-point representation. 20 | # Converts these rounded values into binary strings of length 22, assuming they represent fixed-point numbers with 22 bits (including sign bit). 21 | # Writes these binary strings into text files for the twiddle factors' real and imaginary parts. 22 | # However, there might be an issue in the code: 23 | 24 | # The assignment of bin_real[i] and bin_img[i] seems incorrect because it assigns r[i] and im[i] directly if the condition fails. It should convert the integers r[i] and im[i] to binary strings. You might want to replace bin_real[i] = r[i] and bin_img[i] = im[i] with bin_real[i] = format(r[i],'b').zfill(22) and bin_img[i] = format(im[i],'b').zfill(22) respectively. 25 | # After this correction, the code should properly write the binary representations of the twiddle factors into the specified text files. 26 | 27 | # ******************************************************************** 28 | # Module Function 29 | def twos_comp(val, bits): 30 | """compute the 2's complement of int value val""" 31 | if (val & (1 << (bits - 1))) != 0: # if sign bit is set e.g., 8bit: 128-255 32 | val = val - (1 << bits) # compute negative value 33 | return val 34 | 35 | import math 36 | real = [0 for _ in range(16)] 37 | img = [0 for _ in range(16)] 38 | r = [0 for _ in range(16)] 39 | im = [0 for _ in range(16)] 40 | for i in range(16): 41 | real[i] = math.cos(math.pi / 16 * i) 42 | img[i] = math.sin(math.pi / 16 * i) * (-1) 43 | 44 | for i in range(16): 45 | r[i] = round(real[i] * 256) 46 | im[i] = round(img[i] * 256) 47 | print(r) 48 | print(im) 49 | 50 | bin_real = [0 for _ in range(16)] 51 | bin_img = [0 for _ in range(16)] 52 | 53 | for i in range(16): 54 | bin_real[i] = format(r[i], '022b') # Convert to binary with padding of 22 bits 55 | bin_img[i] = format(im[i], '022b') # Convert to binary with padding of 22 bits 56 | 57 | with open("twiddle_r.txt", "w") as text_file: 58 | for i in bin_real: 59 | text_file.write(str(i)) 60 | text_file.write('\n') 61 | 62 | with open("twiddle_i.txt", "w") as text_file: 63 | for i in bin_img: 64 | text_file.write(str(i)) 65 | text_file.write('\n') 66 | -------------------------------------------------------------------------------- /SIM/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor/89ce7665eca8b77a0c48e610dab11928108566b6/SIM/vsim.wlf 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2 | set_input_delay -max 5 -clock [get_clocks clk] [remove_from_collection [all_inputs] [get_ports clk]] 3 | set_output_delay -max 5 -clock [get_clocks clk] [all_outputs] 4 | set_clock_uncertainty 0.1 [get_clocks clk] 5 | set_clock_latency 0.5 [get_clocks clk] 6 | set_false_path -hold -from [remove_from_collection [all_inputs] [get_ports clk]] 7 | set_false_path -hold -to [all_outputs] 8 | set_fix_hold [get_clocks clk] 9 | set_dont_touch_network [get_ports clk] 10 | set_drive 1 [all_inputs] 11 | set_load 1 [all_outputs] 12 | 13 | group_path -name INREG -from [all_inputs] 14 | group_path -name REGOUT -to [all_outputs] 15 | group_path -name INOUT -from [all_inputs] -to [all_outputs] 16 | 17 | set_fix_multiple_port_nets -all -buffer_constants 18 | 19 | set_operating_conditions -min_library fsc0h_d_generic_core_ff1p32vm40c -min BCCOM -max_library fsc0h_d_generic_core_ss1p08v125c -max WCCOM 20 | set_wire_load_model -name G5K -library fsc0h_d_generic_core_ss1p08v125c 21 | 22 | set_max_area 0 23 | set_boundary_optimization {"*"} 24 | 25 | -------------------------------------------------------------------------------- /SYN/default.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor/89ce7665eca8b77a0c48e610dab11928108566b6/SYN/default.svf -------------------------------------------------------------------------------- /SYN/output/FFT.ddc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor/89ce7665eca8b77a0c48e610dab11928108566b6/SYN/output/FFT.ddc -------------------------------------------------------------------------------- /SYN/output/FFT.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Sat Jan 1 11:36:54 2022 4 | 5 | ################################################################### 6 | set sdc_version 2.0 7 | 8 | set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA 9 | set_operating_conditions -max WCCOM -max_library \ 10 | fsc0h_d_generic_core_ss1p08v125c\ 11 | -min BCCOM -min_library \ 12 | fsc0h_d_generic_core_ff1p32vm40c 13 | set_wire_load_model -name G5K -library fsc0h_d_generic_core_ss1p08v125c 14 | set_max_area 0 15 | set_load -pin_load 1 [get_ports out_valid] 16 | set_load -pin_load 1 [get_ports {dout_r[15]}] 17 | set_load -pin_load 1 [get_ports {dout_r[14]}] 18 | set_load -pin_load 1 [get_ports {dout_r[13]}] 19 | set_load -pin_load 1 [get_ports {dout_r[12]}] 20 | set_load -pin_load 1 [get_ports {dout_r[11]}] 21 | set_load -pin_load 1 [get_ports {dout_r[10]}] 22 | set_load -pin_load 1 [get_ports {dout_r[9]}] 23 | set_load -pin_load 1 [get_ports {dout_r[8]}] 24 | set_load -pin_load 1 [get_ports {dout_r[7]}] 25 | set_load -pin_load 1 [get_ports {dout_r[6]}] 26 | set_load -pin_load 1 [get_ports {dout_r[5]}] 27 | set_load -pin_load 1 [get_ports {dout_r[4]}] 28 | set_load -pin_load 1 [get_ports {dout_r[3]}] 29 | set_load -pin_load 1 [get_ports {dout_r[2]}] 30 | set_load -pin_load 1 [get_ports {dout_r[1]}] 31 | set_load -pin_load 1 [get_ports {dout_r[0]}] 32 | set_load -pin_load 1 [get_ports {dout_i[15]}] 33 | set_load -pin_load 1 [get_ports {dout_i[14]}] 34 | set_load -pin_load 1 [get_ports {dout_i[13]}] 35 | set_load -pin_load 1 [get_ports {dout_i[12]}] 36 | set_load -pin_load 1 [get_ports {dout_i[11]}] 37 | set_load -pin_load 1 [get_ports {dout_i[10]}] 38 | set_load -pin_load 1 [get_ports {dout_i[9]}] 39 | set_load -pin_load 1 [get_ports {dout_i[8]}] 40 | set_load -pin_load 1 [get_ports {dout_i[7]}] 41 | set_load -pin_load 1 [get_ports {dout_i[6]}] 42 | set_load -pin_load 1 [get_ports {dout_i[5]}] 43 | set_load -pin_load 1 [get_ports {dout_i[4]}] 44 | set_load -pin_load 1 [get_ports {dout_i[3]}] 45 | set_load -pin_load 1 [get_ports {dout_i[2]}] 46 | set_load -pin_load 1 [get_ports {dout_i[1]}] 47 | set_load -pin_load 1 [get_ports {dout_i[0]}] 48 | create_clock [get_ports clk] -period 10 -waveform {0 5} 49 | set_clock_latency 0.5 [get_clocks clk] 50 | set_clock_uncertainty 0.1 [get_clocks clk] 51 | group_path -name INOUT -from [list [get_ports clk] [get_ports rst_n] [get_ports in_valid] [get_ports \ 52 | {din_r[11]}] [get_ports {din_r[10]}] [get_ports {din_r[9]}] [get_ports \ 53 | {din_r[8]}] [get_ports {din_r[7]}] [get_ports {din_r[6]}] [get_ports \ 54 | {din_r[5]}] [get_ports {din_r[4]}] [get_ports {din_r[3]}] [get_ports \ 55 | {din_r[2]}] [get_ports {din_r[1]}] [get_ports {din_r[0]}] [get_ports \ 56 | {din_i[11]}] [get_ports {din_i[10]}] [get_ports {din_i[9]}] [get_ports \ 57 | {din_i[8]}] [get_ports {din_i[7]}] [get_ports {din_i[6]}] [get_ports \ 58 | {din_i[5]}] [get_ports {din_i[4]}] [get_ports {din_i[3]}] [get_ports \ 59 | {din_i[2]}] [get_ports {din_i[1]}] [get_ports {din_i[0]}]] -to [list [get_ports out_valid] [get_ports {dout_r[15]}] [get_ports \ 60 | {dout_r[14]}] [get_ports {dout_r[13]}] [get_ports {dout_r[12]}] [get_ports \ 61 | {dout_r[11]}] [get_ports {dout_r[10]}] [get_ports {dout_r[9]}] [get_ports \ 62 | {dout_r[8]}] [get_ports {dout_r[7]}] [get_ports {dout_r[6]}] [get_ports \ 63 | {dout_r[5]}] [get_ports {dout_r[4]}] [get_ports {dout_r[3]}] [get_ports \ 64 | {dout_r[2]}] [get_ports {dout_r[1]}] [get_ports {dout_r[0]}] [get_ports \ 65 | {dout_i[15]}] [get_ports {dout_i[14]}] [get_ports {dout_i[13]}] [get_ports \ 66 | {dout_i[12]}] [get_ports {dout_i[11]}] [get_ports {dout_i[10]}] [get_ports \ 67 | {dout_i[9]}] [get_ports {dout_i[8]}] [get_ports {dout_i[7]}] [get_ports \ 68 | {dout_i[6]}] [get_ports {dout_i[5]}] [get_ports {dout_i[4]}] [get_ports \ 69 | {dout_i[3]}] [get_ports {dout_i[2]}] [get_ports {dout_i[1]}] [get_ports \ 70 | {dout_i[0]}]] 71 | group_path -name INREG -from [list [get_ports rst_n] [get_ports in_valid] [get_ports {din_r[11]}] \ 72 | [get_ports {din_r[10]}] [get_ports {din_r[9]}] [get_ports {din_r[8]}] \ 73 | [get_ports {din_r[7]}] [get_ports {din_r[6]}] [get_ports {din_r[5]}] \ 74 | [get_ports {din_r[4]}] [get_ports {din_r[3]}] [get_ports {din_r[2]}] \ 75 | [get_ports {din_r[1]}] [get_ports {din_r[0]}] [get_ports {din_i[11]}] \ 76 | [get_ports {din_i[10]}] [get_ports {din_i[9]}] [get_ports {din_i[8]}] \ 77 | [get_ports {din_i[7]}] [get_ports {din_i[6]}] [get_ports {din_i[5]}] \ 78 | [get_ports {din_i[4]}] [get_ports {din_i[3]}] [get_ports {din_i[2]}] \ 79 | [get_ports {din_i[1]}] [get_ports {din_i[0]}]] 80 | group_path -name INREG -from [get_ports clk] 81 | group_path -name REGOUT -to [list [get_ports out_valid] [get_ports {dout_r[15]}] [get_ports \ 82 | {dout_r[14]}] [get_ports {dout_r[13]}] [get_ports {dout_r[12]}] [get_ports \ 83 | {dout_r[11]}] [get_ports {dout_r[10]}] [get_ports {dout_r[9]}] [get_ports \ 84 | {dout_r[8]}] [get_ports {dout_r[7]}] [get_ports {dout_r[6]}] [get_ports \ 85 | {dout_r[5]}] [get_ports {dout_r[4]}] [get_ports {dout_r[3]}] [get_ports \ 86 | {dout_r[2]}] [get_ports {dout_r[1]}] [get_ports {dout_r[0]}] [get_ports \ 87 | {dout_i[15]}] [get_ports {dout_i[14]}] [get_ports {dout_i[13]}] [get_ports \ 88 | {dout_i[12]}] [get_ports {dout_i[11]}] [get_ports {dout_i[10]}] [get_ports \ 89 | {dout_i[9]}] [get_ports {dout_i[8]}] [get_ports {dout_i[7]}] [get_ports \ 90 | {dout_i[6]}] [get_ports {dout_i[5]}] [get_ports {dout_i[4]}] [get_ports \ 91 | {dout_i[3]}] [get_ports {dout_i[2]}] [get_ports {dout_i[1]}] [get_ports \ 92 | {dout_i[0]}]] 93 | set_false_path -hold -from [list [get_ports rst_n] [get_ports in_valid] [get_ports {din_r[11]}] \ 94 | [get_ports {din_r[10]}] [get_ports {din_r[9]}] [get_ports {din_r[8]}] \ 95 | [get_ports {din_r[7]}] [get_ports {din_r[6]}] [get_ports {din_r[5]}] \ 96 | [get_ports {din_r[4]}] [get_ports {din_r[3]}] [get_ports {din_r[2]}] \ 97 | [get_ports {din_r[1]}] [get_ports {din_r[0]}] [get_ports {din_i[11]}] \ 98 | [get_ports {din_i[10]}] [get_ports {din_i[9]}] [get_ports {din_i[8]}] \ 99 | [get_ports {din_i[7]}] [get_ports {din_i[6]}] [get_ports {din_i[5]}] \ 100 | [get_ports {din_i[4]}] [get_ports {din_i[3]}] [get_ports {din_i[2]}] \ 101 | [get_ports {din_i[1]}] [get_ports {din_i[0]}]] 102 | set_false_path -hold -to [list [get_ports out_valid] [get_ports {dout_r[15]}] [get_ports \ 103 | {dout_r[14]}] [get_ports {dout_r[13]}] [get_ports {dout_r[12]}] [get_ports \ 104 | {dout_r[11]}] [get_ports {dout_r[10]}] [get_ports {dout_r[9]}] [get_ports \ 105 | {dout_r[8]}] [get_ports {dout_r[7]}] [get_ports {dout_r[6]}] [get_ports \ 106 | {dout_r[5]}] [get_ports {dout_r[4]}] [get_ports {dout_r[3]}] [get_ports \ 107 | {dout_r[2]}] [get_ports {dout_r[1]}] [get_ports {dout_r[0]}] [get_ports \ 108 | {dout_i[15]}] [get_ports {dout_i[14]}] [get_ports {dout_i[13]}] [get_ports \ 109 | {dout_i[12]}] [get_ports {dout_i[11]}] [get_ports {dout_i[10]}] [get_ports \ 110 | {dout_i[9]}] [get_ports {dout_i[8]}] [get_ports {dout_i[7]}] [get_ports \ 111 | {dout_i[6]}] [get_ports {dout_i[5]}] [get_ports {dout_i[4]}] [get_ports \ 112 | {dout_i[3]}] [get_ports {dout_i[2]}] [get_ports {dout_i[1]}] [get_ports \ 113 | {dout_i[0]}]] 114 | set_input_delay -clock clk -max 5 [get_ports rst_n] 115 | set_input_delay -clock clk -max 5 [get_ports in_valid] 116 | set_input_delay -clock clk -max 5 [get_ports {din_r[11]}] 117 | set_input_delay -clock clk -max 5 [get_ports {din_r[10]}] 118 | set_input_delay -clock clk -max 5 [get_ports {din_r[9]}] 119 | set_input_delay -clock clk -max 5 [get_ports {din_r[8]}] 120 | set_input_delay -clock clk -max 5 [get_ports {din_r[7]}] 121 | set_input_delay -clock clk -max 5 [get_ports {din_r[6]}] 122 | set_input_delay -clock clk -max 5 [get_ports {din_r[5]}] 123 | set_input_delay -clock clk -max 5 [get_ports {din_r[4]}] 124 | set_input_delay -clock clk -max 5 [get_ports {din_r[3]}] 125 | set_input_delay -clock clk -max 5 [get_ports {din_r[2]}] 126 | set_input_delay -clock clk -max 5 [get_ports {din_r[1]}] 127 | set_input_delay -clock clk -max 5 [get_ports {din_r[0]}] 128 | set_input_delay -clock clk -max 5 [get_ports {din_i[11]}] 129 | set_input_delay -clock clk -max 5 [get_ports {din_i[10]}] 130 | set_input_delay -clock clk -max 5 [get_ports {din_i[9]}] 131 | set_input_delay -clock clk -max 5 [get_ports {din_i[8]}] 132 | set_input_delay -clock clk -max 5 [get_ports {din_i[7]}] 133 | set_input_delay -clock clk -max 5 [get_ports {din_i[6]}] 134 | set_input_delay -clock clk -max 5 [get_ports {din_i[5]}] 135 | set_input_delay -clock clk -max 5 [get_ports {din_i[4]}] 136 | set_input_delay -clock clk -max 5 [get_ports {din_i[3]}] 137 | set_input_delay -clock clk -max 5 [get_ports {din_i[2]}] 138 | set_input_delay -clock clk -max 5 [get_ports {din_i[1]}] 139 | set_input_delay -clock clk -max 5 [get_ports {din_i[0]}] 140 | set_output_delay -clock clk -max 5 [get_ports out_valid] 141 | set_output_delay -clock clk -max 5 [get_ports {dout_r[15]}] 142 | set_output_delay -clock clk -max 5 [get_ports {dout_r[14]}] 143 | set_output_delay -clock clk -max 5 [get_ports {dout_r[13]}] 144 | set_output_delay -clock clk -max 5 [get_ports {dout_r[12]}] 145 | set_output_delay -clock clk -max 5 [get_ports {dout_r[11]}] 146 | set_output_delay -clock clk -max 5 [get_ports {dout_r[10]}] 147 | set_output_delay -clock clk -max 5 [get_ports {dout_r[9]}] 148 | set_output_delay -clock clk -max 5 [get_ports {dout_r[8]}] 149 | set_output_delay -clock clk -max 5 [get_ports {dout_r[7]}] 150 | set_output_delay -clock clk -max 5 [get_ports {dout_r[6]}] 151 | set_output_delay -clock clk -max 5 [get_ports {dout_r[5]}] 152 | set_output_delay -clock clk -max 5 [get_ports {dout_r[4]}] 153 | set_output_delay -clock clk -max 5 [get_ports {dout_r[3]}] 154 | set_output_delay -clock clk -max 5 [get_ports {dout_r[2]}] 155 | set_output_delay -clock clk -max 5 [get_ports {dout_r[1]}] 156 | set_output_delay -clock clk -max 5 [get_ports {dout_r[0]}] 157 | set_output_delay -clock clk -max 5 [get_ports {dout_i[15]}] 158 | set_output_delay -clock clk -max 5 [get_ports {dout_i[14]}] 159 | set_output_delay -clock clk -max 5 [get_ports {dout_i[13]}] 160 | set_output_delay -clock clk -max 5 [get_ports {dout_i[12]}] 161 | set_output_delay -clock clk -max 5 [get_ports {dout_i[11]}] 162 | set_output_delay -clock clk -max 5 [get_ports {dout_i[10]}] 163 | set_output_delay -clock clk -max 5 [get_ports {dout_i[9]}] 164 | set_output_delay -clock clk -max 5 [get_ports {dout_i[8]}] 165 | set_output_delay -clock clk -max 5 [get_ports {dout_i[7]}] 166 | set_output_delay -clock clk -max 5 [get_ports {dout_i[6]}] 167 | set_output_delay -clock clk -max 5 [get_ports {dout_i[5]}] 168 | set_output_delay -clock clk -max 5 [get_ports {dout_i[4]}] 169 | set_output_delay -clock clk -max 5 [get_ports {dout_i[3]}] 170 | set_output_delay -clock clk -max 5 [get_ports {dout_i[2]}] 171 | set_output_delay -clock clk -max 5 [get_ports {dout_i[1]}] 172 | set_output_delay -clock clk -max 5 [get_ports {dout_i[0]}] 173 | set_drive 1 [get_ports clk] 174 | set_drive 1 [get_ports rst_n] 175 | set_drive 1 [get_ports in_valid] 176 | set_drive 1 [get_ports {din_r[11]}] 177 | set_drive 1 [get_ports {din_r[10]}] 178 | set_drive 1 [get_ports {din_r[9]}] 179 | set_drive 1 [get_ports {din_r[8]}] 180 | set_drive 1 [get_ports {din_r[7]}] 181 | set_drive 1 [get_ports {din_r[6]}] 182 | set_drive 1 [get_ports {din_r[5]}] 183 | set_drive 1 [get_ports {din_r[4]}] 184 | set_drive 1 [get_ports {din_r[3]}] 185 | set_drive 1 [get_ports {din_r[2]}] 186 | set_drive 1 [get_ports {din_r[1]}] 187 | set_drive 1 [get_ports {din_r[0]}] 188 | set_drive 1 [get_ports {din_i[11]}] 189 | set_drive 1 [get_ports {din_i[10]}] 190 | set_drive 1 [get_ports {din_i[9]}] 191 | set_drive 1 [get_ports {din_i[8]}] 192 | set_drive 1 [get_ports {din_i[7]}] 193 | set_drive 1 [get_ports {din_i[6]}] 194 | set_drive 1 [get_ports {din_i[5]}] 195 | set_drive 1 [get_ports {din_i[4]}] 196 | set_drive 1 [get_ports {din_i[3]}] 197 | set_drive 1 [get_ports {din_i[2]}] 198 | set_drive 1 [get_ports {din_i[1]}] 199 | set_drive 1 [get_ports {din_i[0]}] 200 | -------------------------------------------------------------------------------- /SYN/report/synth_area.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : area 4 | Design : FFT 5 | Version: K-2015.06 6 | Date : Sat Jan 1 11:36:53 2022 7 | **************************************** 8 | 9 | Library(s) Used: 10 | 11 | fsc0h_d_generic_core_ss1p08v125c (File: /home/IC/Desktop/Abdelazeem/Technology_Library/UMC130nm/lib/StdCell/fsc0h_d_generic_core_ss1p08v125c.db) 12 | 13 | Number of ports: 1390 14 | Number of nets: 15159 15 | Number of cells: 12799 16 | Number of combinational cells: 10401 17 | Number of sequential cells: 2392 18 | Number of macros/black boxes: 0 19 | Number of buf/inv: 1522 20 | Number of references: 80 21 | 22 | Combinational area: 115985.919649 23 | Buf/Inv area: 6324.479866 24 | Noncombinational area: 86227.200359 25 | Macro/Black Box area: 0.000000 26 | Net Interconnect area: undefined (Wire load has zero net area) 27 | 28 | Total cell area: 202213.120008 29 | Total area: undefined 30 | 1 31 | -------------------------------------------------------------------------------- /SYN/report/synth_power.rpt: -------------------------------------------------------------------------------- 1 | **************************************** 2 | Report : power 3 | -analysis_effort low 4 | Design : FFT 5 | Version: K-2015.06 6 | Date : Sat Jan 1 11:41:59 2022 7 | **************************************** 8 | 9 | 10 | Library(s) Used: 11 | 12 | fsc0h_d_generic_core_ss1p08v125c (File: /home/IC/Desktop/Abdelazeem/Technology_Library/UMC130nm/lib/StdCell/fsc0h_d_generic_core_ss1p08v125c.db) 13 | 14 | 15 | Operating Conditions: WCCOM Library: fsc0h_d_generic_core_ss1p08v125c 16 | Wire Load Model Mode: enclosed 17 | 18 | Design Wire Load Model Library 19 | ------------------------------------------------ 20 | FFT G5K fsc0h_d_generic_core_ss1p08v125c 21 | radix2_4 enG10K fsc0h_d_generic_core_ss1p08v125c 22 | shift_16 enG5K fsc0h_d_generic_core_ss1p08v125c 23 | radix2_3 enG10K fsc0h_d_generic_core_ss1p08v125c 24 | radix2_2 enG10K fsc0h_d_generic_core_ss1p08v125c 25 | radix2_1 enG5K fsc0h_d_generic_core_ss1p08v125c 26 | radix2_0 enG5K fsc0h_d_generic_core_ss1p08v125c 27 | 28 | 29 | Global Operating Voltage = 1.08 30 | Power-specific unit information : 31 | Voltage Units = 1V 32 | Capacitance Units = 1.000000pf 33 | Time Units = 1ns 34 | Dynamic Power Units = 1mW (derived from V,C,T units) 35 | Leakage Power Units = 1pW 36 | 37 | 38 | Cell Internal Power = 2.6986 mW (96%) 39 | Net Switching Power = 126.3021 uW (4%) 40 | --------- 41 | Total Dynamic Power = 2.8249 mW (100%) 42 | 43 | Cell Leakage Power = 127.0537 uW 44 | 45 | 46 | Internal Switching Leakage Total 47 | Power Group Power Power Power Power ( % ) Attrs 48 | -------------------------------------------------------------------------------------------------- 49 | io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) 50 | memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) 51 | black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) 52 | clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) 53 | register 2.6494 1.6785e-02 4.4112e+07 2.7102 ( 91.81%) 54 | sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%) 55 | combinational 4.9205e-02 0.1095 8.2942e+07 0.2417 ( 8.19%) 56 | -------------------------------------------------------------------------------------------------- 57 | Total 2.6986 mW 0.1263 mW 1.2705e+08 pW 2.9519 mW 58 | 59 | -------------------------------------------------------------------------------- /SYN/report/synth_qor.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : qor 4 | Design : FFT 5 | Version: K-2015.06 6 | Date : Sat Jan 1 11:36:53 2022 7 | **************************************** 8 | 9 | 10 | Timing Path Group 'INREG' 11 | ----------------------------------- 12 | Levels of Logic: 0.00 13 | Critical Path Length: 0.00 14 | Critical Path Slack: 4.68 15 | Critical Path Clk Period: 10.00 16 | Total Negative Slack: 0.00 17 | No. of Violating Paths: 0.00 18 | Worst Hold Violation: 0.00 19 | Total Hold Violation: 0.00 20 | No. of Hold Violations: 0.00 21 | ----------------------------------- 22 | 23 | Timing Path Group 'REGOUT' 24 | ----------------------------------- 25 | Levels of Logic: 1.00 26 | Critical Path Length: 1.63 27 | Critical Path Slack: 3.27 28 | Critical Path Clk Period: 10.00 29 | Total Negative Slack: 0.00 30 | No. of Violating Paths: 0.00 31 | Worst Hold Violation: 0.00 32 | Total Hold Violation: 0.00 33 | No. of Hold Violations: 0.00 34 | ----------------------------------- 35 | 36 | Timing Path Group 'clk' 37 | ----------------------------------- 38 | Levels of Logic: 58.00 39 | Critical Path Length: 9.68 40 | Critical Path Slack: 0.00 41 | Critical Path Clk Period: 10.00 42 | Total Negative Slack: 0.00 43 | No. of Violating Paths: 0.00 44 | Worst Hold Violation: 0.00 45 | Total Hold Violation: 0.00 46 | No. of Hold Violations: 0.00 47 | ----------------------------------- 48 | 49 | 50 | Cell Count 51 | ----------------------------------- 52 | Hierarchical Cell Count: 6 53 | Hierarchical Port Count: 1330 54 | Leaf Cell Count: 12793 55 | Buf/Inv Cell Count: 1522 56 | Buf Cell Count: 76 57 | Inv Cell Count: 1446 58 | CT Buf/Inv Cell Count: 0 59 | Combinational Cell Count: 10401 60 | Sequential Cell Count: 2392 61 | Macro Count: 0 62 | ----------------------------------- 63 | 64 | 65 | Area 66 | ----------------------------------- 67 | Combinational Area: 115985.919649 68 | Noncombinational Area: 86227.200359 69 | Buf/Inv Area: 6324.479866 70 | Total Buffer Area: 456.96 71 | Total Inverter Area: 5867.52 72 | Macro/Black Box Area: 0.000000 73 | Net Area: 0.000000 74 | ----------------------------------- 75 | Cell Area: 202213.120008 76 | Design Area: 202213.120008 77 | 78 | 79 | Design Rules 80 | ----------------------------------- 81 | Total Number of Nets: 14116 82 | Nets With Violations: 0 83 | Max Trans Violations: 0 84 | Max Cap Violations: 0 85 | ----------------------------------- 86 | 87 | 88 | Hostname: IC 89 | 90 | Compile CPU Statistics 91 | ----------------------------------------- 92 | Resource Sharing: 0.01 93 | Logic Optimization: 0.54 94 | Mapping Optimization: 20.67 95 | ----------------------------------------- 96 | Overall Compile Time: 41.22 97 | Overall Compile Wall Clock Time: 629.90 98 | 99 | -------------------------------------------------------------------- 100 | 101 | Design WNS: 0.00 TNS: 0.00 Number of Violating Paths: 0 102 | 103 | 104 | Design (Hold) WNS: 0.00 TNS: 0.00 Number of Violating Paths: 0 105 | 106 | -------------------------------------------------------------------- 107 | 108 | 109 | 1 110 | -------------------------------------------------------------------------------- /SYN/report/synth_resources.rpt: -------------------------------------------------------------------------------- 1 | 2 | **************************************** 3 | Report : resources 4 | Design : FFT 5 | Version: K-2015.06 6 | Date : Sat Jan 1 11:36:54 2022 7 | **************************************** 8 | 9 | 10 | Resource Sharing Report for design FFT in file ../rtl/FFT.v 11 | 12 | =============================================================================== 13 | | | | | Contained | | 14 | | Resource | Module | Parameters | Resources | Contained Operations | 15 | =============================================================================== 16 | | r127 | DW01_cmp2 | width=6 | | gt_47 | 17 | | r129 | DW01_sub | width=5 | | sub_47_aco | 18 | | r131 | DW01_inc | width=6 | | add_251_S2 | 19 | | rom16/r66 | | | | 20 | | | DW01_inc | width=6 | | rom16/add_13_S2 | 21 | | rom16/r68 | | | | 22 | | | DW01_cmp2 | width=6 | | rom16/lt_20 | 23 | | shift_8/r61 | | | | 24 | | | DW01_add | width=192 | | shift_8/add_38 | 25 | | | | | | shift_8/add_43 | 26 | | shift_8/r62 | | | | 27 | | | DW01_add | width=192 | | shift_8/add_39 | 28 | | | | | | shift_8/add_44 | 29 | | rom8/r64 | DW01_inc | width=4 | | rom8/add_29 | 30 | | | | | | rom8/add_33 | 31 | | rom8/r67 | DW01_inc | width=6 | | rom8/add_17 | 32 | | shift_4/r61 | | | | 33 | | | DW01_add | width=96 | | shift_4/add_38 | 34 | | | | | | shift_4/add_43 | 35 | | shift_4/r62 | | | | 36 | | | DW01_add | width=96 | | shift_4/add_39 | 37 | | | | | | shift_4/add_44 | 38 | | rom4/r64 | DW01_inc | width=3 | | rom4/add_29 | 39 | | | | | | rom4/add_33 | 40 | | rom4/r67 | DW01_inc | width=6 | | rom4/add_17 | 41 | | shift_2/r60 | | | | 42 | | | DW01_add | width=48 | | shift_2/add_38 | 43 | | | | | | shift_2/add_43 | 44 | | shift_2/r61 | | | | 45 | | | DW01_add | width=48 | | shift_2/add_39 | 46 | | | | | | shift_2/add_44 | 47 | | rom2/r60 | DW01_inc | width=2 | | rom2/add_30 | 48 | | | | | | rom2/add_33 | 49 | | rom2/r63 | DW01_inc | width=6 | | rom2/add_18 | 50 | =============================================================================== 51 | 52 | 53 | No implementations to report 54 | 1 55 | -------------------------------------------------------------------------------- /SYN/run: -------------------------------------------------------------------------------- 1 | rm -rf log/* report/* output/* 2 | dc_shell -f scripts/syn.tcl | tee log/syn.log 3 | rm -rf command.log filenames.log 4 | -------------------------------------------------------------------------------- /SYN/scripts/syn.tcl: -------------------------------------------------------------------------------- 1 | set design FFT 2 | 3 | set_app_var search_path "/home/IC/Desktop/Abdelazeem/Technology_Library/UMC130nm/lib/StdCell" 4 | 5 | set_app_var link_library "* fsc0h_d_generic_core_ss1p08v125c.db fsc0h_d_generic_core_ff1p32vm40c.db" 6 | set_app_var target_library "fsc0h_d_generic_core_ss1p08v125c.db" 7 | 8 | sh rm -rf work 9 | sh mkdir -p work 10 | define_design_lib work -path ./work 11 | 12 | 13 | analyze -library work -format verilog ../rtl/${design}.v 14 | elaborate $design -lib work 15 | current_design 16 | uniquify 17 | 18 | check_design 19 | source ./cons/cons.tcl 20 | link 21 | compile -map_effort medium 22 | optimize_registers 23 | compile_ultra 24 | 25 | report_area > ./report/synth_area.rpt 26 | report_cell > ./report/synth_cells.rpt 27 | report_qor > ./report/synth_qor.rpt 28 | report_resources > ./report/synth_resources.rpt 29 | report_timing -max_paths 10 > ./report/synth_timing.rpt 30 | 31 | write_sdc output/${design}.sdc 32 | 33 | define_name_rules no_case -case_insensitive 34 | change_names -rule no_case -hierarchy 35 | change_names -rule verilog -hierarchy 36 | set verilogout_no_tri true 37 | set verilogout_equation false 38 | 39 | write -hierarchy -format verilog -output output/${design}.v 40 | write -f ddc -hierarchy -output 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