├── LICENSE ├── Pics ├── Arch.png ├── Capture.PNG ├── ReadMe ├── arch of Sys.png └── synthesis_FPGA.PNG ├── Pre-Synthesis_Simulation ├── addr_sel.v ├── golden1.txt ├── golden2.txt ├── golden3.txt ├── mat1.txt ├── mat2.txt ├── quantize.v ├── sram_16x128b.v ├── sram_20000x100b.v ├── sram_256x32b.v ├── sram_64x512b.v ├── systolic.v ├── systolic_controll.v ├── test_tpu.v ├── tpu_top.v └── write_out.v ├── README.md ├── pnr ├── .__tmp_pns_undo_file.tcl ├── .interactive.constr.sdc ├── .mips12254.rs.fp ├── .mips12254.rs.fp.spr ├── .riwKs47h ├── .routing_guide.rgf ├── .timing_file.tif ├── .tmp.itf2TLU.oldattach ├── command.log ├── icc_gui.output ├── icc_output ├── icc_output.txt ├── net.acts ├── output │ ├── tpu_top.gds │ ├── tpu_top.sdc │ ├── tpu_top_icc.v │ └── tpu_top_icc_nopg.v ├── output_heatmap ├── pna_output │ ├── VDD.VD.report │ ├── VDD.pad_current │ ├── VSS.pad_current │ ├── create_pns_pg.tcl │ ├── pns_replay.tcl │ ├── tpu_top.VDD.ar │ ├── tpu_top.VDD.power │ ├── tpu_top.VDD.pw_hl.pna │ ├── tpu_top.VPNA.log │ ├── tpu_top.VSS.ar │ ├── tpu_top.VSS.power │ ├── tpu_top.VSS.pw_hl.pna │ ├── tpu_top.connview │ └── tpu_top.inst_hl.pna ├── run ├── scripts │ ├── 0_design_setup.tcl │ ├── 1_floorplan.tcl │ ├── 2_powerplan.tcl │ ├── 3_placement.tcl │ ├── 4_clock_tree.tcl │ ├── 5_route.tcl │ ├── 6_verify_and_output.tcl │ └── eco.tcl └── tpu_top_port_map.0 ├── rtl ├── RTL_modified │ ├── benchmarking │ │ └── xrays │ │ │ ├── quantized.cpp │ │ │ ├── test.cpp │ │ │ └── train.cpp │ ├── busConn.v │ ├── software │ │ └── instr_set.h │ ├── top.v │ ├── tpu.v │ ├── tpu_system.v │ └── weightFifo │ │ ├── dff8.v │ │ └── weightFifo.v ├── addr_sel.v ├── quantize.v ├── systolic array │ ├── Readme.md │ ├── addr_sel.v │ ├── quantize.v │ ├── systolic.v │ ├── systolic_controller.v │ └── tpu_top.v ├── systolic.v ├── systolic_controll.v ├── tpu_top ├── tpu_top.v └── write_out.v └── syn ├── command.log ├── cons └── cons.tcl ├── default.svf ├── log ├── check_design.log └── check_timing.log ├── output ├── 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