├── ASU-DDR5-digital-Presentation.pdf ├── Documentation ├── Digital Design Architecture.pdf ├── Final_Write Flow.pdf ├── PHY Architecture Design Document.pdf ├── pics │ ├── CA.jpg │ ├── PHY.jpg │ ├── architecture.jpg │ ├── crc.png │ ├── freq.jpg │ ├── fsm.jpg │ ├── pc.txt │ ├── schematic view.png │ ├── timing diagram.png │ └── wm.jpg └── timing diagrams │ ├── back to back freq ratio CRC.png │ ├── singale CRC BL16.png │ ├── single CRC BL32.png │ ├── single mask BL16.png │ ├── two write freq ratio 2.png │ ├── two_ind mask BL16.png │ ├── twowrite CRC BL16.png │ └── twowrite mask BL16.png ├── FPGA ├── FPGA.pptx ├── asu_ddr5_phy_top.bit ├── pictures │ ├── FPGA netlist.PNG │ ├── logic level CA.PNG │ ├── logic level CRC.PNG │ ├── logic level WRcounters.PNG │ ├── logic level WRfsm.PNG │ ├── logic level WRshift.PNG │ ├── logic level freq.PNG │ ├── logic level regfile.PNG │ ├── logic level topsystem.PNG │ ├── pc.txt │ ├── postsynthesis simulation.PNG │ ├── simulation.PNG │ └── zoomed postsynthesis simulation.PNG ├── reports │ ├── asu_ddr5_phy_top_clock_utilization_routed.rpt │ ├── asu_ddr5_phy_top_control_sets_placed.rpt │ ├── asu_ddr5_phy_top_drc_opted.rpt │ ├── asu_ddr5_phy_top_drc_routed.rpt │ ├── asu_ddr5_phy_top_io_placed.rpt │ ├── asu_ddr5_phy_top_route_status.rpt │ ├── asu_ddr5_phy_top_timing_summary_routed.rpt │ └── asu_ddr5_phy_top_utilization_placed.rpt ├── src │ ├── constraints_file.xdc │ ├── rtl │ │ ├── asu_ddr5_command_address.sv │ │ ├── asu_ddr5_crc.sv │ │ ├── asu_ddr5_crc_x4.sv │ │ ├── asu_ddr5_frequency_ratio.sv │ │ ├── asu_ddr5_phy_top.sv │ │ ├── asu_ddr5_register_file.sv │ │ ├── asu_ddr5_write_counter.sv │ │ ├── asu_ddr5_write_fsm.sv │ │ ├── asu_ddr5_write_manager.sv │ │ ├── asu_ddr5_write_shift.sv │ │ └── c │ └── tb │ │ ├── asu_ddr5_phy_top_BL32_CRC_tb.sv │ │ ├── asu_ddr5_phy_top_BL32_MASK_tb.sv │ │ ├── asu_ddr5_phy_top_freq_tb.sv │ │ ├── asu_ddr5_phy_top_tb.sv │ │ ├── asu_ddr5_phy_top_x8_tb.sv │ │ └── testbench.txt └── write_bitstream.pb ├── README.md ├── RTL ├── ddr5_phy_command_address.sv ├── ddr5_phy_crc.sv ├── ddr5_phy_crc_x4.sv ├── ddr5_phy_frequency_ratio.sv ├── ddr5_phy_register_file.sv ├── ddr5_phy_top.sv ├── ddr5_phy_write_counter.sv ├── ddr5_phy_write_fsm.sv ├── ddr5_phy_write_manager.sv └── ddr5_phy_write_shift.sv ├── Synthesis ├── CRC_block │ ├── CRC.txt │ ├── area.rpt │ ├── power.rpt │ ├── syn_script.tcl │ ├── timing_max.rpt │ └── timing_min.rpt ├── command_address_block │ ├── area.rpt │ ├── power.rpt │ ├── syn_script.tcl │ ├── synthesis │ ├── timing_max.rpt │ └── timing_min.rpt ├── frequency_ratio_block │ ├── area.rpt │ ├── fq.txt │ ├── power.rpt │ ├── synthesis_script.tcl │ ├── timing_max.rpt │ └── timing_min.rpt └── write_manager_block │ ├── area.rpt │ ├── power.rpt │ ├── syn_script.tcl │ ├── timing_max.rpt │ ├── timing_min.rpt │ └── wm.txt └── TB ├── ddr5_phy_top_BL32_CRC_tb.sv ├── ddr5_phy_top_BL32_MASK_tb.sv ├── ddr5_phy_top_freq_tb.sv ├── ddr5_phy_top_tb.sv └── ddr5_phy_top_x8_tb.sv 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