├── .cproject ├── .cproject_org ├── .gitignore ├── .mxproject ├── .project ├── .project_org ├── .settings ├── language.settings.xml └── org.eclipse.core.resources.prefs ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F1xx │ │ │ └── Include │ │ │ ├── stm32f103xb.h │ │ │ ├── stm32f1xx.h │ │ │ └── system_stm32f1xx.h │ └── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h └── STM32F1xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f1xx_hal.h │ ├── stm32f1xx_hal_cortex.h │ ├── stm32f1xx_hal_def.h │ ├── stm32f1xx_hal_dma.h │ ├── stm32f1xx_hal_dma_ex.h │ ├── stm32f1xx_hal_exti.h │ ├── stm32f1xx_hal_flash.h │ ├── stm32f1xx_hal_flash_ex.h │ ├── stm32f1xx_hal_gpio.h │ ├── stm32f1xx_hal_gpio_ex.h │ ├── stm32f1xx_hal_pwr.h │ ├── stm32f1xx_hal_rcc.h │ ├── stm32f1xx_hal_rcc_ex.h │ ├── stm32f1xx_hal_rtc.h │ ├── stm32f1xx_hal_rtc_ex.h │ ├── stm32f1xx_hal_tim.h │ └── stm32f1xx_hal_tim_ex.h │ └── Src │ ├── stm32f1xx_hal.c │ ├── stm32f1xx_hal_cortex.c │ ├── stm32f1xx_hal_dma.c │ ├── stm32f1xx_hal_exti.c │ ├── stm32f1xx_hal_flash.c │ ├── stm32f1xx_hal_flash_ex.c │ ├── stm32f1xx_hal_gpio.c │ ├── stm32f1xx_hal_gpio_ex.c │ ├── stm32f1xx_hal_pwr.c │ ├── stm32f1xx_hal_rcc.c │ ├── stm32f1xx_hal_rcc_ex.c │ ├── stm32f1xx_hal_rtc.c │ ├── stm32f1xx_hal_rtc_ex.c │ ├── stm32f1xx_hal_tim.c │ └── stm32f1xx_hal_tim_ex.c ├── Inc ├── main.h ├── stm32f1xx_hal_conf.h └── stm32f1xx_it.h ├── LICENSE ├── Main ├── Display │ ├── VideoSettings.h │ ├── font8x16.c │ ├── font8x16.h │ ├── font8x8.c │ ├── font8x8.h │ ├── timing.cpp │ ├── timing.h │ ├── vgaCore.cpp │ ├── vgaCore.h │ ├── vgaDraw.S │ ├── vgaDraw.h │ ├── vgaText.cpp │ └── vgaText.h ├── Keyboard │ ├── Queue.c │ ├── ps2Keyboard.cpp │ ├── ps2Keyboard.h │ └── queue.h ├── settings.h ├── startup.cpp └── startup.h ├── README.md ├── STM32F103C8Tx_FLASH.ld ├── Src ├── main.c ├── stm32f1xx_hal_msp.c ├── stm32f1xx_it.c ├── syscalls.c └── system_stm32f1xx.c ├── doc ├── Board.jpg └── Screenshot.jpg ├── startup └── startup_stm32f103xb.s ├── stm32f103-vgaText Debug.launch ├── stm32f103-vgaText Release.cfg ├── stm32f103-vgaText.cfg ├── stm32f103-vgaText.ioc ├── stm32f103-vgaText.launch ├── stm32f103-vgaText.xml └── stm32f103-z80emu.xml /.gitignore: -------------------------------------------------------------------------------- 1 | /Debug/ 2 | /Release/ 3 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousLibFiles] 2 | LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; 3 | 4 | [PreviousUsedSW4STM32Files] 5 | SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; 6 | HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; 7 | CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__));USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;STM32F103xB; 8 | 9 | [PreviousGenFiles] 10 | HeaderPath=D:/Projects/GitHub/stm32f103-vgaText/Inc 11 | HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; 12 | SourcePath=D:/Projects/GitHub/stm32f103-vgaText/Src 13 | SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; 14 | 15 | [PreviousUsedCubeIDEFiles] 16 | SourceFiles=Src\main.c;Src\stm32f1xx_it.c;Src\stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Src/system_stm32f1xx.c;;; 17 | HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Inc; 18 | CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;USE_HAL_DRIVER; 19 | 20 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | stm32f103-vgaText 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 24 | org.eclipse.cdt.core.ccnature 25 | com.st.stm32cube.ide.mcu.MCUSW4STM32ConvertedProjectNature 26 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 27 | 28 | 29 | -------------------------------------------------------------------------------- /.project_org: -------------------------------------------------------------------------------- 1 | 2 | 3 | stm32f103-vgaText 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | fr.ac6.mcu.ide.core.MCUProjectNature 26 | org.eclipse.cdt.core.ccnature 27 | 28 | 29 | -------------------------------------------------------------------------------- /.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /.settings/org.eclipse.core.resources.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | encoding//Main/Display/font8x16.c=UTF-8 3 | encoding//Main/Display/font8x8.c=UTF-8 4 | encoding//Main/startup.cpp=UTF-8 5 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f10x_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F10X_H 32 | #define __SYSTEM_STM32F10X_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F10x_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F10x_System_Exported_types 48 | * @{ 49 | */ 50 | 51 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 52 | extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ 53 | extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal.h 4 | * @author MCD Application Team 5 | * @brief This file contains all the functions prototypes for the HAL 6 | * module driver. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F1xx_HAL_H 23 | #define __STM32F1xx_HAL_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx_hal_conf.h" 31 | 32 | /** @addtogroup STM32F1xx_HAL_Driver 33 | * @{ 34 | */ 35 | 36 | /** @addtogroup HAL 37 | * @{ 38 | */ 39 | 40 | /* Exported constants --------------------------------------------------------*/ 41 | 42 | /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 | * @{ 44 | */ 45 | 46 | /** @defgroup HAL_TICK_FREQ Tick Frequency 47 | * @{ 48 | */ 49 | typedef enum 50 | { 51 | HAL_TICK_FREQ_10HZ = 100U, 52 | HAL_TICK_FREQ_100HZ = 10U, 53 | HAL_TICK_FREQ_1KHZ = 1U, 54 | HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 55 | } HAL_TickFreqTypeDef; 56 | /** 57 | * @} 58 | */ 59 | /* Exported types ------------------------------------------------------------*/ 60 | extern __IO uint32_t uwTick; 61 | extern uint32_t uwTickPrio; 62 | extern HAL_TickFreqTypeDef uwTickFreq; 63 | 64 | /** 65 | * @} 66 | */ 67 | /* Exported macro ------------------------------------------------------------*/ 68 | /** @defgroup HAL_Exported_Macros HAL Exported Macros 69 | * @{ 70 | */ 71 | 72 | /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 73 | * @brief Freeze/Unfreeze Peripherals in Debug mode 74 | * Note: On devices STM32F10xx8 and STM32F10xxB, 75 | * STM32F101xC/D/E and STM32F103xC/D/E, 76 | * STM32F101xF/G and STM32F103xF/G 77 | * STM32F10xx4 and STM32F10xx6 78 | * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in 79 | * debug mode (not accessible by the user software in normal mode). 80 | * Refer to errata sheet of these devices for more details. 81 | * @{ 82 | */ 83 | 84 | /* Peripherals on APB1 */ 85 | /** 86 | * @brief TIM2 Peripherals Debug mode 87 | */ 88 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 89 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) 90 | 91 | /** 92 | * @brief TIM3 Peripherals Debug mode 93 | */ 94 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 95 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) 96 | 97 | #if defined (DBGMCU_CR_DBG_TIM4_STOP) 98 | /** 99 | * @brief TIM4 Peripherals Debug mode 100 | */ 101 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 102 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) 103 | #endif 104 | 105 | #if defined (DBGMCU_CR_DBG_TIM5_STOP) 106 | /** 107 | * @brief TIM5 Peripherals Debug mode 108 | */ 109 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 110 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) 111 | #endif 112 | 113 | #if defined (DBGMCU_CR_DBG_TIM6_STOP) 114 | /** 115 | * @brief TIM6 Peripherals Debug mode 116 | */ 117 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 118 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) 119 | #endif 120 | 121 | #if defined (DBGMCU_CR_DBG_TIM7_STOP) 122 | /** 123 | * @brief TIM7 Peripherals Debug mode 124 | */ 125 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 126 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) 127 | #endif 128 | 129 | #if defined (DBGMCU_CR_DBG_TIM12_STOP) 130 | /** 131 | * @brief TIM12 Peripherals Debug mode 132 | */ 133 | #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 134 | #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) 135 | #endif 136 | 137 | #if defined (DBGMCU_CR_DBG_TIM13_STOP) 138 | /** 139 | * @brief TIM13 Peripherals Debug mode 140 | */ 141 | #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 142 | #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) 143 | #endif 144 | 145 | #if defined (DBGMCU_CR_DBG_TIM14_STOP) 146 | /** 147 | * @brief TIM14 Peripherals Debug mode 148 | */ 149 | #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 150 | #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) 151 | #endif 152 | 153 | /** 154 | * @brief WWDG Peripherals Debug mode 155 | */ 156 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 157 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) 158 | 159 | /** 160 | * @brief IWDG Peripherals Debug mode 161 | */ 162 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 163 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) 164 | 165 | /** 166 | * @brief I2C1 Peripherals Debug mode 167 | */ 168 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 169 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) 170 | 171 | #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 172 | /** 173 | * @brief I2C2 Peripherals Debug mode 174 | */ 175 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 176 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 177 | #endif 178 | 179 | #if defined (DBGMCU_CR_DBG_CAN1_STOP) 180 | /** 181 | * @brief CAN1 Peripherals Debug mode 182 | */ 183 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 184 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) 185 | #endif 186 | 187 | #if defined (DBGMCU_CR_DBG_CAN2_STOP) 188 | /** 189 | * @brief CAN2 Peripherals Debug mode 190 | */ 191 | #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 192 | #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) 193 | #endif 194 | 195 | /* Peripherals on APB2 */ 196 | #if defined (DBGMCU_CR_DBG_TIM1_STOP) 197 | /** 198 | * @brief TIM1 Peripherals Debug mode 199 | */ 200 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 201 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) 202 | #endif 203 | 204 | #if defined (DBGMCU_CR_DBG_TIM8_STOP) 205 | /** 206 | * @brief TIM8 Peripherals Debug mode 207 | */ 208 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 209 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) 210 | #endif 211 | 212 | #if defined (DBGMCU_CR_DBG_TIM9_STOP) 213 | /** 214 | * @brief TIM9 Peripherals Debug mode 215 | */ 216 | #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 217 | #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) 218 | #endif 219 | 220 | #if defined (DBGMCU_CR_DBG_TIM10_STOP) 221 | /** 222 | * @brief TIM10 Peripherals Debug mode 223 | */ 224 | #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 225 | #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) 226 | #endif 227 | 228 | #if defined (DBGMCU_CR_DBG_TIM11_STOP) 229 | /** 230 | * @brief TIM11 Peripherals Debug mode 231 | */ 232 | #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 233 | #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) 234 | #endif 235 | 236 | 237 | #if defined (DBGMCU_CR_DBG_TIM15_STOP) 238 | /** 239 | * @brief TIM15 Peripherals Debug mode 240 | */ 241 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 242 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) 243 | #endif 244 | 245 | #if defined (DBGMCU_CR_DBG_TIM16_STOP) 246 | /** 247 | * @brief TIM16 Peripherals Debug mode 248 | */ 249 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 250 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) 251 | #endif 252 | 253 | #if defined (DBGMCU_CR_DBG_TIM17_STOP) 254 | /** 255 | * @brief TIM17 Peripherals Debug mode 256 | */ 257 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 258 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) 259 | #endif 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | /** @defgroup HAL_Private_Macros HAL Private Macros 266 | * @{ 267 | */ 268 | #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 269 | ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 270 | ((FREQ) == HAL_TICK_FREQ_1KHZ)) 271 | /** 272 | * @} 273 | */ 274 | 275 | /* Exported functions --------------------------------------------------------*/ 276 | /** @addtogroup HAL_Exported_Functions 277 | * @{ 278 | */ 279 | /** @addtogroup HAL_Exported_Functions_Group1 280 | * @{ 281 | */ 282 | /* Initialization and de-initialization functions ******************************/ 283 | HAL_StatusTypeDef HAL_Init(void); 284 | HAL_StatusTypeDef HAL_DeInit(void); 285 | void HAL_MspInit(void); 286 | void HAL_MspDeInit(void); 287 | HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 288 | /** 289 | * @} 290 | */ 291 | 292 | /** @addtogroup HAL_Exported_Functions_Group2 293 | * @{ 294 | */ 295 | /* Peripheral Control functions ************************************************/ 296 | void HAL_IncTick(void); 297 | void HAL_Delay(uint32_t Delay); 298 | uint32_t HAL_GetTick(void); 299 | uint32_t HAL_GetTickPrio(void); 300 | HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 301 | HAL_TickFreqTypeDef HAL_GetTickFreq(void); 302 | void HAL_SuspendTick(void); 303 | void HAL_ResumeTick(void); 304 | uint32_t HAL_GetHalVersion(void); 305 | uint32_t HAL_GetREVID(void); 306 | uint32_t HAL_GetDEVID(void); 307 | uint32_t HAL_GetUIDw0(void); 308 | uint32_t HAL_GetUIDw1(void); 309 | uint32_t HAL_GetUIDw2(void); 310 | void HAL_DBGMCU_EnableDBGSleepMode(void); 311 | void HAL_DBGMCU_DisableDBGSleepMode(void); 312 | void HAL_DBGMCU_EnableDBGStopMode(void); 313 | void HAL_DBGMCU_DisableDBGStopMode(void); 314 | void HAL_DBGMCU_EnableDBGStandbyMode(void); 315 | void HAL_DBGMCU_DisableDBGStandbyMode(void); 316 | /** 317 | * @} 318 | */ 319 | 320 | /** 321 | * @} 322 | */ 323 | 324 | /** 325 | * @} 326 | */ 327 | /* Private types -------------------------------------------------------------*/ 328 | /* Private variables ---------------------------------------------------------*/ 329 | /** @defgroup HAL_Private_Variables HAL Private Variables 330 | * @{ 331 | */ 332 | /** 333 | * @} 334 | */ 335 | /* Private constants ---------------------------------------------------------*/ 336 | /** @defgroup HAL_Private_Constants HAL Private Constants 337 | * @{ 338 | */ 339 | /** 340 | * @} 341 | */ 342 | /* Private macros ------------------------------------------------------------*/ 343 | /* Private functions ---------------------------------------------------------*/ 344 | /** 345 | * @} 346 | */ 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | #ifdef __cplusplus 353 | } 354 | #endif 355 | 356 | #endif /* __STM32F1xx_HAL_H */ 357 | 358 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 359 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F1xx_HAL_DEF 23 | #define __STM32F1xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f1xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00U, 42 | HAL_ERROR = 0x01U, 43 | HAL_BUSY = 0x02U, 44 | HAL_TIMEOUT = 0x03U 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00U, 53 | HAL_LOCKED = 0x01U 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | #define HAL_MAX_DELAY 0xFFFFFFFFU 58 | 59 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) 60 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 61 | 62 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 63 | do{ \ 64 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 65 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 66 | } while(0U) 67 | 68 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 69 | 70 | /** @brief Reset the Handle's State field. 71 | * @param __HANDLE__ specifies the Peripheral Handle. 72 | * @note This macro can be used for the following purpose: 73 | * - When the Handle is declared as local variable; before passing it as parameter 74 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 75 | * to set to 0 the Handle's "State" field. 76 | * Otherwise, "State" field may have any random value and the first time the function 77 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 78 | * (i.e. HAL_PPP_MspInit() will not be executed). 79 | * - When there is a need to reconfigure the low level hardware: instead of calling 80 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 81 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 82 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 83 | * @retval None 84 | */ 85 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 86 | 87 | #if (USE_RTOS == 1U) 88 | /* Reserved for future use */ 89 | #error "USE_RTOS should be 0 in the current HAL release" 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0U) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0U) 107 | #endif /* USE_RTOS */ 108 | 109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 110 | #ifndef __weak 111 | #define __weak __attribute__((weak)) 112 | #endif 113 | #ifndef __packed 114 | #define __packed __attribute__((packed)) 115 | #endif 116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 117 | #ifndef __weak 118 | #define __weak __attribute__((weak)) 119 | #endif /* __weak */ 120 | #ifndef __packed 121 | #define __packed __attribute__((__packed__)) 122 | #endif /* __packed */ 123 | #endif /* __GNUC__ */ 124 | 125 | 126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 127 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 128 | #ifndef __ALIGN_BEGIN 129 | #define __ALIGN_BEGIN 130 | #endif 131 | #ifndef __ALIGN_END 132 | #define __ALIGN_END __attribute__ ((aligned (4))) 133 | #endif 134 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 135 | #ifndef __ALIGN_END 136 | #define __ALIGN_END __attribute__ ((aligned (4))) 137 | #endif /* __ALIGN_END */ 138 | #ifndef __ALIGN_BEGIN 139 | #define __ALIGN_BEGIN 140 | #endif /* __ALIGN_BEGIN */ 141 | #else 142 | #ifndef __ALIGN_END 143 | #define __ALIGN_END 144 | #endif /* __ALIGN_END */ 145 | #ifndef __ALIGN_BEGIN 146 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 147 | #define __ALIGN_BEGIN __align(4) 148 | #elif defined (__ICCARM__) /* IAR Compiler */ 149 | #define __ALIGN_BEGIN 150 | #endif /* __CC_ARM */ 151 | #endif /* __ALIGN_BEGIN */ 152 | #endif /* __GNUC__ */ 153 | 154 | 155 | /** 156 | * @brief __RAM_FUNC definition 157 | */ 158 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 159 | /* ARM Compiler V4/V5 and V6 160 | -------------------------- 161 | RAM functions are defined using the toolchain options. 162 | Functions that are executed in RAM should reside in a separate source module. 163 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 164 | area of a module to a memory space in physical RAM. 165 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 166 | dialog. 167 | */ 168 | #define __RAM_FUNC 169 | 170 | #elif defined ( __ICCARM__ ) 171 | /* ICCARM Compiler 172 | --------------- 173 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 174 | */ 175 | #define __RAM_FUNC __ramfunc 176 | 177 | #elif defined ( __GNUC__ ) 178 | /* GNU Compiler 179 | ------------ 180 | RAM functions are defined using a specific toolchain attribute 181 | "__attribute__((section(".RamFunc")))". 182 | */ 183 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 184 | 185 | #endif 186 | 187 | /** 188 | * @brief __NOINLINE definition 189 | */ 190 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 191 | /* ARM V4/V5 and V6 & GNU Compiler 192 | ------------------------------- 193 | */ 194 | #define __NOINLINE __attribute__ ( (noinline) ) 195 | 196 | #elif defined ( __ICCARM__ ) 197 | /* ICCARM Compiler 198 | --------------- 199 | */ 200 | #define __NOINLINE _Pragma("optimize = no_inline") 201 | 202 | #endif 203 | 204 | #ifdef __cplusplus 205 | } 206 | #endif 207 | 208 | #endif /* ___STM32F1xx_HAL_DEF */ 209 | 210 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F1xx_HAL_FLASH_H 22 | #define __STM32F1xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_Private_Constants 40 | * @{ 41 | */ 42 | #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @addtogroup FLASH_Private_Macros 48 | * @{ 49 | */ 50 | 51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 54 | 55 | #if defined(FLASH_ACR_LATENCY) 56 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 57 | ((__LATENCY__) == FLASH_LATENCY_1) || \ 58 | ((__LATENCY__) == FLASH_LATENCY_2)) 59 | 60 | #else 61 | #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) 62 | #endif /* FLASH_ACR_LATENCY */ 63 | /** 64 | * @} 65 | */ 66 | 67 | /* Exported types ------------------------------------------------------------*/ 68 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @brief FLASH Procedure structure definition 74 | */ 75 | typedef enum 76 | { 77 | FLASH_PROC_NONE = 0U, 78 | FLASH_PROC_PAGEERASE = 1U, 79 | FLASH_PROC_MASSERASE = 2U, 80 | FLASH_PROC_PROGRAMHALFWORD = 3U, 81 | FLASH_PROC_PROGRAMWORD = 4U, 82 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 83 | } FLASH_ProcedureTypeDef; 84 | 85 | /** 86 | * @brief FLASH handle Structure definition 87 | */ 88 | typedef struct 89 | { 90 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 91 | 92 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 93 | 94 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 95 | 96 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 97 | 98 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 99 | 100 | __IO uint32_t ErrorCode; /*!< FLASH error code 101 | This parameter can be a value of @ref FLASH_Error_Codes */ 102 | } FLASH_ProcessTypeDef; 103 | 104 | /** 105 | * @} 106 | */ 107 | 108 | /* Exported constants --------------------------------------------------------*/ 109 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 110 | * @{ 111 | */ 112 | 113 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 114 | * @{ 115 | */ 116 | 117 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 118 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 119 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 120 | #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ 121 | 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @defgroup FLASH_Type_Program FLASH Type Program 127 | * @{ 128 | */ 129 | #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!ACR |= FLASH_ACR_HLFCYA) 183 | 184 | /** 185 | * @brief Disable the FLASH half cycle access. 186 | * @note half cycle access can only be used with a low-frequency clock of less than 187 | 8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 188 | * @retval None 189 | */ 190 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) 191 | 192 | /** 193 | * @} 194 | */ 195 | 196 | #if defined(FLASH_ACR_LATENCY) 197 | /** @defgroup FLASH_EM_Latency FLASH Latency 198 | * @brief macros to handle FLASH Latency 199 | * @{ 200 | */ 201 | 202 | /** 203 | * @brief Set the FLASH Latency. 204 | * @param __LATENCY__ FLASH Latency 205 | * The value of this parameter depend on device used within the same series 206 | * @retval None 207 | */ 208 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 209 | 210 | 211 | /** 212 | * @brief Get the FLASH Latency. 213 | * @retval FLASH Latency 214 | * The value of this parameter depend on device used within the same series 215 | */ 216 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 217 | 218 | /** 219 | * @} 220 | */ 221 | 222 | #endif /* FLASH_ACR_LATENCY */ 223 | /** @defgroup FLASH_Prefetch FLASH Prefetch 224 | * @brief macros to handle FLASH Prefetch buffer 225 | * @{ 226 | */ 227 | /** 228 | * @brief Enable the FLASH prefetch buffer. 229 | * @retval None 230 | */ 231 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 232 | 233 | /** 234 | * @brief Disable the FLASH prefetch buffer. 235 | * @retval None 236 | */ 237 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 238 | 239 | /** 240 | * @} 241 | */ 242 | 243 | /** 244 | * @} 245 | */ 246 | 247 | /* Include FLASH HAL Extended module */ 248 | #include "stm32f1xx_hal_flash_ex.h" 249 | 250 | /* Exported functions --------------------------------------------------------*/ 251 | /** @addtogroup FLASH_Exported_Functions 252 | * @{ 253 | */ 254 | 255 | /** @addtogroup FLASH_Exported_Functions_Group1 256 | * @{ 257 | */ 258 | /* IO operation functions *****************************************************/ 259 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 260 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 261 | 262 | /* FLASH IRQ handler function */ 263 | void HAL_FLASH_IRQHandler(void); 264 | /* Callbacks in non blocking modes */ 265 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 266 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 267 | 268 | /** 269 | * @} 270 | */ 271 | 272 | /** @addtogroup FLASH_Exported_Functions_Group2 273 | * @{ 274 | */ 275 | /* Peripheral Control functions ***********************************************/ 276 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 277 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 278 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 279 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 280 | void HAL_FLASH_OB_Launch(void); 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | /** @addtogroup FLASH_Exported_Functions_Group3 287 | * @{ 288 | */ 289 | /* Peripheral State and Error functions ***************************************/ 290 | uint32_t HAL_FLASH_GetError(void); 291 | 292 | /** 293 | * @} 294 | */ 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /* Private function -------------------------------------------------*/ 301 | /** @addtogroup FLASH_Private_Functions 302 | * @{ 303 | */ 304 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 305 | #if defined(FLASH_BANK2_END) 306 | HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); 307 | #endif /* FLASH_BANK2_END */ 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /** 314 | * @} 315 | */ 316 | 317 | /** 318 | * @} 319 | */ 320 | 321 | #ifdef __cplusplus 322 | } 323 | #endif 324 | 325 | #endif /* __STM32F1xx_HAL_FLASH_H */ 326 | 327 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 328 | 329 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_tim_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of TIM HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F1xx_HAL_TIM_EX_H 22 | #define STM32F1xx_HAL_TIM_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f1xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F1xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup TIMEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief TIM Hall sensor Configuration Structure definition 46 | */ 47 | 48 | typedef struct 49 | { 50 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 51 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 52 | 53 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 54 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 55 | 56 | uint32_t IC1Filter; /*!< Specifies the input capture filter. 57 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 58 | 59 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 60 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 61 | } TIM_HallSensor_InitTypeDef; 62 | /** 63 | * @} 64 | */ 65 | /* End of exported types -----------------------------------------------------*/ 66 | 67 | /* Exported constants --------------------------------------------------------*/ 68 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 69 | * @{ 70 | */ 71 | 72 | /** @defgroup TIMEx_Remap TIM Extended Remapping 73 | * @{ 74 | */ 75 | /** 76 | * @} 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | /* End of exported constants -------------------------------------------------*/ 83 | 84 | /* Exported macro ------------------------------------------------------------*/ 85 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | /* End of exported macro -----------------------------------------------------*/ 93 | 94 | /* Private macro -------------------------------------------------------------*/ 95 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | /* End of private macro ------------------------------------------------------*/ 103 | 104 | /* Exported functions --------------------------------------------------------*/ 105 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 106 | * @{ 107 | */ 108 | 109 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 110 | * @brief Timer Hall Sensor functions 111 | * @{ 112 | */ 113 | /* Timer Hall Sensor functions **********************************************/ 114 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); 115 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 116 | 117 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 118 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 119 | 120 | /* Blocking mode: Polling */ 121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 122 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 123 | /* Non-Blocking mode: Interrupt */ 124 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 125 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 126 | /* Non-Blocking mode: DMA */ 127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 128 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 129 | /** 130 | * @} 131 | */ 132 | 133 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 134 | * @brief Timer Complementary Output Compare functions 135 | * @{ 136 | */ 137 | /* Timer Complementary Output Compare functions *****************************/ 138 | /* Blocking mode: Polling */ 139 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 140 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 141 | 142 | /* Non-Blocking mode: Interrupt */ 143 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 144 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 145 | 146 | /* Non-Blocking mode: DMA */ 147 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 148 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 154 | * @brief Timer Complementary PWM functions 155 | * @{ 156 | */ 157 | /* Timer Complementary PWM functions ****************************************/ 158 | /* Blocking mode: Polling */ 159 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 160 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 161 | 162 | /* Non-Blocking mode: Interrupt */ 163 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 164 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 165 | /* Non-Blocking mode: DMA */ 166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 167 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 173 | * @brief Timer Complementary One Pulse functions 174 | * @{ 175 | */ 176 | /* Timer Complementary One Pulse functions **********************************/ 177 | /* Blocking mode: Polling */ 178 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 179 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 180 | 181 | /* Non-Blocking mode: Interrupt */ 182 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 183 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 184 | /** 185 | * @} 186 | */ 187 | 188 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 189 | * @brief Peripheral Control functions 190 | * @{ 191 | */ 192 | /* Extended Control functions ************************************************/ 193 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 194 | uint32_t CommutationSource); 195 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 196 | uint32_t CommutationSource); 197 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 198 | uint32_t CommutationSource); 199 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 200 | TIM_MasterConfigTypeDef *sMasterConfig); 201 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 202 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 203 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 204 | /** 205 | * @} 206 | */ 207 | 208 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 209 | * @brief Extended Callbacks functions 210 | * @{ 211 | */ 212 | /* Extended Callback **********************************************************/ 213 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); 214 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); 215 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 216 | /** 217 | * @} 218 | */ 219 | 220 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 221 | * @brief Extended Peripheral State functions 222 | * @{ 223 | */ 224 | /* Extended Peripheral State functions ***************************************/ 225 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); 226 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); 227 | /** 228 | * @} 229 | */ 230 | 231 | /** 232 | * @} 233 | */ 234 | /* End of exported functions -------------------------------------------------*/ 235 | 236 | /* Private functions----------------------------------------------------------*/ 237 | /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions 238 | * @{ 239 | */ 240 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 241 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); 242 | /** 243 | * @} 244 | */ 245 | /* End of private functions --------------------------------------------------*/ 246 | 247 | /** 248 | * @} 249 | */ 250 | 251 | /** 252 | * @} 253 | */ 254 | 255 | #ifdef __cplusplus 256 | } 257 | #endif 258 | 259 | 260 | #endif /* STM32F1xx_HAL_TIM_EX_H */ 261 | 262 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 263 | -------------------------------------------------------------------------------- /Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f1xx_hal_gpio_ex.c 4 | * @author MCD Application Team 5 | * @brief GPIO Extension HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### GPIO Peripheral extension features ##### 13 | ============================================================================== 14 | [..] GPIO module on STM32F1 family, manage also the AFIO register: 15 | (+) Possibility to use the EVENTOUT Cortex feature 16 | 17 | ##### How to use this driver ##### 18 | ============================================================================== 19 | [..] This driver provides functions to use EVENTOUT Cortex feature 20 | (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 21 | (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 22 | (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 23 | 24 | @endverbatim 25 | ****************************************************************************** 26 | * @attention 27 | * 28 | *

© Copyright (c) 2016 STMicroelectronics. 29 | * All rights reserved.

30 | * 31 | * This software component is licensed by ST under BSD 3-Clause license, 32 | * the "License"; You may not use this file except in compliance with the 33 | * License. You may obtain a copy of the License at: 34 | * opensource.org/licenses/BSD-3-Clause 35 | * 36 | ****************************************************************************** 37 | */ 38 | 39 | /* Includes ------------------------------------------------------------------*/ 40 | #include "stm32f1xx_hal.h" 41 | 42 | /** @addtogroup STM32F1xx_HAL_Driver 43 | * @{ 44 | */ 45 | 46 | /** @defgroup GPIOEx GPIOEx 47 | * @brief GPIO HAL module driver 48 | * @{ 49 | */ 50 | 51 | #ifdef HAL_GPIO_MODULE_ENABLED 52 | 53 | /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions 54 | * @{ 55 | */ 56 | 57 | /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions 58 | * @brief Extended features functions 59 | * 60 | @verbatim 61 | ============================================================================== 62 | ##### Extended features functions ##### 63 | ============================================================================== 64 | [..] This section provides functions allowing to: 65 | (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() 66 | (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() 67 | (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() 68 | 69 | @endverbatim 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. 75 | * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. 76 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. 77 | * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. 78 | * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. 79 | * @retval None 80 | */ 81 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) 82 | { 83 | /* Verify the parameters */ 84 | assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); 85 | assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); 86 | 87 | /* Apply the new configuration */ 88 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); 89 | } 90 | 91 | /** 92 | * @brief Enables the Event Output. 93 | * @retval None 94 | */ 95 | void HAL_GPIOEx_EnableEventout(void) 96 | { 97 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 98 | } 99 | 100 | /** 101 | * @brief Disables the Event Output. 102 | * @retval None 103 | */ 104 | void HAL_GPIOEx_DisableEventout(void) 105 | { 106 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 107 | } 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | #endif /* HAL_GPIO_MODULE_ENABLED */ 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** 124 | * @} 125 | */ 126 | 127 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 128 | -------------------------------------------------------------------------------- /Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2019 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f1xx_hal.h" 32 | 33 | /* Private includes ----------------------------------------------------------*/ 34 | /* USER CODE BEGIN Includes */ 35 | 36 | /* USER CODE END Includes */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* USER CODE BEGIN ET */ 40 | 41 | /* USER CODE END ET */ 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | /* USER CODE BEGIN EC */ 45 | 46 | /* USER CODE END EC */ 47 | 48 | /* Exported macro ------------------------------------------------------------*/ 49 | /* USER CODE BEGIN EM */ 50 | 51 | /* USER CODE END EM */ 52 | 53 | /* Exported functions prototypes ---------------------------------------------*/ 54 | void Error_Handler(void); 55 | 56 | /* USER CODE BEGIN EFP */ 57 | 58 | /* USER CODE END EFP */ 59 | 60 | /* Private defines -----------------------------------------------------------*/ 61 | /* USER CODE BEGIN Private defines */ 62 | 63 | /* USER CODE END Private defines */ 64 | 65 | #ifdef __cplusplus 66 | } 67 | #endif 68 | 69 | #endif /* __MAIN_H */ 70 | 71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 72 | -------------------------------------------------------------------------------- /Inc/stm32f1xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2019 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F1xx_IT_H 23 | #define __STM32F1xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | /* USER CODE BEGIN EFP */ 60 | 61 | /* USER CODE END EFP */ 62 | 63 | #ifdef __cplusplus 64 | } 65 | #endif 66 | 67 | #endif /* __STM32F1xx_IT_H */ 68 | 69 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 70 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Andrey Belykh 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Main/Display/VideoSettings.h: -------------------------------------------------------------------------------- 1 | #ifndef _VIDEOSETTINGS_H 2 | #define _VIDEOSETTINGS_H 3 | 4 | #include 5 | #include "timing.h" 6 | 7 | namespace Vga 8 | { 9 | 10 | class VideoSettings 11 | { 12 | public: 13 | const Vga::Timing* Timing; 14 | 15 | // text resolution 16 | uint8_t TextColumns; 17 | uint8_t TextRows; 18 | 19 | // video memory 20 | uint16_t* ScreenCharacters; 21 | uint32_t* ScreenAttributes; 22 | }; 23 | 24 | } 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /Main/Display/font8x16.h: -------------------------------------------------------------------------------- 1 | #ifndef FONT8X16_H 2 | #define FONT8X16_H 3 | 4 | extern const unsigned char font8x16[]; 5 | 6 | #endif 7 | -------------------------------------------------------------------------------- /Main/Display/font8x8.h: -------------------------------------------------------------------------------- 1 | #ifndef FONT8X8_H 2 | #define FONT8X8_H 3 | 4 | extern const unsigned char font8x8[]; 5 | 6 | #endif -------------------------------------------------------------------------------- /Main/Display/timing.cpp: -------------------------------------------------------------------------------- 1 | #include "timing.h" 2 | 3 | namespace Vga 4 | { 5 | 6 | Timing const timing_640x480_60hz = 7 | { 8 | .pixel_frequency_mhz = 25.175, 9 | 10 | .horizPixels = 640, 11 | .horizSyncPolarity = Timing::Polarity::positive, 12 | .horizWholeLine = 800, 13 | .horizSyncPulse = 96, 14 | .horizStartDraw = 96 - 16, 15 | .horizLead = 0, 16 | 17 | .verticalPixels = 480, 18 | .verticalSyncPolarity = Timing::Polarity::positive, 19 | .verticalWholeFrame = 525, 20 | .verticalSyncPulse = 2, 21 | .verticalStartLine = 35 22 | }; 23 | 24 | Timing const timing_640x480_60_01hz = 25 | { 26 | .pixel_frequency_mhz = 24.00, 27 | 28 | .horizPixels = 640, 29 | .horizSyncPolarity = Timing::Polarity::negative, 30 | .horizWholeLine = 792, 31 | .horizSyncPulse = 88, 32 | .horizStartDraw = 140, 33 | .horizLead = 0, 34 | 35 | .verticalPixels = 480, 36 | .verticalSyncPolarity = Timing::Polarity::negative, 37 | .verticalWholeFrame = 505, 38 | .verticalSyncPulse = 5, 39 | .verticalStartLine = 38 40 | }; 41 | 42 | Timing const timing_800x600_56hz = 43 | { 44 | .pixel_frequency_mhz = 36.0, 45 | 46 | .horizPixels = 800, 47 | .horizSyncPolarity = Timing::Polarity::positive, 48 | .horizWholeLine = 1024, 49 | .horizSyncPulse = 72, 50 | .horizStartDraw = 72 - 24, 51 | .horizLead = -120, 52 | 53 | .verticalPixels = 600, 54 | .verticalSyncPolarity = Timing::Polarity::positive, 55 | .verticalWholeFrame = 625, 56 | .verticalSyncPulse = 2, 57 | .verticalStartLine = 25 58 | }; 59 | 60 | } // namespace Vga 61 | -------------------------------------------------------------------------------- /Main/Display/timing.h: -------------------------------------------------------------------------------- 1 | #ifndef VGA_TIMING_H 2 | #define VGA_TIMING_H 3 | 4 | #include "stdint.h" 5 | 6 | namespace Vga 7 | { 8 | 9 | /* 10 | * Describes the horizontal and vertical timing for a display mode. 11 | */ 12 | struct Timing 13 | { 14 | enum struct Polarity 15 | { 16 | positive = 0, 17 | negative = 1, 18 | }; 19 | 20 | double pixel_frequency_mhz; // Pixel frequency in MHz 21 | 22 | /* 23 | * Horizontal timing, expressed in pixels. 24 | */ 25 | uint16_t horizPixels; 26 | Polarity horizSyncPolarity; 27 | uint16_t horizWholeLine; 28 | uint16_t horizSyncPulse; 29 | uint16_t horizStartDraw; 30 | int16_t horizLead; // manual adjustment as needed 31 | 32 | /* 33 | * Vertical timing, expressed in lines. 34 | */ 35 | uint16_t verticalPixels; 36 | Polarity verticalSyncPolarity; 37 | uint16_t verticalWholeFrame; 38 | uint16_t verticalSyncPulse; 39 | uint16_t verticalStartLine; 40 | }; 41 | 42 | /* 43 | * Canned timings for common modes. 44 | */ 45 | extern Timing const timing_640x480_60hz; 46 | extern Timing const timing_640x480_60_01hz; 47 | extern Timing const timing_800x600_56hz; 48 | 49 | } // namespace Vga 50 | 51 | #endif // VGA_TIMING_H 52 | -------------------------------------------------------------------------------- /Main/Display/vgaCore.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "startup.h" 4 | #include "vgacore.h" 5 | #include "timing.h" 6 | #include "vgadraw.h" 7 | #include "vgaText.h" 8 | 9 | namespace Vga 10 | { 11 | const VideoSettings* settings; 12 | uint16_t* ScreenCharacters; 13 | uint32_t* ScreenAttributes; 14 | 15 | // Attribute in RAM vs. flash makes a big difference 16 | uint8_t StandardAttribute[128]; 17 | static void InitAttribute(uint8_t* attribute, uint8_t backColor, uint8_t foreColor); 18 | } 19 | 20 | static TIM_HandleTypeDef htim2; 21 | static TIM_HandleTypeDef htim3; 22 | static TIM_HandleTypeDef htim4; 23 | 24 | #define REPEAT_LINES 1 25 | static volatile int vline = 0; /* The current line being drawn */ 26 | static volatile int vflag = 0; /* When 1, can draw on the screen */ 27 | static uint8_t *GPIO_ODR; 28 | 29 | static uint16_t verticalPixelCount; 30 | static uint16_t verticalOffset; 31 | 32 | static void InitHSync(Vga::Timing::Polarity polarity, int wholeLine, int syncPulse, int startDraw); 33 | static void InitVSync(Vga::Timing::Polarity polarity, int wholeFrame, int syncPulse, int startDraw); 34 | 35 | #define __irq extern "C" 36 | 37 | void Vga::InitVga(VideoSettings* videoSettings) 38 | { 39 | settings = videoSettings; 40 | const Timing* timing = videoSettings->Timing; 41 | ScreenCharacters = videoSettings->ScreenCharacters; 42 | ScreenAttributes = videoSettings->ScreenAttributes; 43 | InitAttribute(StandardAttribute, BACK_COLOR, FORE_COLOR); 44 | ClearScreen(); 45 | 46 | GPIO_InitTypeDef gpioInit; 47 | 48 | __HAL_RCC_GPIOA_CLK_ENABLE(); 49 | __HAL_RCC_GPIOB_CLK_ENABLE(); 50 | 51 | // HSync on PB0 and VSync on PB6 52 | gpioInit.Pin = GPIO_PIN_0 | GPIO_PIN_6; 53 | gpioInit.Mode = GPIO_MODE_AF_PP; 54 | gpioInit.Pull = GPIO_PULLUP; 55 | gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; 56 | HAL_GPIO_Init(GPIOB, &gpioInit); 57 | 58 | #ifdef BOARD2 59 | // Set PB8..PB9, PB12..PB15 to OUTPUT with high speed 60 | gpioInit.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; 61 | gpioInit.Mode = GPIO_MODE_OUTPUT_PP; 62 | gpioInit.Pull = GPIO_PULLUP; 63 | gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; 64 | HAL_GPIO_Init(GPIOB, &gpioInit); 65 | 66 | GPIO_ODR = (uint8_t*)&GPIOB->ODR + 1; 67 | #else 68 | // Set PA0..PA5 to OUTPUT with high speed 69 | gpioInit.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5; 70 | gpioInit.Mode = GPIO_MODE_OUTPUT_PP; 71 | gpioInit.Pull = GPIO_PULLUP; 72 | gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; 73 | HAL_GPIO_Init(GPIOA, &gpioInit); 74 | 75 | GPIO_ODR = (uint8_t*)&GPIOA->ODR; 76 | #endif 77 | 78 | double realPixelsPerPixel = timing->pixel_frequency_mhz / 18; 79 | uint16_t usedHorizontalPixels = HSIZE_CHARS * 8 * realPixelsPerPixel; 80 | if (usedHorizontalPixels > timing->horizPixels * realPixelsPerPixel) 81 | { 82 | usedHorizontalPixels = timing->horizPixels * realPixelsPerPixel; 83 | } 84 | uint16_t horizontalOffset = (timing->horizPixels - usedHorizontalPixels) / 2; 85 | 86 | uint16_t usedVerticalPixels = VSIZE_CHARS * 16 * REPEAT_LINES; 87 | if (usedVerticalPixels > timing->verticalPixels) 88 | { 89 | usedVerticalPixels = timing->verticalPixels; 90 | } 91 | verticalPixelCount = usedVerticalPixels / REPEAT_LINES; 92 | verticalOffset = (timing->verticalPixels - usedVerticalPixels) / 2; 93 | 94 | double factor = HAL_RCC_GetHCLKFreq() / 1000000.0 / timing->pixel_frequency_mhz; 95 | int wholeLine = factor * timing->horizWholeLine; 96 | int syncPulse = factor * timing->horizSyncPulse; 97 | int startDraw = factor * timing->horizStartDraw - timing->horizLead; 98 | InitHSync(timing->horizSyncPolarity, wholeLine, syncPulse, startDraw + horizontalOffset); 99 | 100 | InitVSync(timing->verticalSyncPolarity, 101 | timing->verticalWholeFrame, 102 | timing->verticalSyncPulse, 103 | timing->verticalStartLine); 104 | 105 | vline = 0; 106 | } 107 | 108 | void Vga::ClearScreen() 109 | { 110 | for (int y = 0; y < VSIZE_CHARS; y++) 111 | { 112 | for (int x = 0; x < HSIZE_CHARS; x++) 113 | { 114 | Vga::PrintChar(x, y, ' ', (uint32_t)StandardAttribute); 115 | } 116 | } 117 | } 118 | 119 | //***************************************************************************** 120 | // This irq is generated slightly before TIM3_IRQHandler 121 | //***************************************************************************** 122 | __irq void TIM2_IRQHandler() 123 | { 124 | __HAL_TIM_CLEAR_IT(&htim2, TIM_FLAG_CC2); 125 | 126 | if (vflag) 127 | { 128 | // Wait for interrupt 129 | __asm__ volatile("wfi \n\t" :::); 130 | } 131 | } 132 | 133 | //***************************************************************************** 134 | // This irq is generated at the end of the horizontal back porch. 135 | //***************************************************************************** 136 | __irq void TIM3_IRQHandler() 137 | { 138 | __HAL_TIM_CLEAR_IT(&htim3, TIM_FLAG_CC2); 139 | 140 | if (vflag) 141 | { 142 | int offset = (vline >> 4) * HSIZE_CHARS; 143 | vgaDraw((uint8_t*)Vga::font + (vline & 0x0F), 144 | &Vga::ScreenCharacters[offset], 145 | &Vga::ScreenAttributes[offset], 146 | GPIO_ODR); 147 | 148 | vline++; 149 | if (vline == verticalPixelCount) 150 | { 151 | vline = vflag = 0; 152 | } 153 | } 154 | 155 | // Triggers PendSV interrupt 156 | SCB->ICSR = SCB->ICSR | SCB_ICSR_PENDSVSET_Msk; 157 | } 158 | 159 | //***************************************************************************** 160 | // This IRQ is generated at the end of the vertical back porch. 161 | //***************************************************************************** 162 | __irq void TIM4_IRQHandler() 163 | { 164 | __HAL_TIM_CLEAR_IT(&htim4, TIM_FLAG_CC4); 165 | 166 | vflag = 1; 167 | vline = 0; 168 | } 169 | 170 | static void InitVSync( 171 | Vga::Timing::Polarity polarity, 172 | int wholeFrame, 173 | int syncPulse, 174 | int startDraw) 175 | { 176 | __HAL_RCC_TIM4_CLK_ENABLE(); 177 | 178 | htim4.Instance = TIM4; 179 | htim4.Init.Prescaler = 0; 180 | htim4.Init.Period = wholeFrame - 1; 181 | htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 182 | htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 183 | htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 184 | HAL_TIM_Base_Init(&htim4); 185 | 186 | // Slave mode Gated, triggered by TIM3 187 | TIM_SlaveConfigTypeDef sSlaveConfig; 188 | sSlaveConfig.SlaveMode = TIM_SLAVEMODE_GATED; 189 | sSlaveConfig.InputTrigger = TIM_TS_ITR2; 190 | sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; 191 | sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; 192 | sSlaveConfig.TriggerFilter = 0; 193 | HAL_TIM_SlaveConfigSynchro(&htim4, &sSlaveConfig); 194 | 195 | HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0); 196 | HAL_NVIC_EnableIRQ(TIM4_IRQn); 197 | 198 | TIM_OC_InitTypeDef sConfigOC; 199 | 200 | // VSync on pin PB6 201 | sConfigOC.OCMode = polarity == Vga::Timing::Polarity::negative ? TIM_OCMODE_PWM2 : TIM_OCMODE_PWM1; 202 | sConfigOC.Pulse = syncPulse; 203 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 204 | sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 205 | sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 206 | HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1); 207 | TIM_CCxChannelCmd(htim4.Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 208 | 209 | sConfigOC.OCMode = TIM_OCMODE_INACTIVE; 210 | sConfigOC.Pulse = startDraw; 211 | HAL_TIM_OC_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4); 212 | __HAL_TIM_ENABLE_IT(&htim4, TIM_IT_CC4); 213 | 214 | if (IS_TIM_BREAK_INSTANCE(htim4.Instance) != RESET) 215 | { 216 | __HAL_TIM_MOE_ENABLE(&htim4); 217 | } 218 | 219 | __HAL_TIM_ENABLE(&htim4); 220 | } 221 | 222 | static void InitHSync( 223 | Vga::Timing::Polarity polarity, 224 | int wholeLine, 225 | int syncPulse, 226 | int startDraw) 227 | { 228 | TIM_OC_InitTypeDef sConfigOC; 229 | TIM_MasterConfigTypeDef sMasterConfig; 230 | 231 | __HAL_RCC_TIM2_CLK_ENABLE(); 232 | 233 | htim2.Instance = TIM2; 234 | htim2.Init.Prescaler = 0; 235 | htim2.Init.Period = wholeLine - 1; 236 | htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 237 | htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 238 | htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 239 | HAL_TIM_Base_Init(&htim2); 240 | 241 | // Master mode 242 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 243 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_ENABLE; 244 | HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig); 245 | 246 | HAL_NVIC_SetPriority(TIM2_IRQn, 1, 1); 247 | HAL_NVIC_EnableIRQ(TIM2_IRQn); 248 | 249 | sConfigOC.OCMode = TIM_OCMODE_INACTIVE; 250 | sConfigOC.Pulse = startDraw - 20 - 1; 251 | HAL_TIM_OC_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2); 252 | __HAL_TIM_ENABLE_IT(&htim2, TIM_IT_CC2); 253 | 254 | if (IS_TIM_BREAK_INSTANCE(htim2.Instance) != RESET) 255 | { 256 | __HAL_TIM_MOE_ENABLE(&htim2); 257 | } 258 | 259 | __HAL_RCC_TIM3_CLK_ENABLE(); 260 | 261 | htim3.Instance = TIM3; 262 | htim3.Init.Prescaler = 0; 263 | htim3.Init.Period = wholeLine - 1; 264 | htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 265 | htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 266 | htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 267 | HAL_TIM_Base_Init(&htim3); 268 | 269 | // Master mode 270 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 271 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 272 | HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig); 273 | 274 | // Slave mode Trigger, triggered by TIM2 275 | TIM_SlaveConfigTypeDef sSlaveConfig; 276 | sSlaveConfig.SlaveMode = TIM_SLAVEMODE_TRIGGER; 277 | sSlaveConfig.InputTrigger = TIM_TS_ITR1; 278 | sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; 279 | sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; 280 | sSlaveConfig.TriggerFilter = 0; 281 | HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig); 282 | 283 | HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 284 | HAL_NVIC_EnableIRQ(TIM3_IRQn); 285 | 286 | // HSync on pin PB0 287 | sConfigOC.OCMode = polarity == Vga::Timing::Polarity::negative ? TIM_OCMODE_PWM2 : TIM_OCMODE_PWM1; 288 | sConfigOC.Pulse = syncPulse; 289 | sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 290 | sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW; 291 | sConfigOC.OCFastMode = TIM_OCFAST_ENABLE; 292 | HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3); 293 | TIM_CCxChannelCmd(htim3.Instance, TIM_CHANNEL_3, TIM_CCx_ENABLE); 294 | 295 | sConfigOC.OCMode = TIM_OCMODE_INACTIVE; 296 | sConfigOC.Pulse = startDraw - 1; 297 | HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2); 298 | __HAL_TIM_ENABLE_IT(&htim3, TIM_IT_CC2); 299 | 300 | if (IS_TIM_BREAK_INSTANCE(htim3.Instance) != RESET) 301 | { 302 | __HAL_TIM_MOE_ENABLE(&htim3); 303 | } 304 | 305 | __HAL_TIM_SET_COUNTER(&htim2, 0); 306 | __HAL_TIM_SET_COUNTER(&htim3, 0); 307 | 308 | // Starts TIM3 as well 309 | __HAL_TIM_ENABLE(&htim2); 310 | //__HAL_TIM_ENABLE(&htim3); 311 | } 312 | 313 | void Vga::InitAttribute(uint8_t* attribute, uint8_t backColor, uint8_t foreColor) 314 | { 315 | for (uint8_t i = 0; i < 16; i++) 316 | { 317 | uint8_t value = i; 318 | for (uint8_t bit = 0; bit < 4; bit++) 319 | { 320 | uint8_t index = (i << 2) + bit; 321 | 322 | // Normal 323 | attribute[index] = (value & 0x08) ? foreColor : backColor; 324 | 325 | // Inverted 326 | attribute[index + 16 * 4] = (value & 0x08) ? backColor : foreColor; 327 | 328 | value <<= 1; 329 | } 330 | } 331 | } 332 | -------------------------------------------------------------------------------- /Main/Display/vgaCore.h: -------------------------------------------------------------------------------- 1 | #ifndef _VGACORE_H_ 2 | #define _VGACORE_H_ 3 | 4 | #include 5 | #include "videosettings.h" 6 | 7 | /* 8 | Pinout 9 | ====== 10 | 11 | PB6 - VSync 12 | PB0 - HSync 13 | 14 | PA0, PA1 - Red 15 | PA2, PA3 - Green 16 | PA4, PA5 - Blue 17 | 18 | Resistors 19 | ========= 20 | 680 Ohm on PA0, PA2, PA4 (0.33 V) 21 | 470 Ohm on PA1, PA2, PA3 22 | ==== 23 | Parallel: 278 Ohm (0.7 V) 24 | 25 | */ 26 | 27 | namespace Vga 28 | { 29 | extern const Vga::VideoSettings* settings; 30 | extern uint16_t* ScreenCharacters; 31 | extern uint32_t* ScreenAttributes; 32 | extern uint16_t horizontalPixelCount; 33 | extern uint8_t StandardAttribute[128]; 34 | 35 | void InitVga(VideoSettings* videoSettings); 36 | void ClearScreen(); 37 | } 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /Main/Display/vgaDraw.S: -------------------------------------------------------------------------------- 1 | #include "settings.h" 2 | 3 | .syntax unified 4 | 5 | @ Arguments: 6 | @ r0 uint8_t* font 7 | @ r1 uint8_t* characters 8 | @ r2 uint32_t* attributes 9 | @ r3 uint8_t* dest 10 | .section .text.vgaDraw,"ax",%progbits 11 | @.section .ramcode,ax,%progbits 12 | .balign 4 13 | .global vgaDraw 14 | .thumb_func 15 | vgaDraw: 16 | @ parameters 17 | fnt .req r0 18 | chr .req r1 19 | col .req r2 20 | odr .req r3 21 | 22 | push {r4, r5, r6, r7, r8} @ 6 23 | 24 | @ prepare 25 | ldrh r5, [chr], #2 @ 2* r5 = {character} 26 | ldr r6, [col], #4 @ 1* r6 = {character attribute} 27 | ldrb r5, [fnt, r5, LSL #3] @ 1* r5 = {character pixels} 28 | lsr r4, r5, #2 @ 1 r4 = {character pixels} >> 2 29 | and r4, r4, #60 @ 1 r4 &= 0B00111100 30 | 31 | .rept HSIZE_CHARS 32 | 33 | @ first 4 pixels, each pixel one byte (r7) 34 | 35 | ldr r7, [r6, r4] @ 2* r7 = {4 bytes for 1st part of character} 36 | strb r7, [odr] @ 2 37 | 38 | ror r7, #8 @ 1 39 | and r4, r5, #15 @ 1 r4 = {character pixels} & 0B00001111 40 | strb r7, [odr] @ 2 41 | 42 | ror r7, #8 @ 1 43 | ldr r8, [r6, r4, LSL #2] @ 1* r8 = {4 bytes for 2nd part of character} 44 | strb r7, [odr] @ 2 45 | 46 | ror r7, #8 @ 1 47 | ldr r6, [col], #4 @ 1* r6 = {character attribute} 48 | strb r7, [odr] @ 2 49 | 50 | @ next 4 pixels, each pixel one byte (r8) 51 | 52 | nop @ 1 53 | ldrh r5, [chr], #2 @ 1* r5 = {character} 54 | strb r8, [odr] @ 2 55 | 56 | ror r8, #8 @ 1 57 | ldrb r5, [fnt, r5, LSL #3] @ 1* r5 = {character pixels} 58 | strb r8, [odr] @ 2 59 | 60 | ror r8, #8 @ 1 61 | lsr r4, r5, #2 @ 1 r4 = {character pixels} >> 2 62 | strb r8, [odr] @ 2 63 | 64 | ror r8, #8 @ 1 65 | and r4, r4, #60 @ 1 r4 &= 0B00111100 66 | strb r8, [odr] @ 2 67 | 68 | .endr 69 | 70 | @ 0 at the end 71 | mov r4, #0 @ 1 72 | nop @ 1 73 | strb r4, [odr] @ 2 74 | 75 | pop {r4, r5, r6, r7, r8} @ 6 76 | bx lr 77 | -------------------------------------------------------------------------------- /Main/Display/vgaDraw.h: -------------------------------------------------------------------------------- 1 | #ifndef VGA_DRAW_H 2 | #define VGA_DRAW_H 3 | 4 | #include 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | void vgaDraw(uint8_t* font, uint16_t* characters, uint32_t* attributes, uint8_t* dest); 11 | 12 | #ifdef __cplusplus 13 | } 14 | #endif 15 | 16 | #endif // DRAW4_H 17 | -------------------------------------------------------------------------------- /Main/Display/vgaText.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/Main/Display/vgaText.cpp -------------------------------------------------------------------------------- /Main/Display/vgaText.h: -------------------------------------------------------------------------------- 1 | #ifndef _VGATEXT_H_ 2 | #define _VGATEXT_H_ 3 | 4 | #include "vgaCore.h" 5 | 6 | namespace Vga 7 | { 8 | extern const uint8_t* font; 9 | 10 | extern uint8_t cursor_x; 11 | extern uint8_t cursor_y; 12 | 13 | void InitVgaText(const uint8_t* f); 14 | 15 | void Print(char* str); 16 | void Print(char* str, uint32_t attribute); 17 | void Print(const char* str); 18 | void Print(const char* str, uint32_t attribute); 19 | void PrintUtf8(const char* str); 20 | void PrintChar(uint16_t x, uint16_t y, uint8_t ch); 21 | void PrintChar(uint16_t x, uint16_t y, uint8_t ch, uint32_t attribute); 22 | void SetAttribute(uint16_t x, uint16_t y, uint32_t attribute); 23 | 24 | void SetCursorPosition(uint8_t x, uint8_t y); 25 | void ShowCursor(); 26 | void HideCursor(); 27 | } 28 | 29 | #endif 30 | -------------------------------------------------------------------------------- /Main/Keyboard/Queue.c: -------------------------------------------------------------------------------- 1 | #include "queue.h" 2 | 3 | #define QUEUE_SIZE (QUEUE_ELEMENTS + 1) 4 | 5 | static int Queue[QUEUE_SIZE]; 6 | static uint8_t QueueIn, QueueOut; 7 | 8 | void QueueInit() 9 | { 10 | QueueIn = QueueOut = 0; 11 | } 12 | 13 | int QueuePut(int32_t element) 14 | { 15 | if (QueueIn == ((QueueOut - 1 + QUEUE_SIZE) % QUEUE_SIZE)) 16 | { 17 | return -1; /* Queue Full*/ 18 | } 19 | 20 | Queue[QueueIn] = element; 21 | QueueIn = (QueueIn + 1) % QUEUE_SIZE; 22 | 23 | return 0; // No errors 24 | } 25 | 26 | int QueueGet(int32_t* element) 27 | { 28 | if (QueueIn == QueueOut) 29 | { 30 | return -1; /* Queue Empty - nothing to get*/ 31 | } 32 | 33 | *element = Queue[QueueOut]; 34 | QueueOut = (QueueOut + 1) % QUEUE_SIZE; 35 | 36 | return 0; // No errors 37 | } 38 | -------------------------------------------------------------------------------- /Main/Keyboard/ps2Keyboard.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "stm32f1xx.h" 4 | #include "ps2keyboard.h" 5 | #include "queue.h" 6 | #include "Display/vgaCore.h" 7 | 8 | typedef enum 9 | { 10 | IDLE = 10, 11 | BIT0 = 0, 12 | BIT1 = 1, 13 | BIT2 = 2, 14 | BIT3 = 3, 15 | BIT4 = 4, 16 | BIT5 = 5, 17 | BIT6 = 6, 18 | BIT7 = 7, 19 | PARITY = 8, 20 | STOP = 9 21 | } ps2_read_status; 22 | 23 | static int32_t ps2_status; 24 | static int32_t kb_data; 25 | 26 | static uint8_t lastClk = 1; 27 | static uint8_t lastData; 28 | static bool _isLeftShiftPressed; 29 | static bool _isRightShiftPressed; 30 | static volatile uint8_t _parity; 31 | 32 | void Ps2_Initialize() 33 | { 34 | #ifdef BOARD2 35 | __HAL_RCC_GPIOA_CLK_ENABLE(); 36 | #else 37 | __HAL_RCC_GPIOB_CLK_ENABLE(); 38 | #endif 39 | 40 | GPIO_InitTypeDef GPIO_InitStruct; 41 | 42 | // CLK pin 43 | GPIO_InitStruct.Pin = CLK_PIN; 44 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 45 | GPIO_InitStruct.Pull = GPIO_NOPULL; 46 | HAL_GPIO_Init(KBD_GPIO, &GPIO_InitStruct); 47 | 48 | // DATA pin 49 | GPIO_InitStruct.Pin = DATA_PIN; 50 | GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 51 | GPIO_InitStruct.Pull = GPIO_NOPULL; 52 | HAL_GPIO_Init(KBD_GPIO, &GPIO_InitStruct); 53 | 54 | ps2_status = IDLE; 55 | QueueInit(); 56 | kb_data = 0; 57 | _isLeftShiftPressed = false; 58 | _isRightShiftPressed = false; 59 | } 60 | 61 | int32_t Ps2_GetScancode() 62 | { 63 | int32_t result; 64 | if (QueueGet(&result) == -1) 65 | { 66 | result = -1; 67 | } 68 | 69 | int32_t code = result & 0xFF; 70 | if (code == KEY_LEFTSHIFT) 71 | { 72 | _isLeftShiftPressed = (result & 0xFF00) != 0xF000; 73 | } 74 | if (code == KEY_RIGHTSHIFT) 75 | { 76 | _isRightShiftPressed = (result & 0xFF00) != 0xF000; 77 | } 78 | 79 | return result; 80 | } 81 | 82 | char Ps2_ConvertScancode(int32_t scanCode) 83 | { 84 | char result; 85 | 86 | switch (scanCode) 87 | { 88 | case KEY_A: 89 | result = 'a'; 90 | break; 91 | case KEY_B: 92 | result = 'b'; 93 | break; 94 | case KEY_C: 95 | result = 'c'; 96 | break; 97 | case KEY_D: 98 | result = 'd'; 99 | break; 100 | case KEY_E: 101 | result = 'e'; 102 | break; 103 | case KEY_F: 104 | result = 'f'; 105 | break; 106 | case KEY_G: 107 | result = 'g'; 108 | break; 109 | case KEY_H: 110 | result = 'h'; 111 | break; 112 | case KEY_I: 113 | result = 'i'; 114 | break; 115 | case KEY_J: 116 | result = 'j'; 117 | break; 118 | case KEY_K: 119 | result = 'k'; 120 | break; 121 | case KEY_L: 122 | result = 'l'; 123 | break; 124 | case KEY_M: 125 | result = 'm'; 126 | break; 127 | case KEY_N: 128 | result = 'n'; 129 | break; 130 | case KEY_O: 131 | result = 'o'; 132 | break; 133 | case KEY_P: 134 | result = 'p'; 135 | break; 136 | case KEY_Q: 137 | result = 'q'; 138 | break; 139 | case KEY_R: 140 | result = 'r'; 141 | break; 142 | case KEY_S: 143 | result = 's'; 144 | break; 145 | case KEY_T: 146 | result = 't'; 147 | break; 148 | case KEY_U: 149 | result = 'u'; 150 | break; 151 | case KEY_V: 152 | result = 'v'; 153 | break; 154 | case KEY_W: 155 | result = 'w'; 156 | break; 157 | case KEY_X: 158 | result = 'x'; 159 | break; 160 | case KEY_Y: 161 | result = 'y'; 162 | break; 163 | case KEY_Z: 164 | result = 'z'; 165 | break; 166 | case KEY_0: 167 | result = '0'; 168 | break; 169 | case KEY_1: 170 | result = '1'; 171 | break; 172 | case KEY_2: 173 | result = '2'; 174 | break; 175 | case KEY_3: 176 | result = '3'; 177 | break; 178 | case KEY_4: 179 | result = '4'; 180 | break; 181 | case KEY_5: 182 | result = '5'; 183 | break; 184 | case KEY_6: 185 | result = '6'; 186 | break; 187 | case KEY_7: 188 | result = '7'; 189 | break; 190 | case KEY_8: 191 | result = '8'; 192 | break; 193 | case KEY_9: 194 | result = '9'; 195 | break; 196 | case KEY_BACKSPACE: 197 | result = '\b'; 198 | break; 199 | case KEY_SPACEBAR: 200 | result = ' '; 201 | break; 202 | case KEY_COMMA: 203 | result = ','; 204 | break; 205 | case KEY_MINUS: 206 | result = '-'; 207 | break; 208 | case KEY_DOT: 209 | result = '.'; 210 | break; 211 | case KEY_DIV: 212 | result = '/'; 213 | break; 214 | case KEY_SINGLE: 215 | result = '`'; 216 | break; 217 | case KEY_APOS: 218 | result = '\''; 219 | break; 220 | case KEY_SEMI: 221 | result = ';'; 222 | break; 223 | case KEY_BACK: 224 | result = '\\'; 225 | break; 226 | case KEY_OPEN_SQ: 227 | result = '['; 228 | break; 229 | case KEY_CLOSE_SQ: 230 | result = ']'; 231 | break; 232 | case KEY_EQUAL: 233 | result = '='; 234 | break; 235 | default: 236 | result = '\0'; 237 | break; 238 | } 239 | 240 | if (_isLeftShiftPressed || _isRightShiftPressed) 241 | { 242 | switch (scanCode) 243 | { 244 | case KEY_0: 245 | result = ')'; 246 | break; 247 | case KEY_1: 248 | result = '!'; 249 | break; 250 | case KEY_2: 251 | result = '@'; 252 | break; 253 | case KEY_3: 254 | result = '#'; 255 | break; 256 | case KEY_4: 257 | result = '$'; 258 | break; 259 | case KEY_5: 260 | result = '%'; 261 | break; 262 | case KEY_6: 263 | result = '^'; 264 | break; 265 | case KEY_7: 266 | result = '&'; 267 | break; 268 | case KEY_8: 269 | result = '*'; 270 | break; 271 | case KEY_9: 272 | result = '('; 273 | break; 274 | case KEY_COMMA: 275 | result = '<'; 276 | break; 277 | case KEY_MINUS: 278 | result = '_'; 279 | break; 280 | case KEY_DOT: 281 | result = '>'; 282 | break; 283 | case KEY_DIV: 284 | result = '?'; 285 | break; 286 | case KEY_SINGLE: 287 | result = '~'; 288 | break; 289 | case KEY_APOS: 290 | result = '"'; 291 | break; 292 | case KEY_SEMI: 293 | result = ':'; 294 | break; 295 | case KEY_BACK: 296 | result = '|'; 297 | break; 298 | case KEY_OPEN_SQ: 299 | result = '{'; 300 | break; 301 | case KEY_CLOSE_SQ: 302 | result = '}'; 303 | break; 304 | case KEY_EQUAL: 305 | result = '+'; 306 | break; 307 | default: 308 | result = toupper(result); 309 | break; 310 | } 311 | } 312 | 313 | return result; 314 | } 315 | 316 | inline void Update(uint8_t dataBit) 317 | { 318 | switch (ps2_status) 319 | { 320 | case IDLE: 321 | ps2_status = BIT0; 322 | _parity = 0; 323 | break; 324 | 325 | case BIT0: 326 | ps2_status = BIT1; 327 | kb_data |= dataBit; 328 | _parity ^= dataBit; 329 | break; 330 | 331 | case BIT1: 332 | case BIT2: 333 | case BIT3: 334 | case BIT4: 335 | case BIT5: 336 | case BIT6: 337 | case BIT7: 338 | kb_data |= (dataBit << ps2_status); 339 | ps2_status++; 340 | _parity ^= dataBit; 341 | break; 342 | 343 | case PARITY: 344 | if (_parity == dataBit) 345 | { 346 | // Parity error 347 | _parity = 0xFD; 348 | kb_data = 0; 349 | 350 | // TODO ask to resend 351 | } 352 | ps2_status = STOP; 353 | break; 354 | 355 | case STOP: 356 | ps2_status = IDLE; 357 | if (_parity != 0xFD) 358 | { 359 | if ((kb_data & 0xE0) == 0xE0) 360 | { 361 | kb_data <<= 8; 362 | } 363 | else 364 | { 365 | QueuePut(kb_data); 366 | kb_data = 0; 367 | } 368 | } 369 | break; 370 | } 371 | } 372 | 373 | extern "C" void HBlankInterrupt() 374 | { 375 | uint32_t gpioBits = KBD_GPIO->IDR; 376 | 377 | if ((gpioBits & CLK_PIN) == 0) 378 | { 379 | // CLK = 0 380 | 381 | lastData = (gpioBits & DATA_PIN) ? 1 : 0; 382 | lastClk = 0; 383 | } 384 | else 385 | { 386 | // CLK = 1 387 | 388 | if (lastClk == 0) 389 | { 390 | Update(lastData); 391 | lastClk = 1; 392 | } 393 | else 394 | { 395 | if (ps2_status != IDLE) 396 | { 397 | lastClk++; 398 | if (lastClk > 10) 399 | { 400 | // Timeout 401 | ps2_status = IDLE; 402 | kb_data = 0; 403 | 404 | // TODO ask to resend 405 | } 406 | } 407 | else 408 | { 409 | lastClk = 1; 410 | } 411 | } 412 | } 413 | } 414 | -------------------------------------------------------------------------------- /Main/Keyboard/ps2Keyboard.h: -------------------------------------------------------------------------------- 1 | #ifndef _PS2KEYBOARD_H_ 2 | #define _PS2KEYBOARD_H_ 3 | 4 | #include "settings.h" 5 | 6 | #ifdef BOARD2 7 | #define CLK_PIN GPIO_PIN_0 8 | #define DATA_PIN GPIO_PIN_1 9 | #define KBD_GPIO GPIOA 10 | #else 11 | #define CLK_PIN GPIO_PIN_10 12 | #define DATA_PIN GPIO_PIN_11 13 | #define KBD_GPIO GPIOB 14 | #endif 15 | 16 | /* Single Byte Key Codes */ 17 | #define KEY_NUM 0x77 18 | #define KEY_SCROLL 0x7E 19 | #define KEY_CAPS 0x58 20 | #define KEY_LEFTSHIFT 0x12 21 | #define KEY_RIGHTSHIFT 0x59 22 | #define KEY_LEFTCONTROL 0x14 23 | #define KEY_ALT 0x11 24 | #define KEY_ESC 0x76 25 | #define KEY_BACKSPACE 0x66 26 | #define KEY_TAB 0x0D 27 | #define KEY_ENTER 0x5A 28 | #define KEY_SPACEBAR 0x29 29 | #define KEY_KP0 0x70 30 | #define KEY_KP1 0x69 31 | #define KEY_KP2 0x72 32 | #define KEY_KP3 0x7A 33 | #define KEY_KP4 0x6B 34 | #define KEY_KP5 0x73 35 | #define KEY_KP6 0x74 36 | #define KEY_KP7 0x6C 37 | #define KEY_KP8 0x75 38 | #define KEY_KP9 0x7D 39 | #define KEY_KP_DOT 0x71 40 | #define KEY_KP_PLUS 0x79 41 | #define KEY_KP_MINUS 0x7B 42 | #define KEY_KP_TIMES 0x7C 43 | #define KEY_0 0X45 44 | #define KEY_1 0X16 45 | #define KEY_2 0X1E 46 | #define KEY_3 0X26 47 | #define KEY_4 0X25 48 | #define KEY_5 0X2E 49 | #define KEY_6 0X36 50 | #define KEY_7 0X3D 51 | #define KEY_8 0X3E 52 | #define KEY_9 0X46 53 | #define KEY_APOS 0X52 54 | #define KEY_COMMA 0X41 55 | #define KEY_MINUS 0X4E 56 | #define KEY_DOT 0X49 57 | #define KEY_DIV 0X4A 58 | /* Single quote or back apostrophe */ 59 | #define KEY_SINGLE 0X0E 60 | #define KEY_A 0X1C 61 | #define KEY_B 0X32 62 | #define KEY_C 0X21 63 | #define KEY_D 0X23 64 | #define KEY_E 0X24 65 | #define KEY_F 0X2B 66 | #define KEY_G 0X34 67 | #define KEY_H 0X33 68 | #define KEY_I 0X43 69 | #define KEY_J 0X3B 70 | #define KEY_K 0X42 71 | #define KEY_L 0X4B 72 | #define KEY_M 0X3A 73 | #define KEY_N 0X31 74 | #define KEY_O 0X44 75 | #define KEY_P 0X4D 76 | #define KEY_Q 0X15 77 | #define KEY_R 0X2D 78 | #define KEY_S 0X1B 79 | #define KEY_T 0X2C 80 | #define KEY_U 0X3C 81 | #define KEY_V 0X2A 82 | #define KEY_W 0X1D 83 | #define KEY_X 0X22 84 | #define KEY_Y 0X35 85 | #define KEY_Z 0X1A 86 | #define KEY_SEMI 0X4C 87 | #define KEY_BACK 0X5D 88 | #define KEY_OPEN_SQ 0X54 89 | #define KEY_CLOSE_SQ 0X5B 90 | #define KEY_EQUAL 0X55 91 | #define KEY_F1 0X05 92 | #define KEY_F2 0X06 93 | #define KEY_F3 0X04 94 | #define KEY_F4 0X0C 95 | #define KEY_F5 0X03 96 | #define KEY_F6 0X0B 97 | #define KEY_F7 0X83 98 | #define KEY_F8 0X0A 99 | #define KEY_F9 0X01 100 | #define KEY_F10 0X09 101 | #define KEY_F11 0X78 102 | #define KEY_F12 0X07 103 | #define KEY_KP_COMMA 0X6D 104 | 105 | /* Extended key codes E0 table for two byte codes */ 106 | /* PS2_CTRL and PS2_ALT Need using in any table for the right keys */ 107 | /* first is special case for PRTSCR not always used so ignored by decoding */ 108 | #define KEY_IGNORE 0xE012 109 | #define KEY_PRTSCR 0xE07C 110 | #define KEY_RIGHTCONTROL 0XE014 111 | /* Sometimes called windows key */ 112 | #define KEY_L_GUI 0xE01F 113 | #define KEY_R_GUI 0xE027 114 | #define KEY_MENU 0xE02F 115 | /* Break is CTRL + PAUSE generated inside keyboard */ 116 | #define KEY_BREAK 0xE07E 117 | #define KEY_HOME 0xE06C 118 | #define KEY_END 0xE069 119 | #define KEY_PGUP 0xE07D 120 | #define KEY_PGDN 0xE07A 121 | #define KEY_LEFTARROW 0xE06B 122 | #define KEY_RIGHTARROW 0xE074 123 | #define KEY_UPARROW 0xE075 124 | #define KEY_DOWNARROW 0xE072 125 | #define KEY_INSERT 0xE070 126 | #define KEY_DELETE 0xE071 127 | #define KEY_KP_ENTER 0xE05A 128 | #define KEY_KP_DIV 0xE04A 129 | #define KEY_NEXT_TR 0XE04D 130 | #define KEY_PREV_TR 0XE015 131 | #define KEY_STOP 0XE038 132 | #define KEY_PLAY 0XE034 133 | #define KEY_MUTE 0XE023 134 | #define KEY_VOL_UP 0XE032 135 | #define KEY_VOL_DN 0XE021 136 | #define KEY_MEDIA 0XE050 137 | #define KEY_EMAIL 0XE048 138 | #define KEY_CALC 0XE02B 139 | #define KEY_COMPUTER 0XE040 140 | 141 | #ifdef __cplusplus 142 | extern "C" { 143 | #endif 144 | 145 | #include 146 | 147 | void Ps2_Initialize(); 148 | int32_t Ps2_GetScancode(); 149 | char Ps2_ConvertScancode(int32_t scanCode); 150 | 151 | void HBlankInterrupt(); 152 | 153 | #ifdef __cplusplus 154 | } 155 | #endif 156 | 157 | #endif 158 | -------------------------------------------------------------------------------- /Main/Keyboard/queue.h: -------------------------------------------------------------------------------- 1 | #ifndef _QUEUE_H_ 2 | #define _QUEUE_H_ 3 | 4 | #include 5 | 6 | #define QUEUE_ELEMENTS 6 7 | 8 | #ifdef __cplusplus 9 | extern "C" { 10 | #endif 11 | 12 | void QueueInit(); 13 | int QueuePut(int32_t element); 14 | int QueueGet(int32_t *element); 15 | 16 | #ifdef __cplusplus 17 | } 18 | #endif 19 | 20 | #endif -------------------------------------------------------------------------------- /Main/settings.h: -------------------------------------------------------------------------------- 1 | #ifndef __VIDEOSETTINGS_H__ 2 | #define __VIDEOSETTINGS_H__ 3 | 4 | //#define BOARD2 5 | 6 | #ifdef BOARD2 7 | #define GET_COLOR(x) ((x & 0x03) | ((x << 2) & 0xF0)) 8 | #else 9 | #define GET_COLOR(x) (x) 10 | #endif 11 | 12 | 13 | // Colors 14 | #define BACK_COLOR GET_COLOR(0x10) 15 | #define FORE_COLOR GET_COLOR(0x3F) 16 | //#define BACK_COLOR 0x00 17 | //#define FORE_COLOR 0x0C 18 | 19 | // Resolution 20 | #define TIMING timing_800x600_56hz 21 | #define HSIZE_CHARS 38 22 | #define VSIZE_CHARS 37 23 | 24 | #endif /* __VIDEOSETTINGS_H__ */ 25 | -------------------------------------------------------------------------------- /Main/startup.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "startup.h" 6 | #include "Display/vgaCore.h" 7 | #include "Display/timing.h" 8 | #include "Display/font8x16.h" 9 | #include "Display/vgaText.h" 10 | #include "Keyboard/ps2Keyboard.h" 11 | 12 | static uint16_t _screenCharacters[HSIZE_CHARS * VSIZE_CHARS + 1]; 13 | static uint32_t _screenAttributes[HSIZE_CHARS * VSIZE_CHARS + 1]; 14 | static uint8_t _allColorsAttribute[256]; 15 | 16 | using namespace Vga; 17 | 18 | static VideoSettings Video { 19 | &TIMING, 20 | HSIZE_CHARS, VSIZE_CHARS, 21 | _screenCharacters, _screenAttributes 22 | }; 23 | extern "C" void initialize() 24 | { 25 | } 26 | 27 | extern "C" void setup() 28 | { 29 | InitVga(&Video); 30 | InitVgaText(font8x16); 31 | 32 | // Display frame 33 | PrintChar(0, 0, '\xC9'); // ╔ 34 | PrintChar(HSIZE_CHARS - 1, 0, '\xBB'); // ╗ 35 | PrintChar(0, VSIZE_CHARS - 1, '\xC8'); // ╚ 36 | PrintChar(HSIZE_CHARS - 1, VSIZE_CHARS - 1, '\xBC'); // ╝ 37 | for (int i = 1; i < HSIZE_CHARS - 1; i++) 38 | { 39 | PrintChar(i, 0, '\x0CD'); // ═ 40 | PrintChar(i, VSIZE_CHARS - 1, '\x0CD'); // ═ 41 | } 42 | for (int i = 1; i < VSIZE_CHARS - 1; i++) 43 | { 44 | PrintChar(0, i, '\x0BA'); // ║ 45 | PrintChar(HSIZE_CHARS - 1, i, '\x0BA'); // ║ 46 | } 47 | 48 | // This is used to display 64 colors using a space character 49 | for (uint8_t color = 0; color < 64; color++) 50 | { 51 | for (uint8_t j = 0; j < 4; j++) 52 | { 53 | _allColorsAttribute[(color << 2) + j] = GET_COLOR(color); 54 | } 55 | } 56 | 57 | char buf[20]; 58 | for (int i = 0; i < 64; i++) 59 | { 60 | sprintf(buf, BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(i)); 61 | 62 | SetCursorPosition(4 + (i % 4) * 7, 4 + (i / 4) * 2); 63 | Print(" ", (uint32_t)&_allColorsAttribute[i * 4]); 64 | 65 | SetCursorPosition(4 + (i % 4) * 7, 3 + (i / 4) * 2); 66 | Print(buf); 67 | } 68 | 69 | // Initialize PS2 Keyboard 70 | Ps2_Initialize(); 71 | 72 | SetCursorPosition(1, 1); 73 | ShowCursor(); 74 | } 75 | 76 | extern "C" void loop() 77 | { 78 | int32_t scanCode = Ps2_GetScancode(); 79 | if (scanCode > 0) 80 | { 81 | //char buf[30]; 82 | //snprintf(buf, 30, "%04lx", (uint32_t)scanCode); 83 | //Print(buf); 84 | 85 | if ((scanCode & 0xFF00) != 0xF000) 86 | { 87 | // key down 88 | switch (scanCode) 89 | { 90 | case KEY_LEFTARROW: 91 | if (Vga::cursor_x > 0) 92 | { 93 | Vga::SetAttribute(Vga::cursor_x - 1, Vga::cursor_y, (int32_t)Vga::StandardAttribute); 94 | Vga::SetCursorPosition(Vga::cursor_x - 1, Vga::cursor_y); 95 | } 96 | break; 97 | case KEY_BACKSPACE: 98 | if (Vga::cursor_x > 0) 99 | { 100 | Vga::SetCursorPosition(Vga::cursor_x - 1, Vga::cursor_y); 101 | Vga::PrintChar(Vga::cursor_x, Vga::cursor_y, ' ', (int32_t)Vga::StandardAttribute); 102 | } 103 | break; 104 | case KEY_RIGHTARROW: 105 | if (Vga::cursor_x < HSIZE_CHARS - 1) 106 | { 107 | Vga::SetAttribute(Vga::cursor_x + 1, Vga::cursor_y, (int32_t)Vga::StandardAttribute); 108 | Vga::SetCursorPosition(Vga::cursor_x + 1, Vga::cursor_y); 109 | } 110 | break; 111 | case KEY_UPARROW: 112 | if (Vga::cursor_y > 0) 113 | { 114 | Vga::SetAttribute(Vga::cursor_x, Vga::cursor_y - 1, (int32_t)Vga::StandardAttribute); 115 | Vga::SetCursorPosition(Vga::cursor_x, Vga::cursor_y - 1); 116 | } 117 | break; 118 | case KEY_DOWNARROW: 119 | if (Vga::cursor_y < VSIZE_CHARS - 1) 120 | { 121 | Vga::SetAttribute(Vga::cursor_x, Vga::cursor_y + 1, (int32_t)Vga::StandardAttribute); 122 | Vga::SetCursorPosition(Vga::cursor_x, Vga::cursor_y + 1); 123 | } 124 | break; 125 | default: 126 | char buf[2]; 127 | buf[0] = Ps2_ConvertScancode(scanCode); 128 | if (buf[0] != '\0') 129 | { 130 | buf[1] = '\0'; 131 | Vga::Print(buf, (int32_t)Vga::StandardAttribute); 132 | } 133 | } 134 | } 135 | } 136 | 137 | //HAL_Delay(10); 138 | } 139 | -------------------------------------------------------------------------------- /Main/startup.h: -------------------------------------------------------------------------------- 1 | #ifndef __STARTUP_H__ 2 | #define __STARTUP_H__ 3 | 4 | #ifdef __cplusplus 5 | extern "C" 6 | { 7 | #endif 8 | 9 | #include "stm32f1xx.h" 10 | #include 11 | 12 | void initialize(); 13 | void setup(); 14 | void loop(); 15 | 16 | #define BYTE_TO_BINARY_PATTERN "%c%c%c%c%c%c" 17 | #define BYTE_TO_BINARY(byte) \ 18 | (byte & 0x20 ? '1' : '0'), \ 19 | (byte & 0x10 ? '1' : '0'), \ 20 | (byte & 0x08 ? '1' : '0'), \ 21 | (byte & 0x04 ? '1' : '0'), \ 22 | (byte & 0x02 ? '1' : '0'), \ 23 | (byte & 0x01 ? '1' : '0') 24 | 25 | #ifdef __cplusplus 26 | } 27 | #endif 28 | 29 | #endif /* __STARTUP_H__ */ 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## stm32f103-vgaText 2 | VGA text demo on STM32F103 "bluepill" 3 | 4 | ![Board](https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/master/doc/Board.jpg) 5 | 6 | ## What it can do 7 | * Display 38x37 characters 8 | * Use PS/2 keyboard to type and move cursor 9 | 10 | ![Screenshot](https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/master/doc/Screenshot.jpg) 11 | 12 | ## Instructions 13 | 14 | | Hardware | Qty| 15 | | ------------- | -----:| 16 | | [STM32F103 "Blue Pill"](https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill) board | 1 17 | | VGA connector | 1 18 | | PS/2 Keyboard | 1 19 | | Resistors 470 Ohm | 3 20 | | Resistors 680 Ohm | 3 21 | | Resistors 2.2 KOhm | 2 22 | | Resistors 3.3 KOhm | 2 23 | | Breadboard | 1 24 | | Jumper wires | 20 25 | | ST-Link v2 or clone | 1 26 | 27 | Software: Install free IDE [STM32CubeIDE](https://www.st.com/en/development-tools/stm32cubeide.html). I am using Windows 10, however STMicroelectronics claims that it also supports Linux and Mac. 28 | 29 | How to connect wires: 30 | 31 | | PIN | Description | Connect To | Output | 32 | | --- | ----------- | ---------- | ------ | 33 | | PA0 | Red 1 | Resistor 470 Ohm | VGA red (1) 34 | | PA1 | Red 2 | Resistor 680 Ohm | VGA red (1) 35 | | PA2 | Green 1 | Resistor 470 Ohm | VGA green (2) 36 | | PA3 | Green 2 | Resistor 680 Ohm | VGA green (2) 37 | | PA4 | Blue 1 | Resistor 470 Ohm | VGA blue (3) 38 | | PA5 | Blue 2 | Resistor 680 Ohm | VGA blue (3) 39 | | PB0 | HSync | | VGA HSync (13) 40 | | PB6 | VSync | | VGA VSync (14) 41 | | PB10 | CLK | Resistor 2K2 to keyboard CLK and resistor 3K3 to GND 42 | | PB11 | DATA | Resistor 2K2 to keyboard DATA and resistor 3K3 to GND 43 | | G | Ground | | VGA Ground (5,6,7,8,10) 44 | 45 | ## Overview 46 | The STM32F103 is a Cortex-M3 microcontroller that has neither a video controller, nor enough RAM for a framebuffer at any reasonable resolution. 47 | 48 | This demo works around this to produce an acceptable quality 800x600 video with 64 colors to display 38x37 (1,406) 8x16 pixel characters. It uses three timers and a GPIO port. In addition to VGA output, the demo also gets input from a PS/2 keyboard. 49 | The release build is using about half of the 20K available RAM. 50 | 51 | ## Implementation Details 52 | * Timer TIM4 is used to generate vertical sync signal 53 | * Timer TIM2 is used as a "shock absorber" to make the VGA stable 54 | * Timer TIM3 is used to generate horizontal sync signal 55 | * The code that reads the PS/2 keyboard input is running inside PendSV interrupt 56 | * Video memory contains 2 byte characters (unfortunately, if using 1 byte, only 127 characters can be supported because of limitation of the "drawing" assembly function) and 4 byte "attributes". The attribute is an address to a 128 byte lookup table containing (4 * 16) normal colors and (4 * 16) inverted colors (to show cursor) 57 | * File settings.h contains definitions for default colors (background and font), timing for VGA mode (set to 800x600 @ 56 Hz), as well as number of character columns and rows 58 | -------------------------------------------------------------------------------- /STM32F103C8Tx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** Author : Auto-generated by Ac6 System Workbench 8 | ** 9 | ** Abstract : Linker script for STM32F103C8Tx series 10 | ** 64Kbytes FLASH and 20Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed �as is,� without any warranty 20 | ** of any kind. 21 | ** 22 | ***************************************************************************** 23 | ** @attention 24 | ** 25 | **

© COPYRIGHT(c) 2014 Ac6

26 | ** 27 | ** Redistribution and use in source and binary forms, with or without modification, 28 | ** are permitted provided that the following conditions are met: 29 | ** 1. Redistributions of source code must retain the above copyright notice, 30 | ** this list of conditions and the following disclaimer. 31 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 32 | ** this list of conditions and the following disclaimer in the documentation 33 | ** and/or other materials provided with the distribution. 34 | ** 3. Neither the name of Ac6 nor the names of its contributors 35 | ** may be used to endorse or promote products derived from this software 36 | ** without specific prior written permission. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ** 49 | ***************************************************************************** 50 | */ 51 | 52 | /* Entry Point */ 53 | ENTRY(Reset_Handler) 54 | 55 | /* Highest address of the user mode stack */ 56 | _estack = 0x20005000; /* end of RAM */ 57 | /* Generate a link error if heap and stack don't fit into RAM */ 58 | _Min_Heap_Size = 0x000; /* required amount of heap */ 59 | _Min_Stack_Size = 0x400; /* required amount of stack */ 60 | 61 | /* Specify the memory areas */ 62 | MEMORY 63 | { 64 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K 65 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K 66 | } 67 | 68 | /* Define output sections */ 69 | SECTIONS 70 | { 71 | /* The startup code goes first into FLASH */ 72 | .isr_vector : 73 | { 74 | . = ALIGN(4); 75 | KEEP(*(.isr_vector)) /* Startup code */ 76 | . = ALIGN(4); 77 | } >FLASH 78 | 79 | /* The program code and other data goes into FLASH */ 80 | .text : 81 | { 82 | . = ALIGN(4); 83 | *(.text) /* .text sections (code) */ 84 | *(.text*) /* .text* sections (code) */ 85 | *(.glue_7) /* glue arm to thumb code */ 86 | *(.glue_7t) /* glue thumb to arm code */ 87 | *(.eh_frame) 88 | 89 | KEEP (*(.init)) 90 | KEEP (*(.fini)) 91 | 92 | . = ALIGN(4); 93 | _etext = .; /* define a global symbols at end of code */ 94 | } >FLASH 95 | 96 | /* Constant data goes into FLASH */ 97 | .rodata : 98 | { 99 | . = ALIGN(4); 100 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 101 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 102 | . = ALIGN(4); 103 | } >FLASH 104 | 105 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 106 | .ARM : { 107 | __exidx_start = .; 108 | *(.ARM.exidx*) 109 | __exidx_end = .; 110 | } >FLASH 111 | 112 | .preinit_array : 113 | { 114 | PROVIDE_HIDDEN (__preinit_array_start = .); 115 | KEEP (*(.preinit_array*)) 116 | PROVIDE_HIDDEN (__preinit_array_end = .); 117 | } >FLASH 118 | .init_array : 119 | { 120 | PROVIDE_HIDDEN (__init_array_start = .); 121 | KEEP (*(SORT(.init_array.*))) 122 | KEEP (*(.init_array*)) 123 | PROVIDE_HIDDEN (__init_array_end = .); 124 | } >FLASH 125 | .fini_array : 126 | { 127 | PROVIDE_HIDDEN (__fini_array_start = .); 128 | KEEP (*(SORT(.fini_array.*))) 129 | KEEP (*(.fini_array*)) 130 | PROVIDE_HIDDEN (__fini_array_end = .); 131 | } >FLASH 132 | 133 | /* used by the startup to initialize data */ 134 | _sidata = LOADADDR(.data); 135 | 136 | /* Initialized data sections goes into RAM, load LMA copy after code */ 137 | .data : 138 | { 139 | . = ALIGN(4); 140 | _sdata = .; /* create a global symbol at data start */ 141 | *(.data) /* .data sections */ 142 | *(.data*) /* .data* sections */ 143 | 144 | . = ALIGN(4); 145 | _edata = .; /* define a global symbol at data end */ 146 | } >RAM AT> FLASH 147 | 148 | 149 | /* Uninitialized data section */ 150 | . = ALIGN(4); 151 | .bss : 152 | { 153 | /* This is used by the startup in order to initialize the .bss secion */ 154 | _sbss = .; /* define a global symbol at bss start */ 155 | __bss_start__ = _sbss; 156 | *(.bss) 157 | *(.bss*) 158 | *(COMMON) 159 | 160 | . = ALIGN(4); 161 | _ebss = .; /* define a global symbol at bss end */ 162 | __bss_end__ = _ebss; 163 | } >RAM 164 | 165 | /* User_heap_stack section, used to check that there is enough RAM left */ 166 | ._user_heap_stack : 167 | { 168 | . = ALIGN(8); 169 | PROVIDE ( end = . ); 170 | PROVIDE ( _end = . ); 171 | . = . + _Min_Heap_Size; 172 | . = . + _Min_Stack_Size; 173 | . = ALIGN(8); 174 | } >RAM 175 | 176 | 177 | 178 | /* Remove information from the standard libraries */ 179 | /DISCARD/ : 180 | { 181 | libc.a ( * ) 182 | libm.a ( * ) 183 | libgcc.a ( * ) 184 | } 185 | 186 | .ARM.attributes 0 : { *(.ARM.attributes) } 187 | } 188 | 189 | 190 | -------------------------------------------------------------------------------- /Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2019 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | 23 | /* Private includes ----------------------------------------------------------*/ 24 | /* USER CODE BEGIN Includes */ 25 | #include "startup.h" 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN PTD */ 30 | 31 | /* USER CODE END PTD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | RTC_HandleTypeDef hrtc; 45 | 46 | TIM_HandleTypeDef htim3; 47 | 48 | /* USER CODE BEGIN PV */ 49 | 50 | /* USER CODE END PV */ 51 | 52 | /* Private function prototypes -----------------------------------------------*/ 53 | void SystemClock_Config(void); 54 | static void MX_GPIO_Init(void); 55 | static void MX_RTC_Init(void); 56 | static void MX_TIM3_Init(void); 57 | /* USER CODE BEGIN PFP */ 58 | 59 | /* USER CODE END PFP */ 60 | 61 | /* Private user code ---------------------------------------------------------*/ 62 | /* USER CODE BEGIN 0 */ 63 | static void MX_TIM3_Init(void) __attribute__((unused)); 64 | /* USER CODE END 0 */ 65 | 66 | /** 67 | * @brief The application entry point. 68 | * @retval int 69 | */ 70 | int main(void) 71 | { 72 | /* USER CODE BEGIN 1 */ 73 | 74 | /* USER CODE END 1 */ 75 | 76 | /* MCU Configuration--------------------------------------------------------*/ 77 | 78 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 79 | HAL_Init(); 80 | 81 | /* USER CODE BEGIN Init */ 82 | 83 | /* USER CODE END Init */ 84 | 85 | /* Configure the system clock */ 86 | SystemClock_Config(); 87 | 88 | /* USER CODE BEGIN SysInit */ 89 | 90 | /* USER CODE END SysInit */ 91 | 92 | /* Initialize all configured peripherals */ 93 | MX_GPIO_Init(); 94 | MX_RTC_Init(); 95 | /* USER CODE BEGIN 2 */ 96 | setup(); 97 | /* USER CODE END 2 */ 98 | 99 | /* Infinite loop */ 100 | /* USER CODE BEGIN WHILE */ 101 | while (1) 102 | { 103 | loop(); 104 | /* USER CODE END WHILE */ 105 | 106 | /* USER CODE BEGIN 3 */ 107 | } 108 | /* USER CODE END 3 */ 109 | } 110 | 111 | /** 112 | * @brief System Clock Configuration 113 | * @retval None 114 | */ 115 | void SystemClock_Config(void) 116 | { 117 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 118 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 119 | RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 120 | 121 | /** Initializes the RCC Oscillators according to the specified parameters 122 | * in the RCC_OscInitTypeDef structure. 123 | */ 124 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 125 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; 126 | RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 127 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 128 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 129 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 130 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 131 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 132 | { 133 | Error_Handler(); 134 | } 135 | /** Initializes the CPU, AHB and APB buses clocks 136 | */ 137 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 138 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 139 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 140 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 141 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 142 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 143 | 144 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 145 | { 146 | Error_Handler(); 147 | } 148 | PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; 149 | PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV128; 150 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 151 | { 152 | Error_Handler(); 153 | } 154 | } 155 | 156 | /** 157 | * @brief RTC Initialization Function 158 | * @param None 159 | * @retval None 160 | */ 161 | static void MX_RTC_Init(void) 162 | { 163 | 164 | /* USER CODE BEGIN RTC_Init 0 */ 165 | 166 | /* USER CODE END RTC_Init 0 */ 167 | 168 | /* USER CODE BEGIN RTC_Init 1 */ 169 | 170 | /* USER CODE END RTC_Init 1 */ 171 | /** Initialize RTC Only 172 | */ 173 | hrtc.Instance = RTC; 174 | hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 175 | hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 176 | if (HAL_RTC_Init(&hrtc) != HAL_OK) 177 | { 178 | Error_Handler(); 179 | } 180 | /* USER CODE BEGIN RTC_Init 2 */ 181 | 182 | /* USER CODE END RTC_Init 2 */ 183 | 184 | } 185 | 186 | /** 187 | * @brief TIM3 Initialization Function 188 | * @param None 189 | * @retval None 190 | */ 191 | static void MX_TIM3_Init(void) 192 | { 193 | 194 | /* USER CODE BEGIN TIM3_Init 0 */ 195 | 196 | /* USER CODE END TIM3_Init 0 */ 197 | 198 | TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 199 | TIM_MasterConfigTypeDef sMasterConfig = {0}; 200 | 201 | /* USER CODE BEGIN TIM3_Init 1 */ 202 | 203 | /* USER CODE END TIM3_Init 1 */ 204 | htim3.Instance = TIM3; 205 | htim3.Init.Prescaler = 0; 206 | htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 207 | htim3.Init.Period = 65535; 208 | htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 209 | htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 210 | if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 211 | { 212 | Error_Handler(); 213 | } 214 | sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 215 | if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 216 | { 217 | Error_Handler(); 218 | } 219 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 220 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 221 | if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 222 | { 223 | Error_Handler(); 224 | } 225 | /* USER CODE BEGIN TIM3_Init 2 */ 226 | 227 | /* USER CODE END TIM3_Init 2 */ 228 | 229 | } 230 | 231 | /** 232 | * @brief GPIO Initialization Function 233 | * @param None 234 | * @retval None 235 | */ 236 | static void MX_GPIO_Init(void) 237 | { 238 | 239 | /* GPIO Ports Clock Enable */ 240 | __HAL_RCC_GPIOD_CLK_ENABLE(); 241 | __HAL_RCC_GPIOA_CLK_ENABLE(); 242 | 243 | } 244 | 245 | /* USER CODE BEGIN 4 */ 246 | 247 | /* USER CODE END 4 */ 248 | 249 | /** 250 | * @brief This function is executed in case of error occurrence. 251 | * @retval None 252 | */ 253 | void Error_Handler(void) 254 | { 255 | /* USER CODE BEGIN Error_Handler_Debug */ 256 | /* User can add his own implementation to report the HAL error return state */ 257 | 258 | /* USER CODE END Error_Handler_Debug */ 259 | } 260 | 261 | #ifdef USE_FULL_ASSERT 262 | /** 263 | * @brief Reports the name of the source file and the source line number 264 | * where the assert_param error has occurred. 265 | * @param file: pointer to the source file name 266 | * @param line: assert_param error line source number 267 | * @retval None 268 | */ 269 | void assert_failed(uint8_t *file, uint32_t line) 270 | { 271 | /* USER CODE BEGIN 6 */ 272 | /* User can add his own implementation to report the file name and line number, 273 | tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 274 | /* USER CODE END 6 */ 275 | } 276 | #endif /* USE_FULL_ASSERT */ 277 | 278 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 279 | -------------------------------------------------------------------------------- /Src/stm32f1xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * File Name : stm32f1xx_hal_msp.c 5 | * Description : This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2019 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_AFIO_CLK_ENABLE(); 71 | __HAL_RCC_PWR_CLK_ENABLE(); 72 | 73 | /* System interrupt init*/ 74 | /* PendSV_IRQn interrupt configuration */ 75 | HAL_NVIC_SetPriority(PendSV_IRQn, 1, 0); 76 | 77 | /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 78 | */ 79 | __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80 | 81 | /* USER CODE BEGIN MspInit 1 */ 82 | 83 | /* USER CODE END MspInit 1 */ 84 | } 85 | 86 | /** 87 | * @brief RTC MSP Initialization 88 | * This function configures the hardware resources used in this example 89 | * @param hrtc: RTC handle pointer 90 | * @retval None 91 | */ 92 | void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) 93 | { 94 | if(hrtc->Instance==RTC) 95 | { 96 | /* USER CODE BEGIN RTC_MspInit 0 */ 97 | 98 | /* USER CODE END RTC_MspInit 0 */ 99 | HAL_PWR_EnableBkUpAccess(); 100 | /* Enable BKP CLK enable for backup registers */ 101 | __HAL_RCC_BKP_CLK_ENABLE(); 102 | /* Peripheral clock enable */ 103 | __HAL_RCC_RTC_ENABLE(); 104 | /* USER CODE BEGIN RTC_MspInit 1 */ 105 | 106 | /* USER CODE END RTC_MspInit 1 */ 107 | } 108 | 109 | } 110 | 111 | /** 112 | * @brief RTC MSP De-Initialization 113 | * This function freeze the hardware resources used in this example 114 | * @param hrtc: RTC handle pointer 115 | * @retval None 116 | */ 117 | void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) 118 | { 119 | if(hrtc->Instance==RTC) 120 | { 121 | /* USER CODE BEGIN RTC_MspDeInit 0 */ 122 | 123 | /* USER CODE END RTC_MspDeInit 0 */ 124 | /* Peripheral clock disable */ 125 | __HAL_RCC_RTC_DISABLE(); 126 | /* USER CODE BEGIN RTC_MspDeInit 1 */ 127 | 128 | /* USER CODE END RTC_MspDeInit 1 */ 129 | } 130 | 131 | } 132 | 133 | /** 134 | * @brief TIM_Base MSP Initialization 135 | * This function configures the hardware resources used in this example 136 | * @param htim_base: TIM_Base handle pointer 137 | * @retval None 138 | */ 139 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) 140 | { 141 | if(htim_base->Instance==TIM3) 142 | { 143 | /* USER CODE BEGIN TIM3_MspInit 0 */ 144 | 145 | /* USER CODE END TIM3_MspInit 0 */ 146 | /* Peripheral clock enable */ 147 | __HAL_RCC_TIM3_CLK_ENABLE(); 148 | /* USER CODE BEGIN TIM3_MspInit 1 */ 149 | 150 | /* USER CODE END TIM3_MspInit 1 */ 151 | } 152 | 153 | } 154 | 155 | /** 156 | * @brief TIM_Base MSP De-Initialization 157 | * This function freeze the hardware resources used in this example 158 | * @param htim_base: TIM_Base handle pointer 159 | * @retval None 160 | */ 161 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) 162 | { 163 | if(htim_base->Instance==TIM3) 164 | { 165 | /* USER CODE BEGIN TIM3_MspDeInit 0 */ 166 | 167 | /* USER CODE END TIM3_MspDeInit 0 */ 168 | /* Peripheral clock disable */ 169 | __HAL_RCC_TIM3_CLK_DISABLE(); 170 | /* USER CODE BEGIN TIM3_MspDeInit 1 */ 171 | 172 | /* USER CODE END TIM3_MspDeInit 1 */ 173 | } 174 | 175 | } 176 | 177 | /* USER CODE BEGIN 1 */ 178 | 179 | /* USER CODE END 1 */ 180 | 181 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 182 | -------------------------------------------------------------------------------- /Src/stm32f1xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f1xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2019 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32f1xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | #include "Keyboard/ps2Keyboard.h" 27 | /* USER CODE END Includes */ 28 | 29 | /* Private typedef -----------------------------------------------------------*/ 30 | /* USER CODE BEGIN TD */ 31 | 32 | /* USER CODE END TD */ 33 | 34 | /* Private define ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN PD */ 36 | 37 | /* USER CODE END PD */ 38 | 39 | /* Private macro -------------------------------------------------------------*/ 40 | /* USER CODE BEGIN PM */ 41 | 42 | /* USER CODE END PM */ 43 | 44 | /* Private variables ---------------------------------------------------------*/ 45 | /* USER CODE BEGIN PV */ 46 | 47 | /* USER CODE END PV */ 48 | 49 | /* Private function prototypes -----------------------------------------------*/ 50 | /* USER CODE BEGIN PFP */ 51 | 52 | /* USER CODE END PFP */ 53 | 54 | /* Private user code ---------------------------------------------------------*/ 55 | /* USER CODE BEGIN 0 */ 56 | 57 | /* USER CODE END 0 */ 58 | 59 | /* External variables --------------------------------------------------------*/ 60 | 61 | /* USER CODE BEGIN EV */ 62 | 63 | /* USER CODE END EV */ 64 | 65 | /******************************************************************************/ 66 | /* Cortex-M3 Processor Interruption and Exception Handlers */ 67 | /******************************************************************************/ 68 | /** 69 | * @brief This function handles Non maskable interrupt. 70 | */ 71 | void NMI_Handler(void) 72 | { 73 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 74 | 75 | /* USER CODE END NonMaskableInt_IRQn 0 */ 76 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 77 | 78 | /* USER CODE END NonMaskableInt_IRQn 1 */ 79 | } 80 | 81 | /** 82 | * @brief This function handles Hard fault interrupt. 83 | */ 84 | void HardFault_Handler(void) 85 | { 86 | /* USER CODE BEGIN HardFault_IRQn 0 */ 87 | 88 | /* USER CODE END HardFault_IRQn 0 */ 89 | while (1) 90 | { 91 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 92 | /* USER CODE END W1_HardFault_IRQn 0 */ 93 | } 94 | } 95 | 96 | /** 97 | * @brief This function handles Memory management fault. 98 | */ 99 | void MemManage_Handler(void) 100 | { 101 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 102 | 103 | /* USER CODE END MemoryManagement_IRQn 0 */ 104 | while (1) 105 | { 106 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 107 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 108 | } 109 | } 110 | 111 | /** 112 | * @brief This function handles Prefetch fault, memory access fault. 113 | */ 114 | void BusFault_Handler(void) 115 | { 116 | /* USER CODE BEGIN BusFault_IRQn 0 */ 117 | 118 | /* USER CODE END BusFault_IRQn 0 */ 119 | while (1) 120 | { 121 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 122 | /* USER CODE END W1_BusFault_IRQn 0 */ 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function handles Undefined instruction or illegal state. 128 | */ 129 | void UsageFault_Handler(void) 130 | { 131 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 132 | 133 | /* USER CODE END UsageFault_IRQn 0 */ 134 | while (1) 135 | { 136 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 137 | /* USER CODE END W1_UsageFault_IRQn 0 */ 138 | } 139 | } 140 | 141 | /** 142 | * @brief This function handles System service call via SWI instruction. 143 | */ 144 | void SVC_Handler(void) 145 | { 146 | /* USER CODE BEGIN SVCall_IRQn 0 */ 147 | 148 | /* USER CODE END SVCall_IRQn 0 */ 149 | /* USER CODE BEGIN SVCall_IRQn 1 */ 150 | 151 | /* USER CODE END SVCall_IRQn 1 */ 152 | } 153 | 154 | /** 155 | * @brief This function handles Debug monitor. 156 | */ 157 | void DebugMon_Handler(void) 158 | { 159 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 160 | 161 | /* USER CODE END DebugMonitor_IRQn 0 */ 162 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 163 | 164 | /* USER CODE END DebugMonitor_IRQn 1 */ 165 | } 166 | 167 | /** 168 | * @brief This function handles Pendable request for system service. 169 | */ 170 | void PendSV_Handler(void) 171 | { 172 | /* USER CODE BEGIN PendSV_IRQn 0 */ 173 | HBlankInterrupt(); 174 | /* USER CODE END PendSV_IRQn 0 */ 175 | /* USER CODE BEGIN PendSV_IRQn 1 */ 176 | 177 | /* USER CODE END PendSV_IRQn 1 */ 178 | } 179 | 180 | /** 181 | * @brief This function handles System tick timer. 182 | */ 183 | void SysTick_Handler(void) 184 | { 185 | /* USER CODE BEGIN SysTick_IRQn 0 */ 186 | 187 | /* USER CODE END SysTick_IRQn 0 */ 188 | HAL_IncTick(); 189 | /* USER CODE BEGIN SysTick_IRQn 1 */ 190 | 191 | /* USER CODE END SysTick_IRQn 1 */ 192 | } 193 | 194 | /******************************************************************************/ 195 | /* STM32F1xx Peripheral Interrupt Handlers */ 196 | /* Add here the Interrupt Handlers for the used peripherals. */ 197 | /* For the available peripheral interrupt handler names, */ 198 | /* please refer to the startup file (startup_stm32f1xx.s). */ 199 | /******************************************************************************/ 200 | 201 | /* USER CODE BEGIN 1 */ 202 | 203 | /* USER CODE END 1 */ 204 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 205 | -------------------------------------------------------------------------------- /Src/syscalls.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/Src/syscalls.c -------------------------------------------------------------------------------- /doc/Board.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/doc/Board.jpg -------------------------------------------------------------------------------- /doc/Screenshot.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abelykh0/stm32f103-vgaText/7513cb106f2915a45502568fc5a9a4dfc7db4f6a/doc/Screenshot.jpg -------------------------------------------------------------------------------- /startup/startup_stm32f103xb.s: -------------------------------------------------------------------------------- 1 | /** 2 | *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ 3 | * @file startup_stm32f103xb.s 4 | * @author MCD Application Team 5 | * @version V4.2.0 6 | * @date 31-March-2017 7 | * @brief STM32F103xB Devices vector table for Atollic toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * 19 | *

© COPYRIGHT(c) 2017 STMicroelectronics

20 | * 21 | * Redistribution and use in source and binary forms, with or without modification, 22 | * are permitted provided that the following conditions are met: 23 | * 1. Redistributions of source code must retain the above copyright notice, 24 | * this list of conditions and the following disclaimer. 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, 26 | * this list of conditions and the following disclaimer in the documentation 27 | * and/or other materials provided with the distribution. 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 29 | * may be used to endorse or promote products derived from this software 30 | * without specific prior written permission. 31 | * 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | * 43 | ****************************************************************************** 44 | */ 45 | 46 | .syntax unified 47 | .cpu cortex-m3 48 | .fpu softvfp 49 | .thumb 50 | 51 | .global g_pfnVectors 52 | .global Default_Handler 53 | 54 | /* start address for the initialization values of the .data section. 55 | defined in linker script */ 56 | .word _sidata 57 | /* start address for the .data section. defined in linker script */ 58 | .word _sdata 59 | /* end address for the .data section. defined in linker script */ 60 | .word _edata 61 | /* start address for the .bss section. defined in linker script */ 62 | .word _sbss 63 | /* end address for the .bss section. defined in linker script */ 64 | .word _ebss 65 | 66 | .equ BootRAM, 0xF108F85F 67 | /** 68 | * @brief This is the code that gets called when the processor first 69 | * starts execution following a reset event. Only the absolutely 70 | * necessary set is performed, after which the application 71 | * supplied main() routine is called. 72 | * @param None 73 | * @retval : None 74 | */ 75 | 76 | .section .text.Reset_Handler 77 | .weak Reset_Handler 78 | .type Reset_Handler, %function 79 | Reset_Handler: 80 | 81 | /* Copy the data segment initializers from flash to SRAM */ 82 | movs r1, #0 83 | b LoopCopyDataInit 84 | 85 | CopyDataInit: 86 | ldr r3, =_sidata 87 | ldr r3, [r3, r1] 88 | str r3, [r0, r1] 89 | adds r1, r1, #4 90 | 91 | LoopCopyDataInit: 92 | ldr r0, =_sdata 93 | ldr r3, =_edata 94 | adds r2, r0, r1 95 | cmp r2, r3 96 | bcc CopyDataInit 97 | ldr r2, =_sbss 98 | b LoopFillZerobss 99 | /* Zero fill the bss segment. */ 100 | FillZerobss: 101 | movs r3, #0 102 | str r3, [r2], #4 103 | 104 | LoopFillZerobss: 105 | ldr r3, = _ebss 106 | cmp r2, r3 107 | bcc FillZerobss 108 | 109 | /* Call the clock system intitialization function.*/ 110 | bl SystemInit 111 | /* Call static constructors */ 112 | bl __libc_init_array 113 | /* Call the application's entry point.*/ 114 | bl main 115 | bx lr 116 | .size Reset_Handler, .-Reset_Handler 117 | 118 | /** 119 | * @brief This is the code that gets called when the processor receives an 120 | * unexpected interrupt. This simply enters an infinite loop, preserving 121 | * the system state for examination by a debugger. 122 | * 123 | * @param None 124 | * @retval : None 125 | */ 126 | .section .text.Default_Handler,"ax",%progbits 127 | Default_Handler: 128 | Infinite_Loop: 129 | b Infinite_Loop 130 | .size Default_Handler, .-Default_Handler 131 | /****************************************************************************** 132 | * 133 | * The minimal vector table for a Cortex M3. Note that the proper constructs 134 | * must be placed on this to ensure that it ends up at physical address 135 | * 0x0000.0000. 136 | * 137 | ******************************************************************************/ 138 | .section .isr_vector,"a",%progbits 139 | .type g_pfnVectors, %object 140 | .size g_pfnVectors, .-g_pfnVectors 141 | 142 | 143 | g_pfnVectors: 144 | 145 | .word _estack 146 | .word Reset_Handler 147 | .word NMI_Handler 148 | .word HardFault_Handler 149 | .word MemManage_Handler 150 | .word BusFault_Handler 151 | .word UsageFault_Handler 152 | .word 0 153 | .word 0 154 | .word 0 155 | .word 0 156 | .word SVC_Handler 157 | .word DebugMon_Handler 158 | .word 0 159 | .word PendSV_Handler 160 | .word SysTick_Handler 161 | .word WWDG_IRQHandler 162 | .word PVD_IRQHandler 163 | .word TAMPER_IRQHandler 164 | .word RTC_IRQHandler 165 | .word FLASH_IRQHandler 166 | .word RCC_IRQHandler 167 | .word EXTI0_IRQHandler 168 | .word EXTI1_IRQHandler 169 | .word EXTI2_IRQHandler 170 | .word EXTI3_IRQHandler 171 | .word EXTI4_IRQHandler 172 | .word DMA1_Channel1_IRQHandler 173 | .word DMA1_Channel2_IRQHandler 174 | .word DMA1_Channel3_IRQHandler 175 | .word DMA1_Channel4_IRQHandler 176 | .word DMA1_Channel5_IRQHandler 177 | .word DMA1_Channel6_IRQHandler 178 | .word DMA1_Channel7_IRQHandler 179 | .word ADC1_2_IRQHandler 180 | .word USB_HP_CAN1_TX_IRQHandler 181 | .word USB_LP_CAN1_RX0_IRQHandler 182 | .word CAN1_RX1_IRQHandler 183 | .word CAN1_SCE_IRQHandler 184 | .word EXTI9_5_IRQHandler 185 | .word TIM1_BRK_IRQHandler 186 | .word TIM1_UP_IRQHandler 187 | .word TIM1_TRG_COM_IRQHandler 188 | .word TIM1_CC_IRQHandler 189 | .word TIM2_IRQHandler 190 | .word TIM3_IRQHandler 191 | .word TIM4_IRQHandler 192 | .word I2C1_EV_IRQHandler 193 | .word I2C1_ER_IRQHandler 194 | .word I2C2_EV_IRQHandler 195 | .word I2C2_ER_IRQHandler 196 | .word SPI1_IRQHandler 197 | .word SPI2_IRQHandler 198 | .word USART1_IRQHandler 199 | .word USART2_IRQHandler 200 | .word USART3_IRQHandler 201 | .word EXTI15_10_IRQHandler 202 | .word RTC_Alarm_IRQHandler 203 | .word USBWakeUp_IRQHandler 204 | .word 0 205 | .word 0 206 | .word 0 207 | .word 0 208 | .word 0 209 | .word 0 210 | .word 0 211 | .word BootRAM /* @0x108. This is for boot in RAM mode for 212 | STM32F10x Medium Density devices. */ 213 | 214 | /******************************************************************************* 215 | * 216 | * Provide weak aliases for each Exception handler to the Default_Handler. 217 | * As they are weak aliases, any function with the same name will override 218 | * this definition. 219 | * 220 | *******************************************************************************/ 221 | 222 | .weak NMI_Handler 223 | .thumb_set NMI_Handler,Default_Handler 224 | 225 | .weak HardFault_Handler 226 | .thumb_set HardFault_Handler,Default_Handler 227 | 228 | .weak MemManage_Handler 229 | .thumb_set MemManage_Handler,Default_Handler 230 | 231 | .weak BusFault_Handler 232 | .thumb_set BusFault_Handler,Default_Handler 233 | 234 | .weak UsageFault_Handler 235 | .thumb_set UsageFault_Handler,Default_Handler 236 | 237 | .weak SVC_Handler 238 | .thumb_set SVC_Handler,Default_Handler 239 | 240 | .weak DebugMon_Handler 241 | .thumb_set DebugMon_Handler,Default_Handler 242 | 243 | .weak PendSV_Handler 244 | .thumb_set PendSV_Handler,Default_Handler 245 | 246 | .weak SysTick_Handler 247 | .thumb_set SysTick_Handler,Default_Handler 248 | 249 | .weak WWDG_IRQHandler 250 | .thumb_set WWDG_IRQHandler,Default_Handler 251 | 252 | .weak PVD_IRQHandler 253 | .thumb_set PVD_IRQHandler,Default_Handler 254 | 255 | .weak TAMPER_IRQHandler 256 | .thumb_set TAMPER_IRQHandler,Default_Handler 257 | 258 | .weak RTC_IRQHandler 259 | .thumb_set RTC_IRQHandler,Default_Handler 260 | 261 | .weak FLASH_IRQHandler 262 | .thumb_set FLASH_IRQHandler,Default_Handler 263 | 264 | .weak RCC_IRQHandler 265 | .thumb_set RCC_IRQHandler,Default_Handler 266 | 267 | .weak EXTI0_IRQHandler 268 | .thumb_set EXTI0_IRQHandler,Default_Handler 269 | 270 | .weak EXTI1_IRQHandler 271 | .thumb_set EXTI1_IRQHandler,Default_Handler 272 | 273 | .weak EXTI2_IRQHandler 274 | .thumb_set EXTI2_IRQHandler,Default_Handler 275 | 276 | .weak EXTI3_IRQHandler 277 | .thumb_set EXTI3_IRQHandler,Default_Handler 278 | 279 | .weak EXTI4_IRQHandler 280 | .thumb_set EXTI4_IRQHandler,Default_Handler 281 | 282 | .weak DMA1_Channel1_IRQHandler 283 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 284 | 285 | .weak DMA1_Channel2_IRQHandler 286 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 287 | 288 | .weak DMA1_Channel3_IRQHandler 289 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 290 | 291 | .weak DMA1_Channel4_IRQHandler 292 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 293 | 294 | .weak DMA1_Channel5_IRQHandler 295 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 296 | 297 | .weak DMA1_Channel6_IRQHandler 298 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 299 | 300 | .weak DMA1_Channel7_IRQHandler 301 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 302 | 303 | .weak ADC1_2_IRQHandler 304 | .thumb_set ADC1_2_IRQHandler,Default_Handler 305 | 306 | .weak USB_HP_CAN1_TX_IRQHandler 307 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 308 | 309 | .weak USB_LP_CAN1_RX0_IRQHandler 310 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 311 | 312 | .weak CAN1_RX1_IRQHandler 313 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 314 | 315 | .weak CAN1_SCE_IRQHandler 316 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 317 | 318 | .weak EXTI9_5_IRQHandler 319 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 320 | 321 | .weak TIM1_BRK_IRQHandler 322 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 323 | 324 | .weak TIM1_UP_IRQHandler 325 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 326 | 327 | .weak TIM1_TRG_COM_IRQHandler 328 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 329 | 330 | .weak TIM1_CC_IRQHandler 331 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 332 | 333 | .weak TIM2_IRQHandler 334 | .thumb_set TIM2_IRQHandler,Default_Handler 335 | 336 | .weak TIM3_IRQHandler 337 | .thumb_set TIM3_IRQHandler,Default_Handler 338 | 339 | .weak TIM4_IRQHandler 340 | .thumb_set TIM4_IRQHandler,Default_Handler 341 | 342 | .weak I2C1_EV_IRQHandler 343 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 344 | 345 | .weak I2C1_ER_IRQHandler 346 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 347 | 348 | .weak I2C2_EV_IRQHandler 349 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 350 | 351 | .weak I2C2_ER_IRQHandler 352 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 353 | 354 | .weak SPI1_IRQHandler 355 | .thumb_set SPI1_IRQHandler,Default_Handler 356 | 357 | .weak SPI2_IRQHandler 358 | .thumb_set SPI2_IRQHandler,Default_Handler 359 | 360 | .weak USART1_IRQHandler 361 | .thumb_set USART1_IRQHandler,Default_Handler 362 | 363 | .weak USART2_IRQHandler 364 | .thumb_set USART2_IRQHandler,Default_Handler 365 | 366 | .weak USART3_IRQHandler 367 | .thumb_set USART3_IRQHandler,Default_Handler 368 | 369 | .weak EXTI15_10_IRQHandler 370 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 371 | 372 | .weak RTC_Alarm_IRQHandler 373 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 374 | 375 | .weak USBWakeUp_IRQHandler 376 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 377 | 378 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 379 | 380 | -------------------------------------------------------------------------------- /stm32f103-vgaText Debug.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | -------------------------------------------------------------------------------- /stm32f103-vgaText Release.cfg: -------------------------------------------------------------------------------- 1 | # This is an genericBoard board with a single STM32F103C8Tx chip 2 | # 3 | # Generated by STM32CubeIDE 4 | # Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) 5 | 6 | source [find interface/stlink-dap.cfg] 7 | 8 | 9 | set WORKAREASIZE 0x5000 10 | 11 | transport select "dapdirect_swd" 12 | 13 | set CHIPNAME STM32F103C8Tx 14 | set BOARDNAME genericBoard 15 | 16 | # Enable debug when in low power modes 17 | set ENABLE_LOW_POWER 1 18 | 19 | # Stop Watchdog counters when halt 20 | set STOP_WATCHDOG 1 21 | 22 | # STlink Debug clock frequency 23 | set CLOCK_FREQ 4000 24 | 25 | # Reset configuration 26 | # use software system reset if reset done 27 | reset_config none 28 | set CONNECT_UNDER_RESET 0 29 | set CORE_RESET 0 30 | 31 | # ACCESS PORT NUMBER 32 | set AP_NUM 0 33 | # GDB PORT 34 | set GDB_PORT 3333 35 | 36 | 37 | 38 | # BCTM CPU variables 39 | 40 | source [find target/stm32f1x.cfg] 41 | 42 | -------------------------------------------------------------------------------- /stm32f103-vgaText.cfg: -------------------------------------------------------------------------------- 1 | # This is an genericBoard board with a single STM32F103C8Tx chip 2 | # 3 | # Generated by STM32CubeIDE 4 | # Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) 5 | 6 | source [find interface/stlink-dap.cfg] 7 | 8 | 9 | set WORKAREASIZE 0x5000 10 | 11 | transport select "dapdirect_swd" 12 | 13 | set CHIPNAME STM32F103C8Tx 14 | set BOARDNAME genericBoard 15 | 16 | # Enable debug when in low power modes 17 | set ENABLE_LOW_POWER 1 18 | 19 | # Stop Watchdog counters when halt 20 | set STOP_WATCHDOG 1 21 | 22 | # STlink Debug clock frequency 23 | set CLOCK_FREQ 4000 24 | 25 | # Reset configuration 26 | # use software system reset if reset done 27 | reset_config none 28 | set CONNECT_UNDER_RESET 0 29 | set CORE_RESET 0 30 | 31 | # ACCESS PORT NUMBER 32 | set AP_NUM 0 33 | # GDB PORT 34 | set GDB_PORT 3333 35 | 36 | 37 | 38 | # BCTM CPU variables 39 | 40 | source [find target/stm32f1x.cfg] 41 | 42 | -------------------------------------------------------------------------------- /stm32f103-vgaText.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | File.Version=6 3 | KeepUserPlacement=false 4 | Mcu.Family=STM32F1 5 | Mcu.IP0=NVIC 6 | Mcu.IP1=RCC 7 | Mcu.IP2=RTC 8 | Mcu.IP3=SYS 9 | Mcu.IP4=TIM3 10 | Mcu.IPNb=5 11 | Mcu.Name=STM32F103C(8-B)Tx 12 | Mcu.Package=LQFP48 13 | Mcu.Pin0=PD0-OSC_IN 14 | Mcu.Pin1=PD1-OSC_OUT 15 | Mcu.Pin2=PA13 16 | Mcu.Pin3=PA14 17 | Mcu.Pin4=VP_RTC_VS_RTC_Activate 18 | Mcu.Pin5=VP_SYS_VS_Systick 19 | Mcu.Pin6=VP_TIM3_VS_ClockSourceINT 20 | Mcu.PinsNb=7 21 | Mcu.ThirdPartyNb=0 22 | Mcu.UserConstants= 23 | Mcu.UserName=STM32F103C8Tx 24 | MxCube.Version=6.3.0 25 | MxDb.Version=DB.6.0.30 26 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 27 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false 28 | NVIC.ForceEnableDMAVector=true 29 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 30 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false 31 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false 32 | NVIC.PendSV_IRQn=true\:1\:0\:true\:false\:true\:false\:false 33 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 34 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false 35 | NVIC.SysTick_IRQn=true\:1\:0\:true\:false\:true\:false\:true 36 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 37 | PA13.Mode=Serial_Wire 38 | PA13.Signal=SYS_JTMS-SWDIO 39 | PA14.Mode=Serial_Wire 40 | PA14.Signal=SYS_JTCK-SWCLK 41 | PD0-OSC_IN.Mode=HSE-External-Oscillator 42 | PD0-OSC_IN.Signal=RCC_OSC_IN 43 | PD1-OSC_OUT.Mode=HSE-External-Oscillator 44 | PD1-OSC_OUT.Signal=RCC_OSC_OUT 45 | PinOutPanel.RotationAngle=0 46 | ProjectManager.AskForMigrate=true 47 | ProjectManager.BackupPrevious=false 48 | ProjectManager.CompilerOptimize=6 49 | ProjectManager.ComputerToolchain=false 50 | ProjectManager.CoupleFile=false 51 | ProjectManager.CustomerFirmwarePackage= 52 | ProjectManager.DefaultFWLocation=true 53 | ProjectManager.DeletePrevious=true 54 | ProjectManager.DeviceId=STM32F103C8Tx 55 | ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 56 | ProjectManager.FreePins=false 57 | ProjectManager.HalAssertFull=false 58 | ProjectManager.HeapSize=0x000 59 | ProjectManager.KeepUserCode=true 60 | ProjectManager.LastFirmware=true 61 | ProjectManager.LibraryCopy=1 62 | ProjectManager.MainLocation=Src 63 | ProjectManager.NoMain=false 64 | ProjectManager.PreviousToolchain=STM32CubeIDE 65 | ProjectManager.ProjectBuild=false 66 | ProjectManager.ProjectFileName=stm32f103-vgaText.ioc 67 | ProjectManager.ProjectName=stm32f103-vgaText 68 | ProjectManager.RegisterCallBack= 69 | ProjectManager.StackSize=0x400 70 | ProjectManager.TargetToolchain=STM32CubeIDE 71 | ProjectManager.ToolChainLocation= 72 | ProjectManager.UnderRoot=true 73 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_RTC_Init-RTC-false-HAL-true,4-MX_TIM3_Init-TIM3-true-HAL-true 74 | RCC.ADCFreqValue=36000000 75 | RCC.AHBFreq_Value=72000000 76 | RCC.APB1CLKDivider=RCC_HCLK_DIV2 77 | RCC.APB1Freq_Value=36000000 78 | RCC.APB1TimFreq_Value=72000000 79 | RCC.APB2Freq_Value=72000000 80 | RCC.APB2TimFreq_Value=72000000 81 | RCC.FCLKCortexFreq_Value=72000000 82 | RCC.FamilyName=M 83 | RCC.HCLKFreq_Value=72000000 84 | RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,USBPrescaler,VCOOutput2Freq_Value 85 | RCC.MCOFreq_Value=72000000 86 | RCC.PLLCLKFreq_Value=72000000 87 | RCC.PLLMCOFreq_Value=36000000 88 | RCC.PLLMUL=RCC_PLL_MUL9 89 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 90 | RCC.RTCClockSelection=RCC_RTCCLKSOURCE_HSE_DIV128 91 | RCC.RTCFreq_Value=62500 92 | RCC.SYSCLKFreq_VALUE=72000000 93 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 94 | RCC.TimSysFreq_Value=72000000 95 | RCC.USBFreq_Value=48000000 96 | RCC.USBPrescaler=RCC_USBCLKSOURCE_PLL_DIV1_5 97 | RCC.VCOOutput2Freq_Value=8000000 98 | VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled 99 | VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate 100 | VP_SYS_VS_Systick.Mode=SysTick 101 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 102 | VP_TIM3_VS_ClockSourceINT.Mode=Internal 103 | VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT 104 | board=custom 105 | -------------------------------------------------------------------------------- /stm32f103-vgaText.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | -------------------------------------------------------------------------------- /stm32f103-vgaText.xml: -------------------------------------------------------------------------------- 1 | 2 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ]> 11 | 12 | 13 | stm32f103-vgaText 14 | SWD 15 | ST-Link 16 | stm32f103c8tx 17 | 18 | 19 | -------------------------------------------------------------------------------- /stm32f103-z80emu.xml: -------------------------------------------------------------------------------- 1 | 2 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ]> 11 | 12 | 13 | 14 | stm32f103-z80emu 15 | SWD 16 | ST-Link 17 | stm32f103c8tx 18 | 19 | 20 | --------------------------------------------------------------------------------