├── Kalmantb └── new │ ├── kalmantb.v │ └── transcript ├── sim_1 └── new │ └── kalmantb.v └── sources_1 ├── ip ├── div_gen_0 │ ├── cmodel │ │ ├── div_gen_v5_1_bitacc_cmodel_lin64.zip │ │ └── div_gen_v5_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ │ └── tb_div_gen_0.vhd │ ├── div_gen_0.dcp │ ├── div_gen_0.veo │ ├── div_gen_0.vho │ ├── div_gen_0.xci │ ├── div_gen_0.xml │ ├── div_gen_0_ooc.xdc │ ├── div_gen_0_sim_netlist.v │ ├── div_gen_0_sim_netlist.vhdl │ ├── div_gen_0_stub.v │ ├── div_gen_0_stub.vhdl │ ├── doc │ │ └── div_gen_v5_1_changelog.txt │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── div_gen_v5_1_vh_rfs.vhd │ │ ├── floating_point_v7_0_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_mult_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── sim │ │ └── div_gen_0.vhd │ └── synth │ │ └── div_gen_0.vhd ├── exponential │ ├── cmodel │ │ ├── floating_point_v7_1_bitacc_cmodel_lin64.zip │ │ └── floating_point_v7_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ │ └── tb_exponential.vhd │ ├── doc │ │ └── floating_point_v7_1_changelog.txt │ ├── exponential.dcp │ ├── exponential.veo │ ├── exponential.vho │ ├── exponential.xci │ ├── exponential.xml │ ├── exponential_ooc.xdc │ ├── exponential_sim_netlist.v │ ├── exponential_sim_netlist.vhdl │ ├── exponential_stub.v │ ├── exponential_stub.vhdl │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── floating_point_v7_1_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── sim │ │ └── exponential.vhd │ └── synth │ │ └── exponential.vhd ├── floating_point_0 │ ├── cmodel │ │ ├── floating_point_v7_1_bitacc_cmodel_lin64.zip │ │ └── floating_point_v7_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ │ └── tb_floating_point_0.vhd │ ├── doc │ │ └── floating_point_v7_1_changelog.txt │ ├── floating_point_0.dcp │ ├── floating_point_0.veo │ ├── floating_point_0.vho │ ├── floating_point_0.xci │ ├── floating_point_0.xml │ ├── floating_point_0_ooc.xdc │ ├── floating_point_0_sim_netlist.v │ ├── floating_point_0_sim_netlist.vhdl │ ├── floating_point_0_stub.v │ ├── floating_point_0_stub.vhdl │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── floating_point_v7_1_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── sim │ │ └── floating_point_0.vhd │ └── synth │ │ └── floating_point_0.vhd ├── floating_point_1 │ ├── cmodel │ │ ├── floating_point_v7_1_bitacc_cmodel_lin64.zip │ │ └── floating_point_v7_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ │ └── tb_floating_point_1.vhd │ ├── doc │ │ └── floating_point_v7_1_changelog.txt │ ├── floating_point_1.dcp │ ├── floating_point_1.veo │ ├── floating_point_1.vho │ ├── floating_point_1.xci │ ├── floating_point_1.xml │ ├── floating_point_1_ooc.xdc │ ├── floating_point_1_sim_netlist.v │ ├── floating_point_1_sim_netlist.vhdl │ ├── floating_point_1_stub.v │ ├── floating_point_1_stub.vhdl │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── floating_point_v7_1_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── sim │ │ └── floating_point_1.vhd │ └── synth │ │ └── floating_point_1.vhd ├── multip │ ├── cmodel │ │ ├── floating_point_v7_1_bitacc_cmodel_lin64.zip │ │ └── floating_point_v7_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ │ └── tb_multip.vhd │ ├── doc │ │ └── floating_point_v7_1_changelog.txt │ ├── hdl │ │ ├── axi_utils_v2_0_vh_rfs.vhd │ │ ├── floating_point_v7_1_vh_rfs.vhd │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── multip.dcp │ ├── multip.veo │ ├── multip.vho │ ├── multip.xci │ ├── multip.xml │ ├── multip_ooc.xdc │ ├── multip_sim_netlist.v │ ├── multip_sim_netlist.vhdl │ ├── multip_stub.v │ ├── multip_stub.vhdl │ ├── sim │ │ └── multip.vhd │ └── synth │ │ └── multip.vhd └── subtractorip │ ├── cmodel │ ├── floating_point_v7_1_bitacc_cmodel_lin64.zip │ └── floating_point_v7_1_bitacc_cmodel_nt64.zip │ ├── demo_tb │ └── tb_subtractorip.vhd │ ├── doc │ └── floating_point_v7_1_changelog.txt │ ├── hdl │ ├── axi_utils_v2_0_vh_rfs.vhd │ ├── floating_point_v7_1_vh_rfs.vhd │ ├── mult_gen_v12_0_vh_rfs.vhd │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ ├── xbip_dsp48_addsub_v3_0_vh_rfs.vhd │ ├── xbip_dsp48_multadd_v3_0_vh_rfs.vhd │ ├── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ └── xbip_utils_v3_0_vh_rfs.vhd │ ├── sim │ └── subtractorip.vhd │ ├── subtractorip.dcp │ ├── subtractorip.veo │ ├── subtractorip.vho │ ├── subtractorip.xci │ ├── subtractorip.xml │ ├── subtractorip_ooc.xdc │ ├── subtractorip_sim_netlist.v │ ├── subtractorip_sim_netlist.vhdl │ ├── subtractorip_stub.v │ ├── subtractorip_stub.vhdl │ └── synth │ └── subtractorip.vhd └── new ├── Hwrappercode.v ├── adderwrapper.v ├── dividertb.v ├── dividerwrapper.v ├── equationfile.v ├── kalmanalu.v ├── multwrapper.v └── subtractorwrapper.v /Kalmantb/new/kalmantb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ps 3 | module kalmantb(); 4 | 5 | wire signed [31:0] Hin,resultd,resulta,resultm,results,resultf,uofk,vrefofk; 6 | reg signed [31:0] dataa,datab,datac; 7 | reg clock,reset,validdataa,validdatab,validdatac,readyo,readyb; 8 | reg uvalid,Vrefofkvalid; 9 | 10 | 11 | 12 | /* equationfile tbf( 13 | .clock(clock), 14 | .dataa(dataa), 15 | .validdataa(validdataa), 16 | .validdatab(validdatab), 17 | .validdatac(validdatac), 18 | // .readyo(readyo), 19 | //.readyb(readyb), 20 | .datab(datab), 21 | .datac(datac), 22 | .result(resultf)); 23 | /*dividerwrapper tb2( 24 | .clock(clock), 25 | .dataa(dataa), 26 | .validdataa(validdataa), 27 | .validdatab(validdatab), 28 | // .readyo(readyo), 29 | //.readyb(readyb), 30 | .datab(datab), 31 | .result(resultd)); 32 | 33 | adderwrapper tb212( 34 | .clock(clock), 35 | .dataa(dataa), 36 | .validdataa(validdataa), 37 | .validdatab(validdatab), 38 | // .readyo(readyo), 39 | //.readyb(readyb), 40 | .datab(datab), 41 | .result(resulta)); 42 | 43 | multwrapper tb3( 44 | .clock(clock), 45 | .dataa(dataa), 46 | .validdataa(validdataa), 47 | .validdatab(validdatab), 48 | // .readyo(readyo), 49 | //.readyb(readyb), 50 | .datab(datab), 51 | .result(resultm)); 52 | 53 | subtractorwrapper tb4( 54 | .clock(clock), 55 | .dataa(dataa), 56 | .validdataa(validdataa), 57 | .validdatab(validdatab), 58 | // .readyo(readyo), 59 | //.readyb(readyb), 60 | .datab(datab), 61 | .result(results)); 62 | */ 63 | 64 | /*Hwrappercode dut11 65 | ( 66 | .Hin(Hin), 67 | .clock(clock), 68 | .reset(reset) 69 | ); 70 | */ 71 | kalmanalu testunit1( 72 | .Yout(Yout), 73 | //input [31:0] k, 74 | .clock(clock), 75 | .uofk(uofk), 76 | .vrefofk(vrefofk), 77 | .uvalid(uvalid), 78 | .Vrefofkvalid(Vrefofkvalid), 79 | .reset(reset) 80 | ); 81 | 82 | 83 | 84 | 85 | 86 | 87 | initial 88 | begin 89 | clock = 1'b0; 90 | /*datab = 32'd0; 91 | dataa = 32'd0; 92 | datac = 32'd0; 93 | //readyo= 1'b0; 94 | validdataa = 1'b0; 95 | validdatab = 1'b0; 96 | validdatac = 1'b0; 97 | //readya = 1'b0; 98 | //readyb = 1'b0;*/ 99 | 100 | /* 101 | dataa = 32'h0x40066666;//2.1 102 | datab = 32'h0x4059999a;//3.4 103 | datac = 32'h0x3dcccccd;//0.1 104 | validdataa = 1'b1; 105 | validdatab = 1'b1; 106 | validdatac = 1'b1; 107 | //readyo = 1'b0; 108 | //readya = 1'b1; 109 | //readyb = 1'b1; 110 | 111 | 112 | #50 113 | dataa = 32'h0x3e4ccccd;//0.2 114 | datab = 32'h0x3e99999a;//0.3 115 | datac = 32'h0x3f000000;//0.5 116 | validdataa = 1'b1; 117 | validdatab = 1'b1; 118 | validdatac = 1'b1; 119 | #50 120 | dataa = 32'h0x40066666;//2.1 121 | datab = 32'h0x4059999a;//3.4 122 | datac = 32'h0x3dcccccd;//0.1 123 | validdataa = 1'b1; 124 | validdatab = 1'b1; 125 | validdatac = 1'b1; 126 | #50 127 | dataa = 32'h0x3e4ccccd;//0.2 128 | datab = 32'h0x3e99999a;//0.3 129 | datac = 32'h0x3f000000;//0.5 130 | validdataa = 1'b1; 131 | validdatab = 1'b1; 132 | validdatac = 1'b1; 133 | #50 134 | dataa = 32'h0x40066666;//2.1 135 | datab = 32'h0x4059999a;//3.4 136 | datac = 32'h0x3dcccccd;//0.1 137 | validdataa = 1'b1; 138 | validdatab = 1'b1; 139 | validdatac = 1'b1; 140 | #50 141 | dataa = 32'h0x3e4ccccd;//0.2 142 | datab = 32'h0x3e99999a;//0.3 143 | datac = 32'h0x3f000000;//0.5 144 | validdataa = 1'b1; 145 | validdatab = 1'b1; 146 | validdatac = 1'b1; 147 | #50 148 | dataa = 32'h0x40066666;//2.1 149 | datab = 32'h0x4059999a;//3.4 150 | datac = 32'h0x3dcccccd;//0.1 151 | validdataa = 1'b1; 152 | validdatab = 1'b1; 153 | validdatac = 1'b1; 154 | #50 155 | dataa = 32'h0x3e4ccccd;//0.2 156 | datab = 32'h0x3e99999a;//0.3 157 | datac = 32'h0x3f000000;//0.5 158 | validdataa = 1'b1; 159 | validdatab = 1'b1; 160 | validdatac = 1'b1; 161 | #50 162 | dataa = 32'h0x40066666;//2.1 163 | datab = 32'h0x4059999a;//3.4 164 | datac = 32'h0x3dcccccd;//0.1 165 | validdataa = 1'b1; 166 | validdatab = 1'b1; 167 | validdatac = 1'b1; 168 | #50 169 | dataa = 32'h0x3e4ccccd;//0.2 170 | datab = 32'h0x3e99999a;//0.3 171 | datac = 32'h0x3f000000;//0.5 172 | validdataa = 1'b1; 173 | validdatab = 1'b1; 174 | validdatac = 1'b1; 175 | /*dataa = 32'b01000000100001100110011001100110; 176 | datab = 32'b01000000000001100110011001100110; 177 | validdataa = 1'b1; 178 | validdatab = 1'b1; 179 | //readya = 1'b0; 180 | //readyb = 1'b0;*/ 181 | reset = 1'b1; 182 | #1000 183 | reset = 1'b0; 184 | 185 | //interation one 186 | #20 187 | uvalid <= 1'b1; 188 | Vrefofkvalid <= 1'b1; 189 | vrefofk <= 32'h3f0a3d71; //0.54 190 | 191 | uofk <=32'd0;//0 192 | 193 | #20 194 | uvalid <= 1'b1; 195 | Vrefofkvalid <= 1'b1; 196 | vrefofk <= 32'h3f0a3d71; //0.54 197 | 198 | uofk <=32'd0;//0 199 | 200 | #20 201 | uvalid <= 1'b1; 202 | Vrefofkvalid <= 1'b1; 203 | vrefofk <= 32'h3f0a3d71; //0.54 204 | 205 | uofk <=32'h40751d15;//3.83 206 | #20 207 | uvalid <= 1'b1; 208 | Vrefofkvalid <= 1'b1; 209 | vrefofk <= 32'h3f4aacda; //0.79 210 | 211 | uofk <=32'h40751d15;//3.83 212 | 213 | #20 214 | uvalid <= 1'b1; 215 | Vrefofkvalid <= 1'b1; 216 | vrefofk <= 32'h3f8ccccd; //1.1 217 | 218 | uofk <=32'h40751d15;//3.83 219 | //readya = 1'b0; 220 | //readyb = 1'b0; 221 | $finish; 222 | 223 | 224 | 225 | end 226 | always 227 | begin 228 | #10 clock = ~clock; 229 | end 230 | endmodule 231 | -------------------------------------------------------------------------------- /Kalmantb/new/transcript: -------------------------------------------------------------------------------- 1 | # Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl 2 | # OpenFile C:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/Kalmantb/new/kalmantb.v 3 | -------------------------------------------------------------------------------- /sim_1/new/kalmantb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/11/2016 05:39:24 PM 7 | // Design Name: 8 | // Module Name: kalmantb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module kalmantb( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/cmodel/div_gen_v5_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/div_gen_0/cmodel/div_gen_v5_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/cmodel/div_gen_v5_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/div_gen_0/cmodel/div_gen_v5_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/div_gen_0/div_gen_0.dcp -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:div_gen:5.1 50 | // IP Revision: 11 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | div_gen_0 your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_divisor_tvalid(s_axis_divisor_tvalid), // input wire s_axis_divisor_tvalid 60 | .s_axis_divisor_tready(s_axis_divisor_tready), // output wire s_axis_divisor_tready 61 | .s_axis_divisor_tdata(s_axis_divisor_tdata), // input wire [31 : 0] s_axis_divisor_tdata 62 | .s_axis_dividend_tvalid(s_axis_dividend_tvalid), // input wire s_axis_dividend_tvalid 63 | .s_axis_dividend_tready(s_axis_dividend_tready), // output wire s_axis_dividend_tready 64 | .s_axis_dividend_tdata(s_axis_dividend_tdata), // input wire [31 : 0] s_axis_dividend_tdata 65 | .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid 66 | .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata 67 | ); 68 | // INST_TAG_END ------ End INSTANTIATION Template --------- 69 | 70 | // You must compile the wrapper file div_gen_0.v when simulating 71 | // the core, div_gen_0. When compiling the wrapper file, be sure to 72 | // reference the Verilog simulation library. 73 | 74 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:div_gen:5.1 50 | -- IP Revision: 11 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT div_gen_0 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_divisor_tvalid : IN STD_LOGIC; 59 | s_axis_divisor_tready : OUT STD_LOGIC; 60 | s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 61 | s_axis_dividend_tvalid : IN STD_LOGIC; 62 | s_axis_dividend_tready : OUT STD_LOGIC; 63 | s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 64 | m_axis_dout_tvalid : OUT STD_LOGIC; 65 | m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) 66 | ); 67 | END COMPONENT; 68 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 69 | 70 | -- The following code must appear in the VHDL architecture 71 | -- body. Substitute your own instance name and net names. 72 | 73 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 74 | your_instance_name : div_gen_0 75 | PORT MAP ( 76 | aclk => aclk, 77 | s_axis_divisor_tvalid => s_axis_divisor_tvalid, 78 | s_axis_divisor_tready => s_axis_divisor_tready, 79 | s_axis_divisor_tdata => s_axis_divisor_tdata, 80 | s_axis_dividend_tvalid => s_axis_dividend_tvalid, 81 | s_axis_dividend_tready => s_axis_dividend_tready, 82 | s_axis_dividend_tdata => s_axis_dividend_tdata, 83 | m_axis_dout_tvalid => m_axis_dout_tvalid, 84 | m_axis_dout_tdata => m_axis_dout_tdata 85 | ); 86 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 87 | 88 | -- You must compile the wrapper file div_gen_0.vhd when simulating 89 | -- the core, div_gen_0. When compiling the wrapper file, be sure to 90 | -- reference the VHDL simulation library. 91 | 92 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | div_gen_0 10 | 11 | 12 | 1000000 13 | 1 14 | 0 15 | 0 16 | 0 17 | 0 18 | 0 19 | 0 20 | 0 21 | 1 22 | 48 23 | 1 24 | 32 25 | 1 26 | 32 27 | 1 28 | 4 29 | 0 30 | virtex7 31 | 1 32 | 32 33 | 32 34 | 1 35 | 11 36 | 1 37 | false 38 | false 39 | div_gen_0 40 | Blocking 41 | Performance 42 | Null 43 | false 44 | Radix2 45 | 1 46 | false 47 | 32 48 | false 49 | false 50 | 1 51 | false 52 | false 53 | 1 54 | 32 55 | 11 56 | 1 57 | Manual 58 | Signed 59 | Fractional 60 | virtex7 61 | 62 | xc7vx485t 63 | ffg1157 64 | VERILOG 65 | 66 | VERILOG 67 | -1 68 | 69 | TRUE 70 | TRUE 71 | IP_Flow 72 | 11 73 | TRUE 74 | . 75 | 76 | . 77 | 2016.3 78 | OUT_OF_CONTEXT 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 1000 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Fri Dec 09 13:58:33 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // C:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/div_gen_0/div_gen_0_stub.v 8 | // Design : div_gen_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "div_gen_v5_1_11,Vivado 2016.3" *) 17 | module div_gen_0(aclk, s_axis_divisor_tvalid, 18 | s_axis_divisor_tready, s_axis_divisor_tdata, s_axis_dividend_tvalid, 19 | s_axis_dividend_tready, s_axis_dividend_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) 20 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_divisor_tvalid,s_axis_divisor_tready,s_axis_divisor_tdata[31:0],s_axis_dividend_tvalid,s_axis_dividend_tready,s_axis_dividend_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]" */; 21 | input aclk; 22 | input s_axis_divisor_tvalid; 23 | output s_axis_divisor_tready; 24 | input [31:0]s_axis_divisor_tdata; 25 | input s_axis_dividend_tvalid; 26 | output s_axis_dividend_tready; 27 | input [31:0]s_axis_dividend_tdata; 28 | output m_axis_dout_tvalid; 29 | output [47:0]m_axis_dout_tdata; 30 | endmodule 31 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/div_gen_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Fri Dec 09 13:58:33 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- C:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/div_gen_0/div_gen_0_stub.vhdl 8 | -- Design : div_gen_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity div_gen_0 is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_divisor_tvalid : in STD_LOGIC; 19 | s_axis_divisor_tready : out STD_LOGIC; 20 | s_axis_divisor_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 21 | s_axis_dividend_tvalid : in STD_LOGIC; 22 | s_axis_dividend_tready : out STD_LOGIC; 23 | s_axis_dividend_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 24 | m_axis_dout_tvalid : out STD_LOGIC; 25 | m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 47 downto 0 ) 26 | ); 27 | 28 | end div_gen_0; 29 | 30 | architecture stub of div_gen_0 is 31 | attribute syn_black_box : boolean; 32 | attribute black_box_pad_pin : string; 33 | attribute syn_black_box of stub : architecture is true; 34 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_divisor_tvalid,s_axis_divisor_tready,s_axis_divisor_tdata[31:0],s_axis_dividend_tvalid,s_axis_dividend_tready,s_axis_dividend_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]"; 35 | attribute x_core_info : string; 36 | attribute x_core_info of stub : architecture is "div_gen_v5_1_11,Vivado 2016.3"; 37 | begin 38 | end; 39 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/doc/div_gen_v5_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 5.1 (Rev. 11) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 5.1 (Rev. 10) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 5.1 (Rev. 10) 12 | * Fix in common c model utilities package for handling of arrays of real types in Matlab 13 | * Revision change in one or more subcores 14 | 15 | 2015.4.2: 16 | * Version 5.1 (Rev. 9) 17 | * No changes 18 | 19 | 2015.4.1: 20 | * Version 5.1 (Rev. 9) 21 | * No changes 22 | 23 | 2015.4: 24 | * Version 5.1 (Rev. 9) 25 | * Revision change in one or more subcores 26 | 27 | 2015.3: 28 | * Version 5.1 (Rev. 8) 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Revision change in one or more subcores 31 | 32 | 2015.2.1: 33 | * Version 5.1 (Rev. 7) 34 | * No changes 35 | 36 | 2015.2: 37 | * Version 5.1 (Rev. 7) 38 | * Addition of MEX wrapper demonstration file. 39 | 40 | 2015.1: 41 | * Version 5.1 (Rev. 6) 42 | * GUI Fix. When using High Radix Divisor Width restricted to a range of [4-64]. No functional change. 43 | * Non-functional change to bip_sdivider_synth.vhd to fix low latency cases of the LutMult architecture. 44 | * Add Matlab MEX wrapper for the C model. 45 | * Addition of Beta support for future devices 46 | * Supported devices and production status are now determined automatically, to simplify support for future devices 47 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 48 | 49 | 2014.4.1: 50 | * Version 5.1 (Rev. 5) 51 | * No changes 52 | 53 | 2014.4: 54 | * Version 5.1 (Rev. 5) 55 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 56 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 57 | 58 | 2014.3: 59 | * Version 5.1 (Rev. 4) 60 | * GUI fix. When using High Radix, changes to Latency Configuration did enable or disable Latency as expected. No functional changes. 61 | 62 | 2014.2: 63 | * Version 5.1 (Rev. 3) 64 | * Disabled unnecessary assertions which triggered incorrectly when low latency serial dividers were simulated. No functional changes. 65 | 66 | 2014.1: 67 | * Version 5.1 (Rev. 2) 68 | * C models for Windows are compiled using Microsoft Visual Studio 2012 69 | * Internal device family name change, no functional changes 70 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 71 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 72 | * Support for Virtex Ultrascale devices at Pre-Production Status 73 | * VCS version H-2013.06-sp1 may cause errors or mismatches between behavioral sim and post- netlists. VCS version I-2014.03-Beta1 or later is recommended. 74 | 75 | 2013.4: 76 | * Version 5.1 (Rev. 1) 77 | * Clock constraint removed from supplied out of context xdc file for cases with no registers 78 | * ACLKEN and ARESETN disabled and set to false on GUI when Latency is set to 0 79 | * Support for Kintex Ultrascale devices at Pre-Production Status 80 | 81 | 2013.3: 82 | * Version 5.1 83 | * Addition of LUT-Mult architecture 84 | * Addition of configurable latency to Radix 2 architecture 85 | * Addition of C model 86 | * Internal standardization in source file delivery, does not change behavior 87 | * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status 88 | * Added support for Cadence IES and Synopsys VCS simulators 89 | * Added default constraints for out of context flow 90 | * Added support for IP Integrator 91 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 92 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 93 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 94 | 95 | 2013.2: 96 | * Version 5.0 (Rev. 1) 97 | * Support for Series 7 devices at Production status 98 | * Beta support for future devices 99 | * Removing support for Defense Grade Low Power Artix7 100 | 101 | 2013.1: 102 | * Version 5.0 103 | * Native Vivado Release 104 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 105 | 106 | (c) Copyright 2002 - 2016 Xilinx, Inc. All rights reserved. 107 | 108 | This file contains confidential and proprietary information 109 | of Xilinx, Inc. and is protected under U.S. and 110 | international copyright and other intellectual property 111 | laws. 112 | 113 | DISCLAIMER 114 | This disclaimer is not a license and does not grant any 115 | rights to the materials distributed herewith. Except as 116 | otherwise provided in a valid license issued to you by 117 | Xilinx, and to the maximum extent permitted by applicable 118 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 119 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 120 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 121 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 122 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 123 | (2) Xilinx shall not be liable (whether in contract or tort, 124 | including negligence, or under any other theory of 125 | liability) for any loss or damage of any kind or nature 126 | related to, arising under or in connection with these 127 | materials, including for any direct, or any indirect, 128 | special, incidental, or consequential loss or damage 129 | (including loss of data, profits, goodwill, or any type of 130 | loss or damage suffered as a result of any action brought 131 | by a third party) even if such damage or loss was 132 | reasonably foreseeable or Xilinx had been advised of the 133 | possibility of the same. 134 | 135 | CRITICAL APPLICATIONS 136 | Xilinx products are not designed or intended to be fail- 137 | safe, or for use in any application requiring fail-safe 138 | performance, such as life-support or safety devices or 139 | systems, Class III medical devices, nuclear facilities, 140 | applications related to the deployment of airbags, or any 141 | other applications that could lead to death, personal 142 | injury, or severe property or environmental damage 143 | (individually and collectively, "Critical 144 | Applications"). Customer assumes the sole risk and 145 | liability of any use of Xilinx products in Critical 146 | Applications, subject only to applicable laws and 147 | regulations governing limitations on product liability. 148 | 149 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 150 | PART OF THIS FILE AT ALL TIMES. 151 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/sim/div_gen_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:div_gen:5.1 50 | -- IP Revision: 11 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY div_gen_v5_1_11; 57 | USE div_gen_v5_1_11.div_gen_v5_1_11; 58 | 59 | ENTITY div_gen_0 IS 60 | PORT ( 61 | aclk : IN STD_LOGIC; 62 | s_axis_divisor_tvalid : IN STD_LOGIC; 63 | s_axis_divisor_tready : OUT STD_LOGIC; 64 | s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 65 | s_axis_dividend_tvalid : IN STD_LOGIC; 66 | s_axis_dividend_tready : OUT STD_LOGIC; 67 | s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 68 | m_axis_dout_tvalid : OUT STD_LOGIC; 69 | m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) 70 | ); 71 | END div_gen_0; 72 | 73 | ARCHITECTURE div_gen_0_arch OF div_gen_0 IS 74 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 75 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF div_gen_0_arch: ARCHITECTURE IS "yes"; 76 | COMPONENT div_gen_v5_1_11 IS 77 | GENERIC ( 78 | C_XDEVICEFAMILY : STRING; 79 | C_HAS_ARESETN : INTEGER; 80 | C_HAS_ACLKEN : INTEGER; 81 | C_LATENCY : INTEGER; 82 | ALGORITHM_TYPE : INTEGER; 83 | DIVISOR_WIDTH : INTEGER; 84 | DIVIDEND_WIDTH : INTEGER; 85 | SIGNED_B : INTEGER; 86 | DIVCLK_SEL : INTEGER; 87 | FRACTIONAL_B : INTEGER; 88 | FRACTIONAL_WIDTH : INTEGER; 89 | C_HAS_DIV_BY_ZERO : INTEGER; 90 | C_THROTTLE_SCHEME : INTEGER; 91 | C_TLAST_RESOLUTION : INTEGER; 92 | C_HAS_S_AXIS_DIVISOR_TUSER : INTEGER; 93 | C_HAS_S_AXIS_DIVISOR_TLAST : INTEGER; 94 | C_S_AXIS_DIVISOR_TDATA_WIDTH : INTEGER; 95 | C_S_AXIS_DIVISOR_TUSER_WIDTH : INTEGER; 96 | C_HAS_S_AXIS_DIVIDEND_TUSER : INTEGER; 97 | C_HAS_S_AXIS_DIVIDEND_TLAST : INTEGER; 98 | C_S_AXIS_DIVIDEND_TDATA_WIDTH : INTEGER; 99 | C_S_AXIS_DIVIDEND_TUSER_WIDTH : INTEGER; 100 | C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; 101 | C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER 102 | ); 103 | PORT ( 104 | aclk : IN STD_LOGIC; 105 | aclken : IN STD_LOGIC; 106 | aresetn : IN STD_LOGIC; 107 | s_axis_divisor_tvalid : IN STD_LOGIC; 108 | s_axis_divisor_tready : OUT STD_LOGIC; 109 | s_axis_divisor_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 110 | s_axis_divisor_tlast : IN STD_LOGIC; 111 | s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 112 | s_axis_dividend_tvalid : IN STD_LOGIC; 113 | s_axis_dividend_tready : OUT STD_LOGIC; 114 | s_axis_dividend_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 115 | s_axis_dividend_tlast : IN STD_LOGIC; 116 | s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 117 | m_axis_dout_tvalid : OUT STD_LOGIC; 118 | m_axis_dout_tready : IN STD_LOGIC; 119 | m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); 120 | m_axis_dout_tlast : OUT STD_LOGIC; 121 | m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) 122 | ); 123 | END COMPONENT div_gen_v5_1_11; 124 | ATTRIBUTE X_INTERFACE_INFO : STRING; 125 | ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; 126 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TVALID"; 127 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TREADY"; 128 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TDATA"; 129 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TVALID"; 130 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TREADY"; 131 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TDATA"; 132 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; 133 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; 134 | BEGIN 135 | U0 : div_gen_v5_1_11 136 | GENERIC MAP ( 137 | C_XDEVICEFAMILY => "virtex7", 138 | C_HAS_ARESETN => 0, 139 | C_HAS_ACLKEN => 0, 140 | C_LATENCY => 1, 141 | ALGORITHM_TYPE => 1, 142 | DIVISOR_WIDTH => 32, 143 | DIVIDEND_WIDTH => 32, 144 | SIGNED_B => 1, 145 | DIVCLK_SEL => 1, 146 | FRACTIONAL_B => 1, 147 | FRACTIONAL_WIDTH => 11, 148 | C_HAS_DIV_BY_ZERO => 0, 149 | C_THROTTLE_SCHEME => 4, 150 | C_TLAST_RESOLUTION => 0, 151 | C_HAS_S_AXIS_DIVISOR_TUSER => 0, 152 | C_HAS_S_AXIS_DIVISOR_TLAST => 0, 153 | C_S_AXIS_DIVISOR_TDATA_WIDTH => 32, 154 | C_S_AXIS_DIVISOR_TUSER_WIDTH => 1, 155 | C_HAS_S_AXIS_DIVIDEND_TUSER => 0, 156 | C_HAS_S_AXIS_DIVIDEND_TLAST => 0, 157 | C_S_AXIS_DIVIDEND_TDATA_WIDTH => 32, 158 | C_S_AXIS_DIVIDEND_TUSER_WIDTH => 1, 159 | C_M_AXIS_DOUT_TDATA_WIDTH => 48, 160 | C_M_AXIS_DOUT_TUSER_WIDTH => 1 161 | ) 162 | PORT MAP ( 163 | aclk => aclk, 164 | aclken => '1', 165 | aresetn => '1', 166 | s_axis_divisor_tvalid => s_axis_divisor_tvalid, 167 | s_axis_divisor_tready => s_axis_divisor_tready, 168 | s_axis_divisor_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 169 | s_axis_divisor_tlast => '0', 170 | s_axis_divisor_tdata => s_axis_divisor_tdata, 171 | s_axis_dividend_tvalid => s_axis_dividend_tvalid, 172 | s_axis_dividend_tready => s_axis_dividend_tready, 173 | s_axis_dividend_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 174 | s_axis_dividend_tlast => '0', 175 | s_axis_dividend_tdata => s_axis_dividend_tdata, 176 | m_axis_dout_tvalid => m_axis_dout_tvalid, 177 | m_axis_dout_tready => '0', 178 | m_axis_dout_tdata => m_axis_dout_tdata 179 | ); 180 | END div_gen_0_arch; 181 | -------------------------------------------------------------------------------- /sources_1/ip/div_gen_0/synth/div_gen_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:div_gen:5.1 50 | -- IP Revision: 11 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY div_gen_v5_1_11; 57 | USE div_gen_v5_1_11.div_gen_v5_1_11; 58 | 59 | ENTITY div_gen_0 IS 60 | PORT ( 61 | aclk : IN STD_LOGIC; 62 | s_axis_divisor_tvalid : IN STD_LOGIC; 63 | s_axis_divisor_tready : OUT STD_LOGIC; 64 | s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 65 | s_axis_dividend_tvalid : IN STD_LOGIC; 66 | s_axis_dividend_tready : OUT STD_LOGIC; 67 | s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 68 | m_axis_dout_tvalid : OUT STD_LOGIC; 69 | m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) 70 | ); 71 | END div_gen_0; 72 | 73 | ARCHITECTURE div_gen_0_arch OF div_gen_0 IS 74 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 75 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF div_gen_0_arch: ARCHITECTURE IS "yes"; 76 | COMPONENT div_gen_v5_1_11 IS 77 | GENERIC ( 78 | C_XDEVICEFAMILY : STRING; 79 | C_HAS_ARESETN : INTEGER; 80 | C_HAS_ACLKEN : INTEGER; 81 | C_LATENCY : INTEGER; 82 | ALGORITHM_TYPE : INTEGER; 83 | DIVISOR_WIDTH : INTEGER; 84 | DIVIDEND_WIDTH : INTEGER; 85 | SIGNED_B : INTEGER; 86 | DIVCLK_SEL : INTEGER; 87 | FRACTIONAL_B : INTEGER; 88 | FRACTIONAL_WIDTH : INTEGER; 89 | C_HAS_DIV_BY_ZERO : INTEGER; 90 | C_THROTTLE_SCHEME : INTEGER; 91 | C_TLAST_RESOLUTION : INTEGER; 92 | C_HAS_S_AXIS_DIVISOR_TUSER : INTEGER; 93 | C_HAS_S_AXIS_DIVISOR_TLAST : INTEGER; 94 | C_S_AXIS_DIVISOR_TDATA_WIDTH : INTEGER; 95 | C_S_AXIS_DIVISOR_TUSER_WIDTH : INTEGER; 96 | C_HAS_S_AXIS_DIVIDEND_TUSER : INTEGER; 97 | C_HAS_S_AXIS_DIVIDEND_TLAST : INTEGER; 98 | C_S_AXIS_DIVIDEND_TDATA_WIDTH : INTEGER; 99 | C_S_AXIS_DIVIDEND_TUSER_WIDTH : INTEGER; 100 | C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; 101 | C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER 102 | ); 103 | PORT ( 104 | aclk : IN STD_LOGIC; 105 | aclken : IN STD_LOGIC; 106 | aresetn : IN STD_LOGIC; 107 | s_axis_divisor_tvalid : IN STD_LOGIC; 108 | s_axis_divisor_tready : OUT STD_LOGIC; 109 | s_axis_divisor_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 110 | s_axis_divisor_tlast : IN STD_LOGIC; 111 | s_axis_divisor_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 112 | s_axis_dividend_tvalid : IN STD_LOGIC; 113 | s_axis_dividend_tready : OUT STD_LOGIC; 114 | s_axis_dividend_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 115 | s_axis_dividend_tlast : IN STD_LOGIC; 116 | s_axis_dividend_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 117 | m_axis_dout_tvalid : OUT STD_LOGIC; 118 | m_axis_dout_tready : IN STD_LOGIC; 119 | m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); 120 | m_axis_dout_tlast : OUT STD_LOGIC; 121 | m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) 122 | ); 123 | END COMPONENT div_gen_v5_1_11; 124 | ATTRIBUTE X_CORE_INFO : STRING; 125 | ATTRIBUTE X_CORE_INFO OF div_gen_0_arch: ARCHITECTURE IS "div_gen_v5_1_11,Vivado 2016.3"; 126 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 127 | ATTRIBUTE CHECK_LICENSE_TYPE OF div_gen_0_arch : ARCHITECTURE IS "div_gen_0,div_gen_v5_1_11,{}"; 128 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 129 | ATTRIBUTE CORE_GENERATION_INFO OF div_gen_0_arch: ARCHITECTURE IS "div_gen_0,div_gen_v5_1_11,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=div_gen,x_ipVersion=5.1,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_XDEVICEFAMILY=virtex7,C_HAS_ARESETN=0,C_HAS_ACLKEN=0,C_LATENCY=1,ALGORITHM_TYPE=1,DIVISOR_WIDTH=32,DIVIDEND_WIDTH=32,SIGNED_B=1,DIVCLK_SEL=1,FRACTIONAL_B=1,FRACTIONAL_WIDTH=11,C_HAS_DIV_BY_ZERO=0,C_THROTTLE_SCHEME=4,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_DIVISOR_TUSER=0,C_HAS_S_AXIS_DIVISOR_TLAST=0,C_S_AXIS_DIVISO" & 130 | "R_TDATA_WIDTH=32,C_S_AXIS_DIVISOR_TUSER_WIDTH=1,C_HAS_S_AXIS_DIVIDEND_TUSER=0,C_HAS_S_AXIS_DIVIDEND_TLAST=0,C_S_AXIS_DIVIDEND_TDATA_WIDTH=32,C_S_AXIS_DIVIDEND_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=48,C_M_AXIS_DOUT_TUSER_WIDTH=1}"; 131 | ATTRIBUTE X_INTERFACE_INFO : STRING; 132 | ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; 133 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TVALID"; 134 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TREADY"; 135 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_divisor_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVISOR TDATA"; 136 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TVALID"; 137 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TREADY"; 138 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_dividend_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DIVIDEND TDATA"; 139 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; 140 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; 141 | BEGIN 142 | U0 : div_gen_v5_1_11 143 | GENERIC MAP ( 144 | C_XDEVICEFAMILY => "virtex7", 145 | C_HAS_ARESETN => 0, 146 | C_HAS_ACLKEN => 0, 147 | C_LATENCY => 1, 148 | ALGORITHM_TYPE => 1, 149 | DIVISOR_WIDTH => 32, 150 | DIVIDEND_WIDTH => 32, 151 | SIGNED_B => 1, 152 | DIVCLK_SEL => 1, 153 | FRACTIONAL_B => 1, 154 | FRACTIONAL_WIDTH => 11, 155 | C_HAS_DIV_BY_ZERO => 0, 156 | C_THROTTLE_SCHEME => 4, 157 | C_TLAST_RESOLUTION => 0, 158 | C_HAS_S_AXIS_DIVISOR_TUSER => 0, 159 | C_HAS_S_AXIS_DIVISOR_TLAST => 0, 160 | C_S_AXIS_DIVISOR_TDATA_WIDTH => 32, 161 | C_S_AXIS_DIVISOR_TUSER_WIDTH => 1, 162 | C_HAS_S_AXIS_DIVIDEND_TUSER => 0, 163 | C_HAS_S_AXIS_DIVIDEND_TLAST => 0, 164 | C_S_AXIS_DIVIDEND_TDATA_WIDTH => 32, 165 | C_S_AXIS_DIVIDEND_TUSER_WIDTH => 1, 166 | C_M_AXIS_DOUT_TDATA_WIDTH => 48, 167 | C_M_AXIS_DOUT_TUSER_WIDTH => 1 168 | ) 169 | PORT MAP ( 170 | aclk => aclk, 171 | aclken => '1', 172 | aresetn => '1', 173 | s_axis_divisor_tvalid => s_axis_divisor_tvalid, 174 | s_axis_divisor_tready => s_axis_divisor_tready, 175 | s_axis_divisor_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 176 | s_axis_divisor_tlast => '0', 177 | s_axis_divisor_tdata => s_axis_divisor_tdata, 178 | s_axis_dividend_tvalid => s_axis_dividend_tvalid, 179 | s_axis_dividend_tready => s_axis_dividend_tready, 180 | s_axis_dividend_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 181 | s_axis_dividend_tlast => '0', 182 | s_axis_dividend_tdata => s_axis_dividend_tdata, 183 | m_axis_dout_tvalid => m_axis_dout_tvalid, 184 | m_axis_dout_tready => '0', 185 | m_axis_dout_tdata => m_axis_dout_tdata 186 | ); 187 | END div_gen_0_arch; 188 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/exponential/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/exponential/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/exponential/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/exponential/doc/floating_point_v7_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 7.1 (Rev. 3) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 7.1 (Rev. 2) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 7.1 (Rev. 2) 12 | * Revision change in one or more subcores 13 | 14 | 2015.4.2: 15 | * Version 7.1 (Rev. 1) 16 | * No changes 17 | 18 | 2015.4.1: 19 | * Version 7.1 (Rev. 1) 20 | * No changes 21 | 22 | 2015.4: 23 | * Version 7.1 (Rev. 1) 24 | * Revision change in one or more subcores 25 | 26 | 2015.3: 27 | * Version 7.1 28 | * Added optimizations for half precision operators. 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com. 31 | * Added support for fixed-to-float conversions from uint32, uint64 and int64 formats. 32 | * Added medium DSP48 usage option for single-precision Add/Subtract 33 | * Revision change in one or more subcores 34 | 35 | 2015.2.1: 36 | * Version 7.0 (Rev. 9) 37 | * No changes 38 | 39 | 2015.2: 40 | * Version 7.0 (Rev. 9) 41 | * Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles. 42 | * Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes. 43 | * Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes. 44 | 45 | 2015.1: 46 | * Version 7.0 (Rev. 8) 47 | * Addition of Beta support for 16nm devices 48 | * Supported devices and production status are now determined automatically, to simplify support for future devices 49 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 50 | * Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons 51 | 52 | 2014.4.1: 53 | * Version 7.0 (Rev. 7) 54 | * No changes 55 | 56 | 2014.4: 57 | * Version 7.0 (Rev. 7) 58 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 59 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 60 | 61 | 2014.3: 62 | * Version 7.0 (Rev. 6) 63 | * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 64 | * Disabled debug assertions which were written to transcript during simulation, no functional changes. 65 | * Fixed C model to prevent crashes that could occur on 32-bit Windows platform. 66 | 67 | 2014.2: 68 | * Version 7.0 (Rev. 5) 69 | * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 70 | * Removed component statement for DSP48E2, no functional changes 71 | * Internal change management process enhancements, no functional changes 72 | 73 | 2014.1: 74 | * Version 7.0 (Rev. 4) 75 | * GUI fix to disable internal debug messages from Accumulator 76 | * Core will now deliver an ooc_xdc file, without constraints, when latency is zero. 77 | * C models for Windows are compiled using Microsoft Visual Studio 2012 78 | * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected. 79 | * Internal device family name change, no functional changes 80 | * Corrected parameter order and comments for Accumulator operator in allfns.c 81 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 82 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 83 | * Support for Virtex Ultrascale devices at Pre-Production Status 84 | * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged. 85 | 86 | 2013.4: 87 | * Version 7.0 (Rev. 3) 88 | * Missing tooltips added to GUI 89 | * GUI fix for possible illegal Latency values 90 | * Support for Kintex Ultrascale devices at Pre-Production Status 91 | 92 | 2013.3: 93 | * Version 7.0 (Rev. 2) 94 | * Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. 95 | * Cosmetic GUI changes to table header row, no change in functionality 96 | * Added additional support for future devices 97 | * Behavioral VHDL model replaced by Encrypted RTL 98 | * Internal standardization in source file delivery, does not change behavior 99 | * Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defence Grade Zynq and Lower Power Artix7 devices at Production Status 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | * Added default constraints for out of context flow 102 | * Added support for IP Integrator 103 | * Optimized support for UltraScale devices 104 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 105 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 106 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 107 | * C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 108 | 109 | 2013.2: 110 | * Version 7.0 (Rev. 1) 111 | * Support for Series 7 devices at Production status 112 | * Added STL portability library to the C model zip files, to support the example code 113 | * Beta support for future devices 114 | * Removing support for Defense Grade Low Power Artix7 115 | 116 | 2013.1: 117 | * Version 7.0 118 | * Native Vivado Release 119 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 120 | 121 | (c) Copyright 2005 - 2016 Xilinx, Inc. All rights reserved. 122 | 123 | This file contains confidential and proprietary information 124 | of Xilinx, Inc. and is protected under U.S. and 125 | international copyright and other intellectual property 126 | laws. 127 | 128 | DISCLAIMER 129 | This disclaimer is not a license and does not grant any 130 | rights to the materials distributed herewith. Except as 131 | otherwise provided in a valid license issued to you by 132 | Xilinx, and to the maximum extent permitted by applicable 133 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 134 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 135 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 136 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 137 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 138 | (2) Xilinx shall not be liable (whether in contract or tort, 139 | including negligence, or under any other theory of 140 | liability) for any loss or damage of any kind or nature 141 | related to, arising under or in connection with these 142 | materials, including for any direct, or any indirect, 143 | special, incidental, or consequential loss or damage 144 | (including loss of data, profits, goodwill, or any type of 145 | loss or damage suffered as a result of any action brought 146 | by a third party) even if such damage or loss was 147 | reasonably foreseeable or Xilinx had been advised of the 148 | possibility of the same. 149 | 150 | CRITICAL APPLICATIONS 151 | Xilinx products are not designed or intended to be fail- 152 | safe, or for use in any application requiring fail-safe 153 | performance, such as life-support or safety devices or 154 | systems, Class III medical devices, nuclear facilities, 155 | applications related to the deployment of airbags, or any 156 | other applications that could lead to death, personal 157 | injury, or severe property or environmental damage 158 | (individually and collectively, "Critical 159 | Applications"). Customer assumes the sole risk and 160 | liability of any use of Xilinx products in Critical 161 | Applications, subject only to applicable laws and 162 | regulations governing limitations on product liability. 163 | 164 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 165 | PART OF THIS FILE AT ALL TIMES. 166 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/exponential/exponential.dcp -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:floating_point:7.1 50 | // IP Revision: 3 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | exponential your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid 60 | .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata 61 | .m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid 62 | .m_axis_result_tdata(m_axis_result_tdata) // output wire [31 : 0] m_axis_result_tdata 63 | ); 64 | // INST_TAG_END ------ End INSTANTIATION Template --------- 65 | 66 | // You must compile the wrapper file exponential.v when simulating 67 | // the core, exponential. When compiling the wrapper file, be sure to 68 | // reference the Verilog simulation library. 69 | 70 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT exponential 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_a_tvalid : IN STD_LOGIC; 59 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 60 | m_axis_result_tvalid : OUT STD_LOGIC; 61 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 62 | ); 63 | END COMPONENT; 64 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 65 | 66 | -- The following code must appear in the VHDL architecture 67 | -- body. Substitute your own instance name and net names. 68 | 69 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 70 | your_instance_name : exponential 71 | PORT MAP ( 72 | aclk => aclk, 73 | s_axis_a_tvalid => s_axis_a_tvalid, 74 | s_axis_a_tdata => s_axis_a_tdata, 75 | m_axis_result_tvalid => m_axis_result_tvalid, 76 | m_axis_result_tdata => m_axis_result_tdata 77 | ); 78 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 79 | 80 | -- You must compile the wrapper file exponential.vhd when simulating 81 | -- the core, exponential. When compiling the wrapper file, be sure to 82 | -- reference the VHDL simulation library. 83 | 84 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 100 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Sun Dec 11 09:36:10 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/exponential/exponential_stub.v 8 | // Design : exponential 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "floating_point_v7_1_3,Vivado 2016.3" *) 17 | module exponential(aclk, s_axis_a_tvalid, s_axis_a_tdata, 18 | m_axis_result_tvalid, m_axis_result_tdata) 19 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]" */; 20 | input aclk; 21 | input s_axis_a_tvalid; 22 | input [31:0]s_axis_a_tdata; 23 | output m_axis_result_tvalid; 24 | output [31:0]m_axis_result_tdata; 25 | endmodule 26 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/exponential_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Sun Dec 11 09:36:10 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/exponential/exponential_stub.vhdl 8 | -- Design : exponential 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity exponential is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_a_tvalid : in STD_LOGIC; 19 | s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 20 | m_axis_result_tvalid : out STD_LOGIC; 21 | m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end exponential; 25 | 26 | architecture stub of exponential is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "floating_point_v7_1_3,Vivado 2016.3"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /sources_1/ip/exponential/sim/exponential.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY floating_point_v7_1_3; 57 | USE floating_point_v7_1_3.floating_point_v7_1_3; 58 | 59 | ENTITY exponential IS 60 | PORT ( 61 | aclk : IN STD_LOGIC; 62 | s_axis_a_tvalid : IN STD_LOGIC; 63 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 64 | m_axis_result_tvalid : OUT STD_LOGIC; 65 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 66 | ); 67 | END exponential; 68 | 69 | ARCHITECTURE exponential_arch OF exponential IS 70 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 71 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF exponential_arch: ARCHITECTURE IS "yes"; 72 | COMPONENT floating_point_v7_1_3 IS 73 | GENERIC ( 74 | C_XDEVICEFAMILY : STRING; 75 | C_HAS_ADD : INTEGER; 76 | C_HAS_SUBTRACT : INTEGER; 77 | C_HAS_MULTIPLY : INTEGER; 78 | C_HAS_DIVIDE : INTEGER; 79 | C_HAS_SQRT : INTEGER; 80 | C_HAS_COMPARE : INTEGER; 81 | C_HAS_FIX_TO_FLT : INTEGER; 82 | C_HAS_FLT_TO_FIX : INTEGER; 83 | C_HAS_FLT_TO_FLT : INTEGER; 84 | C_HAS_RECIP : INTEGER; 85 | C_HAS_RECIP_SQRT : INTEGER; 86 | C_HAS_ABSOLUTE : INTEGER; 87 | C_HAS_LOGARITHM : INTEGER; 88 | C_HAS_EXPONENTIAL : INTEGER; 89 | C_HAS_FMA : INTEGER; 90 | C_HAS_FMS : INTEGER; 91 | C_HAS_ACCUMULATOR_A : INTEGER; 92 | C_HAS_ACCUMULATOR_S : INTEGER; 93 | C_A_WIDTH : INTEGER; 94 | C_A_FRACTION_WIDTH : INTEGER; 95 | C_B_WIDTH : INTEGER; 96 | C_B_FRACTION_WIDTH : INTEGER; 97 | C_C_WIDTH : INTEGER; 98 | C_C_FRACTION_WIDTH : INTEGER; 99 | C_RESULT_WIDTH : INTEGER; 100 | C_RESULT_FRACTION_WIDTH : INTEGER; 101 | C_COMPARE_OPERATION : INTEGER; 102 | C_LATENCY : INTEGER; 103 | C_OPTIMIZATION : INTEGER; 104 | C_MULT_USAGE : INTEGER; 105 | C_BRAM_USAGE : INTEGER; 106 | C_RATE : INTEGER; 107 | C_ACCUM_INPUT_MSB : INTEGER; 108 | C_ACCUM_MSB : INTEGER; 109 | C_ACCUM_LSB : INTEGER; 110 | C_HAS_UNDERFLOW : INTEGER; 111 | C_HAS_OVERFLOW : INTEGER; 112 | C_HAS_INVALID_OP : INTEGER; 113 | C_HAS_DIVIDE_BY_ZERO : INTEGER; 114 | C_HAS_ACCUM_OVERFLOW : INTEGER; 115 | C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; 116 | C_HAS_ACLKEN : INTEGER; 117 | C_HAS_ARESETN : INTEGER; 118 | C_THROTTLE_SCHEME : INTEGER; 119 | C_HAS_A_TUSER : INTEGER; 120 | C_HAS_A_TLAST : INTEGER; 121 | C_HAS_B : INTEGER; 122 | C_HAS_B_TUSER : INTEGER; 123 | C_HAS_B_TLAST : INTEGER; 124 | C_HAS_C : INTEGER; 125 | C_HAS_C_TUSER : INTEGER; 126 | C_HAS_C_TLAST : INTEGER; 127 | C_HAS_OPERATION : INTEGER; 128 | C_HAS_OPERATION_TUSER : INTEGER; 129 | C_HAS_OPERATION_TLAST : INTEGER; 130 | C_HAS_RESULT_TUSER : INTEGER; 131 | C_HAS_RESULT_TLAST : INTEGER; 132 | C_TLAST_RESOLUTION : INTEGER; 133 | C_A_TDATA_WIDTH : INTEGER; 134 | C_A_TUSER_WIDTH : INTEGER; 135 | C_B_TDATA_WIDTH : INTEGER; 136 | C_B_TUSER_WIDTH : INTEGER; 137 | C_C_TDATA_WIDTH : INTEGER; 138 | C_C_TUSER_WIDTH : INTEGER; 139 | C_OPERATION_TDATA_WIDTH : INTEGER; 140 | C_OPERATION_TUSER_WIDTH : INTEGER; 141 | C_RESULT_TDATA_WIDTH : INTEGER; 142 | C_RESULT_TUSER_WIDTH : INTEGER; 143 | C_FIXED_DATA_UNSIGNED : INTEGER 144 | ); 145 | PORT ( 146 | aclk : IN STD_LOGIC; 147 | aclken : IN STD_LOGIC; 148 | aresetn : IN STD_LOGIC; 149 | s_axis_a_tvalid : IN STD_LOGIC; 150 | s_axis_a_tready : OUT STD_LOGIC; 151 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 152 | s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 153 | s_axis_a_tlast : IN STD_LOGIC; 154 | s_axis_b_tvalid : IN STD_LOGIC; 155 | s_axis_b_tready : OUT STD_LOGIC; 156 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 157 | s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 158 | s_axis_b_tlast : IN STD_LOGIC; 159 | s_axis_c_tvalid : IN STD_LOGIC; 160 | s_axis_c_tready : OUT STD_LOGIC; 161 | s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 162 | s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 163 | s_axis_c_tlast : IN STD_LOGIC; 164 | s_axis_operation_tvalid : IN STD_LOGIC; 165 | s_axis_operation_tready : OUT STD_LOGIC; 166 | s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 167 | s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 168 | s_axis_operation_tlast : IN STD_LOGIC; 169 | m_axis_result_tvalid : OUT STD_LOGIC; 170 | m_axis_result_tready : IN STD_LOGIC; 171 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 172 | m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); 173 | m_axis_result_tlast : OUT STD_LOGIC 174 | ); 175 | END COMPONENT floating_point_v7_1_3; 176 | ATTRIBUTE X_INTERFACE_INFO : STRING; 177 | ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; 178 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; 179 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; 180 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; 181 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; 182 | BEGIN 183 | U0 : floating_point_v7_1_3 184 | GENERIC MAP ( 185 | C_XDEVICEFAMILY => "virtex7", 186 | C_HAS_ADD => 0, 187 | C_HAS_SUBTRACT => 0, 188 | C_HAS_MULTIPLY => 0, 189 | C_HAS_DIVIDE => 0, 190 | C_HAS_SQRT => 0, 191 | C_HAS_COMPARE => 0, 192 | C_HAS_FIX_TO_FLT => 0, 193 | C_HAS_FLT_TO_FIX => 0, 194 | C_HAS_FLT_TO_FLT => 0, 195 | C_HAS_RECIP => 0, 196 | C_HAS_RECIP_SQRT => 0, 197 | C_HAS_ABSOLUTE => 0, 198 | C_HAS_LOGARITHM => 0, 199 | C_HAS_EXPONENTIAL => 1, 200 | C_HAS_FMA => 0, 201 | C_HAS_FMS => 0, 202 | C_HAS_ACCUMULATOR_A => 0, 203 | C_HAS_ACCUMULATOR_S => 0, 204 | C_A_WIDTH => 32, 205 | C_A_FRACTION_WIDTH => 24, 206 | C_B_WIDTH => 32, 207 | C_B_FRACTION_WIDTH => 24, 208 | C_C_WIDTH => 32, 209 | C_C_FRACTION_WIDTH => 24, 210 | C_RESULT_WIDTH => 32, 211 | C_RESULT_FRACTION_WIDTH => 24, 212 | C_COMPARE_OPERATION => 8, 213 | C_LATENCY => 1, 214 | C_OPTIMIZATION => 1, 215 | C_MULT_USAGE => 1, 216 | C_BRAM_USAGE => 0, 217 | C_RATE => 1, 218 | C_ACCUM_INPUT_MSB => 32, 219 | C_ACCUM_MSB => 32, 220 | C_ACCUM_LSB => -31, 221 | C_HAS_UNDERFLOW => 0, 222 | C_HAS_OVERFLOW => 0, 223 | C_HAS_INVALID_OP => 0, 224 | C_HAS_DIVIDE_BY_ZERO => 0, 225 | C_HAS_ACCUM_OVERFLOW => 0, 226 | C_HAS_ACCUM_INPUT_OVERFLOW => 0, 227 | C_HAS_ACLKEN => 0, 228 | C_HAS_ARESETN => 0, 229 | C_THROTTLE_SCHEME => 3, 230 | C_HAS_A_TUSER => 0, 231 | C_HAS_A_TLAST => 0, 232 | C_HAS_B => 0, 233 | C_HAS_B_TUSER => 0, 234 | C_HAS_B_TLAST => 0, 235 | C_HAS_C => 0, 236 | C_HAS_C_TUSER => 0, 237 | C_HAS_C_TLAST => 0, 238 | C_HAS_OPERATION => 0, 239 | C_HAS_OPERATION_TUSER => 0, 240 | C_HAS_OPERATION_TLAST => 0, 241 | C_HAS_RESULT_TUSER => 0, 242 | C_HAS_RESULT_TLAST => 0, 243 | C_TLAST_RESOLUTION => 0, 244 | C_A_TDATA_WIDTH => 32, 245 | C_A_TUSER_WIDTH => 1, 246 | C_B_TDATA_WIDTH => 32, 247 | C_B_TUSER_WIDTH => 1, 248 | C_C_TDATA_WIDTH => 32, 249 | C_C_TUSER_WIDTH => 1, 250 | C_OPERATION_TDATA_WIDTH => 8, 251 | C_OPERATION_TUSER_WIDTH => 1, 252 | C_RESULT_TDATA_WIDTH => 32, 253 | C_RESULT_TUSER_WIDTH => 1, 254 | C_FIXED_DATA_UNSIGNED => 0 255 | ) 256 | PORT MAP ( 257 | aclk => aclk, 258 | aclken => '1', 259 | aresetn => '1', 260 | s_axis_a_tvalid => s_axis_a_tvalid, 261 | s_axis_a_tdata => s_axis_a_tdata, 262 | s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 263 | s_axis_a_tlast => '0', 264 | s_axis_b_tvalid => '0', 265 | s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), 266 | s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 267 | s_axis_b_tlast => '0', 268 | s_axis_c_tvalid => '0', 269 | s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), 270 | s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 271 | s_axis_c_tlast => '0', 272 | s_axis_operation_tvalid => '0', 273 | s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), 274 | s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 275 | s_axis_operation_tlast => '0', 276 | m_axis_result_tvalid => m_axis_result_tvalid, 277 | m_axis_result_tready => '0', 278 | m_axis_result_tdata => m_axis_result_tdata 279 | ); 280 | END exponential_arch; 281 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_0/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_0/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/doc/floating_point_v7_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 7.1 (Rev. 3) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 7.1 (Rev. 2) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 7.1 (Rev. 2) 12 | * Revision change in one or more subcores 13 | 14 | 2015.4.2: 15 | * Version 7.1 (Rev. 1) 16 | * No changes 17 | 18 | 2015.4.1: 19 | * Version 7.1 (Rev. 1) 20 | * No changes 21 | 22 | 2015.4: 23 | * Version 7.1 (Rev. 1) 24 | * Revision change in one or more subcores 25 | 26 | 2015.3: 27 | * Version 7.1 28 | * Added optimizations for half precision operators. 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com. 31 | * Added support for fixed-to-float conversions from uint32, uint64 and int64 formats. 32 | * Added medium DSP48 usage option for single-precision Add/Subtract 33 | * Revision change in one or more subcores 34 | 35 | 2015.2.1: 36 | * Version 7.0 (Rev. 9) 37 | * No changes 38 | 39 | 2015.2: 40 | * Version 7.0 (Rev. 9) 41 | * Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles. 42 | * Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes. 43 | * Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes. 44 | 45 | 2015.1: 46 | * Version 7.0 (Rev. 8) 47 | * Addition of Beta support for 16nm devices 48 | * Supported devices and production status are now determined automatically, to simplify support for future devices 49 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 50 | * Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons 51 | 52 | 2014.4.1: 53 | * Version 7.0 (Rev. 7) 54 | * No changes 55 | 56 | 2014.4: 57 | * Version 7.0 (Rev. 7) 58 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 59 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 60 | 61 | 2014.3: 62 | * Version 7.0 (Rev. 6) 63 | * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 64 | * Disabled debug assertions which were written to transcript during simulation, no functional changes. 65 | * Fixed C model to prevent crashes that could occur on 32-bit Windows platform. 66 | 67 | 2014.2: 68 | * Version 7.0 (Rev. 5) 69 | * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 70 | * Removed component statement for DSP48E2, no functional changes 71 | * Internal change management process enhancements, no functional changes 72 | 73 | 2014.1: 74 | * Version 7.0 (Rev. 4) 75 | * GUI fix to disable internal debug messages from Accumulator 76 | * Core will now deliver an ooc_xdc file, without constraints, when latency is zero. 77 | * C models for Windows are compiled using Microsoft Visual Studio 2012 78 | * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected. 79 | * Internal device family name change, no functional changes 80 | * Corrected parameter order and comments for Accumulator operator in allfns.c 81 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 82 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 83 | * Support for Virtex Ultrascale devices at Pre-Production Status 84 | * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged. 85 | 86 | 2013.4: 87 | * Version 7.0 (Rev. 3) 88 | * Missing tooltips added to GUI 89 | * GUI fix for possible illegal Latency values 90 | * Support for Kintex Ultrascale devices at Pre-Production Status 91 | 92 | 2013.3: 93 | * Version 7.0 (Rev. 2) 94 | * Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. 95 | * Cosmetic GUI changes to table header row, no change in functionality 96 | * Added additional support for future devices 97 | * Behavioral VHDL model replaced by Encrypted RTL 98 | * Internal standardization in source file delivery, does not change behavior 99 | * Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defence Grade Zynq and Lower Power Artix7 devices at Production Status 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | * Added default constraints for out of context flow 102 | * Added support for IP Integrator 103 | * Optimized support for UltraScale devices 104 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 105 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 106 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 107 | * C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 108 | 109 | 2013.2: 110 | * Version 7.0 (Rev. 1) 111 | * Support for Series 7 devices at Production status 112 | * Added STL portability library to the C model zip files, to support the example code 113 | * Beta support for future devices 114 | * Removing support for Defense Grade Low Power Artix7 115 | 116 | 2013.1: 117 | * Version 7.0 118 | * Native Vivado Release 119 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 120 | 121 | (c) Copyright 2005 - 2016 Xilinx, Inc. All rights reserved. 122 | 123 | This file contains confidential and proprietary information 124 | of Xilinx, Inc. and is protected under U.S. and 125 | international copyright and other intellectual property 126 | laws. 127 | 128 | DISCLAIMER 129 | This disclaimer is not a license and does not grant any 130 | rights to the materials distributed herewith. Except as 131 | otherwise provided in a valid license issued to you by 132 | Xilinx, and to the maximum extent permitted by applicable 133 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 134 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 135 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 136 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 137 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 138 | (2) Xilinx shall not be liable (whether in contract or tort, 139 | including negligence, or under any other theory of 140 | liability) for any loss or damage of any kind or nature 141 | related to, arising under or in connection with these 142 | materials, including for any direct, or any indirect, 143 | special, incidental, or consequential loss or damage 144 | (including loss of data, profits, goodwill, or any type of 145 | loss or damage suffered as a result of any action brought 146 | by a third party) even if such damage or loss was 147 | reasonably foreseeable or Xilinx had been advised of the 148 | possibility of the same. 149 | 150 | CRITICAL APPLICATIONS 151 | Xilinx products are not designed or intended to be fail- 152 | safe, or for use in any application requiring fail-safe 153 | performance, such as life-support or safety devices or 154 | systems, Class III medical devices, nuclear facilities, 155 | applications related to the deployment of airbags, or any 156 | other applications that could lead to death, personal 157 | injury, or severe property or environmental damage 158 | (individually and collectively, "Critical 159 | Applications"). Customer assumes the sole risk and 160 | liability of any use of Xilinx products in Critical 161 | Applications, subject only to applicable laws and 162 | regulations governing limitations on product liability. 163 | 164 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 165 | PART OF THIS FILE AT ALL TIMES. 166 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_0/floating_point_0.dcp -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:floating_point:7.1 50 | // IP Revision: 3 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | floating_point_0 your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid 60 | .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata 61 | .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid 62 | .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata 63 | .m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid 64 | .m_axis_result_tdata(m_axis_result_tdata) // output wire [31 : 0] m_axis_result_tdata 65 | ); 66 | // INST_TAG_END ------ End INSTANTIATION Template --------- 67 | 68 | // You must compile the wrapper file floating_point_0.v when simulating 69 | // the core, floating_point_0. When compiling the wrapper file, be sure to 70 | // reference the Verilog simulation library. 71 | 72 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT floating_point_0 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_a_tvalid : IN STD_LOGIC; 59 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 60 | s_axis_b_tvalid : IN STD_LOGIC; 61 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | m_axis_result_tvalid : OUT STD_LOGIC; 63 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END COMPONENT; 66 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 67 | 68 | -- The following code must appear in the VHDL architecture 69 | -- body. Substitute your own instance name and net names. 70 | 71 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 72 | your_instance_name : floating_point_0 73 | PORT MAP ( 74 | aclk => aclk, 75 | s_axis_a_tvalid => s_axis_a_tvalid, 76 | s_axis_a_tdata => s_axis_a_tdata, 77 | s_axis_b_tvalid => s_axis_b_tvalid, 78 | s_axis_b_tdata => s_axis_b_tdata, 79 | m_axis_result_tvalid => m_axis_result_tvalid, 80 | m_axis_result_tdata => m_axis_result_tdata 81 | ); 82 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 83 | 84 | -- You must compile the wrapper file floating_point_0.vhd when simulating 85 | -- the core, floating_point_0. When compiling the wrapper file, be sure to 86 | -- reference the VHDL simulation library. 87 | 88 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 100 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Fri Dec 09 15:16:44 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/floating_point_0/floating_point_0_stub.v 8 | // Design : floating_point_0 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "floating_point_v7_1_3,Vivado 2016.3" *) 17 | module floating_point_0(aclk, s_axis_a_tvalid, s_axis_a_tdata, 18 | s_axis_b_tvalid, s_axis_b_tdata, m_axis_result_tvalid, m_axis_result_tdata) 19 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]" */; 20 | input aclk; 21 | input s_axis_a_tvalid; 22 | input [31:0]s_axis_a_tdata; 23 | input s_axis_b_tvalid; 24 | input [31:0]s_axis_b_tdata; 25 | output m_axis_result_tvalid; 26 | output [31:0]m_axis_result_tdata; 27 | endmodule 28 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_0/floating_point_0_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Fri Dec 09 15:16:44 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/floating_point_0/floating_point_0_stub.vhdl 8 | -- Design : floating_point_0 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity floating_point_0 is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_a_tvalid : in STD_LOGIC; 19 | s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 20 | s_axis_b_tvalid : in STD_LOGIC; 21 | s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 22 | m_axis_result_tvalid : out STD_LOGIC; 23 | m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) 24 | ); 25 | 26 | end floating_point_0; 27 | 28 | architecture stub of floating_point_0 is 29 | attribute syn_black_box : boolean; 30 | attribute black_box_pad_pin : string; 31 | attribute syn_black_box of stub : architecture is true; 32 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]"; 33 | attribute x_core_info : string; 34 | attribute x_core_info of stub : architecture is "floating_point_v7_1_3,Vivado 2016.3"; 35 | begin 36 | end; 37 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_1/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_1/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/doc/floating_point_v7_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 7.1 (Rev. 3) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 7.1 (Rev. 2) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 7.1 (Rev. 2) 12 | * Revision change in one or more subcores 13 | 14 | 2015.4.2: 15 | * Version 7.1 (Rev. 1) 16 | * No changes 17 | 18 | 2015.4.1: 19 | * Version 7.1 (Rev. 1) 20 | * No changes 21 | 22 | 2015.4: 23 | * Version 7.1 (Rev. 1) 24 | * Revision change in one or more subcores 25 | 26 | 2015.3: 27 | * Version 7.1 28 | * Added optimizations for half precision operators. 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com. 31 | * Added support for fixed-to-float conversions from uint32, uint64 and int64 formats. 32 | * Added medium DSP48 usage option for single-precision Add/Subtract 33 | * Revision change in one or more subcores 34 | 35 | 2015.2.1: 36 | * Version 7.0 (Rev. 9) 37 | * No changes 38 | 39 | 2015.2: 40 | * Version 7.0 (Rev. 9) 41 | * Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles. 42 | * Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes. 43 | * Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes. 44 | 45 | 2015.1: 46 | * Version 7.0 (Rev. 8) 47 | * Addition of Beta support for 16nm devices 48 | * Supported devices and production status are now determined automatically, to simplify support for future devices 49 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 50 | * Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons 51 | 52 | 2014.4.1: 53 | * Version 7.0 (Rev. 7) 54 | * No changes 55 | 56 | 2014.4: 57 | * Version 7.0 (Rev. 7) 58 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 59 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 60 | 61 | 2014.3: 62 | * Version 7.0 (Rev. 6) 63 | * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 64 | * Disabled debug assertions which were written to transcript during simulation, no functional changes. 65 | * Fixed C model to prevent crashes that could occur on 32-bit Windows platform. 66 | 67 | 2014.2: 68 | * Version 7.0 (Rev. 5) 69 | * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 70 | * Removed component statement for DSP48E2, no functional changes 71 | * Internal change management process enhancements, no functional changes 72 | 73 | 2014.1: 74 | * Version 7.0 (Rev. 4) 75 | * GUI fix to disable internal debug messages from Accumulator 76 | * Core will now deliver an ooc_xdc file, without constraints, when latency is zero. 77 | * C models for Windows are compiled using Microsoft Visual Studio 2012 78 | * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected. 79 | * Internal device family name change, no functional changes 80 | * Corrected parameter order and comments for Accumulator operator in allfns.c 81 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 82 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 83 | * Support for Virtex Ultrascale devices at Pre-Production Status 84 | * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged. 85 | 86 | 2013.4: 87 | * Version 7.0 (Rev. 3) 88 | * Missing tooltips added to GUI 89 | * GUI fix for possible illegal Latency values 90 | * Support for Kintex Ultrascale devices at Pre-Production Status 91 | 92 | 2013.3: 93 | * Version 7.0 (Rev. 2) 94 | * Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. 95 | * Cosmetic GUI changes to table header row, no change in functionality 96 | * Added additional support for future devices 97 | * Behavioral VHDL model replaced by Encrypted RTL 98 | * Internal standardization in source file delivery, does not change behavior 99 | * Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defence Grade Zynq and Lower Power Artix7 devices at Production Status 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | * Added default constraints for out of context flow 102 | * Added support for IP Integrator 103 | * Optimized support for UltraScale devices 104 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 105 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 106 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 107 | * C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 108 | 109 | 2013.2: 110 | * Version 7.0 (Rev. 1) 111 | * Support for Series 7 devices at Production status 112 | * Added STL portability library to the C model zip files, to support the example code 113 | * Beta support for future devices 114 | * Removing support for Defense Grade Low Power Artix7 115 | 116 | 2013.1: 117 | * Version 7.0 118 | * Native Vivado Release 119 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 120 | 121 | (c) Copyright 2005 - 2016 Xilinx, Inc. All rights reserved. 122 | 123 | This file contains confidential and proprietary information 124 | of Xilinx, Inc. and is protected under U.S. and 125 | international copyright and other intellectual property 126 | laws. 127 | 128 | DISCLAIMER 129 | This disclaimer is not a license and does not grant any 130 | rights to the materials distributed herewith. Except as 131 | otherwise provided in a valid license issued to you by 132 | Xilinx, and to the maximum extent permitted by applicable 133 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 134 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 135 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 136 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 137 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 138 | (2) Xilinx shall not be liable (whether in contract or tort, 139 | including negligence, or under any other theory of 140 | liability) for any loss or damage of any kind or nature 141 | related to, arising under or in connection with these 142 | materials, including for any direct, or any indirect, 143 | special, incidental, or consequential loss or damage 144 | (including loss of data, profits, goodwill, or any type of 145 | loss or damage suffered as a result of any action brought 146 | by a third party) even if such damage or loss was 147 | reasonably foreseeable or Xilinx had been advised of the 148 | possibility of the same. 149 | 150 | CRITICAL APPLICATIONS 151 | Xilinx products are not designed or intended to be fail- 152 | safe, or for use in any application requiring fail-safe 153 | performance, such as life-support or safety devices or 154 | systems, Class III medical devices, nuclear facilities, 155 | applications related to the deployment of airbags, or any 156 | other applications that could lead to death, personal 157 | injury, or severe property or environmental damage 158 | (individually and collectively, "Critical 159 | Applications"). Customer assumes the sole risk and 160 | liability of any use of Xilinx products in Critical 161 | Applications, subject only to applicable laws and 162 | regulations governing limitations on product liability. 163 | 164 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 165 | PART OF THIS FILE AT ALL TIMES. 166 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/floating_point_1/floating_point_1.dcp -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:floating_point:7.1 50 | // IP Revision: 3 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | floating_point_1 your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid 60 | .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata 61 | .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid 62 | .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata 63 | .m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid 64 | .m_axis_result_tdata(m_axis_result_tdata) // output wire [31 : 0] m_axis_result_tdata 65 | ); 66 | // INST_TAG_END ------ End INSTANTIATION Template --------- 67 | 68 | // You must compile the wrapper file floating_point_1.v when simulating 69 | // the core, floating_point_1. When compiling the wrapper file, be sure to 70 | // reference the Verilog simulation library. 71 | 72 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT floating_point_1 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_a_tvalid : IN STD_LOGIC; 59 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 60 | s_axis_b_tvalid : IN STD_LOGIC; 61 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | m_axis_result_tvalid : OUT STD_LOGIC; 63 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END COMPONENT; 66 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 67 | 68 | -- The following code must appear in the VHDL architecture 69 | -- body. Substitute your own instance name and net names. 70 | 71 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 72 | your_instance_name : floating_point_1 73 | PORT MAP ( 74 | aclk => aclk, 75 | s_axis_a_tvalid => s_axis_a_tvalid, 76 | s_axis_a_tdata => s_axis_a_tdata, 77 | s_axis_b_tvalid => s_axis_b_tvalid, 78 | s_axis_b_tdata => s_axis_b_tdata, 79 | m_axis_result_tvalid => m_axis_result_tvalid, 80 | m_axis_result_tdata => m_axis_result_tdata 81 | ); 82 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 83 | 84 | -- You must compile the wrapper file floating_point_1.vhd when simulating 85 | -- the core, floating_point_1. When compiling the wrapper file, be sure to 86 | -- reference the VHDL simulation library. 87 | 88 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 100 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Fri Dec 09 15:30:22 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/floating_point_1/floating_point_1_stub.v 8 | // Design : floating_point_1 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "floating_point_v7_1_3,Vivado 2016.3" *) 17 | module floating_point_1(aclk, s_axis_a_tvalid, s_axis_a_tdata, 18 | s_axis_b_tvalid, s_axis_b_tdata, m_axis_result_tvalid, m_axis_result_tdata) 19 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]" */; 20 | input aclk; 21 | input s_axis_a_tvalid; 22 | input [31:0]s_axis_a_tdata; 23 | input s_axis_b_tvalid; 24 | input [31:0]s_axis_b_tdata; 25 | output m_axis_result_tvalid; 26 | output [31:0]m_axis_result_tdata; 27 | endmodule 28 | -------------------------------------------------------------------------------- /sources_1/ip/floating_point_1/floating_point_1_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Fri Dec 09 15:30:22 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/floating_point_1/floating_point_1_stub.vhdl 8 | -- Design : floating_point_1 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity floating_point_1 is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_a_tvalid : in STD_LOGIC; 19 | s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 20 | s_axis_b_tvalid : in STD_LOGIC; 21 | s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 22 | m_axis_result_tvalid : out STD_LOGIC; 23 | m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) 24 | ); 25 | 26 | end floating_point_1; 27 | 28 | architecture stub of floating_point_1 is 29 | attribute syn_black_box : boolean; 30 | attribute black_box_pad_pin : string; 31 | attribute syn_black_box of stub : architecture is true; 32 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]"; 33 | attribute x_core_info : string; 34 | attribute x_core_info of stub : architecture is "floating_point_v7_1_3,Vivado 2016.3"; 35 | begin 36 | end; 37 | -------------------------------------------------------------------------------- /sources_1/ip/multip/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/multip/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/multip/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/multip/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/multip/doc/floating_point_v7_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 7.1 (Rev. 3) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 7.1 (Rev. 2) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 7.1 (Rev. 2) 12 | * Revision change in one or more subcores 13 | 14 | 2015.4.2: 15 | * Version 7.1 (Rev. 1) 16 | * No changes 17 | 18 | 2015.4.1: 19 | * Version 7.1 (Rev. 1) 20 | * No changes 21 | 22 | 2015.4: 23 | * Version 7.1 (Rev. 1) 24 | * Revision change in one or more subcores 25 | 26 | 2015.3: 27 | * Version 7.1 28 | * Added optimizations for half precision operators. 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com. 31 | * Added support for fixed-to-float conversions from uint32, uint64 and int64 formats. 32 | * Added medium DSP48 usage option for single-precision Add/Subtract 33 | * Revision change in one or more subcores 34 | 35 | 2015.2.1: 36 | * Version 7.0 (Rev. 9) 37 | * No changes 38 | 39 | 2015.2: 40 | * Version 7.0 (Rev. 9) 41 | * Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles. 42 | * Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes. 43 | * Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes. 44 | 45 | 2015.1: 46 | * Version 7.0 (Rev. 8) 47 | * Addition of Beta support for 16nm devices 48 | * Supported devices and production status are now determined automatically, to simplify support for future devices 49 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 50 | * Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons 51 | 52 | 2014.4.1: 53 | * Version 7.0 (Rev. 7) 54 | * No changes 55 | 56 | 2014.4: 57 | * Version 7.0 (Rev. 7) 58 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 59 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 60 | 61 | 2014.3: 62 | * Version 7.0 (Rev. 6) 63 | * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 64 | * Disabled debug assertions which were written to transcript during simulation, no functional changes. 65 | * Fixed C model to prevent crashes that could occur on 32-bit Windows platform. 66 | 67 | 2014.2: 68 | * Version 7.0 (Rev. 5) 69 | * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 70 | * Removed component statement for DSP48E2, no functional changes 71 | * Internal change management process enhancements, no functional changes 72 | 73 | 2014.1: 74 | * Version 7.0 (Rev. 4) 75 | * GUI fix to disable internal debug messages from Accumulator 76 | * Core will now deliver an ooc_xdc file, without constraints, when latency is zero. 77 | * C models for Windows are compiled using Microsoft Visual Studio 2012 78 | * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected. 79 | * Internal device family name change, no functional changes 80 | * Corrected parameter order and comments for Accumulator operator in allfns.c 81 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 82 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 83 | * Support for Virtex Ultrascale devices at Pre-Production Status 84 | * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged. 85 | 86 | 2013.4: 87 | * Version 7.0 (Rev. 3) 88 | * Missing tooltips added to GUI 89 | * GUI fix for possible illegal Latency values 90 | * Support for Kintex Ultrascale devices at Pre-Production Status 91 | 92 | 2013.3: 93 | * Version 7.0 (Rev. 2) 94 | * Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. 95 | * Cosmetic GUI changes to table header row, no change in functionality 96 | * Added additional support for future devices 97 | * Behavioral VHDL model replaced by Encrypted RTL 98 | * Internal standardization in source file delivery, does not change behavior 99 | * Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defence Grade Zynq and Lower Power Artix7 devices at Production Status 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | * Added default constraints for out of context flow 102 | * Added support for IP Integrator 103 | * Optimized support for UltraScale devices 104 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 105 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 106 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 107 | * C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 108 | 109 | 2013.2: 110 | * Version 7.0 (Rev. 1) 111 | * Support for Series 7 devices at Production status 112 | * Added STL portability library to the C model zip files, to support the example code 113 | * Beta support for future devices 114 | * Removing support for Defense Grade Low Power Artix7 115 | 116 | 2013.1: 117 | * Version 7.0 118 | * Native Vivado Release 119 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 120 | 121 | (c) Copyright 2005 - 2016 Xilinx, Inc. All rights reserved. 122 | 123 | This file contains confidential and proprietary information 124 | of Xilinx, Inc. and is protected under U.S. and 125 | international copyright and other intellectual property 126 | laws. 127 | 128 | DISCLAIMER 129 | This disclaimer is not a license and does not grant any 130 | rights to the materials distributed herewith. Except as 131 | otherwise provided in a valid license issued to you by 132 | Xilinx, and to the maximum extent permitted by applicable 133 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 134 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 135 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 136 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 137 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 138 | (2) Xilinx shall not be liable (whether in contract or tort, 139 | including negligence, or under any other theory of 140 | liability) for any loss or damage of any kind or nature 141 | related to, arising under or in connection with these 142 | materials, including for any direct, or any indirect, 143 | special, incidental, or consequential loss or damage 144 | (including loss of data, profits, goodwill, or any type of 145 | loss or damage suffered as a result of any action brought 146 | by a third party) even if such damage or loss was 147 | reasonably foreseeable or Xilinx had been advised of the 148 | possibility of the same. 149 | 150 | CRITICAL APPLICATIONS 151 | Xilinx products are not designed or intended to be fail- 152 | safe, or for use in any application requiring fail-safe 153 | performance, such as life-support or safety devices or 154 | systems, Class III medical devices, nuclear facilities, 155 | applications related to the deployment of airbags, or any 156 | other applications that could lead to death, personal 157 | injury, or severe property or environmental damage 158 | (individually and collectively, "Critical 159 | Applications"). Customer assumes the sole risk and 160 | liability of any use of Xilinx products in Critical 161 | Applications, subject only to applicable laws and 162 | regulations governing limitations on product liability. 163 | 164 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 165 | PART OF THIS FILE AT ALL TIMES. 166 | -------------------------------------------------------------------------------- /sources_1/ip/multip/multip.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/multip/multip.dcp -------------------------------------------------------------------------------- /sources_1/ip/multip/multip.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:floating_point:7.1 50 | // IP Revision: 3 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | multip your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid 60 | .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata 61 | .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid 62 | .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata 63 | .m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid 64 | .m_axis_result_tdata(m_axis_result_tdata) // output wire [31 : 0] m_axis_result_tdata 65 | ); 66 | // INST_TAG_END ------ End INSTANTIATION Template --------- 67 | 68 | // You must compile the wrapper file multip.v when simulating 69 | // the core, multip. When compiling the wrapper file, be sure to 70 | // reference the Verilog simulation library. 71 | 72 | -------------------------------------------------------------------------------- /sources_1/ip/multip/multip.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT multip 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_a_tvalid : IN STD_LOGIC; 59 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 60 | s_axis_b_tvalid : IN STD_LOGIC; 61 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | m_axis_result_tvalid : OUT STD_LOGIC; 63 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END COMPONENT; 66 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 67 | 68 | -- The following code must appear in the VHDL architecture 69 | -- body. Substitute your own instance name and net names. 70 | 71 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 72 | your_instance_name : multip 73 | PORT MAP ( 74 | aclk => aclk, 75 | s_axis_a_tvalid => s_axis_a_tvalid, 76 | s_axis_a_tdata => s_axis_a_tdata, 77 | s_axis_b_tvalid => s_axis_b_tvalid, 78 | s_axis_b_tdata => s_axis_b_tdata, 79 | m_axis_result_tvalid => m_axis_result_tvalid, 80 | m_axis_result_tdata => m_axis_result_tdata 81 | ); 82 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 83 | 84 | -- You must compile the wrapper file multip.vhd when simulating 85 | -- the core, multip. When compiling the wrapper file, be sure to 86 | -- reference the VHDL simulation library. 87 | 88 | -------------------------------------------------------------------------------- /sources_1/ip/multip/multip_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 100 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/multip/multip_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Fri Dec 09 16:04:53 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/multip/multip_stub.v 8 | // Design : multip 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "floating_point_v7_1_3,Vivado 2016.3" *) 17 | module multip(aclk, s_axis_a_tvalid, s_axis_a_tdata, 18 | s_axis_b_tvalid, s_axis_b_tdata, m_axis_result_tvalid, m_axis_result_tdata) 19 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]" */; 20 | input aclk; 21 | input s_axis_a_tvalid; 22 | input [31:0]s_axis_a_tdata; 23 | input s_axis_b_tvalid; 24 | input [31:0]s_axis_b_tdata; 25 | output m_axis_result_tvalid; 26 | output [31:0]m_axis_result_tdata; 27 | endmodule 28 | -------------------------------------------------------------------------------- /sources_1/ip/multip/multip_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Fri Dec 09 16:04:53 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- c:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/multip/multip_stub.vhdl 8 | -- Design : multip 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity multip is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_a_tvalid : in STD_LOGIC; 19 | s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 20 | s_axis_b_tvalid : in STD_LOGIC; 21 | s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 22 | m_axis_result_tvalid : out STD_LOGIC; 23 | m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) 24 | ); 25 | 26 | end multip; 27 | 28 | architecture stub of multip is 29 | attribute syn_black_box : boolean; 30 | attribute black_box_pad_pin : string; 31 | attribute syn_black_box of stub : architecture is true; 32 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]"; 33 | attribute x_core_info : string; 34 | attribute x_core_info of stub : architecture is "floating_point_v7_1_3,Vivado 2016.3"; 35 | begin 36 | end; 37 | -------------------------------------------------------------------------------- /sources_1/ip/multip/sim/multip.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY floating_point_v7_1_3; 57 | USE floating_point_v7_1_3.floating_point_v7_1_3; 58 | 59 | ENTITY multip IS 60 | PORT ( 61 | aclk : IN STD_LOGIC; 62 | s_axis_a_tvalid : IN STD_LOGIC; 63 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 64 | s_axis_b_tvalid : IN STD_LOGIC; 65 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 66 | m_axis_result_tvalid : OUT STD_LOGIC; 67 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 68 | ); 69 | END multip; 70 | 71 | ARCHITECTURE multip_arch OF multip IS 72 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 73 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF multip_arch: ARCHITECTURE IS "yes"; 74 | COMPONENT floating_point_v7_1_3 IS 75 | GENERIC ( 76 | C_XDEVICEFAMILY : STRING; 77 | C_HAS_ADD : INTEGER; 78 | C_HAS_SUBTRACT : INTEGER; 79 | C_HAS_MULTIPLY : INTEGER; 80 | C_HAS_DIVIDE : INTEGER; 81 | C_HAS_SQRT : INTEGER; 82 | C_HAS_COMPARE : INTEGER; 83 | C_HAS_FIX_TO_FLT : INTEGER; 84 | C_HAS_FLT_TO_FIX : INTEGER; 85 | C_HAS_FLT_TO_FLT : INTEGER; 86 | C_HAS_RECIP : INTEGER; 87 | C_HAS_RECIP_SQRT : INTEGER; 88 | C_HAS_ABSOLUTE : INTEGER; 89 | C_HAS_LOGARITHM : INTEGER; 90 | C_HAS_EXPONENTIAL : INTEGER; 91 | C_HAS_FMA : INTEGER; 92 | C_HAS_FMS : INTEGER; 93 | C_HAS_ACCUMULATOR_A : INTEGER; 94 | C_HAS_ACCUMULATOR_S : INTEGER; 95 | C_A_WIDTH : INTEGER; 96 | C_A_FRACTION_WIDTH : INTEGER; 97 | C_B_WIDTH : INTEGER; 98 | C_B_FRACTION_WIDTH : INTEGER; 99 | C_C_WIDTH : INTEGER; 100 | C_C_FRACTION_WIDTH : INTEGER; 101 | C_RESULT_WIDTH : INTEGER; 102 | C_RESULT_FRACTION_WIDTH : INTEGER; 103 | C_COMPARE_OPERATION : INTEGER; 104 | C_LATENCY : INTEGER; 105 | C_OPTIMIZATION : INTEGER; 106 | C_MULT_USAGE : INTEGER; 107 | C_BRAM_USAGE : INTEGER; 108 | C_RATE : INTEGER; 109 | C_ACCUM_INPUT_MSB : INTEGER; 110 | C_ACCUM_MSB : INTEGER; 111 | C_ACCUM_LSB : INTEGER; 112 | C_HAS_UNDERFLOW : INTEGER; 113 | C_HAS_OVERFLOW : INTEGER; 114 | C_HAS_INVALID_OP : INTEGER; 115 | C_HAS_DIVIDE_BY_ZERO : INTEGER; 116 | C_HAS_ACCUM_OVERFLOW : INTEGER; 117 | C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; 118 | C_HAS_ACLKEN : INTEGER; 119 | C_HAS_ARESETN : INTEGER; 120 | C_THROTTLE_SCHEME : INTEGER; 121 | C_HAS_A_TUSER : INTEGER; 122 | C_HAS_A_TLAST : INTEGER; 123 | C_HAS_B : INTEGER; 124 | C_HAS_B_TUSER : INTEGER; 125 | C_HAS_B_TLAST : INTEGER; 126 | C_HAS_C : INTEGER; 127 | C_HAS_C_TUSER : INTEGER; 128 | C_HAS_C_TLAST : INTEGER; 129 | C_HAS_OPERATION : INTEGER; 130 | C_HAS_OPERATION_TUSER : INTEGER; 131 | C_HAS_OPERATION_TLAST : INTEGER; 132 | C_HAS_RESULT_TUSER : INTEGER; 133 | C_HAS_RESULT_TLAST : INTEGER; 134 | C_TLAST_RESOLUTION : INTEGER; 135 | C_A_TDATA_WIDTH : INTEGER; 136 | C_A_TUSER_WIDTH : INTEGER; 137 | C_B_TDATA_WIDTH : INTEGER; 138 | C_B_TUSER_WIDTH : INTEGER; 139 | C_C_TDATA_WIDTH : INTEGER; 140 | C_C_TUSER_WIDTH : INTEGER; 141 | C_OPERATION_TDATA_WIDTH : INTEGER; 142 | C_OPERATION_TUSER_WIDTH : INTEGER; 143 | C_RESULT_TDATA_WIDTH : INTEGER; 144 | C_RESULT_TUSER_WIDTH : INTEGER; 145 | C_FIXED_DATA_UNSIGNED : INTEGER 146 | ); 147 | PORT ( 148 | aclk : IN STD_LOGIC; 149 | aclken : IN STD_LOGIC; 150 | aresetn : IN STD_LOGIC; 151 | s_axis_a_tvalid : IN STD_LOGIC; 152 | s_axis_a_tready : OUT STD_LOGIC; 153 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 154 | s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 155 | s_axis_a_tlast : IN STD_LOGIC; 156 | s_axis_b_tvalid : IN STD_LOGIC; 157 | s_axis_b_tready : OUT STD_LOGIC; 158 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 159 | s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 160 | s_axis_b_tlast : IN STD_LOGIC; 161 | s_axis_c_tvalid : IN STD_LOGIC; 162 | s_axis_c_tready : OUT STD_LOGIC; 163 | s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 164 | s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 165 | s_axis_c_tlast : IN STD_LOGIC; 166 | s_axis_operation_tvalid : IN STD_LOGIC; 167 | s_axis_operation_tready : OUT STD_LOGIC; 168 | s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 169 | s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 170 | s_axis_operation_tlast : IN STD_LOGIC; 171 | m_axis_result_tvalid : OUT STD_LOGIC; 172 | m_axis_result_tready : IN STD_LOGIC; 173 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); 174 | m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); 175 | m_axis_result_tlast : OUT STD_LOGIC 176 | ); 177 | END COMPONENT floating_point_v7_1_3; 178 | ATTRIBUTE X_INTERFACE_INFO : STRING; 179 | ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; 180 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; 181 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; 182 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; 183 | ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; 184 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; 185 | ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; 186 | BEGIN 187 | U0 : floating_point_v7_1_3 188 | GENERIC MAP ( 189 | C_XDEVICEFAMILY => "virtex7", 190 | C_HAS_ADD => 0, 191 | C_HAS_SUBTRACT => 0, 192 | C_HAS_MULTIPLY => 1, 193 | C_HAS_DIVIDE => 0, 194 | C_HAS_SQRT => 0, 195 | C_HAS_COMPARE => 0, 196 | C_HAS_FIX_TO_FLT => 0, 197 | C_HAS_FLT_TO_FIX => 0, 198 | C_HAS_FLT_TO_FLT => 0, 199 | C_HAS_RECIP => 0, 200 | C_HAS_RECIP_SQRT => 0, 201 | C_HAS_ABSOLUTE => 0, 202 | C_HAS_LOGARITHM => 0, 203 | C_HAS_EXPONENTIAL => 0, 204 | C_HAS_FMA => 0, 205 | C_HAS_FMS => 0, 206 | C_HAS_ACCUMULATOR_A => 0, 207 | C_HAS_ACCUMULATOR_S => 0, 208 | C_A_WIDTH => 32, 209 | C_A_FRACTION_WIDTH => 24, 210 | C_B_WIDTH => 32, 211 | C_B_FRACTION_WIDTH => 24, 212 | C_C_WIDTH => 32, 213 | C_C_FRACTION_WIDTH => 24, 214 | C_RESULT_WIDTH => 32, 215 | C_RESULT_FRACTION_WIDTH => 24, 216 | C_COMPARE_OPERATION => 8, 217 | C_LATENCY => 1, 218 | C_OPTIMIZATION => 1, 219 | C_MULT_USAGE => 2, 220 | C_BRAM_USAGE => 0, 221 | C_RATE => 1, 222 | C_ACCUM_INPUT_MSB => 32, 223 | C_ACCUM_MSB => 32, 224 | C_ACCUM_LSB => -31, 225 | C_HAS_UNDERFLOW => 0, 226 | C_HAS_OVERFLOW => 0, 227 | C_HAS_INVALID_OP => 0, 228 | C_HAS_DIVIDE_BY_ZERO => 0, 229 | C_HAS_ACCUM_OVERFLOW => 0, 230 | C_HAS_ACCUM_INPUT_OVERFLOW => 0, 231 | C_HAS_ACLKEN => 0, 232 | C_HAS_ARESETN => 0, 233 | C_THROTTLE_SCHEME => 3, 234 | C_HAS_A_TUSER => 0, 235 | C_HAS_A_TLAST => 0, 236 | C_HAS_B => 1, 237 | C_HAS_B_TUSER => 0, 238 | C_HAS_B_TLAST => 0, 239 | C_HAS_C => 0, 240 | C_HAS_C_TUSER => 0, 241 | C_HAS_C_TLAST => 0, 242 | C_HAS_OPERATION => 0, 243 | C_HAS_OPERATION_TUSER => 0, 244 | C_HAS_OPERATION_TLAST => 0, 245 | C_HAS_RESULT_TUSER => 0, 246 | C_HAS_RESULT_TLAST => 0, 247 | C_TLAST_RESOLUTION => 0, 248 | C_A_TDATA_WIDTH => 32, 249 | C_A_TUSER_WIDTH => 1, 250 | C_B_TDATA_WIDTH => 32, 251 | C_B_TUSER_WIDTH => 1, 252 | C_C_TDATA_WIDTH => 32, 253 | C_C_TUSER_WIDTH => 1, 254 | C_OPERATION_TDATA_WIDTH => 8, 255 | C_OPERATION_TUSER_WIDTH => 1, 256 | C_RESULT_TDATA_WIDTH => 32, 257 | C_RESULT_TUSER_WIDTH => 1, 258 | C_FIXED_DATA_UNSIGNED => 0 259 | ) 260 | PORT MAP ( 261 | aclk => aclk, 262 | aclken => '1', 263 | aresetn => '1', 264 | s_axis_a_tvalid => s_axis_a_tvalid, 265 | s_axis_a_tdata => s_axis_a_tdata, 266 | s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 267 | s_axis_a_tlast => '0', 268 | s_axis_b_tvalid => s_axis_b_tvalid, 269 | s_axis_b_tdata => s_axis_b_tdata, 270 | s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 271 | s_axis_b_tlast => '0', 272 | s_axis_c_tvalid => '0', 273 | s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), 274 | s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 275 | s_axis_c_tlast => '0', 276 | s_axis_operation_tvalid => '0', 277 | s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), 278 | s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), 279 | s_axis_operation_tlast => '0', 280 | m_axis_result_tvalid => m_axis_result_tvalid, 281 | m_axis_result_tready => '0', 282 | m_axis_result_tdata => m_axis_result_tdata 283 | ); 284 | END multip_arch; 285 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/subtractorip/cmodel/floating_point_v7_1_bitacc_cmodel_lin64.zip -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/subtractorip/cmodel/floating_point_v7_1_bitacc_cmodel_nt64.zip -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/doc/floating_point_v7_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2016.3: 2 | * Version 7.1 (Rev. 3) 3 | * General: Support for Spartan7 devices 4 | * Revision change in one or more subcores 5 | 6 | 2016.2: 7 | * Version 7.1 (Rev. 2) 8 | * No changes 9 | 10 | 2016.1: 11 | * Version 7.1 (Rev. 2) 12 | * Revision change in one or more subcores 13 | 14 | 2015.4.2: 15 | * Version 7.1 (Rev. 1) 16 | * No changes 17 | 18 | 2015.4.1: 19 | * Version 7.1 (Rev. 1) 20 | * No changes 21 | 22 | 2015.4: 23 | * Version 7.1 (Rev. 1) 24 | * Revision change in one or more subcores 25 | 26 | 2015.3: 27 | * Version 7.1 28 | * Added optimizations for half precision operators. 29 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 30 | * Removed IP GUI resource utilization graph tab now full performance and resource figures are available on xilinx.com. 31 | * Added support for fixed-to-float conversions from uint32, uint64 and int64 formats. 32 | * Added medium DSP48 usage option for single-precision Add/Subtract 33 | * Revision change in one or more subcores 34 | 35 | 2015.2.1: 36 | * Version 7.0 (Rev. 9) 37 | * No changes 38 | 39 | 2015.2: 40 | * Version 7.0 (Rev. 9) 41 | * Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles. 42 | * Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes. 43 | * Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes. 44 | 45 | 2015.1: 46 | * Version 7.0 (Rev. 8) 47 | * Addition of Beta support for 16nm devices 48 | * Supported devices and production status are now determined automatically, to simplify support for future devices 49 | * C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support 50 | * Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons 51 | 52 | 2014.4.1: 53 | * Version 7.0 (Rev. 7) 54 | * No changes 55 | 56 | 2014.4: 57 | * Version 7.0 (Rev. 7) 58 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 59 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 60 | 61 | 2014.3: 62 | * Version 7.0 (Rev. 6) 63 | * Added default values to signals in the Float-to-Fixed, Exponential and Natural Logarithm operators to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 64 | * Disabled debug assertions which were written to transcript during simulation, no functional changes. 65 | * Fixed C model to prevent crashes that could occur on 32-bit Windows platform. 66 | 67 | 2014.2: 68 | * Version 7.0 (Rev. 5) 69 | * Added default values to signals in the Exponential operator to avoid X's being output in behavioral simulation while the pipeline fills and M_AXIS_RESULT_TVALID is Low. Functionality is unchanged. 70 | * Removed component statement for DSP48E2, no functional changes 71 | * Internal change management process enhancements, no functional changes 72 | 73 | 2014.1: 74 | * Version 7.0 (Rev. 4) 75 | * GUI fix to disable internal debug messages from Accumulator 76 | * Core will now deliver an ooc_xdc file, without constraints, when latency is zero. 77 | * C models for Windows are compiled using Microsoft Visual Studio 2012 78 | * Rephased RTL in file flt_round_dsp_opt_full.vhd. Functionality is unaffected. 79 | * Internal device family name change, no functional changes 80 | * Corrected parameter order and comments for Accumulator operator in allfns.c 81 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 82 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 83 | * Support for Virtex Ultrascale devices at Pre-Production Status 84 | * Added attribute in flt_log_addsub_taylor_fabric.vhd to avoid packing error when logic replication occurs in synthesis. Functionality is unchanged. 85 | 86 | 2013.4: 87 | * Version 7.0 (Rev. 3) 88 | * Missing tooltips added to GUI 89 | * GUI fix for possible illegal Latency values 90 | * Support for Kintex Ultrascale devices at Pre-Production Status 91 | 92 | 2013.3: 93 | * Version 7.0 (Rev. 2) 94 | * Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. 95 | * Cosmetic GUI changes to table header row, no change in functionality 96 | * Added additional support for future devices 97 | * Behavioral VHDL model replaced by Encrypted RTL 98 | * Internal standardization in source file delivery, does not change behavior 99 | * Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defence Grade Zynq and Lower Power Artix7 devices at Production Status 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | * Added default constraints for out of context flow 102 | * Added support for IP Integrator 103 | * Optimized support for UltraScale devices 104 | * Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler 105 | * Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008 106 | * C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 107 | * C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll 108 | 109 | 2013.2: 110 | * Version 7.0 (Rev. 1) 111 | * Support for Series 7 devices at Production status 112 | * Added STL portability library to the C model zip files, to support the example code 113 | * Beta support for future devices 114 | * Removing support for Defense Grade Low Power Artix7 115 | 116 | 2013.1: 117 | * Version 7.0 118 | * Native Vivado Release 119 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 120 | 121 | (c) Copyright 2005 - 2016 Xilinx, Inc. All rights reserved. 122 | 123 | This file contains confidential and proprietary information 124 | of Xilinx, Inc. and is protected under U.S. and 125 | international copyright and other intellectual property 126 | laws. 127 | 128 | DISCLAIMER 129 | This disclaimer is not a license and does not grant any 130 | rights to the materials distributed herewith. Except as 131 | otherwise provided in a valid license issued to you by 132 | Xilinx, and to the maximum extent permitted by applicable 133 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 134 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 135 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 136 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 137 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 138 | (2) Xilinx shall not be liable (whether in contract or tort, 139 | including negligence, or under any other theory of 140 | liability) for any loss or damage of any kind or nature 141 | related to, arising under or in connection with these 142 | materials, including for any direct, or any indirect, 143 | special, incidental, or consequential loss or damage 144 | (including loss of data, profits, goodwill, or any type of 145 | loss or damage suffered as a result of any action brought 146 | by a third party) even if such damage or loss was 147 | reasonably foreseeable or Xilinx had been advised of the 148 | possibility of the same. 149 | 150 | CRITICAL APPLICATIONS 151 | Xilinx products are not designed or intended to be fail- 152 | safe, or for use in any application requiring fail-safe 153 | performance, such as life-support or safety devices or 154 | systems, Class III medical devices, nuclear facilities, 155 | applications related to the deployment of airbags, or any 156 | other applications that could lead to death, personal 157 | injury, or severe property or environmental damage 158 | (individually and collectively, "Critical 159 | Applications"). Customer assumes the sole risk and 160 | liability of any use of Xilinx products in Critical 161 | Applications, subject only to applicable laws and 162 | regulations governing limitations on product liability. 163 | 164 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 165 | PART OF THIS FILE AT ALL TIMES. 166 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/abhishekgb/Kalman-Filter-verilog/6c612d3b06fce5ecb3f88d47a5acd1a1d3858858/sources_1/ip/subtractorip/subtractorip.dcp -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:floating_point:7.1 50 | // IP Revision: 3 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | subtractorip your_instance_name ( 58 | .aclk(aclk), // input wire aclk 59 | .s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid 60 | .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata 61 | .s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid 62 | .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata 63 | .m_axis_result_tvalid(m_axis_result_tvalid), // output wire m_axis_result_tvalid 64 | .m_axis_result_tdata(m_axis_result_tdata) // output wire [31 : 0] m_axis_result_tdata 65 | ); 66 | // INST_TAG_END ------ End INSTANTIATION Template --------- 67 | 68 | // You must compile the wrapper file subtractorip.v when simulating 69 | // the core, subtractorip. When compiling the wrapper file, be sure to 70 | // reference the Verilog simulation library. 71 | 72 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:floating_point:7.1 50 | -- IP Revision: 3 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT subtractorip 56 | PORT ( 57 | aclk : IN STD_LOGIC; 58 | s_axis_a_tvalid : IN STD_LOGIC; 59 | s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 60 | s_axis_b_tvalid : IN STD_LOGIC; 61 | s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | m_axis_result_tvalid : OUT STD_LOGIC; 63 | m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END COMPONENT; 66 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 67 | 68 | -- The following code must appear in the VHDL architecture 69 | -- body. Substitute your own instance name and net names. 70 | 71 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 72 | your_instance_name : subtractorip 73 | PORT MAP ( 74 | aclk => aclk, 75 | s_axis_a_tvalid => s_axis_a_tvalid, 76 | s_axis_a_tdata => s_axis_a_tdata, 77 | s_axis_b_tvalid => s_axis_b_tvalid, 78 | s_axis_b_tdata => s_axis_b_tdata, 79 | m_axis_result_tvalid => m_axis_result_tvalid, 80 | m_axis_result_tdata => m_axis_result_tdata 81 | ); 82 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 83 | 84 | -- You must compile the wrapper file subtractorip.vhd when simulating 85 | -- the core, subtractorip. When compiling the wrapper file, be sure to 86 | -- reference the VHDL simulation library. 87 | 88 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip_ooc.xdc: -------------------------------------------------------------------------------- 1 | # (c) Copyright 2012-2016 Xilinx, Inc. All rights reserved. 2 | # 3 | # This file contains confidential and proprietary information 4 | # of Xilinx, Inc. and is protected under U.S. and 5 | # international copyright and other intellectual property 6 | # laws. 7 | # 8 | # DISCLAIMER 9 | # This disclaimer is not a license and does not grant any 10 | # rights to the materials distributed herewith. Except as 11 | # otherwise provided in a valid license issued to you by 12 | # Xilinx, and to the maximum extent permitted by applicable 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | # (2) Xilinx shall not be liable (whether in contract or tort, 19 | # including negligence, or under any other theory of 20 | # liability) for any loss or damage of any kind or nature 21 | # related to, arising under or in connection with these 22 | # materials, including for any direct, or any indirect, 23 | # special, incidental, or consequential loss or damage 24 | # (including loss of data, profits, goodwill, or any type of 25 | # loss or damage suffered as a result of any action brought 26 | # by a third party) even if such damage or loss was 27 | # reasonably foreseeable or Xilinx had been advised of the 28 | # possibility of the same. 29 | # 30 | # CRITICAL APPLICATIONS 31 | # Xilinx products are not designed or intended to be fail- 32 | # safe, or for use in any application requiring fail-safe 33 | # performance, such as life-support or safety devices or 34 | # systems, Class III medical devices, nuclear facilities, 35 | # applications related to the deployment of airbags, or any 36 | # other applications that could lead to death, personal 37 | # injury, or severe property or environmental damage 38 | # (individually and collectively, "Critical 39 | # Applications"). Customer assumes the sole risk and 40 | # liability of any use of Xilinx products in Critical 41 | # Applications, subject only to applicable laws and 42 | # regulations governing limitations on product liability. 43 | # 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | # PART OF THIS FILE AT ALL TIMES. 46 | # 47 | # DO NOT MODIFY THIS FILE. 48 | # ######################################################### 49 | # 50 | # This XDC is used only in OOC mode for synthesis, implementation 51 | # 52 | # ######################################################### 53 | 54 | 55 | create_clock -period 100 -name aclk [get_ports aclk] 56 | 57 | 58 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | // Date : Sun Dec 11 18:14:31 2016 5 | // Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // C:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/subtractorip/subtractorip_stub.v 8 | // Design : subtractorip 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7vx485tffg1157-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "floating_point_v7_1_3,Vivado 2016.3" *) 17 | module subtractorip(aclk, s_axis_a_tvalid, s_axis_a_tdata, 18 | s_axis_b_tvalid, s_axis_b_tdata, m_axis_result_tvalid, m_axis_result_tdata) 19 | /* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]" */; 20 | input aclk; 21 | input s_axis_a_tvalid; 22 | input [31:0]s_axis_a_tdata; 23 | input s_axis_b_tvalid; 24 | input [31:0]s_axis_b_tdata; 25 | output m_axis_result_tvalid; 26 | output [31:0]m_axis_result_tdata; 27 | endmodule 28 | -------------------------------------------------------------------------------- /sources_1/ip/subtractorip/subtractorip_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016 4 | -- Date : Sun Dec 11 18:14:31 2016 5 | -- Host : DESKTOP-3GRRS52 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- C:/Users/abhis/Desktop/abhi_mppt/project_6/project_6.srcs/sources_1/ip/subtractorip/subtractorip_stub.vhdl 8 | -- Design : subtractorip 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7vx485tffg1157-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity subtractorip is 16 | Port ( 17 | aclk : in STD_LOGIC; 18 | s_axis_a_tvalid : in STD_LOGIC; 19 | s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 20 | s_axis_b_tvalid : in STD_LOGIC; 21 | s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); 22 | m_axis_result_tvalid : out STD_LOGIC; 23 | m_axis_result_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) 24 | ); 25 | 26 | end subtractorip; 27 | 28 | architecture stub of subtractorip is 29 | attribute syn_black_box : boolean; 30 | attribute black_box_pad_pin : string; 31 | attribute syn_black_box of stub : architecture is true; 32 | attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_result_tvalid,m_axis_result_tdata[31:0]"; 33 | attribute x_core_info : string; 34 | attribute x_core_info of stub : architecture is "floating_point_v7_1_3,Vivado 2016.3"; 35 | begin 36 | end; 37 | -------------------------------------------------------------------------------- /sources_1/new/Hwrappercode.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/10/2016 12:06:09 AM 7 | // Design Name: 8 | // Module Name: Hwrappercode 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Hwrappercode( 24 | output reg [31:0] Hin, 25 | //input [31:0] k, 26 | input clock, 27 | input reset 28 | ); 29 | 30 | //h = (1-k)*h 31 | wire [31:0] h1wire ,subout,multout; 32 | reg [31:0] k; 33 | wire r1,rf; 34 | 35 | subtractorip dutsub ( 36 | .aclk(clock), // input wire aclk 37 | .s_axis_a_tvalid(1'b1), // input wire s_axis_a_tvalid 38 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 39 | .s_axis_a_tdata(32'h0x3f800000), // input wire [31 : 0] s_axis_a_tdata 40 | .s_axis_b_tvalid(1'b1), // input wire s_axis_b_tvalid 41 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 42 | .s_axis_b_tdata(k), // input wire [31 : 0] s_axis_b_tdata 43 | .m_axis_result_tvalid(rf), // output wire m_axis_result_tvalid 44 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 45 | .m_axis_result_tdata(subout) // output wire [31 : 0] m_axis_result_tdata 46 | ); 47 | 48 | multip dutmut ( 49 | .aclk(clock), // input wire aclk 50 | .s_axis_a_tvalid(rf), // input wire s_axis_a_tvalid 51 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 52 | .s_axis_a_tdata(subout), // input wire [31 : 0] s_axis_a_tdata 53 | .s_axis_b_tvalid(1'b1), // input wire s_axis_b_tvalid 54 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 55 | .s_axis_b_tdata(Hin), // input wire [31 : 0] s_axis_b_tdata 56 | .m_axis_result_tvalid(r1), // output wire m_axis_result_tvalid 57 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 58 | .m_axis_result_tdata(multout) // output wire [31 : 0] m_axis_result_tdata 59 | ); 60 | 61 | always@(posedge clock or reset) 62 | begin 63 | 64 | 65 | if (reset) 66 | begin 67 | Hin <= 32'h0x3e99999a; 68 | k <= 32'h0x3f000000; 69 | end 70 | // If not resetting, update the register output on the busy's falling edge 71 | else 72 | begin 73 | Hin <=multout; 74 | end 75 | end // rg <= r; 76 | 77 | 78 | 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /sources_1/new/adderwrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/09/2016 03:44:33 PM 7 | // Design Name: 8 | // Module Name: adderwrapper 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module adderwrapper( 24 | input [31:0] dataa, 25 | input [31:0] datab, 26 | input validdataa,validdatab,//,readyo , 27 | output reg [31:0] result, 28 | input clock 29 | ); 30 | wire r;//,readyo; 31 | wire [31:0] resultw; 32 | 33 | always@(posedge clock) begin 34 | result <= resultw; 35 | 36 | end 37 | floating_point_1 dutadd ( 38 | .aclk(clock), // input wire aclk 39 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 40 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 41 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 42 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 43 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 44 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 45 | .m_axis_result_tvalid(r), // output wire m_axis_result_tvalid 46 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 47 | .m_axis_result_tdata(resultw) // output wire [31 : 0] m_axis_result_tdata 48 | ); 49 | 50 | endmodule 51 | 52 | 53 | -------------------------------------------------------------------------------- /sources_1/new/dividertb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ps 3 | module kalmantb1(); 4 | 5 | wire signed [31:0] Hin,resultd,resulta,resultm,results,resultf,uofk,vrefofk; 6 | reg signed [31:0] dataa,datab,datac; 7 | reg clock,reset,validdataa,validdatab,validdatac,readyo,readyb; 8 | reg uvalid,Vrefofkvalid; 9 | 10 | 11 | 12 | /* equationfile tbf( 13 | .clock(clock), 14 | .dataa(dataa), 15 | .validdataa(validdataa), 16 | .validdatab(validdatab), 17 | .validdatac(validdatac), 18 | // .readyo(readyo), 19 | //.readyb(readyb), 20 | .datab(datab), 21 | .datac(datac), 22 | .result(resultf)); 23 | /*dividerwrapper tb2( 24 | .clock(clock), 25 | .dataa(dataa), 26 | .validdataa(validdataa), 27 | .validdatab(validdatab), 28 | // .readyo(readyo), 29 | //.readyb(readyb), 30 | .datab(datab), 31 | .result(resultd)); 32 | 33 | adderwrapper tb212( 34 | .clock(clock), 35 | .dataa(dataa), 36 | .validdataa(validdataa), 37 | .validdatab(validdatab), 38 | // .readyo(readyo), 39 | //.readyb(readyb), 40 | .datab(datab), 41 | .result(resulta)); 42 | 43 | multwrapper tb3( 44 | .clock(clock), 45 | .dataa(dataa), 46 | .validdataa(validdataa), 47 | .validdatab(validdatab), 48 | // .readyo(readyo), 49 | //.readyb(readyb), 50 | .datab(datab), 51 | .result(resultm)); 52 | 53 | subtractorwrapper tb4( 54 | .clock(clock), 55 | .dataa(dataa), 56 | .validdataa(validdataa), 57 | .validdatab(validdatab), 58 | // .readyo(readyo), 59 | //.readyb(readyb), 60 | .datab(datab), 61 | .result(results)); 62 | */ 63 | 64 | /*Hwrappercode dut11 65 | ( 66 | .Hin(Hin), 67 | .clock(clock), 68 | .reset(reset) 69 | ); 70 | */ 71 | kalmanalu testunit1( 72 | .Yout(Yout), 73 | //input [31:0] k, 74 | .clock(clock), 75 | .uofk(uofk), 76 | .vrefofk(vrefofk), 77 | .uvalid(uvalid), 78 | .Vrefofkvalid(Vrefofkvalid), 79 | .reset(reset) 80 | ); 81 | 82 | 83 | 84 | 85 | 86 | 87 | initial 88 | begin 89 | clock = 1'b0; 90 | /*datab = 32'd0; 91 | dataa = 32'd0; 92 | datac = 32'd0; 93 | //readyo= 1'b0; 94 | validdataa = 1'b0; 95 | validdatab = 1'b0; 96 | validdatac = 1'b0; 97 | //readya = 1'b0; 98 | //readyb = 1'b0;*/ 99 | 100 | /* 101 | dataa = 32'h0x40066666;//2.1 102 | datab = 32'h0x4059999a;//3.4 103 | datac = 32'h0x3dcccccd;//0.1 104 | validdataa = 1'b1; 105 | validdatab = 1'b1; 106 | validdatac = 1'b1; 107 | //readyo = 1'b0; 108 | //readya = 1'b1; 109 | //readyb = 1'b1; 110 | 111 | 112 | #50 113 | dataa = 32'h0x3e4ccccd;//0.2 114 | datab = 32'h0x3e99999a;//0.3 115 | datac = 32'h0x3f000000;//0.5 116 | validdataa = 1'b1; 117 | validdatab = 1'b1; 118 | validdatac = 1'b1; 119 | #50 120 | dataa = 32'h0x40066666;//2.1 121 | datab = 32'h0x4059999a;//3.4 122 | datac = 32'h0x3dcccccd;//0.1 123 | validdataa = 1'b1; 124 | validdatab = 1'b1; 125 | validdatac = 1'b1; 126 | #50 127 | dataa = 32'h0x3e4ccccd;//0.2 128 | datab = 32'h0x3e99999a;//0.3 129 | datac = 32'h0x3f000000;//0.5 130 | validdataa = 1'b1; 131 | validdatab = 1'b1; 132 | validdatac = 1'b1; 133 | #50 134 | dataa = 32'h0x40066666;//2.1 135 | datab = 32'h0x4059999a;//3.4 136 | datac = 32'h0x3dcccccd;//0.1 137 | validdataa = 1'b1; 138 | validdatab = 1'b1; 139 | validdatac = 1'b1; 140 | #50 141 | dataa = 32'h0x3e4ccccd;//0.2 142 | datab = 32'h0x3e99999a;//0.3 143 | datac = 32'h0x3f000000;//0.5 144 | validdataa = 1'b1; 145 | validdatab = 1'b1; 146 | validdatac = 1'b1; 147 | #50 148 | dataa = 32'h0x40066666;//2.1 149 | datab = 32'h0x4059999a;//3.4 150 | datac = 32'h0x3dcccccd;//0.1 151 | validdataa = 1'b1; 152 | validdatab = 1'b1; 153 | validdatac = 1'b1; 154 | #50 155 | dataa = 32'h0x3e4ccccd;//0.2 156 | datab = 32'h0x3e99999a;//0.3 157 | datac = 32'h0x3f000000;//0.5 158 | validdataa = 1'b1; 159 | validdatab = 1'b1; 160 | validdatac = 1'b1; 161 | #50 162 | dataa = 32'h0x40066666;//2.1 163 | datab = 32'h0x4059999a;//3.4 164 | datac = 32'h0x3dcccccd;//0.1 165 | validdataa = 1'b1; 166 | validdatab = 1'b1; 167 | validdatac = 1'b1; 168 | #50 169 | dataa = 32'h0x3e4ccccd;//0.2 170 | datab = 32'h0x3e99999a;//0.3 171 | datac = 32'h0x3f000000;//0.5 172 | validdataa = 1'b1; 173 | validdatab = 1'b1; 174 | validdatac = 1'b1; 175 | /*dataa = 32'b01000000100001100110011001100110; 176 | datab = 32'b01000000000001100110011001100110; 177 | validdataa = 1'b1; 178 | validdatab = 1'b1; 179 | //readya = 1'b0; 180 | //readyb = 1'b0;*/ 181 | reset = 1'b1; 182 | #1000 183 | reset = 1'b0; 184 | 185 | //interation one 186 | #20 187 | uvalid <= 1'b1; 188 | Vrefofkvalid <= 1'b1; 189 | vrefofk <= 32'h3f0a3d71; //0.54 190 | 191 | uofk <=32'd0;//0 192 | 193 | #20 194 | uvalid <= 1'b1; 195 | Vrefofkvalid <= 1'b1; 196 | vrefofk <= 32'h3f0a3d71; //0.54 197 | 198 | uofk <=32'd0;//0 199 | 200 | #20 201 | uvalid <= 1'b1; 202 | Vrefofkvalid <= 1'b1; 203 | vrefofk <= 32'h3f0a3d71; //0.54 204 | 205 | uofk <=32'h40751d15;//3.83 206 | #20 207 | uvalid <= 1'b1; 208 | Vrefofkvalid <= 1'b1; 209 | vrefofk <= 32'h3f4aacda; //0.79 210 | 211 | uofk <=32'h40751d15;//3.83 212 | 213 | #20 214 | uvalid <= 1'b1; 215 | Vrefofkvalid <= 1'b1; 216 | vrefofk <= 32'h3f8ccccd; //1.1 217 | 218 | uofk <=32'h40751d15;//3.83 219 | //readya = 1'b0; 220 | //readyb = 1'b0; 221 | $finish; 222 | 223 | 224 | 225 | end 226 | always 227 | begin 228 | #10 clock = ~clock; 229 | end 230 | endmodule 231 | -------------------------------------------------------------------------------- /sources_1/new/dividerwrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/07/2016 10:30:33 PM 7 | // Design Name: 8 | // Module Name: dividerwrapper 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module dividerwrapper( 24 | input clock, 25 | input [31:0] dataa, 26 | input [31:0] datab, 27 | input validdataa,validdatab,//,readyo , 28 | output reg [31:0] result 29 | ); 30 | wire r;//,readyo; 31 | wire [31:0] resultw; 32 | 33 | always@(posedge clock) begin 34 | result <= resultw; 35 | 36 | end 37 | floating_point_0 dut123 ( 38 | .aclk(clock), // input wire aclk 39 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 40 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 41 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 42 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 43 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 44 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 45 | .m_axis_result_tvalid(r), // output wire m_axis_result_tvalid 46 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 47 | .m_axis_result_tdata(resultw) // output wire [31 : 0] m_axis_result_tdata 48 | ); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /sources_1/new/equationfile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/09/2016 06:00:16 PM 7 | // Design Name: 8 | // Module Name: equationfile 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module equationfile( 24 | input clock, 25 | input [31:0] dataa, 26 | input [31:0] datab, 27 | input [31:0] datac, 28 | input validdataa,validdatab,validdatac, 29 | output reg [31:0] result 30 | ); 31 | 32 | wire [31:0] result1,result2,result3,resultf; 33 | wire r,r1,r2,r3,rf;//,rg; 34 | reg rg; 35 | 36 | 37 | /// (a+b)-((a/b)*c) 38 | subtractorip dutsub ( 39 | .aclk(clock), // input wire aclk 40 | .s_axis_a_tvalid(r3), // input wire s_axis_a_tvalid 41 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 42 | .s_axis_a_tdata(result3), // input wire [31 : 0] s_axis_a_tdata 43 | .s_axis_b_tvalid(r1), // input wire s_axis_b_tvalid 44 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 45 | .s_axis_b_tdata(result2), // input wire [31 : 0] s_axis_b_tdata 46 | .m_axis_result_tvalid(rf), // output wire m_axis_result_tvalid 47 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 48 | .m_axis_result_tdata(resultf) // output wire [31 : 0] m_axis_result_tdata 49 | ); 50 | 51 | //adder a+b 52 | floating_point_1 dutadd ( 53 | .aclk(clock), // input wire aclk 54 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 55 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 56 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 57 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 58 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 59 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 60 | .m_axis_result_tvalid(r3), // output wire m_axis_result_tvalid 61 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 62 | .m_axis_result_tdata(result3) // output wire [31 : 0] m_axis_result_tdata 63 | ); 64 | 65 | //multiplication---(a/b)*c 66 | multip dutmut ( 67 | .aclk(clock), // input wire aclk 68 | .s_axis_a_tvalid(rg), // input wire s_axis_a_tvalid 69 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 70 | .s_axis_a_tdata(result1), // input wire [31 : 0] s_axis_a_tdata 71 | .s_axis_b_tvalid(validdatac), // input wire s_axis_b_tvalid 72 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 73 | .s_axis_b_tdata(datac), // input wire [31 : 0] s_axis_b_tdata 74 | .m_axis_result_tvalid(r1), // output wire m_axis_result_tvalid 75 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 76 | .m_axis_result_tdata(result2) // output wire [31 : 0] m_axis_result_tdata 77 | ); 78 | //division a/b 79 | floating_point_0 dut123 ( 80 | .aclk(clock), // input wire aclk 81 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 82 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 83 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 84 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 85 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 86 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 87 | .m_axis_result_tvalid(r), // output wire m_axis_result_tvalid 88 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 89 | .m_axis_result_tdata(result1) // output wire [31 : 0] m_axis_result_tdata 90 | ); 91 | 92 | always@(posedge clock) begin 93 | result <= resultf; 94 | rg <= r; 95 | 96 | end 97 | 98 | 99 | 100 | 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /sources_1/new/multwrapper.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 12/09/2016 04:42:42 PM 7 | // Design Name: 8 | // Module Name: multwrapper 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module multwrapper 24 | ( 25 | input clock, 26 | input [31:0] dataa, 27 | input [31:0] datab, 28 | input validdataa,validdatab,//,readyo , 29 | output reg [31:0] result 30 | ); 31 | wire r;//,readyo; 32 | wire [31:0] resultw; 33 | 34 | always@(posedge clock) begin 35 | result <= resultw; 36 | 37 | end 38 | multip dutmut ( 39 | .aclk(clock), // input wire aclk 40 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 41 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 42 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 43 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 44 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 45 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 46 | .m_axis_result_tvalid(r), // output wire m_axis_result_tvalid 47 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 48 | .m_axis_result_tdata(resultw) // output wire [31 : 0] m_axis_result_tdata 49 | ); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /sources_1/new/subtractorwrapper.v: -------------------------------------------------------------------------------- 1 | module subtractorwrapper( 2 | input clock, 3 | input [31:0] dataa, 4 | input [31:0] datab, 5 | input validdataa,validdatab,//,readyo , 6 | output reg [31:0] result 7 | ); 8 | wire r;//,readyo; 9 | wire [31:0] resultw; 10 | 11 | always@(posedge clock) begin 12 | result <= resultw; 13 | 14 | end 15 | subtractorip dutsub ( 16 | .aclk(clock), // input wire aclk 17 | .s_axis_a_tvalid(validdataa), // input wire s_axis_a_tvalid 18 | // .s_axis_a_tready(readya), // output wire s_axis_a_tready 19 | .s_axis_a_tdata(dataa), // input wire [31 : 0] s_axis_a_tdata 20 | .s_axis_b_tvalid(validdatab), // input wire s_axis_b_tvalid 21 | //.s_axis_b_tready(readyb), // output wire s_axis_b_tready 22 | .s_axis_b_tdata(datab), // input wire [31 : 0] s_axis_b_tdata 23 | .m_axis_result_tvalid(r), // output wire m_axis_result_tvalid 24 | // .m_axis_result_tready(readyo), // input wire m_axis_result_tready 25 | .m_axis_result_tdata(resultw) // output wire [31 : 0] m_axis_result_tdata 26 | ); 27 | 28 | endmodule --------------------------------------------------------------------------------