├── .github ├── ISSUE_TEMPLATE.md ├── PULL_REQUEST_TEMPLATE.md └── workflows │ └── githubci.yml ├── API.md ├── LICENSE ├── README.md ├── examples ├── CANReceiver │ └── CANReceiver.ino ├── CANReceiverCallback │ └── CANReceiverCallback.ino └── CANSender │ └── CANSender.ino ├── keywords.txt ├── library.properties ├── mkcandata.py └── src ├── CAN.h ├── CANController.cpp ├── CANController.h ├── CANSAME5x.cpp ├── CANSAME5x.h ├── CANSAME5x_port.h ├── ESP32SJA1000.cpp ├── ESP32SJA1000.h ├── MCP2515.cpp └── MCP2515.h /.github/ISSUE_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | Thank you for opening an issue on an Adafruit Arduino library repository. To 2 | improve the speed of resolution please review the following guidelines and 3 | common troubleshooting steps below before creating the issue: 4 | 5 | - **Do not use GitHub issues for troubleshooting projects and issues.** Instead use 6 | the forums at http://forums.adafruit.com to ask questions and troubleshoot why 7 | something isn't working as expected. In many cases the problem is a common issue 8 | that you will more quickly receive help from the forum community. GitHub issues 9 | are meant for known defects in the code. If you don't know if there is a defect 10 | in the code then start with troubleshooting on the forum first. 11 | 12 | - **If following a tutorial or guide be sure you didn't miss a step.** Carefully 13 | check all of the steps and commands to run have been followed. Consult the 14 | forum if you're unsure or have questions about steps in a guide/tutorial. 15 | 16 | - **For Arduino projects check these very common issues to ensure they don't apply**: 17 | 18 | - For uploading sketches or communicating with the board make sure you're using 19 | a **USB data cable** and **not** a **USB charge-only cable**. It is sometimes 20 | very hard to tell the difference between a data and charge cable! Try using the 21 | cable with other devices or swapping to another cable to confirm it is not 22 | the problem. 23 | 24 | - **Be sure you are supplying adequate power to the board.** Check the specs of 25 | your board and plug in an external power supply. In many cases just 26 | plugging a board into your computer is not enough to power it and other 27 | peripherals. 28 | 29 | - **Double check all soldering joints and connections.** Flakey connections 30 | cause many mysterious problems. See the [guide to excellent soldering](https://learn.adafruit.com/adafruit-guide-excellent-soldering/tools) for examples of good solder joints. 31 | 32 | - **Ensure you are using an official Arduino or Adafruit board.** We can't 33 | guarantee a clone board will have the same functionality and work as expected 34 | with this code and don't support them. 35 | 36 | If you're sure this issue is a defect in the code and checked the steps above 37 | please fill in the following fields to provide enough troubleshooting information. 38 | You may delete the guideline and text above to just leave the following details: 39 | 40 | - Arduino board: **INSERT ARDUINO BOARD NAME/TYPE HERE** 41 | 42 | - Arduino IDE version (found in Arduino -> About Arduino menu): **INSERT ARDUINO 43 | VERSION HERE** 44 | 45 | - List the steps to reproduce the problem below (if possible attach a sketch or 46 | copy the sketch code in too): **LIST REPRO STEPS BELOW** 47 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | Thank you for creating a pull request to contribute to Adafruit's GitHub code! 2 | Before you open the request please review the following guidelines and tips to 3 | help it be more easily integrated: 4 | 5 | - **Describe the scope of your change--i.e. what the change does and what parts 6 | of the code were modified.** This will help us understand any risks of integrating 7 | the code. 8 | 9 | - **Describe any known limitations with your change.** For example if the change 10 | doesn't apply to a supported platform of the library please mention it. 11 | 12 | - **Please run any tests or examples that can exercise your modified code.** We 13 | strive to not break users of the code and running tests/examples helps with this 14 | process. 15 | 16 | Thank you again for contributing! We will try to test and integrate the change 17 | as soon as we can, but be aware we have many GitHub repositories to manage and 18 | can't immediately respond to every request. There is no need to bump or check in 19 | on a pull request (it will clutter the discussion of the request). 20 | 21 | Also don't be worried if the request is closed or not integrated--sometimes the 22 | priorities of Adafruit's GitHub code (education, ease of use) might not match the 23 | priorities of the pull request. Don't fret, the open source community thrives on 24 | forks and GitHub makes it easy to keep your changes in a forked repo. 25 | 26 | After reviewing the guidelines above you can delete this text from the pull request. 27 | -------------------------------------------------------------------------------- /.github/workflows/githubci.yml: -------------------------------------------------------------------------------- 1 | name: Arduino Library CI 2 | 3 | on: [pull_request, push, repository_dispatch] 4 | 5 | jobs: 6 | build: 7 | runs-on: ubuntu-latest 8 | 9 | steps: 10 | - uses: actions/setup-python@v4 11 | with: 12 | python-version: '3.x' 13 | - uses: actions/checkout@v3 14 | - uses: actions/checkout@v3 15 | with: 16 | repository: adafruit/ci-arduino 17 | path: ci 18 | 19 | - name: pre-install 20 | run: bash ci/actions_install.sh 21 | 22 | - name: test platforms 23 | run: python3 ci/build_platform.py main_platforms 24 | -------------------------------------------------------------------------------- /API.md: -------------------------------------------------------------------------------- 1 | # CAN API 2 | 3 | ## Include Library 4 | 5 | ```arduino 6 | #include 7 | ``` 8 | 9 | ## Setup 10 | 11 | ### Begin 12 | 13 | Initialize the library with the specified bit rate. 14 | 15 | ```arduino 16 | CAN.begin(bitrate); 17 | ``` 18 | * `bitrate` - bit rate in bits per seconds (bps) (`1000E3`, `500E3`, `250E3`, `200E3`, `125E3`, `100E3`, `80E3`, `50E3`, `40E3`, `20E3`, `10E3`, `5E3`) 19 | 20 | Returns `1` on success, `0` on failure. 21 | 22 | ### Set pins 23 | 24 | #### MCP2515 25 | 26 | Override the default `CS` and `INT` pins used by the library. **Must** be called before `CAN.begin(...)`. 27 | 28 | ```arduino 29 | CAN.setPins(cs, irq); 30 | ``` 31 | * `cs` - new chip select pin to use, defaults to `10` 32 | * `irq` - new INT pin to use, defaults to `2`. **Must** be interrupt capable via [attachInterrupt(...)](https://www.arduino.cc/en/Reference/AttachInterrupt). 33 | 34 | This call is optional and only needs to be used if you need to change the default pins used. 35 | 36 | #### ESP32 37 | 38 | Override the default `CTX` and `CRX` pins used by the library. **Must** be called before `CAN.begin(...)`. 39 | 40 | ```arduino 41 | CAN.setPins(rx, tx); 42 | ``` 43 | * `rx` - new CRX pin to use, defaults to `4` 44 | * `tx` - new CTX pin to use, defaults to `5`. 45 | 46 | This call is optional and only needs to be used if you need to change the default pins used. 47 | 48 | ### Set SPI Frequency 49 | 50 | **MCP2515 only** 51 | 52 | Override the default SPI frequency of 10 MHz used by the library. **Must** be called before `CAN.begin(...)`. 53 | 54 | ```arduino 55 | CAN.setSPIFrequency(frequency); 56 | ``` 57 | * `frequency` - new SPI frequency to use, defaults to `10E6` 58 | 59 | This call is optional and only needs to be used if you need to change the default SPI frequency used. Some logic level converters cannot support high speeds such as 10 MHz, so a lower SPI frequency can be selected with `CAN.setSPIFrequency(frequency)`. 60 | 61 | ### Set Clock Frequency 62 | 63 | **MCP2515 only** 64 | 65 | Override the default clock source frequency that is connected to the MCP2515. **Must** be called before `CAN.begin(...)`. 66 | 67 | ```arduino 68 | CAN.setClockFrequency(clockFrequency); 69 | ``` 70 | * `clockFrequency` - new clock frequency to use (`8E6`, `16E6`) connected to MCP2515, defaults to `16 Mhz` 71 | 72 | This call is optional and only needs to be used if you need to change the clock source frequency connected to the MCP2515. Most shields have a 16 MHz clock source on board, some breakout boards have a 8 MHz source. 73 | 74 | ### End 75 | 76 | Stop the library 77 | 78 | ```arduino 79 | CAN.end() 80 | ``` 81 | 82 | ## Sending data 83 | 84 | ### Begin packet 85 | 86 | Start the sequence of sending a packet. 87 | 88 | ```arduino 89 | CAN.beginPacket(id); 90 | CAN.beginPacket(id, dlc); 91 | CAN.beginPacket(id, dlc, rtr); 92 | 93 | CAN.beginExtendedPacket(id); 94 | CAN.beginExtendedPacket(id, dlc); 95 | CAN.beginExtendedPacket(id, dlc, rtr); 96 | ``` 97 | 98 | * `id` - 11-bit id (standard packet) or 29-bit packet id (extended packet) 99 | * `dlc` - (optional) value of Data Length Code (DLC) field of packet, default is size of data written in packet 100 | * `rtr` - (optional) value of Remote Transmission Request (RTR) field of packet (`false` or `true`), defaults to `false`. RTR packets contain no data, the DLC field of the packet represents the requested length. 101 | 102 | Returns `1` on success, `0` on failure. 103 | 104 | ### Writing 105 | 106 | Write data to the packet. Each packet can contain up to 8 bytes. 107 | 108 | ```arduino 109 | CAN.write(byte); 110 | 111 | CAN.write(buffer, length); 112 | ``` 113 | * `byte` - single byte to write to packet 114 | 115 | or 116 | 117 | * `buffer` - data to write to packet 118 | * `length` - size of data to write 119 | 120 | Returns the number of bytes written. 121 | 122 | **Note:** Other Arduino `Print` API's can also be used to write data into the packet 123 | 124 | ### End packet 125 | 126 | End the sequence of sending a packet. 127 | 128 | ```arduino 129 | CAN.endPacket() 130 | ``` 131 | 132 | Returns `1` on success, `0` on failure. 133 | 134 | ## Receiving data 135 | 136 | ### Parsing packet 137 | 138 | Check if a packet has been received. 139 | 140 | ```arduino 141 | int packetSize = CAN.parsePacket(); 142 | ``` 143 | 144 | Returns the packet size in bytes or `0` if no packet was received. For RTR packets the size reflects the DLC field of the packet. 145 | 146 | ### Register callback 147 | 148 | Register a callback function for when a packet is received. 149 | 150 | ```arduino 151 | CAN.onReceive(onReceive); 152 | 153 | void onReceive(int packetSize) { 154 | // ... 155 | } 156 | ``` 157 | 158 | * `onReceive` - function to call when a packet is received. 159 | 160 | ### Packet ID 161 | 162 | ```arduino 163 | long id = CAN.packetId(); 164 | ``` 165 | 166 | Returns the id (11-bit or 29 bit) of the received packet. Standard packets have an 11-bit id, extended packets have an 29-bit id. 167 | 168 | ### Packet Extended 169 | 170 | ```arduino 171 | bool extended = CAN.packetExtended(); 172 | ``` 173 | 174 | Returns `true` if the received packet is extended, `false` otherwise. 175 | 176 | ### Packet RTR 177 | 178 | ```arduino 179 | bool rtr = CAN.packetRtr(); 180 | ``` 181 | 182 | Returns the value of the Remote Transmission Request (RTR) field of the packet `true`/`false`. RTR packets contain no data, the DLC field is the requested data length. 183 | 184 | ### Packet DLC 185 | 186 | ```arduino 187 | int DLC = CAN.packetDlc(); 188 | ``` 189 | 190 | Returns the value of the Data Length Code (DLC) field of the packet. 191 | 192 | 193 | ### Available 194 | 195 | ```arduino 196 | int availableBytes = CAN.available() 197 | ``` 198 | 199 | Returns number of bytes available for reading. 200 | 201 | ### Peeking 202 | 203 | Peek at the next byte in the packet. 204 | 205 | ```arduino 206 | int b = CAN.peek(); 207 | ``` 208 | 209 | Returns the next byte in the packet or `-1` if no bytes are available. 210 | 211 | ### Reading 212 | 213 | Read the next byte from the packet. 214 | 215 | ```arduino 216 | int b = CAN.read(); 217 | ``` 218 | 219 | Returns the next byte in the packet or `-1` if no bytes are available. 220 | 221 | **Note:** Other Arduino [`Stream` API's](https://www.arduino.cc/en/Reference/Stream) can also be used to read data from the packet 222 | 223 | ### Filtering 224 | 225 | Filter packets that meet the desired criteria. 226 | 227 | ``` 228 | CAN.filter(id); 229 | CAN.filter(id, mask); 230 | 231 | CAN.filterExtended(id); 232 | CAN.filterExtended(id, mask); 233 | ``` 234 | 235 | * `id` - 11-bit id (standard packet) or 29-bit packet id (extended packet) 236 | * `mask` - (optional) 11-bit mask (standard packet) or 29-bit mask (extended packet), defaults to `0x7ff` or `0x1fffffff` (extended) 237 | 238 | Only packets that meet the following criteria are acknowleged and received, other packets are ignored: 239 | 240 | ``` 241 | if ((packetId & mask) == id) { 242 | // acknowleged and received 243 | } else { 244 | // ignored 245 | } 246 | ``` 247 | 248 | Returns `1` on success, `0` on failure. 249 | 250 | ## Other modes 251 | 252 | ### Loopback mode 253 | 254 | Put the CAN controller in loopback mode, any outgoing packets will also be received. 255 | 256 | ```arduino 257 | CAN.loopback(); 258 | ``` 259 | 260 | ### Sleep mode 261 | 262 | Put the CAN contoller in sleep mode. 263 | 264 | ```arduino 265 | CAN.sleep(); 266 | ``` 267 | 268 | Wake up the CAN contoller if it was previously in sleep mode. 269 | 270 | ```arduino 271 | CAN.wakeup(); 272 | ``` 273 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Sandeep Mistry 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Arduino CAN 2 | 3 | [![Build Status](https://travis-ci.org/sandeepmistry/arduino-CAN.svg?branch=master)](https://travis-ci.org/sandeepmistry/arduino-CAN) 4 | 5 | An Arduino library for sending and receiving data using CAN bus. 6 | 7 | ## Compatible Hardware 8 | 9 | * [Adafruit Feather M4 CAN Express](https://www.digikey.com/catalog/en/partgroup/sam-d5x-e5x/70620) and other [SAM E5x microcontrollers](https://www.digikey.com/catalog/en/partgroup/sam-d5x-e5x/70620) 10 | * [Microchip MCP2515](http://www.microchip.com/wwwproducts/en/en010406) based boards/shields 11 | * [Arduino MKR CAN shield](https://store.arduino.cc/arduino-mkr-can-shield) 12 | * [Espressif ESP32](http://espressif.com/en/products/hardware/esp32/overview)'s built-in [SJA1000](https://www.nxp.com/products/analog/interfaces/in-vehicle-network/can-transceiver-and-controllers/stand-alone-can-controller:SJA1000T) compatible CAN controller with an external 3.3V CAN transceiver 13 | 14 | ### Microchip MCP2515 wiring 15 | 16 | | Microchip MCP2515 | Arduino | 17 | | :---------------: | :-----: | 18 | | VCC | 5V | 19 | | GND | GND | 20 | | SCK | SCK | 21 | | SO | MISO | 22 | | SI | MOSI | 23 | | CS | 10 | 24 | | INT | 2 | 25 | 26 | 27 | `CS` and `INT` pins can be changed by using `CAN.setPins(cs, irq)`. `INT` pin is optional, it is only needed for receive callback mode. If `INT` pin is used, it **must** be interrupt capable via [`attachInterrupt(...)`](https://www.arduino.cc/en/Reference/AttachInterrupt). 28 | 29 | **NOTE**: Logic level converters must be used for boards which operate at 3.3V. 30 | 31 | ### Espressif ESP32 wiring 32 | 33 | Requires an external 3.3V CAN transceiver, such as a [TI SN65HVD230](http://www.ti.com/product/SN65HVD230). 34 | 35 | | CAN transceiver | ESP32 | 36 | | :-------------: | :---: | 37 | | 3V3 | 3V3 | 38 | | GND | GND | 39 | | CTX | 5 | 40 | | CRX | 4 | 41 | 42 | `CTX` and `CRX` pins can be changed by using `CAN.setPins(rx, tx)`. 43 | 44 | ## Installation 45 | 46 | ### Using the Arduino IDE Library Manager 47 | 48 | 1. Choose `Sketch` -> `Include Library` -> `Manage Libraries...` 49 | 2. Type `CAN` into the search box. 50 | 3. Click the row to select the library. 51 | 4. Click the `Install` button to install the library. 52 | 53 | ### Using Git 54 | 55 | ```sh 56 | cd ~/Documents/Arduino/libraries/ 57 | git clone https://github.com/sandeepmistry/arduino-CAN CAN 58 | ``` 59 | 60 | ## API 61 | 62 | See [API.md](API.md). 63 | 64 | ## Examples 65 | 66 | See [examples](examples) folder. 67 | 68 | For OBD-II examples, checkout the [arduino-OBD2](https://github.com/sandeepmistry/arduino-OBD2) library's [examples](https://github.com/sandeepmistry/arduino-OBD2/examples). 69 | 70 | ## License 71 | 72 | This library is [licensed](LICENSE) under the [MIT Licence](http://en.wikipedia.org/wiki/MIT_License). 73 | -------------------------------------------------------------------------------- /examples/CANReceiver/CANReceiver.ino: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #include 5 | 6 | void setup() { 7 | Serial.begin(9600); 8 | while (!Serial); 9 | 10 | Serial.println("CAN Receiver"); 11 | 12 | // start the CAN bus at 500 kbps 13 | if (!CAN.begin(500E3)) { 14 | Serial.println("Starting CAN failed!"); 15 | while (1); 16 | } 17 | } 18 | 19 | void loop() { 20 | // try to parse packet 21 | int packetSize = CAN.parsePacket(); 22 | 23 | if (packetSize) { 24 | // received a packet 25 | Serial.print("Received "); 26 | 27 | if (CAN.packetExtended()) { 28 | Serial.print("extended "); 29 | } 30 | 31 | if (CAN.packetRtr()) { 32 | // Remote transmission request, packet contains no data 33 | Serial.print("RTR "); 34 | } 35 | 36 | Serial.print("packet with id 0x"); 37 | Serial.print(CAN.packetId(), HEX); 38 | 39 | if (CAN.packetRtr()) { 40 | Serial.print(" and requested length "); 41 | Serial.println(CAN.packetDlc()); 42 | } else { 43 | Serial.print(" and length "); 44 | Serial.println(packetSize); 45 | 46 | // only print packet data for non-RTR packets 47 | while (CAN.available()) { 48 | Serial.print((char)CAN.read()); 49 | } 50 | Serial.println(); 51 | } 52 | 53 | Serial.println(); 54 | } 55 | } 56 | 57 | -------------------------------------------------------------------------------- /examples/CANReceiverCallback/CANReceiverCallback.ino: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #include 5 | 6 | void setup() { 7 | Serial.begin(9600); 8 | while (!Serial); 9 | 10 | Serial.println("CAN Receiver Callback"); 11 | 12 | // start the CAN bus at 500 kbps 13 | if (!CAN.begin(500E3)) { 14 | Serial.println("Starting CAN failed!"); 15 | while (1); 16 | } 17 | 18 | // register the receive callback 19 | CAN.onReceive(onReceive); 20 | } 21 | 22 | void loop() { 23 | // do nothing 24 | } 25 | 26 | void onReceive(int packetSize) { 27 | // received a packet 28 | Serial.print("Received "); 29 | 30 | if (CAN.packetExtended()) { 31 | Serial.print("extended "); 32 | } 33 | 34 | if (CAN.packetRtr()) { 35 | // Remote transmission request, packet contains no data 36 | Serial.print("RTR "); 37 | } 38 | 39 | Serial.print("packet with id 0x"); 40 | Serial.print(CAN.packetId(), HEX); 41 | 42 | if (CAN.packetRtr()) { 43 | Serial.print(" and requested length "); 44 | Serial.println(CAN.packetDlc()); 45 | } else { 46 | Serial.print(" and length "); 47 | Serial.println(packetSize); 48 | 49 | // only print packet data for non-RTR packets 50 | while (CAN.available()) { 51 | Serial.print((char)CAN.read()); 52 | } 53 | Serial.println(); 54 | } 55 | 56 | Serial.println(); 57 | } 58 | 59 | 60 | -------------------------------------------------------------------------------- /examples/CANSender/CANSender.ino: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #include 5 | 6 | void setup() { 7 | Serial.begin(9600); 8 | while (!Serial); 9 | 10 | Serial.println("CAN Sender"); 11 | 12 | // start the CAN bus at 500 kbps 13 | if (!CAN.begin(500E3)) { 14 | Serial.println("Starting CAN failed!"); 15 | while (1); 16 | } 17 | } 18 | 19 | void loop() { 20 | // send packet: id is 11 bits, packet can contain up to 8 bytes of data 21 | Serial.print("Sending packet ... "); 22 | 23 | CAN.beginPacket(0x12); 24 | CAN.write('h'); 25 | CAN.write('e'); 26 | CAN.write('l'); 27 | CAN.write('l'); 28 | CAN.write('o'); 29 | CAN.endPacket(); 30 | 31 | Serial.println("done"); 32 | 33 | delay(1000); 34 | 35 | // send extended packet: id is 29 bits, packet can contain up to 8 bytes of data 36 | Serial.print("Sending extended packet ... "); 37 | 38 | CAN.beginExtendedPacket(0xabcdef); 39 | CAN.write('w'); 40 | CAN.write('o'); 41 | CAN.write('r'); 42 | CAN.write('l'); 43 | CAN.write('d'); 44 | CAN.endPacket(); 45 | 46 | Serial.println("done"); 47 | 48 | delay(1000); 49 | } 50 | 51 | -------------------------------------------------------------------------------- /keywords.txt: -------------------------------------------------------------------------------- 1 | ####################################### 2 | # Syntax Coloring Map For CAN 3 | ####################################### 4 | 5 | ####################################### 6 | # Datatypes (KEYWORD1) 7 | ####################################### 8 | 9 | CAN KEYWORD1 10 | 11 | ####################################### 12 | # Methods and Functions (KEYWORD2) 13 | ####################################### 14 | 15 | begin KEYWORD2 16 | end KEYWORD2 17 | 18 | beginPacket KEYWORD2 19 | beginExtendedPacket KEYWORD2 20 | endPacket KEYWORD2 21 | 22 | parsePacket KEYWORD2 23 | packetId KEYWORD2 24 | packetExtended KEYWORD2 25 | packetRtr KEYWORD2 26 | packetDlc KEYWORD2 27 | 28 | write KEYWORD2 29 | 30 | available KEYWORD2 31 | read KEYWORD2 32 | peek KEYWORD2 33 | flush KEYWORD2 34 | 35 | onReceive KEYWORD2 36 | filter KEYWORD2 37 | filterExtended KEYWORD2 38 | loopback KEYWORD2 39 | sleep KEYWORD2 40 | wakeup KEYWORD2 41 | 42 | setPins KEYWORD2 43 | setSPIFrequency KEYWORD2 44 | setClockFrequency KEYWORD2 45 | dumpRegisters KEYWORD2 46 | 47 | ####################################### 48 | # Constants (LITERAL1) 49 | ####################################### 50 | -------------------------------------------------------------------------------- /library.properties: -------------------------------------------------------------------------------- 1 | name=CAN Adafruit Fork 2 | version=1.2.1 3 | author=Sandeep Mistry 4 | maintainer=adafruit 5 | sentence=An Arduino library for sending and receiving data using CAN bus. 6 | paragraph=Supports SAME5x series built-in CAN, Microchip MCP2515 based boards/shields and the Espressif ESP32's built-in SJA1000 compatible CAN controller. 7 | category=Communication 8 | url=https://github.com/adafruit/arduino-CAN 9 | architectures=* 10 | includes=CAN.h 11 | -------------------------------------------------------------------------------- /mkcandata.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python3 2 | 3 | def defines(name, suffix): 4 | print(f'const can_function {name}[] = {{') 5 | for instance in (0, 1): 6 | for function in 'HI': 7 | for port in 'ABCD': 8 | for idx in range(32): 9 | pin = f'P{port}{idx:02d}' 10 | pinmux = f'PINMUX_{pin}{function}_CAN{instance}_{suffix}' 11 | print(f'''\ 12 | #if defined({pinmux}) && !defined(IGNORE_PIN_{pin}) 13 | {{PIN_{pin} >> 5, PIN_{pin} & 0x1f, {instance}, {pinmux} & 0xf}}, 14 | #endif''') 15 | print(f'}};') 16 | 17 | print('''\ 18 | struct can_function { 19 | unsigned port : 3; 20 | unsigned pin : 5; 21 | unsigned instance : 1; 22 | unsigned mux : 4; 23 | }; 24 | ''') 25 | 26 | defines('can_rx', 'RX') 27 | print() 28 | defines('can_tx', 'TX') 29 | -------------------------------------------------------------------------------- /src/CAN.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #ifndef CAN_H 5 | #define CAN_H 6 | 7 | #if defined(ADAFRUIT_FEATHER_M4_CAN) 8 | #include "CANSAME5x.h" 9 | #elif defined(ARDUINO_ARCH_ESP32) 10 | #include "ESP32SJA1000.h" 11 | #else 12 | #include "MCP2515.h" 13 | #endif 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /src/CANController.cpp: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #include "CANController.h" 5 | 6 | CANControllerClass::CANControllerClass() : 7 | _onReceive(NULL), 8 | 9 | _packetBegun(false), 10 | _txId(-1), 11 | _txExtended(-1), 12 | _txRtr(false), 13 | _txDlc(0), 14 | _txLength(0), 15 | 16 | _rxId(-1), 17 | _rxExtended(false), 18 | _rxRtr(false), 19 | _rxDlc(0), 20 | _rxLength(0), 21 | _rxIndex(0) 22 | { 23 | // overide Stream timeout value 24 | setTimeout(0); 25 | } 26 | 27 | CANControllerClass::~CANControllerClass() 28 | { 29 | } 30 | 31 | int CANControllerClass::begin(long /*baudRate*/) 32 | { 33 | _packetBegun = false; 34 | _txId = -1; 35 | _txRtr =false; 36 | _txDlc = 0; 37 | _txLength = 0; 38 | 39 | _rxId = -1; 40 | _rxRtr = false; 41 | _rxDlc = 0; 42 | _rxLength = 0; 43 | _rxIndex = 0; 44 | 45 | return 1; 46 | } 47 | 48 | void CANControllerClass::end() 49 | { 50 | } 51 | 52 | int CANControllerClass::beginPacket(int id, int dlc, bool rtr) 53 | { 54 | if (id < 0 || id > 0x7FF) { 55 | return 0; 56 | } 57 | 58 | if (dlc > 8) { 59 | return 0; 60 | } 61 | 62 | _packetBegun = true; 63 | _txId = id; 64 | _txExtended = false; 65 | _txRtr = rtr; 66 | _txDlc = dlc; 67 | _txLength = 0; 68 | 69 | memset(_txData, 0x00, sizeof(_txData)); 70 | 71 | return 1; 72 | } 73 | 74 | int CANControllerClass::beginExtendedPacket(long id, int dlc, bool rtr) 75 | { 76 | if (id < 0 || id > 0x1FFFFFFF) { 77 | return 0; 78 | } 79 | 80 | if (dlc > 8) { 81 | return 0; 82 | } 83 | 84 | _packetBegun = true; 85 | _txId = id; 86 | _txExtended = true; 87 | _txRtr = rtr; 88 | _txDlc = dlc; 89 | _txLength = 0; 90 | 91 | memset(_txData, 0x00, sizeof(_txData)); 92 | 93 | return 1; 94 | } 95 | 96 | int CANControllerClass::endPacket() 97 | { 98 | if (!_packetBegun) { 99 | return 0; 100 | } 101 | _packetBegun = false; 102 | 103 | if (_txDlc >= 0) { 104 | _txLength = _txDlc; 105 | } 106 | 107 | return 1; 108 | } 109 | 110 | int CANControllerClass::parsePacket() 111 | { 112 | return 0; 113 | } 114 | 115 | long CANControllerClass::packetId() 116 | { 117 | return _rxId; 118 | } 119 | 120 | bool CANControllerClass::packetExtended() 121 | { 122 | return _rxExtended; 123 | } 124 | 125 | bool CANControllerClass::packetRtr() 126 | { 127 | return _rxRtr; 128 | } 129 | 130 | int CANControllerClass::packetDlc() 131 | { 132 | return _rxDlc; 133 | } 134 | 135 | size_t CANControllerClass::write(uint8_t byte) 136 | { 137 | return write(&byte, sizeof(byte)); 138 | } 139 | 140 | size_t CANControllerClass::write(const uint8_t *buffer, size_t size) 141 | { 142 | if (!_packetBegun) { 143 | return 0; 144 | } 145 | 146 | if (size > (sizeof(_txData) - _txLength)) { 147 | size = sizeof(_txData) - _txLength; 148 | } 149 | 150 | memcpy(&_txData[_txLength], buffer, size); 151 | _txLength += size; 152 | 153 | return size; 154 | } 155 | 156 | int CANControllerClass::available() 157 | { 158 | return (_rxLength - _rxIndex); 159 | } 160 | 161 | int CANControllerClass::read() 162 | { 163 | if (!available()) { 164 | return -1; 165 | } 166 | 167 | return _rxData[_rxIndex++]; 168 | } 169 | 170 | int CANControllerClass::peek() 171 | { 172 | if (!available()) { 173 | return -1; 174 | } 175 | 176 | return _rxData[_rxIndex]; 177 | } 178 | 179 | void CANControllerClass::flush() 180 | { 181 | } 182 | 183 | void CANControllerClass::onReceive(void(*callback)(int)) 184 | { 185 | _onReceive = callback; 186 | } 187 | 188 | int CANControllerClass::filter(int /*id*/, int /*mask*/) 189 | { 190 | return 0; 191 | } 192 | 193 | int CANControllerClass::filterExtended(long /*id*/, long /*mask*/) 194 | { 195 | return 0; 196 | } 197 | 198 | int CANControllerClass::observe() 199 | { 200 | return 0; 201 | } 202 | 203 | int CANControllerClass::loopback() 204 | { 205 | return 0; 206 | } 207 | 208 | int CANControllerClass::sleep() 209 | { 210 | return 0; 211 | } 212 | 213 | int CANControllerClass::wakeup() 214 | { 215 | return 0; 216 | } 217 | -------------------------------------------------------------------------------- /src/CANController.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #ifndef CAN_CONTROLLER_H 5 | #define CAN_CONTROLLER_H 6 | 7 | #include 8 | 9 | class CANControllerClass : public Stream { 10 | 11 | public: 12 | virtual int begin(long baudRate); 13 | virtual void end(); 14 | 15 | int beginPacket(int id, int dlc = -1, bool rtr = false); 16 | int beginExtendedPacket(long id, int dlc = -1, bool rtr = false); 17 | virtual int endPacket(); 18 | 19 | virtual int parsePacket(); 20 | long packetId(); 21 | bool packetExtended(); 22 | bool packetRtr(); 23 | int packetDlc(); 24 | 25 | // from Print 26 | virtual size_t write(uint8_t byte); 27 | virtual size_t write(const uint8_t *buffer, size_t size); 28 | 29 | // from Stream 30 | virtual int available(); 31 | virtual int read(); 32 | virtual int peek(); 33 | virtual void flush(); 34 | 35 | virtual void onReceive(void(*callback)(int)); 36 | 37 | virtual int filter(int id) { return filter(id, 0x7ff); } 38 | virtual int filter(int id, int mask); 39 | virtual int filterExtended(long id) { return filterExtended(id, 0x1fffffff); } 40 | virtual int filterExtended(long id, long mask); 41 | 42 | virtual int observe(); 43 | virtual int loopback(); 44 | virtual int sleep(); 45 | virtual int wakeup(); 46 | 47 | protected: 48 | CANControllerClass(); 49 | virtual ~CANControllerClass(); 50 | 51 | protected: 52 | void (*_onReceive)(int); 53 | 54 | bool _packetBegun; 55 | long _txId; 56 | bool _txExtended; 57 | bool _txRtr; 58 | int _txDlc; 59 | int _txLength; 60 | uint8_t _txData[8]; 61 | 62 | long _rxId; 63 | bool _rxExtended; 64 | bool _rxRtr; 65 | int _rxDlc; 66 | int _rxLength; 67 | int _rxIndex; 68 | uint8_t _rxData[8]; 69 | }; 70 | 71 | #endif 72 | -------------------------------------------------------------------------------- /src/CANSAME5x.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2020 © Jeff Epler for Adafruit Industries. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full 3 | // license information. 4 | 5 | #if defined(ADAFRUIT_FEATHER_M4_CAN) 6 | #include 7 | #include 8 | 9 | #include "CANSAME5x.h" 10 | #include "wiring_private.h" 11 | 12 | #define DEBUG_CAN (0) 13 | #if DEBUG_CAN 14 | #define DEBUG_PRINT(...) (Serial.print(__VA_ARGS__), ((void)0)) 15 | #define DEBUG_PRINTLN(...) (Serial.println(__VA_ARGS__), ((void)0)) 16 | #else 17 | #define DEBUG_PRINT(...) ((void)0) 18 | #define DEBUG_PRINTLN(...) ((void)0) 19 | #endif 20 | 21 | namespace { 22 | #include "CANSAME5x_port.h" 23 | } 24 | 25 | #define hw (reinterpret_cast(this->_hw)) 26 | #define state (reinterpret_cast<_canSAME5x_state *>(this->_state)) 27 | 28 | #define DIV_ROUND(a, b) (((a) + (b) / 2) / (b)) 29 | #define DIV_ROUND_UP(a, b) (((a) + (b)-1) / (b)) 30 | 31 | #define GCLK_CAN1 GCLK_PCHCTRL_GEN_GCLK1_Val 32 | #define GCLK_CAN0 GCLK_PCHCTRL_GEN_GCLK1_Val 33 | #define ADAFRUIT_ZEROCAN_TX_BUFFER_SIZE (1) 34 | #define ADAFRUIT_ZEROCAN_RX_FILTER_SIZE (1) 35 | #define ADAFRUIT_ZEROCAN_RX_FIFO_SIZE (8) 36 | #define ADAFRUIT_ZEROCAN_MAX_MESSAGE_LENGTH (8) 37 | 38 | namespace { 39 | 40 | template 41 | constexpr size_t size(const T (&array)[N]) noexcept { 42 | return N; 43 | } 44 | 45 | // Adapted from ASF3 interrupt_sam_nvic.c: 46 | 47 | volatile unsigned long cpu_irq_critical_section_counter = 0; 48 | volatile unsigned char cpu_irq_prev_interrupt_state = 0; 49 | 50 | void cpu_irq_enter_critical(void) { 51 | if (!cpu_irq_critical_section_counter) { 52 | if (__get_PRIMASK() == 0) { // IRQ enabled? 53 | __disable_irq(); // Disable it 54 | __DMB(); 55 | cpu_irq_prev_interrupt_state = 1; 56 | } else { 57 | // Make sure the to save the prev state as false 58 | cpu_irq_prev_interrupt_state = 0; 59 | } 60 | } 61 | 62 | cpu_irq_critical_section_counter++; 63 | } 64 | 65 | void cpu_irq_leave_critical(void) { 66 | // Check if the user is trying to leave a critical section 67 | // when not in a critical section 68 | if (cpu_irq_critical_section_counter > 0) { 69 | cpu_irq_critical_section_counter--; 70 | 71 | // Only enable global interrupts when the counter 72 | // reaches 0 and the state of the global interrupt flag 73 | // was enabled when entering critical state */ 74 | if ((!cpu_irq_critical_section_counter) && cpu_irq_prev_interrupt_state) { 75 | __DMB(); 76 | __enable_irq(); 77 | } 78 | } 79 | } 80 | 81 | // This appears to be a typo (transposition error) in the ASF4 headers 82 | // It's called the "Extended ID Filter Entry" 83 | typedef CanMramXifde CanMramXidfe; 84 | 85 | typedef uint32_t can_filter_t; 86 | 87 | struct _canSAME5x_tx_buf { 88 | CAN_TXBE_0_Type txb0; 89 | CAN_TXBE_1_Type txb1; 90 | __attribute__((aligned(4))) uint8_t data[8]; 91 | }; 92 | 93 | struct _canSAME5x_rx_fifo { 94 | CAN_RXF0E_0_Type rxf0; 95 | CAN_RXF0E_1_Type rxf1; 96 | __attribute((aligned(4))) uint8_t data[ADAFRUIT_ZEROCAN_MAX_MESSAGE_LENGTH]; 97 | } can_rx_fifo_t; 98 | 99 | struct _canSAME5x_state { 100 | _canSAME5x_tx_buf tx_buffer[ADAFRUIT_ZEROCAN_TX_BUFFER_SIZE]; 101 | _canSAME5x_rx_fifo rx_fifo[ADAFRUIT_ZEROCAN_RX_FIFO_SIZE]; 102 | CanMramSidfe standard_rx_filter[ADAFRUIT_ZEROCAN_RX_FILTER_SIZE]; 103 | CanMramXifde extended_rx_filter[ADAFRUIT_ZEROCAN_RX_FILTER_SIZE]; 104 | }; 105 | 106 | // This data must be in the first 64kB of RAM. The "canram" section 107 | // receives special support from the linker file in the Feather M4 CAN's 108 | // board support package. 109 | __attribute__((section(".canram"))) _canSAME5x_state can_state[2]; 110 | 111 | constexpr uint32_t can_frequency = VARIANT_GCLK1_FREQ; 112 | bool compute_nbtp(uint32_t baudrate, CAN_NBTP_Type &result) { 113 | uint32_t clocks_per_bit = DIV_ROUND(can_frequency, baudrate); 114 | uint32_t clocks_to_sample = DIV_ROUND(clocks_per_bit * 7, 8); 115 | uint32_t clocks_after_sample = clocks_per_bit - clocks_to_sample; 116 | uint32_t divisor = max(DIV_ROUND_UP(clocks_to_sample, 256), 117 | DIV_ROUND_UP(clocks_after_sample, 128)); 118 | if (divisor > 32) { 119 | return false; 120 | } 121 | result.bit.NTSEG1 = DIV_ROUND(clocks_to_sample, divisor) - 2; 122 | result.bit.NTSEG2 = DIV_ROUND(clocks_after_sample, divisor) - 1; 123 | result.bit.NBRP = divisor - 1; 124 | result.bit.NSJW = DIV_ROUND(clocks_after_sample, divisor * 4); 125 | return true; 126 | } 127 | 128 | EPioType find_pin(const can_function *table, size_t n, int arduino_pin, 129 | int &instance) { 130 | if (arduino_pin < 0 || arduino_pin > PINS_COUNT) { 131 | return (EPioType)-1; 132 | } 133 | 134 | unsigned port = g_APinDescription[arduino_pin].ulPort; 135 | unsigned pin = g_APinDescription[arduino_pin].ulPin; 136 | for (size_t i = 0; i < n; i++) { 137 | if (table[i].port == port && table[i].pin == pin) { 138 | if (instance == -1 || table[i].instance == instance) { 139 | DEBUG_PRINT("found #"); 140 | DEBUG_PRINTLN(i); 141 | instance = table[i].instance; 142 | return EPioType(table[i].mux); 143 | } 144 | } 145 | } 146 | return (EPioType)-1; 147 | } 148 | 149 | } // namespace 150 | 151 | CANSAME5x::CANSAME5x(uint8_t TX_PIN, uint8_t RX_PIN) 152 | : _tx(TX_PIN), _rx(RX_PIN) {} 153 | #ifdef PIN_CAN_TX 154 | CANSAME5x::CANSAME5x() : _tx(PIN_CAN_TX), _rx(PIN_CAN_RX) {} 155 | #else 156 | CANSAME5x::CANSAME5x() : _tx(-1) {} 157 | #endif 158 | 159 | CANSAME5x::~CANSAME5x() {} 160 | 161 | int CANSAME5x::begin(long baudrate) { 162 | if (_tx == -1) { 163 | return 0; 164 | } 165 | 166 | DEBUG_PRINT("_rx "); 167 | DEBUG_PRINT(_rx); 168 | DEBUG_PRINT(" ulPort="); 169 | DEBUG_PRINT(g_APinDescription[_rx].ulPort); 170 | DEBUG_PRINT(" ulPin="); 171 | DEBUG_PRINTLN(g_APinDescription[_rx].ulPin); 172 | 173 | DEBUG_PRINTLN("rx pin table"); 174 | for (size_t i = 0; i < size(can_rx); i++) { 175 | DEBUG_PRINT(i); 176 | DEBUG_PRINT(" port="); 177 | DEBUG_PRINT(can_rx[i].port); 178 | DEBUG_PRINT(" pin="); 179 | DEBUG_PRINT(can_rx[i].pin); 180 | DEBUG_PRINT(" instance="); 181 | DEBUG_PRINTLN(can_rx[i].instance); 182 | } 183 | 184 | DEBUG_PRINT("_tx "); 185 | DEBUG_PRINT(_tx); 186 | DEBUG_PRINT(" ulPort="); 187 | DEBUG_PRINT(g_APinDescription[_tx].ulPort); 188 | DEBUG_PRINT(" ulPin="); 189 | DEBUG_PRINTLN(g_APinDescription[_tx].ulPin); 190 | 191 | DEBUG_PRINTLN("tx pin table"); 192 | for (size_t i = 0; i < size(can_tx); i++) { 193 | DEBUG_PRINT(i); 194 | DEBUG_PRINT(" port="); 195 | DEBUG_PRINT(can_tx[i].port); 196 | DEBUG_PRINT(" pin="); 197 | DEBUG_PRINT(can_tx[i].pin); 198 | DEBUG_PRINT(" instance="); 199 | DEBUG_PRINTLN(can_tx[i].instance); 200 | } 201 | 202 | int instance = -1; 203 | EPioType tx_function = find_pin(can_tx, size(can_tx), _tx, instance); 204 | EPioType rx_function = find_pin(can_rx, size(can_rx), _rx, instance); 205 | 206 | if (tx_function == EPioType(-1) || rx_function == EPioType(-1) || 207 | instance == -1) { 208 | return 0; 209 | } 210 | 211 | CAN_NBTP_Type nbtp; 212 | if (!compute_nbtp(baudrate, nbtp)) { 213 | return 0; 214 | } 215 | 216 | _idx = instance; 217 | _hw = reinterpret_cast(_idx == 0 ? CAN0 : CAN1); 218 | _state = reinterpret_cast(&can_state[_idx]); 219 | 220 | memset(state, 0, sizeof(*state)); 221 | 222 | pinPeripheral(_tx, tx_function); 223 | pinPeripheral(_rx, rx_function); 224 | 225 | if (_idx == 0) { 226 | GCLK->PCHCTRL[CAN0_GCLK_ID].reg = GCLK_CAN0 | (1 << GCLK_PCHCTRL_CHEN_Pos); 227 | } else { 228 | GCLK->PCHCTRL[CAN1_GCLK_ID].reg = GCLK_CAN1 | (1 << GCLK_PCHCTRL_CHEN_Pos); 229 | } 230 | // reset and allow configuration change 231 | hw->CCCR.bit.INIT = 1; 232 | while (!hw->CCCR.bit.INIT) { 233 | } 234 | hw->CCCR.bit.CCE = 1; 235 | 236 | // All TX data has an 8 byte payload (max) 237 | { 238 | CAN_TXESC_Type esc = {}; 239 | esc.bit.TBDS = CAN_TXESC_TBDS_DATA8_Val; 240 | hw->TXESC.reg = esc.reg; 241 | } 242 | 243 | // Set up TX buffer 244 | { 245 | CAN_TXBC_Type bc = {}; 246 | bc.bit.TBSA = (uint32_t)state->tx_buffer; 247 | bc.bit.NDTB = ADAFRUIT_ZEROCAN_TX_BUFFER_SIZE; 248 | bc.bit.TFQM = 0; // Messages are transmitted in the order submitted 249 | hw->TXBC.reg = bc.reg; 250 | } 251 | 252 | // All RX data has an 8 byte payload (max) 253 | { 254 | CAN_RXESC_Type esc = {}; 255 | esc.bit.F0DS = CAN_RXESC_F0DS_DATA8_Val; 256 | esc.bit.F1DS = CAN_RXESC_F1DS_DATA8_Val; 257 | esc.bit.RBDS = CAN_RXESC_RBDS_DATA8_Val; 258 | hw->RXESC.reg = esc.reg; 259 | } 260 | 261 | // Set up RX fifo 0 262 | { 263 | CAN_RXF0C_Type rxf = {}; 264 | rxf.bit.F0SA = (uint32_t)state->rx_fifo; 265 | rxf.bit.F0S = ADAFRUIT_ZEROCAN_RX_FIFO_SIZE; 266 | hw->RXF0C.reg = rxf.reg; 267 | } 268 | 269 | // Reject all packets not explicitly requested 270 | { 271 | CAN_GFC_Type gfc = {}; 272 | gfc.bit.RRFE = 0; 273 | gfc.bit.ANFS = CAN_GFC_ANFS_REJECT_Val; 274 | gfc.bit.ANFE = CAN_GFC_ANFE_REJECT_Val; 275 | hw->GFC.reg = gfc.reg; 276 | } 277 | 278 | // Initially, receive all standard and extended packets to FIFO 0 279 | state->standard_rx_filter[0].SIDFE_0.bit.SFID1 = 0; // ID 280 | state->standard_rx_filter[0].SIDFE_0.bit.SFID2 = 0; // mask 281 | state->standard_rx_filter[0].SIDFE_0.bit.SFEC = CAN_SIDFE_0_SFEC_STF0M_Val; 282 | state->standard_rx_filter[0].SIDFE_0.bit.SFT = CAN_SIDFE_0_SFT_CLASSIC_Val; 283 | 284 | state->extended_rx_filter[0].XIDFE_0.bit.EFID1 = 0; // ID 285 | state->extended_rx_filter[0].XIDFE_0.bit.EFEC = CAN_XIDFE_0_EFEC_STF0M_Val; 286 | state->extended_rx_filter[0].XIDFE_1.bit.EFID2 = 0; // mask 287 | state->extended_rx_filter[0].XIDFE_1.bit.EFT = CAN_XIDFE_1_EFT_CLASSIC_Val; 288 | 289 | // Set up standard RX filters 290 | { 291 | CAN_SIDFC_Type dfc = {}; 292 | dfc.bit.LSS = ADAFRUIT_ZEROCAN_RX_FILTER_SIZE; 293 | dfc.bit.FLSSA = (uint32_t)state->standard_rx_filter; 294 | hw->SIDFC.reg = dfc.reg; 295 | } 296 | 297 | // Set up extended RX filters 298 | { 299 | CAN_XIDFC_Type dfc = {}; 300 | dfc.bit.LSE = ADAFRUIT_ZEROCAN_RX_FILTER_SIZE; 301 | dfc.bit.FLESA = (uint32_t)state->extended_rx_filter; 302 | hw->XIDFC.reg = dfc.reg; 303 | } 304 | 305 | // Enable receive IRQ (masked until enabled in NVIC) 306 | hw->IE.bit.RF0NE = true; 307 | if (_idx == 0) { 308 | hw->ILE.bit.EINT0 = true; 309 | } else { 310 | hw->ILE.bit.EINT1 = true; 311 | } 312 | hw->ILS.bit.RF0NL = _idx; 313 | 314 | // Set nominal baud rate 315 | hw->NBTP.reg = nbtp.reg; 316 | 317 | // hardware is ready for use 318 | hw->CCCR.bit.CCE = 0; 319 | hw->CCCR.bit.INIT = 0; 320 | while (hw->CCCR.bit.INIT) { 321 | } 322 | 323 | instances[_idx] = this; 324 | 325 | return 1; 326 | } 327 | 328 | void CANSAME5x::end() { 329 | instances[_idx] = 0; 330 | pinMode(_tx, INPUT); 331 | pinMode(_rx, INPUT); 332 | // reset and disable clock 333 | hw->CCCR.bit.INIT = 1; 334 | while (!hw->CCCR.bit.INIT) { 335 | } 336 | if (_idx == 0) { 337 | GCLK->PCHCTRL[CAN0_GCLK_ID].reg = 0; 338 | } else { 339 | GCLK->PCHCTRL[CAN1_GCLK_ID].reg = 0; 340 | } 341 | } 342 | 343 | int CANSAME5x::endPacket() { 344 | if (!CANControllerClass::endPacket()) { 345 | return 0; 346 | } 347 | 348 | bus_autorecover(); 349 | 350 | // TODO wait for TX buffer to free 351 | 352 | _canSAME5x_tx_buf &buf = state->tx_buffer[0]; 353 | buf.txb0.bit.ESI = false; 354 | buf.txb0.bit.XTD = _txExtended; 355 | buf.txb0.bit.RTR = _txRtr; 356 | if (_txExtended) { 357 | buf.txb0.bit.ID = _txId; 358 | } else { 359 | buf.txb0.bit.ID = _txId << 18; 360 | } 361 | buf.txb1.bit.MM = 0; 362 | buf.txb1.bit.EFC = 0; 363 | buf.txb1.bit.FDF = 0; 364 | buf.txb1.bit.BRS = 0; 365 | buf.txb1.bit.DLC = _txLength; 366 | 367 | if (!_txRtr) { 368 | memcpy(buf.data, _txData, _txLength); 369 | } 370 | 371 | // TX buffer add request 372 | hw->TXBAR.reg = 1; 373 | 374 | // wait 8ms (hard coded for now) for TX to occur 375 | for (int i = 0; i < 8000; i++) { 376 | if (hw->TXBTO.reg & 1) { 377 | return true; 378 | } 379 | yield(); 380 | } 381 | 382 | return 1; 383 | } 384 | 385 | int CANSAME5x::_parsePacket() { 386 | if (!hw->RXF0S.bit.F0FL) { 387 | return 0; 388 | } 389 | 390 | int index = hw->RXF0S.bit.F0GI; 391 | auto &hw_message = state->rx_fifo[index]; 392 | 393 | _rxExtended = hw_message.rxf0.bit.XTD; 394 | _rxRtr = hw_message.rxf0.bit.RTR; 395 | _rxDlc = hw_message.rxf1.bit.DLC; 396 | 397 | if (_rxExtended) { 398 | _rxId = hw_message.rxf0.bit.ID; 399 | } else { 400 | _rxId = hw_message.rxf0.bit.ID >> 18; 401 | } 402 | 403 | if (_rxRtr) { 404 | _rxLength = 0; 405 | } else { 406 | _rxLength = _rxDlc; 407 | memcpy(_rxData, hw_message.data, _rxLength); 408 | } 409 | 410 | _rxIndex = 0; 411 | 412 | hw->RXF0A.bit.F0AI = index; 413 | 414 | return _rxDlc; 415 | } 416 | 417 | int CANSAME5x::parsePacket() { 418 | cpu_irq_enter_critical(); 419 | bus_autorecover(); 420 | int result = _parsePacket(); 421 | cpu_irq_leave_critical(); 422 | return result; 423 | } 424 | 425 | void CANSAME5x::onReceive(void (*callback)(int)) { 426 | CANControllerClass::onReceive(callback); 427 | 428 | auto irq = _idx == 0 ? CAN0_IRQn : CAN1_IRQn; 429 | if (callback) { 430 | NVIC_EnableIRQ(irq); 431 | } else { 432 | NVIC_DisableIRQ(irq); 433 | } 434 | } 435 | 436 | void CANSAME5x::handleInterrupt() { 437 | uint32_t ir = hw->IR.reg; 438 | 439 | if (ir & CAN_IR_RF0N) { 440 | while (int i = parsePacket()) 441 | _onReceive(i); 442 | } 443 | 444 | hw->IR.reg = ir; 445 | } 446 | 447 | int CANSAME5x::filter(int id, int mask) { 448 | // accept matching standard messages 449 | state->standard_rx_filter[0].SIDFE_0.bit.SFID1 = id; 450 | state->standard_rx_filter[0].SIDFE_0.bit.SFID2 = mask; 451 | state->standard_rx_filter[0].SIDFE_0.bit.SFEC = CAN_SIDFE_0_SFEC_STF0M_Val; 452 | state->standard_rx_filter[0].SIDFE_0.bit.SFT = CAN_SIDFE_0_SFT_CLASSIC_Val; 453 | 454 | // reject all extended messages 455 | state->extended_rx_filter[0].XIDFE_0.bit.EFID1 = 0; // ID 456 | state->extended_rx_filter[0].XIDFE_0.bit.EFEC = CAN_XIDFE_0_EFEC_REJECT_Val; 457 | state->extended_rx_filter[0].XIDFE_1.bit.EFID2 = 0; // mask 458 | state->extended_rx_filter[0].XIDFE_1.bit.EFT = CAN_XIDFE_1_EFT_CLASSIC_Val; 459 | 460 | return 1; 461 | } 462 | 463 | int CANSAME5x::filterExtended(long id, long mask) { 464 | // reject all standard messages 465 | state->standard_rx_filter[0].SIDFE_0.bit.SFID1 = 0; 466 | state->standard_rx_filter[0].SIDFE_0.bit.SFID2 = 0; 467 | state->standard_rx_filter[0].SIDFE_0.bit.SFEC = CAN_SIDFE_0_SFEC_REJECT_Val; 468 | state->standard_rx_filter[0].SIDFE_0.bit.SFT = CAN_SIDFE_0_SFT_CLASSIC_Val; 469 | 470 | // accept matching extended messages 471 | state->extended_rx_filter[0].XIDFE_0.bit.EFID1 = id; 472 | state->extended_rx_filter[0].XIDFE_0.bit.EFEC = CAN_XIDFE_0_EFEC_STF0M_Val; 473 | state->extended_rx_filter[0].XIDFE_1.bit.EFID2 = mask; 474 | state->extended_rx_filter[0].XIDFE_1.bit.EFT = CAN_XIDFE_1_EFT_CLASSIC_Val; 475 | 476 | return 1; 477 | } 478 | 479 | int CANSAME5x::observe() { 480 | hw->CCCR.bit.INIT = 1; 481 | while (!hw->CCCR.bit.INIT) { 482 | } 483 | hw->CCCR.bit.CCE = 1; 484 | 485 | hw->CCCR.bit.MON = 1; 486 | 487 | hw->CCCR.bit.CCE = 0; 488 | hw->CCCR.bit.INIT = 0; 489 | while (hw->CCCR.bit.INIT) { 490 | } 491 | return 1; 492 | } 493 | 494 | int CANSAME5x::loopback() { 495 | hw->CCCR.bit.INIT = 1; 496 | while (!hw->CCCR.bit.INIT) { 497 | } 498 | hw->CCCR.bit.CCE = 1; 499 | 500 | hw->CCCR.bit.TEST = 1; 501 | hw->TEST.bit.LBCK = 1; 502 | 503 | hw->CCCR.bit.CCE = 0; 504 | hw->CCCR.bit.INIT = 0; 505 | while (hw->CCCR.bit.INIT) { 506 | } 507 | return 1; 508 | } 509 | 510 | int CANSAME5x::sleep() { 511 | hw->CCCR.bit.CSR = 1; 512 | while (!hw->CCCR.bit.CSA) { 513 | } 514 | if (_idx == 0) { 515 | GCLK->PCHCTRL[CAN0_GCLK_ID].reg = 0; 516 | } else { 517 | GCLK->PCHCTRL[CAN1_GCLK_ID].reg = 0; 518 | } 519 | return 1; 520 | } 521 | 522 | int CANSAME5x::wakeup() { 523 | if (_idx == 0) { 524 | GCLK->PCHCTRL[CAN0_GCLK_ID].reg = GCLK_CAN0 | (1 << GCLK_PCHCTRL_CHEN_Pos); 525 | } else { 526 | GCLK->PCHCTRL[CAN1_GCLK_ID].reg = GCLK_CAN1 | (1 << GCLK_PCHCTRL_CHEN_Pos); 527 | } 528 | hw->CCCR.bit.INIT = 0; 529 | while (hw->CCCR.bit.INIT) { 530 | } 531 | return 1; 532 | } 533 | 534 | void CANSAME5x::bus_autorecover() { 535 | if (hw->PSR.bit.BO) { 536 | DEBUG_PRINTLN("bus autorecovery activated"); 537 | hw->CCCR.bit.INIT = 0; 538 | while (hw->CCCR.bit.INIT) { 539 | } 540 | } 541 | } 542 | 543 | void CANSAME5x::onInterrupt() { 544 | for (int i = 0; i < size(instances); i++) { 545 | CANSAME5x *instance = instances[i]; 546 | if (instance) { 547 | instance->handleInterrupt(); 548 | } 549 | } 550 | } 551 | 552 | extern "C" __attribute__((externally_visible)) void CAN0_Handler() { 553 | cpu_irq_enter_critical(); 554 | CANSAME5x::onInterrupt(); 555 | cpu_irq_leave_critical(); 556 | } 557 | 558 | extern "C" __attribute__((externally_visible)) void CAN1_Handler() { 559 | cpu_irq_enter_critical(); 560 | CANSAME5x::onInterrupt(); 561 | cpu_irq_leave_critical(); 562 | } 563 | 564 | CANSAME5x *CANSAME5x::instances[2]; 565 | 566 | CANSAME5x CAN; 567 | 568 | #endif 569 | -------------------------------------------------------------------------------- /src/CANSAME5x.h: -------------------------------------------------------------------------------- 1 | // Copyright 2020 © Jeff Epler for Adafruit Industries. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full 3 | // license information. 4 | 5 | #include "CANController.h" 6 | 7 | class CANSAME5x : public CANControllerClass { 8 | public: 9 | CANSAME5x(); 10 | CANSAME5x(uint8_t tx_pin, uint8_t rx_pin); 11 | ~CANSAME5x() final; 12 | 13 | int begin(long baudRate) final; 14 | void end() final; 15 | 16 | int endPacket() final; 17 | 18 | int parsePacket() final; 19 | 20 | void onReceive(void (*callback)(int)) final; 21 | 22 | using CANControllerClass::filter; 23 | int filter(int id, int mask) final; 24 | using CANControllerClass::filterExtended; 25 | int filterExtended(long id, long mask) final; 26 | 27 | int observe() final; 28 | int loopback() final; 29 | int sleep() final; 30 | int wakeup() final; 31 | 32 | void dumpRegisters(Stream &out); 33 | 34 | private: 35 | void bus_autorecover(); 36 | 37 | void handleInterrupt(); 38 | 39 | int _parsePacket(); 40 | 41 | private: 42 | int8_t _tx, _rx; 43 | int8_t _idx; 44 | // intr_handle_t _intrHandle; 45 | void *_state; 46 | void *_hw; 47 | static CANSAME5x *instances[2]; 48 | 49 | static void onInterrupt(); 50 | 51 | friend void CAN0_Handler(void); 52 | friend void CAN1_Handler(void); 53 | }; 54 | 55 | extern CANSAME5x CAN; 56 | -------------------------------------------------------------------------------- /src/CANSAME5x_port.h: -------------------------------------------------------------------------------- 1 | struct can_function { 2 | unsigned port : 3; 3 | unsigned pin : 5; 4 | unsigned instance : 1; 5 | unsigned mux : 4; 6 | }; 7 | 8 | const can_function can_rx[] = { 9 | #if defined(PINMUX_PA00H_CAN0_RX) && !defined(IGNORE_PIN_PA00) 10 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 0, PINMUX_PA00H_CAN0_RX & 0xf}, 11 | #endif 12 | #if defined(PINMUX_PA01H_CAN0_RX) && !defined(IGNORE_PIN_PA01) 13 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 0, PINMUX_PA01H_CAN0_RX & 0xf}, 14 | #endif 15 | #if defined(PINMUX_PA02H_CAN0_RX) && !defined(IGNORE_PIN_PA02) 16 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 0, PINMUX_PA02H_CAN0_RX & 0xf}, 17 | #endif 18 | #if defined(PINMUX_PA03H_CAN0_RX) && !defined(IGNORE_PIN_PA03) 19 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 0, PINMUX_PA03H_CAN0_RX & 0xf}, 20 | #endif 21 | #if defined(PINMUX_PA04H_CAN0_RX) && !defined(IGNORE_PIN_PA04) 22 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 0, PINMUX_PA04H_CAN0_RX & 0xf}, 23 | #endif 24 | #if defined(PINMUX_PA05H_CAN0_RX) && !defined(IGNORE_PIN_PA05) 25 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 0, PINMUX_PA05H_CAN0_RX & 0xf}, 26 | #endif 27 | #if defined(PINMUX_PA06H_CAN0_RX) && !defined(IGNORE_PIN_PA06) 28 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 0, PINMUX_PA06H_CAN0_RX & 0xf}, 29 | #endif 30 | #if defined(PINMUX_PA07H_CAN0_RX) && !defined(IGNORE_PIN_PA07) 31 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 0, PINMUX_PA07H_CAN0_RX & 0xf}, 32 | #endif 33 | #if defined(PINMUX_PA08H_CAN0_RX) && !defined(IGNORE_PIN_PA08) 34 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 0, PINMUX_PA08H_CAN0_RX & 0xf}, 35 | #endif 36 | #if defined(PINMUX_PA09H_CAN0_RX) && !defined(IGNORE_PIN_PA09) 37 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 0, PINMUX_PA09H_CAN0_RX & 0xf}, 38 | #endif 39 | #if defined(PINMUX_PA10H_CAN0_RX) && !defined(IGNORE_PIN_PA10) 40 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 0, PINMUX_PA10H_CAN0_RX & 0xf}, 41 | #endif 42 | #if defined(PINMUX_PA11H_CAN0_RX) && !defined(IGNORE_PIN_PA11) 43 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 0, PINMUX_PA11H_CAN0_RX & 0xf}, 44 | #endif 45 | #if defined(PINMUX_PA12H_CAN0_RX) && !defined(IGNORE_PIN_PA12) 46 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 0, PINMUX_PA12H_CAN0_RX & 0xf}, 47 | #endif 48 | #if defined(PINMUX_PA13H_CAN0_RX) && !defined(IGNORE_PIN_PA13) 49 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 0, PINMUX_PA13H_CAN0_RX & 0xf}, 50 | #endif 51 | #if defined(PINMUX_PA14H_CAN0_RX) && !defined(IGNORE_PIN_PA14) 52 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 0, PINMUX_PA14H_CAN0_RX & 0xf}, 53 | #endif 54 | #if defined(PINMUX_PA15H_CAN0_RX) && !defined(IGNORE_PIN_PA15) 55 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 0, PINMUX_PA15H_CAN0_RX & 0xf}, 56 | #endif 57 | #if defined(PINMUX_PA16H_CAN0_RX) && !defined(IGNORE_PIN_PA16) 58 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 0, PINMUX_PA16H_CAN0_RX & 0xf}, 59 | #endif 60 | #if defined(PINMUX_PA17H_CAN0_RX) && !defined(IGNORE_PIN_PA17) 61 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 0, PINMUX_PA17H_CAN0_RX & 0xf}, 62 | #endif 63 | #if defined(PINMUX_PA18H_CAN0_RX) && !defined(IGNORE_PIN_PA18) 64 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 0, PINMUX_PA18H_CAN0_RX & 0xf}, 65 | #endif 66 | #if defined(PINMUX_PA19H_CAN0_RX) && !defined(IGNORE_PIN_PA19) 67 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 0, PINMUX_PA19H_CAN0_RX & 0xf}, 68 | #endif 69 | #if defined(PINMUX_PA20H_CAN0_RX) && !defined(IGNORE_PIN_PA20) 70 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 0, PINMUX_PA20H_CAN0_RX & 0xf}, 71 | #endif 72 | #if defined(PINMUX_PA21H_CAN0_RX) && !defined(IGNORE_PIN_PA21) 73 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 0, PINMUX_PA21H_CAN0_RX & 0xf}, 74 | #endif 75 | #if defined(PINMUX_PA22H_CAN0_RX) && !defined(IGNORE_PIN_PA22) 76 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 0, PINMUX_PA22H_CAN0_RX & 0xf}, 77 | #endif 78 | #if defined(PINMUX_PA23H_CAN0_RX) && !defined(IGNORE_PIN_PA23) 79 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 0, PINMUX_PA23H_CAN0_RX & 0xf}, 80 | #endif 81 | #if defined(PINMUX_PA24H_CAN0_RX) && !defined(IGNORE_PIN_PA24) 82 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 0, PINMUX_PA24H_CAN0_RX & 0xf}, 83 | #endif 84 | #if defined(PINMUX_PA25H_CAN0_RX) && !defined(IGNORE_PIN_PA25) 85 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 0, PINMUX_PA25H_CAN0_RX & 0xf}, 86 | #endif 87 | #if defined(PINMUX_PA26H_CAN0_RX) && !defined(IGNORE_PIN_PA26) 88 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 0, PINMUX_PA26H_CAN0_RX & 0xf}, 89 | #endif 90 | #if defined(PINMUX_PA27H_CAN0_RX) && !defined(IGNORE_PIN_PA27) 91 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 0, PINMUX_PA27H_CAN0_RX & 0xf}, 92 | #endif 93 | #if defined(PINMUX_PA28H_CAN0_RX) && !defined(IGNORE_PIN_PA28) 94 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 0, PINMUX_PA28H_CAN0_RX & 0xf}, 95 | #endif 96 | #if defined(PINMUX_PA29H_CAN0_RX) && !defined(IGNORE_PIN_PA29) 97 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 0, PINMUX_PA29H_CAN0_RX & 0xf}, 98 | #endif 99 | #if defined(PINMUX_PA30H_CAN0_RX) && !defined(IGNORE_PIN_PA30) 100 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 0, PINMUX_PA30H_CAN0_RX & 0xf}, 101 | #endif 102 | #if defined(PINMUX_PA31H_CAN0_RX) && !defined(IGNORE_PIN_PA31) 103 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 0, PINMUX_PA31H_CAN0_RX & 0xf}, 104 | #endif 105 | #if defined(PINMUX_PB00H_CAN0_RX) && !defined(IGNORE_PIN_PB00) 106 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 0, PINMUX_PB00H_CAN0_RX & 0xf}, 107 | #endif 108 | #if defined(PINMUX_PB01H_CAN0_RX) && !defined(IGNORE_PIN_PB01) 109 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 0, PINMUX_PB01H_CAN0_RX & 0xf}, 110 | #endif 111 | #if defined(PINMUX_PB02H_CAN0_RX) && !defined(IGNORE_PIN_PB02) 112 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 0, PINMUX_PB02H_CAN0_RX & 0xf}, 113 | #endif 114 | #if defined(PINMUX_PB03H_CAN0_RX) && !defined(IGNORE_PIN_PB03) 115 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 0, PINMUX_PB03H_CAN0_RX & 0xf}, 116 | #endif 117 | #if defined(PINMUX_PB04H_CAN0_RX) && !defined(IGNORE_PIN_PB04) 118 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 0, PINMUX_PB04H_CAN0_RX & 0xf}, 119 | #endif 120 | #if defined(PINMUX_PB05H_CAN0_RX) && !defined(IGNORE_PIN_PB05) 121 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 0, PINMUX_PB05H_CAN0_RX & 0xf}, 122 | #endif 123 | #if defined(PINMUX_PB06H_CAN0_RX) && !defined(IGNORE_PIN_PB06) 124 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 0, PINMUX_PB06H_CAN0_RX & 0xf}, 125 | #endif 126 | #if defined(PINMUX_PB07H_CAN0_RX) && !defined(IGNORE_PIN_PB07) 127 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 0, PINMUX_PB07H_CAN0_RX & 0xf}, 128 | #endif 129 | #if defined(PINMUX_PB08H_CAN0_RX) && !defined(IGNORE_PIN_PB08) 130 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 0, PINMUX_PB08H_CAN0_RX & 0xf}, 131 | #endif 132 | #if defined(PINMUX_PB09H_CAN0_RX) && !defined(IGNORE_PIN_PB09) 133 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 0, PINMUX_PB09H_CAN0_RX & 0xf}, 134 | #endif 135 | #if defined(PINMUX_PB10H_CAN0_RX) && !defined(IGNORE_PIN_PB10) 136 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 0, PINMUX_PB10H_CAN0_RX & 0xf}, 137 | #endif 138 | #if defined(PINMUX_PB11H_CAN0_RX) && !defined(IGNORE_PIN_PB11) 139 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 0, PINMUX_PB11H_CAN0_RX & 0xf}, 140 | #endif 141 | #if defined(PINMUX_PB12H_CAN0_RX) && !defined(IGNORE_PIN_PB12) 142 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 0, PINMUX_PB12H_CAN0_RX & 0xf}, 143 | #endif 144 | #if defined(PINMUX_PB13H_CAN0_RX) && !defined(IGNORE_PIN_PB13) 145 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 0, PINMUX_PB13H_CAN0_RX & 0xf}, 146 | #endif 147 | #if defined(PINMUX_PB14H_CAN0_RX) && !defined(IGNORE_PIN_PB14) 148 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 0, PINMUX_PB14H_CAN0_RX & 0xf}, 149 | #endif 150 | #if defined(PINMUX_PB15H_CAN0_RX) && !defined(IGNORE_PIN_PB15) 151 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 0, PINMUX_PB15H_CAN0_RX & 0xf}, 152 | #endif 153 | #if defined(PINMUX_PB16H_CAN0_RX) && !defined(IGNORE_PIN_PB16) 154 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 0, PINMUX_PB16H_CAN0_RX & 0xf}, 155 | #endif 156 | #if defined(PINMUX_PB17H_CAN0_RX) && !defined(IGNORE_PIN_PB17) 157 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 0, PINMUX_PB17H_CAN0_RX & 0xf}, 158 | #endif 159 | #if defined(PINMUX_PB18H_CAN0_RX) && !defined(IGNORE_PIN_PB18) 160 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 0, PINMUX_PB18H_CAN0_RX & 0xf}, 161 | #endif 162 | #if defined(PINMUX_PB19H_CAN0_RX) && !defined(IGNORE_PIN_PB19) 163 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 0, PINMUX_PB19H_CAN0_RX & 0xf}, 164 | #endif 165 | #if defined(PINMUX_PB20H_CAN0_RX) && !defined(IGNORE_PIN_PB20) 166 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 0, PINMUX_PB20H_CAN0_RX & 0xf}, 167 | #endif 168 | #if defined(PINMUX_PB21H_CAN0_RX) && !defined(IGNORE_PIN_PB21) 169 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 0, PINMUX_PB21H_CAN0_RX & 0xf}, 170 | #endif 171 | #if defined(PINMUX_PB22H_CAN0_RX) && !defined(IGNORE_PIN_PB22) 172 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 0, PINMUX_PB22H_CAN0_RX & 0xf}, 173 | #endif 174 | #if defined(PINMUX_PB23H_CAN0_RX) && !defined(IGNORE_PIN_PB23) 175 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 0, PINMUX_PB23H_CAN0_RX & 0xf}, 176 | #endif 177 | #if defined(PINMUX_PB24H_CAN0_RX) && !defined(IGNORE_PIN_PB24) 178 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 0, PINMUX_PB24H_CAN0_RX & 0xf}, 179 | #endif 180 | #if defined(PINMUX_PB25H_CAN0_RX) && !defined(IGNORE_PIN_PB25) 181 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 0, PINMUX_PB25H_CAN0_RX & 0xf}, 182 | #endif 183 | #if defined(PINMUX_PB26H_CAN0_RX) && !defined(IGNORE_PIN_PB26) 184 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 0, PINMUX_PB26H_CAN0_RX & 0xf}, 185 | #endif 186 | #if defined(PINMUX_PB27H_CAN0_RX) && !defined(IGNORE_PIN_PB27) 187 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 0, PINMUX_PB27H_CAN0_RX & 0xf}, 188 | #endif 189 | #if defined(PINMUX_PB28H_CAN0_RX) && !defined(IGNORE_PIN_PB28) 190 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 0, PINMUX_PB28H_CAN0_RX & 0xf}, 191 | #endif 192 | #if defined(PINMUX_PB29H_CAN0_RX) && !defined(IGNORE_PIN_PB29) 193 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 0, PINMUX_PB29H_CAN0_RX & 0xf}, 194 | #endif 195 | #if defined(PINMUX_PB30H_CAN0_RX) && !defined(IGNORE_PIN_PB30) 196 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 0, PINMUX_PB30H_CAN0_RX & 0xf}, 197 | #endif 198 | #if defined(PINMUX_PB31H_CAN0_RX) && !defined(IGNORE_PIN_PB31) 199 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 0, PINMUX_PB31H_CAN0_RX & 0xf}, 200 | #endif 201 | #if defined(PINMUX_PC00H_CAN0_RX) && !defined(IGNORE_PIN_PC00) 202 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 0, PINMUX_PC00H_CAN0_RX & 0xf}, 203 | #endif 204 | #if defined(PINMUX_PC01H_CAN0_RX) && !defined(IGNORE_PIN_PC01) 205 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 0, PINMUX_PC01H_CAN0_RX & 0xf}, 206 | #endif 207 | #if defined(PINMUX_PC02H_CAN0_RX) && !defined(IGNORE_PIN_PC02) 208 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 0, PINMUX_PC02H_CAN0_RX & 0xf}, 209 | #endif 210 | #if defined(PINMUX_PC03H_CAN0_RX) && !defined(IGNORE_PIN_PC03) 211 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 0, PINMUX_PC03H_CAN0_RX & 0xf}, 212 | #endif 213 | #if defined(PINMUX_PC04H_CAN0_RX) && !defined(IGNORE_PIN_PC04) 214 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 0, PINMUX_PC04H_CAN0_RX & 0xf}, 215 | #endif 216 | #if defined(PINMUX_PC05H_CAN0_RX) && !defined(IGNORE_PIN_PC05) 217 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 0, PINMUX_PC05H_CAN0_RX & 0xf}, 218 | #endif 219 | #if defined(PINMUX_PC06H_CAN0_RX) && !defined(IGNORE_PIN_PC06) 220 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 0, PINMUX_PC06H_CAN0_RX & 0xf}, 221 | #endif 222 | #if defined(PINMUX_PC07H_CAN0_RX) && !defined(IGNORE_PIN_PC07) 223 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 0, PINMUX_PC07H_CAN0_RX & 0xf}, 224 | #endif 225 | #if defined(PINMUX_PC08H_CAN0_RX) && !defined(IGNORE_PIN_PC08) 226 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 0, PINMUX_PC08H_CAN0_RX & 0xf}, 227 | #endif 228 | #if defined(PINMUX_PC09H_CAN0_RX) && !defined(IGNORE_PIN_PC09) 229 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 0, PINMUX_PC09H_CAN0_RX & 0xf}, 230 | #endif 231 | #if defined(PINMUX_PC10H_CAN0_RX) && !defined(IGNORE_PIN_PC10) 232 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 0, PINMUX_PC10H_CAN0_RX & 0xf}, 233 | #endif 234 | #if defined(PINMUX_PC11H_CAN0_RX) && !defined(IGNORE_PIN_PC11) 235 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 0, PINMUX_PC11H_CAN0_RX & 0xf}, 236 | #endif 237 | #if defined(PINMUX_PC12H_CAN0_RX) && !defined(IGNORE_PIN_PC12) 238 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 0, PINMUX_PC12H_CAN0_RX & 0xf}, 239 | #endif 240 | #if defined(PINMUX_PC13H_CAN0_RX) && !defined(IGNORE_PIN_PC13) 241 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 0, PINMUX_PC13H_CAN0_RX & 0xf}, 242 | #endif 243 | #if defined(PINMUX_PC14H_CAN0_RX) && !defined(IGNORE_PIN_PC14) 244 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 0, PINMUX_PC14H_CAN0_RX & 0xf}, 245 | #endif 246 | #if defined(PINMUX_PC15H_CAN0_RX) && !defined(IGNORE_PIN_PC15) 247 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 0, PINMUX_PC15H_CAN0_RX & 0xf}, 248 | #endif 249 | #if defined(PINMUX_PC16H_CAN0_RX) && !defined(IGNORE_PIN_PC16) 250 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 0, PINMUX_PC16H_CAN0_RX & 0xf}, 251 | #endif 252 | #if defined(PINMUX_PC17H_CAN0_RX) && !defined(IGNORE_PIN_PC17) 253 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 0, PINMUX_PC17H_CAN0_RX & 0xf}, 254 | #endif 255 | #if defined(PINMUX_PC18H_CAN0_RX) && !defined(IGNORE_PIN_PC18) 256 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 0, PINMUX_PC18H_CAN0_RX & 0xf}, 257 | #endif 258 | #if defined(PINMUX_PC19H_CAN0_RX) && !defined(IGNORE_PIN_PC19) 259 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 0, PINMUX_PC19H_CAN0_RX & 0xf}, 260 | #endif 261 | #if defined(PINMUX_PC20H_CAN0_RX) && !defined(IGNORE_PIN_PC20) 262 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 0, PINMUX_PC20H_CAN0_RX & 0xf}, 263 | #endif 264 | #if defined(PINMUX_PC21H_CAN0_RX) && !defined(IGNORE_PIN_PC21) 265 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 0, PINMUX_PC21H_CAN0_RX & 0xf}, 266 | #endif 267 | #if defined(PINMUX_PC22H_CAN0_RX) && !defined(IGNORE_PIN_PC22) 268 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 0, PINMUX_PC22H_CAN0_RX & 0xf}, 269 | #endif 270 | #if defined(PINMUX_PC23H_CAN0_RX) && !defined(IGNORE_PIN_PC23) 271 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 0, PINMUX_PC23H_CAN0_RX & 0xf}, 272 | #endif 273 | #if defined(PINMUX_PC24H_CAN0_RX) && !defined(IGNORE_PIN_PC24) 274 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 0, PINMUX_PC24H_CAN0_RX & 0xf}, 275 | #endif 276 | #if defined(PINMUX_PC25H_CAN0_RX) && !defined(IGNORE_PIN_PC25) 277 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 0, PINMUX_PC25H_CAN0_RX & 0xf}, 278 | #endif 279 | #if defined(PINMUX_PC26H_CAN0_RX) && !defined(IGNORE_PIN_PC26) 280 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 0, PINMUX_PC26H_CAN0_RX & 0xf}, 281 | #endif 282 | #if defined(PINMUX_PC27H_CAN0_RX) && !defined(IGNORE_PIN_PC27) 283 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 0, PINMUX_PC27H_CAN0_RX & 0xf}, 284 | #endif 285 | #if defined(PINMUX_PC28H_CAN0_RX) && !defined(IGNORE_PIN_PC28) 286 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 0, PINMUX_PC28H_CAN0_RX & 0xf}, 287 | #endif 288 | #if defined(PINMUX_PC29H_CAN0_RX) && !defined(IGNORE_PIN_PC29) 289 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 0, PINMUX_PC29H_CAN0_RX & 0xf}, 290 | #endif 291 | #if defined(PINMUX_PC30H_CAN0_RX) && !defined(IGNORE_PIN_PC30) 292 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 0, PINMUX_PC30H_CAN0_RX & 0xf}, 293 | #endif 294 | #if defined(PINMUX_PC31H_CAN0_RX) && !defined(IGNORE_PIN_PC31) 295 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 0, PINMUX_PC31H_CAN0_RX & 0xf}, 296 | #endif 297 | #if defined(PINMUX_PD00H_CAN0_RX) && !defined(IGNORE_PIN_PD00) 298 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 0, PINMUX_PD00H_CAN0_RX & 0xf}, 299 | #endif 300 | #if defined(PINMUX_PD01H_CAN0_RX) && !defined(IGNORE_PIN_PD01) 301 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 0, PINMUX_PD01H_CAN0_RX & 0xf}, 302 | #endif 303 | #if defined(PINMUX_PD02H_CAN0_RX) && !defined(IGNORE_PIN_PD02) 304 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 0, PINMUX_PD02H_CAN0_RX & 0xf}, 305 | #endif 306 | #if defined(PINMUX_PD03H_CAN0_RX) && !defined(IGNORE_PIN_PD03) 307 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 0, PINMUX_PD03H_CAN0_RX & 0xf}, 308 | #endif 309 | #if defined(PINMUX_PD04H_CAN0_RX) && !defined(IGNORE_PIN_PD04) 310 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 0, PINMUX_PD04H_CAN0_RX & 0xf}, 311 | #endif 312 | #if defined(PINMUX_PD05H_CAN0_RX) && !defined(IGNORE_PIN_PD05) 313 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 0, PINMUX_PD05H_CAN0_RX & 0xf}, 314 | #endif 315 | #if defined(PINMUX_PD06H_CAN0_RX) && !defined(IGNORE_PIN_PD06) 316 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 0, PINMUX_PD06H_CAN0_RX & 0xf}, 317 | #endif 318 | #if defined(PINMUX_PD07H_CAN0_RX) && !defined(IGNORE_PIN_PD07) 319 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 0, PINMUX_PD07H_CAN0_RX & 0xf}, 320 | #endif 321 | #if defined(PINMUX_PD08H_CAN0_RX) && !defined(IGNORE_PIN_PD08) 322 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 0, PINMUX_PD08H_CAN0_RX & 0xf}, 323 | #endif 324 | #if defined(PINMUX_PD09H_CAN0_RX) && !defined(IGNORE_PIN_PD09) 325 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 0, PINMUX_PD09H_CAN0_RX & 0xf}, 326 | #endif 327 | #if defined(PINMUX_PD10H_CAN0_RX) && !defined(IGNORE_PIN_PD10) 328 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 0, PINMUX_PD10H_CAN0_RX & 0xf}, 329 | #endif 330 | #if defined(PINMUX_PD11H_CAN0_RX) && !defined(IGNORE_PIN_PD11) 331 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 0, PINMUX_PD11H_CAN0_RX & 0xf}, 332 | #endif 333 | #if defined(PINMUX_PD12H_CAN0_RX) && !defined(IGNORE_PIN_PD12) 334 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 0, PINMUX_PD12H_CAN0_RX & 0xf}, 335 | #endif 336 | #if defined(PINMUX_PD13H_CAN0_RX) && !defined(IGNORE_PIN_PD13) 337 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 0, PINMUX_PD13H_CAN0_RX & 0xf}, 338 | #endif 339 | #if defined(PINMUX_PD14H_CAN0_RX) && !defined(IGNORE_PIN_PD14) 340 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 0, PINMUX_PD14H_CAN0_RX & 0xf}, 341 | #endif 342 | #if defined(PINMUX_PD15H_CAN0_RX) && !defined(IGNORE_PIN_PD15) 343 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 0, PINMUX_PD15H_CAN0_RX & 0xf}, 344 | #endif 345 | #if defined(PINMUX_PD16H_CAN0_RX) && !defined(IGNORE_PIN_PD16) 346 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 0, PINMUX_PD16H_CAN0_RX & 0xf}, 347 | #endif 348 | #if defined(PINMUX_PD17H_CAN0_RX) && !defined(IGNORE_PIN_PD17) 349 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 0, PINMUX_PD17H_CAN0_RX & 0xf}, 350 | #endif 351 | #if defined(PINMUX_PD18H_CAN0_RX) && !defined(IGNORE_PIN_PD18) 352 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 0, PINMUX_PD18H_CAN0_RX & 0xf}, 353 | #endif 354 | #if defined(PINMUX_PD19H_CAN0_RX) && !defined(IGNORE_PIN_PD19) 355 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 0, PINMUX_PD19H_CAN0_RX & 0xf}, 356 | #endif 357 | #if defined(PINMUX_PD20H_CAN0_RX) && !defined(IGNORE_PIN_PD20) 358 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 0, PINMUX_PD20H_CAN0_RX & 0xf}, 359 | #endif 360 | #if defined(PINMUX_PD21H_CAN0_RX) && !defined(IGNORE_PIN_PD21) 361 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 0, PINMUX_PD21H_CAN0_RX & 0xf}, 362 | #endif 363 | #if defined(PINMUX_PD22H_CAN0_RX) && !defined(IGNORE_PIN_PD22) 364 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 0, PINMUX_PD22H_CAN0_RX & 0xf}, 365 | #endif 366 | #if defined(PINMUX_PD23H_CAN0_RX) && !defined(IGNORE_PIN_PD23) 367 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 0, PINMUX_PD23H_CAN0_RX & 0xf}, 368 | #endif 369 | #if defined(PINMUX_PD24H_CAN0_RX) && !defined(IGNORE_PIN_PD24) 370 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 0, PINMUX_PD24H_CAN0_RX & 0xf}, 371 | #endif 372 | #if defined(PINMUX_PD25H_CAN0_RX) && !defined(IGNORE_PIN_PD25) 373 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 0, PINMUX_PD25H_CAN0_RX & 0xf}, 374 | #endif 375 | #if defined(PINMUX_PD26H_CAN0_RX) && !defined(IGNORE_PIN_PD26) 376 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 0, PINMUX_PD26H_CAN0_RX & 0xf}, 377 | #endif 378 | #if defined(PINMUX_PD27H_CAN0_RX) && !defined(IGNORE_PIN_PD27) 379 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 0, PINMUX_PD27H_CAN0_RX & 0xf}, 380 | #endif 381 | #if defined(PINMUX_PD28H_CAN0_RX) && !defined(IGNORE_PIN_PD28) 382 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 0, PINMUX_PD28H_CAN0_RX & 0xf}, 383 | #endif 384 | #if defined(PINMUX_PD29H_CAN0_RX) && !defined(IGNORE_PIN_PD29) 385 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 0, PINMUX_PD29H_CAN0_RX & 0xf}, 386 | #endif 387 | #if defined(PINMUX_PD30H_CAN0_RX) && !defined(IGNORE_PIN_PD30) 388 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 0, PINMUX_PD30H_CAN0_RX & 0xf}, 389 | #endif 390 | #if defined(PINMUX_PD31H_CAN0_RX) && !defined(IGNORE_PIN_PD31) 391 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 0, PINMUX_PD31H_CAN0_RX & 0xf}, 392 | #endif 393 | #if defined(PINMUX_PA00I_CAN0_RX) && !defined(IGNORE_PIN_PA00) 394 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 0, PINMUX_PA00I_CAN0_RX & 0xf}, 395 | #endif 396 | #if defined(PINMUX_PA01I_CAN0_RX) && !defined(IGNORE_PIN_PA01) 397 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 0, PINMUX_PA01I_CAN0_RX & 0xf}, 398 | #endif 399 | #if defined(PINMUX_PA02I_CAN0_RX) && !defined(IGNORE_PIN_PA02) 400 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 0, PINMUX_PA02I_CAN0_RX & 0xf}, 401 | #endif 402 | #if defined(PINMUX_PA03I_CAN0_RX) && !defined(IGNORE_PIN_PA03) 403 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 0, PINMUX_PA03I_CAN0_RX & 0xf}, 404 | #endif 405 | #if defined(PINMUX_PA04I_CAN0_RX) && !defined(IGNORE_PIN_PA04) 406 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 0, PINMUX_PA04I_CAN0_RX & 0xf}, 407 | #endif 408 | #if defined(PINMUX_PA05I_CAN0_RX) && !defined(IGNORE_PIN_PA05) 409 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 0, PINMUX_PA05I_CAN0_RX & 0xf}, 410 | #endif 411 | #if defined(PINMUX_PA06I_CAN0_RX) && !defined(IGNORE_PIN_PA06) 412 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 0, PINMUX_PA06I_CAN0_RX & 0xf}, 413 | #endif 414 | #if defined(PINMUX_PA07I_CAN0_RX) && !defined(IGNORE_PIN_PA07) 415 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 0, PINMUX_PA07I_CAN0_RX & 0xf}, 416 | #endif 417 | #if defined(PINMUX_PA08I_CAN0_RX) && !defined(IGNORE_PIN_PA08) 418 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 0, PINMUX_PA08I_CAN0_RX & 0xf}, 419 | #endif 420 | #if defined(PINMUX_PA09I_CAN0_RX) && !defined(IGNORE_PIN_PA09) 421 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 0, PINMUX_PA09I_CAN0_RX & 0xf}, 422 | #endif 423 | #if defined(PINMUX_PA10I_CAN0_RX) && !defined(IGNORE_PIN_PA10) 424 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 0, PINMUX_PA10I_CAN0_RX & 0xf}, 425 | #endif 426 | #if defined(PINMUX_PA11I_CAN0_RX) && !defined(IGNORE_PIN_PA11) 427 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 0, PINMUX_PA11I_CAN0_RX & 0xf}, 428 | #endif 429 | #if defined(PINMUX_PA12I_CAN0_RX) && !defined(IGNORE_PIN_PA12) 430 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 0, PINMUX_PA12I_CAN0_RX & 0xf}, 431 | #endif 432 | #if defined(PINMUX_PA13I_CAN0_RX) && !defined(IGNORE_PIN_PA13) 433 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 0, PINMUX_PA13I_CAN0_RX & 0xf}, 434 | #endif 435 | #if defined(PINMUX_PA14I_CAN0_RX) && !defined(IGNORE_PIN_PA14) 436 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 0, PINMUX_PA14I_CAN0_RX & 0xf}, 437 | #endif 438 | #if defined(PINMUX_PA15I_CAN0_RX) && !defined(IGNORE_PIN_PA15) 439 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 0, PINMUX_PA15I_CAN0_RX & 0xf}, 440 | #endif 441 | #if defined(PINMUX_PA16I_CAN0_RX) && !defined(IGNORE_PIN_PA16) 442 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 0, PINMUX_PA16I_CAN0_RX & 0xf}, 443 | #endif 444 | #if defined(PINMUX_PA17I_CAN0_RX) && !defined(IGNORE_PIN_PA17) 445 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 0, PINMUX_PA17I_CAN0_RX & 0xf}, 446 | #endif 447 | #if defined(PINMUX_PA18I_CAN0_RX) && !defined(IGNORE_PIN_PA18) 448 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 0, PINMUX_PA18I_CAN0_RX & 0xf}, 449 | #endif 450 | #if defined(PINMUX_PA19I_CAN0_RX) && !defined(IGNORE_PIN_PA19) 451 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 0, PINMUX_PA19I_CAN0_RX & 0xf}, 452 | #endif 453 | #if defined(PINMUX_PA20I_CAN0_RX) && !defined(IGNORE_PIN_PA20) 454 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 0, PINMUX_PA20I_CAN0_RX & 0xf}, 455 | #endif 456 | #if defined(PINMUX_PA21I_CAN0_RX) && !defined(IGNORE_PIN_PA21) 457 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 0, PINMUX_PA21I_CAN0_RX & 0xf}, 458 | #endif 459 | #if defined(PINMUX_PA22I_CAN0_RX) && !defined(IGNORE_PIN_PA22) 460 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 0, PINMUX_PA22I_CAN0_RX & 0xf}, 461 | #endif 462 | #if defined(PINMUX_PA23I_CAN0_RX) && !defined(IGNORE_PIN_PA23) 463 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 0, PINMUX_PA23I_CAN0_RX & 0xf}, 464 | #endif 465 | #if defined(PINMUX_PA24I_CAN0_RX) && !defined(IGNORE_PIN_PA24) 466 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 0, PINMUX_PA24I_CAN0_RX & 0xf}, 467 | #endif 468 | #if defined(PINMUX_PA25I_CAN0_RX) && !defined(IGNORE_PIN_PA25) 469 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 0, PINMUX_PA25I_CAN0_RX & 0xf}, 470 | #endif 471 | #if defined(PINMUX_PA26I_CAN0_RX) && !defined(IGNORE_PIN_PA26) 472 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 0, PINMUX_PA26I_CAN0_RX & 0xf}, 473 | #endif 474 | #if defined(PINMUX_PA27I_CAN0_RX) && !defined(IGNORE_PIN_PA27) 475 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 0, PINMUX_PA27I_CAN0_RX & 0xf}, 476 | #endif 477 | #if defined(PINMUX_PA28I_CAN0_RX) && !defined(IGNORE_PIN_PA28) 478 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 0, PINMUX_PA28I_CAN0_RX & 0xf}, 479 | #endif 480 | #if defined(PINMUX_PA29I_CAN0_RX) && !defined(IGNORE_PIN_PA29) 481 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 0, PINMUX_PA29I_CAN0_RX & 0xf}, 482 | #endif 483 | #if defined(PINMUX_PA30I_CAN0_RX) && !defined(IGNORE_PIN_PA30) 484 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 0, PINMUX_PA30I_CAN0_RX & 0xf}, 485 | #endif 486 | #if defined(PINMUX_PA31I_CAN0_RX) && !defined(IGNORE_PIN_PA31) 487 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 0, PINMUX_PA31I_CAN0_RX & 0xf}, 488 | #endif 489 | #if defined(PINMUX_PB00I_CAN0_RX) && !defined(IGNORE_PIN_PB00) 490 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 0, PINMUX_PB00I_CAN0_RX & 0xf}, 491 | #endif 492 | #if defined(PINMUX_PB01I_CAN0_RX) && !defined(IGNORE_PIN_PB01) 493 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 0, PINMUX_PB01I_CAN0_RX & 0xf}, 494 | #endif 495 | #if defined(PINMUX_PB02I_CAN0_RX) && !defined(IGNORE_PIN_PB02) 496 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 0, PINMUX_PB02I_CAN0_RX & 0xf}, 497 | #endif 498 | #if defined(PINMUX_PB03I_CAN0_RX) && !defined(IGNORE_PIN_PB03) 499 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 0, PINMUX_PB03I_CAN0_RX & 0xf}, 500 | #endif 501 | #if defined(PINMUX_PB04I_CAN0_RX) && !defined(IGNORE_PIN_PB04) 502 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 0, PINMUX_PB04I_CAN0_RX & 0xf}, 503 | #endif 504 | #if defined(PINMUX_PB05I_CAN0_RX) && !defined(IGNORE_PIN_PB05) 505 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 0, PINMUX_PB05I_CAN0_RX & 0xf}, 506 | #endif 507 | #if defined(PINMUX_PB06I_CAN0_RX) && !defined(IGNORE_PIN_PB06) 508 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 0, PINMUX_PB06I_CAN0_RX & 0xf}, 509 | #endif 510 | #if defined(PINMUX_PB07I_CAN0_RX) && !defined(IGNORE_PIN_PB07) 511 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 0, PINMUX_PB07I_CAN0_RX & 0xf}, 512 | #endif 513 | #if defined(PINMUX_PB08I_CAN0_RX) && !defined(IGNORE_PIN_PB08) 514 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 0, PINMUX_PB08I_CAN0_RX & 0xf}, 515 | #endif 516 | #if defined(PINMUX_PB09I_CAN0_RX) && !defined(IGNORE_PIN_PB09) 517 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 0, PINMUX_PB09I_CAN0_RX & 0xf}, 518 | #endif 519 | #if defined(PINMUX_PB10I_CAN0_RX) && !defined(IGNORE_PIN_PB10) 520 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 0, PINMUX_PB10I_CAN0_RX & 0xf}, 521 | #endif 522 | #if defined(PINMUX_PB11I_CAN0_RX) && !defined(IGNORE_PIN_PB11) 523 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 0, PINMUX_PB11I_CAN0_RX & 0xf}, 524 | #endif 525 | #if defined(PINMUX_PB12I_CAN0_RX) && !defined(IGNORE_PIN_PB12) 526 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 0, PINMUX_PB12I_CAN0_RX & 0xf}, 527 | #endif 528 | #if defined(PINMUX_PB13I_CAN0_RX) && !defined(IGNORE_PIN_PB13) 529 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 0, PINMUX_PB13I_CAN0_RX & 0xf}, 530 | #endif 531 | #if defined(PINMUX_PB14I_CAN0_RX) && !defined(IGNORE_PIN_PB14) 532 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 0, PINMUX_PB14I_CAN0_RX & 0xf}, 533 | #endif 534 | #if defined(PINMUX_PB15I_CAN0_RX) && !defined(IGNORE_PIN_PB15) 535 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 0, PINMUX_PB15I_CAN0_RX & 0xf}, 536 | #endif 537 | #if defined(PINMUX_PB16I_CAN0_RX) && !defined(IGNORE_PIN_PB16) 538 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 0, PINMUX_PB16I_CAN0_RX & 0xf}, 539 | #endif 540 | #if defined(PINMUX_PB17I_CAN0_RX) && !defined(IGNORE_PIN_PB17) 541 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 0, PINMUX_PB17I_CAN0_RX & 0xf}, 542 | #endif 543 | #if defined(PINMUX_PB18I_CAN0_RX) && !defined(IGNORE_PIN_PB18) 544 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 0, PINMUX_PB18I_CAN0_RX & 0xf}, 545 | #endif 546 | #if defined(PINMUX_PB19I_CAN0_RX) && !defined(IGNORE_PIN_PB19) 547 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 0, PINMUX_PB19I_CAN0_RX & 0xf}, 548 | #endif 549 | #if defined(PINMUX_PB20I_CAN0_RX) && !defined(IGNORE_PIN_PB20) 550 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 0, PINMUX_PB20I_CAN0_RX & 0xf}, 551 | #endif 552 | #if defined(PINMUX_PB21I_CAN0_RX) && !defined(IGNORE_PIN_PB21) 553 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 0, PINMUX_PB21I_CAN0_RX & 0xf}, 554 | #endif 555 | #if defined(PINMUX_PB22I_CAN0_RX) && !defined(IGNORE_PIN_PB22) 556 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 0, PINMUX_PB22I_CAN0_RX & 0xf}, 557 | #endif 558 | #if defined(PINMUX_PB23I_CAN0_RX) && !defined(IGNORE_PIN_PB23) 559 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 0, PINMUX_PB23I_CAN0_RX & 0xf}, 560 | #endif 561 | #if defined(PINMUX_PB24I_CAN0_RX) && !defined(IGNORE_PIN_PB24) 562 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 0, PINMUX_PB24I_CAN0_RX & 0xf}, 563 | #endif 564 | #if defined(PINMUX_PB25I_CAN0_RX) && !defined(IGNORE_PIN_PB25) 565 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 0, PINMUX_PB25I_CAN0_RX & 0xf}, 566 | #endif 567 | #if defined(PINMUX_PB26I_CAN0_RX) && !defined(IGNORE_PIN_PB26) 568 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 0, PINMUX_PB26I_CAN0_RX & 0xf}, 569 | #endif 570 | #if defined(PINMUX_PB27I_CAN0_RX) && !defined(IGNORE_PIN_PB27) 571 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 0, PINMUX_PB27I_CAN0_RX & 0xf}, 572 | #endif 573 | #if defined(PINMUX_PB28I_CAN0_RX) && !defined(IGNORE_PIN_PB28) 574 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 0, PINMUX_PB28I_CAN0_RX & 0xf}, 575 | #endif 576 | #if defined(PINMUX_PB29I_CAN0_RX) && !defined(IGNORE_PIN_PB29) 577 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 0, PINMUX_PB29I_CAN0_RX & 0xf}, 578 | #endif 579 | #if defined(PINMUX_PB30I_CAN0_RX) && !defined(IGNORE_PIN_PB30) 580 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 0, PINMUX_PB30I_CAN0_RX & 0xf}, 581 | #endif 582 | #if defined(PINMUX_PB31I_CAN0_RX) && !defined(IGNORE_PIN_PB31) 583 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 0, PINMUX_PB31I_CAN0_RX & 0xf}, 584 | #endif 585 | #if defined(PINMUX_PC00I_CAN0_RX) && !defined(IGNORE_PIN_PC00) 586 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 0, PINMUX_PC00I_CAN0_RX & 0xf}, 587 | #endif 588 | #if defined(PINMUX_PC01I_CAN0_RX) && !defined(IGNORE_PIN_PC01) 589 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 0, PINMUX_PC01I_CAN0_RX & 0xf}, 590 | #endif 591 | #if defined(PINMUX_PC02I_CAN0_RX) && !defined(IGNORE_PIN_PC02) 592 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 0, PINMUX_PC02I_CAN0_RX & 0xf}, 593 | #endif 594 | #if defined(PINMUX_PC03I_CAN0_RX) && !defined(IGNORE_PIN_PC03) 595 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 0, PINMUX_PC03I_CAN0_RX & 0xf}, 596 | #endif 597 | #if defined(PINMUX_PC04I_CAN0_RX) && !defined(IGNORE_PIN_PC04) 598 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 0, PINMUX_PC04I_CAN0_RX & 0xf}, 599 | #endif 600 | #if defined(PINMUX_PC05I_CAN0_RX) && !defined(IGNORE_PIN_PC05) 601 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 0, PINMUX_PC05I_CAN0_RX & 0xf}, 602 | #endif 603 | #if defined(PINMUX_PC06I_CAN0_RX) && !defined(IGNORE_PIN_PC06) 604 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 0, PINMUX_PC06I_CAN0_RX & 0xf}, 605 | #endif 606 | #if defined(PINMUX_PC07I_CAN0_RX) && !defined(IGNORE_PIN_PC07) 607 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 0, PINMUX_PC07I_CAN0_RX & 0xf}, 608 | #endif 609 | #if defined(PINMUX_PC08I_CAN0_RX) && !defined(IGNORE_PIN_PC08) 610 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 0, PINMUX_PC08I_CAN0_RX & 0xf}, 611 | #endif 612 | #if defined(PINMUX_PC09I_CAN0_RX) && !defined(IGNORE_PIN_PC09) 613 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 0, PINMUX_PC09I_CAN0_RX & 0xf}, 614 | #endif 615 | #if defined(PINMUX_PC10I_CAN0_RX) && !defined(IGNORE_PIN_PC10) 616 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 0, PINMUX_PC10I_CAN0_RX & 0xf}, 617 | #endif 618 | #if defined(PINMUX_PC11I_CAN0_RX) && !defined(IGNORE_PIN_PC11) 619 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 0, PINMUX_PC11I_CAN0_RX & 0xf}, 620 | #endif 621 | #if defined(PINMUX_PC12I_CAN0_RX) && !defined(IGNORE_PIN_PC12) 622 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 0, PINMUX_PC12I_CAN0_RX & 0xf}, 623 | #endif 624 | #if defined(PINMUX_PC13I_CAN0_RX) && !defined(IGNORE_PIN_PC13) 625 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 0, PINMUX_PC13I_CAN0_RX & 0xf}, 626 | #endif 627 | #if defined(PINMUX_PC14I_CAN0_RX) && !defined(IGNORE_PIN_PC14) 628 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 0, PINMUX_PC14I_CAN0_RX & 0xf}, 629 | #endif 630 | #if defined(PINMUX_PC15I_CAN0_RX) && !defined(IGNORE_PIN_PC15) 631 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 0, PINMUX_PC15I_CAN0_RX & 0xf}, 632 | #endif 633 | #if defined(PINMUX_PC16I_CAN0_RX) && !defined(IGNORE_PIN_PC16) 634 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 0, PINMUX_PC16I_CAN0_RX & 0xf}, 635 | #endif 636 | #if defined(PINMUX_PC17I_CAN0_RX) && !defined(IGNORE_PIN_PC17) 637 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 0, PINMUX_PC17I_CAN0_RX & 0xf}, 638 | #endif 639 | #if defined(PINMUX_PC18I_CAN0_RX) && !defined(IGNORE_PIN_PC18) 640 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 0, PINMUX_PC18I_CAN0_RX & 0xf}, 641 | #endif 642 | #if defined(PINMUX_PC19I_CAN0_RX) && !defined(IGNORE_PIN_PC19) 643 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 0, PINMUX_PC19I_CAN0_RX & 0xf}, 644 | #endif 645 | #if defined(PINMUX_PC20I_CAN0_RX) && !defined(IGNORE_PIN_PC20) 646 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 0, PINMUX_PC20I_CAN0_RX & 0xf}, 647 | #endif 648 | #if defined(PINMUX_PC21I_CAN0_RX) && !defined(IGNORE_PIN_PC21) 649 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 0, PINMUX_PC21I_CAN0_RX & 0xf}, 650 | #endif 651 | #if defined(PINMUX_PC22I_CAN0_RX) && !defined(IGNORE_PIN_PC22) 652 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 0, PINMUX_PC22I_CAN0_RX & 0xf}, 653 | #endif 654 | #if defined(PINMUX_PC23I_CAN0_RX) && !defined(IGNORE_PIN_PC23) 655 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 0, PINMUX_PC23I_CAN0_RX & 0xf}, 656 | #endif 657 | #if defined(PINMUX_PC24I_CAN0_RX) && !defined(IGNORE_PIN_PC24) 658 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 0, PINMUX_PC24I_CAN0_RX & 0xf}, 659 | #endif 660 | #if defined(PINMUX_PC25I_CAN0_RX) && !defined(IGNORE_PIN_PC25) 661 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 0, PINMUX_PC25I_CAN0_RX & 0xf}, 662 | #endif 663 | #if defined(PINMUX_PC26I_CAN0_RX) && !defined(IGNORE_PIN_PC26) 664 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 0, PINMUX_PC26I_CAN0_RX & 0xf}, 665 | #endif 666 | #if defined(PINMUX_PC27I_CAN0_RX) && !defined(IGNORE_PIN_PC27) 667 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 0, PINMUX_PC27I_CAN0_RX & 0xf}, 668 | #endif 669 | #if defined(PINMUX_PC28I_CAN0_RX) && !defined(IGNORE_PIN_PC28) 670 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 0, PINMUX_PC28I_CAN0_RX & 0xf}, 671 | #endif 672 | #if defined(PINMUX_PC29I_CAN0_RX) && !defined(IGNORE_PIN_PC29) 673 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 0, PINMUX_PC29I_CAN0_RX & 0xf}, 674 | #endif 675 | #if defined(PINMUX_PC30I_CAN0_RX) && !defined(IGNORE_PIN_PC30) 676 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 0, PINMUX_PC30I_CAN0_RX & 0xf}, 677 | #endif 678 | #if defined(PINMUX_PC31I_CAN0_RX) && !defined(IGNORE_PIN_PC31) 679 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 0, PINMUX_PC31I_CAN0_RX & 0xf}, 680 | #endif 681 | #if defined(PINMUX_PD00I_CAN0_RX) && !defined(IGNORE_PIN_PD00) 682 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 0, PINMUX_PD00I_CAN0_RX & 0xf}, 683 | #endif 684 | #if defined(PINMUX_PD01I_CAN0_RX) && !defined(IGNORE_PIN_PD01) 685 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 0, PINMUX_PD01I_CAN0_RX & 0xf}, 686 | #endif 687 | #if defined(PINMUX_PD02I_CAN0_RX) && !defined(IGNORE_PIN_PD02) 688 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 0, PINMUX_PD02I_CAN0_RX & 0xf}, 689 | #endif 690 | #if defined(PINMUX_PD03I_CAN0_RX) && !defined(IGNORE_PIN_PD03) 691 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 0, PINMUX_PD03I_CAN0_RX & 0xf}, 692 | #endif 693 | #if defined(PINMUX_PD04I_CAN0_RX) && !defined(IGNORE_PIN_PD04) 694 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 0, PINMUX_PD04I_CAN0_RX & 0xf}, 695 | #endif 696 | #if defined(PINMUX_PD05I_CAN0_RX) && !defined(IGNORE_PIN_PD05) 697 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 0, PINMUX_PD05I_CAN0_RX & 0xf}, 698 | #endif 699 | #if defined(PINMUX_PD06I_CAN0_RX) && !defined(IGNORE_PIN_PD06) 700 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 0, PINMUX_PD06I_CAN0_RX & 0xf}, 701 | #endif 702 | #if defined(PINMUX_PD07I_CAN0_RX) && !defined(IGNORE_PIN_PD07) 703 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 0, PINMUX_PD07I_CAN0_RX & 0xf}, 704 | #endif 705 | #if defined(PINMUX_PD08I_CAN0_RX) && !defined(IGNORE_PIN_PD08) 706 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 0, PINMUX_PD08I_CAN0_RX & 0xf}, 707 | #endif 708 | #if defined(PINMUX_PD09I_CAN0_RX) && !defined(IGNORE_PIN_PD09) 709 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 0, PINMUX_PD09I_CAN0_RX & 0xf}, 710 | #endif 711 | #if defined(PINMUX_PD10I_CAN0_RX) && !defined(IGNORE_PIN_PD10) 712 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 0, PINMUX_PD10I_CAN0_RX & 0xf}, 713 | #endif 714 | #if defined(PINMUX_PD11I_CAN0_RX) && !defined(IGNORE_PIN_PD11) 715 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 0, PINMUX_PD11I_CAN0_RX & 0xf}, 716 | #endif 717 | #if defined(PINMUX_PD12I_CAN0_RX) && !defined(IGNORE_PIN_PD12) 718 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 0, PINMUX_PD12I_CAN0_RX & 0xf}, 719 | #endif 720 | #if defined(PINMUX_PD13I_CAN0_RX) && !defined(IGNORE_PIN_PD13) 721 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 0, PINMUX_PD13I_CAN0_RX & 0xf}, 722 | #endif 723 | #if defined(PINMUX_PD14I_CAN0_RX) && !defined(IGNORE_PIN_PD14) 724 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 0, PINMUX_PD14I_CAN0_RX & 0xf}, 725 | #endif 726 | #if defined(PINMUX_PD15I_CAN0_RX) && !defined(IGNORE_PIN_PD15) 727 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 0, PINMUX_PD15I_CAN0_RX & 0xf}, 728 | #endif 729 | #if defined(PINMUX_PD16I_CAN0_RX) && !defined(IGNORE_PIN_PD16) 730 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 0, PINMUX_PD16I_CAN0_RX & 0xf}, 731 | #endif 732 | #if defined(PINMUX_PD17I_CAN0_RX) && !defined(IGNORE_PIN_PD17) 733 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 0, PINMUX_PD17I_CAN0_RX & 0xf}, 734 | #endif 735 | #if defined(PINMUX_PD18I_CAN0_RX) && !defined(IGNORE_PIN_PD18) 736 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 0, PINMUX_PD18I_CAN0_RX & 0xf}, 737 | #endif 738 | #if defined(PINMUX_PD19I_CAN0_RX) && !defined(IGNORE_PIN_PD19) 739 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 0, PINMUX_PD19I_CAN0_RX & 0xf}, 740 | #endif 741 | #if defined(PINMUX_PD20I_CAN0_RX) && !defined(IGNORE_PIN_PD20) 742 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 0, PINMUX_PD20I_CAN0_RX & 0xf}, 743 | #endif 744 | #if defined(PINMUX_PD21I_CAN0_RX) && !defined(IGNORE_PIN_PD21) 745 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 0, PINMUX_PD21I_CAN0_RX & 0xf}, 746 | #endif 747 | #if defined(PINMUX_PD22I_CAN0_RX) && !defined(IGNORE_PIN_PD22) 748 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 0, PINMUX_PD22I_CAN0_RX & 0xf}, 749 | #endif 750 | #if defined(PINMUX_PD23I_CAN0_RX) && !defined(IGNORE_PIN_PD23) 751 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 0, PINMUX_PD23I_CAN0_RX & 0xf}, 752 | #endif 753 | #if defined(PINMUX_PD24I_CAN0_RX) && !defined(IGNORE_PIN_PD24) 754 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 0, PINMUX_PD24I_CAN0_RX & 0xf}, 755 | #endif 756 | #if defined(PINMUX_PD25I_CAN0_RX) && !defined(IGNORE_PIN_PD25) 757 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 0, PINMUX_PD25I_CAN0_RX & 0xf}, 758 | #endif 759 | #if defined(PINMUX_PD26I_CAN0_RX) && !defined(IGNORE_PIN_PD26) 760 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 0, PINMUX_PD26I_CAN0_RX & 0xf}, 761 | #endif 762 | #if defined(PINMUX_PD27I_CAN0_RX) && !defined(IGNORE_PIN_PD27) 763 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 0, PINMUX_PD27I_CAN0_RX & 0xf}, 764 | #endif 765 | #if defined(PINMUX_PD28I_CAN0_RX) && !defined(IGNORE_PIN_PD28) 766 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 0, PINMUX_PD28I_CAN0_RX & 0xf}, 767 | #endif 768 | #if defined(PINMUX_PD29I_CAN0_RX) && !defined(IGNORE_PIN_PD29) 769 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 0, PINMUX_PD29I_CAN0_RX & 0xf}, 770 | #endif 771 | #if defined(PINMUX_PD30I_CAN0_RX) && !defined(IGNORE_PIN_PD30) 772 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 0, PINMUX_PD30I_CAN0_RX & 0xf}, 773 | #endif 774 | #if defined(PINMUX_PD31I_CAN0_RX) && !defined(IGNORE_PIN_PD31) 775 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 0, PINMUX_PD31I_CAN0_RX & 0xf}, 776 | #endif 777 | #if defined(PINMUX_PA00H_CAN1_RX) && !defined(IGNORE_PIN_PA00) 778 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 1, PINMUX_PA00H_CAN1_RX & 0xf}, 779 | #endif 780 | #if defined(PINMUX_PA01H_CAN1_RX) && !defined(IGNORE_PIN_PA01) 781 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 1, PINMUX_PA01H_CAN1_RX & 0xf}, 782 | #endif 783 | #if defined(PINMUX_PA02H_CAN1_RX) && !defined(IGNORE_PIN_PA02) 784 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 1, PINMUX_PA02H_CAN1_RX & 0xf}, 785 | #endif 786 | #if defined(PINMUX_PA03H_CAN1_RX) && !defined(IGNORE_PIN_PA03) 787 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 1, PINMUX_PA03H_CAN1_RX & 0xf}, 788 | #endif 789 | #if defined(PINMUX_PA04H_CAN1_RX) && !defined(IGNORE_PIN_PA04) 790 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 1, PINMUX_PA04H_CAN1_RX & 0xf}, 791 | #endif 792 | #if defined(PINMUX_PA05H_CAN1_RX) && !defined(IGNORE_PIN_PA05) 793 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 1, PINMUX_PA05H_CAN1_RX & 0xf}, 794 | #endif 795 | #if defined(PINMUX_PA06H_CAN1_RX) && !defined(IGNORE_PIN_PA06) 796 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 1, PINMUX_PA06H_CAN1_RX & 0xf}, 797 | #endif 798 | #if defined(PINMUX_PA07H_CAN1_RX) && !defined(IGNORE_PIN_PA07) 799 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 1, PINMUX_PA07H_CAN1_RX & 0xf}, 800 | #endif 801 | #if defined(PINMUX_PA08H_CAN1_RX) && !defined(IGNORE_PIN_PA08) 802 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 1, PINMUX_PA08H_CAN1_RX & 0xf}, 803 | #endif 804 | #if defined(PINMUX_PA09H_CAN1_RX) && !defined(IGNORE_PIN_PA09) 805 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 1, PINMUX_PA09H_CAN1_RX & 0xf}, 806 | #endif 807 | #if defined(PINMUX_PA10H_CAN1_RX) && !defined(IGNORE_PIN_PA10) 808 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 1, PINMUX_PA10H_CAN1_RX & 0xf}, 809 | #endif 810 | #if defined(PINMUX_PA11H_CAN1_RX) && !defined(IGNORE_PIN_PA11) 811 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 1, PINMUX_PA11H_CAN1_RX & 0xf}, 812 | #endif 813 | #if defined(PINMUX_PA12H_CAN1_RX) && !defined(IGNORE_PIN_PA12) 814 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 1, PINMUX_PA12H_CAN1_RX & 0xf}, 815 | #endif 816 | #if defined(PINMUX_PA13H_CAN1_RX) && !defined(IGNORE_PIN_PA13) 817 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 1, PINMUX_PA13H_CAN1_RX & 0xf}, 818 | #endif 819 | #if defined(PINMUX_PA14H_CAN1_RX) && !defined(IGNORE_PIN_PA14) 820 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 1, PINMUX_PA14H_CAN1_RX & 0xf}, 821 | #endif 822 | #if defined(PINMUX_PA15H_CAN1_RX) && !defined(IGNORE_PIN_PA15) 823 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 1, PINMUX_PA15H_CAN1_RX & 0xf}, 824 | #endif 825 | #if defined(PINMUX_PA16H_CAN1_RX) && !defined(IGNORE_PIN_PA16) 826 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 1, PINMUX_PA16H_CAN1_RX & 0xf}, 827 | #endif 828 | #if defined(PINMUX_PA17H_CAN1_RX) && !defined(IGNORE_PIN_PA17) 829 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 1, PINMUX_PA17H_CAN1_RX & 0xf}, 830 | #endif 831 | #if defined(PINMUX_PA18H_CAN1_RX) && !defined(IGNORE_PIN_PA18) 832 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 1, PINMUX_PA18H_CAN1_RX & 0xf}, 833 | #endif 834 | #if defined(PINMUX_PA19H_CAN1_RX) && !defined(IGNORE_PIN_PA19) 835 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 1, PINMUX_PA19H_CAN1_RX & 0xf}, 836 | #endif 837 | #if defined(PINMUX_PA20H_CAN1_RX) && !defined(IGNORE_PIN_PA20) 838 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 1, PINMUX_PA20H_CAN1_RX & 0xf}, 839 | #endif 840 | #if defined(PINMUX_PA21H_CAN1_RX) && !defined(IGNORE_PIN_PA21) 841 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 1, PINMUX_PA21H_CAN1_RX & 0xf}, 842 | #endif 843 | #if defined(PINMUX_PA22H_CAN1_RX) && !defined(IGNORE_PIN_PA22) 844 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 1, PINMUX_PA22H_CAN1_RX & 0xf}, 845 | #endif 846 | #if defined(PINMUX_PA23H_CAN1_RX) && !defined(IGNORE_PIN_PA23) 847 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 1, PINMUX_PA23H_CAN1_RX & 0xf}, 848 | #endif 849 | #if defined(PINMUX_PA24H_CAN1_RX) && !defined(IGNORE_PIN_PA24) 850 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 1, PINMUX_PA24H_CAN1_RX & 0xf}, 851 | #endif 852 | #if defined(PINMUX_PA25H_CAN1_RX) && !defined(IGNORE_PIN_PA25) 853 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 1, PINMUX_PA25H_CAN1_RX & 0xf}, 854 | #endif 855 | #if defined(PINMUX_PA26H_CAN1_RX) && !defined(IGNORE_PIN_PA26) 856 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 1, PINMUX_PA26H_CAN1_RX & 0xf}, 857 | #endif 858 | #if defined(PINMUX_PA27H_CAN1_RX) && !defined(IGNORE_PIN_PA27) 859 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 1, PINMUX_PA27H_CAN1_RX & 0xf}, 860 | #endif 861 | #if defined(PINMUX_PA28H_CAN1_RX) && !defined(IGNORE_PIN_PA28) 862 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 1, PINMUX_PA28H_CAN1_RX & 0xf}, 863 | #endif 864 | #if defined(PINMUX_PA29H_CAN1_RX) && !defined(IGNORE_PIN_PA29) 865 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 1, PINMUX_PA29H_CAN1_RX & 0xf}, 866 | #endif 867 | #if defined(PINMUX_PA30H_CAN1_RX) && !defined(IGNORE_PIN_PA30) 868 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 1, PINMUX_PA30H_CAN1_RX & 0xf}, 869 | #endif 870 | #if defined(PINMUX_PA31H_CAN1_RX) && !defined(IGNORE_PIN_PA31) 871 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 1, PINMUX_PA31H_CAN1_RX & 0xf}, 872 | #endif 873 | #if defined(PINMUX_PB00H_CAN1_RX) && !defined(IGNORE_PIN_PB00) 874 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 1, PINMUX_PB00H_CAN1_RX & 0xf}, 875 | #endif 876 | #if defined(PINMUX_PB01H_CAN1_RX) && !defined(IGNORE_PIN_PB01) 877 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 1, PINMUX_PB01H_CAN1_RX & 0xf}, 878 | #endif 879 | #if defined(PINMUX_PB02H_CAN1_RX) && !defined(IGNORE_PIN_PB02) 880 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 1, PINMUX_PB02H_CAN1_RX & 0xf}, 881 | #endif 882 | #if defined(PINMUX_PB03H_CAN1_RX) && !defined(IGNORE_PIN_PB03) 883 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 1, PINMUX_PB03H_CAN1_RX & 0xf}, 884 | #endif 885 | #if defined(PINMUX_PB04H_CAN1_RX) && !defined(IGNORE_PIN_PB04) 886 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 1, PINMUX_PB04H_CAN1_RX & 0xf}, 887 | #endif 888 | #if defined(PINMUX_PB05H_CAN1_RX) && !defined(IGNORE_PIN_PB05) 889 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 1, PINMUX_PB05H_CAN1_RX & 0xf}, 890 | #endif 891 | #if defined(PINMUX_PB06H_CAN1_RX) && !defined(IGNORE_PIN_PB06) 892 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 1, PINMUX_PB06H_CAN1_RX & 0xf}, 893 | #endif 894 | #if defined(PINMUX_PB07H_CAN1_RX) && !defined(IGNORE_PIN_PB07) 895 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 1, PINMUX_PB07H_CAN1_RX & 0xf}, 896 | #endif 897 | #if defined(PINMUX_PB08H_CAN1_RX) && !defined(IGNORE_PIN_PB08) 898 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 1, PINMUX_PB08H_CAN1_RX & 0xf}, 899 | #endif 900 | #if defined(PINMUX_PB09H_CAN1_RX) && !defined(IGNORE_PIN_PB09) 901 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 1, PINMUX_PB09H_CAN1_RX & 0xf}, 902 | #endif 903 | #if defined(PINMUX_PB10H_CAN1_RX) && !defined(IGNORE_PIN_PB10) 904 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 1, PINMUX_PB10H_CAN1_RX & 0xf}, 905 | #endif 906 | #if defined(PINMUX_PB11H_CAN1_RX) && !defined(IGNORE_PIN_PB11) 907 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 1, PINMUX_PB11H_CAN1_RX & 0xf}, 908 | #endif 909 | #if defined(PINMUX_PB12H_CAN1_RX) && !defined(IGNORE_PIN_PB12) 910 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 1, PINMUX_PB12H_CAN1_RX & 0xf}, 911 | #endif 912 | #if defined(PINMUX_PB13H_CAN1_RX) && !defined(IGNORE_PIN_PB13) 913 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 1, PINMUX_PB13H_CAN1_RX & 0xf}, 914 | #endif 915 | #if defined(PINMUX_PB14H_CAN1_RX) && !defined(IGNORE_PIN_PB14) 916 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 1, PINMUX_PB14H_CAN1_RX & 0xf}, 917 | #endif 918 | #if defined(PINMUX_PB15H_CAN1_RX) && !defined(IGNORE_PIN_PB15) 919 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 1, PINMUX_PB15H_CAN1_RX & 0xf}, 920 | #endif 921 | #if defined(PINMUX_PB16H_CAN1_RX) && !defined(IGNORE_PIN_PB16) 922 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 1, PINMUX_PB16H_CAN1_RX & 0xf}, 923 | #endif 924 | #if defined(PINMUX_PB17H_CAN1_RX) && !defined(IGNORE_PIN_PB17) 925 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 1, PINMUX_PB17H_CAN1_RX & 0xf}, 926 | #endif 927 | #if defined(PINMUX_PB18H_CAN1_RX) && !defined(IGNORE_PIN_PB18) 928 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 1, PINMUX_PB18H_CAN1_RX & 0xf}, 929 | #endif 930 | #if defined(PINMUX_PB19H_CAN1_RX) && !defined(IGNORE_PIN_PB19) 931 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 1, PINMUX_PB19H_CAN1_RX & 0xf}, 932 | #endif 933 | #if defined(PINMUX_PB20H_CAN1_RX) && !defined(IGNORE_PIN_PB20) 934 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 1, PINMUX_PB20H_CAN1_RX & 0xf}, 935 | #endif 936 | #if defined(PINMUX_PB21H_CAN1_RX) && !defined(IGNORE_PIN_PB21) 937 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 1, PINMUX_PB21H_CAN1_RX & 0xf}, 938 | #endif 939 | #if defined(PINMUX_PB22H_CAN1_RX) && !defined(IGNORE_PIN_PB22) 940 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 1, PINMUX_PB22H_CAN1_RX & 0xf}, 941 | #endif 942 | #if defined(PINMUX_PB23H_CAN1_RX) && !defined(IGNORE_PIN_PB23) 943 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 1, PINMUX_PB23H_CAN1_RX & 0xf}, 944 | #endif 945 | #if defined(PINMUX_PB24H_CAN1_RX) && !defined(IGNORE_PIN_PB24) 946 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 1, PINMUX_PB24H_CAN1_RX & 0xf}, 947 | #endif 948 | #if defined(PINMUX_PB25H_CAN1_RX) && !defined(IGNORE_PIN_PB25) 949 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 1, PINMUX_PB25H_CAN1_RX & 0xf}, 950 | #endif 951 | #if defined(PINMUX_PB26H_CAN1_RX) && !defined(IGNORE_PIN_PB26) 952 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 1, PINMUX_PB26H_CAN1_RX & 0xf}, 953 | #endif 954 | #if defined(PINMUX_PB27H_CAN1_RX) && !defined(IGNORE_PIN_PB27) 955 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 1, PINMUX_PB27H_CAN1_RX & 0xf}, 956 | #endif 957 | #if defined(PINMUX_PB28H_CAN1_RX) && !defined(IGNORE_PIN_PB28) 958 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 1, PINMUX_PB28H_CAN1_RX & 0xf}, 959 | #endif 960 | #if defined(PINMUX_PB29H_CAN1_RX) && !defined(IGNORE_PIN_PB29) 961 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 1, PINMUX_PB29H_CAN1_RX & 0xf}, 962 | #endif 963 | #if defined(PINMUX_PB30H_CAN1_RX) && !defined(IGNORE_PIN_PB30) 964 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 1, PINMUX_PB30H_CAN1_RX & 0xf}, 965 | #endif 966 | #if defined(PINMUX_PB31H_CAN1_RX) && !defined(IGNORE_PIN_PB31) 967 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 1, PINMUX_PB31H_CAN1_RX & 0xf}, 968 | #endif 969 | #if defined(PINMUX_PC00H_CAN1_RX) && !defined(IGNORE_PIN_PC00) 970 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 1, PINMUX_PC00H_CAN1_RX & 0xf}, 971 | #endif 972 | #if defined(PINMUX_PC01H_CAN1_RX) && !defined(IGNORE_PIN_PC01) 973 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 1, PINMUX_PC01H_CAN1_RX & 0xf}, 974 | #endif 975 | #if defined(PINMUX_PC02H_CAN1_RX) && !defined(IGNORE_PIN_PC02) 976 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 1, PINMUX_PC02H_CAN1_RX & 0xf}, 977 | #endif 978 | #if defined(PINMUX_PC03H_CAN1_RX) && !defined(IGNORE_PIN_PC03) 979 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 1, PINMUX_PC03H_CAN1_RX & 0xf}, 980 | #endif 981 | #if defined(PINMUX_PC04H_CAN1_RX) && !defined(IGNORE_PIN_PC04) 982 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 1, PINMUX_PC04H_CAN1_RX & 0xf}, 983 | #endif 984 | #if defined(PINMUX_PC05H_CAN1_RX) && !defined(IGNORE_PIN_PC05) 985 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 1, PINMUX_PC05H_CAN1_RX & 0xf}, 986 | #endif 987 | #if defined(PINMUX_PC06H_CAN1_RX) && !defined(IGNORE_PIN_PC06) 988 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 1, PINMUX_PC06H_CAN1_RX & 0xf}, 989 | #endif 990 | #if defined(PINMUX_PC07H_CAN1_RX) && !defined(IGNORE_PIN_PC07) 991 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 1, PINMUX_PC07H_CAN1_RX & 0xf}, 992 | #endif 993 | #if defined(PINMUX_PC08H_CAN1_RX) && !defined(IGNORE_PIN_PC08) 994 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 1, PINMUX_PC08H_CAN1_RX & 0xf}, 995 | #endif 996 | #if defined(PINMUX_PC09H_CAN1_RX) && !defined(IGNORE_PIN_PC09) 997 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 1, PINMUX_PC09H_CAN1_RX & 0xf}, 998 | #endif 999 | #if defined(PINMUX_PC10H_CAN1_RX) && !defined(IGNORE_PIN_PC10) 1000 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 1, PINMUX_PC10H_CAN1_RX & 0xf}, 1001 | #endif 1002 | #if defined(PINMUX_PC11H_CAN1_RX) && !defined(IGNORE_PIN_PC11) 1003 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 1, PINMUX_PC11H_CAN1_RX & 0xf}, 1004 | #endif 1005 | #if defined(PINMUX_PC12H_CAN1_RX) && !defined(IGNORE_PIN_PC12) 1006 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 1, PINMUX_PC12H_CAN1_RX & 0xf}, 1007 | #endif 1008 | #if defined(PINMUX_PC13H_CAN1_RX) && !defined(IGNORE_PIN_PC13) 1009 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 1, PINMUX_PC13H_CAN1_RX & 0xf}, 1010 | #endif 1011 | #if defined(PINMUX_PC14H_CAN1_RX) && !defined(IGNORE_PIN_PC14) 1012 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 1, PINMUX_PC14H_CAN1_RX & 0xf}, 1013 | #endif 1014 | #if defined(PINMUX_PC15H_CAN1_RX) && !defined(IGNORE_PIN_PC15) 1015 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 1, PINMUX_PC15H_CAN1_RX & 0xf}, 1016 | #endif 1017 | #if defined(PINMUX_PC16H_CAN1_RX) && !defined(IGNORE_PIN_PC16) 1018 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 1, PINMUX_PC16H_CAN1_RX & 0xf}, 1019 | #endif 1020 | #if defined(PINMUX_PC17H_CAN1_RX) && !defined(IGNORE_PIN_PC17) 1021 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 1, PINMUX_PC17H_CAN1_RX & 0xf}, 1022 | #endif 1023 | #if defined(PINMUX_PC18H_CAN1_RX) && !defined(IGNORE_PIN_PC18) 1024 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 1, PINMUX_PC18H_CAN1_RX & 0xf}, 1025 | #endif 1026 | #if defined(PINMUX_PC19H_CAN1_RX) && !defined(IGNORE_PIN_PC19) 1027 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 1, PINMUX_PC19H_CAN1_RX & 0xf}, 1028 | #endif 1029 | #if defined(PINMUX_PC20H_CAN1_RX) && !defined(IGNORE_PIN_PC20) 1030 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 1, PINMUX_PC20H_CAN1_RX & 0xf}, 1031 | #endif 1032 | #if defined(PINMUX_PC21H_CAN1_RX) && !defined(IGNORE_PIN_PC21) 1033 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 1, PINMUX_PC21H_CAN1_RX & 0xf}, 1034 | #endif 1035 | #if defined(PINMUX_PC22H_CAN1_RX) && !defined(IGNORE_PIN_PC22) 1036 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 1, PINMUX_PC22H_CAN1_RX & 0xf}, 1037 | #endif 1038 | #if defined(PINMUX_PC23H_CAN1_RX) && !defined(IGNORE_PIN_PC23) 1039 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 1, PINMUX_PC23H_CAN1_RX & 0xf}, 1040 | #endif 1041 | #if defined(PINMUX_PC24H_CAN1_RX) && !defined(IGNORE_PIN_PC24) 1042 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 1, PINMUX_PC24H_CAN1_RX & 0xf}, 1043 | #endif 1044 | #if defined(PINMUX_PC25H_CAN1_RX) && !defined(IGNORE_PIN_PC25) 1045 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 1, PINMUX_PC25H_CAN1_RX & 0xf}, 1046 | #endif 1047 | #if defined(PINMUX_PC26H_CAN1_RX) && !defined(IGNORE_PIN_PC26) 1048 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 1, PINMUX_PC26H_CAN1_RX & 0xf}, 1049 | #endif 1050 | #if defined(PINMUX_PC27H_CAN1_RX) && !defined(IGNORE_PIN_PC27) 1051 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 1, PINMUX_PC27H_CAN1_RX & 0xf}, 1052 | #endif 1053 | #if defined(PINMUX_PC28H_CAN1_RX) && !defined(IGNORE_PIN_PC28) 1054 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 1, PINMUX_PC28H_CAN1_RX & 0xf}, 1055 | #endif 1056 | #if defined(PINMUX_PC29H_CAN1_RX) && !defined(IGNORE_PIN_PC29) 1057 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 1, PINMUX_PC29H_CAN1_RX & 0xf}, 1058 | #endif 1059 | #if defined(PINMUX_PC30H_CAN1_RX) && !defined(IGNORE_PIN_PC30) 1060 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 1, PINMUX_PC30H_CAN1_RX & 0xf}, 1061 | #endif 1062 | #if defined(PINMUX_PC31H_CAN1_RX) && !defined(IGNORE_PIN_PC31) 1063 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 1, PINMUX_PC31H_CAN1_RX & 0xf}, 1064 | #endif 1065 | #if defined(PINMUX_PD00H_CAN1_RX) && !defined(IGNORE_PIN_PD00) 1066 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 1, PINMUX_PD00H_CAN1_RX & 0xf}, 1067 | #endif 1068 | #if defined(PINMUX_PD01H_CAN1_RX) && !defined(IGNORE_PIN_PD01) 1069 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 1, PINMUX_PD01H_CAN1_RX & 0xf}, 1070 | #endif 1071 | #if defined(PINMUX_PD02H_CAN1_RX) && !defined(IGNORE_PIN_PD02) 1072 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 1, PINMUX_PD02H_CAN1_RX & 0xf}, 1073 | #endif 1074 | #if defined(PINMUX_PD03H_CAN1_RX) && !defined(IGNORE_PIN_PD03) 1075 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 1, PINMUX_PD03H_CAN1_RX & 0xf}, 1076 | #endif 1077 | #if defined(PINMUX_PD04H_CAN1_RX) && !defined(IGNORE_PIN_PD04) 1078 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 1, PINMUX_PD04H_CAN1_RX & 0xf}, 1079 | #endif 1080 | #if defined(PINMUX_PD05H_CAN1_RX) && !defined(IGNORE_PIN_PD05) 1081 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 1, PINMUX_PD05H_CAN1_RX & 0xf}, 1082 | #endif 1083 | #if defined(PINMUX_PD06H_CAN1_RX) && !defined(IGNORE_PIN_PD06) 1084 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 1, PINMUX_PD06H_CAN1_RX & 0xf}, 1085 | #endif 1086 | #if defined(PINMUX_PD07H_CAN1_RX) && !defined(IGNORE_PIN_PD07) 1087 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 1, PINMUX_PD07H_CAN1_RX & 0xf}, 1088 | #endif 1089 | #if defined(PINMUX_PD08H_CAN1_RX) && !defined(IGNORE_PIN_PD08) 1090 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 1, PINMUX_PD08H_CAN1_RX & 0xf}, 1091 | #endif 1092 | #if defined(PINMUX_PD09H_CAN1_RX) && !defined(IGNORE_PIN_PD09) 1093 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 1, PINMUX_PD09H_CAN1_RX & 0xf}, 1094 | #endif 1095 | #if defined(PINMUX_PD10H_CAN1_RX) && !defined(IGNORE_PIN_PD10) 1096 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 1, PINMUX_PD10H_CAN1_RX & 0xf}, 1097 | #endif 1098 | #if defined(PINMUX_PD11H_CAN1_RX) && !defined(IGNORE_PIN_PD11) 1099 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 1, PINMUX_PD11H_CAN1_RX & 0xf}, 1100 | #endif 1101 | #if defined(PINMUX_PD12H_CAN1_RX) && !defined(IGNORE_PIN_PD12) 1102 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 1, PINMUX_PD12H_CAN1_RX & 0xf}, 1103 | #endif 1104 | #if defined(PINMUX_PD13H_CAN1_RX) && !defined(IGNORE_PIN_PD13) 1105 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 1, PINMUX_PD13H_CAN1_RX & 0xf}, 1106 | #endif 1107 | #if defined(PINMUX_PD14H_CAN1_RX) && !defined(IGNORE_PIN_PD14) 1108 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 1, PINMUX_PD14H_CAN1_RX & 0xf}, 1109 | #endif 1110 | #if defined(PINMUX_PD15H_CAN1_RX) && !defined(IGNORE_PIN_PD15) 1111 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 1, PINMUX_PD15H_CAN1_RX & 0xf}, 1112 | #endif 1113 | #if defined(PINMUX_PD16H_CAN1_RX) && !defined(IGNORE_PIN_PD16) 1114 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 1, PINMUX_PD16H_CAN1_RX & 0xf}, 1115 | #endif 1116 | #if defined(PINMUX_PD17H_CAN1_RX) && !defined(IGNORE_PIN_PD17) 1117 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 1, PINMUX_PD17H_CAN1_RX & 0xf}, 1118 | #endif 1119 | #if defined(PINMUX_PD18H_CAN1_RX) && !defined(IGNORE_PIN_PD18) 1120 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 1, PINMUX_PD18H_CAN1_RX & 0xf}, 1121 | #endif 1122 | #if defined(PINMUX_PD19H_CAN1_RX) && !defined(IGNORE_PIN_PD19) 1123 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 1, PINMUX_PD19H_CAN1_RX & 0xf}, 1124 | #endif 1125 | #if defined(PINMUX_PD20H_CAN1_RX) && !defined(IGNORE_PIN_PD20) 1126 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 1, PINMUX_PD20H_CAN1_RX & 0xf}, 1127 | #endif 1128 | #if defined(PINMUX_PD21H_CAN1_RX) && !defined(IGNORE_PIN_PD21) 1129 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 1, PINMUX_PD21H_CAN1_RX & 0xf}, 1130 | #endif 1131 | #if defined(PINMUX_PD22H_CAN1_RX) && !defined(IGNORE_PIN_PD22) 1132 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 1, PINMUX_PD22H_CAN1_RX & 0xf}, 1133 | #endif 1134 | #if defined(PINMUX_PD23H_CAN1_RX) && !defined(IGNORE_PIN_PD23) 1135 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 1, PINMUX_PD23H_CAN1_RX & 0xf}, 1136 | #endif 1137 | #if defined(PINMUX_PD24H_CAN1_RX) && !defined(IGNORE_PIN_PD24) 1138 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 1, PINMUX_PD24H_CAN1_RX & 0xf}, 1139 | #endif 1140 | #if defined(PINMUX_PD25H_CAN1_RX) && !defined(IGNORE_PIN_PD25) 1141 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 1, PINMUX_PD25H_CAN1_RX & 0xf}, 1142 | #endif 1143 | #if defined(PINMUX_PD26H_CAN1_RX) && !defined(IGNORE_PIN_PD26) 1144 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 1, PINMUX_PD26H_CAN1_RX & 0xf}, 1145 | #endif 1146 | #if defined(PINMUX_PD27H_CAN1_RX) && !defined(IGNORE_PIN_PD27) 1147 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 1, PINMUX_PD27H_CAN1_RX & 0xf}, 1148 | #endif 1149 | #if defined(PINMUX_PD28H_CAN1_RX) && !defined(IGNORE_PIN_PD28) 1150 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 1, PINMUX_PD28H_CAN1_RX & 0xf}, 1151 | #endif 1152 | #if defined(PINMUX_PD29H_CAN1_RX) && !defined(IGNORE_PIN_PD29) 1153 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 1, PINMUX_PD29H_CAN1_RX & 0xf}, 1154 | #endif 1155 | #if defined(PINMUX_PD30H_CAN1_RX) && !defined(IGNORE_PIN_PD30) 1156 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 1, PINMUX_PD30H_CAN1_RX & 0xf}, 1157 | #endif 1158 | #if defined(PINMUX_PD31H_CAN1_RX) && !defined(IGNORE_PIN_PD31) 1159 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 1, PINMUX_PD31H_CAN1_RX & 0xf}, 1160 | #endif 1161 | #if defined(PINMUX_PA00I_CAN1_RX) && !defined(IGNORE_PIN_PA00) 1162 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 1, PINMUX_PA00I_CAN1_RX & 0xf}, 1163 | #endif 1164 | #if defined(PINMUX_PA01I_CAN1_RX) && !defined(IGNORE_PIN_PA01) 1165 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 1, PINMUX_PA01I_CAN1_RX & 0xf}, 1166 | #endif 1167 | #if defined(PINMUX_PA02I_CAN1_RX) && !defined(IGNORE_PIN_PA02) 1168 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 1, PINMUX_PA02I_CAN1_RX & 0xf}, 1169 | #endif 1170 | #if defined(PINMUX_PA03I_CAN1_RX) && !defined(IGNORE_PIN_PA03) 1171 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 1, PINMUX_PA03I_CAN1_RX & 0xf}, 1172 | #endif 1173 | #if defined(PINMUX_PA04I_CAN1_RX) && !defined(IGNORE_PIN_PA04) 1174 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 1, PINMUX_PA04I_CAN1_RX & 0xf}, 1175 | #endif 1176 | #if defined(PINMUX_PA05I_CAN1_RX) && !defined(IGNORE_PIN_PA05) 1177 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 1, PINMUX_PA05I_CAN1_RX & 0xf}, 1178 | #endif 1179 | #if defined(PINMUX_PA06I_CAN1_RX) && !defined(IGNORE_PIN_PA06) 1180 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 1, PINMUX_PA06I_CAN1_RX & 0xf}, 1181 | #endif 1182 | #if defined(PINMUX_PA07I_CAN1_RX) && !defined(IGNORE_PIN_PA07) 1183 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 1, PINMUX_PA07I_CAN1_RX & 0xf}, 1184 | #endif 1185 | #if defined(PINMUX_PA08I_CAN1_RX) && !defined(IGNORE_PIN_PA08) 1186 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 1, PINMUX_PA08I_CAN1_RX & 0xf}, 1187 | #endif 1188 | #if defined(PINMUX_PA09I_CAN1_RX) && !defined(IGNORE_PIN_PA09) 1189 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 1, PINMUX_PA09I_CAN1_RX & 0xf}, 1190 | #endif 1191 | #if defined(PINMUX_PA10I_CAN1_RX) && !defined(IGNORE_PIN_PA10) 1192 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 1, PINMUX_PA10I_CAN1_RX & 0xf}, 1193 | #endif 1194 | #if defined(PINMUX_PA11I_CAN1_RX) && !defined(IGNORE_PIN_PA11) 1195 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 1, PINMUX_PA11I_CAN1_RX & 0xf}, 1196 | #endif 1197 | #if defined(PINMUX_PA12I_CAN1_RX) && !defined(IGNORE_PIN_PA12) 1198 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 1, PINMUX_PA12I_CAN1_RX & 0xf}, 1199 | #endif 1200 | #if defined(PINMUX_PA13I_CAN1_RX) && !defined(IGNORE_PIN_PA13) 1201 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 1, PINMUX_PA13I_CAN1_RX & 0xf}, 1202 | #endif 1203 | #if defined(PINMUX_PA14I_CAN1_RX) && !defined(IGNORE_PIN_PA14) 1204 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 1, PINMUX_PA14I_CAN1_RX & 0xf}, 1205 | #endif 1206 | #if defined(PINMUX_PA15I_CAN1_RX) && !defined(IGNORE_PIN_PA15) 1207 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 1, PINMUX_PA15I_CAN1_RX & 0xf}, 1208 | #endif 1209 | #if defined(PINMUX_PA16I_CAN1_RX) && !defined(IGNORE_PIN_PA16) 1210 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 1, PINMUX_PA16I_CAN1_RX & 0xf}, 1211 | #endif 1212 | #if defined(PINMUX_PA17I_CAN1_RX) && !defined(IGNORE_PIN_PA17) 1213 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 1, PINMUX_PA17I_CAN1_RX & 0xf}, 1214 | #endif 1215 | #if defined(PINMUX_PA18I_CAN1_RX) && !defined(IGNORE_PIN_PA18) 1216 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 1, PINMUX_PA18I_CAN1_RX & 0xf}, 1217 | #endif 1218 | #if defined(PINMUX_PA19I_CAN1_RX) && !defined(IGNORE_PIN_PA19) 1219 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 1, PINMUX_PA19I_CAN1_RX & 0xf}, 1220 | #endif 1221 | #if defined(PINMUX_PA20I_CAN1_RX) && !defined(IGNORE_PIN_PA20) 1222 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 1, PINMUX_PA20I_CAN1_RX & 0xf}, 1223 | #endif 1224 | #if defined(PINMUX_PA21I_CAN1_RX) && !defined(IGNORE_PIN_PA21) 1225 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 1, PINMUX_PA21I_CAN1_RX & 0xf}, 1226 | #endif 1227 | #if defined(PINMUX_PA22I_CAN1_RX) && !defined(IGNORE_PIN_PA22) 1228 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 1, PINMUX_PA22I_CAN1_RX & 0xf}, 1229 | #endif 1230 | #if defined(PINMUX_PA23I_CAN1_RX) && !defined(IGNORE_PIN_PA23) 1231 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 1, PINMUX_PA23I_CAN1_RX & 0xf}, 1232 | #endif 1233 | #if defined(PINMUX_PA24I_CAN1_RX) && !defined(IGNORE_PIN_PA24) 1234 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 1, PINMUX_PA24I_CAN1_RX & 0xf}, 1235 | #endif 1236 | #if defined(PINMUX_PA25I_CAN1_RX) && !defined(IGNORE_PIN_PA25) 1237 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 1, PINMUX_PA25I_CAN1_RX & 0xf}, 1238 | #endif 1239 | #if defined(PINMUX_PA26I_CAN1_RX) && !defined(IGNORE_PIN_PA26) 1240 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 1, PINMUX_PA26I_CAN1_RX & 0xf}, 1241 | #endif 1242 | #if defined(PINMUX_PA27I_CAN1_RX) && !defined(IGNORE_PIN_PA27) 1243 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 1, PINMUX_PA27I_CAN1_RX & 0xf}, 1244 | #endif 1245 | #if defined(PINMUX_PA28I_CAN1_RX) && !defined(IGNORE_PIN_PA28) 1246 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 1, PINMUX_PA28I_CAN1_RX & 0xf}, 1247 | #endif 1248 | #if defined(PINMUX_PA29I_CAN1_RX) && !defined(IGNORE_PIN_PA29) 1249 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 1, PINMUX_PA29I_CAN1_RX & 0xf}, 1250 | #endif 1251 | #if defined(PINMUX_PA30I_CAN1_RX) && !defined(IGNORE_PIN_PA30) 1252 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 1, PINMUX_PA30I_CAN1_RX & 0xf}, 1253 | #endif 1254 | #if defined(PINMUX_PA31I_CAN1_RX) && !defined(IGNORE_PIN_PA31) 1255 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 1, PINMUX_PA31I_CAN1_RX & 0xf}, 1256 | #endif 1257 | #if defined(PINMUX_PB00I_CAN1_RX) && !defined(IGNORE_PIN_PB00) 1258 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 1, PINMUX_PB00I_CAN1_RX & 0xf}, 1259 | #endif 1260 | #if defined(PINMUX_PB01I_CAN1_RX) && !defined(IGNORE_PIN_PB01) 1261 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 1, PINMUX_PB01I_CAN1_RX & 0xf}, 1262 | #endif 1263 | #if defined(PINMUX_PB02I_CAN1_RX) && !defined(IGNORE_PIN_PB02) 1264 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 1, PINMUX_PB02I_CAN1_RX & 0xf}, 1265 | #endif 1266 | #if defined(PINMUX_PB03I_CAN1_RX) && !defined(IGNORE_PIN_PB03) 1267 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 1, PINMUX_PB03I_CAN1_RX & 0xf}, 1268 | #endif 1269 | #if defined(PINMUX_PB04I_CAN1_RX) && !defined(IGNORE_PIN_PB04) 1270 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 1, PINMUX_PB04I_CAN1_RX & 0xf}, 1271 | #endif 1272 | #if defined(PINMUX_PB05I_CAN1_RX) && !defined(IGNORE_PIN_PB05) 1273 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 1, PINMUX_PB05I_CAN1_RX & 0xf}, 1274 | #endif 1275 | #if defined(PINMUX_PB06I_CAN1_RX) && !defined(IGNORE_PIN_PB06) 1276 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 1, PINMUX_PB06I_CAN1_RX & 0xf}, 1277 | #endif 1278 | #if defined(PINMUX_PB07I_CAN1_RX) && !defined(IGNORE_PIN_PB07) 1279 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 1, PINMUX_PB07I_CAN1_RX & 0xf}, 1280 | #endif 1281 | #if defined(PINMUX_PB08I_CAN1_RX) && !defined(IGNORE_PIN_PB08) 1282 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 1, PINMUX_PB08I_CAN1_RX & 0xf}, 1283 | #endif 1284 | #if defined(PINMUX_PB09I_CAN1_RX) && !defined(IGNORE_PIN_PB09) 1285 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 1, PINMUX_PB09I_CAN1_RX & 0xf}, 1286 | #endif 1287 | #if defined(PINMUX_PB10I_CAN1_RX) && !defined(IGNORE_PIN_PB10) 1288 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 1, PINMUX_PB10I_CAN1_RX & 0xf}, 1289 | #endif 1290 | #if defined(PINMUX_PB11I_CAN1_RX) && !defined(IGNORE_PIN_PB11) 1291 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 1, PINMUX_PB11I_CAN1_RX & 0xf}, 1292 | #endif 1293 | #if defined(PINMUX_PB12I_CAN1_RX) && !defined(IGNORE_PIN_PB12) 1294 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 1, PINMUX_PB12I_CAN1_RX & 0xf}, 1295 | #endif 1296 | #if defined(PINMUX_PB13I_CAN1_RX) && !defined(IGNORE_PIN_PB13) 1297 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 1, PINMUX_PB13I_CAN1_RX & 0xf}, 1298 | #endif 1299 | #if defined(PINMUX_PB14I_CAN1_RX) && !defined(IGNORE_PIN_PB14) 1300 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 1, PINMUX_PB14I_CAN1_RX & 0xf}, 1301 | #endif 1302 | #if defined(PINMUX_PB15I_CAN1_RX) && !defined(IGNORE_PIN_PB15) 1303 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 1, PINMUX_PB15I_CAN1_RX & 0xf}, 1304 | #endif 1305 | #if defined(PINMUX_PB16I_CAN1_RX) && !defined(IGNORE_PIN_PB16) 1306 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 1, PINMUX_PB16I_CAN1_RX & 0xf}, 1307 | #endif 1308 | #if defined(PINMUX_PB17I_CAN1_RX) && !defined(IGNORE_PIN_PB17) 1309 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 1, PINMUX_PB17I_CAN1_RX & 0xf}, 1310 | #endif 1311 | #if defined(PINMUX_PB18I_CAN1_RX) && !defined(IGNORE_PIN_PB18) 1312 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 1, PINMUX_PB18I_CAN1_RX & 0xf}, 1313 | #endif 1314 | #if defined(PINMUX_PB19I_CAN1_RX) && !defined(IGNORE_PIN_PB19) 1315 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 1, PINMUX_PB19I_CAN1_RX & 0xf}, 1316 | #endif 1317 | #if defined(PINMUX_PB20I_CAN1_RX) && !defined(IGNORE_PIN_PB20) 1318 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 1, PINMUX_PB20I_CAN1_RX & 0xf}, 1319 | #endif 1320 | #if defined(PINMUX_PB21I_CAN1_RX) && !defined(IGNORE_PIN_PB21) 1321 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 1, PINMUX_PB21I_CAN1_RX & 0xf}, 1322 | #endif 1323 | #if defined(PINMUX_PB22I_CAN1_RX) && !defined(IGNORE_PIN_PB22) 1324 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 1, PINMUX_PB22I_CAN1_RX & 0xf}, 1325 | #endif 1326 | #if defined(PINMUX_PB23I_CAN1_RX) && !defined(IGNORE_PIN_PB23) 1327 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 1, PINMUX_PB23I_CAN1_RX & 0xf}, 1328 | #endif 1329 | #if defined(PINMUX_PB24I_CAN1_RX) && !defined(IGNORE_PIN_PB24) 1330 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 1, PINMUX_PB24I_CAN1_RX & 0xf}, 1331 | #endif 1332 | #if defined(PINMUX_PB25I_CAN1_RX) && !defined(IGNORE_PIN_PB25) 1333 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 1, PINMUX_PB25I_CAN1_RX & 0xf}, 1334 | #endif 1335 | #if defined(PINMUX_PB26I_CAN1_RX) && !defined(IGNORE_PIN_PB26) 1336 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 1, PINMUX_PB26I_CAN1_RX & 0xf}, 1337 | #endif 1338 | #if defined(PINMUX_PB27I_CAN1_RX) && !defined(IGNORE_PIN_PB27) 1339 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 1, PINMUX_PB27I_CAN1_RX & 0xf}, 1340 | #endif 1341 | #if defined(PINMUX_PB28I_CAN1_RX) && !defined(IGNORE_PIN_PB28) 1342 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 1, PINMUX_PB28I_CAN1_RX & 0xf}, 1343 | #endif 1344 | #if defined(PINMUX_PB29I_CAN1_RX) && !defined(IGNORE_PIN_PB29) 1345 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 1, PINMUX_PB29I_CAN1_RX & 0xf}, 1346 | #endif 1347 | #if defined(PINMUX_PB30I_CAN1_RX) && !defined(IGNORE_PIN_PB30) 1348 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 1, PINMUX_PB30I_CAN1_RX & 0xf}, 1349 | #endif 1350 | #if defined(PINMUX_PB31I_CAN1_RX) && !defined(IGNORE_PIN_PB31) 1351 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 1, PINMUX_PB31I_CAN1_RX & 0xf}, 1352 | #endif 1353 | #if defined(PINMUX_PC00I_CAN1_RX) && !defined(IGNORE_PIN_PC00) 1354 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 1, PINMUX_PC00I_CAN1_RX & 0xf}, 1355 | #endif 1356 | #if defined(PINMUX_PC01I_CAN1_RX) && !defined(IGNORE_PIN_PC01) 1357 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 1, PINMUX_PC01I_CAN1_RX & 0xf}, 1358 | #endif 1359 | #if defined(PINMUX_PC02I_CAN1_RX) && !defined(IGNORE_PIN_PC02) 1360 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 1, PINMUX_PC02I_CAN1_RX & 0xf}, 1361 | #endif 1362 | #if defined(PINMUX_PC03I_CAN1_RX) && !defined(IGNORE_PIN_PC03) 1363 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 1, PINMUX_PC03I_CAN1_RX & 0xf}, 1364 | #endif 1365 | #if defined(PINMUX_PC04I_CAN1_RX) && !defined(IGNORE_PIN_PC04) 1366 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 1, PINMUX_PC04I_CAN1_RX & 0xf}, 1367 | #endif 1368 | #if defined(PINMUX_PC05I_CAN1_RX) && !defined(IGNORE_PIN_PC05) 1369 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 1, PINMUX_PC05I_CAN1_RX & 0xf}, 1370 | #endif 1371 | #if defined(PINMUX_PC06I_CAN1_RX) && !defined(IGNORE_PIN_PC06) 1372 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 1, PINMUX_PC06I_CAN1_RX & 0xf}, 1373 | #endif 1374 | #if defined(PINMUX_PC07I_CAN1_RX) && !defined(IGNORE_PIN_PC07) 1375 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 1, PINMUX_PC07I_CAN1_RX & 0xf}, 1376 | #endif 1377 | #if defined(PINMUX_PC08I_CAN1_RX) && !defined(IGNORE_PIN_PC08) 1378 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 1, PINMUX_PC08I_CAN1_RX & 0xf}, 1379 | #endif 1380 | #if defined(PINMUX_PC09I_CAN1_RX) && !defined(IGNORE_PIN_PC09) 1381 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 1, PINMUX_PC09I_CAN1_RX & 0xf}, 1382 | #endif 1383 | #if defined(PINMUX_PC10I_CAN1_RX) && !defined(IGNORE_PIN_PC10) 1384 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 1, PINMUX_PC10I_CAN1_RX & 0xf}, 1385 | #endif 1386 | #if defined(PINMUX_PC11I_CAN1_RX) && !defined(IGNORE_PIN_PC11) 1387 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 1, PINMUX_PC11I_CAN1_RX & 0xf}, 1388 | #endif 1389 | #if defined(PINMUX_PC12I_CAN1_RX) && !defined(IGNORE_PIN_PC12) 1390 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 1, PINMUX_PC12I_CAN1_RX & 0xf}, 1391 | #endif 1392 | #if defined(PINMUX_PC13I_CAN1_RX) && !defined(IGNORE_PIN_PC13) 1393 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 1, PINMUX_PC13I_CAN1_RX & 0xf}, 1394 | #endif 1395 | #if defined(PINMUX_PC14I_CAN1_RX) && !defined(IGNORE_PIN_PC14) 1396 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 1, PINMUX_PC14I_CAN1_RX & 0xf}, 1397 | #endif 1398 | #if defined(PINMUX_PC15I_CAN1_RX) && !defined(IGNORE_PIN_PC15) 1399 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 1, PINMUX_PC15I_CAN1_RX & 0xf}, 1400 | #endif 1401 | #if defined(PINMUX_PC16I_CAN1_RX) && !defined(IGNORE_PIN_PC16) 1402 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 1, PINMUX_PC16I_CAN1_RX & 0xf}, 1403 | #endif 1404 | #if defined(PINMUX_PC17I_CAN1_RX) && !defined(IGNORE_PIN_PC17) 1405 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 1, PINMUX_PC17I_CAN1_RX & 0xf}, 1406 | #endif 1407 | #if defined(PINMUX_PC18I_CAN1_RX) && !defined(IGNORE_PIN_PC18) 1408 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 1, PINMUX_PC18I_CAN1_RX & 0xf}, 1409 | #endif 1410 | #if defined(PINMUX_PC19I_CAN1_RX) && !defined(IGNORE_PIN_PC19) 1411 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 1, PINMUX_PC19I_CAN1_RX & 0xf}, 1412 | #endif 1413 | #if defined(PINMUX_PC20I_CAN1_RX) && !defined(IGNORE_PIN_PC20) 1414 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 1, PINMUX_PC20I_CAN1_RX & 0xf}, 1415 | #endif 1416 | #if defined(PINMUX_PC21I_CAN1_RX) && !defined(IGNORE_PIN_PC21) 1417 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 1, PINMUX_PC21I_CAN1_RX & 0xf}, 1418 | #endif 1419 | #if defined(PINMUX_PC22I_CAN1_RX) && !defined(IGNORE_PIN_PC22) 1420 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 1, PINMUX_PC22I_CAN1_RX & 0xf}, 1421 | #endif 1422 | #if defined(PINMUX_PC23I_CAN1_RX) && !defined(IGNORE_PIN_PC23) 1423 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 1, PINMUX_PC23I_CAN1_RX & 0xf}, 1424 | #endif 1425 | #if defined(PINMUX_PC24I_CAN1_RX) && !defined(IGNORE_PIN_PC24) 1426 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 1, PINMUX_PC24I_CAN1_RX & 0xf}, 1427 | #endif 1428 | #if defined(PINMUX_PC25I_CAN1_RX) && !defined(IGNORE_PIN_PC25) 1429 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 1, PINMUX_PC25I_CAN1_RX & 0xf}, 1430 | #endif 1431 | #if defined(PINMUX_PC26I_CAN1_RX) && !defined(IGNORE_PIN_PC26) 1432 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 1, PINMUX_PC26I_CAN1_RX & 0xf}, 1433 | #endif 1434 | #if defined(PINMUX_PC27I_CAN1_RX) && !defined(IGNORE_PIN_PC27) 1435 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 1, PINMUX_PC27I_CAN1_RX & 0xf}, 1436 | #endif 1437 | #if defined(PINMUX_PC28I_CAN1_RX) && !defined(IGNORE_PIN_PC28) 1438 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 1, PINMUX_PC28I_CAN1_RX & 0xf}, 1439 | #endif 1440 | #if defined(PINMUX_PC29I_CAN1_RX) && !defined(IGNORE_PIN_PC29) 1441 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 1, PINMUX_PC29I_CAN1_RX & 0xf}, 1442 | #endif 1443 | #if defined(PINMUX_PC30I_CAN1_RX) && !defined(IGNORE_PIN_PC30) 1444 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 1, PINMUX_PC30I_CAN1_RX & 0xf}, 1445 | #endif 1446 | #if defined(PINMUX_PC31I_CAN1_RX) && !defined(IGNORE_PIN_PC31) 1447 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 1, PINMUX_PC31I_CAN1_RX & 0xf}, 1448 | #endif 1449 | #if defined(PINMUX_PD00I_CAN1_RX) && !defined(IGNORE_PIN_PD00) 1450 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 1, PINMUX_PD00I_CAN1_RX & 0xf}, 1451 | #endif 1452 | #if defined(PINMUX_PD01I_CAN1_RX) && !defined(IGNORE_PIN_PD01) 1453 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 1, PINMUX_PD01I_CAN1_RX & 0xf}, 1454 | #endif 1455 | #if defined(PINMUX_PD02I_CAN1_RX) && !defined(IGNORE_PIN_PD02) 1456 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 1, PINMUX_PD02I_CAN1_RX & 0xf}, 1457 | #endif 1458 | #if defined(PINMUX_PD03I_CAN1_RX) && !defined(IGNORE_PIN_PD03) 1459 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 1, PINMUX_PD03I_CAN1_RX & 0xf}, 1460 | #endif 1461 | #if defined(PINMUX_PD04I_CAN1_RX) && !defined(IGNORE_PIN_PD04) 1462 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 1, PINMUX_PD04I_CAN1_RX & 0xf}, 1463 | #endif 1464 | #if defined(PINMUX_PD05I_CAN1_RX) && !defined(IGNORE_PIN_PD05) 1465 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 1, PINMUX_PD05I_CAN1_RX & 0xf}, 1466 | #endif 1467 | #if defined(PINMUX_PD06I_CAN1_RX) && !defined(IGNORE_PIN_PD06) 1468 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 1, PINMUX_PD06I_CAN1_RX & 0xf}, 1469 | #endif 1470 | #if defined(PINMUX_PD07I_CAN1_RX) && !defined(IGNORE_PIN_PD07) 1471 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 1, PINMUX_PD07I_CAN1_RX & 0xf}, 1472 | #endif 1473 | #if defined(PINMUX_PD08I_CAN1_RX) && !defined(IGNORE_PIN_PD08) 1474 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 1, PINMUX_PD08I_CAN1_RX & 0xf}, 1475 | #endif 1476 | #if defined(PINMUX_PD09I_CAN1_RX) && !defined(IGNORE_PIN_PD09) 1477 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 1, PINMUX_PD09I_CAN1_RX & 0xf}, 1478 | #endif 1479 | #if defined(PINMUX_PD10I_CAN1_RX) && !defined(IGNORE_PIN_PD10) 1480 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 1, PINMUX_PD10I_CAN1_RX & 0xf}, 1481 | #endif 1482 | #if defined(PINMUX_PD11I_CAN1_RX) && !defined(IGNORE_PIN_PD11) 1483 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 1, PINMUX_PD11I_CAN1_RX & 0xf}, 1484 | #endif 1485 | #if defined(PINMUX_PD12I_CAN1_RX) && !defined(IGNORE_PIN_PD12) 1486 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 1, PINMUX_PD12I_CAN1_RX & 0xf}, 1487 | #endif 1488 | #if defined(PINMUX_PD13I_CAN1_RX) && !defined(IGNORE_PIN_PD13) 1489 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 1, PINMUX_PD13I_CAN1_RX & 0xf}, 1490 | #endif 1491 | #if defined(PINMUX_PD14I_CAN1_RX) && !defined(IGNORE_PIN_PD14) 1492 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 1, PINMUX_PD14I_CAN1_RX & 0xf}, 1493 | #endif 1494 | #if defined(PINMUX_PD15I_CAN1_RX) && !defined(IGNORE_PIN_PD15) 1495 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 1, PINMUX_PD15I_CAN1_RX & 0xf}, 1496 | #endif 1497 | #if defined(PINMUX_PD16I_CAN1_RX) && !defined(IGNORE_PIN_PD16) 1498 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 1, PINMUX_PD16I_CAN1_RX & 0xf}, 1499 | #endif 1500 | #if defined(PINMUX_PD17I_CAN1_RX) && !defined(IGNORE_PIN_PD17) 1501 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 1, PINMUX_PD17I_CAN1_RX & 0xf}, 1502 | #endif 1503 | #if defined(PINMUX_PD18I_CAN1_RX) && !defined(IGNORE_PIN_PD18) 1504 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 1, PINMUX_PD18I_CAN1_RX & 0xf}, 1505 | #endif 1506 | #if defined(PINMUX_PD19I_CAN1_RX) && !defined(IGNORE_PIN_PD19) 1507 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 1, PINMUX_PD19I_CAN1_RX & 0xf}, 1508 | #endif 1509 | #if defined(PINMUX_PD20I_CAN1_RX) && !defined(IGNORE_PIN_PD20) 1510 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 1, PINMUX_PD20I_CAN1_RX & 0xf}, 1511 | #endif 1512 | #if defined(PINMUX_PD21I_CAN1_RX) && !defined(IGNORE_PIN_PD21) 1513 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 1, PINMUX_PD21I_CAN1_RX & 0xf}, 1514 | #endif 1515 | #if defined(PINMUX_PD22I_CAN1_RX) && !defined(IGNORE_PIN_PD22) 1516 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 1, PINMUX_PD22I_CAN1_RX & 0xf}, 1517 | #endif 1518 | #if defined(PINMUX_PD23I_CAN1_RX) && !defined(IGNORE_PIN_PD23) 1519 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 1, PINMUX_PD23I_CAN1_RX & 0xf}, 1520 | #endif 1521 | #if defined(PINMUX_PD24I_CAN1_RX) && !defined(IGNORE_PIN_PD24) 1522 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 1, PINMUX_PD24I_CAN1_RX & 0xf}, 1523 | #endif 1524 | #if defined(PINMUX_PD25I_CAN1_RX) && !defined(IGNORE_PIN_PD25) 1525 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 1, PINMUX_PD25I_CAN1_RX & 0xf}, 1526 | #endif 1527 | #if defined(PINMUX_PD26I_CAN1_RX) && !defined(IGNORE_PIN_PD26) 1528 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 1, PINMUX_PD26I_CAN1_RX & 0xf}, 1529 | #endif 1530 | #if defined(PINMUX_PD27I_CAN1_RX) && !defined(IGNORE_PIN_PD27) 1531 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 1, PINMUX_PD27I_CAN1_RX & 0xf}, 1532 | #endif 1533 | #if defined(PINMUX_PD28I_CAN1_RX) && !defined(IGNORE_PIN_PD28) 1534 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 1, PINMUX_PD28I_CAN1_RX & 0xf}, 1535 | #endif 1536 | #if defined(PINMUX_PD29I_CAN1_RX) && !defined(IGNORE_PIN_PD29) 1537 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 1, PINMUX_PD29I_CAN1_RX & 0xf}, 1538 | #endif 1539 | #if defined(PINMUX_PD30I_CAN1_RX) && !defined(IGNORE_PIN_PD30) 1540 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 1, PINMUX_PD30I_CAN1_RX & 0xf}, 1541 | #endif 1542 | #if defined(PINMUX_PD31I_CAN1_RX) && !defined(IGNORE_PIN_PD31) 1543 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 1, PINMUX_PD31I_CAN1_RX & 0xf}, 1544 | #endif 1545 | }; 1546 | 1547 | const can_function can_tx[] = { 1548 | #if defined(PINMUX_PA00H_CAN0_TX) && !defined(IGNORE_PIN_PA00) 1549 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 0, PINMUX_PA00H_CAN0_TX & 0xf}, 1550 | #endif 1551 | #if defined(PINMUX_PA01H_CAN0_TX) && !defined(IGNORE_PIN_PA01) 1552 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 0, PINMUX_PA01H_CAN0_TX & 0xf}, 1553 | #endif 1554 | #if defined(PINMUX_PA02H_CAN0_TX) && !defined(IGNORE_PIN_PA02) 1555 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 0, PINMUX_PA02H_CAN0_TX & 0xf}, 1556 | #endif 1557 | #if defined(PINMUX_PA03H_CAN0_TX) && !defined(IGNORE_PIN_PA03) 1558 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 0, PINMUX_PA03H_CAN0_TX & 0xf}, 1559 | #endif 1560 | #if defined(PINMUX_PA04H_CAN0_TX) && !defined(IGNORE_PIN_PA04) 1561 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 0, PINMUX_PA04H_CAN0_TX & 0xf}, 1562 | #endif 1563 | #if defined(PINMUX_PA05H_CAN0_TX) && !defined(IGNORE_PIN_PA05) 1564 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 0, PINMUX_PA05H_CAN0_TX & 0xf}, 1565 | #endif 1566 | #if defined(PINMUX_PA06H_CAN0_TX) && !defined(IGNORE_PIN_PA06) 1567 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 0, PINMUX_PA06H_CAN0_TX & 0xf}, 1568 | #endif 1569 | #if defined(PINMUX_PA07H_CAN0_TX) && !defined(IGNORE_PIN_PA07) 1570 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 0, PINMUX_PA07H_CAN0_TX & 0xf}, 1571 | #endif 1572 | #if defined(PINMUX_PA08H_CAN0_TX) && !defined(IGNORE_PIN_PA08) 1573 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 0, PINMUX_PA08H_CAN0_TX & 0xf}, 1574 | #endif 1575 | #if defined(PINMUX_PA09H_CAN0_TX) && !defined(IGNORE_PIN_PA09) 1576 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 0, PINMUX_PA09H_CAN0_TX & 0xf}, 1577 | #endif 1578 | #if defined(PINMUX_PA10H_CAN0_TX) && !defined(IGNORE_PIN_PA10) 1579 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 0, PINMUX_PA10H_CAN0_TX & 0xf}, 1580 | #endif 1581 | #if defined(PINMUX_PA11H_CAN0_TX) && !defined(IGNORE_PIN_PA11) 1582 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 0, PINMUX_PA11H_CAN0_TX & 0xf}, 1583 | #endif 1584 | #if defined(PINMUX_PA12H_CAN0_TX) && !defined(IGNORE_PIN_PA12) 1585 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 0, PINMUX_PA12H_CAN0_TX & 0xf}, 1586 | #endif 1587 | #if defined(PINMUX_PA13H_CAN0_TX) && !defined(IGNORE_PIN_PA13) 1588 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 0, PINMUX_PA13H_CAN0_TX & 0xf}, 1589 | #endif 1590 | #if defined(PINMUX_PA14H_CAN0_TX) && !defined(IGNORE_PIN_PA14) 1591 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 0, PINMUX_PA14H_CAN0_TX & 0xf}, 1592 | #endif 1593 | #if defined(PINMUX_PA15H_CAN0_TX) && !defined(IGNORE_PIN_PA15) 1594 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 0, PINMUX_PA15H_CAN0_TX & 0xf}, 1595 | #endif 1596 | #if defined(PINMUX_PA16H_CAN0_TX) && !defined(IGNORE_PIN_PA16) 1597 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 0, PINMUX_PA16H_CAN0_TX & 0xf}, 1598 | #endif 1599 | #if defined(PINMUX_PA17H_CAN0_TX) && !defined(IGNORE_PIN_PA17) 1600 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 0, PINMUX_PA17H_CAN0_TX & 0xf}, 1601 | #endif 1602 | #if defined(PINMUX_PA18H_CAN0_TX) && !defined(IGNORE_PIN_PA18) 1603 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 0, PINMUX_PA18H_CAN0_TX & 0xf}, 1604 | #endif 1605 | #if defined(PINMUX_PA19H_CAN0_TX) && !defined(IGNORE_PIN_PA19) 1606 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 0, PINMUX_PA19H_CAN0_TX & 0xf}, 1607 | #endif 1608 | #if defined(PINMUX_PA20H_CAN0_TX) && !defined(IGNORE_PIN_PA20) 1609 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 0, PINMUX_PA20H_CAN0_TX & 0xf}, 1610 | #endif 1611 | #if defined(PINMUX_PA21H_CAN0_TX) && !defined(IGNORE_PIN_PA21) 1612 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 0, PINMUX_PA21H_CAN0_TX & 0xf}, 1613 | #endif 1614 | #if defined(PINMUX_PA22H_CAN0_TX) && !defined(IGNORE_PIN_PA22) 1615 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 0, PINMUX_PA22H_CAN0_TX & 0xf}, 1616 | #endif 1617 | #if defined(PINMUX_PA23H_CAN0_TX) && !defined(IGNORE_PIN_PA23) 1618 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 0, PINMUX_PA23H_CAN0_TX & 0xf}, 1619 | #endif 1620 | #if defined(PINMUX_PA24H_CAN0_TX) && !defined(IGNORE_PIN_PA24) 1621 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 0, PINMUX_PA24H_CAN0_TX & 0xf}, 1622 | #endif 1623 | #if defined(PINMUX_PA25H_CAN0_TX) && !defined(IGNORE_PIN_PA25) 1624 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 0, PINMUX_PA25H_CAN0_TX & 0xf}, 1625 | #endif 1626 | #if defined(PINMUX_PA26H_CAN0_TX) && !defined(IGNORE_PIN_PA26) 1627 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 0, PINMUX_PA26H_CAN0_TX & 0xf}, 1628 | #endif 1629 | #if defined(PINMUX_PA27H_CAN0_TX) && !defined(IGNORE_PIN_PA27) 1630 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 0, PINMUX_PA27H_CAN0_TX & 0xf}, 1631 | #endif 1632 | #if defined(PINMUX_PA28H_CAN0_TX) && !defined(IGNORE_PIN_PA28) 1633 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 0, PINMUX_PA28H_CAN0_TX & 0xf}, 1634 | #endif 1635 | #if defined(PINMUX_PA29H_CAN0_TX) && !defined(IGNORE_PIN_PA29) 1636 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 0, PINMUX_PA29H_CAN0_TX & 0xf}, 1637 | #endif 1638 | #if defined(PINMUX_PA30H_CAN0_TX) && !defined(IGNORE_PIN_PA30) 1639 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 0, PINMUX_PA30H_CAN0_TX & 0xf}, 1640 | #endif 1641 | #if defined(PINMUX_PA31H_CAN0_TX) && !defined(IGNORE_PIN_PA31) 1642 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 0, PINMUX_PA31H_CAN0_TX & 0xf}, 1643 | #endif 1644 | #if defined(PINMUX_PB00H_CAN0_TX) && !defined(IGNORE_PIN_PB00) 1645 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 0, PINMUX_PB00H_CAN0_TX & 0xf}, 1646 | #endif 1647 | #if defined(PINMUX_PB01H_CAN0_TX) && !defined(IGNORE_PIN_PB01) 1648 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 0, PINMUX_PB01H_CAN0_TX & 0xf}, 1649 | #endif 1650 | #if defined(PINMUX_PB02H_CAN0_TX) && !defined(IGNORE_PIN_PB02) 1651 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 0, PINMUX_PB02H_CAN0_TX & 0xf}, 1652 | #endif 1653 | #if defined(PINMUX_PB03H_CAN0_TX) && !defined(IGNORE_PIN_PB03) 1654 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 0, PINMUX_PB03H_CAN0_TX & 0xf}, 1655 | #endif 1656 | #if defined(PINMUX_PB04H_CAN0_TX) && !defined(IGNORE_PIN_PB04) 1657 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 0, PINMUX_PB04H_CAN0_TX & 0xf}, 1658 | #endif 1659 | #if defined(PINMUX_PB05H_CAN0_TX) && !defined(IGNORE_PIN_PB05) 1660 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 0, PINMUX_PB05H_CAN0_TX & 0xf}, 1661 | #endif 1662 | #if defined(PINMUX_PB06H_CAN0_TX) && !defined(IGNORE_PIN_PB06) 1663 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 0, PINMUX_PB06H_CAN0_TX & 0xf}, 1664 | #endif 1665 | #if defined(PINMUX_PB07H_CAN0_TX) && !defined(IGNORE_PIN_PB07) 1666 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 0, PINMUX_PB07H_CAN0_TX & 0xf}, 1667 | #endif 1668 | #if defined(PINMUX_PB08H_CAN0_TX) && !defined(IGNORE_PIN_PB08) 1669 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 0, PINMUX_PB08H_CAN0_TX & 0xf}, 1670 | #endif 1671 | #if defined(PINMUX_PB09H_CAN0_TX) && !defined(IGNORE_PIN_PB09) 1672 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 0, PINMUX_PB09H_CAN0_TX & 0xf}, 1673 | #endif 1674 | #if defined(PINMUX_PB10H_CAN0_TX) && !defined(IGNORE_PIN_PB10) 1675 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 0, PINMUX_PB10H_CAN0_TX & 0xf}, 1676 | #endif 1677 | #if defined(PINMUX_PB11H_CAN0_TX) && !defined(IGNORE_PIN_PB11) 1678 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 0, PINMUX_PB11H_CAN0_TX & 0xf}, 1679 | #endif 1680 | #if defined(PINMUX_PB12H_CAN0_TX) && !defined(IGNORE_PIN_PB12) 1681 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 0, PINMUX_PB12H_CAN0_TX & 0xf}, 1682 | #endif 1683 | #if defined(PINMUX_PB13H_CAN0_TX) && !defined(IGNORE_PIN_PB13) 1684 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 0, PINMUX_PB13H_CAN0_TX & 0xf}, 1685 | #endif 1686 | #if defined(PINMUX_PB14H_CAN0_TX) && !defined(IGNORE_PIN_PB14) 1687 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 0, PINMUX_PB14H_CAN0_TX & 0xf}, 1688 | #endif 1689 | #if defined(PINMUX_PB15H_CAN0_TX) && !defined(IGNORE_PIN_PB15) 1690 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 0, PINMUX_PB15H_CAN0_TX & 0xf}, 1691 | #endif 1692 | #if defined(PINMUX_PB16H_CAN0_TX) && !defined(IGNORE_PIN_PB16) 1693 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 0, PINMUX_PB16H_CAN0_TX & 0xf}, 1694 | #endif 1695 | #if defined(PINMUX_PB17H_CAN0_TX) && !defined(IGNORE_PIN_PB17) 1696 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 0, PINMUX_PB17H_CAN0_TX & 0xf}, 1697 | #endif 1698 | #if defined(PINMUX_PB18H_CAN0_TX) && !defined(IGNORE_PIN_PB18) 1699 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 0, PINMUX_PB18H_CAN0_TX & 0xf}, 1700 | #endif 1701 | #if defined(PINMUX_PB19H_CAN0_TX) && !defined(IGNORE_PIN_PB19) 1702 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 0, PINMUX_PB19H_CAN0_TX & 0xf}, 1703 | #endif 1704 | #if defined(PINMUX_PB20H_CAN0_TX) && !defined(IGNORE_PIN_PB20) 1705 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 0, PINMUX_PB20H_CAN0_TX & 0xf}, 1706 | #endif 1707 | #if defined(PINMUX_PB21H_CAN0_TX) && !defined(IGNORE_PIN_PB21) 1708 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 0, PINMUX_PB21H_CAN0_TX & 0xf}, 1709 | #endif 1710 | #if defined(PINMUX_PB22H_CAN0_TX) && !defined(IGNORE_PIN_PB22) 1711 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 0, PINMUX_PB22H_CAN0_TX & 0xf}, 1712 | #endif 1713 | #if defined(PINMUX_PB23H_CAN0_TX) && !defined(IGNORE_PIN_PB23) 1714 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 0, PINMUX_PB23H_CAN0_TX & 0xf}, 1715 | #endif 1716 | #if defined(PINMUX_PB24H_CAN0_TX) && !defined(IGNORE_PIN_PB24) 1717 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 0, PINMUX_PB24H_CAN0_TX & 0xf}, 1718 | #endif 1719 | #if defined(PINMUX_PB25H_CAN0_TX) && !defined(IGNORE_PIN_PB25) 1720 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 0, PINMUX_PB25H_CAN0_TX & 0xf}, 1721 | #endif 1722 | #if defined(PINMUX_PB26H_CAN0_TX) && !defined(IGNORE_PIN_PB26) 1723 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 0, PINMUX_PB26H_CAN0_TX & 0xf}, 1724 | #endif 1725 | #if defined(PINMUX_PB27H_CAN0_TX) && !defined(IGNORE_PIN_PB27) 1726 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 0, PINMUX_PB27H_CAN0_TX & 0xf}, 1727 | #endif 1728 | #if defined(PINMUX_PB28H_CAN0_TX) && !defined(IGNORE_PIN_PB28) 1729 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 0, PINMUX_PB28H_CAN0_TX & 0xf}, 1730 | #endif 1731 | #if defined(PINMUX_PB29H_CAN0_TX) && !defined(IGNORE_PIN_PB29) 1732 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 0, PINMUX_PB29H_CAN0_TX & 0xf}, 1733 | #endif 1734 | #if defined(PINMUX_PB30H_CAN0_TX) && !defined(IGNORE_PIN_PB30) 1735 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 0, PINMUX_PB30H_CAN0_TX & 0xf}, 1736 | #endif 1737 | #if defined(PINMUX_PB31H_CAN0_TX) && !defined(IGNORE_PIN_PB31) 1738 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 0, PINMUX_PB31H_CAN0_TX & 0xf}, 1739 | #endif 1740 | #if defined(PINMUX_PC00H_CAN0_TX) && !defined(IGNORE_PIN_PC00) 1741 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 0, PINMUX_PC00H_CAN0_TX & 0xf}, 1742 | #endif 1743 | #if defined(PINMUX_PC01H_CAN0_TX) && !defined(IGNORE_PIN_PC01) 1744 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 0, PINMUX_PC01H_CAN0_TX & 0xf}, 1745 | #endif 1746 | #if defined(PINMUX_PC02H_CAN0_TX) && !defined(IGNORE_PIN_PC02) 1747 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 0, PINMUX_PC02H_CAN0_TX & 0xf}, 1748 | #endif 1749 | #if defined(PINMUX_PC03H_CAN0_TX) && !defined(IGNORE_PIN_PC03) 1750 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 0, PINMUX_PC03H_CAN0_TX & 0xf}, 1751 | #endif 1752 | #if defined(PINMUX_PC04H_CAN0_TX) && !defined(IGNORE_PIN_PC04) 1753 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 0, PINMUX_PC04H_CAN0_TX & 0xf}, 1754 | #endif 1755 | #if defined(PINMUX_PC05H_CAN0_TX) && !defined(IGNORE_PIN_PC05) 1756 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 0, PINMUX_PC05H_CAN0_TX & 0xf}, 1757 | #endif 1758 | #if defined(PINMUX_PC06H_CAN0_TX) && !defined(IGNORE_PIN_PC06) 1759 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 0, PINMUX_PC06H_CAN0_TX & 0xf}, 1760 | #endif 1761 | #if defined(PINMUX_PC07H_CAN0_TX) && !defined(IGNORE_PIN_PC07) 1762 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 0, PINMUX_PC07H_CAN0_TX & 0xf}, 1763 | #endif 1764 | #if defined(PINMUX_PC08H_CAN0_TX) && !defined(IGNORE_PIN_PC08) 1765 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 0, PINMUX_PC08H_CAN0_TX & 0xf}, 1766 | #endif 1767 | #if defined(PINMUX_PC09H_CAN0_TX) && !defined(IGNORE_PIN_PC09) 1768 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 0, PINMUX_PC09H_CAN0_TX & 0xf}, 1769 | #endif 1770 | #if defined(PINMUX_PC10H_CAN0_TX) && !defined(IGNORE_PIN_PC10) 1771 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 0, PINMUX_PC10H_CAN0_TX & 0xf}, 1772 | #endif 1773 | #if defined(PINMUX_PC11H_CAN0_TX) && !defined(IGNORE_PIN_PC11) 1774 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 0, PINMUX_PC11H_CAN0_TX & 0xf}, 1775 | #endif 1776 | #if defined(PINMUX_PC12H_CAN0_TX) && !defined(IGNORE_PIN_PC12) 1777 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 0, PINMUX_PC12H_CAN0_TX & 0xf}, 1778 | #endif 1779 | #if defined(PINMUX_PC13H_CAN0_TX) && !defined(IGNORE_PIN_PC13) 1780 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 0, PINMUX_PC13H_CAN0_TX & 0xf}, 1781 | #endif 1782 | #if defined(PINMUX_PC14H_CAN0_TX) && !defined(IGNORE_PIN_PC14) 1783 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 0, PINMUX_PC14H_CAN0_TX & 0xf}, 1784 | #endif 1785 | #if defined(PINMUX_PC15H_CAN0_TX) && !defined(IGNORE_PIN_PC15) 1786 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 0, PINMUX_PC15H_CAN0_TX & 0xf}, 1787 | #endif 1788 | #if defined(PINMUX_PC16H_CAN0_TX) && !defined(IGNORE_PIN_PC16) 1789 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 0, PINMUX_PC16H_CAN0_TX & 0xf}, 1790 | #endif 1791 | #if defined(PINMUX_PC17H_CAN0_TX) && !defined(IGNORE_PIN_PC17) 1792 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 0, PINMUX_PC17H_CAN0_TX & 0xf}, 1793 | #endif 1794 | #if defined(PINMUX_PC18H_CAN0_TX) && !defined(IGNORE_PIN_PC18) 1795 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 0, PINMUX_PC18H_CAN0_TX & 0xf}, 1796 | #endif 1797 | #if defined(PINMUX_PC19H_CAN0_TX) && !defined(IGNORE_PIN_PC19) 1798 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 0, PINMUX_PC19H_CAN0_TX & 0xf}, 1799 | #endif 1800 | #if defined(PINMUX_PC20H_CAN0_TX) && !defined(IGNORE_PIN_PC20) 1801 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 0, PINMUX_PC20H_CAN0_TX & 0xf}, 1802 | #endif 1803 | #if defined(PINMUX_PC21H_CAN0_TX) && !defined(IGNORE_PIN_PC21) 1804 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 0, PINMUX_PC21H_CAN0_TX & 0xf}, 1805 | #endif 1806 | #if defined(PINMUX_PC22H_CAN0_TX) && !defined(IGNORE_PIN_PC22) 1807 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 0, PINMUX_PC22H_CAN0_TX & 0xf}, 1808 | #endif 1809 | #if defined(PINMUX_PC23H_CAN0_TX) && !defined(IGNORE_PIN_PC23) 1810 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 0, PINMUX_PC23H_CAN0_TX & 0xf}, 1811 | #endif 1812 | #if defined(PINMUX_PC24H_CAN0_TX) && !defined(IGNORE_PIN_PC24) 1813 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 0, PINMUX_PC24H_CAN0_TX & 0xf}, 1814 | #endif 1815 | #if defined(PINMUX_PC25H_CAN0_TX) && !defined(IGNORE_PIN_PC25) 1816 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 0, PINMUX_PC25H_CAN0_TX & 0xf}, 1817 | #endif 1818 | #if defined(PINMUX_PC26H_CAN0_TX) && !defined(IGNORE_PIN_PC26) 1819 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 0, PINMUX_PC26H_CAN0_TX & 0xf}, 1820 | #endif 1821 | #if defined(PINMUX_PC27H_CAN0_TX) && !defined(IGNORE_PIN_PC27) 1822 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 0, PINMUX_PC27H_CAN0_TX & 0xf}, 1823 | #endif 1824 | #if defined(PINMUX_PC28H_CAN0_TX) && !defined(IGNORE_PIN_PC28) 1825 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 0, PINMUX_PC28H_CAN0_TX & 0xf}, 1826 | #endif 1827 | #if defined(PINMUX_PC29H_CAN0_TX) && !defined(IGNORE_PIN_PC29) 1828 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 0, PINMUX_PC29H_CAN0_TX & 0xf}, 1829 | #endif 1830 | #if defined(PINMUX_PC30H_CAN0_TX) && !defined(IGNORE_PIN_PC30) 1831 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 0, PINMUX_PC30H_CAN0_TX & 0xf}, 1832 | #endif 1833 | #if defined(PINMUX_PC31H_CAN0_TX) && !defined(IGNORE_PIN_PC31) 1834 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 0, PINMUX_PC31H_CAN0_TX & 0xf}, 1835 | #endif 1836 | #if defined(PINMUX_PD00H_CAN0_TX) && !defined(IGNORE_PIN_PD00) 1837 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 0, PINMUX_PD00H_CAN0_TX & 0xf}, 1838 | #endif 1839 | #if defined(PINMUX_PD01H_CAN0_TX) && !defined(IGNORE_PIN_PD01) 1840 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 0, PINMUX_PD01H_CAN0_TX & 0xf}, 1841 | #endif 1842 | #if defined(PINMUX_PD02H_CAN0_TX) && !defined(IGNORE_PIN_PD02) 1843 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 0, PINMUX_PD02H_CAN0_TX & 0xf}, 1844 | #endif 1845 | #if defined(PINMUX_PD03H_CAN0_TX) && !defined(IGNORE_PIN_PD03) 1846 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 0, PINMUX_PD03H_CAN0_TX & 0xf}, 1847 | #endif 1848 | #if defined(PINMUX_PD04H_CAN0_TX) && !defined(IGNORE_PIN_PD04) 1849 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 0, PINMUX_PD04H_CAN0_TX & 0xf}, 1850 | #endif 1851 | #if defined(PINMUX_PD05H_CAN0_TX) && !defined(IGNORE_PIN_PD05) 1852 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 0, PINMUX_PD05H_CAN0_TX & 0xf}, 1853 | #endif 1854 | #if defined(PINMUX_PD06H_CAN0_TX) && !defined(IGNORE_PIN_PD06) 1855 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 0, PINMUX_PD06H_CAN0_TX & 0xf}, 1856 | #endif 1857 | #if defined(PINMUX_PD07H_CAN0_TX) && !defined(IGNORE_PIN_PD07) 1858 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 0, PINMUX_PD07H_CAN0_TX & 0xf}, 1859 | #endif 1860 | #if defined(PINMUX_PD08H_CAN0_TX) && !defined(IGNORE_PIN_PD08) 1861 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 0, PINMUX_PD08H_CAN0_TX & 0xf}, 1862 | #endif 1863 | #if defined(PINMUX_PD09H_CAN0_TX) && !defined(IGNORE_PIN_PD09) 1864 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 0, PINMUX_PD09H_CAN0_TX & 0xf}, 1865 | #endif 1866 | #if defined(PINMUX_PD10H_CAN0_TX) && !defined(IGNORE_PIN_PD10) 1867 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 0, PINMUX_PD10H_CAN0_TX & 0xf}, 1868 | #endif 1869 | #if defined(PINMUX_PD11H_CAN0_TX) && !defined(IGNORE_PIN_PD11) 1870 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 0, PINMUX_PD11H_CAN0_TX & 0xf}, 1871 | #endif 1872 | #if defined(PINMUX_PD12H_CAN0_TX) && !defined(IGNORE_PIN_PD12) 1873 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 0, PINMUX_PD12H_CAN0_TX & 0xf}, 1874 | #endif 1875 | #if defined(PINMUX_PD13H_CAN0_TX) && !defined(IGNORE_PIN_PD13) 1876 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 0, PINMUX_PD13H_CAN0_TX & 0xf}, 1877 | #endif 1878 | #if defined(PINMUX_PD14H_CAN0_TX) && !defined(IGNORE_PIN_PD14) 1879 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 0, PINMUX_PD14H_CAN0_TX & 0xf}, 1880 | #endif 1881 | #if defined(PINMUX_PD15H_CAN0_TX) && !defined(IGNORE_PIN_PD15) 1882 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 0, PINMUX_PD15H_CAN0_TX & 0xf}, 1883 | #endif 1884 | #if defined(PINMUX_PD16H_CAN0_TX) && !defined(IGNORE_PIN_PD16) 1885 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 0, PINMUX_PD16H_CAN0_TX & 0xf}, 1886 | #endif 1887 | #if defined(PINMUX_PD17H_CAN0_TX) && !defined(IGNORE_PIN_PD17) 1888 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 0, PINMUX_PD17H_CAN0_TX & 0xf}, 1889 | #endif 1890 | #if defined(PINMUX_PD18H_CAN0_TX) && !defined(IGNORE_PIN_PD18) 1891 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 0, PINMUX_PD18H_CAN0_TX & 0xf}, 1892 | #endif 1893 | #if defined(PINMUX_PD19H_CAN0_TX) && !defined(IGNORE_PIN_PD19) 1894 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 0, PINMUX_PD19H_CAN0_TX & 0xf}, 1895 | #endif 1896 | #if defined(PINMUX_PD20H_CAN0_TX) && !defined(IGNORE_PIN_PD20) 1897 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 0, PINMUX_PD20H_CAN0_TX & 0xf}, 1898 | #endif 1899 | #if defined(PINMUX_PD21H_CAN0_TX) && !defined(IGNORE_PIN_PD21) 1900 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 0, PINMUX_PD21H_CAN0_TX & 0xf}, 1901 | #endif 1902 | #if defined(PINMUX_PD22H_CAN0_TX) && !defined(IGNORE_PIN_PD22) 1903 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 0, PINMUX_PD22H_CAN0_TX & 0xf}, 1904 | #endif 1905 | #if defined(PINMUX_PD23H_CAN0_TX) && !defined(IGNORE_PIN_PD23) 1906 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 0, PINMUX_PD23H_CAN0_TX & 0xf}, 1907 | #endif 1908 | #if defined(PINMUX_PD24H_CAN0_TX) && !defined(IGNORE_PIN_PD24) 1909 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 0, PINMUX_PD24H_CAN0_TX & 0xf}, 1910 | #endif 1911 | #if defined(PINMUX_PD25H_CAN0_TX) && !defined(IGNORE_PIN_PD25) 1912 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 0, PINMUX_PD25H_CAN0_TX & 0xf}, 1913 | #endif 1914 | #if defined(PINMUX_PD26H_CAN0_TX) && !defined(IGNORE_PIN_PD26) 1915 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 0, PINMUX_PD26H_CAN0_TX & 0xf}, 1916 | #endif 1917 | #if defined(PINMUX_PD27H_CAN0_TX) && !defined(IGNORE_PIN_PD27) 1918 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 0, PINMUX_PD27H_CAN0_TX & 0xf}, 1919 | #endif 1920 | #if defined(PINMUX_PD28H_CAN0_TX) && !defined(IGNORE_PIN_PD28) 1921 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 0, PINMUX_PD28H_CAN0_TX & 0xf}, 1922 | #endif 1923 | #if defined(PINMUX_PD29H_CAN0_TX) && !defined(IGNORE_PIN_PD29) 1924 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 0, PINMUX_PD29H_CAN0_TX & 0xf}, 1925 | #endif 1926 | #if defined(PINMUX_PD30H_CAN0_TX) && !defined(IGNORE_PIN_PD30) 1927 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 0, PINMUX_PD30H_CAN0_TX & 0xf}, 1928 | #endif 1929 | #if defined(PINMUX_PD31H_CAN0_TX) && !defined(IGNORE_PIN_PD31) 1930 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 0, PINMUX_PD31H_CAN0_TX & 0xf}, 1931 | #endif 1932 | #if defined(PINMUX_PA00I_CAN0_TX) && !defined(IGNORE_PIN_PA00) 1933 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 0, PINMUX_PA00I_CAN0_TX & 0xf}, 1934 | #endif 1935 | #if defined(PINMUX_PA01I_CAN0_TX) && !defined(IGNORE_PIN_PA01) 1936 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 0, PINMUX_PA01I_CAN0_TX & 0xf}, 1937 | #endif 1938 | #if defined(PINMUX_PA02I_CAN0_TX) && !defined(IGNORE_PIN_PA02) 1939 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 0, PINMUX_PA02I_CAN0_TX & 0xf}, 1940 | #endif 1941 | #if defined(PINMUX_PA03I_CAN0_TX) && !defined(IGNORE_PIN_PA03) 1942 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 0, PINMUX_PA03I_CAN0_TX & 0xf}, 1943 | #endif 1944 | #if defined(PINMUX_PA04I_CAN0_TX) && !defined(IGNORE_PIN_PA04) 1945 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 0, PINMUX_PA04I_CAN0_TX & 0xf}, 1946 | #endif 1947 | #if defined(PINMUX_PA05I_CAN0_TX) && !defined(IGNORE_PIN_PA05) 1948 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 0, PINMUX_PA05I_CAN0_TX & 0xf}, 1949 | #endif 1950 | #if defined(PINMUX_PA06I_CAN0_TX) && !defined(IGNORE_PIN_PA06) 1951 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 0, PINMUX_PA06I_CAN0_TX & 0xf}, 1952 | #endif 1953 | #if defined(PINMUX_PA07I_CAN0_TX) && !defined(IGNORE_PIN_PA07) 1954 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 0, PINMUX_PA07I_CAN0_TX & 0xf}, 1955 | #endif 1956 | #if defined(PINMUX_PA08I_CAN0_TX) && !defined(IGNORE_PIN_PA08) 1957 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 0, PINMUX_PA08I_CAN0_TX & 0xf}, 1958 | #endif 1959 | #if defined(PINMUX_PA09I_CAN0_TX) && !defined(IGNORE_PIN_PA09) 1960 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 0, PINMUX_PA09I_CAN0_TX & 0xf}, 1961 | #endif 1962 | #if defined(PINMUX_PA10I_CAN0_TX) && !defined(IGNORE_PIN_PA10) 1963 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 0, PINMUX_PA10I_CAN0_TX & 0xf}, 1964 | #endif 1965 | #if defined(PINMUX_PA11I_CAN0_TX) && !defined(IGNORE_PIN_PA11) 1966 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 0, PINMUX_PA11I_CAN0_TX & 0xf}, 1967 | #endif 1968 | #if defined(PINMUX_PA12I_CAN0_TX) && !defined(IGNORE_PIN_PA12) 1969 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 0, PINMUX_PA12I_CAN0_TX & 0xf}, 1970 | #endif 1971 | #if defined(PINMUX_PA13I_CAN0_TX) && !defined(IGNORE_PIN_PA13) 1972 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 0, PINMUX_PA13I_CAN0_TX & 0xf}, 1973 | #endif 1974 | #if defined(PINMUX_PA14I_CAN0_TX) && !defined(IGNORE_PIN_PA14) 1975 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 0, PINMUX_PA14I_CAN0_TX & 0xf}, 1976 | #endif 1977 | #if defined(PINMUX_PA15I_CAN0_TX) && !defined(IGNORE_PIN_PA15) 1978 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 0, PINMUX_PA15I_CAN0_TX & 0xf}, 1979 | #endif 1980 | #if defined(PINMUX_PA16I_CAN0_TX) && !defined(IGNORE_PIN_PA16) 1981 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 0, PINMUX_PA16I_CAN0_TX & 0xf}, 1982 | #endif 1983 | #if defined(PINMUX_PA17I_CAN0_TX) && !defined(IGNORE_PIN_PA17) 1984 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 0, PINMUX_PA17I_CAN0_TX & 0xf}, 1985 | #endif 1986 | #if defined(PINMUX_PA18I_CAN0_TX) && !defined(IGNORE_PIN_PA18) 1987 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 0, PINMUX_PA18I_CAN0_TX & 0xf}, 1988 | #endif 1989 | #if defined(PINMUX_PA19I_CAN0_TX) && !defined(IGNORE_PIN_PA19) 1990 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 0, PINMUX_PA19I_CAN0_TX & 0xf}, 1991 | #endif 1992 | #if defined(PINMUX_PA20I_CAN0_TX) && !defined(IGNORE_PIN_PA20) 1993 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 0, PINMUX_PA20I_CAN0_TX & 0xf}, 1994 | #endif 1995 | #if defined(PINMUX_PA21I_CAN0_TX) && !defined(IGNORE_PIN_PA21) 1996 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 0, PINMUX_PA21I_CAN0_TX & 0xf}, 1997 | #endif 1998 | #if defined(PINMUX_PA22I_CAN0_TX) && !defined(IGNORE_PIN_PA22) 1999 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 0, PINMUX_PA22I_CAN0_TX & 0xf}, 2000 | #endif 2001 | #if defined(PINMUX_PA23I_CAN0_TX) && !defined(IGNORE_PIN_PA23) 2002 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 0, PINMUX_PA23I_CAN0_TX & 0xf}, 2003 | #endif 2004 | #if defined(PINMUX_PA24I_CAN0_TX) && !defined(IGNORE_PIN_PA24) 2005 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 0, PINMUX_PA24I_CAN0_TX & 0xf}, 2006 | #endif 2007 | #if defined(PINMUX_PA25I_CAN0_TX) && !defined(IGNORE_PIN_PA25) 2008 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 0, PINMUX_PA25I_CAN0_TX & 0xf}, 2009 | #endif 2010 | #if defined(PINMUX_PA26I_CAN0_TX) && !defined(IGNORE_PIN_PA26) 2011 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 0, PINMUX_PA26I_CAN0_TX & 0xf}, 2012 | #endif 2013 | #if defined(PINMUX_PA27I_CAN0_TX) && !defined(IGNORE_PIN_PA27) 2014 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 0, PINMUX_PA27I_CAN0_TX & 0xf}, 2015 | #endif 2016 | #if defined(PINMUX_PA28I_CAN0_TX) && !defined(IGNORE_PIN_PA28) 2017 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 0, PINMUX_PA28I_CAN0_TX & 0xf}, 2018 | #endif 2019 | #if defined(PINMUX_PA29I_CAN0_TX) && !defined(IGNORE_PIN_PA29) 2020 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 0, PINMUX_PA29I_CAN0_TX & 0xf}, 2021 | #endif 2022 | #if defined(PINMUX_PA30I_CAN0_TX) && !defined(IGNORE_PIN_PA30) 2023 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 0, PINMUX_PA30I_CAN0_TX & 0xf}, 2024 | #endif 2025 | #if defined(PINMUX_PA31I_CAN0_TX) && !defined(IGNORE_PIN_PA31) 2026 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 0, PINMUX_PA31I_CAN0_TX & 0xf}, 2027 | #endif 2028 | #if defined(PINMUX_PB00I_CAN0_TX) && !defined(IGNORE_PIN_PB00) 2029 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 0, PINMUX_PB00I_CAN0_TX & 0xf}, 2030 | #endif 2031 | #if defined(PINMUX_PB01I_CAN0_TX) && !defined(IGNORE_PIN_PB01) 2032 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 0, PINMUX_PB01I_CAN0_TX & 0xf}, 2033 | #endif 2034 | #if defined(PINMUX_PB02I_CAN0_TX) && !defined(IGNORE_PIN_PB02) 2035 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 0, PINMUX_PB02I_CAN0_TX & 0xf}, 2036 | #endif 2037 | #if defined(PINMUX_PB03I_CAN0_TX) && !defined(IGNORE_PIN_PB03) 2038 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 0, PINMUX_PB03I_CAN0_TX & 0xf}, 2039 | #endif 2040 | #if defined(PINMUX_PB04I_CAN0_TX) && !defined(IGNORE_PIN_PB04) 2041 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 0, PINMUX_PB04I_CAN0_TX & 0xf}, 2042 | #endif 2043 | #if defined(PINMUX_PB05I_CAN0_TX) && !defined(IGNORE_PIN_PB05) 2044 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 0, PINMUX_PB05I_CAN0_TX & 0xf}, 2045 | #endif 2046 | #if defined(PINMUX_PB06I_CAN0_TX) && !defined(IGNORE_PIN_PB06) 2047 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 0, PINMUX_PB06I_CAN0_TX & 0xf}, 2048 | #endif 2049 | #if defined(PINMUX_PB07I_CAN0_TX) && !defined(IGNORE_PIN_PB07) 2050 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 0, PINMUX_PB07I_CAN0_TX & 0xf}, 2051 | #endif 2052 | #if defined(PINMUX_PB08I_CAN0_TX) && !defined(IGNORE_PIN_PB08) 2053 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 0, PINMUX_PB08I_CAN0_TX & 0xf}, 2054 | #endif 2055 | #if defined(PINMUX_PB09I_CAN0_TX) && !defined(IGNORE_PIN_PB09) 2056 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 0, PINMUX_PB09I_CAN0_TX & 0xf}, 2057 | #endif 2058 | #if defined(PINMUX_PB10I_CAN0_TX) && !defined(IGNORE_PIN_PB10) 2059 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 0, PINMUX_PB10I_CAN0_TX & 0xf}, 2060 | #endif 2061 | #if defined(PINMUX_PB11I_CAN0_TX) && !defined(IGNORE_PIN_PB11) 2062 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 0, PINMUX_PB11I_CAN0_TX & 0xf}, 2063 | #endif 2064 | #if defined(PINMUX_PB12I_CAN0_TX) && !defined(IGNORE_PIN_PB12) 2065 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 0, PINMUX_PB12I_CAN0_TX & 0xf}, 2066 | #endif 2067 | #if defined(PINMUX_PB13I_CAN0_TX) && !defined(IGNORE_PIN_PB13) 2068 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 0, PINMUX_PB13I_CAN0_TX & 0xf}, 2069 | #endif 2070 | #if defined(PINMUX_PB14I_CAN0_TX) && !defined(IGNORE_PIN_PB14) 2071 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 0, PINMUX_PB14I_CAN0_TX & 0xf}, 2072 | #endif 2073 | #if defined(PINMUX_PB15I_CAN0_TX) && !defined(IGNORE_PIN_PB15) 2074 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 0, PINMUX_PB15I_CAN0_TX & 0xf}, 2075 | #endif 2076 | #if defined(PINMUX_PB16I_CAN0_TX) && !defined(IGNORE_PIN_PB16) 2077 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 0, PINMUX_PB16I_CAN0_TX & 0xf}, 2078 | #endif 2079 | #if defined(PINMUX_PB17I_CAN0_TX) && !defined(IGNORE_PIN_PB17) 2080 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 0, PINMUX_PB17I_CAN0_TX & 0xf}, 2081 | #endif 2082 | #if defined(PINMUX_PB18I_CAN0_TX) && !defined(IGNORE_PIN_PB18) 2083 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 0, PINMUX_PB18I_CAN0_TX & 0xf}, 2084 | #endif 2085 | #if defined(PINMUX_PB19I_CAN0_TX) && !defined(IGNORE_PIN_PB19) 2086 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 0, PINMUX_PB19I_CAN0_TX & 0xf}, 2087 | #endif 2088 | #if defined(PINMUX_PB20I_CAN0_TX) && !defined(IGNORE_PIN_PB20) 2089 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 0, PINMUX_PB20I_CAN0_TX & 0xf}, 2090 | #endif 2091 | #if defined(PINMUX_PB21I_CAN0_TX) && !defined(IGNORE_PIN_PB21) 2092 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 0, PINMUX_PB21I_CAN0_TX & 0xf}, 2093 | #endif 2094 | #if defined(PINMUX_PB22I_CAN0_TX) && !defined(IGNORE_PIN_PB22) 2095 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 0, PINMUX_PB22I_CAN0_TX & 0xf}, 2096 | #endif 2097 | #if defined(PINMUX_PB23I_CAN0_TX) && !defined(IGNORE_PIN_PB23) 2098 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 0, PINMUX_PB23I_CAN0_TX & 0xf}, 2099 | #endif 2100 | #if defined(PINMUX_PB24I_CAN0_TX) && !defined(IGNORE_PIN_PB24) 2101 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 0, PINMUX_PB24I_CAN0_TX & 0xf}, 2102 | #endif 2103 | #if defined(PINMUX_PB25I_CAN0_TX) && !defined(IGNORE_PIN_PB25) 2104 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 0, PINMUX_PB25I_CAN0_TX & 0xf}, 2105 | #endif 2106 | #if defined(PINMUX_PB26I_CAN0_TX) && !defined(IGNORE_PIN_PB26) 2107 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 0, PINMUX_PB26I_CAN0_TX & 0xf}, 2108 | #endif 2109 | #if defined(PINMUX_PB27I_CAN0_TX) && !defined(IGNORE_PIN_PB27) 2110 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 0, PINMUX_PB27I_CAN0_TX & 0xf}, 2111 | #endif 2112 | #if defined(PINMUX_PB28I_CAN0_TX) && !defined(IGNORE_PIN_PB28) 2113 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 0, PINMUX_PB28I_CAN0_TX & 0xf}, 2114 | #endif 2115 | #if defined(PINMUX_PB29I_CAN0_TX) && !defined(IGNORE_PIN_PB29) 2116 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 0, PINMUX_PB29I_CAN0_TX & 0xf}, 2117 | #endif 2118 | #if defined(PINMUX_PB30I_CAN0_TX) && !defined(IGNORE_PIN_PB30) 2119 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 0, PINMUX_PB30I_CAN0_TX & 0xf}, 2120 | #endif 2121 | #if defined(PINMUX_PB31I_CAN0_TX) && !defined(IGNORE_PIN_PB31) 2122 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 0, PINMUX_PB31I_CAN0_TX & 0xf}, 2123 | #endif 2124 | #if defined(PINMUX_PC00I_CAN0_TX) && !defined(IGNORE_PIN_PC00) 2125 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 0, PINMUX_PC00I_CAN0_TX & 0xf}, 2126 | #endif 2127 | #if defined(PINMUX_PC01I_CAN0_TX) && !defined(IGNORE_PIN_PC01) 2128 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 0, PINMUX_PC01I_CAN0_TX & 0xf}, 2129 | #endif 2130 | #if defined(PINMUX_PC02I_CAN0_TX) && !defined(IGNORE_PIN_PC02) 2131 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 0, PINMUX_PC02I_CAN0_TX & 0xf}, 2132 | #endif 2133 | #if defined(PINMUX_PC03I_CAN0_TX) && !defined(IGNORE_PIN_PC03) 2134 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 0, PINMUX_PC03I_CAN0_TX & 0xf}, 2135 | #endif 2136 | #if defined(PINMUX_PC04I_CAN0_TX) && !defined(IGNORE_PIN_PC04) 2137 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 0, PINMUX_PC04I_CAN0_TX & 0xf}, 2138 | #endif 2139 | #if defined(PINMUX_PC05I_CAN0_TX) && !defined(IGNORE_PIN_PC05) 2140 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 0, PINMUX_PC05I_CAN0_TX & 0xf}, 2141 | #endif 2142 | #if defined(PINMUX_PC06I_CAN0_TX) && !defined(IGNORE_PIN_PC06) 2143 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 0, PINMUX_PC06I_CAN0_TX & 0xf}, 2144 | #endif 2145 | #if defined(PINMUX_PC07I_CAN0_TX) && !defined(IGNORE_PIN_PC07) 2146 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 0, PINMUX_PC07I_CAN0_TX & 0xf}, 2147 | #endif 2148 | #if defined(PINMUX_PC08I_CAN0_TX) && !defined(IGNORE_PIN_PC08) 2149 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 0, PINMUX_PC08I_CAN0_TX & 0xf}, 2150 | #endif 2151 | #if defined(PINMUX_PC09I_CAN0_TX) && !defined(IGNORE_PIN_PC09) 2152 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 0, PINMUX_PC09I_CAN0_TX & 0xf}, 2153 | #endif 2154 | #if defined(PINMUX_PC10I_CAN0_TX) && !defined(IGNORE_PIN_PC10) 2155 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 0, PINMUX_PC10I_CAN0_TX & 0xf}, 2156 | #endif 2157 | #if defined(PINMUX_PC11I_CAN0_TX) && !defined(IGNORE_PIN_PC11) 2158 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 0, PINMUX_PC11I_CAN0_TX & 0xf}, 2159 | #endif 2160 | #if defined(PINMUX_PC12I_CAN0_TX) && !defined(IGNORE_PIN_PC12) 2161 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 0, PINMUX_PC12I_CAN0_TX & 0xf}, 2162 | #endif 2163 | #if defined(PINMUX_PC13I_CAN0_TX) && !defined(IGNORE_PIN_PC13) 2164 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 0, PINMUX_PC13I_CAN0_TX & 0xf}, 2165 | #endif 2166 | #if defined(PINMUX_PC14I_CAN0_TX) && !defined(IGNORE_PIN_PC14) 2167 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 0, PINMUX_PC14I_CAN0_TX & 0xf}, 2168 | #endif 2169 | #if defined(PINMUX_PC15I_CAN0_TX) && !defined(IGNORE_PIN_PC15) 2170 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 0, PINMUX_PC15I_CAN0_TX & 0xf}, 2171 | #endif 2172 | #if defined(PINMUX_PC16I_CAN0_TX) && !defined(IGNORE_PIN_PC16) 2173 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 0, PINMUX_PC16I_CAN0_TX & 0xf}, 2174 | #endif 2175 | #if defined(PINMUX_PC17I_CAN0_TX) && !defined(IGNORE_PIN_PC17) 2176 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 0, PINMUX_PC17I_CAN0_TX & 0xf}, 2177 | #endif 2178 | #if defined(PINMUX_PC18I_CAN0_TX) && !defined(IGNORE_PIN_PC18) 2179 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 0, PINMUX_PC18I_CAN0_TX & 0xf}, 2180 | #endif 2181 | #if defined(PINMUX_PC19I_CAN0_TX) && !defined(IGNORE_PIN_PC19) 2182 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 0, PINMUX_PC19I_CAN0_TX & 0xf}, 2183 | #endif 2184 | #if defined(PINMUX_PC20I_CAN0_TX) && !defined(IGNORE_PIN_PC20) 2185 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 0, PINMUX_PC20I_CAN0_TX & 0xf}, 2186 | #endif 2187 | #if defined(PINMUX_PC21I_CAN0_TX) && !defined(IGNORE_PIN_PC21) 2188 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 0, PINMUX_PC21I_CAN0_TX & 0xf}, 2189 | #endif 2190 | #if defined(PINMUX_PC22I_CAN0_TX) && !defined(IGNORE_PIN_PC22) 2191 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 0, PINMUX_PC22I_CAN0_TX & 0xf}, 2192 | #endif 2193 | #if defined(PINMUX_PC23I_CAN0_TX) && !defined(IGNORE_PIN_PC23) 2194 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 0, PINMUX_PC23I_CAN0_TX & 0xf}, 2195 | #endif 2196 | #if defined(PINMUX_PC24I_CAN0_TX) && !defined(IGNORE_PIN_PC24) 2197 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 0, PINMUX_PC24I_CAN0_TX & 0xf}, 2198 | #endif 2199 | #if defined(PINMUX_PC25I_CAN0_TX) && !defined(IGNORE_PIN_PC25) 2200 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 0, PINMUX_PC25I_CAN0_TX & 0xf}, 2201 | #endif 2202 | #if defined(PINMUX_PC26I_CAN0_TX) && !defined(IGNORE_PIN_PC26) 2203 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 0, PINMUX_PC26I_CAN0_TX & 0xf}, 2204 | #endif 2205 | #if defined(PINMUX_PC27I_CAN0_TX) && !defined(IGNORE_PIN_PC27) 2206 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 0, PINMUX_PC27I_CAN0_TX & 0xf}, 2207 | #endif 2208 | #if defined(PINMUX_PC28I_CAN0_TX) && !defined(IGNORE_PIN_PC28) 2209 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 0, PINMUX_PC28I_CAN0_TX & 0xf}, 2210 | #endif 2211 | #if defined(PINMUX_PC29I_CAN0_TX) && !defined(IGNORE_PIN_PC29) 2212 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 0, PINMUX_PC29I_CAN0_TX & 0xf}, 2213 | #endif 2214 | #if defined(PINMUX_PC30I_CAN0_TX) && !defined(IGNORE_PIN_PC30) 2215 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 0, PINMUX_PC30I_CAN0_TX & 0xf}, 2216 | #endif 2217 | #if defined(PINMUX_PC31I_CAN0_TX) && !defined(IGNORE_PIN_PC31) 2218 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 0, PINMUX_PC31I_CAN0_TX & 0xf}, 2219 | #endif 2220 | #if defined(PINMUX_PD00I_CAN0_TX) && !defined(IGNORE_PIN_PD00) 2221 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 0, PINMUX_PD00I_CAN0_TX & 0xf}, 2222 | #endif 2223 | #if defined(PINMUX_PD01I_CAN0_TX) && !defined(IGNORE_PIN_PD01) 2224 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 0, PINMUX_PD01I_CAN0_TX & 0xf}, 2225 | #endif 2226 | #if defined(PINMUX_PD02I_CAN0_TX) && !defined(IGNORE_PIN_PD02) 2227 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 0, PINMUX_PD02I_CAN0_TX & 0xf}, 2228 | #endif 2229 | #if defined(PINMUX_PD03I_CAN0_TX) && !defined(IGNORE_PIN_PD03) 2230 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 0, PINMUX_PD03I_CAN0_TX & 0xf}, 2231 | #endif 2232 | #if defined(PINMUX_PD04I_CAN0_TX) && !defined(IGNORE_PIN_PD04) 2233 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 0, PINMUX_PD04I_CAN0_TX & 0xf}, 2234 | #endif 2235 | #if defined(PINMUX_PD05I_CAN0_TX) && !defined(IGNORE_PIN_PD05) 2236 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 0, PINMUX_PD05I_CAN0_TX & 0xf}, 2237 | #endif 2238 | #if defined(PINMUX_PD06I_CAN0_TX) && !defined(IGNORE_PIN_PD06) 2239 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 0, PINMUX_PD06I_CAN0_TX & 0xf}, 2240 | #endif 2241 | #if defined(PINMUX_PD07I_CAN0_TX) && !defined(IGNORE_PIN_PD07) 2242 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 0, PINMUX_PD07I_CAN0_TX & 0xf}, 2243 | #endif 2244 | #if defined(PINMUX_PD08I_CAN0_TX) && !defined(IGNORE_PIN_PD08) 2245 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 0, PINMUX_PD08I_CAN0_TX & 0xf}, 2246 | #endif 2247 | #if defined(PINMUX_PD09I_CAN0_TX) && !defined(IGNORE_PIN_PD09) 2248 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 0, PINMUX_PD09I_CAN0_TX & 0xf}, 2249 | #endif 2250 | #if defined(PINMUX_PD10I_CAN0_TX) && !defined(IGNORE_PIN_PD10) 2251 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 0, PINMUX_PD10I_CAN0_TX & 0xf}, 2252 | #endif 2253 | #if defined(PINMUX_PD11I_CAN0_TX) && !defined(IGNORE_PIN_PD11) 2254 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 0, PINMUX_PD11I_CAN0_TX & 0xf}, 2255 | #endif 2256 | #if defined(PINMUX_PD12I_CAN0_TX) && !defined(IGNORE_PIN_PD12) 2257 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 0, PINMUX_PD12I_CAN0_TX & 0xf}, 2258 | #endif 2259 | #if defined(PINMUX_PD13I_CAN0_TX) && !defined(IGNORE_PIN_PD13) 2260 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 0, PINMUX_PD13I_CAN0_TX & 0xf}, 2261 | #endif 2262 | #if defined(PINMUX_PD14I_CAN0_TX) && !defined(IGNORE_PIN_PD14) 2263 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 0, PINMUX_PD14I_CAN0_TX & 0xf}, 2264 | #endif 2265 | #if defined(PINMUX_PD15I_CAN0_TX) && !defined(IGNORE_PIN_PD15) 2266 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 0, PINMUX_PD15I_CAN0_TX & 0xf}, 2267 | #endif 2268 | #if defined(PINMUX_PD16I_CAN0_TX) && !defined(IGNORE_PIN_PD16) 2269 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 0, PINMUX_PD16I_CAN0_TX & 0xf}, 2270 | #endif 2271 | #if defined(PINMUX_PD17I_CAN0_TX) && !defined(IGNORE_PIN_PD17) 2272 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 0, PINMUX_PD17I_CAN0_TX & 0xf}, 2273 | #endif 2274 | #if defined(PINMUX_PD18I_CAN0_TX) && !defined(IGNORE_PIN_PD18) 2275 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 0, PINMUX_PD18I_CAN0_TX & 0xf}, 2276 | #endif 2277 | #if defined(PINMUX_PD19I_CAN0_TX) && !defined(IGNORE_PIN_PD19) 2278 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 0, PINMUX_PD19I_CAN0_TX & 0xf}, 2279 | #endif 2280 | #if defined(PINMUX_PD20I_CAN0_TX) && !defined(IGNORE_PIN_PD20) 2281 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 0, PINMUX_PD20I_CAN0_TX & 0xf}, 2282 | #endif 2283 | #if defined(PINMUX_PD21I_CAN0_TX) && !defined(IGNORE_PIN_PD21) 2284 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 0, PINMUX_PD21I_CAN0_TX & 0xf}, 2285 | #endif 2286 | #if defined(PINMUX_PD22I_CAN0_TX) && !defined(IGNORE_PIN_PD22) 2287 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 0, PINMUX_PD22I_CAN0_TX & 0xf}, 2288 | #endif 2289 | #if defined(PINMUX_PD23I_CAN0_TX) && !defined(IGNORE_PIN_PD23) 2290 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 0, PINMUX_PD23I_CAN0_TX & 0xf}, 2291 | #endif 2292 | #if defined(PINMUX_PD24I_CAN0_TX) && !defined(IGNORE_PIN_PD24) 2293 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 0, PINMUX_PD24I_CAN0_TX & 0xf}, 2294 | #endif 2295 | #if defined(PINMUX_PD25I_CAN0_TX) && !defined(IGNORE_PIN_PD25) 2296 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 0, PINMUX_PD25I_CAN0_TX & 0xf}, 2297 | #endif 2298 | #if defined(PINMUX_PD26I_CAN0_TX) && !defined(IGNORE_PIN_PD26) 2299 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 0, PINMUX_PD26I_CAN0_TX & 0xf}, 2300 | #endif 2301 | #if defined(PINMUX_PD27I_CAN0_TX) && !defined(IGNORE_PIN_PD27) 2302 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 0, PINMUX_PD27I_CAN0_TX & 0xf}, 2303 | #endif 2304 | #if defined(PINMUX_PD28I_CAN0_TX) && !defined(IGNORE_PIN_PD28) 2305 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 0, PINMUX_PD28I_CAN0_TX & 0xf}, 2306 | #endif 2307 | #if defined(PINMUX_PD29I_CAN0_TX) && !defined(IGNORE_PIN_PD29) 2308 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 0, PINMUX_PD29I_CAN0_TX & 0xf}, 2309 | #endif 2310 | #if defined(PINMUX_PD30I_CAN0_TX) && !defined(IGNORE_PIN_PD30) 2311 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 0, PINMUX_PD30I_CAN0_TX & 0xf}, 2312 | #endif 2313 | #if defined(PINMUX_PD31I_CAN0_TX) && !defined(IGNORE_PIN_PD31) 2314 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 0, PINMUX_PD31I_CAN0_TX & 0xf}, 2315 | #endif 2316 | #if defined(PINMUX_PA00H_CAN1_TX) && !defined(IGNORE_PIN_PA00) 2317 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 1, PINMUX_PA00H_CAN1_TX & 0xf}, 2318 | #endif 2319 | #if defined(PINMUX_PA01H_CAN1_TX) && !defined(IGNORE_PIN_PA01) 2320 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 1, PINMUX_PA01H_CAN1_TX & 0xf}, 2321 | #endif 2322 | #if defined(PINMUX_PA02H_CAN1_TX) && !defined(IGNORE_PIN_PA02) 2323 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 1, PINMUX_PA02H_CAN1_TX & 0xf}, 2324 | #endif 2325 | #if defined(PINMUX_PA03H_CAN1_TX) && !defined(IGNORE_PIN_PA03) 2326 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 1, PINMUX_PA03H_CAN1_TX & 0xf}, 2327 | #endif 2328 | #if defined(PINMUX_PA04H_CAN1_TX) && !defined(IGNORE_PIN_PA04) 2329 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 1, PINMUX_PA04H_CAN1_TX & 0xf}, 2330 | #endif 2331 | #if defined(PINMUX_PA05H_CAN1_TX) && !defined(IGNORE_PIN_PA05) 2332 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 1, PINMUX_PA05H_CAN1_TX & 0xf}, 2333 | #endif 2334 | #if defined(PINMUX_PA06H_CAN1_TX) && !defined(IGNORE_PIN_PA06) 2335 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 1, PINMUX_PA06H_CAN1_TX & 0xf}, 2336 | #endif 2337 | #if defined(PINMUX_PA07H_CAN1_TX) && !defined(IGNORE_PIN_PA07) 2338 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 1, PINMUX_PA07H_CAN1_TX & 0xf}, 2339 | #endif 2340 | #if defined(PINMUX_PA08H_CAN1_TX) && !defined(IGNORE_PIN_PA08) 2341 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 1, PINMUX_PA08H_CAN1_TX & 0xf}, 2342 | #endif 2343 | #if defined(PINMUX_PA09H_CAN1_TX) && !defined(IGNORE_PIN_PA09) 2344 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 1, PINMUX_PA09H_CAN1_TX & 0xf}, 2345 | #endif 2346 | #if defined(PINMUX_PA10H_CAN1_TX) && !defined(IGNORE_PIN_PA10) 2347 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 1, PINMUX_PA10H_CAN1_TX & 0xf}, 2348 | #endif 2349 | #if defined(PINMUX_PA11H_CAN1_TX) && !defined(IGNORE_PIN_PA11) 2350 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 1, PINMUX_PA11H_CAN1_TX & 0xf}, 2351 | #endif 2352 | #if defined(PINMUX_PA12H_CAN1_TX) && !defined(IGNORE_PIN_PA12) 2353 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 1, PINMUX_PA12H_CAN1_TX & 0xf}, 2354 | #endif 2355 | #if defined(PINMUX_PA13H_CAN1_TX) && !defined(IGNORE_PIN_PA13) 2356 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 1, PINMUX_PA13H_CAN1_TX & 0xf}, 2357 | #endif 2358 | #if defined(PINMUX_PA14H_CAN1_TX) && !defined(IGNORE_PIN_PA14) 2359 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 1, PINMUX_PA14H_CAN1_TX & 0xf}, 2360 | #endif 2361 | #if defined(PINMUX_PA15H_CAN1_TX) && !defined(IGNORE_PIN_PA15) 2362 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 1, PINMUX_PA15H_CAN1_TX & 0xf}, 2363 | #endif 2364 | #if defined(PINMUX_PA16H_CAN1_TX) && !defined(IGNORE_PIN_PA16) 2365 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 1, PINMUX_PA16H_CAN1_TX & 0xf}, 2366 | #endif 2367 | #if defined(PINMUX_PA17H_CAN1_TX) && !defined(IGNORE_PIN_PA17) 2368 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 1, PINMUX_PA17H_CAN1_TX & 0xf}, 2369 | #endif 2370 | #if defined(PINMUX_PA18H_CAN1_TX) && !defined(IGNORE_PIN_PA18) 2371 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 1, PINMUX_PA18H_CAN1_TX & 0xf}, 2372 | #endif 2373 | #if defined(PINMUX_PA19H_CAN1_TX) && !defined(IGNORE_PIN_PA19) 2374 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 1, PINMUX_PA19H_CAN1_TX & 0xf}, 2375 | #endif 2376 | #if defined(PINMUX_PA20H_CAN1_TX) && !defined(IGNORE_PIN_PA20) 2377 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 1, PINMUX_PA20H_CAN1_TX & 0xf}, 2378 | #endif 2379 | #if defined(PINMUX_PA21H_CAN1_TX) && !defined(IGNORE_PIN_PA21) 2380 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 1, PINMUX_PA21H_CAN1_TX & 0xf}, 2381 | #endif 2382 | #if defined(PINMUX_PA22H_CAN1_TX) && !defined(IGNORE_PIN_PA22) 2383 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 1, PINMUX_PA22H_CAN1_TX & 0xf}, 2384 | #endif 2385 | #if defined(PINMUX_PA23H_CAN1_TX) && !defined(IGNORE_PIN_PA23) 2386 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 1, PINMUX_PA23H_CAN1_TX & 0xf}, 2387 | #endif 2388 | #if defined(PINMUX_PA24H_CAN1_TX) && !defined(IGNORE_PIN_PA24) 2389 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 1, PINMUX_PA24H_CAN1_TX & 0xf}, 2390 | #endif 2391 | #if defined(PINMUX_PA25H_CAN1_TX) && !defined(IGNORE_PIN_PA25) 2392 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 1, PINMUX_PA25H_CAN1_TX & 0xf}, 2393 | #endif 2394 | #if defined(PINMUX_PA26H_CAN1_TX) && !defined(IGNORE_PIN_PA26) 2395 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 1, PINMUX_PA26H_CAN1_TX & 0xf}, 2396 | #endif 2397 | #if defined(PINMUX_PA27H_CAN1_TX) && !defined(IGNORE_PIN_PA27) 2398 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 1, PINMUX_PA27H_CAN1_TX & 0xf}, 2399 | #endif 2400 | #if defined(PINMUX_PA28H_CAN1_TX) && !defined(IGNORE_PIN_PA28) 2401 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 1, PINMUX_PA28H_CAN1_TX & 0xf}, 2402 | #endif 2403 | #if defined(PINMUX_PA29H_CAN1_TX) && !defined(IGNORE_PIN_PA29) 2404 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 1, PINMUX_PA29H_CAN1_TX & 0xf}, 2405 | #endif 2406 | #if defined(PINMUX_PA30H_CAN1_TX) && !defined(IGNORE_PIN_PA30) 2407 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 1, PINMUX_PA30H_CAN1_TX & 0xf}, 2408 | #endif 2409 | #if defined(PINMUX_PA31H_CAN1_TX) && !defined(IGNORE_PIN_PA31) 2410 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 1, PINMUX_PA31H_CAN1_TX & 0xf}, 2411 | #endif 2412 | #if defined(PINMUX_PB00H_CAN1_TX) && !defined(IGNORE_PIN_PB00) 2413 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 1, PINMUX_PB00H_CAN1_TX & 0xf}, 2414 | #endif 2415 | #if defined(PINMUX_PB01H_CAN1_TX) && !defined(IGNORE_PIN_PB01) 2416 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 1, PINMUX_PB01H_CAN1_TX & 0xf}, 2417 | #endif 2418 | #if defined(PINMUX_PB02H_CAN1_TX) && !defined(IGNORE_PIN_PB02) 2419 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 1, PINMUX_PB02H_CAN1_TX & 0xf}, 2420 | #endif 2421 | #if defined(PINMUX_PB03H_CAN1_TX) && !defined(IGNORE_PIN_PB03) 2422 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 1, PINMUX_PB03H_CAN1_TX & 0xf}, 2423 | #endif 2424 | #if defined(PINMUX_PB04H_CAN1_TX) && !defined(IGNORE_PIN_PB04) 2425 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 1, PINMUX_PB04H_CAN1_TX & 0xf}, 2426 | #endif 2427 | #if defined(PINMUX_PB05H_CAN1_TX) && !defined(IGNORE_PIN_PB05) 2428 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 1, PINMUX_PB05H_CAN1_TX & 0xf}, 2429 | #endif 2430 | #if defined(PINMUX_PB06H_CAN1_TX) && !defined(IGNORE_PIN_PB06) 2431 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 1, PINMUX_PB06H_CAN1_TX & 0xf}, 2432 | #endif 2433 | #if defined(PINMUX_PB07H_CAN1_TX) && !defined(IGNORE_PIN_PB07) 2434 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 1, PINMUX_PB07H_CAN1_TX & 0xf}, 2435 | #endif 2436 | #if defined(PINMUX_PB08H_CAN1_TX) && !defined(IGNORE_PIN_PB08) 2437 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 1, PINMUX_PB08H_CAN1_TX & 0xf}, 2438 | #endif 2439 | #if defined(PINMUX_PB09H_CAN1_TX) && !defined(IGNORE_PIN_PB09) 2440 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 1, PINMUX_PB09H_CAN1_TX & 0xf}, 2441 | #endif 2442 | #if defined(PINMUX_PB10H_CAN1_TX) && !defined(IGNORE_PIN_PB10) 2443 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 1, PINMUX_PB10H_CAN1_TX & 0xf}, 2444 | #endif 2445 | #if defined(PINMUX_PB11H_CAN1_TX) && !defined(IGNORE_PIN_PB11) 2446 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 1, PINMUX_PB11H_CAN1_TX & 0xf}, 2447 | #endif 2448 | #if defined(PINMUX_PB12H_CAN1_TX) && !defined(IGNORE_PIN_PB12) 2449 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 1, PINMUX_PB12H_CAN1_TX & 0xf}, 2450 | #endif 2451 | #if defined(PINMUX_PB13H_CAN1_TX) && !defined(IGNORE_PIN_PB13) 2452 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 1, PINMUX_PB13H_CAN1_TX & 0xf}, 2453 | #endif 2454 | #if defined(PINMUX_PB14H_CAN1_TX) && !defined(IGNORE_PIN_PB14) 2455 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 1, PINMUX_PB14H_CAN1_TX & 0xf}, 2456 | #endif 2457 | #if defined(PINMUX_PB15H_CAN1_TX) && !defined(IGNORE_PIN_PB15) 2458 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 1, PINMUX_PB15H_CAN1_TX & 0xf}, 2459 | #endif 2460 | #if defined(PINMUX_PB16H_CAN1_TX) && !defined(IGNORE_PIN_PB16) 2461 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 1, PINMUX_PB16H_CAN1_TX & 0xf}, 2462 | #endif 2463 | #if defined(PINMUX_PB17H_CAN1_TX) && !defined(IGNORE_PIN_PB17) 2464 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 1, PINMUX_PB17H_CAN1_TX & 0xf}, 2465 | #endif 2466 | #if defined(PINMUX_PB18H_CAN1_TX) && !defined(IGNORE_PIN_PB18) 2467 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 1, PINMUX_PB18H_CAN1_TX & 0xf}, 2468 | #endif 2469 | #if defined(PINMUX_PB19H_CAN1_TX) && !defined(IGNORE_PIN_PB19) 2470 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 1, PINMUX_PB19H_CAN1_TX & 0xf}, 2471 | #endif 2472 | #if defined(PINMUX_PB20H_CAN1_TX) && !defined(IGNORE_PIN_PB20) 2473 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 1, PINMUX_PB20H_CAN1_TX & 0xf}, 2474 | #endif 2475 | #if defined(PINMUX_PB21H_CAN1_TX) && !defined(IGNORE_PIN_PB21) 2476 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 1, PINMUX_PB21H_CAN1_TX & 0xf}, 2477 | #endif 2478 | #if defined(PINMUX_PB22H_CAN1_TX) && !defined(IGNORE_PIN_PB22) 2479 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 1, PINMUX_PB22H_CAN1_TX & 0xf}, 2480 | #endif 2481 | #if defined(PINMUX_PB23H_CAN1_TX) && !defined(IGNORE_PIN_PB23) 2482 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 1, PINMUX_PB23H_CAN1_TX & 0xf}, 2483 | #endif 2484 | #if defined(PINMUX_PB24H_CAN1_TX) && !defined(IGNORE_PIN_PB24) 2485 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 1, PINMUX_PB24H_CAN1_TX & 0xf}, 2486 | #endif 2487 | #if defined(PINMUX_PB25H_CAN1_TX) && !defined(IGNORE_PIN_PB25) 2488 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 1, PINMUX_PB25H_CAN1_TX & 0xf}, 2489 | #endif 2490 | #if defined(PINMUX_PB26H_CAN1_TX) && !defined(IGNORE_PIN_PB26) 2491 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 1, PINMUX_PB26H_CAN1_TX & 0xf}, 2492 | #endif 2493 | #if defined(PINMUX_PB27H_CAN1_TX) && !defined(IGNORE_PIN_PB27) 2494 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 1, PINMUX_PB27H_CAN1_TX & 0xf}, 2495 | #endif 2496 | #if defined(PINMUX_PB28H_CAN1_TX) && !defined(IGNORE_PIN_PB28) 2497 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 1, PINMUX_PB28H_CAN1_TX & 0xf}, 2498 | #endif 2499 | #if defined(PINMUX_PB29H_CAN1_TX) && !defined(IGNORE_PIN_PB29) 2500 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 1, PINMUX_PB29H_CAN1_TX & 0xf}, 2501 | #endif 2502 | #if defined(PINMUX_PB30H_CAN1_TX) && !defined(IGNORE_PIN_PB30) 2503 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 1, PINMUX_PB30H_CAN1_TX & 0xf}, 2504 | #endif 2505 | #if defined(PINMUX_PB31H_CAN1_TX) && !defined(IGNORE_PIN_PB31) 2506 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 1, PINMUX_PB31H_CAN1_TX & 0xf}, 2507 | #endif 2508 | #if defined(PINMUX_PC00H_CAN1_TX) && !defined(IGNORE_PIN_PC00) 2509 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 1, PINMUX_PC00H_CAN1_TX & 0xf}, 2510 | #endif 2511 | #if defined(PINMUX_PC01H_CAN1_TX) && !defined(IGNORE_PIN_PC01) 2512 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 1, PINMUX_PC01H_CAN1_TX & 0xf}, 2513 | #endif 2514 | #if defined(PINMUX_PC02H_CAN1_TX) && !defined(IGNORE_PIN_PC02) 2515 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 1, PINMUX_PC02H_CAN1_TX & 0xf}, 2516 | #endif 2517 | #if defined(PINMUX_PC03H_CAN1_TX) && !defined(IGNORE_PIN_PC03) 2518 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 1, PINMUX_PC03H_CAN1_TX & 0xf}, 2519 | #endif 2520 | #if defined(PINMUX_PC04H_CAN1_TX) && !defined(IGNORE_PIN_PC04) 2521 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 1, PINMUX_PC04H_CAN1_TX & 0xf}, 2522 | #endif 2523 | #if defined(PINMUX_PC05H_CAN1_TX) && !defined(IGNORE_PIN_PC05) 2524 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 1, PINMUX_PC05H_CAN1_TX & 0xf}, 2525 | #endif 2526 | #if defined(PINMUX_PC06H_CAN1_TX) && !defined(IGNORE_PIN_PC06) 2527 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 1, PINMUX_PC06H_CAN1_TX & 0xf}, 2528 | #endif 2529 | #if defined(PINMUX_PC07H_CAN1_TX) && !defined(IGNORE_PIN_PC07) 2530 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 1, PINMUX_PC07H_CAN1_TX & 0xf}, 2531 | #endif 2532 | #if defined(PINMUX_PC08H_CAN1_TX) && !defined(IGNORE_PIN_PC08) 2533 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 1, PINMUX_PC08H_CAN1_TX & 0xf}, 2534 | #endif 2535 | #if defined(PINMUX_PC09H_CAN1_TX) && !defined(IGNORE_PIN_PC09) 2536 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 1, PINMUX_PC09H_CAN1_TX & 0xf}, 2537 | #endif 2538 | #if defined(PINMUX_PC10H_CAN1_TX) && !defined(IGNORE_PIN_PC10) 2539 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 1, PINMUX_PC10H_CAN1_TX & 0xf}, 2540 | #endif 2541 | #if defined(PINMUX_PC11H_CAN1_TX) && !defined(IGNORE_PIN_PC11) 2542 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 1, PINMUX_PC11H_CAN1_TX & 0xf}, 2543 | #endif 2544 | #if defined(PINMUX_PC12H_CAN1_TX) && !defined(IGNORE_PIN_PC12) 2545 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 1, PINMUX_PC12H_CAN1_TX & 0xf}, 2546 | #endif 2547 | #if defined(PINMUX_PC13H_CAN1_TX) && !defined(IGNORE_PIN_PC13) 2548 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 1, PINMUX_PC13H_CAN1_TX & 0xf}, 2549 | #endif 2550 | #if defined(PINMUX_PC14H_CAN1_TX) && !defined(IGNORE_PIN_PC14) 2551 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 1, PINMUX_PC14H_CAN1_TX & 0xf}, 2552 | #endif 2553 | #if defined(PINMUX_PC15H_CAN1_TX) && !defined(IGNORE_PIN_PC15) 2554 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 1, PINMUX_PC15H_CAN1_TX & 0xf}, 2555 | #endif 2556 | #if defined(PINMUX_PC16H_CAN1_TX) && !defined(IGNORE_PIN_PC16) 2557 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 1, PINMUX_PC16H_CAN1_TX & 0xf}, 2558 | #endif 2559 | #if defined(PINMUX_PC17H_CAN1_TX) && !defined(IGNORE_PIN_PC17) 2560 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 1, PINMUX_PC17H_CAN1_TX & 0xf}, 2561 | #endif 2562 | #if defined(PINMUX_PC18H_CAN1_TX) && !defined(IGNORE_PIN_PC18) 2563 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 1, PINMUX_PC18H_CAN1_TX & 0xf}, 2564 | #endif 2565 | #if defined(PINMUX_PC19H_CAN1_TX) && !defined(IGNORE_PIN_PC19) 2566 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 1, PINMUX_PC19H_CAN1_TX & 0xf}, 2567 | #endif 2568 | #if defined(PINMUX_PC20H_CAN1_TX) && !defined(IGNORE_PIN_PC20) 2569 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 1, PINMUX_PC20H_CAN1_TX & 0xf}, 2570 | #endif 2571 | #if defined(PINMUX_PC21H_CAN1_TX) && !defined(IGNORE_PIN_PC21) 2572 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 1, PINMUX_PC21H_CAN1_TX & 0xf}, 2573 | #endif 2574 | #if defined(PINMUX_PC22H_CAN1_TX) && !defined(IGNORE_PIN_PC22) 2575 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 1, PINMUX_PC22H_CAN1_TX & 0xf}, 2576 | #endif 2577 | #if defined(PINMUX_PC23H_CAN1_TX) && !defined(IGNORE_PIN_PC23) 2578 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 1, PINMUX_PC23H_CAN1_TX & 0xf}, 2579 | #endif 2580 | #if defined(PINMUX_PC24H_CAN1_TX) && !defined(IGNORE_PIN_PC24) 2581 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 1, PINMUX_PC24H_CAN1_TX & 0xf}, 2582 | #endif 2583 | #if defined(PINMUX_PC25H_CAN1_TX) && !defined(IGNORE_PIN_PC25) 2584 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 1, PINMUX_PC25H_CAN1_TX & 0xf}, 2585 | #endif 2586 | #if defined(PINMUX_PC26H_CAN1_TX) && !defined(IGNORE_PIN_PC26) 2587 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 1, PINMUX_PC26H_CAN1_TX & 0xf}, 2588 | #endif 2589 | #if defined(PINMUX_PC27H_CAN1_TX) && !defined(IGNORE_PIN_PC27) 2590 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 1, PINMUX_PC27H_CAN1_TX & 0xf}, 2591 | #endif 2592 | #if defined(PINMUX_PC28H_CAN1_TX) && !defined(IGNORE_PIN_PC28) 2593 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 1, PINMUX_PC28H_CAN1_TX & 0xf}, 2594 | #endif 2595 | #if defined(PINMUX_PC29H_CAN1_TX) && !defined(IGNORE_PIN_PC29) 2596 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 1, PINMUX_PC29H_CAN1_TX & 0xf}, 2597 | #endif 2598 | #if defined(PINMUX_PC30H_CAN1_TX) && !defined(IGNORE_PIN_PC30) 2599 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 1, PINMUX_PC30H_CAN1_TX & 0xf}, 2600 | #endif 2601 | #if defined(PINMUX_PC31H_CAN1_TX) && !defined(IGNORE_PIN_PC31) 2602 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 1, PINMUX_PC31H_CAN1_TX & 0xf}, 2603 | #endif 2604 | #if defined(PINMUX_PD00H_CAN1_TX) && !defined(IGNORE_PIN_PD00) 2605 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 1, PINMUX_PD00H_CAN1_TX & 0xf}, 2606 | #endif 2607 | #if defined(PINMUX_PD01H_CAN1_TX) && !defined(IGNORE_PIN_PD01) 2608 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 1, PINMUX_PD01H_CAN1_TX & 0xf}, 2609 | #endif 2610 | #if defined(PINMUX_PD02H_CAN1_TX) && !defined(IGNORE_PIN_PD02) 2611 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 1, PINMUX_PD02H_CAN1_TX & 0xf}, 2612 | #endif 2613 | #if defined(PINMUX_PD03H_CAN1_TX) && !defined(IGNORE_PIN_PD03) 2614 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 1, PINMUX_PD03H_CAN1_TX & 0xf}, 2615 | #endif 2616 | #if defined(PINMUX_PD04H_CAN1_TX) && !defined(IGNORE_PIN_PD04) 2617 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 1, PINMUX_PD04H_CAN1_TX & 0xf}, 2618 | #endif 2619 | #if defined(PINMUX_PD05H_CAN1_TX) && !defined(IGNORE_PIN_PD05) 2620 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 1, PINMUX_PD05H_CAN1_TX & 0xf}, 2621 | #endif 2622 | #if defined(PINMUX_PD06H_CAN1_TX) && !defined(IGNORE_PIN_PD06) 2623 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 1, PINMUX_PD06H_CAN1_TX & 0xf}, 2624 | #endif 2625 | #if defined(PINMUX_PD07H_CAN1_TX) && !defined(IGNORE_PIN_PD07) 2626 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 1, PINMUX_PD07H_CAN1_TX & 0xf}, 2627 | #endif 2628 | #if defined(PINMUX_PD08H_CAN1_TX) && !defined(IGNORE_PIN_PD08) 2629 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 1, PINMUX_PD08H_CAN1_TX & 0xf}, 2630 | #endif 2631 | #if defined(PINMUX_PD09H_CAN1_TX) && !defined(IGNORE_PIN_PD09) 2632 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 1, PINMUX_PD09H_CAN1_TX & 0xf}, 2633 | #endif 2634 | #if defined(PINMUX_PD10H_CAN1_TX) && !defined(IGNORE_PIN_PD10) 2635 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 1, PINMUX_PD10H_CAN1_TX & 0xf}, 2636 | #endif 2637 | #if defined(PINMUX_PD11H_CAN1_TX) && !defined(IGNORE_PIN_PD11) 2638 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 1, PINMUX_PD11H_CAN1_TX & 0xf}, 2639 | #endif 2640 | #if defined(PINMUX_PD12H_CAN1_TX) && !defined(IGNORE_PIN_PD12) 2641 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 1, PINMUX_PD12H_CAN1_TX & 0xf}, 2642 | #endif 2643 | #if defined(PINMUX_PD13H_CAN1_TX) && !defined(IGNORE_PIN_PD13) 2644 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 1, PINMUX_PD13H_CAN1_TX & 0xf}, 2645 | #endif 2646 | #if defined(PINMUX_PD14H_CAN1_TX) && !defined(IGNORE_PIN_PD14) 2647 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 1, PINMUX_PD14H_CAN1_TX & 0xf}, 2648 | #endif 2649 | #if defined(PINMUX_PD15H_CAN1_TX) && !defined(IGNORE_PIN_PD15) 2650 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 1, PINMUX_PD15H_CAN1_TX & 0xf}, 2651 | #endif 2652 | #if defined(PINMUX_PD16H_CAN1_TX) && !defined(IGNORE_PIN_PD16) 2653 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 1, PINMUX_PD16H_CAN1_TX & 0xf}, 2654 | #endif 2655 | #if defined(PINMUX_PD17H_CAN1_TX) && !defined(IGNORE_PIN_PD17) 2656 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 1, PINMUX_PD17H_CAN1_TX & 0xf}, 2657 | #endif 2658 | #if defined(PINMUX_PD18H_CAN1_TX) && !defined(IGNORE_PIN_PD18) 2659 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 1, PINMUX_PD18H_CAN1_TX & 0xf}, 2660 | #endif 2661 | #if defined(PINMUX_PD19H_CAN1_TX) && !defined(IGNORE_PIN_PD19) 2662 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 1, PINMUX_PD19H_CAN1_TX & 0xf}, 2663 | #endif 2664 | #if defined(PINMUX_PD20H_CAN1_TX) && !defined(IGNORE_PIN_PD20) 2665 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 1, PINMUX_PD20H_CAN1_TX & 0xf}, 2666 | #endif 2667 | #if defined(PINMUX_PD21H_CAN1_TX) && !defined(IGNORE_PIN_PD21) 2668 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 1, PINMUX_PD21H_CAN1_TX & 0xf}, 2669 | #endif 2670 | #if defined(PINMUX_PD22H_CAN1_TX) && !defined(IGNORE_PIN_PD22) 2671 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 1, PINMUX_PD22H_CAN1_TX & 0xf}, 2672 | #endif 2673 | #if defined(PINMUX_PD23H_CAN1_TX) && !defined(IGNORE_PIN_PD23) 2674 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 1, PINMUX_PD23H_CAN1_TX & 0xf}, 2675 | #endif 2676 | #if defined(PINMUX_PD24H_CAN1_TX) && !defined(IGNORE_PIN_PD24) 2677 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 1, PINMUX_PD24H_CAN1_TX & 0xf}, 2678 | #endif 2679 | #if defined(PINMUX_PD25H_CAN1_TX) && !defined(IGNORE_PIN_PD25) 2680 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 1, PINMUX_PD25H_CAN1_TX & 0xf}, 2681 | #endif 2682 | #if defined(PINMUX_PD26H_CAN1_TX) && !defined(IGNORE_PIN_PD26) 2683 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 1, PINMUX_PD26H_CAN1_TX & 0xf}, 2684 | #endif 2685 | #if defined(PINMUX_PD27H_CAN1_TX) && !defined(IGNORE_PIN_PD27) 2686 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 1, PINMUX_PD27H_CAN1_TX & 0xf}, 2687 | #endif 2688 | #if defined(PINMUX_PD28H_CAN1_TX) && !defined(IGNORE_PIN_PD28) 2689 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 1, PINMUX_PD28H_CAN1_TX & 0xf}, 2690 | #endif 2691 | #if defined(PINMUX_PD29H_CAN1_TX) && !defined(IGNORE_PIN_PD29) 2692 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 1, PINMUX_PD29H_CAN1_TX & 0xf}, 2693 | #endif 2694 | #if defined(PINMUX_PD30H_CAN1_TX) && !defined(IGNORE_PIN_PD30) 2695 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 1, PINMUX_PD30H_CAN1_TX & 0xf}, 2696 | #endif 2697 | #if defined(PINMUX_PD31H_CAN1_TX) && !defined(IGNORE_PIN_PD31) 2698 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 1, PINMUX_PD31H_CAN1_TX & 0xf}, 2699 | #endif 2700 | #if defined(PINMUX_PA00I_CAN1_TX) && !defined(IGNORE_PIN_PA00) 2701 | {PIN_PA00 >> 5, PIN_PA00 & 0x1f, 1, PINMUX_PA00I_CAN1_TX & 0xf}, 2702 | #endif 2703 | #if defined(PINMUX_PA01I_CAN1_TX) && !defined(IGNORE_PIN_PA01) 2704 | {PIN_PA01 >> 5, PIN_PA01 & 0x1f, 1, PINMUX_PA01I_CAN1_TX & 0xf}, 2705 | #endif 2706 | #if defined(PINMUX_PA02I_CAN1_TX) && !defined(IGNORE_PIN_PA02) 2707 | {PIN_PA02 >> 5, PIN_PA02 & 0x1f, 1, PINMUX_PA02I_CAN1_TX & 0xf}, 2708 | #endif 2709 | #if defined(PINMUX_PA03I_CAN1_TX) && !defined(IGNORE_PIN_PA03) 2710 | {PIN_PA03 >> 5, PIN_PA03 & 0x1f, 1, PINMUX_PA03I_CAN1_TX & 0xf}, 2711 | #endif 2712 | #if defined(PINMUX_PA04I_CAN1_TX) && !defined(IGNORE_PIN_PA04) 2713 | {PIN_PA04 >> 5, PIN_PA04 & 0x1f, 1, PINMUX_PA04I_CAN1_TX & 0xf}, 2714 | #endif 2715 | #if defined(PINMUX_PA05I_CAN1_TX) && !defined(IGNORE_PIN_PA05) 2716 | {PIN_PA05 >> 5, PIN_PA05 & 0x1f, 1, PINMUX_PA05I_CAN1_TX & 0xf}, 2717 | #endif 2718 | #if defined(PINMUX_PA06I_CAN1_TX) && !defined(IGNORE_PIN_PA06) 2719 | {PIN_PA06 >> 5, PIN_PA06 & 0x1f, 1, PINMUX_PA06I_CAN1_TX & 0xf}, 2720 | #endif 2721 | #if defined(PINMUX_PA07I_CAN1_TX) && !defined(IGNORE_PIN_PA07) 2722 | {PIN_PA07 >> 5, PIN_PA07 & 0x1f, 1, PINMUX_PA07I_CAN1_TX & 0xf}, 2723 | #endif 2724 | #if defined(PINMUX_PA08I_CAN1_TX) && !defined(IGNORE_PIN_PA08) 2725 | {PIN_PA08 >> 5, PIN_PA08 & 0x1f, 1, PINMUX_PA08I_CAN1_TX & 0xf}, 2726 | #endif 2727 | #if defined(PINMUX_PA09I_CAN1_TX) && !defined(IGNORE_PIN_PA09) 2728 | {PIN_PA09 >> 5, PIN_PA09 & 0x1f, 1, PINMUX_PA09I_CAN1_TX & 0xf}, 2729 | #endif 2730 | #if defined(PINMUX_PA10I_CAN1_TX) && !defined(IGNORE_PIN_PA10) 2731 | {PIN_PA10 >> 5, PIN_PA10 & 0x1f, 1, PINMUX_PA10I_CAN1_TX & 0xf}, 2732 | #endif 2733 | #if defined(PINMUX_PA11I_CAN1_TX) && !defined(IGNORE_PIN_PA11) 2734 | {PIN_PA11 >> 5, PIN_PA11 & 0x1f, 1, PINMUX_PA11I_CAN1_TX & 0xf}, 2735 | #endif 2736 | #if defined(PINMUX_PA12I_CAN1_TX) && !defined(IGNORE_PIN_PA12) 2737 | {PIN_PA12 >> 5, PIN_PA12 & 0x1f, 1, PINMUX_PA12I_CAN1_TX & 0xf}, 2738 | #endif 2739 | #if defined(PINMUX_PA13I_CAN1_TX) && !defined(IGNORE_PIN_PA13) 2740 | {PIN_PA13 >> 5, PIN_PA13 & 0x1f, 1, PINMUX_PA13I_CAN1_TX & 0xf}, 2741 | #endif 2742 | #if defined(PINMUX_PA14I_CAN1_TX) && !defined(IGNORE_PIN_PA14) 2743 | {PIN_PA14 >> 5, PIN_PA14 & 0x1f, 1, PINMUX_PA14I_CAN1_TX & 0xf}, 2744 | #endif 2745 | #if defined(PINMUX_PA15I_CAN1_TX) && !defined(IGNORE_PIN_PA15) 2746 | {PIN_PA15 >> 5, PIN_PA15 & 0x1f, 1, PINMUX_PA15I_CAN1_TX & 0xf}, 2747 | #endif 2748 | #if defined(PINMUX_PA16I_CAN1_TX) && !defined(IGNORE_PIN_PA16) 2749 | {PIN_PA16 >> 5, PIN_PA16 & 0x1f, 1, PINMUX_PA16I_CAN1_TX & 0xf}, 2750 | #endif 2751 | #if defined(PINMUX_PA17I_CAN1_TX) && !defined(IGNORE_PIN_PA17) 2752 | {PIN_PA17 >> 5, PIN_PA17 & 0x1f, 1, PINMUX_PA17I_CAN1_TX & 0xf}, 2753 | #endif 2754 | #if defined(PINMUX_PA18I_CAN1_TX) && !defined(IGNORE_PIN_PA18) 2755 | {PIN_PA18 >> 5, PIN_PA18 & 0x1f, 1, PINMUX_PA18I_CAN1_TX & 0xf}, 2756 | #endif 2757 | #if defined(PINMUX_PA19I_CAN1_TX) && !defined(IGNORE_PIN_PA19) 2758 | {PIN_PA19 >> 5, PIN_PA19 & 0x1f, 1, PINMUX_PA19I_CAN1_TX & 0xf}, 2759 | #endif 2760 | #if defined(PINMUX_PA20I_CAN1_TX) && !defined(IGNORE_PIN_PA20) 2761 | {PIN_PA20 >> 5, PIN_PA20 & 0x1f, 1, PINMUX_PA20I_CAN1_TX & 0xf}, 2762 | #endif 2763 | #if defined(PINMUX_PA21I_CAN1_TX) && !defined(IGNORE_PIN_PA21) 2764 | {PIN_PA21 >> 5, PIN_PA21 & 0x1f, 1, PINMUX_PA21I_CAN1_TX & 0xf}, 2765 | #endif 2766 | #if defined(PINMUX_PA22I_CAN1_TX) && !defined(IGNORE_PIN_PA22) 2767 | {PIN_PA22 >> 5, PIN_PA22 & 0x1f, 1, PINMUX_PA22I_CAN1_TX & 0xf}, 2768 | #endif 2769 | #if defined(PINMUX_PA23I_CAN1_TX) && !defined(IGNORE_PIN_PA23) 2770 | {PIN_PA23 >> 5, PIN_PA23 & 0x1f, 1, PINMUX_PA23I_CAN1_TX & 0xf}, 2771 | #endif 2772 | #if defined(PINMUX_PA24I_CAN1_TX) && !defined(IGNORE_PIN_PA24) 2773 | {PIN_PA24 >> 5, PIN_PA24 & 0x1f, 1, PINMUX_PA24I_CAN1_TX & 0xf}, 2774 | #endif 2775 | #if defined(PINMUX_PA25I_CAN1_TX) && !defined(IGNORE_PIN_PA25) 2776 | {PIN_PA25 >> 5, PIN_PA25 & 0x1f, 1, PINMUX_PA25I_CAN1_TX & 0xf}, 2777 | #endif 2778 | #if defined(PINMUX_PA26I_CAN1_TX) && !defined(IGNORE_PIN_PA26) 2779 | {PIN_PA26 >> 5, PIN_PA26 & 0x1f, 1, PINMUX_PA26I_CAN1_TX & 0xf}, 2780 | #endif 2781 | #if defined(PINMUX_PA27I_CAN1_TX) && !defined(IGNORE_PIN_PA27) 2782 | {PIN_PA27 >> 5, PIN_PA27 & 0x1f, 1, PINMUX_PA27I_CAN1_TX & 0xf}, 2783 | #endif 2784 | #if defined(PINMUX_PA28I_CAN1_TX) && !defined(IGNORE_PIN_PA28) 2785 | {PIN_PA28 >> 5, PIN_PA28 & 0x1f, 1, PINMUX_PA28I_CAN1_TX & 0xf}, 2786 | #endif 2787 | #if defined(PINMUX_PA29I_CAN1_TX) && !defined(IGNORE_PIN_PA29) 2788 | {PIN_PA29 >> 5, PIN_PA29 & 0x1f, 1, PINMUX_PA29I_CAN1_TX & 0xf}, 2789 | #endif 2790 | #if defined(PINMUX_PA30I_CAN1_TX) && !defined(IGNORE_PIN_PA30) 2791 | {PIN_PA30 >> 5, PIN_PA30 & 0x1f, 1, PINMUX_PA30I_CAN1_TX & 0xf}, 2792 | #endif 2793 | #if defined(PINMUX_PA31I_CAN1_TX) && !defined(IGNORE_PIN_PA31) 2794 | {PIN_PA31 >> 5, PIN_PA31 & 0x1f, 1, PINMUX_PA31I_CAN1_TX & 0xf}, 2795 | #endif 2796 | #if defined(PINMUX_PB00I_CAN1_TX) && !defined(IGNORE_PIN_PB00) 2797 | {PIN_PB00 >> 5, PIN_PB00 & 0x1f, 1, PINMUX_PB00I_CAN1_TX & 0xf}, 2798 | #endif 2799 | #if defined(PINMUX_PB01I_CAN1_TX) && !defined(IGNORE_PIN_PB01) 2800 | {PIN_PB01 >> 5, PIN_PB01 & 0x1f, 1, PINMUX_PB01I_CAN1_TX & 0xf}, 2801 | #endif 2802 | #if defined(PINMUX_PB02I_CAN1_TX) && !defined(IGNORE_PIN_PB02) 2803 | {PIN_PB02 >> 5, PIN_PB02 & 0x1f, 1, PINMUX_PB02I_CAN1_TX & 0xf}, 2804 | #endif 2805 | #if defined(PINMUX_PB03I_CAN1_TX) && !defined(IGNORE_PIN_PB03) 2806 | {PIN_PB03 >> 5, PIN_PB03 & 0x1f, 1, PINMUX_PB03I_CAN1_TX & 0xf}, 2807 | #endif 2808 | #if defined(PINMUX_PB04I_CAN1_TX) && !defined(IGNORE_PIN_PB04) 2809 | {PIN_PB04 >> 5, PIN_PB04 & 0x1f, 1, PINMUX_PB04I_CAN1_TX & 0xf}, 2810 | #endif 2811 | #if defined(PINMUX_PB05I_CAN1_TX) && !defined(IGNORE_PIN_PB05) 2812 | {PIN_PB05 >> 5, PIN_PB05 & 0x1f, 1, PINMUX_PB05I_CAN1_TX & 0xf}, 2813 | #endif 2814 | #if defined(PINMUX_PB06I_CAN1_TX) && !defined(IGNORE_PIN_PB06) 2815 | {PIN_PB06 >> 5, PIN_PB06 & 0x1f, 1, PINMUX_PB06I_CAN1_TX & 0xf}, 2816 | #endif 2817 | #if defined(PINMUX_PB07I_CAN1_TX) && !defined(IGNORE_PIN_PB07) 2818 | {PIN_PB07 >> 5, PIN_PB07 & 0x1f, 1, PINMUX_PB07I_CAN1_TX & 0xf}, 2819 | #endif 2820 | #if defined(PINMUX_PB08I_CAN1_TX) && !defined(IGNORE_PIN_PB08) 2821 | {PIN_PB08 >> 5, PIN_PB08 & 0x1f, 1, PINMUX_PB08I_CAN1_TX & 0xf}, 2822 | #endif 2823 | #if defined(PINMUX_PB09I_CAN1_TX) && !defined(IGNORE_PIN_PB09) 2824 | {PIN_PB09 >> 5, PIN_PB09 & 0x1f, 1, PINMUX_PB09I_CAN1_TX & 0xf}, 2825 | #endif 2826 | #if defined(PINMUX_PB10I_CAN1_TX) && !defined(IGNORE_PIN_PB10) 2827 | {PIN_PB10 >> 5, PIN_PB10 & 0x1f, 1, PINMUX_PB10I_CAN1_TX & 0xf}, 2828 | #endif 2829 | #if defined(PINMUX_PB11I_CAN1_TX) && !defined(IGNORE_PIN_PB11) 2830 | {PIN_PB11 >> 5, PIN_PB11 & 0x1f, 1, PINMUX_PB11I_CAN1_TX & 0xf}, 2831 | #endif 2832 | #if defined(PINMUX_PB12I_CAN1_TX) && !defined(IGNORE_PIN_PB12) 2833 | {PIN_PB12 >> 5, PIN_PB12 & 0x1f, 1, PINMUX_PB12I_CAN1_TX & 0xf}, 2834 | #endif 2835 | #if defined(PINMUX_PB13I_CAN1_TX) && !defined(IGNORE_PIN_PB13) 2836 | {PIN_PB13 >> 5, PIN_PB13 & 0x1f, 1, PINMUX_PB13I_CAN1_TX & 0xf}, 2837 | #endif 2838 | #if defined(PINMUX_PB14I_CAN1_TX) && !defined(IGNORE_PIN_PB14) 2839 | {PIN_PB14 >> 5, PIN_PB14 & 0x1f, 1, PINMUX_PB14I_CAN1_TX & 0xf}, 2840 | #endif 2841 | #if defined(PINMUX_PB15I_CAN1_TX) && !defined(IGNORE_PIN_PB15) 2842 | {PIN_PB15 >> 5, PIN_PB15 & 0x1f, 1, PINMUX_PB15I_CAN1_TX & 0xf}, 2843 | #endif 2844 | #if defined(PINMUX_PB16I_CAN1_TX) && !defined(IGNORE_PIN_PB16) 2845 | {PIN_PB16 >> 5, PIN_PB16 & 0x1f, 1, PINMUX_PB16I_CAN1_TX & 0xf}, 2846 | #endif 2847 | #if defined(PINMUX_PB17I_CAN1_TX) && !defined(IGNORE_PIN_PB17) 2848 | {PIN_PB17 >> 5, PIN_PB17 & 0x1f, 1, PINMUX_PB17I_CAN1_TX & 0xf}, 2849 | #endif 2850 | #if defined(PINMUX_PB18I_CAN1_TX) && !defined(IGNORE_PIN_PB18) 2851 | {PIN_PB18 >> 5, PIN_PB18 & 0x1f, 1, PINMUX_PB18I_CAN1_TX & 0xf}, 2852 | #endif 2853 | #if defined(PINMUX_PB19I_CAN1_TX) && !defined(IGNORE_PIN_PB19) 2854 | {PIN_PB19 >> 5, PIN_PB19 & 0x1f, 1, PINMUX_PB19I_CAN1_TX & 0xf}, 2855 | #endif 2856 | #if defined(PINMUX_PB20I_CAN1_TX) && !defined(IGNORE_PIN_PB20) 2857 | {PIN_PB20 >> 5, PIN_PB20 & 0x1f, 1, PINMUX_PB20I_CAN1_TX & 0xf}, 2858 | #endif 2859 | #if defined(PINMUX_PB21I_CAN1_TX) && !defined(IGNORE_PIN_PB21) 2860 | {PIN_PB21 >> 5, PIN_PB21 & 0x1f, 1, PINMUX_PB21I_CAN1_TX & 0xf}, 2861 | #endif 2862 | #if defined(PINMUX_PB22I_CAN1_TX) && !defined(IGNORE_PIN_PB22) 2863 | {PIN_PB22 >> 5, PIN_PB22 & 0x1f, 1, PINMUX_PB22I_CAN1_TX & 0xf}, 2864 | #endif 2865 | #if defined(PINMUX_PB23I_CAN1_TX) && !defined(IGNORE_PIN_PB23) 2866 | {PIN_PB23 >> 5, PIN_PB23 & 0x1f, 1, PINMUX_PB23I_CAN1_TX & 0xf}, 2867 | #endif 2868 | #if defined(PINMUX_PB24I_CAN1_TX) && !defined(IGNORE_PIN_PB24) 2869 | {PIN_PB24 >> 5, PIN_PB24 & 0x1f, 1, PINMUX_PB24I_CAN1_TX & 0xf}, 2870 | #endif 2871 | #if defined(PINMUX_PB25I_CAN1_TX) && !defined(IGNORE_PIN_PB25) 2872 | {PIN_PB25 >> 5, PIN_PB25 & 0x1f, 1, PINMUX_PB25I_CAN1_TX & 0xf}, 2873 | #endif 2874 | #if defined(PINMUX_PB26I_CAN1_TX) && !defined(IGNORE_PIN_PB26) 2875 | {PIN_PB26 >> 5, PIN_PB26 & 0x1f, 1, PINMUX_PB26I_CAN1_TX & 0xf}, 2876 | #endif 2877 | #if defined(PINMUX_PB27I_CAN1_TX) && !defined(IGNORE_PIN_PB27) 2878 | {PIN_PB27 >> 5, PIN_PB27 & 0x1f, 1, PINMUX_PB27I_CAN1_TX & 0xf}, 2879 | #endif 2880 | #if defined(PINMUX_PB28I_CAN1_TX) && !defined(IGNORE_PIN_PB28) 2881 | {PIN_PB28 >> 5, PIN_PB28 & 0x1f, 1, PINMUX_PB28I_CAN1_TX & 0xf}, 2882 | #endif 2883 | #if defined(PINMUX_PB29I_CAN1_TX) && !defined(IGNORE_PIN_PB29) 2884 | {PIN_PB29 >> 5, PIN_PB29 & 0x1f, 1, PINMUX_PB29I_CAN1_TX & 0xf}, 2885 | #endif 2886 | #if defined(PINMUX_PB30I_CAN1_TX) && !defined(IGNORE_PIN_PB30) 2887 | {PIN_PB30 >> 5, PIN_PB30 & 0x1f, 1, PINMUX_PB30I_CAN1_TX & 0xf}, 2888 | #endif 2889 | #if defined(PINMUX_PB31I_CAN1_TX) && !defined(IGNORE_PIN_PB31) 2890 | {PIN_PB31 >> 5, PIN_PB31 & 0x1f, 1, PINMUX_PB31I_CAN1_TX & 0xf}, 2891 | #endif 2892 | #if defined(PINMUX_PC00I_CAN1_TX) && !defined(IGNORE_PIN_PC00) 2893 | {PIN_PC00 >> 5, PIN_PC00 & 0x1f, 1, PINMUX_PC00I_CAN1_TX & 0xf}, 2894 | #endif 2895 | #if defined(PINMUX_PC01I_CAN1_TX) && !defined(IGNORE_PIN_PC01) 2896 | {PIN_PC01 >> 5, PIN_PC01 & 0x1f, 1, PINMUX_PC01I_CAN1_TX & 0xf}, 2897 | #endif 2898 | #if defined(PINMUX_PC02I_CAN1_TX) && !defined(IGNORE_PIN_PC02) 2899 | {PIN_PC02 >> 5, PIN_PC02 & 0x1f, 1, PINMUX_PC02I_CAN1_TX & 0xf}, 2900 | #endif 2901 | #if defined(PINMUX_PC03I_CAN1_TX) && !defined(IGNORE_PIN_PC03) 2902 | {PIN_PC03 >> 5, PIN_PC03 & 0x1f, 1, PINMUX_PC03I_CAN1_TX & 0xf}, 2903 | #endif 2904 | #if defined(PINMUX_PC04I_CAN1_TX) && !defined(IGNORE_PIN_PC04) 2905 | {PIN_PC04 >> 5, PIN_PC04 & 0x1f, 1, PINMUX_PC04I_CAN1_TX & 0xf}, 2906 | #endif 2907 | #if defined(PINMUX_PC05I_CAN1_TX) && !defined(IGNORE_PIN_PC05) 2908 | {PIN_PC05 >> 5, PIN_PC05 & 0x1f, 1, PINMUX_PC05I_CAN1_TX & 0xf}, 2909 | #endif 2910 | #if defined(PINMUX_PC06I_CAN1_TX) && !defined(IGNORE_PIN_PC06) 2911 | {PIN_PC06 >> 5, PIN_PC06 & 0x1f, 1, PINMUX_PC06I_CAN1_TX & 0xf}, 2912 | #endif 2913 | #if defined(PINMUX_PC07I_CAN1_TX) && !defined(IGNORE_PIN_PC07) 2914 | {PIN_PC07 >> 5, PIN_PC07 & 0x1f, 1, PINMUX_PC07I_CAN1_TX & 0xf}, 2915 | #endif 2916 | #if defined(PINMUX_PC08I_CAN1_TX) && !defined(IGNORE_PIN_PC08) 2917 | {PIN_PC08 >> 5, PIN_PC08 & 0x1f, 1, PINMUX_PC08I_CAN1_TX & 0xf}, 2918 | #endif 2919 | #if defined(PINMUX_PC09I_CAN1_TX) && !defined(IGNORE_PIN_PC09) 2920 | {PIN_PC09 >> 5, PIN_PC09 & 0x1f, 1, PINMUX_PC09I_CAN1_TX & 0xf}, 2921 | #endif 2922 | #if defined(PINMUX_PC10I_CAN1_TX) && !defined(IGNORE_PIN_PC10) 2923 | {PIN_PC10 >> 5, PIN_PC10 & 0x1f, 1, PINMUX_PC10I_CAN1_TX & 0xf}, 2924 | #endif 2925 | #if defined(PINMUX_PC11I_CAN1_TX) && !defined(IGNORE_PIN_PC11) 2926 | {PIN_PC11 >> 5, PIN_PC11 & 0x1f, 1, PINMUX_PC11I_CAN1_TX & 0xf}, 2927 | #endif 2928 | #if defined(PINMUX_PC12I_CAN1_TX) && !defined(IGNORE_PIN_PC12) 2929 | {PIN_PC12 >> 5, PIN_PC12 & 0x1f, 1, PINMUX_PC12I_CAN1_TX & 0xf}, 2930 | #endif 2931 | #if defined(PINMUX_PC13I_CAN1_TX) && !defined(IGNORE_PIN_PC13) 2932 | {PIN_PC13 >> 5, PIN_PC13 & 0x1f, 1, PINMUX_PC13I_CAN1_TX & 0xf}, 2933 | #endif 2934 | #if defined(PINMUX_PC14I_CAN1_TX) && !defined(IGNORE_PIN_PC14) 2935 | {PIN_PC14 >> 5, PIN_PC14 & 0x1f, 1, PINMUX_PC14I_CAN1_TX & 0xf}, 2936 | #endif 2937 | #if defined(PINMUX_PC15I_CAN1_TX) && !defined(IGNORE_PIN_PC15) 2938 | {PIN_PC15 >> 5, PIN_PC15 & 0x1f, 1, PINMUX_PC15I_CAN1_TX & 0xf}, 2939 | #endif 2940 | #if defined(PINMUX_PC16I_CAN1_TX) && !defined(IGNORE_PIN_PC16) 2941 | {PIN_PC16 >> 5, PIN_PC16 & 0x1f, 1, PINMUX_PC16I_CAN1_TX & 0xf}, 2942 | #endif 2943 | #if defined(PINMUX_PC17I_CAN1_TX) && !defined(IGNORE_PIN_PC17) 2944 | {PIN_PC17 >> 5, PIN_PC17 & 0x1f, 1, PINMUX_PC17I_CAN1_TX & 0xf}, 2945 | #endif 2946 | #if defined(PINMUX_PC18I_CAN1_TX) && !defined(IGNORE_PIN_PC18) 2947 | {PIN_PC18 >> 5, PIN_PC18 & 0x1f, 1, PINMUX_PC18I_CAN1_TX & 0xf}, 2948 | #endif 2949 | #if defined(PINMUX_PC19I_CAN1_TX) && !defined(IGNORE_PIN_PC19) 2950 | {PIN_PC19 >> 5, PIN_PC19 & 0x1f, 1, PINMUX_PC19I_CAN1_TX & 0xf}, 2951 | #endif 2952 | #if defined(PINMUX_PC20I_CAN1_TX) && !defined(IGNORE_PIN_PC20) 2953 | {PIN_PC20 >> 5, PIN_PC20 & 0x1f, 1, PINMUX_PC20I_CAN1_TX & 0xf}, 2954 | #endif 2955 | #if defined(PINMUX_PC21I_CAN1_TX) && !defined(IGNORE_PIN_PC21) 2956 | {PIN_PC21 >> 5, PIN_PC21 & 0x1f, 1, PINMUX_PC21I_CAN1_TX & 0xf}, 2957 | #endif 2958 | #if defined(PINMUX_PC22I_CAN1_TX) && !defined(IGNORE_PIN_PC22) 2959 | {PIN_PC22 >> 5, PIN_PC22 & 0x1f, 1, PINMUX_PC22I_CAN1_TX & 0xf}, 2960 | #endif 2961 | #if defined(PINMUX_PC23I_CAN1_TX) && !defined(IGNORE_PIN_PC23) 2962 | {PIN_PC23 >> 5, PIN_PC23 & 0x1f, 1, PINMUX_PC23I_CAN1_TX & 0xf}, 2963 | #endif 2964 | #if defined(PINMUX_PC24I_CAN1_TX) && !defined(IGNORE_PIN_PC24) 2965 | {PIN_PC24 >> 5, PIN_PC24 & 0x1f, 1, PINMUX_PC24I_CAN1_TX & 0xf}, 2966 | #endif 2967 | #if defined(PINMUX_PC25I_CAN1_TX) && !defined(IGNORE_PIN_PC25) 2968 | {PIN_PC25 >> 5, PIN_PC25 & 0x1f, 1, PINMUX_PC25I_CAN1_TX & 0xf}, 2969 | #endif 2970 | #if defined(PINMUX_PC26I_CAN1_TX) && !defined(IGNORE_PIN_PC26) 2971 | {PIN_PC26 >> 5, PIN_PC26 & 0x1f, 1, PINMUX_PC26I_CAN1_TX & 0xf}, 2972 | #endif 2973 | #if defined(PINMUX_PC27I_CAN1_TX) && !defined(IGNORE_PIN_PC27) 2974 | {PIN_PC27 >> 5, PIN_PC27 & 0x1f, 1, PINMUX_PC27I_CAN1_TX & 0xf}, 2975 | #endif 2976 | #if defined(PINMUX_PC28I_CAN1_TX) && !defined(IGNORE_PIN_PC28) 2977 | {PIN_PC28 >> 5, PIN_PC28 & 0x1f, 1, PINMUX_PC28I_CAN1_TX & 0xf}, 2978 | #endif 2979 | #if defined(PINMUX_PC29I_CAN1_TX) && !defined(IGNORE_PIN_PC29) 2980 | {PIN_PC29 >> 5, PIN_PC29 & 0x1f, 1, PINMUX_PC29I_CAN1_TX & 0xf}, 2981 | #endif 2982 | #if defined(PINMUX_PC30I_CAN1_TX) && !defined(IGNORE_PIN_PC30) 2983 | {PIN_PC30 >> 5, PIN_PC30 & 0x1f, 1, PINMUX_PC30I_CAN1_TX & 0xf}, 2984 | #endif 2985 | #if defined(PINMUX_PC31I_CAN1_TX) && !defined(IGNORE_PIN_PC31) 2986 | {PIN_PC31 >> 5, PIN_PC31 & 0x1f, 1, PINMUX_PC31I_CAN1_TX & 0xf}, 2987 | #endif 2988 | #if defined(PINMUX_PD00I_CAN1_TX) && !defined(IGNORE_PIN_PD00) 2989 | {PIN_PD00 >> 5, PIN_PD00 & 0x1f, 1, PINMUX_PD00I_CAN1_TX & 0xf}, 2990 | #endif 2991 | #if defined(PINMUX_PD01I_CAN1_TX) && !defined(IGNORE_PIN_PD01) 2992 | {PIN_PD01 >> 5, PIN_PD01 & 0x1f, 1, PINMUX_PD01I_CAN1_TX & 0xf}, 2993 | #endif 2994 | #if defined(PINMUX_PD02I_CAN1_TX) && !defined(IGNORE_PIN_PD02) 2995 | {PIN_PD02 >> 5, PIN_PD02 & 0x1f, 1, PINMUX_PD02I_CAN1_TX & 0xf}, 2996 | #endif 2997 | #if defined(PINMUX_PD03I_CAN1_TX) && !defined(IGNORE_PIN_PD03) 2998 | {PIN_PD03 >> 5, PIN_PD03 & 0x1f, 1, PINMUX_PD03I_CAN1_TX & 0xf}, 2999 | #endif 3000 | #if defined(PINMUX_PD04I_CAN1_TX) && !defined(IGNORE_PIN_PD04) 3001 | {PIN_PD04 >> 5, PIN_PD04 & 0x1f, 1, PINMUX_PD04I_CAN1_TX & 0xf}, 3002 | #endif 3003 | #if defined(PINMUX_PD05I_CAN1_TX) && !defined(IGNORE_PIN_PD05) 3004 | {PIN_PD05 >> 5, PIN_PD05 & 0x1f, 1, PINMUX_PD05I_CAN1_TX & 0xf}, 3005 | #endif 3006 | #if defined(PINMUX_PD06I_CAN1_TX) && !defined(IGNORE_PIN_PD06) 3007 | {PIN_PD06 >> 5, PIN_PD06 & 0x1f, 1, PINMUX_PD06I_CAN1_TX & 0xf}, 3008 | #endif 3009 | #if defined(PINMUX_PD07I_CAN1_TX) && !defined(IGNORE_PIN_PD07) 3010 | {PIN_PD07 >> 5, PIN_PD07 & 0x1f, 1, PINMUX_PD07I_CAN1_TX & 0xf}, 3011 | #endif 3012 | #if defined(PINMUX_PD08I_CAN1_TX) && !defined(IGNORE_PIN_PD08) 3013 | {PIN_PD08 >> 5, PIN_PD08 & 0x1f, 1, PINMUX_PD08I_CAN1_TX & 0xf}, 3014 | #endif 3015 | #if defined(PINMUX_PD09I_CAN1_TX) && !defined(IGNORE_PIN_PD09) 3016 | {PIN_PD09 >> 5, PIN_PD09 & 0x1f, 1, PINMUX_PD09I_CAN1_TX & 0xf}, 3017 | #endif 3018 | #if defined(PINMUX_PD10I_CAN1_TX) && !defined(IGNORE_PIN_PD10) 3019 | {PIN_PD10 >> 5, PIN_PD10 & 0x1f, 1, PINMUX_PD10I_CAN1_TX & 0xf}, 3020 | #endif 3021 | #if defined(PINMUX_PD11I_CAN1_TX) && !defined(IGNORE_PIN_PD11) 3022 | {PIN_PD11 >> 5, PIN_PD11 & 0x1f, 1, PINMUX_PD11I_CAN1_TX & 0xf}, 3023 | #endif 3024 | #if defined(PINMUX_PD12I_CAN1_TX) && !defined(IGNORE_PIN_PD12) 3025 | {PIN_PD12 >> 5, PIN_PD12 & 0x1f, 1, PINMUX_PD12I_CAN1_TX & 0xf}, 3026 | #endif 3027 | #if defined(PINMUX_PD13I_CAN1_TX) && !defined(IGNORE_PIN_PD13) 3028 | {PIN_PD13 >> 5, PIN_PD13 & 0x1f, 1, PINMUX_PD13I_CAN1_TX & 0xf}, 3029 | #endif 3030 | #if defined(PINMUX_PD14I_CAN1_TX) && !defined(IGNORE_PIN_PD14) 3031 | {PIN_PD14 >> 5, PIN_PD14 & 0x1f, 1, PINMUX_PD14I_CAN1_TX & 0xf}, 3032 | #endif 3033 | #if defined(PINMUX_PD15I_CAN1_TX) && !defined(IGNORE_PIN_PD15) 3034 | {PIN_PD15 >> 5, PIN_PD15 & 0x1f, 1, PINMUX_PD15I_CAN1_TX & 0xf}, 3035 | #endif 3036 | #if defined(PINMUX_PD16I_CAN1_TX) && !defined(IGNORE_PIN_PD16) 3037 | {PIN_PD16 >> 5, PIN_PD16 & 0x1f, 1, PINMUX_PD16I_CAN1_TX & 0xf}, 3038 | #endif 3039 | #if defined(PINMUX_PD17I_CAN1_TX) && !defined(IGNORE_PIN_PD17) 3040 | {PIN_PD17 >> 5, PIN_PD17 & 0x1f, 1, PINMUX_PD17I_CAN1_TX & 0xf}, 3041 | #endif 3042 | #if defined(PINMUX_PD18I_CAN1_TX) && !defined(IGNORE_PIN_PD18) 3043 | {PIN_PD18 >> 5, PIN_PD18 & 0x1f, 1, PINMUX_PD18I_CAN1_TX & 0xf}, 3044 | #endif 3045 | #if defined(PINMUX_PD19I_CAN1_TX) && !defined(IGNORE_PIN_PD19) 3046 | {PIN_PD19 >> 5, PIN_PD19 & 0x1f, 1, PINMUX_PD19I_CAN1_TX & 0xf}, 3047 | #endif 3048 | #if defined(PINMUX_PD20I_CAN1_TX) && !defined(IGNORE_PIN_PD20) 3049 | {PIN_PD20 >> 5, PIN_PD20 & 0x1f, 1, PINMUX_PD20I_CAN1_TX & 0xf}, 3050 | #endif 3051 | #if defined(PINMUX_PD21I_CAN1_TX) && !defined(IGNORE_PIN_PD21) 3052 | {PIN_PD21 >> 5, PIN_PD21 & 0x1f, 1, PINMUX_PD21I_CAN1_TX & 0xf}, 3053 | #endif 3054 | #if defined(PINMUX_PD22I_CAN1_TX) && !defined(IGNORE_PIN_PD22) 3055 | {PIN_PD22 >> 5, PIN_PD22 & 0x1f, 1, PINMUX_PD22I_CAN1_TX & 0xf}, 3056 | #endif 3057 | #if defined(PINMUX_PD23I_CAN1_TX) && !defined(IGNORE_PIN_PD23) 3058 | {PIN_PD23 >> 5, PIN_PD23 & 0x1f, 1, PINMUX_PD23I_CAN1_TX & 0xf}, 3059 | #endif 3060 | #if defined(PINMUX_PD24I_CAN1_TX) && !defined(IGNORE_PIN_PD24) 3061 | {PIN_PD24 >> 5, PIN_PD24 & 0x1f, 1, PINMUX_PD24I_CAN1_TX & 0xf}, 3062 | #endif 3063 | #if defined(PINMUX_PD25I_CAN1_TX) && !defined(IGNORE_PIN_PD25) 3064 | {PIN_PD25 >> 5, PIN_PD25 & 0x1f, 1, PINMUX_PD25I_CAN1_TX & 0xf}, 3065 | #endif 3066 | #if defined(PINMUX_PD26I_CAN1_TX) && !defined(IGNORE_PIN_PD26) 3067 | {PIN_PD26 >> 5, PIN_PD26 & 0x1f, 1, PINMUX_PD26I_CAN1_TX & 0xf}, 3068 | #endif 3069 | #if defined(PINMUX_PD27I_CAN1_TX) && !defined(IGNORE_PIN_PD27) 3070 | {PIN_PD27 >> 5, PIN_PD27 & 0x1f, 1, PINMUX_PD27I_CAN1_TX & 0xf}, 3071 | #endif 3072 | #if defined(PINMUX_PD28I_CAN1_TX) && !defined(IGNORE_PIN_PD28) 3073 | {PIN_PD28 >> 5, PIN_PD28 & 0x1f, 1, PINMUX_PD28I_CAN1_TX & 0xf}, 3074 | #endif 3075 | #if defined(PINMUX_PD29I_CAN1_TX) && !defined(IGNORE_PIN_PD29) 3076 | {PIN_PD29 >> 5, PIN_PD29 & 0x1f, 1, PINMUX_PD29I_CAN1_TX & 0xf}, 3077 | #endif 3078 | #if defined(PINMUX_PD30I_CAN1_TX) && !defined(IGNORE_PIN_PD30) 3079 | {PIN_PD30 >> 5, PIN_PD30 & 0x1f, 1, PINMUX_PD30I_CAN1_TX & 0xf}, 3080 | #endif 3081 | #if defined(PINMUX_PD31I_CAN1_TX) && !defined(IGNORE_PIN_PD31) 3082 | {PIN_PD31 >> 5, PIN_PD31 & 0x1f, 1, PINMUX_PD31I_CAN1_TX & 0xf}, 3083 | #endif 3084 | }; 3085 | -------------------------------------------------------------------------------- /src/ESP32SJA1000.cpp: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #ifdef ARDUINO_ARCH_ESP32 5 | 6 | #include "esp_intr.h" 7 | #include "soc/dport_reg.h" 8 | #include "driver/gpio.h" 9 | 10 | #include "ESP32SJA1000.h" 11 | 12 | #define REG_BASE 0x3ff6b000 13 | 14 | #define REG_MOD 0x00 15 | #define REG_CMR 0x01 16 | #define REG_SR 0x02 17 | #define REG_IR 0x03 18 | #define REG_IER 0x04 19 | 20 | #define REG_BTR0 0x06 21 | #define REG_BTR1 0x07 22 | #define REG_OCR 0x08 23 | 24 | #define REG_ALC 0x0b 25 | #define REG_ECC 0x0c 26 | #define REG_EWLR 0x0d 27 | #define REG_RXERR 0x0e 28 | #define REG_TXERR 0x0f 29 | #define REG_SFF 0x10 30 | #define REG_EFF 0x10 31 | #define REG_ACRn(n) (0x10 + n) 32 | #define REG_AMRn(n) (0x14 + n) 33 | 34 | #define REG_CDR 0x1F 35 | 36 | 37 | ESP32SJA1000Class::ESP32SJA1000Class() : 38 | CANControllerClass(), 39 | _rxPin(DEFAULT_CAN_RX_PIN), 40 | _txPin(DEFAULT_CAN_TX_PIN), 41 | _loopback(false), 42 | _intrHandle(NULL) 43 | { 44 | } 45 | 46 | ESP32SJA1000Class::~ESP32SJA1000Class() 47 | { 48 | } 49 | 50 | int ESP32SJA1000Class::begin(long baudRate) 51 | { 52 | CANControllerClass::begin(baudRate); 53 | 54 | _loopback = false; 55 | 56 | DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST); 57 | DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN); 58 | 59 | // RX pin 60 | gpio_set_direction(_rxPin, GPIO_MODE_INPUT); 61 | gpio_matrix_in(_rxPin, CAN_RX_IDX, 0); 62 | gpio_pad_select_gpio(_rxPin); 63 | 64 | // TX pin 65 | gpio_set_direction(_txPin, GPIO_MODE_OUTPUT); 66 | gpio_matrix_out(_txPin, CAN_TX_IDX, 0, 0); 67 | gpio_pad_select_gpio(_txPin); 68 | 69 | modifyRegister(REG_CDR, 0x80, 0x80); // pelican mode 70 | modifyRegister(REG_BTR0, 0xc0, 0x40); // SJW = 1 71 | modifyRegister(REG_BTR1, 0x70, 0x10); // TSEG2 = 1 72 | 73 | switch (baudRate) { 74 | case (long)1000E3: 75 | modifyRegister(REG_BTR1, 0x0f, 0x04); 76 | modifyRegister(REG_BTR0, 0x3f, 4); 77 | break; 78 | 79 | case (long)500E3: 80 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 81 | modifyRegister(REG_BTR0, 0x3f, 4); 82 | break; 83 | 84 | case (long)250E3: 85 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 86 | modifyRegister(REG_BTR0, 0x3f, 9); 87 | break; 88 | 89 | case (long)200E3: 90 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 91 | modifyRegister(REG_BTR0, 0x3f, 12); 92 | break; 93 | 94 | case (long)125E3: 95 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 96 | modifyRegister(REG_BTR0, 0x3f, 19); 97 | break; 98 | 99 | case (long)100E3: 100 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 101 | modifyRegister(REG_BTR0, 0x3f, 24); 102 | break; 103 | 104 | case (long)80E3: 105 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 106 | modifyRegister(REG_BTR0, 0x3f, 30); 107 | break; 108 | 109 | case (long)50E3: 110 | modifyRegister(REG_BTR1, 0x0f, 0x0c); 111 | modifyRegister(REG_BTR0, 0x3f, 49); 112 | break; 113 | 114 | /* 115 | Due to limitations in ESP32 hardware and/or RTOS software, baudrate can't be lower than 50kbps. 116 | See https://esp32.com/viewtopic.php?t=2142 117 | */ 118 | default: 119 | return 0; 120 | break; 121 | } 122 | 123 | modifyRegister(REG_BTR1, 0x80, 0x80); // SAM = 1 124 | writeRegister(REG_IER, 0xff); // enable all interrupts 125 | 126 | // set filter to allow anything 127 | writeRegister(REG_ACRn(0), 0x00); 128 | writeRegister(REG_ACRn(1), 0x00); 129 | writeRegister(REG_ACRn(2), 0x00); 130 | writeRegister(REG_ACRn(3), 0x00); 131 | writeRegister(REG_AMRn(0), 0xff); 132 | writeRegister(REG_AMRn(1), 0xff); 133 | writeRegister(REG_AMRn(2), 0xff); 134 | writeRegister(REG_AMRn(3), 0xff); 135 | 136 | modifyRegister(REG_OCR, 0x03, 0x02); // normal output mode 137 | // reset error counters 138 | writeRegister(REG_TXERR, 0x00); 139 | writeRegister(REG_RXERR, 0x00); 140 | 141 | // clear errors and interrupts 142 | readRegister(REG_ECC); 143 | readRegister(REG_IR); 144 | 145 | // normal mode 146 | modifyRegister(REG_MOD, 0x08, 0x08); 147 | modifyRegister(REG_MOD, 0x17, 0x00); 148 | 149 | return 1; 150 | } 151 | 152 | void ESP32SJA1000Class::end() 153 | { 154 | if (_intrHandle) { 155 | esp_intr_free(_intrHandle); 156 | _intrHandle = NULL; 157 | } 158 | 159 | DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_CAN_RST); 160 | DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_CAN_CLK_EN); 161 | 162 | CANControllerClass::end(); 163 | } 164 | 165 | int ESP32SJA1000Class::endPacket() 166 | { 167 | if (!CANControllerClass::endPacket()) { 168 | return 0; 169 | } 170 | 171 | // wait for TX buffer to free 172 | while ((readRegister(REG_SR) & 0x04) != 0x04) { 173 | yield(); 174 | } 175 | 176 | int dataReg; 177 | 178 | if (_txExtended) { 179 | writeRegister(REG_EFF, 0x80 | (_txRtr ? 0x40 : 0x00) | (0x0f & _txLength)); 180 | writeRegister(REG_EFF + 1, _txId >> 21); 181 | writeRegister(REG_EFF + 2, _txId >> 13); 182 | writeRegister(REG_EFF + 3, _txId >> 5); 183 | writeRegister(REG_EFF + 4, _txId << 3); 184 | 185 | dataReg = REG_EFF + 5; 186 | } else { 187 | writeRegister(REG_SFF, (_txRtr ? 0x40 : 0x00) | (0x0f & _txLength)); 188 | writeRegister(REG_SFF + 1, _txId >> 3); 189 | writeRegister(REG_SFF + 2, _txId << 5); 190 | 191 | dataReg = REG_SFF + 3; 192 | } 193 | 194 | for (int i = 0; i < _txLength; i++) { 195 | writeRegister(dataReg + i, _txData[i]); 196 | } 197 | 198 | if ( _loopback) { 199 | // self reception request 200 | modifyRegister(REG_CMR, 0x1f, 0x10); 201 | } else { 202 | // transmit request 203 | modifyRegister(REG_CMR, 0x1f, 0x01); 204 | } 205 | 206 | // wait for TX complete 207 | while ((readRegister(REG_SR) & 0x08) != 0x08) { 208 | if (readRegister(REG_ECC) == 0xd9) { 209 | modifyRegister(REG_CMR, 0x1f, 0x02); // error, abort 210 | return 0; 211 | } 212 | yield(); 213 | } 214 | 215 | return 1; 216 | } 217 | 218 | int ESP32SJA1000Class::parsePacket() 219 | { 220 | if ((readRegister(REG_SR) & 0x01) != 0x01) { 221 | // no packet 222 | return 0; 223 | } 224 | 225 | _rxExtended = (readRegister(REG_SFF) & 0x80) ? true : false; 226 | _rxRtr = (readRegister(REG_SFF) & 0x40) ? true : false; 227 | _rxDlc = (readRegister(REG_SFF) & 0x0f); 228 | _rxIndex = 0; 229 | 230 | int dataReg; 231 | 232 | if (_rxExtended) { 233 | _rxId = (readRegister(REG_EFF + 1) << 21) | 234 | (readRegister(REG_EFF + 2) << 13) | 235 | (readRegister(REG_EFF + 3) << 5) | 236 | (readRegister(REG_EFF + 4) >> 3); 237 | 238 | dataReg = REG_EFF + 5; 239 | } else { 240 | _rxId = (readRegister(REG_SFF + 1) << 3) | ((readRegister(REG_SFF + 2) >> 5) & 0x07); 241 | 242 | dataReg = REG_SFF + 3; 243 | } 244 | 245 | if (_rxRtr) { 246 | _rxLength = 0; 247 | } else { 248 | _rxLength = _rxDlc; 249 | 250 | for (int i = 0; i < _rxLength; i++) { 251 | _rxData[i] = readRegister(dataReg + i); 252 | } 253 | } 254 | 255 | // release RX buffer 256 | modifyRegister(REG_CMR, 0x04, 0x04); 257 | 258 | return _rxDlc; 259 | } 260 | 261 | void ESP32SJA1000Class::onReceive(void(*callback)(int)) 262 | { 263 | CANControllerClass::onReceive(callback); 264 | 265 | if (_intrHandle) { 266 | esp_intr_free(_intrHandle); 267 | _intrHandle = NULL; 268 | } 269 | 270 | if (callback) { 271 | esp_intr_alloc(ETS_CAN_INTR_SOURCE, 0, ESP32SJA1000Class::onInterrupt, this, &_intrHandle); 272 | } 273 | } 274 | 275 | int ESP32SJA1000Class::filter(int id, int mask) 276 | { 277 | id &= 0x7ff; 278 | mask = ~(mask & 0x7ff); 279 | 280 | modifyRegister(REG_MOD, 0x17, 0x01); // reset 281 | 282 | writeRegister(REG_ACRn(0), id >> 3); 283 | writeRegister(REG_ACRn(1), id << 5); 284 | writeRegister(REG_ACRn(2), 0x00); 285 | writeRegister(REG_ACRn(3), 0x00); 286 | 287 | writeRegister(REG_AMRn(0), mask >> 3); 288 | writeRegister(REG_AMRn(1), (mask << 5) | 0x1f); 289 | writeRegister(REG_AMRn(2), 0xff); 290 | writeRegister(REG_AMRn(3), 0xff); 291 | 292 | modifyRegister(REG_MOD, 0x17, 0x00); // normal 293 | 294 | return 1; 295 | } 296 | 297 | int ESP32SJA1000Class::filterExtended(long id, long mask) 298 | { 299 | id &= 0x1FFFFFFF; 300 | mask &= ~(mask & 0x1FFFFFFF); 301 | 302 | modifyRegister(REG_MOD, 0x17, 0x01); // reset 303 | 304 | writeRegister(REG_ACRn(0), id >> 21); 305 | writeRegister(REG_ACRn(1), id >> 13); 306 | writeRegister(REG_ACRn(2), id >> 5); 307 | writeRegister(REG_ACRn(3), id << 5); 308 | 309 | writeRegister(REG_AMRn(0), mask >> 21); 310 | writeRegister(REG_AMRn(1), mask >> 13); 311 | writeRegister(REG_AMRn(2), mask >> 5); 312 | writeRegister(REG_AMRn(3), (mask << 5) | 0x1f); 313 | 314 | modifyRegister(REG_MOD, 0x17, 0x00); // normal 315 | 316 | return 1; 317 | } 318 | 319 | int ESP32SJA1000Class::observe() 320 | { 321 | modifyRegister(REG_MOD, 0x17, 0x01); // reset 322 | modifyRegister(REG_MOD, 0x17, 0x02); // observe 323 | 324 | return 1; 325 | } 326 | 327 | int ESP32SJA1000Class::loopback() 328 | { 329 | _loopback = true; 330 | 331 | modifyRegister(REG_MOD, 0x17, 0x01); // reset 332 | modifyRegister(REG_MOD, 0x17, 0x04); // self test mode 333 | 334 | return 1; 335 | } 336 | 337 | int ESP32SJA1000Class::sleep() 338 | { 339 | modifyRegister(REG_MOD, 0x1f, 0x10); 340 | 341 | return 1; 342 | } 343 | 344 | int ESP32SJA1000Class::wakeup() 345 | { 346 | modifyRegister(REG_MOD, 0x1f, 0x00); 347 | 348 | return 1; 349 | } 350 | 351 | void ESP32SJA1000Class::setPins(int rx, int tx) 352 | { 353 | _rxPin = (gpio_num_t)rx; 354 | _txPin = (gpio_num_t)tx; 355 | } 356 | 357 | void ESP32SJA1000Class::dumpRegisters(Stream& out) 358 | { 359 | for (int i = 0; i < 32; i++) { 360 | byte b = readRegister(i); 361 | 362 | out.print("0x"); 363 | if (i < 16) { 364 | out.print('0'); 365 | } 366 | out.print(i, HEX); 367 | out.print(": 0x"); 368 | if (b < 16) { 369 | out.print('0'); 370 | } 371 | out.println(b, HEX); 372 | } 373 | } 374 | 375 | void ESP32SJA1000Class::handleInterrupt() 376 | { 377 | uint8_t ir = readRegister(REG_IR); 378 | 379 | if (ir & 0x01) { 380 | // received packet, parse and call callback 381 | parsePacket(); 382 | 383 | _onReceive(available()); 384 | } 385 | } 386 | 387 | uint8_t ESP32SJA1000Class::readRegister(uint8_t address) 388 | { 389 | volatile uint32_t* reg = (volatile uint32_t*)(REG_BASE + address * 4); 390 | 391 | return *reg; 392 | } 393 | 394 | void ESP32SJA1000Class::modifyRegister(uint8_t address, uint8_t mask, uint8_t value) 395 | { 396 | volatile uint32_t* reg = (volatile uint32_t*)(REG_BASE + address * 4); 397 | 398 | *reg = (*reg & ~mask) | value; 399 | } 400 | 401 | void ESP32SJA1000Class::writeRegister(uint8_t address, uint8_t value) 402 | { 403 | volatile uint32_t* reg = (volatile uint32_t*)(REG_BASE + address * 4); 404 | 405 | *reg = value; 406 | } 407 | 408 | void ESP32SJA1000Class::onInterrupt(void* arg) 409 | { 410 | ((ESP32SJA1000Class*)arg)->handleInterrupt(); 411 | } 412 | 413 | ESP32SJA1000Class CAN; 414 | 415 | #endif 416 | -------------------------------------------------------------------------------- /src/ESP32SJA1000.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #ifdef ARDUINO_ARCH_ESP32 5 | 6 | #ifndef ESP32_SJA1000_H 7 | #define ESP32_SJA1000_H 8 | 9 | #include "CANController.h" 10 | 11 | #define DEFAULT_CAN_RX_PIN GPIO_NUM_4 12 | #define DEFAULT_CAN_TX_PIN GPIO_NUM_5 13 | 14 | class ESP32SJA1000Class : public CANControllerClass { 15 | 16 | public: 17 | ESP32SJA1000Class(); 18 | virtual ~ESP32SJA1000Class(); 19 | 20 | virtual int begin(long baudRate); 21 | virtual void end(); 22 | 23 | virtual int endPacket(); 24 | 25 | virtual int parsePacket(); 26 | 27 | virtual void onReceive(void(*callback)(int)); 28 | 29 | using CANControllerClass::filter; 30 | virtual int filter(int id, int mask); 31 | using CANControllerClass::filterExtended; 32 | virtual int filterExtended(long id, long mask); 33 | 34 | virtual int observe(); 35 | virtual int loopback(); 36 | virtual int sleep(); 37 | virtual int wakeup(); 38 | 39 | void setPins(int rx, int tx); 40 | 41 | void dumpRegisters(Stream& out); 42 | 43 | private: 44 | void reset(); 45 | 46 | void handleInterrupt(); 47 | 48 | uint8_t readRegister(uint8_t address); 49 | void modifyRegister(uint8_t address, uint8_t mask, uint8_t value); 50 | void writeRegister(uint8_t address, uint8_t value); 51 | 52 | static void onInterrupt(void* arg); 53 | 54 | private: 55 | gpio_num_t _rxPin; 56 | gpio_num_t _txPin; 57 | bool _loopback; 58 | intr_handle_t _intrHandle; 59 | }; 60 | 61 | extern ESP32SJA1000Class CAN; 62 | 63 | #endif 64 | 65 | #endif 66 | -------------------------------------------------------------------------------- /src/MCP2515.cpp: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #if !defined(ARDUINO_ARCH_ESP32) && !defined(ARDUINO_FEATHER_M4_CAN) 5 | 6 | #include "MCP2515.h" 7 | 8 | #define REG_BFPCTRL 0x0c 9 | #define REG_TXRTSCTRL 0x0d 10 | 11 | #define REG_CANCTRL 0x0f 12 | 13 | #define REG_CNF3 0x28 14 | #define REG_CNF2 0x29 15 | #define REG_CNF1 0x2a 16 | 17 | #define REG_CANINTE 0x2b 18 | #define REG_CANINTF 0x2c 19 | 20 | #define FLAG_RXnIE(n) (0x01 << n) 21 | #define FLAG_RXnIF(n) (0x01 << n) 22 | #define FLAG_TXnIF(n) (0x04 << n) 23 | 24 | #define REG_RXFnSIDH(n) (0x00 + (n * 4)) 25 | #define REG_RXFnSIDL(n) (0x01 + (n * 4)) 26 | #define REG_RXFnEID8(n) (0x02 + (n * 4)) 27 | #define REG_RXFnEID0(n) (0x03 + (n * 4)) 28 | 29 | #define REG_RXMnSIDH(n) (0x20 + (n * 0x04)) 30 | #define REG_RXMnSIDL(n) (0x21 + (n * 0x04)) 31 | #define REG_RXMnEID8(n) (0x22 + (n * 0x04)) 32 | #define REG_RXMnEID0(n) (0x23 + (n * 0x04)) 33 | 34 | #define REG_TXBnCTRL(n) (0x30 + (n * 0x10)) 35 | #define REG_TXBnSIDH(n) (0x31 + (n * 0x10)) 36 | #define REG_TXBnSIDL(n) (0x32 + (n * 0x10)) 37 | #define REG_TXBnEID8(n) (0x33 + (n * 0x10)) 38 | #define REG_TXBnEID0(n) (0x34 + (n * 0x10)) 39 | #define REG_TXBnDLC(n) (0x35 + (n * 0x10)) 40 | #define REG_TXBnD0(n) (0x36 + (n * 0x10)) 41 | 42 | #define REG_RXBnCTRL(n) (0x60 + (n * 0x10)) 43 | #define REG_RXBnSIDH(n) (0x61 + (n * 0x10)) 44 | #define REG_RXBnSIDL(n) (0x62 + (n * 0x10)) 45 | #define REG_RXBnEID8(n) (0x63 + (n * 0x10)) 46 | #define REG_RXBnEID0(n) (0x64 + (n * 0x10)) 47 | #define REG_RXBnDLC(n) (0x65 + (n * 0x10)) 48 | #define REG_RXBnD0(n) (0x66 + (n * 0x10)) 49 | 50 | #define FLAG_IDE 0x08 51 | #define FLAG_SRR 0x10 52 | #define FLAG_RTR 0x40 53 | #define FLAG_EXIDE 0x08 54 | 55 | #define FLAG_RXM0 0x20 56 | #define FLAG_RXM1 0x40 57 | 58 | 59 | MCP2515Class::MCP2515Class() : 60 | CANControllerClass(), 61 | _spiSettings(10E6, MSBFIRST, SPI_MODE0), 62 | _csPin(MCP2515_DEFAULT_CS_PIN), 63 | _intPin(MCP2515_DEFAULT_INT_PIN), 64 | _clockFrequency(MCP2515_DEFAULT_CLOCK_FREQUENCY) 65 | { 66 | } 67 | 68 | MCP2515Class::~MCP2515Class() 69 | { 70 | } 71 | 72 | int MCP2515Class::begin(long baudRate) 73 | { 74 | CANControllerClass::begin(baudRate); 75 | 76 | pinMode(_csPin, OUTPUT); 77 | 78 | // start SPI 79 | SPI.begin(); 80 | 81 | reset(); 82 | 83 | writeRegister(REG_CANCTRL, 0x80); 84 | if (readRegister(REG_CANCTRL) != 0x80) { 85 | return 0; 86 | } 87 | 88 | const struct { 89 | long clockFrequency; 90 | long baudRate; 91 | uint8_t cnf[3]; 92 | } CNF_MAPPER[] = { 93 | { (long)8E6, (long)1000E3, { 0x00, 0x80, 0x00 } }, 94 | { (long)8E6, (long)500E3, { 0x00, 0x90, 0x02 } }, 95 | { (long)8E6, (long)250E3, { 0x00, 0xb1, 0x05 } }, 96 | { (long)8E6, (long)200E3, { 0x00, 0xb4, 0x06 } }, 97 | { (long)8E6, (long)125E3, { 0x01, 0xb1, 0x05 } }, 98 | { (long)8E6, (long)100E3, { 0x01, 0xb4, 0x06 } }, 99 | { (long)8E6, (long)80E3, { 0x01, 0xbf, 0x07 } }, 100 | { (long)8E6, (long)50E3, { 0x03, 0xb4, 0x06 } }, 101 | { (long)8E6, (long)40E3, { 0x03, 0xbf, 0x07 } }, 102 | { (long)8E6, (long)20E3, { 0x07, 0xbf, 0x07 } }, 103 | { (long)8E6, (long)10E3, { 0x0f, 0xbf, 0x07 } }, 104 | { (long)8E6, (long)5E3, { 0x1f, 0xbf, 0x07 } }, 105 | 106 | { (long)16E6, (long)1000E3, { 0x00, 0xd0, 0x82 } }, 107 | { (long)16E6, (long)500E3, { 0x00, 0xf0, 0x86 } }, 108 | { (long)16E6, (long)250E3, { 0x41, 0xf1, 0x85 } }, 109 | { (long)16E6, (long)200E3, { 0x01, 0xfa, 0x87 } }, 110 | { (long)16E6, (long)125E3, { 0x03, 0xf0, 0x86 } }, 111 | { (long)16E6, (long)100E3, { 0x03, 0xfa, 0x87 } }, 112 | { (long)16E6, (long)80E3, { 0x03, 0xff, 0x87 } }, 113 | { (long)16E6, (long)50E3, { 0x07, 0xfa, 0x87 } }, 114 | { (long)16E6, (long)40E3, { 0x07, 0xff, 0x87 } }, 115 | { (long)16E6, (long)20E3, { 0x0f, 0xff, 0x87 } }, 116 | { (long)16E6, (long)10E3, { 0x1f, 0xff, 0x87 } }, 117 | { (long)16E6, (long)5E3, { 0x3f, 0xff, 0x87 } }, 118 | }; 119 | 120 | const uint8_t* cnf = NULL; 121 | 122 | for (unsigned int i = 0; i < (sizeof(CNF_MAPPER) / sizeof(CNF_MAPPER[0])); i++) { 123 | if (CNF_MAPPER[i].clockFrequency == _clockFrequency && CNF_MAPPER[i].baudRate == baudRate) { 124 | cnf = CNF_MAPPER[i].cnf; 125 | break; 126 | } 127 | } 128 | 129 | if (cnf == NULL) { 130 | return 0; 131 | } 132 | 133 | writeRegister(REG_CNF1, cnf[0]); 134 | writeRegister(REG_CNF2, cnf[1]); 135 | writeRegister(REG_CNF3, cnf[2]); 136 | 137 | writeRegister(REG_CANINTE, FLAG_RXnIE(1) | FLAG_RXnIE(0)); 138 | writeRegister(REG_BFPCTRL, 0x00); 139 | writeRegister(REG_TXRTSCTRL, 0x00); 140 | writeRegister(REG_RXBnCTRL(0), FLAG_RXM1 | FLAG_RXM0); 141 | writeRegister(REG_RXBnCTRL(1), FLAG_RXM1 | FLAG_RXM0); 142 | 143 | writeRegister(REG_CANCTRL, 0x00); 144 | if (readRegister(REG_CANCTRL) != 0x00) { 145 | return 0; 146 | } 147 | 148 | return 1; 149 | } 150 | 151 | void MCP2515Class::end() 152 | { 153 | SPI.end(); 154 | 155 | CANControllerClass::end(); 156 | } 157 | 158 | int MCP2515Class::endPacket() 159 | { 160 | if (!CANControllerClass::endPacket()) { 161 | return 0; 162 | } 163 | 164 | int n = 0; 165 | 166 | if (_txExtended) { 167 | writeRegister(REG_TXBnSIDH(n), _txId >> 21); 168 | writeRegister(REG_TXBnSIDL(n), (((_txId >> 18) & 0x07) << 5) | FLAG_EXIDE | ((_txId >> 16) & 0x03)); 169 | writeRegister(REG_TXBnEID8(n), (_txId >> 8) & 0xff); 170 | writeRegister(REG_TXBnEID0(n), _txId & 0xff); 171 | } else { 172 | writeRegister(REG_TXBnSIDH(n), _txId >> 3); 173 | writeRegister(REG_TXBnSIDL(n), _txId << 5); 174 | writeRegister(REG_TXBnEID8(n), 0x00); 175 | writeRegister(REG_TXBnEID0(n), 0x00); 176 | } 177 | 178 | if (_txRtr) { 179 | writeRegister(REG_TXBnDLC(n), 0x40 | _txLength); 180 | } else { 181 | writeRegister(REG_TXBnDLC(n), _txLength); 182 | 183 | for (int i = 0; i < _txLength; i++) { 184 | writeRegister(REG_TXBnD0(n) + i, _txData[i]); 185 | } 186 | } 187 | 188 | writeRegister(REG_TXBnCTRL(n), 0x08); 189 | 190 | bool aborted = false; 191 | 192 | while (readRegister(REG_TXBnCTRL(n)) & 0x08) { 193 | if (readRegister(REG_TXBnCTRL(n)) & 0x10) { 194 | // abort 195 | aborted = true; 196 | 197 | modifyRegister(REG_CANCTRL, 0x10, 0x10); 198 | } 199 | 200 | yield(); 201 | } 202 | 203 | if (aborted) { 204 | // clear abort command 205 | modifyRegister(REG_CANCTRL, 0x10, 0x00); 206 | } 207 | 208 | modifyRegister(REG_CANINTF, FLAG_TXnIF(n), 0x00); 209 | 210 | return (readRegister(REG_TXBnCTRL(n)) & 0x70) ? 0 : 1; 211 | } 212 | 213 | int MCP2515Class::parsePacket() 214 | { 215 | int n; 216 | 217 | uint8_t intf = readRegister(REG_CANINTF); 218 | 219 | if (intf & FLAG_RXnIF(0)) { 220 | n = 0; 221 | } else if (intf & FLAG_RXnIF(1)) { 222 | n = 1; 223 | } else { 224 | _rxId = -1; 225 | _rxExtended = false; 226 | _rxRtr = false; 227 | _rxLength = 0; 228 | return 0; 229 | } 230 | 231 | _rxExtended = (readRegister(REG_RXBnSIDL(n)) & FLAG_IDE) ? true : false; 232 | 233 | uint32_t idA = ((readRegister(REG_RXBnSIDH(n)) << 3) & 0x07f8) | ((readRegister(REG_RXBnSIDL(n)) >> 5) & 0x07); 234 | if (_rxExtended) { 235 | uint32_t idB = (((uint32_t)(readRegister(REG_RXBnSIDL(n)) & 0x03) << 16) & 0x30000) | ((readRegister(REG_RXBnEID8(n)) << 8) & 0xff00) | readRegister(REG_RXBnEID0(n)); 236 | 237 | _rxId = (idA << 18) | idB; 238 | _rxRtr = (readRegister(REG_RXBnDLC(n)) & FLAG_RTR) ? true : false; 239 | } else { 240 | _rxId = idA; 241 | _rxRtr = (readRegister(REG_RXBnSIDL(n)) & FLAG_SRR) ? true : false; 242 | } 243 | _rxDlc = readRegister(REG_RXBnDLC(n)) & 0x0f; 244 | _rxIndex = 0; 245 | 246 | if (_rxRtr) { 247 | _rxLength = 0; 248 | } else { 249 | _rxLength = _rxDlc; 250 | 251 | for (int i = 0; i < _rxLength; i++) { 252 | _rxData[i] = readRegister(REG_RXBnD0(n) + i); 253 | } 254 | } 255 | 256 | modifyRegister(REG_CANINTF, FLAG_RXnIF(n), 0x00); 257 | 258 | return _rxDlc; 259 | } 260 | 261 | void MCP2515Class::onReceive(void(*callback)(int)) 262 | { 263 | CANControllerClass::onReceive(callback); 264 | 265 | pinMode(_intPin, INPUT); 266 | 267 | if (callback) { 268 | #ifndef ESP8266 269 | SPI.usingInterrupt(digitalPinToInterrupt(_intPin)); 270 | #endif 271 | attachInterrupt(digitalPinToInterrupt(_intPin), MCP2515Class::onInterrupt, LOW); 272 | } else { 273 | detachInterrupt(digitalPinToInterrupt(_intPin)); 274 | #ifdef SPI_HAS_NOTUSINGINTERRUPT 275 | SPI.notUsingInterrupt(digitalPinToInterrupt(_intPin)); 276 | #endif 277 | } 278 | } 279 | 280 | int MCP2515Class::filter(int id, int mask) 281 | { 282 | id &= 0x7ff; 283 | mask &= 0x7ff; 284 | 285 | // config mode 286 | writeRegister(REG_CANCTRL, 0x80); 287 | if (readRegister(REG_CANCTRL) != 0x80) { 288 | return 0; 289 | } 290 | 291 | for (int n = 0; n < 2; n++) { 292 | // standard only 293 | writeRegister(REG_RXBnCTRL(n), FLAG_RXM0); 294 | writeRegister(REG_RXBnCTRL(n), FLAG_RXM0); 295 | 296 | writeRegister(REG_RXMnSIDH(n), mask >> 3); 297 | writeRegister(REG_RXMnSIDL(n), mask << 5); 298 | writeRegister(REG_RXMnEID8(n), 0); 299 | writeRegister(REG_RXMnEID0(n), 0); 300 | } 301 | 302 | for (int n = 0; n < 6; n++) { 303 | writeRegister(REG_RXFnSIDH(n), id >> 3); 304 | writeRegister(REG_RXFnSIDL(n), id << 5); 305 | writeRegister(REG_RXFnEID8(n), 0); 306 | writeRegister(REG_RXFnEID0(n), 0); 307 | } 308 | 309 | // normal mode 310 | writeRegister(REG_CANCTRL, 0x00); 311 | if (readRegister(REG_CANCTRL) != 0x00) { 312 | return 0; 313 | } 314 | 315 | return 1; 316 | } 317 | 318 | int MCP2515Class::filterExtended(long id, long mask) 319 | { 320 | id &= 0x1FFFFFFF; 321 | mask &= 0x1FFFFFFF; 322 | 323 | // config mode 324 | writeRegister(REG_CANCTRL, 0x80); 325 | if (readRegister(REG_CANCTRL) != 0x80) { 326 | return 0; 327 | } 328 | 329 | for (int n = 0; n < 2; n++) { 330 | // extended only 331 | writeRegister(REG_RXBnCTRL(n), FLAG_RXM1); 332 | writeRegister(REG_RXBnCTRL(n), FLAG_RXM1); 333 | 334 | writeRegister(REG_RXMnSIDH(n), mask >> 21); 335 | writeRegister(REG_RXMnSIDL(n), (((mask >> 18) & 0x03) << 5) | FLAG_EXIDE | ((mask >> 16) & 0x03)); 336 | writeRegister(REG_RXMnEID8(n), (mask >> 8) & 0xff); 337 | writeRegister(REG_RXMnEID0(n), mask & 0xff); 338 | } 339 | 340 | for (int n = 0; n < 6; n++) { 341 | writeRegister(REG_RXFnSIDH(n), id >> 21); 342 | writeRegister(REG_RXFnSIDL(n), (((id >> 18) & 0x03) << 5) | FLAG_EXIDE | ((id >> 16) & 0x03)); 343 | writeRegister(REG_RXFnEID8(n), (id >> 8) & 0xff); 344 | writeRegister(REG_RXFnEID0(n), id & 0xff); 345 | } 346 | 347 | // normal mode 348 | writeRegister(REG_CANCTRL, 0x00); 349 | if (readRegister(REG_CANCTRL) != 0x00) { 350 | return 0; 351 | } 352 | 353 | return 1; 354 | } 355 | 356 | int MCP2515Class::observe() 357 | { 358 | writeRegister(REG_CANCTRL, 0x80); 359 | if (readRegister(REG_CANCTRL) != 0x80) { 360 | return 0; 361 | } 362 | 363 | return 1; 364 | } 365 | 366 | int MCP2515Class::loopback() 367 | { 368 | writeRegister(REG_CANCTRL, 0x40); 369 | if (readRegister(REG_CANCTRL) != 0x40) { 370 | return 0; 371 | } 372 | 373 | return 1; 374 | } 375 | 376 | int MCP2515Class::sleep() 377 | { 378 | writeRegister(REG_CANCTRL, 0x01); 379 | if (readRegister(REG_CANCTRL) != 0x01) { 380 | return 0; 381 | } 382 | 383 | return 1; 384 | } 385 | 386 | int MCP2515Class::wakeup() 387 | { 388 | writeRegister(REG_CANCTRL, 0x00); 389 | if (readRegister(REG_CANCTRL) != 0x00) { 390 | return 0; 391 | } 392 | 393 | return 1; 394 | } 395 | 396 | void MCP2515Class::setPins(int cs, int irq) 397 | { 398 | _csPin = cs; 399 | _intPin = irq; 400 | } 401 | 402 | void MCP2515Class::setSPIFrequency(uint32_t frequency) 403 | { 404 | _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); 405 | } 406 | 407 | void MCP2515Class::setClockFrequency(long clockFrequency) 408 | { 409 | _clockFrequency = clockFrequency; 410 | } 411 | 412 | void MCP2515Class::dumpRegisters(Stream& out) 413 | { 414 | for (int i = 0; i < 128; i++) { 415 | byte b = readRegister(i); 416 | 417 | out.print("0x"); 418 | if (i < 16) { 419 | out.print('0'); 420 | } 421 | out.print(i, HEX); 422 | out.print(": 0x"); 423 | if (b < 16) { 424 | out.print('0'); 425 | } 426 | out.println(b, HEX); 427 | } 428 | } 429 | 430 | void MCP2515Class::reset() 431 | { 432 | SPI.beginTransaction(_spiSettings); 433 | digitalWrite(_csPin, LOW); 434 | SPI.transfer(0xc0); 435 | digitalWrite(_csPin, HIGH); 436 | SPI.endTransaction(); 437 | 438 | delayMicroseconds(10); 439 | } 440 | 441 | void MCP2515Class::handleInterrupt() 442 | { 443 | if (readRegister(REG_CANINTF) == 0) { 444 | return; 445 | } 446 | 447 | while (parsePacket()) { 448 | _onReceive(available()); 449 | } 450 | } 451 | 452 | uint8_t MCP2515Class::readRegister(uint8_t address) 453 | { 454 | uint8_t value; 455 | 456 | SPI.beginTransaction(_spiSettings); 457 | digitalWrite(_csPin, LOW); 458 | SPI.transfer(0x03); 459 | SPI.transfer(address); 460 | value = SPI.transfer(0x00); 461 | digitalWrite(_csPin, HIGH); 462 | SPI.endTransaction(); 463 | 464 | return value; 465 | } 466 | 467 | void MCP2515Class::modifyRegister(uint8_t address, uint8_t mask, uint8_t value) 468 | { 469 | SPI.beginTransaction(_spiSettings); 470 | digitalWrite(_csPin, LOW); 471 | SPI.transfer(0x05); 472 | SPI.transfer(address); 473 | SPI.transfer(mask); 474 | SPI.transfer(value); 475 | digitalWrite(_csPin, HIGH); 476 | SPI.endTransaction(); 477 | } 478 | 479 | void MCP2515Class::writeRegister(uint8_t address, uint8_t value) 480 | { 481 | SPI.beginTransaction(_spiSettings); 482 | digitalWrite(_csPin, LOW); 483 | SPI.transfer(0x02); 484 | SPI.transfer(address); 485 | SPI.transfer(value); 486 | digitalWrite(_csPin, HIGH); 487 | SPI.endTransaction(); 488 | } 489 | 490 | void MCP2515Class::onInterrupt() 491 | { 492 | CAN.handleInterrupt(); 493 | } 494 | 495 | MCP2515Class CAN; 496 | 497 | #endif 498 | -------------------------------------------------------------------------------- /src/MCP2515.h: -------------------------------------------------------------------------------- 1 | // Copyright (c) Sandeep Mistry. All rights reserved. 2 | // Licensed under the MIT license. See LICENSE file in the project root for full license information. 3 | 4 | #ifndef ARDUINO_ARCH_ESP32 5 | 6 | #ifndef MCP2515_H 7 | #define MCP2515_H 8 | 9 | #include 10 | 11 | #include "CANController.h" 12 | 13 | #define MCP2515_DEFAULT_CLOCK_FREQUENCY 16e6 14 | 15 | #if defined(ARDUINO_ARCH_SAMD) && defined(PIN_SPI_MISO) && defined(PIN_SPI_MOSI) && defined(PIN_SPI_SCK) && (PIN_SPI_MISO == 10) && (PIN_SPI_MOSI == 8) && (PIN_SPI_SCK == 9) 16 | // Arduino MKR board: MKR CAN shield CS is pin 3, INT is pin 7 17 | #define MCP2515_DEFAULT_CS_PIN 3 18 | #define MCP2515_DEFAULT_INT_PIN 7 19 | #else 20 | #define MCP2515_DEFAULT_CS_PIN 10 21 | #define MCP2515_DEFAULT_INT_PIN 2 22 | #endif 23 | 24 | class MCP2515Class : public CANControllerClass { 25 | 26 | public: 27 | MCP2515Class(); 28 | virtual ~MCP2515Class(); 29 | 30 | virtual int begin(long baudRate); 31 | virtual void end(); 32 | 33 | virtual int endPacket(); 34 | 35 | virtual int parsePacket(); 36 | 37 | virtual void onReceive(void(*callback)(int)); 38 | 39 | using CANControllerClass::filter; 40 | virtual int filter(int id, int mask); 41 | using CANControllerClass::filterExtended; 42 | virtual int filterExtended(long id, long mask); 43 | 44 | virtual int observe(); 45 | virtual int loopback(); 46 | virtual int sleep(); 47 | virtual int wakeup(); 48 | 49 | void setPins(int cs = MCP2515_DEFAULT_CS_PIN, int irq = MCP2515_DEFAULT_INT_PIN); 50 | void setSPIFrequency(uint32_t frequency); 51 | void setClockFrequency(long clockFrequency); 52 | 53 | void dumpRegisters(Stream& out); 54 | 55 | private: 56 | void reset(); 57 | 58 | void handleInterrupt(); 59 | 60 | uint8_t readRegister(uint8_t address); 61 | void modifyRegister(uint8_t address, uint8_t mask, uint8_t value); 62 | void writeRegister(uint8_t address, uint8_t value); 63 | 64 | static void onInterrupt(); 65 | 66 | private: 67 | SPISettings _spiSettings; 68 | int _csPin; 69 | int _intPin; 70 | long _clockFrequency; 71 | }; 72 | 73 | extern MCP2515Class CAN; 74 | 75 | #endif 76 | 77 | #endif 78 | --------------------------------------------------------------------------------