├── .gitattributes ├── .gitignore ├── README ├── contrib ├── AppIcon.ico ├── photos │ ├── demo_adafruit.jpg │ ├── demo_firefox.jpg │ ├── demo_google.jpg │ └── demo_nyan.jpg └── tutorial │ ├── assignmenteditor.png │ ├── gpio0diagram.png │ ├── hardwaresetup.png │ ├── importassignments.png │ ├── newproject1.png │ ├── newproject2.png │ ├── newproject3.png │ ├── newproject4.png │ ├── nohardware.png │ ├── pintristate.png │ ├── programmer.png │ ├── tutorial.html │ ├── vjtagserver.png │ └── voltage.png ├── de0-nano ├── DE0_Nano.qsf ├── program.cmd └── rgbmatrix-fpga.qsf ├── processing ├── Chaser │ ├── Chaser.pde │ └── vjtag_client.pde └── Magnify │ ├── Magnify.pde │ └── vjtag_client.pde ├── tcl ├── Useful links.txt ├── run.cmd └── vjtag_server.tcl └── vhdl ├── clk_div.vhd ├── config.vhd ├── jtag_iface.vhd ├── ledctrl.vhd ├── megawizard ├── megawizard_vjtag.cmp ├── megawizard_vjtag.qip ├── megawizard_vjtag.vhd └── megawizard_vjtag_inst.vhd ├── memory.vhd ├── testbenches ├── ledctrl_tb.vhd ├── memory_tb.vhd └── testbench.vhd └── top_level.vhd /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | *.sln merge=union 7 | *.csproj merge=union 8 | *.vbproj merge=union 9 | *.fsproj merge=union 10 | *.dbproj merge=union 11 | 12 | # Standard to msysgit 13 | *.doc diff=astextplain 14 | *.DOC diff=astextplain 15 | *.docx diff=astextplain 16 | *.DOCX diff=astextplain 17 | *.dot diff=astextplain 18 | *.DOT diff=astextplain 19 | *.pdf diff=astextplain 20 | *.PDF diff=astextplain 21 | *.rtf diff=astextplain 22 | *.RTF diff=astextplain 23 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ################# 2 | ## Eclipse 3 | ################# 4 | 5 | *.pydevproject 6 | .project 7 | .metadata 8 | bin/ 9 | tmp/ 10 | *.tmp 11 | *.bak 12 | *.swp 13 | *~.nib 14 | local.properties 15 | .classpath 16 | .settings/ 17 | .loadpath 18 | 19 | # External tool builders 20 | .externalToolBuilders/ 21 | 22 | # Locally stored "Eclipse launch configurations" 23 | *.launch 24 | 25 | # CDT-specific 26 | .cproject 27 | 28 | # PDT-specific 29 | .buildpath 30 | 31 | 32 | ################# 33 | ## Visual Studio 34 | ################# 35 | 36 | ## Ignore Visual Studio temporary files, build results, and 37 | ## files generated by popular Visual Studio add-ons. 38 | 39 | # User-specific files 40 | *.suo 41 | *.user 42 | *.sln.docstates 43 | 44 | # Build results 45 | [Dd]ebug/ 46 | [Rr]elease/ 47 | *_i.c 48 | *_p.c 49 | *.ilk 50 | *.meta 51 | *.obj 52 | *.pch 53 | *.pdb 54 | *.pgc 55 | *.pgd 56 | *.rsp 57 | *.sbr 58 | *.tlb 59 | *.tli 60 | *.tlh 61 | *.tmp 62 | *.vspscc 63 | .builds 64 | *.dotCover 65 | 66 | ## TODO: If you have NuGet Package Restore enabled, uncomment this 67 | #packages/ 68 | 69 | # Visual C++ cache files 70 | ipch/ 71 | *.aps 72 | *.ncb 73 | *.opensdf 74 | *.sdf 75 | 76 | # Visual Studio profiler 77 | *.psess 78 | *.vsp 79 | 80 | # ReSharper is a .NET coding add-in 81 | _ReSharper* 82 | 83 | # Installshield output folder 84 | [Ee]xpress 85 | 86 | # DocProject is a documentation generator add-in 87 | DocProject/buildhelp/ 88 | DocProject/Help/*.HxT 89 | DocProject/Help/*.HxC 90 | DocProject/Help/*.hhc 91 | DocProject/Help/*.hhk 92 | DocProject/Help/*.hhp 93 | DocProject/Help/Html2 94 | DocProject/Help/html 95 | 96 | # Click-Once directory 97 | publish 98 | 99 | # Others 100 | [Bb]in 101 | [Oo]bj 102 | sql 103 | TestResults 104 | *.Cache 105 | ClientBin 106 | stylecop.* 107 | ~$* 108 | *.dbmdl 109 | Generated_Code #added for RIA/Silverlight projects 110 | 111 | # Backup & report files from converting an old project file to a newer 112 | # Visual Studio version. Backup files are not needed, because we have git ;-) 113 | _UpgradeReport_Files/ 114 | Backup*/ 115 | UpgradeLog*.XML 116 | 117 | 118 | 119 | ############ 120 | ## Windows 121 | ############ 122 | 123 | # Windows image file caches 124 | Thumbs.db 125 | 126 | # Folder config file 127 | Desktop.ini 128 | 129 | 130 | ############# 131 | ## Python 132 | ############# 133 | 134 | *.py[co] 135 | 136 | # Packages 137 | *.egg 138 | *.egg-info 139 | dist 140 | build 141 | eggs 142 | parts 143 | bin 144 | var 145 | sdist 146 | develop-eggs 147 | .installed.cfg 148 | 149 | # Installer logs 150 | pip-log.txt 151 | 152 | # Unit test / coverage reports 153 | .coverage 154 | .tox 155 | 156 | #Translations 157 | *.mo 158 | 159 | #Mr Developer 160 | .mr.developer.cfg 161 | 162 | # Mac crap 163 | .DS_Store 164 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | ################################################################ 2 | # # 3 | # Adafruit RGB LED Matrix Display Driver and Client Software # 4 | # # 5 | ################################################################ 6 | 7 | This is a design that will enable use of the RGB LED matrix sold by Adafruit 8 | with an FPGA in order to achieve full-motion graphics across any number of 9 | panels in a variety of configurations. It is written in VHDL and is currently a 10 | work-in-progress. 11 | 12 | Also included in this project is client software that is used to send data to 13 | the circuit running on the FPGA. There are two parts to it. The first part is a 14 | Processing library that provides an easy way to send images to the device. The 15 | second part is a small Tcl server script that interfaces with a ByteBlaster 16 | (through the Altera Tcl API) and provides a vendor-specific JTAG wrapper over 17 | a TCP/IP socket. 18 | 19 | What's included: 20 | * contrib Additional files not required for building the project 21 | * photos Photographs of the design and hardware in use 22 | * tutorial Tutorial on how to setup, build, and use the design 23 | * de0-nano Files specific to the DE0-Nano FPGA dev board 24 | * processing Client library with usage example 25 | * tcl Server script to interface with the virtual JTAG 26 | * vhdl VHDL source code for the design to use on the FPGA 27 | * megawizard Altera Megafunction IP code for the virtual JTAG 28 | * testbenches VHDL to use for simulation of selected entities 29 | 30 | Features implemented: 31 | * Read graphics data from RAM and display it on panel 32 | * Support multiple panels 33 | * Read video data from external device and fill into RAM 34 | * User configurable pixel depth (brightness control) 35 | 36 | Demo videos: 37 | * http://www.youtube.com/watch?v=DWirBxcCs2A 38 | * http://www.youtube.com/watch?v=or1Qpbdxw2o 39 | * http://www.youtube.com/watch?v=0Zrrlw3kZHA 40 | -------------------------------------------------------------------------------- /contrib/AppIcon.ico: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/AppIcon.ico -------------------------------------------------------------------------------- /contrib/photos/demo_adafruit.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/photos/demo_adafruit.jpg -------------------------------------------------------------------------------- /contrib/photos/demo_firefox.jpg: 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/contrib/tutorial/pintristate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/tutorial/pintristate.png -------------------------------------------------------------------------------- /contrib/tutorial/programmer.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/tutorial/programmer.png -------------------------------------------------------------------------------- /contrib/tutorial/tutorial.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 19 | 20 | 21 | 22 | 27 | Controlling the Adafruit 32x16 RGB LED Matrix with a DE0-Nano 28 | 29 | 30 | 31 |

Controlling the Adafruit 32x16 RGB LED Matrix
with a DE0-Nano FPGA Board

32 | 33 |

Adafruit currently sells a really cool 16x32 RGB LED matrix panel in their store that is "designed to be driven by an FPGA or other high speed processor." The purpose of this tutorial is to help you get started driving a small handful of these displays with the DE0-Nano board, which contains a mid-range Altera FPGA.

34 | 35 |

Prerequisites

36 | 37 |

This tutorial assumes that you're already somewhat familiar with electronics, digital logic, editing source code, using IDEs, and installing Windows device drivers.

38 | 39 |

You need to have the Quartus II software installed on your computer. If not, you can download it from Altera's website or install it from the DVD that comes with the DE0-Nano board. You will also need to install the USB-Blaster drivers that enable your computer to communicate with the FPGA (see this short YouTube video).

40 | 41 |

On you are all set up and ready to begin, download the necessary files for this project from its GitHub repository (click on the "ZIP" icon).

42 | 43 |

User configuration

44 | 45 |

Open the file vhdl/config.vhd in a text editor and change line 32 (constant NUM_PANELS...) to indicate the total number of LED panels you have daisy-chained together in your display. For example, if you are using a 1x2 or 2x1 grid, you will want to change the line to:

46 | 47 |

constant NUM_PANELS : integer := 2;

48 | 49 |

You may optionally edit line 33 (constant PIXEL_DEPTH...) in a similar manner to indicate how many bits-per-pixel you want to use. This will affect the level of brightness control available to you later. Finally, save the file!

50 | 51 |

Creating the Quartus II project

52 | 53 |

Start Quartus II and open the "New Project Wizard" from the "File" menu. On the first page, name the project rgbmatrix-fpga (or something similar) and name the top-level entity top_level. Click Next.

54 | 55 | 56 | 57 |

Now we will add the source code files to the project. Click the "..." button to open the file browser and select the .vhd files in the vhdl folder you downloaded earlier (do not include the testbenches directory). Click "..." again and open the megawizard folder. Set the type drop-down menu to "All Files (*.*)" so you can select the .qip, .cmp, and megawizard_vjtag.vhd files (do not include megawizard_vjtag_inst.vhd). Add them to the project and click Next.

58 | 59 | 60 | 61 |

The FPGA chip in use on the DE0-Nano is the Cyclone IV EP4CE22F17C6N. You can find it by setting the device family to "Cyclone IV E", package to "FBGA", pin count to 256, and speed grade to 6. Select the chip and click Next.

62 | 63 | 64 | 65 |

Set the "Simulation" tool name to "ModelSim-Altera" and the format to "VHDL". Leave everything else as "<None>" and click Next.

66 | 67 | 68 | 69 |

Click Finish to create the project!

70 | 71 |

Pin settings

72 | 73 |

Now that the project has been created, you need to change two more settings before we can move on. Go to the Project Navigator panel in the top left area of Quartus and right click on the device ("Cyclone IV E: ..."). Select "Device" from the menu.

74 | 75 | 76 | 77 |

A window will open. Click "Device and Pin Options...". In the left hand side of the new window that comes up, open the "Unused Pins" category. Change the "Reserve all unused pins" settings to "As input tri-stated". This will essentially prevent the unused pins on the FPGA from doing anything unwanted on the DE0-Nano when we program the design.

78 | 79 |

Now select the "Voltage" category. Change the "Default I/O standard" to "3.3-V LVTTL". This is essential to do because the panels will not recognize a signal below this voltage.

80 | 81 | 82 | 83 |

Click OK, then click OK again.

84 | 85 |

Making pin assignments

86 | 87 |

Go to the "Assignments" menu and select "Import Assignments...". Import the de0-nano/rgbmatrix-fpga.qsf file. After you do this, a message should appear in the "System" console tab at the bottom of Quartus: "Import completed. 14 assignments were written (out of 14 read)."

88 | 89 | 90 | 91 |

You can (optionally) customize the pin assignments that were imported by going to the "Assignments" menu and selecting "Assignment Editor". Additional information on the GPIO headers can be found in the DE0-Nano PDF manual (pages 18-20). A machine-readable mapping of FPGA pins to GPIO headers can also be found in the de0-nano/DE0_Nano.qsf file (open it with a text editor).

92 | 93 | 94 | 95 |

Save any changes. Now we are ready to connect the pins on the FPGA to the pins on the RGB LED matrix panel!

96 | 97 | 98 | 99 |

Please refer to the Adafruit guide for wiring details on the panel side. You may want to use female-female jumper wires to make the connections between the IDC pins!

100 | 101 |

Important: DOUBLE-CHECK ALL YOUR CONNECTIONS BEFORE POWERING ON! Be sure the board's orientation matches the diagrams when you connect the wires!

102 | 103 |

Synthesizing the design

104 | 105 |

To synthesize the design, go to the "Processing" menu and select "Start Compilation", or click on the purple arrow icon in the toolbar. Synthesis should be quite fast since the design is small. After compilation is successful, you should have a new .sof file in your Quartus project directory. It should be 703,642 bytes long.

106 | 107 |

Uploading the bitfile

108 | 109 |

Plug in your DE0-Nano board via the USB connector. Now, go to the "Tools" menu and select "Programmer".

110 | 111 | 112 | 113 |

In the top left of the window that appears, you should see "USB-Blaster [USB-0]". If instead you see "No Hardware", click on "Hardware Setup..." and (re-)select your device.

114 | 115 | 116 | 117 |

Now, select the .sof file in the list, ensure "Program/Configure" is checked, and click "Start"! This should take about a second.

118 | 119 | 120 | 121 |

The FPGA is now programmed with your design! (This only programmed the SRAM though, not the onboard EEPROM — so the design is only stored until power is turned off.)

122 | 123 |

Note: In the future, you can use the command script de0-nano/program.cmd to quickly program the FPGA's SRAM with your .sof file (it uses the Quartus command line programming utility).

124 | 125 |

Running the Virtual JTAG interface server

126 | 127 |

Open the command script tcl/run.cmd in a text editor and ensure that the path to the quartus_stp executable is correct. Then, double click the script to launch the Virtual JTAG interface server (tcl/vjtag_server.tcl). This binds to a TCP port to allow programs and scripts to write data to the FPGA through Altera's Tcl API. This allows you to send video to the FPGA from any device that can communicate over the network! For example, a remote Arduino with a Wi-Fi shield, or an Android cellphone.

128 | 129 | 130 | 131 |

The included Processing demos and code

132 | 133 |

Two demos written in the Processing programming language (a dialect of Java) are available in the processing folder. You can run either demo by copying its directory to your local sketchbook folder (usually ~/Processing). The first demo, Chaser is a basic test animation. The second demo, Magnify sends a real-time screen capture to the panels through the FPGA.

134 | 135 |

Note: When running the Processing demos, it is important to change the panelsWide and panelsTall constants at the top of the sketch to match your panel configuration! Otherwise, the sketch will not work properly.

136 | 137 |

Both demos contain a copy of vjtag_client.pde which you can use to make you own Processing sketch that communicates with the board! In addition, the "protocol" that is used to interact with the Virtual JTAG server is extremely simple, and can easily be ported to another language such as Python.

138 | 139 |

Conclusion

140 | 141 |

That's it! I hope this tutorial was useful to you. Please feel free to fork this project on GitHub and contribute back any modifications or improvements! Thanks!

142 | 143 | 144 | -------------------------------------------------------------------------------- /contrib/tutorial/vjtagserver.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/tutorial/vjtagserver.png -------------------------------------------------------------------------------- /contrib/tutorial/voltage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adafruit/rgbmatrix-fpga/4acd7514ac0ff51faa0dab3f6c9030227356a215/contrib/tutorial/voltage.png -------------------------------------------------------------------------------- /de0-nano/DE0_Nano.qsf: -------------------------------------------------------------------------------- 1 | # Copyright (C) 1991-2011 Altera Corporation 2 | # Your use of Altera Corporation's design tools, logic functions 3 | # and other software and tools, and its AMPP partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Altera Program License 8 | # Subscription Agreement, Altera MegaCore Function License 9 | # Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by 12 | # Altera or its authorized distributors. Please refer to the 13 | # applicable agreement for further details. 14 | 15 | # Altera recommends that you do not modify this file. This 16 | # file is updated automatically by the Quartus II software 17 | # and any changes you make may be lost or overwritten. 18 | 19 | 20 | set_global_assignment -name FAMILY "Cyclone IV E" 21 | set_global_assignment -name DEVICE EP4CE22F17C6 22 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 23 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 24 | 25 | # Pin & Location Assignments 26 | # ========================== 27 | #============================================================ 28 | # CLOCK 29 | #============================================================ 30 | set_location_assignment PIN_R8 -to CLOCK_50 31 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 32 | 33 | #============================================================ 34 | # LED 35 | #============================================================ 36 | set_location_assignment PIN_A15 -to LED[0] 37 | set_location_assignment PIN_A13 -to LED[1] 38 | set_location_assignment PIN_B13 -to LED[2] 39 | set_location_assignment PIN_A11 -to LED[3] 40 | set_location_assignment PIN_D1 -to LED[4] 41 | set_location_assignment PIN_F3 -to LED[5] 42 | set_location_assignment PIN_B1 -to LED[6] 43 | set_location_assignment PIN_L3 -to LED[7] 44 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 45 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 46 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 47 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 48 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 49 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 50 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 51 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 52 | 53 | #============================================================ 54 | # KEY 55 | #============================================================ 56 | set_location_assignment PIN_J15 -to KEY[0] 57 | set_location_assignment PIN_E1 -to KEY[1] 58 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 59 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 60 | 61 | #============================================================ 62 | # SW 63 | #============================================================ 64 | set_location_assignment PIN_M1 -to SW[0] 65 | set_location_assignment PIN_T8 -to SW[1] 66 | set_location_assignment PIN_B9 -to SW[2] 67 | set_location_assignment PIN_M15 -to SW[3] 68 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] 70 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] 72 | 73 | #============================================================ 74 | # SDRAM 75 | #============================================================ 76 | set_location_assignment PIN_P2 -to DRAM_ADDR[0] 77 | set_location_assignment PIN_N5 -to DRAM_ADDR[1] 78 | set_location_assignment PIN_N6 -to DRAM_ADDR[2] 79 | set_location_assignment PIN_M8 -to DRAM_ADDR[3] 80 | set_location_assignment PIN_P8 -to DRAM_ADDR[4] 81 | set_location_assignment PIN_T7 -to DRAM_ADDR[5] 82 | set_location_assignment PIN_N8 -to DRAM_ADDR[6] 83 | set_location_assignment PIN_T6 -to DRAM_ADDR[7] 84 | set_location_assignment PIN_R1 -to DRAM_ADDR[8] 85 | set_location_assignment PIN_P1 -to DRAM_ADDR[9] 86 | set_location_assignment PIN_N2 -to DRAM_ADDR[10] 87 | set_location_assignment PIN_N1 -to DRAM_ADDR[11] 88 | set_location_assignment PIN_L4 -to DRAM_ADDR[12] 89 | set_location_assignment PIN_M7 -to DRAM_BA[0] 90 | set_location_assignment PIN_M6 -to DRAM_BA[1] 91 | set_location_assignment PIN_L7 -to DRAM_CKE 92 | set_location_assignment PIN_R4 -to DRAM_CLK 93 | set_location_assignment PIN_P6 -to DRAM_CS_N 94 | set_location_assignment PIN_G2 -to DRAM_DQ[0] 95 | set_location_assignment PIN_G1 -to DRAM_DQ[1] 96 | set_location_assignment PIN_L8 -to DRAM_DQ[2] 97 | set_location_assignment PIN_K5 -to DRAM_DQ[3] 98 | set_location_assignment PIN_K2 -to DRAM_DQ[4] 99 | set_location_assignment PIN_J2 -to DRAM_DQ[5] 100 | set_location_assignment PIN_J1 -to DRAM_DQ[6] 101 | set_location_assignment PIN_R7 -to DRAM_DQ[7] 102 | set_location_assignment PIN_T4 -to DRAM_DQ[8] 103 | set_location_assignment PIN_T2 -to DRAM_DQ[9] 104 | set_location_assignment PIN_T3 -to DRAM_DQ[10] 105 | set_location_assignment PIN_R3 -to DRAM_DQ[11] 106 | set_location_assignment PIN_R5 -to DRAM_DQ[12] 107 | set_location_assignment PIN_P3 -to DRAM_DQ[13] 108 | set_location_assignment PIN_N3 -to DRAM_DQ[14] 109 | set_location_assignment PIN_K1 -to DRAM_DQ[15] 110 | set_location_assignment PIN_R6 -to DRAM_DQM[0] 111 | set_location_assignment PIN_T5 -to DRAM_DQM[1] 112 | set_location_assignment PIN_L1 -to DRAM_CAS_N 113 | set_location_assignment PIN_L2 -to DRAM_RAS_N 114 | set_location_assignment PIN_C2 -to DRAM_WE_N 115 | 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] 120 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] 122 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] 124 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] 126 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] 128 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] 130 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] 131 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE 132 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK 133 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N 134 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] 135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] 136 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] 137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] 138 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] 139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] 140 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] 141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] 142 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] 143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] 144 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] 145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] 146 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] 147 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] 148 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] 149 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] 150 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] 151 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] 152 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N 153 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N 154 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N 155 | 156 | #============================================================ 157 | # Accelerometer and EEPROM 158 | #============================================================ 159 | set_location_assignment PIN_F2 -to I2C_SCLK 160 | set_location_assignment PIN_F1 -to I2C_SDAT 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK 162 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT 163 | 164 | set_location_assignment PIN_G5 -to G_SENSOR_CS_N 165 | set_location_assignment PIN_M2 -to G_SENSOR_INT 166 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT 168 | 169 | #============================================================ 170 | # ADC 171 | #============================================================ 172 | set_location_assignment PIN_A10 -to ADC_CS_N 173 | set_location_assignment PIN_B10 -to ADC_SADDR 174 | set_location_assignment PIN_B14 -to ADC_SCLK 175 | set_location_assignment PIN_A9 -to ADC_SDAT 176 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR 178 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK 179 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT 180 | 181 | #============================================================ 182 | # 2x13 GPIO Header 183 | #============================================================ 184 | set_location_assignment PIN_A14 -to GPIO_2[0] 185 | set_location_assignment PIN_B16 -to GPIO_2[1] 186 | set_location_assignment PIN_C14 -to GPIO_2[2] 187 | set_location_assignment PIN_C16 -to GPIO_2[3] 188 | set_location_assignment PIN_C15 -to GPIO_2[4] 189 | set_location_assignment PIN_D16 -to GPIO_2[5] 190 | set_location_assignment PIN_D15 -to GPIO_2[6] 191 | set_location_assignment PIN_D14 -to GPIO_2[7] 192 | set_location_assignment PIN_F15 -to GPIO_2[8] 193 | set_location_assignment PIN_F16 -to GPIO_2[9] 194 | set_location_assignment PIN_F14 -to GPIO_2[10] 195 | set_location_assignment PIN_G16 -to GPIO_2[11] 196 | set_location_assignment PIN_G15 -to GPIO_2[12] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] 198 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] 199 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] 200 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] 201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] 202 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] 203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] 204 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] 205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] 206 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] 207 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] 208 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] 209 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] 210 | 211 | set_location_assignment PIN_E15 -to GPIO_2_IN[0] 212 | set_location_assignment PIN_E16 -to GPIO_2_IN[1] 213 | set_location_assignment PIN_M16 -to GPIO_2_IN[2] 214 | 215 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] 216 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] 217 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] 218 | 219 | #============================================================ 220 | # GPIO_0, GPIO_0 connect to GPIO Default 221 | #============================================================ 222 | set_location_assignment PIN_A8 -to GPIO_0_IN[0] 223 | set_location_assignment PIN_D3 -to GPIO_0[0] 224 | set_location_assignment PIN_B8 -to GPIO_0_IN[1] 225 | set_location_assignment PIN_C3 -to GPIO_0[1] 226 | set_location_assignment PIN_A2 -to GPIO_0[2] 227 | set_location_assignment PIN_A3 -to GPIO_0[3] 228 | set_location_assignment PIN_B3 -to GPIO_0[4] 229 | set_location_assignment PIN_B4 -to GPIO_0[5] 230 | set_location_assignment PIN_A4 -to GPIO_0[6] 231 | set_location_assignment PIN_B5 -to GPIO_0[7] 232 | set_location_assignment PIN_A5 -to GPIO_0[8] 233 | set_location_assignment PIN_D5 -to GPIO_0[9] 234 | set_location_assignment PIN_B6 -to GPIO_0[10] 235 | set_location_assignment PIN_A6 -to GPIO_0[11] 236 | set_location_assignment PIN_B7 -to GPIO_0[12] 237 | set_location_assignment PIN_D6 -to GPIO_0[13] 238 | set_location_assignment PIN_A7 -to GPIO_0[14] 239 | set_location_assignment PIN_C6 -to GPIO_0[15] 240 | set_location_assignment PIN_C8 -to GPIO_0[16] 241 | set_location_assignment PIN_E6 -to GPIO_0[17] 242 | set_location_assignment PIN_E7 -to GPIO_0[18] 243 | set_location_assignment PIN_D8 -to GPIO_0[19] 244 | set_location_assignment PIN_E8 -to GPIO_0[20] 245 | set_location_assignment PIN_F8 -to GPIO_0[21] 246 | set_location_assignment PIN_F9 -to GPIO_0[22] 247 | set_location_assignment PIN_E9 -to GPIO_0[23] 248 | set_location_assignment PIN_C9 -to GPIO_0[24] 249 | set_location_assignment PIN_D9 -to GPIO_0[25] 250 | set_location_assignment PIN_E11 -to GPIO_0[26] 251 | set_location_assignment PIN_E10 -to GPIO_0[27] 252 | set_location_assignment PIN_C11 -to GPIO_0[28] 253 | set_location_assignment PIN_B11 -to GPIO_0[29] 254 | set_location_assignment PIN_A12 -to GPIO_0[30] 255 | set_location_assignment PIN_D11 -to GPIO_0[31] 256 | set_location_assignment PIN_D12 -to GPIO_0[32] 257 | set_location_assignment PIN_B12 -to GPIO_0[33] 258 | 259 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] 260 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] 261 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] 262 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] 263 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] 264 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] 265 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] 266 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] 267 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] 268 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] 269 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] 270 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] 271 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] 272 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] 273 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] 274 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] 275 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] 276 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] 277 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] 278 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] 279 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] 280 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] 281 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] 282 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] 283 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] 284 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] 285 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] 286 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] 287 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] 288 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] 289 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] 290 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] 291 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] 292 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] 293 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] 294 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] 295 | 296 | #============================================================ 297 | # GPIO_0, GPIO_1 connect to GPIO Default 298 | #============================================================ 299 | set_location_assignment PIN_T9 -to GPIO_1_IN[0] 300 | set_location_assignment PIN_F13 -to GPIO_1[0] 301 | set_location_assignment PIN_R9 -to GPIO_1_IN[1] 302 | set_location_assignment PIN_T15 -to GPIO_1[1] 303 | set_location_assignment PIN_T14 -to GPIO_1[2] 304 | set_location_assignment PIN_T13 -to GPIO_1[3] 305 | set_location_assignment PIN_R13 -to GPIO_1[4] 306 | set_location_assignment PIN_T12 -to GPIO_1[5] 307 | set_location_assignment PIN_R12 -to GPIO_1[6] 308 | set_location_assignment PIN_T11 -to GPIO_1[7] 309 | set_location_assignment PIN_T10 -to GPIO_1[8] 310 | set_location_assignment PIN_R11 -to GPIO_1[9] 311 | set_location_assignment PIN_P11 -to GPIO_1[10] 312 | set_location_assignment PIN_R10 -to GPIO_1[11] 313 | set_location_assignment PIN_N12 -to GPIO_1[12] 314 | set_location_assignment PIN_P9 -to GPIO_1[13] 315 | set_location_assignment PIN_N9 -to GPIO_1[14] 316 | set_location_assignment PIN_N11 -to GPIO_1[15] 317 | set_location_assignment PIN_L16 -to GPIO_1[16] 318 | set_location_assignment PIN_K16 -to GPIO_1[17] 319 | set_location_assignment PIN_R16 -to GPIO_1[18] 320 | set_location_assignment PIN_L15 -to GPIO_1[19] 321 | set_location_assignment PIN_P15 -to GPIO_1[20] 322 | set_location_assignment PIN_P16 -to GPIO_1[21] 323 | set_location_assignment PIN_R14 -to GPIO_1[22] 324 | set_location_assignment PIN_N16 -to GPIO_1[23] 325 | set_location_assignment PIN_N15 -to GPIO_1[24] 326 | set_location_assignment PIN_P14 -to GPIO_1[25] 327 | set_location_assignment PIN_L14 -to GPIO_1[26] 328 | set_location_assignment PIN_N14 -to GPIO_1[27] 329 | set_location_assignment PIN_M10 -to GPIO_1[28] 330 | set_location_assignment PIN_L13 -to GPIO_1[29] 331 | set_location_assignment PIN_J16 -to GPIO_1[30] 332 | set_location_assignment PIN_K15 -to GPIO_1[31] 333 | set_location_assignment PIN_J13 -to GPIO_1[32] 334 | set_location_assignment PIN_J14 -to GPIO_1[33] 335 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] 336 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] 337 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] 338 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] 339 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] 340 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] 341 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] 342 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] 343 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] 344 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] 345 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] 346 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] 347 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] 348 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] 349 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] 350 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] 351 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] 352 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] 353 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] 354 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] 355 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] 356 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] 357 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] 358 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] 359 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] 360 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] 361 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] 362 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] 363 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] 364 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] 365 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] 366 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] 367 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] 368 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] 369 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] 370 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] 371 | 372 | set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 373 | set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 374 | 375 | set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" 376 | set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" 377 | 378 | set_instance_assignment -name FAST_INPUT_REGISTER ON -to * 379 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to * 380 | set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * 381 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to * 382 | 383 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 384 | -------------------------------------------------------------------------------- /de0-nano/program.cmd: -------------------------------------------------------------------------------- 1 | C:\altera\10.1\quartus\bin\quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;rgbmatrix.sof" 2 | pause -------------------------------------------------------------------------------- /de0-nano/rgbmatrix-fpga.qsf: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_B12 -to lat 2 | set_location_assignment PIN_E7 -to r1 3 | set_location_assignment PIN_E8 -to b1 4 | set_location_assignment PIN_F9 -to r2 5 | set_location_assignment PIN_C9 -to b2 6 | set_location_assignment PIN_E11 -to a 7 | set_location_assignment PIN_E10 -to g1 8 | set_location_assignment PIN_C11 -to c 9 | set_location_assignment PIN_B11 -to g2 10 | set_location_assignment PIN_A12 -to clk_out 11 | set_location_assignment PIN_D11 -to b 12 | set_location_assignment PIN_D12 -to oe 13 | set_location_assignment PIN_R8 -to clk_in 14 | set_location_assignment PIN_J15 -to rst_n -------------------------------------------------------------------------------- /processing/Chaser/Chaser.pde: -------------------------------------------------------------------------------- 1 | // Processing example sketch for the Adafruit RGB LED Matrix Display Driver project 2 | // Copyright (c) 2012 Brian Nezvadovitz 3 | // This software is distributed under the terms of the MIT License. 4 | 5 | // Constants 6 | static final int panelsWide = 1, // How many panels wide is your display? 7 | panelsTall = 1, // How many panels tall is your display? 8 | imgScale = 10; // Scale factor for displayed preview 9 | 10 | // Global variables 11 | int xPos = 0, yPos = 0, frameNum = 0; 12 | 13 | final int imgWidth = pixelsWide*panelsWide; 14 | final int imgHeight = pixelsTall*panelsTall; 15 | 16 | void setup() { 17 | // Try to establish connection 18 | if(!vjtag_client_connect()) return; 19 | 20 | // Erase the display before starting 21 | blank_leds(); 22 | 23 | // Setup the window 24 | size(imgWidth * imgScale, imgHeight * imgScale); 25 | frameRate(30); // max FPS 26 | } 27 | 28 | void draw() { 29 | // Erase 30 | background(0); 31 | 32 | // Draw the chasers 33 | set(xPos, yPos, #ff0000); 34 | set(xPos+imgWidth/2, yPos, #0000ff); 35 | set(xPos, yPos+imgHeight/2, #00ff00); 36 | set(xPos+imgWidth/2, yPos+imgHeight/2, #ffffff); 37 | 38 | // Update positions 39 | if(++xPos == imgWidth/2) { 40 | xPos = 0; 41 | if(++yPos == imgHeight/2) 42 | yPos = 0; 43 | } 44 | 45 | // Capture the image, rearrange it necessary for this panel configuration 46 | PImage img = get(0, 0, imgWidth, imgHeight); 47 | 48 | // Preview image data on computer display 49 | image(img, 0, 0, imgWidth*imgScale, imgHeight*imgScale); 50 | 51 | // Issue pixel data to the FPGA 52 | refresh(img); 53 | 54 | // Stop when the end is reached 55 | if(frameNum >= panelsTall*panelsWide*pixelsTall*pixelsWide/4-1) { 56 | exit(); 57 | } else { 58 | frameNum++; 59 | } 60 | 61 | } 62 | 63 | -------------------------------------------------------------------------------- /processing/Chaser/vjtag_client.pde: -------------------------------------------------------------------------------- 1 | // TCP client connector for the (virtual) JTAG Interface 2 | // Part of the Adafruit RGB LED Matrix Display Driver project 3 | // For use with Processing sketches 4 | // Copyright (c) 2012 Brian Nezvadovitz 5 | // This software is distributed under the terms of the MIT License. 6 | 7 | // Libraries 8 | import processing.net.*; 9 | import java.math.BigInteger; 10 | 11 | // Constants 12 | static final int pixelsWide = 32, 13 | pixelsTall = 16; 14 | 15 | // Global variables 16 | Client jtagsrv; 17 | 18 | boolean vjtag_client_connect() { 19 | // Connect to the Virtual JTAG server 20 | jtagsrv = new Client(this, "localhost", 1337); 21 | // Check if connection worked... 22 | try { 23 | println("* Connected to " + jtagsrv.ip()); 24 | return true; 25 | } catch(NullPointerException e) { 26 | println("* Unable to connect client socket!"); 27 | exit(); 28 | return false; 29 | } 30 | } 31 | 32 | void refresh(PImage img) { 33 | // Electrically, all the panels are dasiy-chained together into one very long display 34 | // However in reality, we may have our panels in any arbitrary rectangular arrangement 35 | // This function slides a small "window" frame over the image in the correct order and 36 | // sends the data to the FPGA one panel's worth of pixels at a time. 37 | int regionsCopied = 0; 38 | PImage frame = new PImage(pixelsWide*panelsWide*panelsTall, pixelsTall); 39 | // For each panel in height of display... 40 | for(int y = 0; y < panelsTall*pixelsTall; y += pixelsTall) { 41 | // Rearrange region 42 | frame.copy(img, 0, y, pixelsWide*panelsWide, pixelsTall, pixelsWide*panelsWide*regionsCopied, 0, pixelsWide*panelsWide, pixelsTall); 43 | regionsCopied++; 44 | } 45 | // Send the frame over the wire 46 | push_frame(frame); 47 | } 48 | 49 | void push_frame(PImage frame) { 50 | // Convert the pixel data into a format that can be sent to the FPGA, 51 | // then send it over the connection to the virtual JTAG server 52 | final int middlePixel = (frame.width*frame.height)/2; 53 | frame.loadPixels(); 54 | BigInteger bigint = BigInteger.valueOf(0); 55 | // Read in the frame, one pixel at a time 56 | for(int i = 0; i < middlePixel; i++) { 57 | // Get the upper and lower pixel's RGB data (mask off alpha) 58 | int upper = frame.pixels[i] & 0x00FFFFFF; 59 | int lower = frame.pixels[i+middlePixel] & 0x00FFFFFF; 60 | // Append this new data to the bitwise-least-significant-end of the "bigint" accumulator 61 | BigInteger shifted = BigInteger.valueOf(upper).shiftLeft(i*48+24); 62 | shifted = shifted.or(BigInteger.valueOf(lower).shiftLeft(i*48)); 63 | bigint = bigint.or(shifted); 64 | } 65 | // Now, send completed data to the server as a hex string followed by a newline 66 | String hexStr = pad_string(bigint.toString(16), frame.width*frame.height*24/4); 67 | jtagsrv.write(hexStr + "\n"); 68 | } 69 | 70 | void blank_leds() { 71 | // First, reset the design on the FPGA 72 | jtagsrv.write("RST\n"); 73 | // Erase the LED panel by sending all "black" pixels 74 | PImage frame = new PImage(pixelsWide*panelsWide*panelsTall, pixelsTall); 75 | push_frame(frame); 76 | println("* Reset and erased LED matrix panels"); 77 | } 78 | 79 | String pad_string(String s, int len) { 80 | // Left-pads a string with zeros until it meets the given length requirement 81 | // Does nothing if the string is already at the required length 82 | // Blows up if the string is too long 83 | if(s.length() > len) { 84 | System.err.println("Error: Cannot pad string to requested length because it is too long (" + s.length() + ")!"); 85 | System.err.println(" The string is: " + s); 86 | exit(); 87 | } 88 | while(s.length() < len) { 89 | s = "0" + s; 90 | } 91 | return s; 92 | } 93 | 94 | -------------------------------------------------------------------------------- /processing/Magnify/Magnify.pde: -------------------------------------------------------------------------------- 1 | // "Magnify" example sketch for the Adafruit RGB LED Matrix Display Driver project 2 | 3 | // Libraries 4 | import java.awt.*; 5 | import java.awt.image.*; 6 | import java.awt.MouseInfo; 7 | 8 | // Constants 9 | static final int panelsWide = 1, // How many panels wide is your display? 10 | panelsTall = 1, // How many panels tall is your display? 11 | imgScale = 10; // Scale factor for displayed preview 12 | 13 | // Global variables 14 | PImage img; 15 | Robot bot; // For screen capture 16 | 17 | final int imgWidth = pixelsWide*panelsWide; 18 | final int imgHeight = pixelsTall*panelsTall; 19 | 20 | void setup() { 21 | // Try to establish connection 22 | if(!vjtag_client_connect()) return; 23 | 24 | // Erase the display before starting 25 | blank_leds(); 26 | 27 | // Initialize capture code 28 | GraphicsEnvironment ge = GraphicsEnvironment.getLocalGraphicsEnvironment(); 29 | GraphicsDevice[] gd = ge.getScreenDevices(); 30 | try { 31 | bot = new Robot(gd[0]); 32 | } 33 | catch(AWTException e) { 34 | System.err.println("new Robot() failed."); 35 | } 36 | 37 | // Setup the window 38 | size(imgWidth * imgScale, imgHeight * imgScale); 39 | background(0); 40 | frameRate(30); // max FPS 41 | } 42 | 43 | void draw() { 44 | int x, y; 45 | Rectangle r; 46 | PImage img; 47 | 48 | // Get absolute mouse coordinates on screen, offset to center on LED array, 49 | // and constrain result so it doesn't extend offscreen in any direction. 50 | x = constrain(MouseInfo.getPointerInfo().getLocation().x - imgWidth / 2, 51 | 0, screen.width - imgWidth); 52 | y = constrain(MouseInfo.getPointerInfo().getLocation().y - imgHeight / 2, 53 | 0, screen.height - imgHeight); 54 | r = new Rectangle(x, y, imgWidth, imgHeight); 55 | 56 | // Capture rectangle from screen, convert BufferedImage to PImage 57 | img = new PImage(bot.createScreenCapture(r)); 58 | img.loadPixels(); // Make pixel array readable 59 | 60 | // Display captured image 61 | scale(imgScale); 62 | image(img, 0, 0); 63 | 64 | // Issue to LED array 65 | refresh(img); 66 | } 67 | 68 | -------------------------------------------------------------------------------- /processing/Magnify/vjtag_client.pde: -------------------------------------------------------------------------------- 1 | // TCP client connector for the (virtual) JTAG Interface 2 | // Part of the Adafruit RGB LED Matrix Display Driver project 3 | // For use with Processing sketches 4 | // Copyright (c) 2012 Brian Nezvadovitz 5 | // This software is distributed under the terms of the MIT License. 6 | 7 | // Libraries 8 | import processing.net.*; 9 | import java.math.BigInteger; 10 | 11 | // Constants 12 | static final int pixelsWide = 32, 13 | pixelsTall = 16; 14 | 15 | // Global variables 16 | Client jtagsrv; 17 | 18 | boolean vjtag_client_connect() { 19 | // Connect to the Virtual JTAG server 20 | jtagsrv = new Client(this, "localhost", 1337); 21 | // Check if connection worked... 22 | try { 23 | println("* Connected to " + jtagsrv.ip()); 24 | return true; 25 | } catch(NullPointerException e) { 26 | println("* Unable to connect client socket!"); 27 | exit(); 28 | return false; 29 | } 30 | } 31 | 32 | void refresh(PImage img) { 33 | // Electrically, all the panels are dasiy-chained together into one very long display 34 | // However in reality, we may have our panels in any arbitrary rectangular arrangement 35 | // This function slides a small "window" frame over the image in the correct order and 36 | // sends the data to the FPGA one panel's worth of pixels at a time. 37 | int regionsCopied = 0; 38 | PImage frame = new PImage(pixelsWide*panelsWide*panelsTall, pixelsTall); 39 | // For each panel in height of display... 40 | for(int y = 0; y < panelsTall*pixelsTall; y += pixelsTall) { 41 | // Rearrange region 42 | frame.copy(img, 0, y, pixelsWide*panelsWide, pixelsTall, pixelsWide*panelsWide*regionsCopied, 0, pixelsWide*panelsWide, pixelsTall); 43 | regionsCopied++; 44 | } 45 | // Send the frame over the wire 46 | push_frame(frame); 47 | } 48 | 49 | void push_frame(PImage frame) { 50 | // Convert the pixel data into a format that can be sent to the FPGA, 51 | // then send it over the connection to the virtual JTAG server 52 | final int middlePixel = (frame.width*frame.height)/2; 53 | frame.loadPixels(); 54 | BigInteger bigint = BigInteger.valueOf(0); 55 | // Read in the frame, one pixel at a time 56 | for(int i = 0; i < middlePixel; i++) { 57 | // Get the upper and lower pixel's RGB data (mask off alpha) 58 | int upper = frame.pixels[i] & 0x00FFFFFF; 59 | int lower = frame.pixels[i+middlePixel] & 0x00FFFFFF; 60 | // Append this new data to the bitwise-least-significant-end of the "bigint" accumulator 61 | BigInteger shifted = BigInteger.valueOf(upper).shiftLeft(i*48+24); 62 | shifted = shifted.or(BigInteger.valueOf(lower).shiftLeft(i*48)); 63 | bigint = bigint.or(shifted); 64 | } 65 | // Now, send completed data to the server as a hex string followed by a newline 66 | String hexStr = pad_string(bigint.toString(16), frame.width*frame.height*24/4); 67 | jtagsrv.write(hexStr + "\n"); 68 | } 69 | 70 | void blank_leds() { 71 | // First, reset the design on the FPGA 72 | jtagsrv.write("RST\n"); 73 | // Erase the LED panel by sending all "black" pixels 74 | PImage frame = new PImage(pixelsWide*panelsWide*panelsTall, pixelsTall); 75 | push_frame(frame); 76 | println("* Reset and erased LED matrix panels"); 77 | } 78 | 79 | String pad_string(String s, int len) { 80 | // Left-pads a string with zeros until it meets the given length requirement 81 | // Does nothing if the string is already at the required length 82 | // Blows up if the string is too long 83 | if(s.length() > len) { 84 | System.err.println("Error: Cannot pad string to requested length because it is too long (" + s.length() + ")!"); 85 | System.err.println(" The string is: " + s); 86 | exit(); 87 | } 88 | while(s.length() < len) { 89 | s = "0" + s; 90 | } 91 | return s; 92 | } 93 | 94 | -------------------------------------------------------------------------------- /tcl/Useful links.txt: -------------------------------------------------------------------------------- 1 | http://en.wikipedia.org/wiki/Tcl 2 | http://wiki.tcl.tk/ 3 | http://antirez.com/articoli/tclmisunderstood.html 4 | -------------------------------------------------------------------------------- /tcl/run.cmd: -------------------------------------------------------------------------------- 1 | C:\altera\10.1\quartus\bin\quartus_stp.exe -t "vjtag_server.tcl" 2 | pause -------------------------------------------------------------------------------- /tcl/vjtag_server.tcl: -------------------------------------------------------------------------------- 1 | # Basic TCP server gateway for the (virtual) JTAG Interface 2 | # Part of the Adafruit RGB LED Matrix Display Driver project 3 | # Written partially by Brian Nezvadovitz 4 | 5 | # You can run this script through the Quartus II SignalTap II Tcl interpreter 6 | # (quartus_stp.exe) by invoking it with the -t parameter. 7 | 8 | # This TCL script is derived from the example posted online at 9 | # http://idle-logic.com/2012/04/15/talking-to-the-de0-nano-using-the-virtual-jtag-interface/ 10 | # TCP/IP server code dervied from Tcl Developer Exchange - http://www.tcl.tk/about/netserver.html 11 | # The JTAG portion of the script is derived from some of the examples from Altera. 12 | 13 | # After starting this script, connect to localhost on port 1337 and send strings 14 | # of hex characters followed by a newline ("\n") character. 15 | 16 | proc Script_Main {} { 17 | # Print welcome banner 18 | puts "------------------------------------------------" 19 | puts "" 20 | puts " <<-=*\[ JTAG server for RGB LED Matrix \]*-=>> " 21 | puts "" 22 | 23 | # Find the USB-Blaster device attached to the system 24 | puts "* Locating USB-Blaster device..." 25 | foreach hardware_name [get_hardware_names] { 26 | if { [string match "USB-Blaster*" $hardware_name] } { 27 | set usbblaster_name $hardware_name 28 | } 29 | } 30 | 31 | # List all devices on the chain, and select the first device on the chain. 32 | puts "* Finding devices attached to $usbblaster_name..." 33 | foreach device_name [get_device_names -hardware_name $usbblaster_name] { 34 | if { [string match "@1*" $device_name] } { 35 | set jtag_device $device_name 36 | } 37 | } 38 | 39 | # Open the selected JTAG device 40 | puts "* Opening $jtag_device" 41 | open_device -hardware_name $usbblaster_name -device_name $jtag_device 42 | 43 | # Start the TCP/IP listener 44 | puts "* Starting server on port 1337..." 45 | set s [socket -server ConnAccept 1337] 46 | 47 | # Wait for connections... 48 | vwait forever 49 | #catch {close_device} 50 | } 51 | 52 | proc Write_JTAG_DR {send_data data_length} { 53 | #puts "DEBUG: Write_JTAG_DR $send_data" 54 | device_lock -timeout 10000 55 | device_virtual_dr_shift -dr_value $send_data -instance_index 0 -length $data_length -value_in_hex -no_captured_dr_value 56 | catch {device_unlock} 57 | } 58 | 59 | proc Write_JTAG_IR {send_data} { 60 | puts "DEBUG: Write_JTAG_IR $send_data" 61 | device_lock -timeout 10000 62 | device_virtual_ir_shift -instance_index 0 -ir_value $send_data -no_captured_ir_value 63 | catch {device_unlock} 64 | } 65 | 66 | proc ConnAccept {sock addr port} { 67 | global conn 68 | puts "* Connection from $addr $port opened" 69 | set conn(addr,$sock) [list $addr $port] 70 | # Ensure that each "puts" by the server results in a network transmission 71 | fconfigure $sock -buffering line 72 | # Set up a callback for when the client sends data 73 | fileevent $sock readable [list IncomingData $sock] 74 | # Set IR to 1 which is "write to register" mode 75 | Write_JTAG_IR 1 76 | } 77 | 78 | proc IncomingData {sock} { 79 | global conn 80 | # Check for EOF or abnormal connection drop 81 | if {[eof $sock] || [catch {gets $sock line}]} { 82 | # Set IR back to 0, which is "bypass" mode 83 | Write_JTAG_IR 0 84 | # Clean up the socket 85 | close $sock 86 | puts "* Connection with $conn(addr,$sock) closed" 87 | unset conn(addr,$sock) 88 | } else { 89 | # Incoming data from the client 90 | set data_len [string length $line] 91 | # Check length 92 | if {$data_len >= 4} then { 93 | # Write to the data register 94 | Write_JTAG_DR $line [expr 4*$data_len] 95 | } elseif {$data_len == 3 && $line == "RST"} then { 96 | # Send reset command to the device 97 | puts "* Sending reset command!" 98 | Write_JTAG_IR 2 99 | # Put the device back in "write to register" mode 100 | Write_JTAG_IR 1 101 | } else { 102 | puts "DEBUG: Ignored incoming data of length $data_len chars" 103 | } 104 | } 105 | } 106 | 107 | # Start the script! 108 | Script_Main 109 | 110 | #EOF -------------------------------------------------------------------------------- /vhdl/clk_div.vhd: -------------------------------------------------------------------------------- 1 | -- Simple parameterized clock divider that uses a counter 2 | -- 3 | -- Copyright (c) 2012 Brian Nezvadovitz 4 | -- This software is distributed under the terms of the MIT License shown below. 5 | -- 6 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 7 | -- of this software and associated documentation files (the "Software"), to 8 | -- deal in the Software without restriction, including without limitation the 9 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 | -- sell copies of the Software, and to permit persons to whom the Software is 11 | -- furnished to do so, subject to the following conditions: 12 | -- 13 | -- The above copyright notice and this permission notice shall be included in 14 | -- all copies or substantial portions of the Software. 15 | -- 16 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 | -- IN THE SOFTWARE. 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | use ieee.numeric_std.all; 27 | use ieee.math_real.all; -- don't use for synthesis, but OK for static numbers 28 | 29 | entity clk_div is 30 | generic ( 31 | clk_in_freq : natural; 32 | clk_out_freq : natural 33 | ); 34 | port ( 35 | clk_in : in std_logic; 36 | clk_out : out std_logic; 37 | rst : in std_logic 38 | ); 39 | end clk_div; 40 | 41 | architecture bhv of clk_div is 42 | constant OUT_PERIOD_COUNT : integer := (clk_in_freq/clk_out_freq)-1; 43 | begin 44 | process(clk_in, rst) 45 | variable count : integer range 0 to OUT_PERIOD_COUNT; -- note: integer type defaults to 32-bits wide unless you specify the range yourself 46 | begin 47 | if(rst = '1') then 48 | count := 0; 49 | clk_out <= '0'; 50 | elsif(rising_edge(clk_in)) then 51 | if(count = OUT_PERIOD_COUNT) then 52 | count := 0; 53 | else 54 | count := count + 1; 55 | end if; 56 | if(count > OUT_PERIOD_COUNT/2) then 57 | clk_out <= '1'; 58 | else 59 | clk_out <= '0'; 60 | end if; 61 | end if; 62 | end process; 63 | end bhv; 64 | -------------------------------------------------------------------------------- /vhdl/config.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- User-editable configuration and constants package 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | library ieee; 26 | use ieee.math_real.log2; 27 | use ieee.math_real.ceil; 28 | 29 | package rgbmatrix is 30 | 31 | -- User configurable constants 32 | constant NUM_PANELS : integer := 2; -- total number of LED matrix panels 33 | constant PIXEL_DEPTH : integer := 8; -- number of bits per pixel 34 | 35 | -- Special constants (change these at your own risk, stuff might break!) 36 | constant PANEL_WIDTH : integer := 32; -- width of the panel in pixels 37 | constant PANEL_HEIGHT : integer := 16; -- height of the panel in pixels 38 | constant DATA_WIDTH : positive := PIXEL_DEPTH*6; 39 | -- one bit for each subpixel (3), times 40 | -- the number of simultaneous lines (2) 41 | 42 | -- Derived constants 43 | constant ADDR_WIDTH : positive := positive(log2(real(NUM_PANELS*PANEL_WIDTH*PANEL_HEIGHT/2))); 44 | constant IMG_WIDTH : positive := PANEL_WIDTH*NUM_PANELS; 45 | constant IMG_WIDTH_LOG2 : positive := positive(log2(real(IMG_WIDTH))); 46 | 47 | end rgbmatrix; 48 | -------------------------------------------------------------------------------- /vhdl/jtag_iface.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Interface between the virtual JTAG port and the video data controller 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | -- For information on how the Altera Virtual JTAG works, see this document: 26 | -- http://www.altera.com/literature/ug/ug_virtualjtag.pdf 27 | 28 | library ieee; 29 | use ieee.std_logic_1164.all; 30 | use ieee.numeric_std.all; 31 | 32 | use work.rgbmatrix.all; 33 | 34 | entity jtag_iface is 35 | port ( 36 | rst : in std_logic; 37 | rst_out : out std_logic; 38 | output : out std_logic_vector(DATA_WIDTH-1 downto 0); 39 | valid : out std_logic 40 | ); 41 | end jtag_iface; 42 | 43 | architecture bhv of jtag_iface is 44 | -- External/raw JTAG signals 45 | signal jtag_tdo, jtag_tck, jtag_tdi, jtag_sdr : std_logic; 46 | signal jtag_ir_in : std_logic_vector(1 downto 0); 47 | -- Internal JTAG signals 48 | signal dr_select : std_logic; 49 | signal dr0 : std_logic; 50 | signal dr1 : std_logic_vector(DATA_WIDTH-1 downto 0); 51 | -- Internal counter signals 52 | signal dr1_pulse : std_logic_vector(DATA_WIDTH-1 downto 0); 53 | begin 54 | 55 | -- Altera Virtual JTAG "megafunction" 56 | U_vJTAG : entity work.megawizard_vjtag 57 | port map ( 58 | ir_out => "00", 59 | tdo => jtag_tdo, 60 | ir_in => jtag_ir_in, 61 | tck => jtag_tck, 62 | tdi => jtag_tdi, 63 | virtual_state_cdr => open, 64 | virtual_state_cir => open, 65 | virtual_state_e1dr => open, 66 | virtual_state_e2dr => open, 67 | virtual_state_pdr => open, 68 | virtual_state_sdr => jtag_sdr, 69 | virtual_state_udr => open, 70 | virtual_state_uir => open 71 | ); 72 | 73 | -- Break out the instruction register's low bit which we use to select the destination data register 74 | dr_select <= jtag_ir_in(0); 75 | 76 | -- Break out the instruction register's high bit which we use to perform a self-reset 77 | rst_out <= jtag_ir_in(1); 78 | 79 | -- Clocked process to shift data into the data registers 80 | process(rst, jtag_tck, dr_select) 81 | begin 82 | if(rst = '1') then 83 | dr0 <= '0'; 84 | dr1 <= (others => '0'); 85 | dr1_pulse <= (others => '0'); 86 | dr1_pulse(DATA_WIDTH-1) <= '1'; 87 | elsif(rising_edge(jtag_tck)) then 88 | dr0 <= jtag_tdi; 89 | if(jtag_sdr = '1' and dr_select = '1') then -- JTAG is in Shift DR state and data register 1 is selected 90 | dr1 <= (jtag_tdi & dr1(DATA_WIDTH-1 downto 1)); -- drop the LSB, shift in the new MSB 91 | dr1_pulse <= (dr1_pulse(0) & dr1_pulse(DATA_WIDTH-1 downto 1)); -- rotate right the dr1 word pulse 92 | end if; 93 | end if; 94 | end process; 95 | 96 | -- Maintain the TDO continuity 97 | process(dr_select, dr0, dr1) 98 | begin 99 | if(dr_select = '1') then 100 | jtag_tdo <= dr1(0); 101 | else 102 | jtag_tdo <= dr0; 103 | end if; 104 | end process; 105 | 106 | -- The UDR signal will assert when the data has been transmitted and the data register has 107 | -- captured the word. Ignoring this signal will cause an unwanted behavior as data is shifted 108 | -- through the data register. In this case we are using a memory to store the value in DR1. 109 | -- The original idea was to use UDR as the write clock (rising edge triggered), but this 110 | -- requires all JTAG transfers to be exactly one word. Instead, a bit counter is implemented 111 | -- that indicates when a full word is shifted in by the JTAG clock (TCK). 112 | valid <= dr1_pulse(DATA_WIDTH-1); 113 | 114 | -- Break out the data register to the output 115 | output <= dr1; 116 | 117 | end bhv; -------------------------------------------------------------------------------- /vhdl/ledctrl.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Finite state machine to control the LED matrix hardware 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | -- For some great documentation on how the RGB LED panel works, see this page: 26 | -- http://www.rayslogic.com/propeller/Programming/AdafruitRGB/AdafruitRGB.htm 27 | -- or this page 28 | -- http://www.ladyada.net/wiki/tutorials/products/rgbledmatrix/index.html#how_the_matrix_works 29 | 30 | library ieee; 31 | use ieee.std_logic_1164.all; 32 | use ieee.numeric_std.all; 33 | 34 | use work.rgbmatrix.all; 35 | 36 | entity ledctrl is 37 | port ( 38 | clk_in : in std_logic; 39 | rst : in std_logic; 40 | -- LED Panel IO 41 | clk_out : out std_logic; 42 | rgb1 : out std_logic_vector(2 downto 0); 43 | rgb2 : out std_logic_vector(2 downto 0); 44 | led_addr : out std_logic_vector(2 downto 0); 45 | lat : out std_logic; 46 | oe : out std_logic; 47 | -- Memory IO 48 | addr : out std_logic_vector(ADDR_WIDTH-1 downto 0); 49 | data : in std_logic_vector(DATA_WIDTH-1 downto 0) 50 | ); 51 | end ledctrl; 52 | 53 | architecture bhv of ledctrl is 54 | -- Internal signals 55 | signal clk : std_logic; 56 | 57 | -- Essential state machine signals 58 | type STATE_TYPE is (INIT, READ_PIXEL_DATA, INCR_RAM_ADDR, LATCH, INCR_LED_ADDR); 59 | signal state, next_state : STATE_TYPE; 60 | 61 | -- State machine signals 62 | signal col_count, next_col_count : unsigned(IMG_WIDTH_LOG2 downto 0); 63 | signal bpp_count, next_bpp_count : unsigned(PIXEL_DEPTH-1 downto 0); 64 | signal s_led_addr, next_led_addr : std_logic_vector(2 downto 0); 65 | signal s_ram_addr, next_ram_addr : std_logic_vector(ADDR_WIDTH-1 downto 0); 66 | signal s_rgb1, next_rgb1, s_rgb2, next_rgb2 : std_logic_vector(2 downto 0); 67 | signal s_oe, s_lat, s_clk_out : std_logic; 68 | begin 69 | 70 | -- A simple clock divider is used here to slow down this part of the circuit 71 | U_CLKDIV : entity work.clk_div 72 | generic map ( 73 | clk_in_freq => 50000000, -- 50MHz input clock 74 | clk_out_freq => 10000000 -- 10MHz output clock 75 | ) 76 | port map ( 77 | rst => rst, 78 | clk_in => clk_in, 79 | clk_out => clk 80 | ); 81 | 82 | -- Breakout internal signals to the output port 83 | led_addr <= s_led_addr; 84 | addr <= s_ram_addr; 85 | rgb1 <= s_rgb1; 86 | rgb2 <= s_rgb2; 87 | oe <= s_oe; 88 | lat <= s_lat; 89 | clk_out <= s_clk_out; 90 | 91 | -- State register 92 | process(rst, clk) 93 | begin 94 | if(rst = '1') then 95 | state <= INIT; 96 | col_count <= (others => '0'); 97 | bpp_count <= (others => '0'); 98 | s_led_addr <= (others => '1'); -- this inits to 111 because the led_addr is actually used *after* the incoming data is latched by the panel (not while being shifted in), so by then it has been "incremented" to 000 99 | s_ram_addr <= (others => '0'); 100 | s_rgb1 <= (others => '0'); 101 | s_rgb2 <= (others => '0'); 102 | elsif(rising_edge(clk)) then 103 | state <= next_state; 104 | col_count <= next_col_count; 105 | bpp_count <= next_bpp_count; 106 | s_led_addr <= next_led_addr; 107 | s_ram_addr <= next_ram_addr; 108 | s_rgb1 <= next_rgb1; 109 | s_rgb2 <= next_rgb2; 110 | end if; 111 | end process; 112 | 113 | -- Next-state logic 114 | process(state, col_count, bpp_count, s_led_addr, s_ram_addr, s_rgb1, s_rgb2, data) is 115 | -- Internal breakouts 116 | variable upper, lower : unsigned(DATA_WIDTH/2-1 downto 0); 117 | variable upper_r, upper_g, upper_b : unsigned(PIXEL_DEPTH-1 downto 0); 118 | variable lower_r, lower_g, lower_b : unsigned(PIXEL_DEPTH-1 downto 0); 119 | variable r1, g1, b1, r2, g2, b2 : std_logic; 120 | begin 121 | 122 | r1 := '0'; g1 := '0'; b1 := '0'; -- Defaults 123 | r2 := '0'; g2 := '0'; b2 := '0'; -- Defaults 124 | 125 | -- Default register next-state assignments 126 | next_col_count <= col_count; 127 | next_bpp_count <= bpp_count; 128 | next_led_addr <= s_led_addr; 129 | next_ram_addr <= s_ram_addr; 130 | next_rgb1 <= s_rgb1; 131 | next_rgb2 <= s_rgb2; 132 | 133 | -- Default signal assignments 134 | s_clk_out <= '0'; 135 | s_lat <= '0'; 136 | s_oe <= '1'; -- this signal is "active low" 137 | 138 | -- States 139 | case state is 140 | when INIT => 141 | if(s_led_addr = "111") then 142 | if(bpp_count = unsigned(to_signed(-2, PIXEL_DEPTH))) then 143 | next_bpp_count <= (others => '0'); 144 | else 145 | next_bpp_count <= bpp_count + 1; 146 | end if; 147 | end if; 148 | next_state <= READ_PIXEL_DATA; 149 | when READ_PIXEL_DATA => 150 | s_oe <= '0'; -- enable display 151 | -- Do parallel comparisons against BPP counter to gain multibit color 152 | if(upper_r > bpp_count) then 153 | r1 := '1'; 154 | end if; 155 | if(upper_g > bpp_count) then 156 | g1 := '1'; 157 | end if; 158 | if(upper_b > bpp_count) then 159 | b1 := '1'; 160 | end if; 161 | if(lower_r > bpp_count) then 162 | r2 := '1'; 163 | end if; 164 | if(lower_g > bpp_count) then 165 | g2 := '1'; 166 | end if; 167 | if(lower_b > bpp_count) then 168 | b2 := '1'; 169 | end if; 170 | next_col_count <= col_count + 1; -- update/increment column counter 171 | if(col_count < IMG_WIDTH) then -- check if at the rightmost side of the image 172 | next_state <= INCR_RAM_ADDR; 173 | else 174 | next_state <= INCR_LED_ADDR; 175 | end if; 176 | when INCR_RAM_ADDR => 177 | s_clk_out <= '1'; -- pulse the output clock 178 | s_oe <= '0'; -- enable display 179 | next_ram_addr <= std_logic_vector( unsigned(s_ram_addr) + 1 ); 180 | next_state <= READ_PIXEL_DATA; 181 | when INCR_LED_ADDR => 182 | -- display is disabled during led_addr (select lines) update 183 | next_led_addr <= std_logic_vector( unsigned(s_led_addr) + 1 ); 184 | next_col_count <= (others => '0'); -- reset the column counter 185 | next_state <= LATCH; 186 | when LATCH => 187 | -- display is disabled during latching 188 | s_lat <= '1'; -- latch the data 189 | next_state <= INIT; -- restart state machine 190 | when others => null; 191 | end case; 192 | 193 | -- Pixel data is given as 2 combined words, with the upper half containing 194 | -- the upper pixel and the lower half containing the lower pixel. Inside 195 | -- each half the pixel data is encoded in RGB order with multiple repeated 196 | -- bits for each subpixel depending on the chosen color depth. For example, 197 | -- a PIXEL_DEPTH of 3 results in a 18-bit word arranged RRRGGGBBBrrrgggbbb. 198 | -- The following assignments break up this encoding into the human-readable 199 | -- signals used above, or reconstruct it into LED data signals. 200 | upper := unsigned(data(DATA_WIDTH-1 downto DATA_WIDTH/2)); 201 | lower := unsigned(data(DATA_WIDTH/2-1 downto 0)); 202 | upper_r := upper(3*PIXEL_DEPTH-1 downto 2*PIXEL_DEPTH); 203 | upper_g := upper(2*PIXEL_DEPTH-1 downto PIXEL_DEPTH); 204 | upper_b := upper( PIXEL_DEPTH-1 downto 0); 205 | lower_r := lower(3*PIXEL_DEPTH-1 downto 2*PIXEL_DEPTH); 206 | lower_g := lower(2*PIXEL_DEPTH-1 downto PIXEL_DEPTH); 207 | lower_b := lower( PIXEL_DEPTH-1 downto 0); 208 | next_rgb1 <= r1 & g1 & b1; 209 | next_rgb2 <= r2 & g2 & b2; 210 | 211 | end process; 212 | 213 | end bhv; 214 | -------------------------------------------------------------------------------- /vhdl/megawizard/megawizard_vjtag.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component megawizard_vjtag 17 | PORT 18 | ( 19 | ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 20 | tdo : IN STD_LOGIC ; 21 | ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); 22 | tck : OUT STD_LOGIC ; 23 | tdi : OUT STD_LOGIC ; 24 | virtual_state_cdr : OUT STD_LOGIC ; 25 | virtual_state_cir : OUT STD_LOGIC ; 26 | virtual_state_e1dr : OUT STD_LOGIC ; 27 | virtual_state_e2dr : OUT STD_LOGIC ; 28 | virtual_state_pdr : OUT STD_LOGIC ; 29 | virtual_state_sdr : OUT STD_LOGIC ; 30 | virtual_state_udr : OUT STD_LOGIC ; 31 | virtual_state_uir : OUT STD_LOGIC 32 | ); 33 | end component; 34 | -------------------------------------------------------------------------------- /vhdl/megawizard/megawizard_vjtag.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "Virtual JTAG" 2 | set_global_assignment -name IP_TOOL_VERSION "10.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "megawizard_vjtag.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "megawizard_vjtag_inst.vhd"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "megawizard_vjtag.cmp"] 6 | -------------------------------------------------------------------------------- /vhdl/megawizard/megawizard_vjtag.vhd: -------------------------------------------------------------------------------- 1 | -- megafunction wizard: %Virtual JTAG% 2 | -- GENERATION: STANDARD 3 | -- VERSION: WM1.0 4 | -- MODULE: sld_virtual_jtag 5 | 6 | -- ============================================================ 7 | -- File Name: megawizard_vjtag.vhd 8 | -- Megafunction Name(s): 9 | -- sld_virtual_jtag 10 | -- 11 | -- Simulation Library Files(s): 12 | -- altera_mf 13 | -- ============================================================ 14 | -- ************************************************************ 15 | -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | -- 17 | -- 10.1 Build 153 11/29/2010 SJ Web Edition 18 | -- ************************************************************ 19 | 20 | 21 | --Copyright (C) 1991-2010 Altera Corporation 22 | --Your use of Altera Corporation's design tools, logic functions 23 | --and other software and tools, and its AMPP partner logic 24 | --functions, and any output files from any of the foregoing 25 | --(including device programming or simulation files), and any 26 | --associated documentation or information are expressly subject 27 | --to the terms and conditions of the Altera Program License 28 | --Subscription Agreement, Altera MegaCore Function License 29 | --Agreement, or other applicable license agreement, including, 30 | --without limitation, that your use is for the sole purpose of 31 | --programming logic devices manufactured by Altera and sold by 32 | --Altera or its authorized distributors. Please refer to the 33 | --applicable agreement for further details. 34 | 35 | 36 | LIBRARY ieee; 37 | USE ieee.std_logic_1164.all; 38 | 39 | LIBRARY altera_mf; 40 | USE altera_mf.all; 41 | 42 | ENTITY megawizard_vjtag IS 43 | PORT 44 | ( 45 | ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 46 | tdo : IN STD_LOGIC ; 47 | ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); 48 | tck : OUT STD_LOGIC ; 49 | tdi : OUT STD_LOGIC ; 50 | virtual_state_cdr : OUT STD_LOGIC ; 51 | virtual_state_cir : OUT STD_LOGIC ; 52 | virtual_state_e1dr : OUT STD_LOGIC ; 53 | virtual_state_e2dr : OUT STD_LOGIC ; 54 | virtual_state_pdr : OUT STD_LOGIC ; 55 | virtual_state_sdr : OUT STD_LOGIC ; 56 | virtual_state_udr : OUT STD_LOGIC ; 57 | virtual_state_uir : OUT STD_LOGIC 58 | ); 59 | END megawizard_vjtag; 60 | 61 | 62 | ARCHITECTURE SYN OF megawizard_vjtag IS 63 | 64 | SIGNAL sub_wire0 : STD_LOGIC ; 65 | SIGNAL sub_wire1 : STD_LOGIC ; 66 | SIGNAL sub_wire2 : STD_LOGIC_VECTOR (1 DOWNTO 0); 67 | SIGNAL sub_wire3 : STD_LOGIC ; 68 | SIGNAL sub_wire4 : STD_LOGIC ; 69 | SIGNAL sub_wire5 : STD_LOGIC ; 70 | SIGNAL sub_wire6 : STD_LOGIC ; 71 | SIGNAL sub_wire7 : STD_LOGIC ; 72 | SIGNAL sub_wire8 : STD_LOGIC ; 73 | SIGNAL sub_wire9 : STD_LOGIC ; 74 | SIGNAL sub_wire10 : STD_LOGIC ; 75 | 76 | 77 | 78 | COMPONENT sld_virtual_jtag 79 | GENERIC ( 80 | sld_auto_instance_index : STRING; 81 | sld_instance_index : NATURAL; 82 | sld_ir_width : NATURAL; 83 | sld_sim_action : STRING; 84 | sld_sim_n_scan : NATURAL; 85 | sld_sim_total_length : NATURAL; 86 | lpm_type : STRING 87 | ); 88 | PORT ( 89 | virtual_state_cir : OUT STD_LOGIC ; 90 | virtual_state_pdr : OUT STD_LOGIC ; 91 | ir_in : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); 92 | tdi : OUT STD_LOGIC ; 93 | virtual_state_udr : OUT STD_LOGIC ; 94 | ir_out : IN STD_LOGIC_VECTOR (1 DOWNTO 0); 95 | tck : OUT STD_LOGIC ; 96 | virtual_state_e1dr : OUT STD_LOGIC ; 97 | virtual_state_uir : OUT STD_LOGIC ; 98 | tdo : IN STD_LOGIC ; 99 | virtual_state_cdr : OUT STD_LOGIC ; 100 | virtual_state_e2dr : OUT STD_LOGIC ; 101 | virtual_state_sdr : OUT STD_LOGIC 102 | ); 103 | END COMPONENT; 104 | 105 | BEGIN 106 | virtual_state_cir <= sub_wire0; 107 | virtual_state_pdr <= sub_wire1; 108 | ir_in <= sub_wire2(1 DOWNTO 0); 109 | tdi <= sub_wire3; 110 | virtual_state_udr <= sub_wire4; 111 | tck <= sub_wire5; 112 | virtual_state_e1dr <= sub_wire6; 113 | virtual_state_uir <= sub_wire7; 114 | virtual_state_cdr <= sub_wire8; 115 | virtual_state_e2dr <= sub_wire9; 116 | virtual_state_sdr <= sub_wire10; 117 | 118 | sld_virtual_jtag_component : sld_virtual_jtag 119 | GENERIC MAP ( 120 | sld_auto_instance_index => "YES", 121 | sld_instance_index => 0, 122 | sld_ir_width => 2, 123 | sld_sim_action => "", 124 | sld_sim_n_scan => 0, 125 | sld_sim_total_length => 0, 126 | lpm_type => "sld_virtual_jtag" 127 | ) 128 | PORT MAP ( 129 | ir_out => ir_out, 130 | tdo => tdo, 131 | virtual_state_cir => sub_wire0, 132 | virtual_state_pdr => sub_wire1, 133 | ir_in => sub_wire2, 134 | tdi => sub_wire3, 135 | virtual_state_udr => sub_wire4, 136 | tck => sub_wire5, 137 | virtual_state_e1dr => sub_wire6, 138 | virtual_state_uir => sub_wire7, 139 | virtual_state_cdr => sub_wire8, 140 | virtual_state_e2dr => sub_wire9, 141 | virtual_state_sdr => sub_wire10 142 | ); 143 | 144 | 145 | 146 | END SYN; 147 | 148 | -- ============================================================ 149 | -- CNX file retrieval info 150 | -- ============================================================ 151 | -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 152 | -- Retrieval info: PRIVATE: show_jtag_state STRING "0" 153 | -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 154 | -- Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 155 | -- Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 156 | -- Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "2" 157 | -- Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "" 158 | -- Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "0" 159 | -- Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "0" 160 | -- Retrieval info: USED_PORT: ir_in 0 0 2 0 OUTPUT NODEFVAL "ir_in[1..0]" 161 | -- Retrieval info: USED_PORT: ir_out 0 0 2 0 INPUT NODEFVAL "ir_out[1..0]" 162 | -- Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck" 163 | -- Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi" 164 | -- Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo" 165 | -- Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr" 166 | -- Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir" 167 | -- Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr" 168 | -- Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr" 169 | -- Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr" 170 | -- Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr" 171 | -- Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr" 172 | -- Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir" 173 | -- Retrieval info: CONNECT: @ir_out 0 0 2 0 ir_out 0 0 2 0 174 | -- Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0 175 | -- Retrieval info: CONNECT: ir_in 0 0 2 0 @ir_in 0 0 2 0 176 | -- Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0 177 | -- Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0 178 | -- Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0 179 | -- Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0 180 | -- Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0 181 | -- Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0 182 | -- Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0 183 | -- Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0 184 | -- Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0 185 | -- Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0 186 | -- Retrieval info: GEN_FILE: TYPE_NORMAL megawizard_vjtag.vhd TRUE 187 | -- Retrieval info: GEN_FILE: TYPE_NORMAL megawizard_vjtag.inc FALSE 188 | -- Retrieval info: GEN_FILE: TYPE_NORMAL megawizard_vjtag.cmp TRUE 189 | -- Retrieval info: GEN_FILE: TYPE_NORMAL megawizard_vjtag.bsf FALSE 190 | -- Retrieval info: GEN_FILE: TYPE_NORMAL megawizard_vjtag_inst.vhd TRUE 191 | -- Retrieval info: LIB_FILE: altera_mf 192 | -------------------------------------------------------------------------------- /vhdl/megawizard/megawizard_vjtag_inst.vhd: -------------------------------------------------------------------------------- 1 | megawizard_vjtag_inst : megawizard_vjtag PORT MAP ( 2 | ir_out => ir_out_sig, 3 | tdo => tdo_sig, 4 | ir_in => ir_in_sig, 5 | tck => tck_sig, 6 | tdi => tdi_sig, 7 | virtual_state_cdr => virtual_state_cdr_sig, 8 | virtual_state_cir => virtual_state_cir_sig, 9 | virtual_state_e1dr => virtual_state_e1dr_sig, 10 | virtual_state_e2dr => virtual_state_e2dr_sig, 11 | virtual_state_pdr => virtual_state_pdr_sig, 12 | virtual_state_sdr => virtual_state_sdr_sig, 13 | virtual_state_udr => virtual_state_udr_sig, 14 | virtual_state_uir => virtual_state_uir_sig 15 | ); 16 | -------------------------------------------------------------------------------- /vhdl/memory.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Special memory for the framebuffer with separate read/write clocks 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | -- For more information on how to infer RAMs on Altera devices see this page: 26 | -- http://quartushelp.altera.com/current/mergedProjects/hdl/vhdl/vhdl_pro_ram_inferred.htm 27 | 28 | library ieee; 29 | use ieee.std_logic_1164.all; 30 | use ieee.numeric_std.all; 31 | use ieee.std_logic_unsigned.all; 32 | 33 | use work.rgbmatrix.all; 34 | 35 | entity memory is 36 | port ( 37 | rst : in std_logic; 38 | clk_wr : in std_logic; 39 | input : in std_logic_vector(DATA_WIDTH-1 downto 0); 40 | clk_rd : in std_logic; 41 | addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); 42 | output : out std_logic_vector(DATA_WIDTH-1 downto 0) 43 | ); 44 | end memory; 45 | 46 | architecture bhv of memory is 47 | -- Internal signals 48 | signal waddr, next_waddr : std_logic_vector(ADDR_WIDTH-1 downto 0); 49 | 50 | -- Inferred RAM storage signal 51 | type ram is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); 52 | signal ram_block : ram; 53 | begin 54 | 55 | -- Create an adder to calculate the next write address 56 | next_waddr <= std_logic_vector( unsigned(waddr) + 1 ); 57 | 58 | -- Write process for the memory 59 | process(rst, clk_wr, next_waddr) 60 | begin 61 | if(rst = '1') then 62 | waddr <= (others => '0'); -- reset the write address to the beginning 63 | elsif(rising_edge(clk_wr)) then 64 | ram_block(conv_integer(waddr)) <= input; -- store input at the current write address 65 | waddr <= next_waddr; -- allow the write address to increment 66 | end if; 67 | end process; 68 | 69 | -- Read process for the memory 70 | process(clk_rd) 71 | begin 72 | if(rising_edge(clk_rd)) then 73 | output <= ram_block(conv_integer(addr)); -- retrieve contents at the given read address 74 | end if; 75 | end process; 76 | 77 | end bhv; 78 | -------------------------------------------------------------------------------- /vhdl/testbenches/ledctrl_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Testbench for simulation of the LED matrix finite state machine 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | library ieee; 26 | use ieee.std_logic_1164.all; 27 | 28 | use work.rgbmatrix.all; 29 | 30 | entity ledctrl_tb is 31 | end ledctrl_tb; 32 | 33 | architecture tb of ledctrl_tb is 34 | constant clk_period : time := 20 ns; -- for a 50MHz clock 35 | constant num_cycles : positive := 10; -- change this to your liking 36 | -- 37 | signal clk_in, rst, clk_out, lat, oe : std_logic; 38 | signal rgb1 : std_logic_vector(2 downto 0); 39 | signal rgb2 : std_logic_vector(2 downto 0); 40 | signal led_addr : std_logic_vector(2 downto 0); 41 | signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0); 42 | signal data : std_logic_vector(DATA_WIDTH-1 downto 0); 43 | begin 44 | 45 | -- Instantiate the Unit Under Test (UUT) 46 | UUT : entity work.ledctrl 47 | port map ( 48 | clk_in => clk_in, 49 | rst => rst, 50 | clk_out => clk_out, 51 | rgb1 => rgb1, 52 | rgb2 => rgb2, 53 | led_addr => led_addr, 54 | lat => lat, 55 | oe => oe, 56 | addr => addr, 57 | data => data 58 | ); 59 | 60 | -- Clock process 61 | process 62 | begin 63 | clk_in <= '0'; 64 | wait for clk_period/2; 65 | clk_in <= '1'; 66 | wait for clk_period/2; 67 | end process; 68 | 69 | -- Stimulus process 70 | process 71 | begin 72 | data <= (others => '0'); 73 | -- Hold reset state 74 | rst <= '1'; 75 | wait for clk_period/2; 76 | rst <= '0'; 77 | -- Perform the simulation 78 | wait for clk_period*num_cycles; 79 | -- Wait forever 80 | wait; 81 | end process; 82 | 83 | end tb; 84 | -------------------------------------------------------------------------------- /vhdl/testbenches/memory_tb.vhd: -------------------------------------------------------------------------------- 1 | -- Testbench for simulation of the special memory for the framebuffer 2 | -- 3 | -- Copyright (c) 2012 Brian Nezvadovitz 4 | -- This software is distributed under the terms of the MIT License shown below. 5 | -- 6 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 7 | -- of this software and associated documentation files (the "Software"), to 8 | -- deal in the Software without restriction, including without limitation the 9 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 | -- sell copies of the Software, and to permit persons to whom the Software is 11 | -- furnished to do so, subject to the following conditions: 12 | -- 13 | -- The above copyright notice and this permission notice shall be included in 14 | -- all copies or substantial portions of the Software. 15 | -- 16 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 | -- IN THE SOFTWARE. 23 | 24 | library ieee; 25 | use ieee.std_logic_1164.all; 26 | 27 | use work.rgbmatrix.all; 28 | 29 | entity memory_tb is 30 | end memory_tb; 31 | 32 | architecture tb of memory_tb is 33 | signal rst, clk_wr, clk_rd : std_logic; 34 | signal input, output : std_logic_vector(DATA_WIDTH-1 downto 0); 35 | signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0); 36 | constant clk_period : time := 20 ns; -- for a 50MHz clock 37 | constant num_cycles : positive := 50; -- change this to your liking 38 | begin 39 | 40 | -- Instantiate the Unit Under Test (UUT) 41 | UUT : entity work.memory 42 | port map ( 43 | rst => rst, 44 | clk_wr => clk_wr, 45 | input => input, 46 | clk_rd => clk_rd, 47 | addr => addr, 48 | output => output 49 | ); 50 | 51 | -- Clock process 52 | process 53 | begin 54 | clk_rd <= '0'; 55 | wait for clk_period/2; 56 | clk_rd <= '1'; 57 | wait for clk_period/2; 58 | end process; 59 | 60 | -- Stimulus process 61 | process 62 | begin 63 | -- Hold reset state 64 | rst <= '1'; 65 | clk_wr <= '0'; 66 | input <= "000000"; 67 | addr <= (others => '0'); 68 | wait for clk_period; 69 | rst <= '0'; 70 | -- Perform the simulation 71 | wait for clk_period; 72 | input <= "000111"; 73 | clk_wr <= '1'; 74 | wait for clk_period; 75 | input <= "111000"; 76 | wait for clk_period; 77 | clk_wr <= '0'; 78 | wait for clk_period; 79 | input <= "010101"; 80 | clk_wr <= '1'; 81 | wait for clk_period; 82 | clk_wr <= '0'; 83 | wait for clk_period*3; 84 | -- Wait forever 85 | wait; 86 | end process; 87 | 88 | end tb; 89 | -------------------------------------------------------------------------------- /vhdl/testbenches/testbench.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Testbench for simulation of the top level entity 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | library ieee; 26 | use ieee.std_logic_1164.all; 27 | 28 | entity testbench is 29 | end testbench; 30 | 31 | architecture tb of testbench is 32 | signal clk_in, rst_n : std_logic; 33 | signal clk_out, r1, r2, b1, b2, g1, g2, a, b, c, lat, oe : std_logic; 34 | constant clk_period : time := 20 ns; -- for a 50MHz clock 35 | constant num_cycles : positive := 10; -- change this to your liking 36 | begin 37 | 38 | -- Instantiate the Unit Under Test (UUT) 39 | UUT : entity work.top_level 40 | port map ( 41 | clk_in => clk_in, 42 | rst_n => rst_n, 43 | clk_out => clk_out, 44 | r1 => r1, 45 | r2 => r2, 46 | b1 => b1, 47 | b2 => b2, 48 | g1 => g1, 49 | g2 => g2, 50 | a => a, 51 | b => b, 52 | c => c, 53 | lat => lat, 54 | oe => oe 55 | ); 56 | 57 | -- Clock process 58 | process 59 | begin 60 | clk_in <= '0'; 61 | wait for clk_period/2; 62 | clk_in <= '1'; 63 | wait for clk_period/2; 64 | end process; 65 | 66 | -- Stimulus process 67 | process 68 | begin 69 | -- Hold reset state 70 | rst_n <= '0'; 71 | wait for clk_period/2; 72 | rst_n <= '1'; 73 | -- Perform the simulation 74 | wait for clk_period*num_cycles; 75 | -- Wait forever 76 | wait; 77 | end process; 78 | 79 | end tb; 80 | -------------------------------------------------------------------------------- /vhdl/top_level.vhd: -------------------------------------------------------------------------------- 1 | -- Adafruit RGB LED Matrix Display Driver 2 | -- Top Level Entity 3 | -- 4 | -- Copyright (c) 2012 Brian Nezvadovitz 5 | -- This software is distributed under the terms of the MIT License shown below. 6 | -- 7 | -- Permission is hereby granted, free of charge, to any person obtaining a copy 8 | -- of this software and associated documentation files (the "Software"), to 9 | -- deal in the Software without restriction, including without limitation the 10 | -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 | -- sell copies of the Software, and to permit persons to whom the Software is 12 | -- furnished to do so, subject to the following conditions: 13 | -- 14 | -- The above copyright notice and this permission notice shall be included in 15 | -- all copies or substantial portions of the Software. 16 | -- 17 | -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 | -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 | -- IN THE SOFTWARE. 24 | 25 | library ieee; 26 | use ieee.std_logic_1164.all; 27 | 28 | use work.rgbmatrix.all; -- Constants & Configuration 29 | 30 | entity top_level is 31 | port ( 32 | clk_in : in std_logic; 33 | rst_n : in std_logic; 34 | clk_out : out std_logic; 35 | r1 : out std_logic; 36 | r2 : out std_logic; 37 | b1 : out std_logic; 38 | b2 : out std_logic; 39 | g1 : out std_logic; 40 | g2 : out std_logic; 41 | a : out std_logic; 42 | b : out std_logic; 43 | c : out std_logic; 44 | lat : out std_logic; 45 | oe : out std_logic 46 | ); 47 | end top_level; 48 | 49 | architecture str of top_level is 50 | -- Reset signals 51 | signal rst, rst_p, jtag_rst_out : std_logic; 52 | 53 | -- Memory signals 54 | signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0); 55 | signal data_incoming : std_logic_vector(DATA_WIDTH-1 downto 0); 56 | signal data_outgoing : std_logic_vector(DATA_WIDTH-1 downto 0); 57 | 58 | -- Flags 59 | signal data_valid : std_logic; 60 | begin 61 | 62 | -- Reset button is an "active low" input, invert it so we can treat is as 63 | -- "active high", then OR it with the JTAG reset command output signal. 64 | rst_p <= not rst_n; 65 | rst <= rst_p or jtag_rst_out; 66 | 67 | -- LED panel controller 68 | U_LEDCTRL : entity work.ledctrl 69 | port map ( 70 | rst => rst, 71 | clk_in => clk_in, 72 | -- Connection to LED panel 73 | clk_out => clk_out, 74 | rgb1(2) => r1, 75 | rgb1(1) => g1, 76 | rgb1(0) => b1, 77 | rgb2(2) => r2, 78 | rgb2(1) => g2, 79 | rgb2(0) => b2, 80 | led_addr(2) => c, 81 | led_addr(1) => b, 82 | led_addr(0) => a, 83 | lat => lat, 84 | oe => oe, 85 | -- Connection with framebuffer 86 | addr => addr, 87 | data => data_outgoing 88 | ); 89 | 90 | -- Virtual JTAG interface 91 | U_JTAGIFACE : entity work.jtag_iface 92 | port map ( 93 | rst => rst, 94 | rst_out => jtag_rst_out, 95 | output => data_incoming, 96 | valid => data_valid 97 | ); 98 | 99 | -- Special memory for the framebuffer 100 | U_MEMORY : entity work.memory 101 | port map ( 102 | rst => rst, 103 | -- Writing side 104 | clk_wr => data_valid, 105 | input => data_incoming, 106 | -- Reading side 107 | clk_rd => clk_in, 108 | addr => addr, 109 | output => data_outgoing 110 | ); 111 | 112 | end str; 113 | --------------------------------------------------------------------------------