├── .gitmodules ├── LICENSE ├── README.md ├── gateware ├── .gitignore ├── Makefile ├── README.md ├── daqnet │ ├── .gitignore │ ├── __init__.py │ ├── __main__.py │ ├── ethernet │ │ ├── __init__.py │ │ ├── crc.py │ │ ├── ip.py │ │ ├── mac.py │ │ ├── mac_address_match.py │ │ ├── mdio.py │ │ └── rmii.py │ ├── platform.py │ ├── top.py │ ├── user.py │ └── utils.py └── pytest.ini ├── hardware ├── .gitignore ├── interposer │ ├── fp-info-cache │ ├── fp-lib-table │ ├── gerber │ │ ├── agg-daqnet-interposer-r1-20181201.zip │ │ ├── interposer-B.Cu.gbl │ │ ├── interposer-B.Mask.gbs │ │ ├── interposer-B.Paste.gbp │ │ ├── interposer-B.SilkS.gbo │ │ ├── interposer-Edge.Cuts.gm1 │ │ ├── interposer-F.Cu.gtl │ │ ├── interposer-F.Mask.gts │ │ ├── interposer-F.Paste.gtp │ │ ├── interposer-F.SilkS.gto │ │ ├── interposer-NPTH.drl │ │ └── interposer-PTH.drl │ ├── interposer-cache.lib │ ├── interposer.bom │ ├── interposer.kicad_pcb │ ├── interposer.pro │ ├── interposer.sch │ ├── interposer.xml │ └── sym-lib-table ├── proto-sensor │ ├── fp-info-cache │ ├── fp-lib-table │ ├── gerber │ │ ├── proto-sensor-B.Cu.gbl │ │ ├── proto-sensor-B.Mask.gbs │ │ ├── proto-sensor-B.Paste.gbp │ │ ├── proto-sensor-B.SilkS.gbo │ │ ├── proto-sensor-Edge.Cuts.gm1 │ │ ├── proto-sensor-F.Cu.gtl │ │ ├── proto-sensor-F.Mask.gts │ │ ├── proto-sensor-F.Paste.gtp │ │ ├── proto-sensor-F.SilkS.gto │ │ ├── proto-sensor-In1.Cu.g2 │ │ ├── proto-sensor-In2.Cu.g3 │ │ ├── proto-sensor-NPTH.drl │ │ ├── proto-sensor-PTH.drl │ │ └── proto-sensor.zip │ ├── proto-sensor-cache.lib │ ├── proto-sensor-pcb-back.png │ ├── proto-sensor-pcb.png │ ├── proto-sensor.bom │ ├── proto-sensor.kicad_pcb │ ├── proto-sensor.pdf │ ├── proto-sensor.png │ ├── proto-sensor.pro │ ├── proto-sensor.sch │ ├── proto-sensor.xml │ ├── proto-sensor_bom.pdf │ └── sym-lib-table ├── proto-switch │ ├── daqnet.sch │ ├── ethernet.sch │ ├── fp-info-cache │ ├── fp-lib-table │ ├── gerber │ │ ├── proto-switch-B.Cu.gbr │ │ ├── proto-switch-B.Mask.gbr │ │ ├── proto-switch-B.Paste.gbr │ │ ├── proto-switch-B.SilkS.gbr │ │ ├── proto-switch-Edge.Cuts.gbr │ │ ├── proto-switch-F.Cu.gbr │ │ ├── proto-switch-F.Mask.gbr │ │ ├── proto-switch-F.Paste.gbr │ │ ├── proto-switch-F.SilkS.gbr │ │ ├── proto-switch-In1.Cu.gbr │ │ ├── proto-switch-In2.Cu.gbr │ │ ├── proto-switch-NPTH.drl │ │ └── proto-switch-PTH.drl │ ├── ice40.sch │ ├── ports.sch │ ├── power.sch │ ├── proto-switch-cache.lib │ ├── proto-switch.bom │ ├── proto-switch.kicad_pcb │ ├── proto-switch.pro │ ├── proto-switch.sch │ ├── proto-switch.xml │ ├── proto-switch_bom.pdf │ ├── stm32.sch │ └── sym-lib-table └── rtm │ ├── 20181127_bom.ods │ ├── gerber │ ├── agg-tbge-pr1-20181127.zip │ ├── proto_switch_sensor_r1_panel-B.Cu.gbl │ ├── proto_switch_sensor_r1_panel-B.Mask.gbs │ ├── proto_switch_sensor_r1_panel-B.SilkS.gbo │ ├── proto_switch_sensor_r1_panel-Edge.Cuts.gm1 │ ├── proto_switch_sensor_r1_panel-F.Cu.gtl │ ├── proto_switch_sensor_r1_panel-F.Mask.gts │ ├── proto_switch_sensor_r1_panel-F.Paste.gtp │ ├── proto_switch_sensor_r1_panel-F.SilkS.gto │ ├── proto_switch_sensor_r1_panel-In1.Cu.g2 │ ├── proto_switch_sensor_r1_panel-In2.Cu.g3 │ └── proto_switch_sensor_r1_panel.drl │ └── proto_switch_sensor_r1_panel.kicad_pcb └── software └── scripts ├── plot.py ├── run_leds.py └── user.py /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "hardware/agg-kicad"] 2 | path = hardware/agg-kicad 3 | url = https://github.com/adamgreig/agg-kicad.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2018-2019 Adam Greig 2 | 3 | Permission is hereby granted, free of charge, to any 4 | person obtaining a copy of this software and associated 5 | documentation files (the "Software"), to deal in the 6 | Software without restriction, including without 7 | limitation the rights to use, copy, modify, merge, 8 | publish, distribute, sublicense, and/or sell copies of 9 | the Software, and to permit persons to whom the Software 10 | is furnished to do so, subject to the following 11 | conditions: 12 | 13 | The above copyright notice and this permission notice 14 | shall be included in all copies or substantial portions 15 | of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 18 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 19 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 20 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 21 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 24 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 | DEALINGS IN THE SOFTWARE. 26 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DAQnet 2 | 3 | Experiment into FPGAs for distributed data acquisition. 4 | -------------------------------------------------------------------------------- /gateware/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | .pytest_cache/ 3 | *.vcd 4 | -------------------------------------------------------------------------------- /gateware/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: program 2 | program: 3 | /home/adam/Projects/amp_flashprog/prog.py --fpga build/switch.bin 4 | 5 | .PHONY: clean 6 | clean: 7 | $(RM) -rf build 8 | -------------------------------------------------------------------------------- /gateware/README.md: -------------------------------------------------------------------------------- 1 | # DAQnet Gateware 2 | 3 | This folder contains FPGA gateware for DAQnet hardware. 4 | 5 | To build bitstreams: 6 | 7 | ``` 8 | $ python3 -m daqnet switch 9 | # or 10 | $ python3 -m daqnet sensor 11 | ``` 12 | -------------------------------------------------------------------------------- /gateware/daqnet/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ 2 | -------------------------------------------------------------------------------- /gateware/daqnet/__init__.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import subprocess 3 | 4 | from .platform import SensorPlatform, SwitchPlatform 5 | from .top import SensorTop, SwitchTop 6 | 7 | 8 | def main(): 9 | parser = argparse.ArgumentParser() 10 | parser.add_argument("device", choices=["switch", "sensor"]) 11 | parser.add_argument("--seed", type=int, default=0) 12 | parser.add_argument("--verilog", action="store_true") 13 | parser.add_argument("--program", action="store_true") 14 | parser.add_argument("--flash", action="store_true") 15 | args = parser.parse_args() 16 | if args.device == "switch": 17 | plat = SwitchPlatform() 18 | top = SwitchTop(plat, args) 19 | elif args.device == "sensor": 20 | plat = SensorPlatform() 21 | top = SensorTop(plat, args) 22 | plat.build(top, args.device, "build/", synth_opts=["-relut"], 23 | nextpnr_opts=["--seed", args.seed, "--freq", 100, 24 | "--placer", "heap"]) 25 | if args.program: 26 | subprocess.run( 27 | ["ffp", "fpga", "program", "build/{}.bin".format(args.device)]) 28 | if args.flash: 29 | subprocess.run( 30 | ["ffp", "flash", "program", "build/{}.bin".format(args.device)]) 31 | -------------------------------------------------------------------------------- /gateware/daqnet/__main__.py: -------------------------------------------------------------------------------- 1 | from daqnet import main 2 | 3 | if __name__ == "__main__": 4 | main() 5 | -------------------------------------------------------------------------------- /gateware/daqnet/ethernet/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/gateware/daqnet/ethernet/__init__.py -------------------------------------------------------------------------------- /gateware/daqnet/ethernet/crc.py: -------------------------------------------------------------------------------- 1 | """ 2 | Ethernet CRC32 Module 3 | 4 | Copyright 2018-2019 Adam Greig 5 | Released under the MIT license; see LICENSE for details. 6 | """ 7 | 8 | from nmigen import Elaboratable, Module, Signal, Memory 9 | 10 | 11 | class CRC32(Elaboratable): 12 | """ 13 | Ethernet CRC32 14 | 15 | Processes one byte of data every two clock cycles. 16 | 17 | Inputs: 18 | * `reset`: Re-initialises CRC to start state while high 19 | * `data`: 8-bit input data 20 | * `data_valid`: Pulsed high when new data is ready at `data`. 21 | Requires one clock to process between new data. 22 | 23 | Outputs: 24 | * `crc_out`: complement of current 32-bit CRC value 25 | * `crc_match`: high if crc residual is currently 0xC704DD7B 26 | 27 | When using for transmission, note that `crc_out` must be sent in little 28 | endian (i.e. if `crc_out` is 0xAABBCCDD then transmit 0xDD 0xCC 0xBB 0xAA). 29 | """ 30 | def __init__(self): 31 | # Inputs 32 | self.reset = Signal() 33 | self.data = Signal(8) 34 | self.data_valid = Signal() 35 | 36 | # Outputs 37 | self.crc_out = Signal(32) 38 | self.crc_match = Signal() 39 | 40 | def elaborate(self, platform): 41 | 42 | m = Module() 43 | crc = Signal(32) 44 | 45 | self.crctable = Memory(32, 256, make_crc32_table()) 46 | table_port = self.crctable.read_port() 47 | m.submodules += table_port 48 | 49 | m.d.comb += [ 50 | self.crc_out.eq(crc ^ 0xFFFFFFFF), 51 | self.crc_match.eq(crc == 0xDEBB20E3), 52 | table_port.addr.eq(crc ^ self.data), 53 | ] 54 | 55 | with m.FSM(): 56 | with m.State("RESET"): 57 | m.d.sync += crc.eq(0xFFFFFFFF) 58 | m.next = "IDLE" 59 | 60 | with m.State("IDLE"): 61 | with m.If(self.reset): 62 | m.next = "RESET" 63 | with m.Elif(self.data_valid): 64 | m.next = "BUSY" 65 | 66 | with m.State("BUSY"): 67 | with m.If(self.reset): 68 | m.next = "RESET" 69 | m.d.sync += crc.eq(table_port.data ^ (crc >> 8)) 70 | m.next = "IDLE" 71 | 72 | return m 73 | 74 | 75 | def make_crc32_table(): 76 | poly = 0x04C11DB7 77 | table = [] 78 | for i in range(256): 79 | ir = int(f"{i:08b}"[::-1], 2) 80 | r = ir << 24 81 | for _ in range(8): 82 | if r & (1 << 31): 83 | r = ((r << 1) & 0xFFFFFFFF) ^ poly 84 | else: 85 | r = (r << 1) & 0xFFFFFFFF 86 | r = int(f"{r:032b}"[::-1], 2) 87 | table.append(r) 88 | return table 89 | 90 | 91 | def test_crc32(): 92 | from nmigen.back import pysim 93 | crc = CRC32() 94 | 95 | def testbench(): 96 | yield 97 | yield 98 | for byte in [ord(x) for x in "123456789"]: 99 | yield (crc.data.eq(byte)) 100 | yield (crc.data_valid.eq(1)) 101 | yield 102 | yield (crc.data_valid.eq(0)) 103 | yield (crc.data.eq(0)) 104 | yield 105 | yield 106 | out = yield (crc.crc_out) 107 | assert out == 0xCBF43926 108 | 109 | vcdf = open("crc32.vcd", "w") 110 | with pysim.Simulator(crc, vcd_file=vcdf) as sim: 111 | sim.add_clock(1e-6) 112 | sim.add_sync_process(testbench()) 113 | sim.run() 114 | 115 | 116 | def test_crc32_match(): 117 | from nmigen.back import pysim 118 | crc = CRC32() 119 | 120 | frame = [ 121 | 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xDE, 0xF1, 0x38, 0x89, 0x40, 122 | 0x08, 0x00, 0x45, 0x00, 0x00, 0x54, 0x00, 0x00, 0x40, 0x00, 0x40, 0x01, 123 | 0xB6, 0xD0, 0xC0, 0xA8, 0x01, 0x88, 0xC0, 0xA8, 0x01, 0x00, 0x08, 0x00, 124 | 0x0D, 0xD9, 0x12, 0x1E, 0x00, 0x07, 0x3B, 0x3E, 0x0C, 0x5C, 0x00, 0x00, 125 | 0x00, 0x00, 0x13, 0x03, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x57, 126 | 0x6F, 0x72, 0x6C, 0x64, 0x48, 0x65, 0x6C, 0x6C, 0x6F, 0x20, 0x57, 0x6F, 127 | 0x72, 0x6C, 0x64, 0x48, 0x65, 0x6C, 0x6C, 0x6F, 0x20, 0x57, 0x6F, 0x72, 128 | 0x6C, 0x64, 0x48, 0x65, 0x6C, 0x6C, 0x6F, 0x20, 0x57, 0x6F, 0x72, 0x6C, 129 | 0x64, 0x48, 0x52, 0x32, 0x1F, 0x9E 130 | ] 131 | 132 | def testbench(): 133 | yield 134 | yield 135 | for byte in frame: 136 | yield (crc.data.eq(byte)) 137 | yield (crc.data_valid.eq(1)) 138 | yield 139 | yield (crc.data_valid.eq(0)) 140 | yield (crc.data.eq(0)) 141 | yield 142 | yield 143 | match = yield (crc.crc_match) 144 | assert match == 1 145 | 146 | vcdf = open("crc32_match.vcd", "w") 147 | with pysim.Simulator(crc, vcd_file=vcdf) as sim: 148 | sim.add_clock(1e-6) 149 | sim.add_sync_process(testbench()) 150 | sim.run() 151 | 152 | 153 | def test_crc32_py(): 154 | check = 0xCBF43926 155 | 156 | data = [ord(x) for x in "123456789"] 157 | 158 | table = make_crc32_table() 159 | 160 | # init 161 | crc = 0xFFFFFFFF 162 | 163 | # process 164 | for byte in data: 165 | crc = table[(crc & 0xFF) ^ byte] ^ (crc >> 8) 166 | 167 | # xorout 168 | crc ^= 0xFFFFFFFF 169 | 170 | assert hex(crc) == hex(check) 171 | -------------------------------------------------------------------------------- /gateware/daqnet/ethernet/mac.py: -------------------------------------------------------------------------------- 1 | """ 2 | Ethernet RMII MAC 3 | 4 | Copyright 2018-2019 Adam Greig 5 | Released under the MIT license; see LICENSE for details. 6 | """ 7 | 8 | from nmigen import Elaboratable, Module, Signal, Const, Memory, ClockDomain 9 | from nmigen import Cat 10 | from nmigen.lib.fifo import AsyncFIFO 11 | from nmigen.hdl.xfrm import DomainRenamer 12 | from .mdio import MDIO 13 | from .rmii import RMIIRx, RMIITx 14 | from ..utils import PulseStretch 15 | 16 | 17 | class MAC(Elaboratable): 18 | """ 19 | Ethernet RMII MAC. 20 | 21 | Clock domain: 22 | This module is clocked at the system clock frequency and generates an 23 | RMII clock domain internally. All its inputs and outputs are in the 24 | system clock domain. 25 | 26 | Parameters: 27 | * `clk_freq`: MAC's clock frequency 28 | * `phy_addr`: 5-bit address of the PHY 29 | * `mac_addr`: MAC address in standard XX:XX:XX:XX:XX:XX format 30 | 31 | Memory Ports: 32 | * `rx_port`: Read port into RX packet memory, 8 bytes by 2048 cells. 33 | * `tx_port`: Write port into TX packet memory, 8 bytes by 2048 cells. 34 | 35 | Pins: 36 | * `rmii`: signal group containing: 37 | txd0, txd1, txen, rxd0, rxd1, crs_dv, ref_clk 38 | * `mdio`: signal group containing: mdc, mdio 39 | * `phy_rst`: PHY RST pin (output, active low) 40 | * `eth_led`: Ethernet LED, active high, pulsed on packet traffic 41 | 42 | TX port: 43 | * `tx_start`: Pulse high to begin transmission of a packet from memory 44 | * `tx_len`: 11-bit length of packet to transmit 45 | * `tx_offset`: n-bit address offset of packet to transmit, with 46 | n=log2(tx_buf_size) 47 | 48 | RX port: 49 | * `rx_valid`: Held high while `rx_len` and `rx_offset` are valid 50 | * `rx_len`: 11-bit length of received packet 51 | * `rx_offset`: n-bit address offset of received packet, with 52 | n=log2(rx_buf_size) 53 | * `rx_ack`: Pulse high to acknowledge packet receipt 54 | 55 | Inputs: 56 | * `phy_reset`: Assert to reset the PHY, de-assert for normal operation 57 | 58 | Outputs: 59 | * `link_up`: High while link is established 60 | """ 61 | def __init__(self, clk_freq, phy_addr, mac_addr, rmii, mdio, 62 | phy_rst, eth_led, tx_buf_size=2048, rx_buf_size=2048): 63 | # Memory Ports 64 | self.rx_port = None # Assigned below 65 | self.tx_port = None # Assigned below 66 | 67 | # TX port 68 | self.tx_start = Signal() 69 | self.tx_len = Signal(11) 70 | self.tx_offset = Signal(max=tx_buf_size-1) 71 | 72 | # RX port 73 | self.rx_ack = Signal() 74 | self.rx_valid = Signal() 75 | self.rx_len = Signal(11) 76 | self.rx_offset = Signal(max=rx_buf_size-1) 77 | 78 | # Inputs 79 | self.phy_reset = Signal() 80 | 81 | # Outputs 82 | self.link_up = Signal() 83 | 84 | self.clk_freq = clk_freq 85 | self.phy_addr = phy_addr 86 | self.mac_addr = [int(x, 16) for x in mac_addr.split(":")] 87 | self.rmii = rmii 88 | self.mdio = mdio 89 | self.phy_rst = phy_rst 90 | self.eth_led = eth_led 91 | 92 | # Create packet memories and interface ports 93 | self.tx_mem = Memory(8, tx_buf_size) 94 | self.tx_port = self.tx_mem.write_port() 95 | self.rx_mem = Memory(8, rx_buf_size) 96 | self.rx_port = self.rx_mem.read_port(transparent=False) 97 | 98 | def elaborate(self, platform): 99 | m = Module() 100 | 101 | # Create RMII clock domain from RMII clock input 102 | cd = ClockDomain("rmii", reset_less=True) 103 | m.d.comb += cd.clk.eq(self.rmii.ref_clk) 104 | m.domains.rmii = cd 105 | 106 | # Create RX write and TX read ports for RMII use 107 | rx_port_w = self.rx_mem.write_port(domain="rmii") 108 | tx_port_r = self.tx_mem.read_port(domain="rmii", transparent=False) 109 | m.submodules += [self.rx_port, rx_port_w, self.tx_port, tx_port_r] 110 | m.d.comb += [self.rx_port.en.eq(1), tx_port_r.en.eq(1)] 111 | 112 | # Create submodules for PHY and RMII 113 | m.submodules.phy_manager = phy_manager = PHYManager( 114 | self.clk_freq, self.phy_addr, self.phy_rst, 115 | self.mdio.mdio, self.mdio.mdc) 116 | m.submodules.stretch = stretch = PulseStretch(int(1e6)) 117 | 118 | rmii_rx = RMIIRx( 119 | self.mac_addr, rx_port_w, self.rmii.crs_dv, 120 | self.rmii.rxd0, self.rmii.rxd1) 121 | rmii_tx = RMIITx( 122 | tx_port_r, self.rmii.txen, self.rmii.txd0, self.rmii.txd1) 123 | 124 | # Create FIFOs to interface to RMII modules 125 | rx_fifo = AsyncFIFO(width=11+self.rx_port.addr.nbits, depth=4) 126 | tx_fifo = AsyncFIFO(width=11+self.tx_port.addr.nbits, depth=4) 127 | 128 | m.d.comb += [ 129 | # RX FIFO 130 | rx_fifo.din.eq(Cat(rmii_rx.rx_offset, rmii_rx.rx_len)), 131 | rx_fifo.we.eq(rmii_rx.rx_valid), 132 | Cat(self.rx_offset, self.rx_len).eq(rx_fifo.dout), 133 | rx_fifo.re.eq(self.rx_ack), 134 | self.rx_valid.eq(rx_fifo.readable), 135 | 136 | # TX FIFO 137 | tx_fifo.din.eq(Cat(self.tx_offset, self.tx_len)), 138 | tx_fifo.we.eq(self.tx_start), 139 | Cat(rmii_tx.tx_offset, rmii_tx.tx_len).eq(tx_fifo.dout), 140 | tx_fifo.re.eq(rmii_tx.tx_ready), 141 | rmii_tx.tx_start.eq(tx_fifo.readable), 142 | 143 | # Other submodules 144 | phy_manager.phy_reset.eq(self.phy_reset), 145 | self.link_up.eq(phy_manager.link_up), 146 | stretch.trigger.eq(self.rx_valid), 147 | self.eth_led.eq(stretch.pulse), 148 | ] 149 | 150 | rdr = DomainRenamer({"read": "sync", "write": "rmii"}) 151 | wdr = DomainRenamer({"write": "sync", "read": "rmii"}) 152 | rr = DomainRenamer("rmii") 153 | m.submodules.rx_fifo = rdr(rx_fifo) 154 | m.submodules.tx_fifo = wdr(tx_fifo) 155 | m.submodules.rmii_rx = rr(rmii_rx) 156 | m.submodules.rmii_tx = rr(rmii_tx) 157 | 158 | return m 159 | 160 | 161 | class PHYManager(Elaboratable): 162 | """ 163 | Manage a PHY over MDIO. 164 | 165 | Can trigger a PHY reset. Resets PHY at power-up. 166 | 167 | Continually polls PHY for acceptable link status and outputs link status. 168 | 169 | Parameters: 170 | * `clk_freq`: Frequency of this module's clock, used to time the 1ms 171 | reset period and calculate the MDIO clock divider 172 | * `phy_addr`: 5-bit address of the PHY 173 | 174 | Pins: 175 | * `phy_rst`: PHY RST pin (output, active low) 176 | * `mdio`: MDIO pin (data in/out) 177 | * `mdc`: MDC pin (clock out) 178 | 179 | Inputs: 180 | * `phy_reset`: Pulse high to trigger a PHY reset 181 | 182 | Outputs: 183 | * `link_up`: High while link is established 184 | """ 185 | def __init__(self, clk_freq, phy_addr, phy_rst, mdio, mdc): 186 | # Inputs 187 | self.phy_reset = Signal() 188 | 189 | # Outputs 190 | self.link_up = Signal() 191 | 192 | self.clk_freq = clk_freq 193 | self.phy_addr = phy_addr 194 | self.phy_rst = phy_rst 195 | self.mdio = mdio 196 | self.mdc = mdc 197 | 198 | def elaborate(self, platform): 199 | m = Module() 200 | 201 | # Create MDIO submodule 202 | clk_div = int(self.clk_freq // 2.5e6) 203 | m.submodules.mdio = mdio = MDIO(clk_div, self.mdio, self.mdc) 204 | self.mdio_mod = mdio 205 | mdio.phy_addr = Const(self.phy_addr) 206 | 207 | # Latches for registers we read 208 | bsr = Signal(16) 209 | 210 | # Compute output signal from registers 211 | m.d.comb += self.link_up.eq( 212 | bsr[2] & # Link must be up 213 | ~bsr[4] & # No remote fault 214 | bsr[5] & # Autonegotiation complete 215 | bsr[14] # 100Mbps full duplex 216 | ) 217 | 218 | registers_to_write = [ 219 | # Enable 100Mbps, autonegotiation, and full-duplex 220 | # ("BCR", 0x00, (1 << 13) | (1 << 12) | (1 << 8)), 221 | ] 222 | 223 | registers_to_read = [ 224 | # Basic status register contains everything we need to know 225 | ("BSR", 0x01, bsr), 226 | ] 227 | 228 | # Controller FSM 229 | one_ms = int(self.clk_freq//1000) 230 | counter = Signal(max=one_ms) 231 | with m.FSM(): 232 | 233 | # Assert PHY_RST and begin 1ms counter 234 | with m.State("RESET"): 235 | m.d.comb += self.phy_rst.eq(0) 236 | m.d.sync += counter.eq(one_ms) 237 | m.next = "RESET_WAIT" 238 | 239 | # Wait for reset timeout 240 | with m.State("RESET_WAIT"): 241 | m.d.comb += self.phy_rst.eq(0) 242 | m.d.sync += counter.eq(counter - 1) 243 | with m.If(self.phy_reset): 244 | m.next = "RESET" 245 | with m.Elif(counter == 0): 246 | m.d.sync += counter.eq(one_ms) 247 | write = bool(registers_to_write) 248 | m.next = "WRITE_WAIT" if write else "POLL_WAIT" 249 | 250 | # Wait 1ms before writing 251 | if registers_to_write: 252 | with m.State("WRITE_WAIT"): 253 | m.d.comb += self.phy_rst.eq(1), 254 | m.d.sync += counter.eq(counter - 1) 255 | with m.If(self.phy_reset): 256 | m.next = "RESET" 257 | with m.Elif(counter == 0): 258 | m.next = f"WRITE_{registers_to_write[0][0]}" 259 | else: 260 | m.d.comb += mdio.write_data.eq(0) 261 | 262 | for idx, (name, addr, val) in enumerate(registers_to_write): 263 | if idx == len(registers_to_write) - 1: 264 | next_state = "POLL_WAIT" 265 | else: 266 | next_state = f"WRITE_{registers_to_write[idx+1][0]}" 267 | 268 | with m.State(f"WRITE_{name}"): 269 | m.d.comb += [ 270 | self.phy_rst.eq(0), 271 | mdio.reg_addr.eq(Const(addr)), 272 | mdio.rw.eq(1), 273 | mdio.write_data.eq(Const(val)), 274 | mdio.start.eq(1), 275 | ] 276 | 277 | with m.If(self.phy_reset): 278 | m.next = "RESET" 279 | with m.Elif(mdio.busy): 280 | m.next = f"WRITE_{name}_WAIT" 281 | 282 | with m.State(f"WRITE_{name}_WAIT"): 283 | m.d.comb += [ 284 | self.phy_rst.eq(1), 285 | mdio.reg_addr.eq(0), 286 | mdio.rw.eq(0), 287 | mdio.write_data.eq(0), 288 | mdio.start.eq(0), 289 | ] 290 | with m.If(self.phy_reset): 291 | m.next = "RESET" 292 | with m.Elif(~mdio.busy): 293 | m.d.sync += counter.eq(one_ms) 294 | m.next = next_state 295 | 296 | # Wait 1ms between polls 297 | with m.State("POLL_WAIT"): 298 | m.d.comb += self.phy_rst.eq(1) 299 | m.d.sync += counter.eq(counter - 1) 300 | with m.If(self.phy_reset): 301 | m.next = "RESET" 302 | with m.Elif(counter == 0): 303 | m.next = f"POLL_{registers_to_read[0][0]}" 304 | 305 | for idx, (name, addr, latch) in enumerate(registers_to_read): 306 | if idx == len(registers_to_read) - 1: 307 | next_state = "POLL_WAIT" 308 | else: 309 | next_state = f"POLL_{registers_to_read[idx+1][0]}" 310 | 311 | # Trigger a read of the register 312 | with m.State(f"POLL_{name}"): 313 | m.d.comb += [ 314 | self.phy_rst.eq(1), 315 | mdio.reg_addr.eq(Const(addr)), 316 | mdio.rw.eq(0), 317 | mdio.start.eq(1), 318 | ] 319 | 320 | with m.If(self.phy_reset): 321 | m.next = "RESET" 322 | with m.Elif(mdio.busy): 323 | m.next = f"POLL_{name}_WAIT" 324 | 325 | # Wait for MDIO to stop being busy 326 | with m.State(f"POLL_{name}_WAIT"): 327 | m.d.comb += [ 328 | self.phy_rst.eq(1), 329 | mdio.reg_addr.eq(0), 330 | mdio.rw.eq(0), 331 | mdio.start.eq(0), 332 | ] 333 | 334 | with m.If(self.phy_reset): 335 | m.next = "RESET" 336 | with m.Elif(~mdio.busy): 337 | m.d.sync += [ 338 | latch.eq(mdio.read_data), 339 | counter.eq(one_ms), 340 | ] 341 | m.next = next_state 342 | 343 | return m 344 | 345 | 346 | def test_phy_manager(): 347 | from nmigen.back import pysim 348 | from nmigen.lib.io import Pin 349 | 350 | mdc = Signal() 351 | mdio = Pin(1, 'io') 352 | phy_rst = Signal() 353 | 354 | # Specify a fake 10MHz clock frequency to reduce number of simulation steps 355 | phy_manager = PHYManager(10e6, 0, phy_rst, mdio, mdc) 356 | 357 | def testbench(): 358 | # 1ms is 10000 ticks, so check we're still asserting phy_rst 359 | for _ in range(10000): 360 | assert (yield phy_rst) == 0 361 | yield 362 | 363 | assert (yield phy_manager.link_up) == 0 364 | 365 | # Allow enough clocks to step the state machine through 366 | for _ in range(100): 367 | yield 368 | 369 | # Now we wait another 1ms for bring-up, without asserting reset 370 | for _ in range(9900): 371 | assert (yield phy_rst) == 1 372 | yield 373 | 374 | assert (yield phy_manager.link_up) == 0 375 | 376 | # Wait for the register read to synchronise to MDIO 377 | while True: 378 | if (yield phy_manager.mdio_mod.mdio.o) == 1: 379 | break 380 | yield 381 | 382 | # Clock through BSR register read, setting bits 14, 5, 2 383 | for clk in range(260): 384 | if clk in (194, 230, 242): 385 | yield (phy_manager.mdio_mod.mdio.i.eq(1)) 386 | else: 387 | yield (phy_manager.mdio_mod.mdio.i.eq(0)) 388 | yield 389 | 390 | # Finish register reads 391 | for _ in range(100): 392 | yield 393 | 394 | # Check link_up becomes 1 395 | assert (yield phy_manager.link_up) == 1 396 | 397 | vcdf = open("phy_manager.vcd", "w") 398 | with pysim.Simulator(phy_manager, vcd_file=vcdf) as sim: 399 | sim.add_clock(1e-6) 400 | sim.add_sync_process(testbench()) 401 | sim.run() 402 | -------------------------------------------------------------------------------- /gateware/daqnet/ethernet/mac_address_match.py: -------------------------------------------------------------------------------- 1 | """ 2 | MAC Address Matcher 3 | 4 | Copyright 2018-2019 Adam Greig 5 | Released under the MIT license; see LICENSE for details. 6 | """ 7 | 8 | import operator 9 | from functools import reduce 10 | 11 | from nmigen import Elaboratable, Module, Signal 12 | 13 | 14 | class MACAddressMatch(Elaboratable): 15 | """ 16 | MAC Address Matcher 17 | 18 | Parameters: 19 | * `mac_addr`: 6-byte MAC address (list of ints) 20 | 21 | Inputs: 22 | * `reset`: Restart address matching 23 | * `data`: 8-bit input data 24 | * `data_valid`: Pulsed high when new data is ready at `data`. 25 | 26 | Outputs: 27 | * `mac_match`: High if destination MAC address matches or is broadcast. 28 | Remains high until `reset` is asserted. 29 | """ 30 | def __init__(self, mac_addr): 31 | # Inputs 32 | self.reset = Signal() 33 | self.data = Signal(8) 34 | self.data_valid = Signal() 35 | 36 | # Outputs 37 | self.mac_match = Signal() 38 | 39 | # Parameters 40 | self.mac_addr = mac_addr 41 | 42 | def elaborate(self, platform): 43 | m = Module() 44 | mac = [Signal(8) for _ in range(6)] 45 | 46 | m.d.sync += self.mac_match.eq( 47 | reduce(operator.and_, 48 | [(mac[idx] == self.mac_addr[idx]) | (mac[idx] == 0xFF) 49 | for idx in range(6)])) 50 | 51 | with m.FSM(): 52 | with m.State("RESET"): 53 | m.d.sync += [mac[idx].eq(0) for idx in range(6)] 54 | with m.If(~self.reset): 55 | m.next = "BYTE0" 56 | 57 | for idx in range(6): 58 | next_state = f"BYTE{idx+1}" if idx < 5 else "DONE" 59 | 60 | with m.State(f"BYTE{idx}"): 61 | m.d.sync += mac[idx].eq(self.data) 62 | with m.If(self.reset): 63 | m.next = "RESET" 64 | with m.Elif(self.data_valid): 65 | m.next = next_state 66 | 67 | with m.State("DONE"): 68 | with m.If(self.reset): 69 | m.next = "RESET" 70 | 71 | return m 72 | 73 | 74 | def test_mac_address_match(): 75 | import random 76 | from nmigen.back import pysim 77 | 78 | mac_address = [random.randint(0, 255) for _ in range(6)] 79 | mac_address = [0x01, 0x23, 0x45, 0x67, 0x89, 0xAB] 80 | mac_matcher = MACAddressMatch(mac_address) 81 | 82 | data = mac_matcher.data 83 | data_valid = mac_matcher.data_valid 84 | reset = mac_matcher.reset 85 | 86 | def testbench(): 87 | yield (reset.eq(1)) 88 | for _ in range(10): 89 | yield 90 | yield (reset.eq(0)) 91 | yield 92 | 93 | # Check it matches its own MAC address 94 | for byte in mac_address: 95 | yield (data.eq(byte)) 96 | yield (data_valid.eq(1)) 97 | yield 98 | yield (data_valid.eq(0)) 99 | yield 100 | 101 | for idx in range(100): 102 | yield (data.eq(idx)) 103 | yield (data_valid.eq(1)) 104 | yield 105 | yield (data_valid.eq(0)) 106 | yield 107 | 108 | assert (yield mac_matcher.mac_match) == 1 109 | 110 | yield (reset.eq(1)) 111 | yield 112 | yield (reset.eq(0)) 113 | yield 114 | 115 | # Check it matches broadcast 116 | for byte in [0xFF]*6: 117 | yield (data.eq(byte)) 118 | yield (data_valid.eq(1)) 119 | yield 120 | yield (data_valid.eq(0)) 121 | yield 122 | 123 | for idx in range(100): 124 | yield (data.eq(idx)) 125 | yield (data_valid.eq(1)) 126 | yield 127 | yield (data_valid.eq(0)) 128 | yield 129 | 130 | assert (yield mac_matcher.mac_match) == 1 131 | 132 | yield (reset.eq(1)) 133 | yield 134 | yield (reset.eq(0)) 135 | yield 136 | 137 | # Check it doesn't match some other MAC address 138 | for byte in mac_address[::-1]: 139 | yield (data.eq(byte)) 140 | yield (data_valid.eq(1)) 141 | yield 142 | yield (data_valid.eq(0)) 143 | yield 144 | 145 | for idx in range(100): 146 | yield (data.eq(idx)) 147 | yield (data_valid.eq(1)) 148 | yield 149 | yield (data_valid.eq(0)) 150 | yield 151 | 152 | assert (yield mac_matcher.mac_match) == 0 153 | 154 | yield (reset.eq(1)) 155 | yield 156 | yield (reset.eq(0)) 157 | yield 158 | 159 | vcdf = open("mac_matcher.vcd", "w") 160 | with pysim.Simulator(mac_matcher, vcd_file=vcdf) as sim: 161 | sim.add_clock(1e-6) 162 | sim.add_sync_process(testbench()) 163 | sim.run() 164 | -------------------------------------------------------------------------------- /gateware/daqnet/ethernet/mdio.py: -------------------------------------------------------------------------------- 1 | """ 2 | MDIO Controller 3 | 4 | Copyright 2018-2019 Adam Greig 5 | Released under the MIT license; see LICENSE for details. 6 | """ 7 | 8 | from nmigen import Elaboratable, Module, Signal, Array 9 | 10 | 11 | class MDIO(Elaboratable): 12 | """ 13 | MDIO interface controller. 14 | 15 | Reads/writes MDIO registers on an attached PHY. 16 | 17 | Parameters: 18 | * `clk_div`: divider from controller clock to MDC (aim for ~2.5MHz) 19 | 20 | Pins: 21 | * `mdio`: MDIO pin (data in/out) 22 | * `mdc`: MDC pin (clock out) 23 | 24 | Inputs: 25 | * `phy_addr`: 5-bit PHY address 26 | * `reg_addr`: 5-bit register address to read/write to 27 | * `rw`: select read (0) or write (1) operation 28 | * `write_data`: 16-bit data to write 29 | * `start`: operation begins on rising edge of `start` 30 | 31 | Outputs: 32 | * `read_data`: 16-bit data read from register, valid once busy is 0 33 | * `busy`: 1 if controller is busy, 0 if ready to take requests 34 | """ 35 | def __init__(self, clk_div, mdio, mdc): 36 | # Inputs 37 | self.phy_addr = Signal(5) 38 | self.reg_addr = Signal(5) 39 | self.rw = Signal() 40 | self.write_data = Signal(16) 41 | self.start = Signal() 42 | 43 | # Outputs 44 | self.read_data = Signal(16) 45 | self.busy = Signal() 46 | 47 | # Parameters 48 | self.clk_div = clk_div 49 | 50 | # Pins 51 | self.mdio = mdio 52 | self.mdc = mdc 53 | 54 | def elaborate(self, platform): 55 | 56 | m = Module() 57 | 58 | # Create divided clock for MDC 59 | mdc_int = Signal() 60 | mdc_rise = Signal() 61 | mdc_fall = Signal() 62 | mdc_divider = Signal(max=self.clk_div) 63 | with m.If(mdc_divider == 0): 64 | m.d.sync += [ 65 | mdc_divider.eq(self.clk_div - 1), 66 | mdc_int.eq(0), 67 | mdc_fall.eq(1), 68 | mdc_rise.eq(0), 69 | ] 70 | 71 | with m.Elif(mdc_divider == self.clk_div//2): 72 | m.d.sync += [ 73 | mdc_divider.eq(mdc_divider - 1), 74 | mdc_int.eq(1), 75 | mdc_fall.eq(0), 76 | mdc_rise.eq(1), 77 | ] 78 | 79 | with m.Else(): 80 | m.d.sync += [ 81 | mdc_divider.eq(mdc_divider - 1), 82 | mdc_fall.eq(0), 83 | mdc_rise.eq(0), 84 | ] 85 | 86 | # Latches for inputs 87 | _phy_addr = Signal.like(self.phy_addr) 88 | _reg_addr = Signal.like(self.reg_addr) 89 | _rw = Signal.like(self.rw) 90 | _write_data = Signal.like(self.write_data) 91 | 92 | # MDIO FSM 93 | bit_counter = Signal(6) 94 | with m.FSM() as fsm: 95 | m.d.comb += self.busy.eq(~fsm.ongoing("IDLE")) 96 | 97 | # Idle state 98 | # Constantly register input data and wait for START signal 99 | with m.State("IDLE"): 100 | m.d.comb += [ 101 | self.mdc.eq(0), 102 | self.mdio.oe.eq(0), 103 | ] 104 | 105 | # Latch input signals while in idle 106 | m.d.sync += [ 107 | _phy_addr.eq(self.phy_addr), 108 | _reg_addr.eq(self.reg_addr), 109 | _rw.eq(self.rw), 110 | _write_data.eq(self.write_data), 111 | ] 112 | 113 | with m.If(self.start): 114 | m.next = "SYNC" 115 | 116 | # Synchronise to MDC. Enter this state at any time. 117 | # Will transition to PRE_32 immediately after the next 118 | # falling edge on MDC. 119 | with m.State("SYNC"): 120 | m.d.comb += [ 121 | self.mdc.eq(0), 122 | self.mdio.oe.eq(0), 123 | ] 124 | 125 | with m.If(mdc_fall): 126 | m.d.sync += bit_counter.eq(32) 127 | m.next = "PRE_32" 128 | 129 | # PRE_32 130 | # Preamble field: 32 bits of 1 131 | with m.State("PRE_32"): 132 | m.d.comb += [ 133 | self.mdc.eq(mdc_int), 134 | self.mdio.oe.eq(1), 135 | 136 | # Output all 1s 137 | self.mdio.o.eq(1), 138 | ] 139 | 140 | # Count falling edges of MDC, 141 | # transition to ST after 32 MDC clocks 142 | with m.If(mdc_fall): 143 | with m.If(bit_counter == 1): 144 | m.d.sync += bit_counter.eq(2) 145 | m.next = "ST" 146 | with m.Else(): 147 | m.d.sync += bit_counter.eq(bit_counter - 1) 148 | 149 | # ST 150 | # Start field: always 01 151 | with m.State("ST"): 152 | m.d.comb += [ 153 | self.mdc.eq(mdc_int), 154 | self.mdio.oe.eq(1), 155 | self.mdio.o.eq(bit_counter[0]), 156 | ] 157 | 158 | with m.If(mdc_fall): 159 | with m.If(bit_counter == 1): 160 | m.d.sync += bit_counter.eq(2) 161 | m.next = "OP" 162 | with m.Else(): 163 | m.d.sync += bit_counter.eq(bit_counter - 1) 164 | 165 | # OP 166 | # Opcode field: read=10, write=01 167 | with m.State("OP"): 168 | m.d.comb += [ 169 | self.mdc.eq(mdc_int), 170 | self.mdio.oe.eq(1), 171 | ] 172 | with m.If(_rw): 173 | m.d.comb += self.mdio.o.eq(bit_counter[0]) 174 | with m.Else(): 175 | m.d.comb += self.mdio.o.eq(~bit_counter[0]) 176 | 177 | with m.If(mdc_fall): 178 | with m.If(bit_counter == 1): 179 | m.d.sync += bit_counter.eq(5) 180 | m.next = "PA5" 181 | with m.Else(): 182 | m.d.sync += bit_counter.eq(bit_counter - 1) 183 | 184 | # PA5 185 | # PHY address field, 5 bits 186 | with m.State("PA5"): 187 | m.d.comb += [ 188 | self.mdc.eq(mdc_int), 189 | self.mdio.oe.eq(1), 190 | self.mdio.o.eq(Array(_phy_addr)[bit_counter - 1]), 191 | ] 192 | 193 | with m.If(mdc_fall): 194 | with m.If(bit_counter == 1): 195 | m.d.sync += bit_counter.eq(5) 196 | m.next = "RA5" 197 | with m.Else(): 198 | m.d.sync += bit_counter.eq(bit_counter - 1) 199 | 200 | # RA5 201 | # Register address field, 5 bits 202 | with m.State("RA5"): 203 | m.d.comb += [ 204 | self.mdc.eq(mdc_int), 205 | self.mdio.oe.eq(1), 206 | self.mdio.o.eq(Array(_reg_addr)[bit_counter - 1]), 207 | ] 208 | 209 | with m.If(mdc_fall): 210 | with m.If(bit_counter == 1): 211 | with m.If(_rw): 212 | m.d.sync += bit_counter.eq(2) 213 | m.next = "TA_W" 214 | with m.Else(): 215 | m.d.sync += bit_counter.eq(1) 216 | m.next = "TA_R" 217 | with m.Else(): 218 | m.d.sync += bit_counter.eq(bit_counter - 1) 219 | 220 | # TA 221 | # Turnaround, 1 bits, OE released for read operations 222 | with m.State("TA_R"): 223 | m.d.comb += [ 224 | self.mdc.eq(mdc_int), 225 | self.mdio.oe.eq(0), 226 | ] 227 | 228 | with m.If(mdc_fall): 229 | with m.If(bit_counter == 1): 230 | m.d.sync += bit_counter.eq(16) 231 | m.next = "D16_R" 232 | with m.Else(): 233 | m.d.sync += bit_counter.eq(bit_counter - 1) 234 | 235 | # TA 236 | # Turnaround, 2 bits, driven to 10 for write operations 237 | with m.State("TA_W"): 238 | m.d.comb += [ 239 | self.mdc.eq(mdc_int), 240 | self.mdio.oe.eq(1), 241 | self.mdio.o.eq(~bit_counter[0]), 242 | ] 243 | 244 | with m.If(mdc_fall): 245 | with m.If(bit_counter == 1): 246 | m.d.sync += bit_counter.eq(16) 247 | m.next = "D16_W" 248 | with m.Else(): 249 | m.d.sync += bit_counter.eq(bit_counter - 1) 250 | 251 | # D16 252 | # Data field, read operation 253 | with m.State("D16_R"): 254 | m.d.comb += [ 255 | self.mdc.eq(mdc_int), 256 | self.mdio.oe.eq(0), 257 | ] 258 | 259 | with m.If(mdc_fall): 260 | bit = Array(self.read_data)[bit_counter - 1] 261 | m.d.sync += bit.eq(self.mdio.i) 262 | with m.If(bit_counter == 1): 263 | m.next = "READ_LAST_CLOCK" 264 | with m.Else(): 265 | m.d.sync += bit_counter.eq(bit_counter - 1) 266 | 267 | # Because we sample MDIO on the falling edge, the final clock 268 | # pulse is not used for data, but should probably be emitted to 269 | # stop things getting confused. 270 | with m.State("READ_LAST_CLOCK"): 271 | m.d.comb += [ 272 | self.mdc.eq(mdc_int), 273 | self.mdio.oe.eq(0), 274 | ] 275 | 276 | with m.If(mdc_fall): 277 | m.next = "IDLE" 278 | 279 | # D16 280 | # Data field, write operation 281 | with m.State("D16_W"): 282 | m.d.comb += [ 283 | self.mdc.eq(mdc_int), 284 | self.mdio.oe.eq(1), 285 | self.mdio.o.eq(Array(_write_data)[bit_counter - 1]), 286 | ] 287 | 288 | with m.If(mdc_fall): 289 | with m.If(bit_counter == 0): 290 | m.next = "IDLE" 291 | with m.Else(): 292 | m.d.sync += bit_counter.eq(bit_counter - 1) 293 | 294 | return m 295 | 296 | 297 | def test_mdio_read(): 298 | import random 299 | from nmigen.lib.io import Pin 300 | from nmigen.back import pysim 301 | 302 | mdc = Signal() 303 | mdio_pin = Pin(1, 'io') 304 | mdio = MDIO(20, mdio_pin, mdc) 305 | 306 | def testbench(): 307 | rng = random.Random(0) 308 | 309 | # Run ten random reads in sequence 310 | for testrun in range(10): 311 | phy_addr = rng.randint(0, 31) 312 | reg_addr = rng.randint(0, 31) 313 | reg_value = rng.randint(0, 65535) 314 | 315 | # Idle clocks at start 316 | for _ in range(10): 317 | yield 318 | 319 | # Set up a register read 320 | yield (mdio.phy_addr.eq(phy_addr)) 321 | yield (mdio.reg_addr.eq(reg_addr)) 322 | yield (mdio.rw.eq(0)) 323 | yield (mdio.start.eq(1)) 324 | yield 325 | yield (mdio.phy_addr.eq(0)) 326 | yield (mdio.reg_addr.eq(0)) 327 | yield (mdio.start.eq(0)) 328 | 329 | # Clock through the read 330 | ibits = [int(x) for x in f"{reg_value:016b}"] 331 | obits = [] 332 | oebits = [] 333 | mdio_clk = 0 334 | last_mdc = (yield mdc) 335 | while True: 336 | yield 337 | new_mdc = (yield mdc) 338 | # Detect rising edge 339 | if new_mdc and last_mdc == 0: 340 | mdio_clk += 1 341 | obits.append((yield mdio.mdio.o)) 342 | oebits.append((yield mdio.mdio.oe)) 343 | if mdio_clk >= 48: 344 | yield (mdio.mdio.i.eq(ibits[mdio_clk - 48])) 345 | if mdio_clk == 63: 346 | break 347 | last_mdc = new_mdc 348 | 349 | for _ in range(100): 350 | yield 351 | 352 | read_data = (yield mdio.read_data) 353 | was_busy = (yield mdio.busy) 354 | 355 | # Check transmitted bits were correct 356 | pre_32 = [1]*32 357 | st = [0, 1] 358 | op = [1, 0] 359 | pa5 = [int(x) for x in f"{phy_addr:05b}"] 360 | ra5 = [int(x) for x in f"{reg_addr:05b}"] 361 | expected = pre_32 + st + op + pa5 + ra5 362 | assert obits[:46] == expected 363 | 364 | # Check OE transitioned correctly 365 | expected = [1]*46 + [0]*17 366 | assert oebits == expected 367 | 368 | # Check we read the correct value in the end 369 | expected = int("".join(str(x) for x in ibits), 2) 370 | assert read_data == expected 371 | assert not was_busy 372 | 373 | vcdf = open("mdio_read.vcd", "w") 374 | with pysim.Simulator(mdio, vcd_file=vcdf) as sim: 375 | sim.add_clock(1e-6) 376 | sim.add_sync_process(testbench()) 377 | sim.run() 378 | 379 | 380 | def test_mdio_write(): 381 | import random 382 | from nmigen.lib.io import Pin 383 | from nmigen.back import pysim 384 | 385 | mdc = Signal() 386 | mdio_pin = Pin(1, 'io') 387 | mdio = MDIO(20, mdio_pin, mdc) 388 | 389 | def testbench(): 390 | rng = random.Random(0) 391 | 392 | # Run ten random writes in sequence 393 | for testrun in range(10): 394 | phy_addr = rng.randint(0, 31) 395 | reg_addr = rng.randint(0, 31) 396 | reg_value = rng.randint(0, 65535) 397 | 398 | # Idle clocks at start 399 | for _ in range(10): 400 | yield 401 | 402 | # Set up a register write 403 | yield (mdio.phy_addr.eq(phy_addr)) 404 | yield (mdio.reg_addr.eq(reg_addr)) 405 | yield (mdio.write_data.eq(reg_value)) 406 | yield (mdio.rw.eq(1)) 407 | yield (mdio.start.eq(1)) 408 | yield 409 | yield (mdio.phy_addr.eq(0)) 410 | yield (mdio.write_data.eq(0)) 411 | yield (mdio.rw.eq(0)) 412 | yield (mdio.reg_addr.eq(0)) 413 | yield (mdio.start.eq(0)) 414 | 415 | # Clock through the write 416 | obits = [] 417 | oebits = [] 418 | mdio_clk = 0 419 | last_mdc = (yield mdc) 420 | while True: 421 | yield 422 | new_mdc = (yield mdc) 423 | # Detect rising edge 424 | if new_mdc and last_mdc == 0: 425 | mdio_clk += 1 426 | obits.append((yield mdio.mdio.o)) 427 | oebits.append((yield mdio.mdio.oe)) 428 | if mdio_clk == 64: 429 | break 430 | last_mdc = new_mdc 431 | 432 | # Idle at end 433 | for _ in range(100): 434 | yield 435 | 436 | was_busy = (yield mdio.busy) 437 | 438 | # Check transmitted bits were correct 439 | pre_32 = [1]*32 440 | st = [0, 1] 441 | op = [0, 1] 442 | pa5 = [int(x) for x in f"{phy_addr:05b}"] 443 | ra5 = [int(x) for x in f"{reg_addr:05b}"] 444 | ta = [1, 0] 445 | d16 = [int(x) for x in f"{reg_value:016b}"] 446 | expected = pre_32 + st + op + pa5 + ra5 + ta + d16 447 | assert obits == expected 448 | 449 | # Check OE transitioned correctly 450 | expected = [1]*64 451 | assert oebits == expected 452 | assert not was_busy 453 | 454 | vcdf = open("mdio_write.vcd", "w") 455 | with pysim.Simulator(mdio, vcd_file=vcdf) as sim: 456 | sim.add_clock(1e-6) 457 | sim.add_sync_process(testbench()) 458 | sim.run() 459 | -------------------------------------------------------------------------------- /gateware/daqnet/platform.py: -------------------------------------------------------------------------------- 1 | """ 2 | iCE40HX Platform 3 | 4 | Platform support and instance wrappers for iCE40 FPGAs. 5 | 6 | Copyright 2019 Adam Greig 7 | Released under the MIT license; see LICENSE for details. 8 | """ 9 | 10 | from nmigen import Fragment, Elaboratable, Signal, Instance, Const, Module 11 | from nmigen.vendor.lattice_ice40 import LatticeICE40Platform 12 | from nmigen.build import Resource, Pins, Clock, Subsignal 13 | 14 | 15 | class _InstanceWrapper(Elaboratable): 16 | """ 17 | Wraps an Instance, taking parameters in the constructor and then 18 | exposing all ports as attributes. Unused ports are not specified 19 | in the eventual Instance. 20 | 21 | itype: the type of the instance to create 22 | params: a dictionary of parameter names to values 23 | ports: a dictionary of port names to (dirn, shape) tuples 24 | required_ports: a list of required port names 25 | defaults: a dictionary of port names to default values if unused 26 | """ 27 | def __init__(self, itype, params, ports, required_ports, defaults=None): 28 | super().__setattr__('ports_used', {}) 29 | super().__setattr__('ports', ports) 30 | self.itype = itype 31 | self.params = params 32 | self.required_ports = required_ports 33 | self.defaults = defaults 34 | 35 | def __getattr__(self, name): 36 | if name in self.__dict__['ports_used']: 37 | return self.__dict__['ports_used'][name] 38 | elif name.upper() in self.__dict__['ports']: 39 | _, shape = self.__dict__['ports'][name.upper()] 40 | self.__dict__['ports_used'][name] = Signal(shape=shape, name=name) 41 | return self.__dict__['ports_used'][name] 42 | else: 43 | raise AttributeError 44 | 45 | def __setattr__(self, name, value): 46 | if 'ports' in self.__dict__ and name.upper() in self.__dict__['ports']: 47 | self.__dict__['ports_used'][name] = value 48 | else: 49 | super().__setattr__(name, value) 50 | 51 | def elaborate(self, platform): 52 | args = {f"p_{key.upper()}": val for (key, val) in self.params.items()} 53 | for port, (dirn, shape) in self.ports.items(): 54 | if port.lower() in self.ports_used: 55 | args[f"{dirn}_{port}"] = self.ports_used[port.lower()] 56 | elif self.defaults and port in self.defaults: 57 | args[f"{dirn}_{port}"] = self.defaults[port] 58 | elif port in self.required_ports: 59 | raise ValueError(f"{self.itype}: Required port {port} missing") 60 | 61 | return Instance(self.itype, **args) 62 | 63 | 64 | class SB_IO(_InstanceWrapper): 65 | """ 66 | I/O Primitive SB_IO. 67 | 68 | Parameters: 69 | * in_pin_type: one of: 70 | SB_IO.PIN_INPUT (default), 71 | SB_IO.PIN_INPUT_LATCH 72 | SB_IO.PIN_INPUT_REGISTERED 73 | SB_IO.PIN_INPUT_REGISTERED_LATCH 74 | SB_IO.PIN_INPUT_DDR 75 | * out_pin_type: one of: 76 | SB_IO.PIN_NO_OUTPUT (default) 77 | SB_IO.PIN_OUTPUT 78 | SB_IO.PIN_OUTPUT_TRISTATE 79 | SB_IO.PIN_OUTPUT_ENABLE_REGISTERED 80 | SB_IO.PIN_OUTPUT_REGISTERED 81 | SB_IO.PIN_OUTPUT_REGISTERED_ENABLE 82 | SB_IO.PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED 83 | SB_IO.PIN_OUTPUT_DDR 84 | SB_IO.PIN_OUTPUT_DDR_ENABLE 85 | SB_IO.PIN_OUTPUT_DDR_ENABLE_REGISTERED 86 | SB_IO.PIN_OUTPUT_REGISTERED_INVERTED 87 | SB_IO.PIN_OUTPUT_REGISTERED_ENABLE_INVERTED 88 | SB_IO.PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED_INVERTED 89 | * pullup: boolean whether to enable internal pullup. 90 | * neg_trigger: boolean whether to invert polarity of IO FFs 91 | * io_standard: one of "SB_LVCMOS" or "SB_LVDS_INPUT" 92 | 93 | Ports: 94 | Ports must be used or accessed as attributes, e.g.: 95 | io1 = SB_IO(out_pin_type=SB_IO.PIN_OUTPUT) 96 | io1.package_pin = user_led1 97 | io2 = SB_IO() 98 | io2.package_pin = user_sw1 99 | m.d.comb += io1.d_out_0.eq(io2.d_in_0) 100 | Unused ports will not be added to the instantiated Instance. 101 | 102 | * package_pin: required, connect to top-level pin 103 | * latch_input_value: when high, maintain current input value 104 | * clock_enable: clock enable common to input and output clock 105 | * input_clock: clock for input FFs 106 | * output_clock: clock for output FFs 107 | * output_enable: when high, enable output, otherwise high impedance 108 | * d_out_0: Output data, or in DDR mode, data for rising output_clock 109 | * d_out_1: In DDR mode, data for falling output_clock edge 110 | * d_in_0: Input data, or in DDR mode, data at rising input_clock edge 111 | * d_in_1: In DDR mode, data at falling input_clock edge 112 | """ 113 | 114 | PIN_INPUT = 0b01 115 | PIN_INPUT_LATCH = 0b11 116 | PIN_INPUT_REGISTERED = 0b00 117 | PIN_INPUT_REGISTERED_LATCH = 0b10 118 | PIN_INPUT_DDR = 0b00 119 | 120 | PIN_NO_OUTPUT = 0b0000 121 | PIN_OUTPUT = 0b0110 122 | PIN_OUTPUT_TRISTATE = 0b1010 123 | PIN_OUTPUT_ENABLE_REGISTERED = 0b1110 124 | PIN_OUTPUT_REGISTERED = 0b0101 125 | PIN_OUTPUT_REGISTERED_ENABLE = 0b1001 126 | PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED = 0b1101 127 | PIN_OUTPUT_DDR = 0b0100 128 | PIN_OUTPUT_DDR_ENABLE = 0b1000 129 | PIN_OUTPUT_DDR_ENABLE_REGISTERED = 0b1100 130 | PIN_OUTPUT_REGISTERED_INVERTED = 0b0111 131 | PIN_OUTPUT_REGISTERED_ENABLE_INVERTED = 0b1011 132 | PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED_INVERTED = 0b1111 133 | 134 | def __init__(self, 135 | in_pin_type=PIN_INPUT, 136 | out_pin_type=PIN_NO_OUTPUT, 137 | pullup=False, neg_trigger=False, 138 | io_standard="SB_LVCMOS"): 139 | params = { 140 | "pin_type": in_pin_type | (out_pin_type << 2), 141 | "pullup": int(pullup), 142 | "neg_trigger": int(neg_trigger), 143 | "io_standard": io_standard, 144 | } 145 | 146 | ports = { 147 | "PACKAGE_PIN": ("io", 1), 148 | "LATCH_INPUT_VALUE": ("i", 1), 149 | "CLOCK_ENABLE": ("i", 1), 150 | "INPUT_CLK": ("i", 1), 151 | "OUTPUT_CLK": ("i", 1), 152 | "OUTPUT_ENABLE": ("i", 1), 153 | "D_OUT_0": ("i", 1), 154 | "D_OUT_1": ("i", 1), 155 | "D_IN_0": ("o", 1), 156 | "D_IN_1": ("o", 1), 157 | } 158 | 159 | required = ("PACKAGE_PIN",) 160 | super().__init__("SB_IO", params, ports, required) 161 | 162 | def change_pin_type(self, in_pin_type, out_pin_type): 163 | self.params["pin_type"] = in_pin_type | (out_pin_type << 2) 164 | 165 | 166 | class SB_PLL40_PAD(_InstanceWrapper): 167 | """ 168 | Phase-locked loop primitive SB_PLL40_PAD. 169 | 170 | Used when the PLL source is an input pad in banks 0 or 2, and the source 171 | clock is not required inside the FPGA. 172 | 173 | Required Parameters: 174 | * divr: Reference clock divider, 0 to 15 175 | * divf: Feedback divider, 0 to 63 176 | * divq: VCO divider, 1 to 6 177 | * filter_range: PLL filter setting, 0 to 7 178 | 179 | Optional Parameters: 180 | See SB_PLL40_PAD documentation. Parameters may be given as additional 181 | kwargs when initialising SB_PLL40_PAD, e.g.: 182 | pll = SB_PLL40_PAD(0, 31, 3, 2, feedback_path="DELAY", fda_feedback=10) 183 | 184 | If unspecified, FEEDBACK_PATH is set to SIMPLE and PLLOUT_SELECT 185 | to GENCLK. 186 | 187 | Ports: 188 | Ports must be set or accessed as attributes to be used, e.g.: 189 | pll = SB_PLL40_PAD(0, 31, 3, 2) 190 | pll.packagepin = clk25 191 | m.d.comb += cd.clk.eq(pll.plloutglobal) 192 | Unused ports will not be added to the instantiated Instance. 193 | 194 | See SB_PLL40_PAD documentation for the full list of ports. 195 | 196 | Required ports: 197 | * packagepin: Connect directly to input pad 198 | 199 | Commonly used ports: 200 | * plloutglobal: Global buffer clock out 201 | * plloutcore: Core logic clock out 202 | 203 | If unspecified, RESETB is set to 1. 204 | """ 205 | def __init__(self, divr, divf, divq, filter_range, **params): 206 | params["divr"] = divr 207 | params["divf"] = divf 208 | params["divq"] = divq 209 | params["filter_range"] = filter_range 210 | 211 | if "feedback_path" not in params: 212 | params["feedback_path"] = "SIMPLE" 213 | if "pllout_select" not in params: 214 | params["pllout_select"] = "GENCLK" 215 | 216 | ports = { 217 | "PACKAGEPIN": ("i", 1), 218 | "EXTFEEDBACK": ("i", 1), 219 | "DYNAMICDELAY": ("i", 1), 220 | "LATCHINPUTVALUE": ("i", 1), 221 | "SCLK": ("i", 1), 222 | "SDI": ("i", 1), 223 | "SDO": ("o", 1), 224 | "RESETB": ("i", 1), 225 | "LOCK": ("o", 1), 226 | "PLLOUTCORE": ("o", 1), 227 | "PLLOUTGLOBAL": ("o", 1), 228 | } 229 | 230 | required = ("PACKAGEPIN",) 231 | default = {"RESETB": Const(1)} 232 | super().__init__("SB_PLL40_PAD", params, ports, required, default) 233 | 234 | 235 | class SensorPlatform(LatticeICE40Platform): 236 | device = "iCE40HX8K" 237 | package = "BG121" 238 | resources = [ 239 | Resource("clk25", 0, Pins("B6", dir="i"), Clock(25e6)), 240 | Resource("user_led", 0, Pins("A10", dir="o")), 241 | Resource("user_led", 1, Pins("A11", dir="o")), 242 | Resource("user_sw", 0, Pins("L1", dir="i")), 243 | Resource("user_sw", 1, Pins("L7", dir="i")), 244 | Resource( 245 | "adc", 0, 246 | Subsignal("cs", Pins("L2", dir="o")), 247 | Subsignal("dout", Pins("L3", dir="o")), 248 | Subsignal("sclk", Pins("L4", dir="o")), 249 | ), 250 | Resource( 251 | "daqnet", 0, 252 | Subsignal("led1", Pins("A3", dir="o")), 253 | Subsignal("led2", Pins("A4", dir="o")), 254 | Subsignal("txp", Pins("C2", dir="o")), 255 | Subsignal("txn", Pins("C1", dir="o")), 256 | Subsignal("rx", Pins("B2", dir="i")), 257 | ), 258 | ] 259 | connectors = [] 260 | 261 | 262 | class SwitchPlatform(LatticeICE40Platform): 263 | device = "iCE40HX8K" 264 | package = "BG121" 265 | resources = [ 266 | Resource("clk25", 0, Pins("B6", dir="i")), 267 | Resource("user_led", 0, Pins("A11", dir="o")), 268 | Resource("user_led", 1, Pins("A10", dir="o")), 269 | Resource( 270 | "uart", 0, 271 | Subsignal("rx", Pins("A4", dir="i")), 272 | Subsignal("tx", Pins("A3", dir="o")), 273 | ), 274 | Resource( 275 | "flash", 0, 276 | Subsignal("sdi", Pins("K9", dir="o")), 277 | Subsignal("sdo", Pins("J9", dir="i")), 278 | Subsignal("sck", Pins("L10", dir="o")), 279 | Subsignal("cs", Pins("K10", dir="o")), 280 | Subsignal("io2", Pins("K11", dir="i")), 281 | Subsignal("io3", Pins("J11", dir="i")), 282 | ), 283 | Resource( 284 | "rmii", 0, 285 | Subsignal("txd0", Pins("J3", dir="o")), 286 | Subsignal("txd1", Pins("L1", dir="o")), 287 | Subsignal("txen", Pins("L2", dir="o")), 288 | Subsignal("rxd0", Pins("K5", dir="i")), 289 | Subsignal("rxd1", Pins("J5", dir="i")), 290 | Subsignal("crs_dv", Pins("L4", dir="i")), 291 | Subsignal("ref_clk", Pins("K4", dir="i")), 292 | ), 293 | Resource( 294 | "mdio", 0, 295 | Subsignal("mdc", Pins("K3", dir="o")), 296 | Subsignal("mdio", Pins("L3", dir="io")), 297 | ), 298 | Resource( 299 | "phy", 0, 300 | Subsignal("rst", Pins("K2", dir="o")), 301 | Subsignal("led", Pins("J2", dir="o")), 302 | ), 303 | Resource( 304 | "daqnet", 0, 305 | Subsignal("led1", Pins("C4", dir="o")), 306 | Subsignal("led2", Pins("D3", dir="o")), 307 | Subsignal("txp", Pins("B1", dir="o")), 308 | Subsignal("txn", Pins("B2", dir="o")), 309 | Subsignal("rx", Pins("C1", dir="i")), 310 | ), 311 | Resource( 312 | "daqnet", 1, 313 | Subsignal("led1", Pins("D2", dir="o")), 314 | Subsignal("led2", Pins("C3", dir="o")), 315 | Subsignal("txp", Pins("E1", dir="o")), 316 | Subsignal("txn", Pins("D1", dir="o")), 317 | Subsignal("rx", Pins("E3", dir="i")), 318 | ), 319 | Resource( 320 | "daqnet", 2, 321 | Subsignal("led1", Pins("G3", dir="o")), 322 | Subsignal("led2", Pins("F3", dir="o")), 323 | Subsignal("txp", Pins("F1", dir="o")), 324 | Subsignal("txn", Pins("F2", dir="o")), 325 | Subsignal("rx", Pins("G2", dir="i")), 326 | ), 327 | Resource( 328 | "daqnet", 3, 329 | Subsignal("led1", Pins("F4", dir="o")), 330 | Subsignal("led2", Pins("H3", dir="o")), 331 | Subsignal("txp", Pins("H1", dir="o")), 332 | Subsignal("txn", Pins("H2", dir="o")), 333 | Subsignal("rx", Pins("K1", dir="i")), 334 | ), 335 | ] 336 | connectors = [] 337 | -------------------------------------------------------------------------------- /gateware/daqnet/top.py: -------------------------------------------------------------------------------- 1 | """ 2 | Copyright 2018-2019 Adam Greig 3 | Released under the MIT license; see LICENSE for details. 4 | """ 5 | 6 | from nmigen import Elaboratable, Signal, Module, ClockDomain 7 | from .platform import SB_PLL40_PAD 8 | 9 | from .ethernet.mac import MAC 10 | from .ethernet.ip import IPStack 11 | from .user import User 12 | 13 | 14 | class LEDBlinker(Elaboratable): 15 | def __init__(self, nbits): 16 | self.led = Signal() 17 | self.nbits = nbits 18 | 19 | def elaborate(self, platform): 20 | m = Module() 21 | divider = Signal(self.nbits) 22 | m.d.sync += divider.eq(divider + 1) 23 | m.d.comb += self.led.eq(divider[-1]) 24 | return m 25 | 26 | 27 | class Top(Elaboratable): 28 | def __init__(self, platform, args): 29 | pass 30 | 31 | def elaborate(self, platform): 32 | raise NotImplementedError 33 | 34 | 35 | class SensorTop(Top): 36 | def elaborate(self, platform): 37 | m = Module() 38 | 39 | # Set up PLL 40 | m.submodules.pll = pll = SB_PLL40_PAD(0, 31, 3, 2) 41 | pll.packagepin = platform.request("clk25") 42 | pll.plloutglobal = Signal() 43 | 44 | # Set up clock domain on PLL output 45 | cd = ClockDomain("sync", reset_less=True) 46 | m.d.comb += cd.clk.eq(pll.plloutglobal) 47 | m.domains += cd 48 | 49 | # Create LED blinker in PLL clock domain 50 | blinker = LEDBlinker(24) 51 | m.submodules.led_blinker = blinker 52 | m.d.comb += platform.request("user_led").eq(blinker.led) 53 | 54 | return m 55 | 56 | 57 | class SwitchTop(Top): 58 | def elaborate(self, platform): 59 | m = Module() 60 | 61 | # Set up PLL to multiply 25MHz clock to 100MHz clock 62 | m.submodules.pll = pll = SB_PLL40_PAD(0, 31, 3, 2) 63 | pll.packagepin = platform.request("clk25") 64 | pll.plloutglobal = Signal() 65 | 66 | # Set up clock domain on output of PLL 67 | cd = ClockDomain("sync", reset_less=True) 68 | m.d.comb += cd.clk.eq(pll.plloutglobal) 69 | m.domains += cd 70 | 71 | # Ethernet MAC 72 | phy = platform.request("phy") 73 | rmii = platform.request("rmii") 74 | mdio = platform.request("mdio") 75 | mac_addr = "02:44:4E:30:76:9E" 76 | mac = MAC(100e6, 0, mac_addr, rmii, mdio, phy.rst, phy.led) 77 | m.submodules.mac = mac 78 | 79 | # Explicitly zero unused inputs in MAC 80 | m.d.comb += [ 81 | mac.phy_reset.eq(0), 82 | ] 83 | 84 | # User data stuff 85 | user = User() 86 | m.submodules.user = user 87 | 88 | # IP stack 89 | ip4_addr = "10.1.1.5" 90 | m.submodules.ipstack = ipstack = IPStack( 91 | mac_addr, ip4_addr, 16, 1735, mac.rx_port, mac.tx_port, 92 | user.mem_r_port, user.mem_w_port) 93 | m.d.comb += [ 94 | mac.tx_start.eq(ipstack.tx_start), 95 | mac.tx_len.eq(ipstack.tx_len), 96 | mac.tx_offset.eq(ipstack.tx_offset), 97 | ipstack.rx_valid.eq(mac.rx_valid), 98 | ipstack.rx_len.eq(mac.rx_len), 99 | ipstack.rx_offset.eq(mac.rx_offset), 100 | mac.rx_ack.eq(ipstack.rx_ack), 101 | ipstack.user_tx.eq(user.transmit_packet), 102 | user.transmit_ready.eq(ipstack.user_ready), 103 | user.packet_received.eq(ipstack.user_rx), 104 | ] 105 | 106 | return m 107 | -------------------------------------------------------------------------------- /gateware/daqnet/user.py: -------------------------------------------------------------------------------- 1 | from nmigen import Elaboratable, Module, Signal, Memory 2 | 3 | 4 | class User(Elaboratable): 5 | def __init__(self): 6 | self.user_rx_mem = Memory(8, 32) 7 | self.user_tx_mem = Memory(8, 32, 8 | [ord(x) for x in "Hello, World!!\r\n"]) 9 | self.mem_r_port = self.user_tx_mem.read_port() 10 | self.mem_w_port = self.user_rx_mem.write_port() 11 | self.packet_received = Signal() 12 | self.transmit_ready = Signal() 13 | self.transmit_packet = Signal() 14 | 15 | def elaborate(self, platform): 16 | m = Module() 17 | rx_port = self.user_rx_mem.read_port() 18 | tx_port = self.user_tx_mem.write_port() 19 | 20 | m.submodules += [self.mem_r_port, self.mem_w_port, rx_port, tx_port] 21 | 22 | led1 = platform.request("user_led", 0) 23 | led2 = platform.request("user_led", 1) 24 | 25 | m.d.comb += [ 26 | tx_port.addr.eq(0), 27 | tx_port.en.eq(0), 28 | tx_port.data.eq(0), 29 | rx_port.addr.eq(0), 30 | ] 31 | 32 | m.d.sync += [ 33 | led1.eq(rx_port.data & 1), 34 | led2.eq((rx_port.data & 2) >> 1), 35 | ] 36 | 37 | with m.FSM(): 38 | with m.State("IDLE"): 39 | m.d.sync += self.transmit_packet.eq(0) 40 | with m.If(self.packet_received): 41 | m.next = "RX" 42 | with m.State("RX"): 43 | with m.If(self.transmit_ready): 44 | m.d.sync += self.transmit_packet.eq(1) 45 | m.next = "IDLE" 46 | 47 | return m 48 | -------------------------------------------------------------------------------- /gateware/daqnet/utils.py: -------------------------------------------------------------------------------- 1 | """ 2 | Gateway utilities and common modules. 3 | 4 | Copyright 2018-2019 Adam Greig 5 | Released under the MIT license; see LICENSE for details. 6 | """ 7 | 8 | from nmigen import Module, Signal, Cat, Elaboratable 9 | 10 | 11 | class LFSR(Elaboratable): 12 | TAPS = {7: 6, 9: 5, 11: 9, 15: 14, 20: 3, 23: 18, 31: 28} 13 | 14 | def __init__(self, k): 15 | self.reset = Signal() 16 | self.state = Signal(k, reset=1) 17 | 18 | if k not in LFSR.TAPS.keys(): 19 | raise ValueError(f"k={k} invalid for LFSR") 20 | 21 | self.k = k 22 | 23 | def elaborate(self, platform): 24 | m = Module() 25 | x = Signal() 26 | tap = LFSR.TAPS[self.k] 27 | m.d.comb += x.eq(self.state[self.k-1] ^ self.state[tap-1]) 28 | with m.If(self.reset): 29 | m.d.sync += self.state.eq(1) 30 | with m.Else(): 31 | m.d.sync += Cat(self.state).eq(Cat(x, self.state)) 32 | 33 | return m 34 | 35 | 36 | class PulseStretch(Elaboratable): 37 | def __init__(self, nclks): 38 | # Inputs 39 | self.trigger = Signal() 40 | 41 | # Outputs 42 | self.pulse = Signal() 43 | 44 | self.nclks = nclks 45 | 46 | def elaborate(self, platform): 47 | m = Module() 48 | 49 | counter = Signal(max=self.nclks) 50 | 51 | with m.FSM() as fsm: 52 | m.d.comb += self.pulse.eq(fsm.ongoing("STRETCH")) 53 | with m.State("WAIT"): 54 | m.d.sync += counter.eq(0) 55 | with m.If(self.trigger): 56 | m.next = "STRETCH" 57 | 58 | with m.State("STRETCH"): 59 | with m.If(counter == self.nclks - 1): 60 | m.next = "WAIT" 61 | with m.Else(): 62 | m.d.sync += counter.eq(counter + 1) 63 | 64 | return m 65 | 66 | 67 | class PipelinedAdder(Elaboratable): 68 | """ 69 | Implements an n-wide adder using m pipelined sub-adders. 70 | """ 71 | def __init__(self, n, m): 72 | self.a = Signal(n) 73 | self.b = Signal(n) 74 | self.c = Signal(n) 75 | 76 | self.n = n 77 | self.m = m 78 | 79 | def elaborate(self, platform): 80 | m = Module() 81 | 82 | bits_per_sub = self.n//self.m 83 | ci = 0 84 | for idx in range(self.m): 85 | sub_adder = Signal(bits_per_sub+1, name=f"sub{idx}") 86 | i0 = idx*bits_per_sub 87 | i1 = (idx+1)*bits_per_sub 88 | m.d.sync += sub_adder.eq(self.a[i0:i1] + self.b[i0:i1] + ci) 89 | m.d.comb += self.c[i0:i1].eq(sub_adder[:bits_per_sub]) 90 | ci = sub_adder[-1] 91 | 92 | return m 93 | 94 | 95 | def test_pipelined_adder(): 96 | from nmigen.back import pysim 97 | import random 98 | 99 | n = 64 100 | m = 4 101 | adder = PipelinedAdder(n, m) 102 | 103 | def testbench(): 104 | for _ in range(100): 105 | a = random.randrange(2**n) 106 | b = random.randrange(2**n) 107 | yield 108 | yield adder.a.eq(a) 109 | yield adder.b.eq(b) 110 | for _ in range(m+1): 111 | yield 112 | assert (yield adder.c) == (a+b) % (2**n) 113 | 114 | yield adder.a.eq(2**n-1) 115 | yield adder.b.eq(1) 116 | for _ in range(m+1): 117 | yield 118 | assert (yield adder.c) == 0 119 | 120 | vcdf = open("adder.vcd", "w") 121 | with pysim.Simulator(adder, vcd_file=vcdf) as sim: 122 | sim.add_clock(1e-6) 123 | sim.add_sync_process(testbench()) 124 | sim.run() 125 | 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| X101026071Y-108817857D01* 292 | X101073690Y-109008333D01* 293 | X101073690Y-109246428D01* 294 | X101026071Y-109436904D01* 295 | X100978452Y-109532142D01* 296 | X100930833Y-109579761D01* 297 | X100835595Y-109627380D01* 298 | X100740357Y-109627380D01* 299 | X100645119Y-109579761D01* 300 | X100597500Y-109532142D01* 301 | X100549880Y-109436904D01* 302 | X100502261Y-109246428D01* 303 | X100502261Y-109008333D01* 304 | X100549880Y-108817857D01* 305 | X100597500Y-108722619D01* 306 | X100645119Y-108675000D01* 307 | X100740357Y-108627380D01* 308 | X102026071Y-109627380D02* 309 | X101454642Y-109627380D01* 310 | X101740357Y-109627380D02* 311 | X101740357Y-108627380D01* 312 | X101645119Y-108770238D01* 313 | X101549880Y-108865476D01* 314 | X101454642Y-108913095D01* 315 | X94835595Y-111277380D02* 316 | X94835595Y-110610714D01* 317 | X94835595Y-110801190D02* 318 | X94883214Y-110705952D01* 319 | X94930833Y-110658333D01* 320 | X95026071Y-110610714D01* 321 | X95121309Y-110610714D01* 322 | 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X118285714Y-126678571D01* 355 | X119071428Y-126678571D02* 356 | X120071428Y-128178571D01* 357 | X120071428Y-126678571D02* 358 | X119071428Y-128178571D01* 359 | X118750000Y-108178571D02* 360 | X118250000Y-107464285D01* 361 | X117892857Y-108178571D02* 362 | X117892857Y-106678571D01* 363 | X118464285Y-106678571D01* 364 | X118607142Y-106750000D01* 365 | X118678571Y-106821428D01* 366 | X118750000Y-106964285D01* 367 | X118750000Y-107178571D01* 368 | X118678571Y-107321428D01* 369 | X118607142Y-107392857D01* 370 | X118464285Y-107464285D01* 371 | X117892857Y-107464285D01* 372 | X119250000Y-106678571D02* 373 | X120250000Y-108178571D01* 374 | X120250000Y-106678571D02* 375 | X119250000Y-108178571D01* 376 | G04 #@! TO.C,J102* 377 | X110100000Y-128100000D02* 378 | X110100000Y-111900000D01* 379 | X104800000Y-128100000D02* 380 | X110100000Y-128100000D01* 381 | X94700000Y-128100000D02* 382 | X102000000Y-128100000D01* 383 | X94700000Y-111900000D02* 384 | X94700000Y-128100000D01* 385 | X102000000Y-111900000D02* 386 | X94700000Y-111900000D01* 387 | X110100000Y-111900000D02* 388 | X104800000Y-111900000D01* 389 | G04 #@! TO.C,U101* 390 | X117625000Y-93500000D02* 391 | X118550000Y-93500000D01* 392 | X117625000Y-90375000D02* 393 | X114375000Y-90375000D01* 394 | X117625000Y-93625000D02* 395 | X114375000Y-93625000D01* 396 | X117625000Y-90375000D02* 397 | X117625000Y-90590000D01* 398 | X114375000Y-90375000D02* 399 | X114375000Y-90590000D01* 400 | X114375000Y-93625000D02* 401 | X114375000Y-93410000D01* 402 | X117625000Y-93625000D02* 403 | X117625000Y-93500000D01* 404 | G04 #@! TO.C,J101* 405 | X110100000Y-108100000D02* 406 | X110100000Y-91900000D01* 407 | X104800000Y-108100000D02* 408 | X110100000Y-108100000D01* 409 | X94700000Y-108100000D02* 410 | X102000000Y-108100000D01* 411 | X94700000Y-91900000D02* 412 | X94700000Y-108100000D01* 413 | X102000000Y-91900000D02* 414 | X94700000Y-91900000D01* 415 | X110100000Y-91900000D02* 416 | X104800000Y-91900000D01* 417 | G04 #@! TO.C,IC102* 418 | X113375000Y-99025000D02* 419 | X113975000Y-99625000D01* 420 | X112025000Y-99025000D02* 421 | X113375000Y-99025000D01* 422 | X112025000Y-100975000D02* 423 | X112025000Y-99025000D01* 424 | X113975000Y-100975000D02* 425 | X112025000Y-100975000D01* 426 | X113975000Y-99625000D02* 427 | X113975000Y-100975000D01* 428 | G04 #@! TO.C,IC101* 429 | X113375000Y-119025000D02* 430 | X113975000Y-119625000D01* 431 | X112025000Y-119025000D02* 432 | X113375000Y-119025000D01* 433 | X112025000Y-120975000D02* 434 | X112025000Y-119025000D01* 435 | X113975000Y-120975000D02* 436 | X112025000Y-120975000D01* 437 | X113975000Y-119625000D02* 438 | X113975000Y-120975000D01* 439 | G04 #@! TO.C,C102* 440 | X120550000Y-92125000D02* 441 | X119450000Y-92125000D01* 442 | X120550000Y-91875000D02* 443 | X120550000Y-92125000D01* 444 | X119450000Y-91875000D02* 445 | X120550000Y-91875000D01* 446 | X119450000Y-92125000D02* 447 | X119450000Y-91875000D01* 448 | G04 #@! TO.C,C101* 449 | X112550000Y-92125000D02* 450 | X111450000Y-92125000D01* 451 | X112550000Y-91875000D02* 452 | X112550000Y-92125000D01* 453 | X111450000Y-91875000D02* 454 | X112550000Y-91875000D01* 455 | X111450000Y-92125000D02* 456 | X111450000Y-91875000D01* 457 | G04 #@! TD* 458 | M02* 459 | -------------------------------------------------------------------------------- /hardware/interposer/gerber/interposer-NPTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Sat 01 Dec 2018 20:35:57 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.1280 7 | % 8 | G90 9 | G05 10 | T1 11 | X3.937Y-3.687 12 | X3.937Y-4.187 13 | X3.937Y-4.4744 14 | X3.937Y-4.9744 15 | T0 16 | M30 17 | -------------------------------------------------------------------------------- /hardware/interposer/gerber/interposer-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Sat 01 Dec 2018 20:35:57 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.0118 7 | T2C0.0354 8 | T3C0.0620 9 | % 10 | G90 11 | G05 12 | T1 13 | X4.2028Y-3.9508 14 | X4.2047Y-4.0059 15 | X4.2224Y-4.7717 16 | X4.2323Y-4.0512 17 | X4.2559Y-4.0709 18 | X4.2736Y-4.7717 19 | X4.3583Y-3.5866 20 | X4.4291Y-4.126 21 | X4.4291Y-4.9134 22 | X4.4665Y-4.126 23 | X4.4685Y-4.9134 24 | X4.5453Y-3.8976 25 | X4.5472Y-4.0079 26 | X4.5472Y-4.6831 27 | X4.5472Y-4.7874 28 | X4.5669Y-3.622 29 | X4.685Y-3.7047 30 | X4.685Y-4.1693 31 | X4.685Y-4.4921 32 | X4.685Y-4.9567 33 | X4.7717Y-3.5866 34 | T2 35 | X4.037Y-3.837 36 | X4.037Y-3.917 37 | X4.037Y-3.997 38 | X4.037Y-4.077 39 | X4.107Y-3.797 40 | X4.107Y-3.877 41 | X4.107Y-3.957 42 | X4.107Y-4.037 43 | X4.297Y-3.667 44 | X4.297Y-3.757 45 | X4.297Y-4.117 46 | X4.297Y-4.207 47 | X4.037Y-4.6244 48 | X4.037Y-4.7044 49 | X4.037Y-4.7844 50 | X4.037Y-4.8644 51 | X4.107Y-4.5844 52 | X4.107Y-4.6644 53 | X4.107Y-4.7444 54 | X4.107Y-4.8244 55 | X4.297Y-4.4544 56 | X4.297Y-4.5444 57 | X4.297Y-4.9044 58 | X4.297Y-4.9944 59 | T3 60 | X4.072Y-3.617 61 | X4.072Y-4.257 62 | X4.072Y-4.4044 63 | X4.072Y-5.0444 64 | T0 65 | M30 66 | -------------------------------------------------------------------------------- /hardware/interposer/interposer-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # Regulator_Linear_LT3010-5 5 | # 6 | DEF Regulator_Linear_LT3010-5 U 0 30 Y Y 1 F N 7 | F0 "U" -250 250 50 H V C CNN 8 | F1 "Regulator_Linear_LT3010-5" 0 250 50 H V L CNN 9 | F2 "Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm" 0 325 50 H I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | $FPLIST 12 | MSOP*3x3mm*P0.65mm* 13 | $ENDFPLIST 14 | DRAW 15 | S -300 200 300 -200 0 1 10 f 16 | X OUT 1 400 100 100 L 50 50 1 1 w 17 | X SENSE 2 400 0 100 L 50 50 1 1 P 18 | X NC 3 -400 -100 100 R 50 50 1 1 N N 19 | X GND 4 0 -300 100 U 50 50 1 1 W 20 | X ~SHDN 5 -400 0 100 R 50 50 1 1 I 21 | X NC 6 400 -100 100 L 50 50 1 1 N N 22 | X NC 7 100 -300 100 U 50 50 1 1 N N 23 | X IN 8 -400 100 100 R 50 50 1 1 W 24 | X GND 9 0 -300 100 U 50 50 1 1 P N 25 | ENDDRAW 26 | ENDDEF 27 | # 28 | # agg_5v 29 | # 30 | DEF agg_5v #PWR 0 40 N N 1 F P 31 | F0 "#PWR" 0 110 50 H I L CNN 32 | F1 "agg_5v" 0 90 50 H V C CNN 33 | F2 "" 0 0 50 H I C CNN 34 | F3 "" 0 0 50 H I C CNN 35 | DRAW 36 | P 2 0 1 0 0 50 20 20 N 37 | P 3 0 1 0 0 0 0 50 -20 20 N 38 | X 5v 1 0 0 0 L 50 50 1 1 W N 39 | ENDDRAW 40 | ENDDEF 41 | # 42 | # agg_AD8226 43 | # 44 | DEF agg_AD8226 IC 0 40 Y Y 1 F N 45 | F0 "IC" -200 450 50 H V L CNN 46 | F1 "agg_AD8226" -200 -450 50 H V L CNN 47 | F2 "agg:MSOP-8" -200 -550 50 H I L CNN 48 | F3 "" 50 0 50 H I C CNN 49 | F4 "2462026" -200 -650 50 H I L CNN "Farnell" 50 | DRAW 51 | S -200 400 300 -400 0 1 0 f 52 | X -IN 1 -300 0 100 R 50 50 1 1 I 53 | X RG 2 400 300 100 L 50 50 1 1 P 54 | X RG 3 400 200 100 L 50 50 1 1 P 55 | X +IN 4 -300 -100 100 R 50 50 1 1 I 56 | X -Vs 5 -300 200 100 R 50 50 1 1 W 57 | X REF 6 -300 -300 100 R 50 50 1 1 I 58 | X OUT 7 400 0 100 L 50 50 1 1 O 59 | X +Vs 8 -300 300 100 R 50 50 1 1 W 60 | ENDDRAW 61 | ENDDEF 62 | # 63 | # agg_C 64 | # 65 | DEF agg_C C 0 40 N N 1 F N 66 | F0 "C" 50 70 50 H V C CNN 67 | F1 "agg_C" 50 -70 50 H V C CNN 68 | F2 "" 0 0 50 H I C CNN 69 | F3 "" 0 0 50 H I C CNN 70 | DRAW 71 | P 2 0 1 0 40 30 40 -30 N 72 | P 2 0 1 0 60 30 60 -30 N 73 | X ~ 1 0 0 40 R 50 50 1 1 P 74 | X ~ 2 100 0 40 L 50 50 1 1 P 75 | ENDDRAW 76 | ENDDEF 77 | # 78 | # agg_CHASSIS 79 | # 80 | DEF agg_CHASSIS #PWR 0 40 N N 1 F P 81 | F0 "#PWR" -130 40 50 H I L CNN 82 | F1 "agg_CHASSIS" 0 -100 50 H V C CNN 83 | F2 "" 0 0 50 H I C CNN 84 | F3 "" 0 0 50 H I C CNN 85 | DRAW 86 | P 2 0 1 0 0 0 0 -30 N 87 | P 4 0 1 0 -30 -30 30 -30 0 -60 -30 -30 f 88 | X CHASSIS 1 0 0 0 L 50 50 1 1 W N 89 | ENDDRAW 90 | ENDDEF 91 | # 92 | # agg_COAX 93 | # 94 | DEF agg_COAX P 0 40 N N 1 F N 95 | F0 "P" 0 100 50 H V C CNN 96 | F1 "agg_COAX" 0 -150 50 H V C CNN 97 | F2 "agg:SMA-EDGE" 0 -210 50 H I C CNN 98 | F3 "" 100 -100 50 H I C CNN 99 | F4 "1608592" 0 -280 50 H I C CNN "Farnell" 100 | DRAW 101 | C 0 0 20 0 1 0 F 102 | C 0 0 60 0 1 0 f 103 | P 2 0 1 0 0 -60 0 -100 N 104 | X RF 1 -100 0 100 R 50 50 1 1 B 105 | X GND 2 -100 -100 100 R 50 50 1 1 W 106 | ENDDRAW 107 | ENDDEF 108 | # 109 | # agg_ESD_DIODE 110 | # 111 | DEF ~agg_ESD_DIODE D 0 0 N N 1 F N 112 | F0 "D" -50 100 50 H V L CNN 113 | F1 "agg_ESD_DIODE" -50 -100 50 H I L CNN 114 | F2 "agg:0402" -50 -200 50 H I L CNN 115 | F3 "" -100 0 50 H I C CNN 116 | F4 "2368169" -50 -300 50 H I L CNN "Farnell" 117 | DRAW 118 | P 2 0 1 0 0 -30 10 -30 N 119 | P 2 0 1 0 0 30 -10 30 N 120 | P 2 0 1 0 0 30 0 -30 N 121 | P 4 0 1 0 0 0 -50 30 -50 -30 0 0 F 122 | P 4 0 1 0 0 0 50 30 50 -30 0 0 F 123 | X 1 1 -100 0 50 R 50 50 1 1 P 124 | X 2 2 100 0 50 L 50 50 1 1 P 125 | ENDDRAW 126 | ENDDEF 127 | # 128 | # agg_GND 129 | # 130 | DEF agg_GND #PWR 0 40 N N 1 F P 131 | F0 "#PWR" -130 40 50 H I L CNN 132 | F1 "agg_GND" 0 -100 50 H V C CNN 133 | F2 "" 0 0 50 H I C CNN 134 | F3 "" 0 0 50 H I C CNN 135 | DRAW 136 | P 2 0 1 0 0 0 0 -30 N 137 | P 4 0 1 0 -30 -30 30 -30 0 -60 -30 -30 f 138 | X GND 1 0 0 0 L 50 50 1 1 W N 139 | ENDDRAW 140 | ENDDEF 141 | # 142 | # agg_PWR 143 | # 144 | DEF agg_PWR #FLG 0 40 N N 1 F P 145 | F0 "#FLG" 0 160 50 H I C CNN 146 | F1 "agg_PWR" 0 90 50 H V C CNN 147 | F2 "" 0 0 50 H I C CNN 148 | F3 "" 0 0 50 H I C CNN 149 | DRAW 150 | P 5 0 1 0 0 20 -20 40 0 60 20 40 0 20 f 151 | X pwr 1 0 0 20 U 50 50 1 1 w 152 | ENDDRAW 153 | ENDDEF 154 | # 155 | # agg_R 156 | # 157 | DEF agg_R R 0 40 N N 1 F N 158 | F0 "R" 50 50 50 H V C CNN 159 | F1 "agg_R" 50 -50 50 H V C CNN 160 | F2 "" 0 0 50 H I C CNN 161 | F3 "" 0 0 50 H I C CNN 162 | DRAW 163 | S 20 10 80 -10 0 1 0 f 164 | X ~ 1 0 0 20 R 50 50 1 1 P 165 | X ~ 2 100 0 20 L 50 50 1 1 P 166 | ENDDRAW 167 | ENDDEF 168 | # 169 | # agg_RJHSE-538x 170 | # 171 | DEF agg_RJHSE-538x J 0 40 Y Y 1 F N 172 | F0 "J" -400 500 50 H V L CNN 173 | F1 "agg_RJHSE-538x" -400 -500 50 H V L CNN 174 | F2 "agg:RJHSE-538X" -400 -600 50 H I L CNN 175 | F3 "http://www.farnell.com/cad/2167247.pdf" -400 -700 50 H I L CNN 176 | F4 "1462758" -400 -800 50 H I L CNN "Farnell" 177 | DRAW 178 | S -400 450 400 -450 0 1 0 f 179 | X TX+ 1 500 -300 100 L 50 50 0 0 P 180 | X LED1_A 10 -500 300 100 R 50 50 0 0 P 181 | X LED2_C 11 -500 100 100 R 50 50 0 0 P 182 | X LED2_A 12 -500 0 100 R 50 50 0 0 P 183 | X TX- 2 500 -200 100 L 50 50 0 0 P 184 | X RX+ 3 500 -100 100 L 50 50 0 0 P 185 | X ~ 4 500 0 100 L 50 50 0 0 P 186 | X ~ 5 500 100 100 L 50 50 0 0 P 187 | X RX- 6 500 200 100 L 50 50 0 0 P 188 | X ~ 7 500 300 100 L 50 50 0 0 P 189 | X ~ 8 500 400 100 L 50 50 0 0 P 190 | X LED1_C 9 -500 400 100 R 50 50 0 0 P 191 | X SHIELD S1 -500 -200 100 R 50 50 0 0 P 192 | X SHIELD S2 -500 -300 100 R 50 50 0 0 P 193 | ENDDRAW 194 | ENDDEF 195 | # 196 | # power_+48V 197 | # 198 | DEF power_+48V #PWR 0 0 Y Y 1 F P 199 | F0 "#PWR" 0 -150 50 H I C CNN 200 | F1 "power_+48V" 0 140 50 H V C CNN 201 | F2 "" 0 0 50 H I C CNN 202 | F3 "" 0 0 50 H I C CNN 203 | DRAW 204 | P 2 0 1 0 -30 50 0 100 N 205 | P 2 0 1 0 0 0 0 100 N 206 | P 2 0 1 0 0 100 30 50 N 207 | X +48V 1 0 0 0 U 50 50 1 1 W N 208 | ENDDRAW 209 | ENDDEF 210 | # 211 | #End Library 212 | -------------------------------------------------------------------------------- /hardware/interposer/interposer.bom: -------------------------------------------------------------------------------- 1 | Bill Of Materials 2 | ================= 3 | 4 | Source file: interposer.xml 5 | Date: 2018-12-01T20:48:58.090790 6 | 7 | Parts Missing Footprints 8 | ------------------------ 9 | 10 | 11 | Parts Missing Order Codes 12 | ------------------------- 13 | P102 COAX agg:SMA-EDGE 14 | P101 COAX agg:SMA-EDGE 15 | C101 1µ agg:0805 16 | C102 1µ agg:0805 17 | C103 100n agg:0402 18 | C104 100n agg:0402 19 | R101 DNF agg:0402 20 | R102 DNF agg:0402 21 | 22 | Inconsistent Order Codes 23 | ------------------------ 24 | 25 | 26 | Vendor Specific BOMs 27 | -------------------- 28 | RS 29 | ~~ 30 | 257-8785,2,,2x--RJHSE-5381--RJHSE-538X--J101J102 31 | 759-1288,2,,2x--AD8226ARMZ--MSOP-8--IC101IC102 32 | 794-7990,1,,1x--ESD_DIODE--0402--D101 33 | 761-8591,1,,1x--LT3010-5--MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm--U101 34 | 35 | 36 | Farnell 37 | ~~~~~~~ 38 | 2368169,1,1x ESD_DIODE 0402 39 | 40 | 41 | Assembly BOM 42 | ------------ 43 | 257-8785 2 RJHSE-5381 RJHSE-538X J101 J102 44 | 759-1288 2 AD8226ARMZ MSOP-8 IC101 IC102 45 | 794-7990 1 ESD_DIODE 0402 D101 46 | 761-8591 1 LT3010-5 MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm U101 47 | 2368169 1 ESD_DIODE 0402 D102 48 | 49 | -------------------------------------------------------------------------------- /hardware/interposer/interposer.pro: -------------------------------------------------------------------------------- 1 | update=Sat 01 Dec 2018 20:38:27 GMT 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [pcbnew] 16 | version=1 17 | PageLayoutDescrFile= 18 | LastNetListRead= 19 | CopperLayerCount=2 20 | BoardThickness=1.6 21 | AllowMicroVias=0 22 | AllowBlindVias=0 23 | RequireCourtyardDefinitions=0 24 | ProhibitOverlappingCourtyards=1 25 | MinTrackWidth=0.15 26 | MinViaDiameter=0.4 27 | MinViaDrill=0.3 28 | MinMicroViaDiameter=0.2 29 | MinMicroViaDrill=0.09999999999999999 30 | MinHoleToHole=0.25 31 | TrackWidth1=0.15 32 | TrackWidth2=0.15 33 | TrackWidth3=0.2 34 | TrackWidth4=0.4 35 | TrackWidth5=0.8 36 | TrackWidth6=1 37 | ViaDiameter1=0.8 38 | ViaDrill1=0.4 39 | ViaDiameter2=0.6 40 | ViaDrill2=0.3 41 | ViaDiameter3=0.8 42 | ViaDrill3=0.4 43 | ViaDiameter4=1 44 | ViaDrill4=0.5 45 | dPairWidth1=0.2 46 | dPairGap1=0.25 47 | dPairViaGap1=0.25 48 | dPairWidth2=0.15 49 | dPairGap2=0.15 50 | dPairViaGap2=0 51 | SilkLineWidth=0.12 52 | SilkTextSizeV=1 53 | SilkTextSizeH=1 54 | SilkTextSizeThickness=0.15 55 | SilkTextItalic=0 56 | SilkTextUpright=1 57 | CopperLineWidth=0.2 58 | CopperTextSizeV=1.5 59 | CopperTextSizeH=1.5 60 | CopperTextThickness=0.3 61 | CopperTextItalic=0 62 | CopperTextUpright=1 63 | EdgeCutLineWidth=0.05 64 | CourtyardLineWidth=0.05 65 | OthersLineWidth=0.15 66 | OthersTextSizeV=1 67 | OthersTextSizeH=1 68 | OthersTextSizeThickness=0.15 69 | OthersTextItalic=0 70 | OthersTextUpright=1 71 | SolderMaskClearance=0.02 72 | SolderMaskMinWidth=0.25 73 | SolderPasteClearance=0 74 | SolderPasteRatio=-0 75 | -------------------------------------------------------------------------------- /hardware/interposer/interposer.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | /home/adam/Projects/daqnet/hardware/interposer/interposer.sch 5 | Sat 01 Dec 2018 20:48:58 GMT 6 | Eeschema 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1 7 | 8 | 9 | DAQnet Interposer 10 | 11 | 1 12 | 2018-12-01 13 | interposer.sch 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | RJHSE-5381 24 | agg:RJHSE-538X 25 | 26 | 257-8785 27 | 28 | 29 | 30 | 5C02DBD9 31 | 32 | 33 | RJHSE-5381 34 | agg:RJHSE-538X 35 | 36 | 257-8785 37 | 38 | 39 | 40 | 5C02EBFB 41 | 42 | 43 | AD8226ARMZ 44 | agg:MSOP-8 45 | 46 | 759-1288 47 | 48 | 49 | 50 | 5C034410 51 | 52 | 53 | COAX 54 | agg:SMA-EDGE 55 | 56 | 57 | 5C03516A 58 | 59 | 60 | COAX 61 | agg:SMA-EDGE 62 | 63 | 64 | 5C03585A 65 | 66 | 67 | ESD_DIODE 68 | agg:0402 69 | 70 | 2368169 71 | 72 | 73 | 74 | 5C036043 75 | 76 | 77 | ESD_DIODE 78 | agg:0402 79 | 80 | 794-7990 81 | 82 | 83 | 84 | 5C03650B 85 | 86 | 87 | AD8226ARMZ 88 | agg:MSOP-8 89 | 90 | 759-1288 91 | 92 | 93 | 94 | 5C06787C 95 | 96 | 97 | LT3010-5 98 | Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm 99 | http://cds.linear.com/docs/en/datasheet/30105fe.pdf 100 | 101 | 761-8591 102 | 103 | 104 | 105 | 5C068E47 106 | 107 | 108 | 1µ 109 | agg:0805 110 | 111 | 112 | 5C0732F9 113 | 114 | 115 | 1µ 116 | agg:0805 117 | 118 | 119 | 5C076F7D 120 | 121 | 122 | 100n 123 | agg:0402 124 | 125 | 126 | 5C09D320 127 | 128 | 129 | 100n 130 | agg:0402 131 | 132 | 133 | 5C0A219C 134 | 135 | 136 | DNF 137 | agg:0402 138 | 139 | 140 | 5C0312EA 141 | 142 | 143 | DNF 144 | agg:0402 145 | 146 | 147 | 5C03662C 148 | 149 | 150 | 151 | 152 | 50mA 3-80V Micropower Low Dropout Regulator, fixed output 5V, MSOP-8 153 | http://cds.linear.com/docs/en/datasheet/30105fe.pdf 154 | 155 | MSOP*3x3mm*P0.65mm* 156 | 157 | 158 | U 159 | LT3010-5 160 | Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | Instrumentation Amplifier 176 | 177 | IC 178 | AD8226 179 | agg:MSOP-8 180 | 2462026 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | C 196 | C 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | Coaxial connection 205 | 206 | P 207 | COAX 208 | agg:SMA-EDGE 209 | 1608592 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | ESD diode 218 | 219 | D 220 | ESD_DIODE 221 | agg:0402 222 | 2368169 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | R 232 | R 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | Shielded 8P8C Modular Connector with LEDs 241 | 242 | J 243 | RJHSE-538x 244 | agg:RJHSE-538X 245 | http://www.farnell.com/cad/2167247.pdf 246 | 1462758 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | /usr/lib/kicad-nightly/share/kicad/library/Regulator_Linear.lib 269 | 270 | 271 | /home/adam/Projects/daqnet/hardware/interposer/../agg-kicad/agg-kicad.lib 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | -------------------------------------------------------------------------------- /hardware/interposer/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name agg)(type Legacy)(uri "$(KIPRJMOD)/../agg-kicad/agg-kicad.lib")(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /hardware/proto-sensor/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name agg)(type KiCad)(uri "$(KIPRJMOD)/../agg-kicad/agg.pretty")(options "")(descr "")) 3 | ) 4 | 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TO.C,J1* 266 | X66465000Y-93960000D03* 267 | X67735000Y-93960000D03* 268 | X66465000Y-95230000D03* 269 | X67735000Y-95230000D03* 270 | X66465000Y-96500000D03* 271 | X67735000Y-96500000D03* 272 | X66465000Y-97770000D03* 273 | X67735000Y-97770000D03* 274 | X66465000Y-99040000D03* 275 | X67735000Y-99040000D03* 276 | G04 #@! TD* 277 | D17* 278 | G04 #@! TO.C,P1* 279 | X56700000Y-108700000D03* 280 | X63300000Y-108700000D03* 281 | X56700000Y-115300000D03* 282 | D18* 283 | X60000000Y-112000000D03* 284 | D17* 285 | X63300000Y-115300000D03* 286 | G04 #@! TD* 287 | M02* 288 | -------------------------------------------------------------------------------- /hardware/proto-sensor/gerber/proto-sensor-Edge.Cuts.gm1: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:39:04+00:00* 3 | G04 #@! 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TF.FileFunction,Profile,NP* 6 | %FSLAX46Y46*% 7 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 8 | G04 Created by KiCad (PCBNEW 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1) date Tue 27 Nov 2018 01:39:04 GMT* 9 | %MOMM*% 10 | %LPD*% 11 | G01* 12 | G04 APERTURE LIST* 13 | %ADD10C,0.050000*% 14 | G04 APERTURE END LIST* 15 | D10* 16 | X51000000Y-120000000D02* 17 | G75* 18 | G02X50000000Y-119000000I0J1000000D01* 19 | G01* 20 | X70000000Y-119000000D02* 21 | G75* 22 | G02X69000000Y-120000000I-1000000J0D01* 23 | G01* 24 | X69000000Y-50000000D02* 25 | G75* 26 | G02X70000000Y-51000000I0J-1000000D01* 27 | G01* 28 | X50000000Y-51000000D02* 29 | G75* 30 | G02X51000000Y-50000000I1000000J0D01* 31 | G01* 32 | X69000000Y-120000000D02* 33 | X51000000Y-120000000D01* 34 | X50000000Y-119000000D02* 35 | X50000000Y-51000000D01* 36 | X70000000Y-51000000D02* 37 | X70000000Y-119000000D01* 38 | X51000000Y-50000000D02* 39 | X69000000Y-50000000D01* 40 | M02* 41 | -------------------------------------------------------------------------------- /hardware/proto-sensor/gerber/proto-sensor-F.Paste.gtp: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:39:04+00:00* 3 | G04 #@! TF.ProjectId,proto-sensor,70726f74-6f2d-4736-956e-736f722e6b69,1* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Paste,Top* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1) date Tue 27 Nov 2018 01:39:04 GMT* 10 | %MOMM*% 11 | %LPD*% 12 | G01* 13 | G04 APERTURE LIST* 14 | %ADD10R,0.950000X1.000000*% 15 | %ADD11R,0.800000X1.000000*% 16 | %ADD12R,0.200000X0.700000*% 17 | %ADD13R,0.620000X0.620000*% 18 | %ADD14R,1.400000X1.000000*% 19 | %ADD15R,3.890000X1.450000*% 20 | %ADD16R,0.600000X1.100000*% 21 | %ADD17R,1.000000X0.600000*% 22 | %ADD18R,0.850000X0.300000*% 23 | %ADD19R,0.300000X0.250000*% 24 | %ADD20R,1.000000X0.950000*% 25 | %ADD21C,0.400000*% 26 | G04 APERTURE END LIST* 27 | D10* 28 | G04 #@! TO.C,C15* 29 | X63050000Y-72150000D03* 30 | X64650000Y-72150000D03* 31 | G04 #@! TD* 32 | D11* 33 | G04 #@! TO.C,Y1* 34 | X64150000Y-78250000D03* 35 | X62450000Y-78250000D03* 36 | X62450000Y-76650000D03* 37 | X64150000Y-76650000D03* 38 | G04 #@! TD* 39 | D12* 40 | G04 #@! TO.C,IC7* 41 | X56450000Y-67525000D03* 42 | X55950000Y-67525000D03* 43 | X55450000Y-67525000D03* 44 | X54950000Y-67525000D03* 45 | X54450000Y-67525000D03* 46 | X54450000Y-66475000D03* 47 | X54950000Y-66475000D03* 48 | X55450000Y-66475000D03* 49 | X55950000Y-66475000D03* 50 | X56450000Y-66475000D03* 51 | G04 #@! TD* 52 | D13* 53 | G04 #@! TO.C,R1* 54 | X52400000Y-66350000D03* 55 | X53300000Y-66350000D03* 56 | G04 #@! TD* 57 | D14* 58 | G04 #@! TO.C,SW3* 59 | X52400000Y-102700000D03* 60 | X52400000Y-109700000D03* 61 | G04 #@! TD* 62 | G04 #@! TO.C,SW2* 63 | X67600000Y-102700000D03* 64 | X67600000Y-109700000D03* 65 | G04 #@! TD* 66 | D13* 67 | G04 #@! TO.C,R21* 68 | X55200000Y-102550000D03* 69 | X55200000Y-103450000D03* 70 | G04 #@! TD* 71 | G04 #@! TO.C,R20* 72 | X64800000Y-102550000D03* 73 | X64800000Y-103450000D03* 74 | G04 #@! TD* 75 | G04 #@! TO.C,C30* 76 | X69300000Y-80250000D03* 77 | X69300000Y-81150000D03* 78 | G04 #@! TD* 79 | G04 #@! TO.C,C29* 80 | X53350000Y-79800000D03* 81 | X54250000Y-79800000D03* 82 | G04 #@! TD* 83 | G04 #@! TO.C,C24* 84 | X53350000Y-78600000D03* 85 | X54250000Y-78600000D03* 86 | G04 #@! TD* 87 | D10* 88 | G04 #@! TO.C,D2* 89 | X66500000Y-76100000D03* 90 | X68100000Y-76100000D03* 91 | G04 #@! TD* 92 | D15* 93 | G04 #@! TO.C,L1* 94 | X67600000Y-71075000D03* 95 | X67600000Y-68125000D03* 96 | G04 #@! TD* 97 | D14* 98 | G04 #@! TO.C,SW1* 99 | X52400000Y-93000000D03* 100 | X52400000Y-100000000D03* 101 | G04 #@! TD* 102 | D13* 103 | G04 #@! TO.C,R19* 104 | X60450000Y-104400000D03* 105 | X59550000Y-104400000D03* 106 | G04 #@! TD* 107 | G04 #@! TO.C,R11* 108 | X68100000Y-81150000D03* 109 | X68100000Y-80250000D03* 110 | G04 #@! TD* 111 | D16* 112 | G04 #@! TO.C,IC6* 113 | X59050000Y-100400000D03* 114 | X60000000Y-100400000D03* 115 | X60950000Y-100400000D03* 116 | X60950000Y-103000000D03* 117 | X60000000Y-103000000D03* 118 | X59050000Y-103000000D03* 119 | G04 #@! TD* 120 | D17* 121 | G04 #@! TO.C,IC3* 122 | X61150000Y-69200000D03* 123 | X58850000Y-70150000D03* 124 | X58850000Y-68250000D03* 125 | G04 #@! TD* 126 | D18* 127 | G04 #@! TO.C,IC2* 128 | X64650000Y-69350000D03* 129 | X64650000Y-69850000D03* 130 | X64650000Y-70350000D03* 131 | X64650000Y-70850000D03* 132 | X62750000Y-70850000D03* 133 | X62750000Y-70350000D03* 134 | X62750000Y-69850000D03* 135 | X62750000Y-69350000D03* 136 | G04 #@! TD* 137 | D13* 138 | G04 #@! TO.C,D4* 139 | X57450000Y-104400000D03* 140 | X58350000Y-104400000D03* 141 | G04 #@! TD* 142 | D10* 143 | G04 #@! TO.C,D3* 144 | X66500000Y-78900000D03* 145 | X68100000Y-78900000D03* 146 | G04 #@! TD* 147 | G04 #@! TO.C,D1* 148 | X66500000Y-73300000D03* 149 | X68100000Y-73300000D03* 150 | G04 #@! TD* 151 | D13* 152 | G04 #@! TO.C,C27* 153 | X62550000Y-104400000D03* 154 | X61650000Y-104400000D03* 155 | G04 #@! TD* 156 | G04 #@! TO.C,C25* 157 | X57500000Y-102250000D03* 158 | X57500000Y-103150000D03* 159 | G04 #@! TD* 160 | G04 #@! TO.C,C22* 161 | X59600000Y-72150000D03* 162 | X58700000Y-72150000D03* 163 | G04 #@! TD* 164 | G04 #@! TO.C,C21* 165 | X60550000Y-66500000D03* 166 | X61450000Y-66500000D03* 167 | G04 #@! TD* 168 | G04 #@! TO.C,C18* 169 | X61700000Y-72150000D03* 170 | X60800000Y-72150000D03* 171 | G04 #@! TD* 172 | D10* 173 | G04 #@! TO.C,C16* 174 | X64500000Y-66500000D03* 175 | X62900000Y-66500000D03* 176 | G04 #@! TD* 177 | D13* 178 | G04 #@! TO.C,R15* 179 | X69250000Y-86850000D03* 180 | X69250000Y-87750000D03* 181 | G04 #@! TD* 182 | G04 #@! TO.C,R17* 183 | X69300000Y-84450000D03* 184 | X69300000Y-85350000D03* 185 | G04 #@! TD* 186 | G04 #@! TO.C,R14* 187 | X68100000Y-85350000D03* 188 | X68100000Y-84450000D03* 189 | G04 #@! TD* 190 | G04 #@! TO.C,R10* 191 | X66850000Y-77500000D03* 192 | X67750000Y-77500000D03* 193 | G04 #@! TD* 194 | G04 #@! TO.C,R9* 195 | X66850000Y-74700000D03* 196 | X67750000Y-74700000D03* 197 | G04 #@! TD* 198 | G04 #@! TO.C,R18* 199 | X69350000Y-90600000D03* 200 | X68450000Y-90600000D03* 201 | G04 #@! TD* 202 | G04 #@! TO.C,C26* 203 | X63400000Y-99850000D03* 204 | X63400000Y-98950000D03* 205 | G04 #@! TD* 206 | D19* 207 | G04 #@! TO.C,IC5* 208 | X65775000Y-88250000D03* 209 | X65775000Y-87750000D03* 210 | X65775000Y-87250000D03* 211 | X65775000Y-86750000D03* 212 | X68225000Y-86750000D03* 213 | X68225000Y-87250000D03* 214 | X68225000Y-87750000D03* 215 | X68225000Y-88250000D03* 216 | G04 #@! TD* 217 | D13* 218 | G04 #@! TO.C,C28* 219 | X62850000Y-75300000D03* 220 | X63750000Y-75300000D03* 221 | G04 #@! TD* 222 | D10* 223 | G04 #@! TO.C,C17* 224 | X64500000Y-68000000D03* 225 | X62900000Y-68000000D03* 226 | G04 #@! TD* 227 | D13* 228 | G04 #@! TO.C,C23* 229 | X67250000Y-89400000D03* 230 | X66350000Y-89400000D03* 231 | G04 #@! TD* 232 | G04 #@! TO.C,C12* 233 | X65700000Y-80250000D03* 234 | X65700000Y-81150000D03* 235 | G04 #@! TD* 236 | G04 #@! TO.C,C11* 237 | X51900000Y-83850000D03* 238 | X51900000Y-84750000D03* 239 | G04 #@! TD* 240 | G04 #@! TO.C,C10* 241 | X54300000Y-90250000D03* 242 | X54300000Y-89350000D03* 243 | G04 #@! TD* 244 | G04 #@! TO.C,C4* 245 | X54300000Y-83850000D03* 246 | X54300000Y-84750000D03* 247 | G04 #@! TD* 248 | G04 #@! TO.C,C9* 249 | X66900000Y-85350000D03* 250 | X66900000Y-84450000D03* 251 | G04 #@! TD* 252 | G04 #@! TO.C,C3* 253 | X65700000Y-82350000D03* 254 | X65700000Y-83250000D03* 255 | G04 #@! TD* 256 | G04 #@! TO.C,C8* 257 | X66900000Y-80250000D03* 258 | X66900000Y-81150000D03* 259 | G04 #@! TD* 260 | G04 #@! TO.C,C6* 261 | X65700000Y-85350000D03* 262 | X65700000Y-84450000D03* 263 | G04 #@! TD* 264 | G04 #@! TO.C,C2* 265 | X66900000Y-82350000D03* 266 | X66900000Y-83250000D03* 267 | G04 #@! TD* 268 | G04 #@! TO.C,C7* 269 | X53100000Y-90250000D03* 270 | X53100000Y-89350000D03* 271 | G04 #@! TD* 272 | G04 #@! TO.C,C5* 273 | X50700000Y-83850000D03* 274 | X50700000Y-84750000D03* 275 | G04 #@! TD* 276 | G04 #@! TO.C,C1* 277 | X53100000Y-83850000D03* 278 | X53100000Y-84750000D03* 279 | G04 #@! TD* 280 | G04 #@! TO.C,R13* 281 | X68100000Y-82350000D03* 282 | X68100000Y-83250000D03* 283 | G04 #@! TD* 284 | G04 #@! TO.C,R12* 285 | X66350000Y-90600000D03* 286 | X67250000Y-90600000D03* 287 | G04 #@! TD* 288 | G04 #@! TO.C,R16* 289 | X68450000Y-89400000D03* 290 | X69350000Y-89400000D03* 291 | G04 #@! TD* 292 | G04 #@! TO.C,R8* 293 | X60150000Y-75300000D03* 294 | X59250000Y-75300000D03* 295 | G04 #@! TD* 296 | G04 #@! TO.C,R7* 297 | X51500000Y-86550000D03* 298 | X51500000Y-87450000D03* 299 | G04 #@! TD* 300 | G04 #@! TO.C,C20* 301 | X59250000Y-78300000D03* 302 | X60150000Y-78300000D03* 303 | G04 #@! TD* 304 | G04 #@! TO.C,C14* 305 | X54300000Y-87450000D03* 306 | X54300000Y-86550000D03* 307 | G04 #@! TD* 308 | D10* 309 | G04 #@! TO.C,C19* 310 | X58900000Y-76800000D03* 311 | X60500000Y-76800000D03* 312 | G04 #@! TD* 313 | D20* 314 | G04 #@! TO.C,C13* 315 | X52900000Y-87800000D03* 316 | X52900000Y-86200000D03* 317 | G04 #@! TD* 318 | D13* 319 | G04 #@! TO.C,R4* 320 | X54250000Y-82200000D03* 321 | X53350000Y-82200000D03* 322 | G04 #@! TD* 323 | G04 #@! TO.C,R6* 324 | X54250000Y-81000000D03* 325 | X53350000Y-81000000D03* 326 | G04 #@! TD* 327 | G04 #@! TO.C,R3* 328 | X67650000Y-66400000D03* 329 | X66750000Y-66400000D03* 330 | G04 #@! TD* 331 | G04 #@! TO.C,R5* 332 | X52000000Y-81150000D03* 333 | X52000000Y-82050000D03* 334 | G04 #@! TD* 335 | G04 #@! TO.C,R2* 336 | X56650000Y-78200000D03* 337 | X55750000Y-78200000D03* 338 | G04 #@! TD* 339 | D21* 340 | G04 #@! TO.C,IC4* 341 | X64000000Y-88000000D03* 342 | X64000000Y-87200000D03* 343 | X64000000Y-86400000D03* 344 | X64000000Y-85600000D03* 345 | X64000000Y-84800000D03* 346 | X64000000Y-84000000D03* 347 | X64000000Y-83200000D03* 348 | X64000000Y-82400000D03* 349 | X64000000Y-81600000D03* 350 | X64000000Y-80800000D03* 351 | X64000000Y-80000000D03* 352 | X63200000Y-88000000D03* 353 | X63200000Y-87200000D03* 354 | X63200000Y-86400000D03* 355 | X63200000Y-85600000D03* 356 | X63200000Y-84800000D03* 357 | X63200000Y-84000000D03* 358 | X63200000Y-83200000D03* 359 | X63200000Y-82400000D03* 360 | X63200000Y-81600000D03* 361 | X63200000Y-80800000D03* 362 | X63200000Y-80000000D03* 363 | X62400000Y-88000000D03* 364 | X62400000Y-87200000D03* 365 | X62400000Y-86400000D03* 366 | X62400000Y-85600000D03* 367 | X62400000Y-84800000D03* 368 | X62400000Y-84000000D03* 369 | X62400000Y-83200000D03* 370 | X62400000Y-82400000D03* 371 | X62400000Y-81600000D03* 372 | X62400000Y-80800000D03* 373 | X62400000Y-80000000D03* 374 | X61600000Y-88000000D03* 375 | X61600000Y-87200000D03* 376 | X61600000Y-86400000D03* 377 | X61600000Y-85600000D03* 378 | X61600000Y-84800000D03* 379 | X61600000Y-84000000D03* 380 | X61600000Y-83200000D03* 381 | X61600000Y-82400000D03* 382 | X61600000Y-81600000D03* 383 | X61600000Y-80800000D03* 384 | X61600000Y-80000000D03* 385 | X60800000Y-88000000D03* 386 | X60800000Y-87200000D03* 387 | X60800000Y-86400000D03* 388 | X60800000Y-85600000D03* 389 | X60800000Y-84800000D03* 390 | X60800000Y-84000000D03* 391 | X60800000Y-83200000D03* 392 | X60800000Y-82400000D03* 393 | X60800000Y-81600000D03* 394 | X60800000Y-80800000D03* 395 | X60800000Y-80000000D03* 396 | X60000000Y-88000000D03* 397 | X60000000Y-87200000D03* 398 | X60000000Y-86400000D03* 399 | X60000000Y-85600000D03* 400 | X60000000Y-84800000D03* 401 | X60000000Y-84000000D03* 402 | X60000000Y-83200000D03* 403 | X60000000Y-82400000D03* 404 | X60000000Y-81600000D03* 405 | X60000000Y-80800000D03* 406 | X60000000Y-80000000D03* 407 | X59200000Y-88000000D03* 408 | X59200000Y-87200000D03* 409 | X59200000Y-86400000D03* 410 | X59200000Y-85600000D03* 411 | X59200000Y-84800000D03* 412 | X59200000Y-84000000D03* 413 | X59200000Y-83200000D03* 414 | X59200000Y-82400000D03* 415 | X59200000Y-81600000D03* 416 | X59200000Y-80800000D03* 417 | X59200000Y-80000000D03* 418 | X58400000Y-88000000D03* 419 | X58400000Y-87200000D03* 420 | X58400000Y-86400000D03* 421 | X58400000Y-85600000D03* 422 | X58400000Y-84800000D03* 423 | X58400000Y-84000000D03* 424 | X58400000Y-83200000D03* 425 | X58400000Y-82400000D03* 426 | X58400000Y-81600000D03* 427 | X58400000Y-80800000D03* 428 | X58400000Y-80000000D03* 429 | X57600000Y-88000000D03* 430 | X57600000Y-87200000D03* 431 | X57600000Y-86400000D03* 432 | X57600000Y-85600000D03* 433 | X57600000Y-84800000D03* 434 | X57600000Y-84000000D03* 435 | X57600000Y-83200000D03* 436 | X57600000Y-82400000D03* 437 | X57600000Y-81600000D03* 438 | X57600000Y-80800000D03* 439 | X57600000Y-80000000D03* 440 | X56800000Y-88000000D03* 441 | X56800000Y-87200000D03* 442 | X56800000Y-86400000D03* 443 | X56800000Y-85600000D03* 444 | X56800000Y-84800000D03* 445 | X56800000Y-84000000D03* 446 | X56800000Y-83200000D03* 447 | X56800000Y-82400000D03* 448 | X56800000Y-81600000D03* 449 | X56800000Y-80800000D03* 450 | X56800000Y-80000000D03* 451 | X56000000Y-88000000D03* 452 | X56000000Y-87200000D03* 453 | X56000000Y-86400000D03* 454 | X56000000Y-85600000D03* 455 | X56000000Y-84800000D03* 456 | X56000000Y-84000000D03* 457 | X56000000Y-83200000D03* 458 | X56000000Y-82400000D03* 459 | X56000000Y-81600000D03* 460 | X56000000Y-80800000D03* 461 | X56000000Y-80000000D03* 462 | G04 #@! TD* 463 | M02* 464 | -------------------------------------------------------------------------------- /hardware/proto-sensor/gerber/proto-sensor-NPTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Tue 27 Nov 2018 01:39:06 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.0394 7 | T2C0.1280 8 | % 9 | G90 10 | G05 11 | T1 12 | X2.4011Y-3.6283 13 | X2.4411Y-3.8283 14 | X2.4811Y-3.6283 15 | T2 16 | X2.1122Y-2.1654 17 | X2.6122Y-2.1654 18 | T0 19 | M30 20 | -------------------------------------------------------------------------------- /hardware/proto-sensor/gerber/proto-sensor-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Tue 27 Nov 2018 01:39:06 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.0100 7 | T2C0.0118 8 | T3C0.0157 9 | T4C0.0250 10 | T5C0.0354 11 | T6C0.0394 12 | T7C0.0472 13 | T8C0.0620 14 | T9C0.0866 15 | % 16 | G90 17 | G05 18 | T1 19 | X2.2835Y-3.2283 20 | X2.2835Y-3.2913 21 | X2.2835Y-3.3228 22 | X2.2835Y-3.3858 23 | X2.3465Y-3.2913 24 | X2.3465Y-3.3228 25 | X2.3465Y-3.3543 26 | X2.378Y-3.2283 27 | X2.378Y-3.2913 28 | X2.378Y-3.3228 29 | X2.378Y-3.3858 30 | X2.4094Y-3.2913 31 | X2.4094Y-3.3858 32 | X2.4409Y-3.2598 33 | X2.4724Y-3.1969 34 | X2.501Y-3.4783 35 | X2.5079Y-3.3583 36 | X2.561Y-3.4547 37 | X2.6654Y-3.4528 38 | X2.7047Y-3.3917 39 | T2 40 | X1.9961Y-3.2677 41 | X1.9961Y-3.3701 42 | X2.0079Y-2.4016 43 | X2.0079Y-2.5394 44 | X2.0079Y-2.9528 45 | X2.0079Y-3.0315 46 | X2.0079Y-3.5827 47 | X2.0079Y-3.6614 48 | X2.0079Y-3.7402 49 | X2.0079Y-3.8189 50 | X2.0079Y-3.8976 51 | X2.0079Y-3.9764 52 | X2.0079Y-4.0551 53 | X2.0079Y-4.1339 54 | X2.0079Y-4.2126 55 | X2.0079Y-4.2913 56 | X2.0079Y-4.3701 57 | X2.0079Y-4.4488 58 | X2.0079Y-4.5276 59 | X2.0079Y-4.6063 60 | X2.0079Y-4.685 61 | X2.0315Y-2.6122 62 | X2.0394Y-3.4803 63 | X2.0433Y-3.3661 64 | X2.0591Y-3.5197 65 | X2.0591Y-3.5551 66 | X2.0669Y-2.7874 67 | X2.0669Y-2.8465 68 | X2.0669Y-2.9055 69 | X2.0866Y-2.9528 70 | X2.0866Y-4.685 71 | X2.0965Y-2.6575 72 | X2.0965Y-2.7461 73 | X2.1024Y-3.063 74 | X2.1063Y-2.8543 75 | X2.1161Y-2.2638 76 | X2.1201Y-3.6614 77 | X2.1378Y-3.063 78 | X2.1614Y-3.1575 79 | X2.1654Y-3.7402 80 | X2.1654Y-3.8189 81 | X2.1654Y-3.8976 82 | X2.1654Y-3.9764 83 | X2.1654Y-4.685 84 | X2.1713Y-3.5177 85 | X2.1713Y-3.5531 86 | X2.1732Y-3.3386 87 | X2.1732Y-4.1102 88 | X2.1752Y-2.313 89 | X2.1831Y-2.5807 90 | X2.1831Y-2.687 91 | X2.2323Y-4.0276 92 | X2.2323Y-4.063 93 | X2.2441Y-3.8976 94 | X2.2441Y-4.685 95 | X2.2598Y-2.5512 96 | X2.2638Y-2.2146 97 | X2.2835Y-3.9764 98 | X2.3189Y-2.6575 99 | X2.3228Y-4.685 100 | X2.3425Y-3.563 101 | X2.3425Y-3.622 102 | X2.3425Y-3.6909 103 | X2.3465Y-2.872 104 | X2.3465Y-2.9045 105 | X2.3465Y-2.9291 106 | X2.3504Y-2.6181 107 | X2.4016Y-4.685 108 | X2.4213Y-2.4311 109 | X2.4213Y-2.5866 110 | X2.4291Y-2.872 111 | X2.4409Y-4.0551 112 | X2.4429Y-2.9705 113 | X2.4606Y-3.563 114 | X2.4646Y-3.8937 115 | X2.4803Y-4.685 116 | X2.4823Y-2.878 117 | X2.4882Y-3.1181 118 | X2.4902Y-2.5 119 | X2.4961Y-3.9646 120 | X2.5Y-3.5354 121 | X2.5059Y-3.8189 122 | X2.5079Y-2.9154 123 | X2.5197Y-3.1181 124 | X2.5236Y-3.6772 125 | X2.5315Y-3.5433 126 | X2.5386Y-3.7047 127 | X2.5394Y-3.6024 128 | X2.5472Y-2.9685 129 | X2.5512Y-3.3268 130 | X2.5512Y-3.3583 131 | X2.5512Y-4.1102 132 | X2.5551Y-3.1575 133 | X2.5551Y-3.1969 134 | X2.5551Y-3.2402 135 | X2.5551Y-3.2717 136 | X2.5591Y-4.685 137 | X2.5709Y-3.7008 138 | X2.5748Y-2.9961 139 | X2.5748Y-3.4961 140 | X2.5886Y-2.4311 141 | X2.5984Y-2.3228 142 | X2.5984Y-2.9409 143 | X2.5984Y-3.0512 144 | X2.6063Y-2.7402 145 | X2.6083Y-2.2539 146 | X2.622Y-3.4685 147 | X2.6378Y-3.3937 148 | X2.6378Y-4.685 149 | X2.6457Y-3.4882 150 | X2.6496Y-3.6024 151 | X2.6654Y-3.4134 152 | X2.6969Y-2.6142 153 | X2.7126Y-3.2756 154 | X2.7165Y-2.4016 155 | X2.7165Y-2.5394 156 | X2.7165Y-3.6614 157 | X2.7165Y-3.7402 158 | X2.7165Y-3.8189 159 | X2.7165Y-3.8976 160 | X2.7165Y-3.9764 161 | X2.7165Y-4.0551 162 | X2.7165Y-4.1339 163 | X2.7165Y-4.2126 164 | X2.7165Y-4.2913 165 | X2.7165Y-4.3701 166 | X2.7165Y-4.4488 167 | X2.7165Y-4.5276 168 | X2.7165Y-4.6063 169 | X2.7165Y-4.685 170 | X2.7264Y-2.9134 171 | X2.7264Y-3.0413 172 | X2.7264Y-3.4882 173 | X2.7283Y-3.126 174 | X2.7283Y-3.2283 175 | X2.7323Y-3.5984 176 | X2.7362Y-3.2953 177 | T3 178 | X2.4764Y-2.5551 179 | X2.5276Y-2.8937 180 | X2.5866Y-2.6181 181 | T4 182 | X2.6167Y-3.6992 183 | X2.6167Y-3.7492 184 | X2.6167Y-3.7992 185 | X2.6167Y-3.8492 186 | X2.6167Y-3.8992 187 | X2.6667Y-3.6992 188 | X2.6667Y-3.7492 189 | X2.6667Y-3.7992 190 | X2.6667Y-3.8492 191 | X2.6667Y-3.8992 192 | T5 193 | X2.0922Y-2.5254 194 | X2.1822Y-2.5254 195 | X2.2222Y-2.2654 196 | X2.2622Y-2.3354 197 | X2.3022Y-2.2654 198 | X2.3422Y-2.3354 199 | X2.3822Y-2.2654 200 | X2.4222Y-2.3354 201 | X2.4622Y-2.2654 202 | X2.5022Y-2.3354 203 | X2.5422Y-2.5254 204 | X2.6322Y-2.5254 205 | T6 206 | X2.0295Y-2.6969 207 | T7 208 | X2.3622Y-4.4094 209 | T8 210 | X2.0422Y-2.3004 211 | X2.6822Y-2.3004 212 | T9 213 | X2.2323Y-4.2795 214 | X2.2323Y-4.5394 215 | X2.4921Y-4.2795 216 | X2.4921Y-4.5394 217 | T0 218 | M30 219 | -------------------------------------------------------------------------------- /hardware/proto-sensor/gerber/proto-sensor.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/gerber/proto-sensor.zip -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor-pcb-back.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/proto-sensor-pcb-back.png -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor-pcb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/proto-sensor-pcb.png -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor.bom: -------------------------------------------------------------------------------- 1 | Bill Of Materials 2 | ================= 3 | 4 | Source file: proto-sensor.xml 5 | Date: 2018-11-29T20:35:01.680405 6 | 7 | Parts Missing Footprints 8 | ------------------------ 9 | 10 | 11 | Parts Missing Order Codes 12 | ------------------------- 13 | R18 DNF agg:0402 14 | R17 DNF agg:0402 15 | J2 ~ agg:TC2030-NL 16 | TP1 TESTPAD agg:TESTPAD 17 | TP3 TESTPAD agg:TESTPAD 18 | TP2 TESTPAD agg:TESTPAD 19 | J3 GND agg:SIL-254P-01 20 | 21 | Inconsistent Order Codes 22 | ------------------------ 23 | Voltage Rating 24 | ~~~~~~~~~~~~~~ 25 | 50: 26 | R1 1k agg:0402 27 | R5 140 agg:0402 28 | R4 140 agg:0402 29 | R6 140 agg:0402 30 | R2 100 agg:0402 31 | R8 100 agg:0402 32 | R7 100 agg:0402 33 | R13 10k agg:0402 34 | R12 10k agg:0402 35 | R16 10k agg:0402 36 | C4 10n agg:0402 37 | C3 10n agg:0402 38 | C10 10n agg:0402 39 | C11 10n agg:0402 40 | C12 10n agg:0402 41 | C6 10n agg:0402 42 | C17 100n 48V agg:0603 43 | R15 10k agg:0402 44 | R14 10k agg:0402 45 | C16 0µ47 48V agg:0603 46 | R19 100 agg:0402 47 | C27 10n agg:0402 48 | C29 10n agg:0402 49 | R20 10k agg:0402 50 | R21 10k agg:0402 51 | 52 | Vendor Specific BOMs 53 | -------------------- 54 | DigiKey 55 | ~~~~~~~ 56 | 1,220-2148-ND,1x iCE40HX8K-BG121 Lattice-BG121 IC4 57 | 1,W25Q80DVUXIECT-ND,1x W25Q80 UFDFN-8 IC5 58 | 1,MAX15062AATA+TCT-ND,1x MAX15062 TDFN-8 IC2 59 | 60 | 61 | Farnell 62 | ~~~~~~~ 63 | 2331474,5,5x 1k 0402 64 | 1462758,1,1x RJHSE-538x RJHSE-538X 65 | 2302541,3,3x 140 0402 66 | 9239111,4,4x 100 0402 67 | 1248952,1,1x COAX BNC_PCB_RA_5-1634556-0 68 | 2810260,15,15x 100n 0402 69 | 2611921,3,3x 10µ 0603 70 | 2302739,7,7x 10k 0402 71 | 2470416,8,8x 10n 0402 72 | 431989,1,1x 100n 48V 0603 73 | 2290328,2,2x LED 0603-LED 74 | 2516650,1,1x MAX15062 TDFN-8 75 | 1458896,2,2x 1µ 0402 76 | 2211183,1,1x 0µ47 48V 0603 77 | 2408110,1,1x 33µ LPS4018 78 | 2856426,1,1x ~ FTSH-105-01-F-D-K 79 | 2290329,1,1x LED 0603-LED 80 | 2849479,1,1x 25M XTAL-25x20 81 | 2845744,3,3x ~ KSR232G 82 | 1851940,1,1x MCP1700 SOT-23 83 | 2513633,1,1x MAX11665AUT SOT-23-6 84 | 2368169,1,1x ESD_DIODE 0402 85 | 2462664,1,1x ECMF04-4HSM10 uQFN-10L 86 | 87 | 88 | Voltage Rating 89 | ~~~~~~~~~~~~~~ 90 | 50,29,29x R1 R3 R5 R4 R6 R2 R8 R7 R13 R12 R16 C4 C3 C10 C11 C12 C6 C17 R15 R14 R9 R10 C16 R11 R19 C27 C29 R20 R21 0402,0603 91 | 16,15,15x C20 C14 C2 C1 C8 C7 C9 C5 C28 C23 C26 C21 C25 C24 C30 0402 92 | 6.3,3,3x C19 C13 C15 0603 93 | 10,2,2x C18 C22 0402 94 | 95 | 96 | Assembly BOM 97 | ------------ 98 | 220-2148-ND 1 iCE40HX8K-BG121 Lattice-BG121 IC4 99 | W25Q80DVUXIECT-ND 1 W25Q80 UFDFN-8 IC5 100 | MAX15062AATA+TCT-ND 1 MAX15062 TDFN-8 IC2 101 | 2331474 5 1k 0402 R1 R10 R11 R3 R9 102 | 1462758 1 RJHSE-538x RJHSE-538X IC1 103 | 2302541 3 140 0402 R4 R5 R6 104 | 9239111 4 100 0402 R19 R2 R7 R8 105 | 1248952 1 COAX BNC_PCB_RA_5-1634556-0 P1 106 | 2810260 15 100n 0402 C1 C14 C2 C20 C21 C23 C24 C25 C26 C28 C30 C5 C7 C8 C9 107 | 2611921 3 10µ 0603 C13 C15 C19 108 | 2302739 7 10k 0402 R12 R13 R14 R15 R16 R20 R21 109 | 2470416 8 10n 0402 C10 C11 C12 C27 C29 C3 C4 C6 110 | 431989 1 100n 48V 0603 C17 111 | 2290328 2 LED 0603-LED D1 D2 112 | 2516650 1 MAX15062 TDFN-8 IC2 113 | 1458896 2 1µ 0402 C18 C22 114 | 2211183 1 0µ47 48V 0603 C16 115 | 2408110 1 33µ LPS4018 L1 116 | 2856426 1 ~ FTSH-105-01-F-D-K J1 117 | 2290329 1 LED 0603-LED D3 118 | 2849479 1 25M XTAL-25x20 Y1 119 | 2845744 3 ~ KSR232G SW1 SW2 SW3 120 | 1851940 1 MCP1700 SOT-23 IC3 121 | 2513633 1 MAX11665AUT SOT-23-6 IC6 122 | 2368169 1 ESD_DIODE 0402 D4 123 | 2462664 1 ECMF04-4HSM10 uQFN-10L IC7 124 | 50 29 10n,10k,140,100,0µ47 48V,100n 48V,1k 0402,0603 C10 C11 C12 C16 C17 C27 C29 C3 C4 C6 R1 R10 R11 R12 R13 R14 R15 R16 R19 R2 R20 R21 R3 R4 R5 R6 R7 R8 R9 125 | 16 15 100n 0402 C1 C14 C2 C20 C21 C23 C24 C25 C26 C28 C30 C5 C7 C8 C9 126 | 6.3 3 10µ 0603 C13 C15 C19 127 | 10 2 1µ 0402 C18 C22 128 | 129 | -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/proto-sensor.pdf -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/proto-sensor.png -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor.pro: -------------------------------------------------------------------------------- 1 | update=Tue 15 Jan 2019 20:25:00 GMT 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [pcbnew] 16 | version=1 17 | PageLayoutDescrFile= 18 | LastNetListRead= 19 | CopperLayerCount=4 20 | BoardThickness=1.6 21 | AllowMicroVias=0 22 | AllowBlindVias=0 23 | RequireCourtyardDefinitions=0 24 | ProhibitOverlappingCourtyards=1 25 | MinTrackWidth=0.127 26 | MinViaDiameter=0.4572 27 | MinViaDrill=0.254 28 | MinMicroViaDiameter=0.2 29 | MinMicroViaDrill=0.09999999999999999 30 | MinHoleToHole=0.25 31 | TrackWidth1=0.127 32 | TrackWidth2=0.127 33 | TrackWidth3=0.15 34 | TrackWidth4=0.2 35 | TrackWidth5=0.4 36 | TrackWidth6=0.6 37 | ViaDiameter1=0.4572 38 | ViaDrill1=0.254 39 | ViaDiameter2=0.4572 40 | ViaDrill2=0.254 41 | ViaDiameter3=0.6 42 | ViaDrill3=0.3 43 | ViaDiameter4=0.8 44 | ViaDrill4=0.4 45 | dPairWidth1=0.15 46 | dPairGap1=0.15 47 | dPairViaGap1=0.25 48 | dPairWidth2=0.127 49 | dPairGap2=0.127 50 | dPairViaGap2=0 51 | SilkLineWidth=0.12 52 | SilkTextSizeV=1 53 | SilkTextSizeH=1 54 | SilkTextSizeThickness=0.15 55 | SilkTextItalic=0 56 | SilkTextUpright=1 57 | CopperLineWidth=0.2 58 | CopperTextSizeV=1.5 59 | CopperTextSizeH=1.5 60 | CopperTextThickness=0.3 61 | CopperTextItalic=0 62 | CopperTextUpright=1 63 | EdgeCutLineWidth=0.05 64 | CourtyardLineWidth=0.05 65 | OthersLineWidth=0.15 66 | OthersTextSizeV=1 67 | OthersTextSizeH=1 68 | OthersTextSizeThickness=0.15 69 | OthersTextItalic=0 70 | OthersTextUpright=1 71 | SolderMaskClearance=0.02 72 | SolderMaskMinWidth=0.05 73 | SolderPasteClearance=0 74 | SolderPasteRatio=-0 75 | [pcbnew/Layer.In1.Cu] 76 | Name=In1.Cu 77 | Type=1 78 | [pcbnew/Layer.In2.Cu] 79 | Name=In2.Cu 80 | Type=1 81 | -------------------------------------------------------------------------------- /hardware/proto-sensor/proto-sensor_bom.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-sensor/proto-sensor_bom.pdf -------------------------------------------------------------------------------- /hardware/proto-sensor/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name agg)(type Legacy)(uri "$(KIPRJMOD)/../agg-kicad/agg-kicad.lib")(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /hardware/proto-switch/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name agg)(type KiCad)(uri "$(KIPRJMOD)/../agg-kicad/agg.pretty")(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /hardware/proto-switch/gerber/proto-switch-B.Paste.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:39:18+00:00* 3 | G04 #@! TF.ProjectId,proto-switch,70726f74-6f2d-4737-9769-7463682e6b69,1* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Paste,Bot* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1) date Tue 27 Nov 2018 01:39:18 GMT* 10 | %MOMM*% 11 | %LPD*% 12 | G01* 13 | G04 APERTURE LIST* 14 | G04 APERTURE END LIST* 15 | M02* 16 | -------------------------------------------------------------------------------- /hardware/proto-switch/gerber/proto-switch-B.SilkS.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:39:18+00:00* 3 | G04 #@! TF.ProjectId,proto-switch,70726f74-6f2d-4737-9769-7463682e6b69,1* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Legend,Bot* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1) date Tue 27 Nov 2018 01:39:18 GMT* 10 | %MOMM*% 11 | %LPD*% 12 | G01* 13 | G04 APERTURE LIST* 14 | G04 APERTURE END LIST* 15 | M02* 16 | -------------------------------------------------------------------------------- /hardware/proto-switch/gerber/proto-switch-Edge.Cuts.gbr: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:39:18+00:00* 3 | G04 #@! TF.ProjectId,proto-switch,70726f74-6f2d-4737-9769-7463682e6b69,1* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Profile,NP* 6 | %FSLAX46Y46*% 7 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 8 | G04 Created by KiCad (PCBNEW 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1) date Tue 27 Nov 2018 01:39:18 GMT* 9 | %MOMM*% 10 | %LPD*% 11 | G01* 12 | G04 APERTURE LIST* 13 | %ADD10C,0.050000*% 14 | G04 APERTURE END LIST* 15 | D10* 16 | X80000000Y-119000000D02* 17 | G75* 18 | G02X81000000Y-118000000I1000000J0D01* 19 | G01* 20 | X81000000Y-160000000D02* 21 | G75* 22 | G02X80000000Y-159000000I0J1000000D01* 23 | G01* 24 | X192000000Y-159000000D02* 25 | G75* 26 | G02X191000000Y-160000000I-1000000J0D01* 27 | G01* 28 | X191000000Y-118000000D02* 29 | G75* 30 | G02X192000000Y-119000000I0J-1000000D01* 31 | G01* 32 | X80000000Y-119000000D02* 33 | X80000000Y-159000000D01* 34 | X191000000Y-118000000D02* 35 | X81000000Y-118000000D01* 36 | X192000000Y-159000000D02* 37 | X192000000Y-119000000D01* 38 | X81000000Y-160000000D02* 39 | X191000000Y-160000000D01* 40 | M02* 41 | -------------------------------------------------------------------------------- /hardware/proto-switch/gerber/proto-switch-NPTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Tue 27 Nov 2018 01:39:19 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.0236 7 | T2C0.1280 8 | T3C0.1299 9 | % 10 | G90 11 | G05 12 | T1 13 | X7.3031Y-6.1417 14 | X7.3307Y-6.0709 15 | X7.3307Y-6.2126 16 | X7.4016Y-6.0433 17 | X7.4016Y-6.2402 18 | X7.4724Y-6.0709 19 | X7.4724Y-6.2126 20 | X7.5Y-6.1417 21 | X7.3031Y-4.8031 22 | X7.3307Y-4.7323 23 | X7.3307Y-4.874 24 | X7.4016Y-4.7047 25 | X7.4016Y-4.9016 26 | X7.4724Y-4.7323 27 | X7.4724Y-4.874 28 | X7.5Y-4.8031 29 | X3.2087Y-6.1417 30 | X3.2362Y-6.0709 31 | X3.2362Y-6.2126 32 | X3.3071Y-6.0433 33 | X3.3071Y-6.2402 34 | X3.378Y-6.0709 35 | X3.378Y-6.2126 36 | X3.4055Y-6.1417 37 | X3.2087Y-4.8031 38 | X3.2362Y-4.7323 39 | X3.2362Y-4.874 40 | X3.3071Y-4.7047 41 | X3.3071Y-4.9016 42 | X3.378Y-4.7323 43 | X3.378Y-4.874 44 | X3.4055Y-4.8031 45 | T2 46 | X6.565Y-6.0827 47 | X7.065Y-6.0827 48 | X3.6035Y-6.0827 49 | X5.9633Y-6.0827 50 | T3 51 | X7.4016Y-6.1417 52 | X7.4016Y-4.8031 53 | X3.3071Y-6.1417 54 | X3.3071Y-4.8031 55 | T0 56 | M30 57 | -------------------------------------------------------------------------------- /hardware/proto-switch/gerber/proto-switch-PTH.drl: -------------------------------------------------------------------------------- 1 | M48 2 | ;DRILL file {KiCad 6.0.0-rc1-unknown-106eaaa~84~ubuntu18.04.1} date Tue 27 Nov 2018 01:39:19 GMT 3 | ;FORMAT={-:-/ absolute / inch / decimal} 4 | FMAT,2 5 | INCH 6 | T1C0.0100 7 | T2C0.0118 8 | T3C0.0138 9 | T4C0.0157 10 | T5C0.0250 11 | T6C0.0315 12 | T7C0.0354 13 | T8C0.0394 14 | T9C0.0620 15 | % 16 | G90 17 | G05 18 | T1 19 | X4.6732Y-5.0551 20 | X4.6732Y-5.0866 21 | X4.7047Y-4.8661 22 | X4.7047Y-5.0551 23 | X4.7047Y-5.0866 24 | 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X3.9567Y-5.5709 167 | X4.0157Y-5.1575 168 | X4.0551Y-6.0039 169 | X4.0551Y-6.2598 170 | X4.1102Y-5.4173 171 | X4.2126Y-5.1575 172 | X4.252Y-6.2598 173 | X4.3071Y-4.748 174 | X4.3228Y-5.4173 175 | X4.4134Y-5.1417 176 | X4.4134Y-5.315 177 | X4.4488Y-6.2598 178 | X4.4882Y-5.3346 179 | X4.5236Y-5.5354 180 | X4.6457Y-6.2598 181 | X4.6772Y-6.0 182 | X4.7638Y-5.4331 183 | X4.8425Y-6.2598 184 | X4.8937Y-5.5591 185 | X5.0394Y-6.2598 186 | X5.1339Y-5.4213 187 | X5.2362Y-4.685 188 | X5.2362Y-6.2598 189 | X5.2953Y-5.1772 190 | X5.2953Y-6.0039 191 | X5.4331Y-4.685 192 | X5.4331Y-6.2598 193 | X5.5709Y-5.4213 194 | X5.6299Y-6.2598 195 | X5.6496Y-5.563 196 | X5.7402Y-5.4488 197 | X5.8268Y-4.685 198 | X5.8268Y-6.2598 199 | X6.0236Y-6.2598 200 | X6.4449Y-5.7677 201 | X6.4449Y-5.8504 202 | X6.5394Y-5.0984 203 | X6.6339Y-4.7717 204 | X6.685Y-5.6417 205 | X6.8937Y-4.7087 206 | X6.937Y-5.6417 207 | X7.0945Y-4.7087 208 | X7.1024Y-5.1772 209 | X7.189Y-5.5866 210 | X7.189Y-5.689 211 | X7.189Y-5.7992 212 | X7.2047Y-4.7244 213 | X7.2165Y-5.185 214 | X7.2165Y-5.2992 215 | X7.2402Y-5.9488 216 | X7.4843Y-5.6299 217 | X7.4843Y-5.7598 218 | T5 219 | X5.2917Y-4.7531 220 | X5.2917Y-4.8031 221 | X5.3417Y-4.7531 222 | X5.3417Y-4.8031 223 | X5.3917Y-4.7531 224 | X5.3917Y-4.8031 225 | X5.4417Y-4.7531 226 | X5.4417Y-4.8031 227 | X5.4917Y-4.7531 228 | X5.4917Y-4.8031 229 | T6 230 | X5.7524Y-5.187 231 | X5.8524Y-5.187 232 | X5.9524Y-5.187 233 | X6.0524Y-5.187 234 | X6.2524Y-5.187 235 | X6.3524Y-5.187 236 | X6.4524Y-5.187 237 | X5.7524Y-4.7933 238 | X5.8524Y-4.7933 239 | X5.9524Y-4.7933 240 | X6.0524Y-4.7933 241 | X6.2524Y-4.7933 242 | X6.3524Y-4.7933 243 | X6.4524Y-4.7933 244 | T7 245 | X6.545Y-5.7227 246 | X6.635Y-5.7227 247 | X6.675Y-5.9127 248 | X6.715Y-5.9827 249 | X6.755Y-5.9127 250 | X6.795Y-5.9827 251 | X6.835Y-5.9127 252 | X6.875Y-5.9827 253 | X6.915Y-5.9127 254 | X6.955Y-5.9827 255 | X6.995Y-5.7227 256 | X7.085Y-5.7227 257 | X3.5835Y-5.7227 258 | X3.6735Y-5.7227 259 | X3.7135Y-5.9127 260 | X3.7535Y-5.9827 261 | X3.7935Y-5.9127 262 | X3.8335Y-5.9827 263 | X3.8735Y-5.9127 264 | X3.9135Y-5.9827 265 | X3.9535Y-5.9127 266 | X3.9935Y-5.9827 267 | X4.0335Y-5.7227 268 | X4.1235Y-5.7227 269 | X4.2035Y-5.7227 270 | X4.2935Y-5.7227 271 | X4.3335Y-5.9127 272 | X4.3735Y-5.9827 273 | X4.4135Y-5.9127 274 | X4.4535Y-5.9827 275 | X4.4935Y-5.9127 276 | X4.5335Y-5.9827 277 | X4.5735Y-5.9127 278 | X4.6135Y-5.9827 279 | X4.6535Y-5.7227 280 | X4.7435Y-5.7227 281 | X4.8236Y-5.7227 282 | X4.9136Y-5.7227 283 | X4.9536Y-5.9127 284 | X4.9936Y-5.9827 285 | X5.0336Y-5.9127 286 | X5.0736Y-5.9827 287 | X5.1136Y-5.9127 288 | X5.1536Y-5.9827 289 | X5.1936Y-5.9127 290 | X5.2336Y-5.9827 291 | X5.2736Y-5.7227 292 | X5.3636Y-5.7227 293 | X5.4437Y-5.7227 294 | X5.5337Y-5.7227 295 | X5.5737Y-5.9127 296 | X5.6137Y-5.9827 297 | X5.6537Y-5.9127 298 | X5.6937Y-5.9827 299 | X5.7337Y-5.9127 300 | X5.7737Y-5.9827 301 | X5.8137Y-5.9127 302 | X5.8537Y-5.9827 303 | X5.8937Y-5.7227 304 | X5.9837Y-5.7227 305 | T8 306 | X3.248Y-5.9252 307 | T9 308 | X6.495Y-5.9477 309 | X7.135Y-5.9477 310 | X3.5335Y-5.9477 311 | X4.4735Y-5.6827 312 | X5.0936Y-5.6827 313 | X6.0335Y-5.9477 314 | T0 315 | M30 316 | -------------------------------------------------------------------------------- /hardware/proto-switch/ports.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:proto-switch-cache 3 | EELAYER 29 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 4 5 8 | Title "" 9 | Date "" 10 | Rev "" 11 | Comp "" 12 | Comment1 "" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | $Comp 18 | L agg:R R? 19 | U 1 1 5C33D9A6 20 | P 4850 1150 21 | F 0 "R?" H 4900 1200 50 0000 C CNN 22 | F 1 "R" H 4900 1100 50 0000 C CNN 23 | F 2 "agg:0402" H 4850 1150 50 0001 C CNN 24 | F 3 "" H 4850 1150 50 0001 C CNN 25 | 1 4850 1150 26 | 1 0 0 -1 27 | $EndComp 28 | $Comp 29 | L agg:RJHSE-538x IC? 30 | U 1 1 5C33D9AD 31 | P 4250 1550 32 | F 0 "IC?" H 3850 2050 50 0000 L CNN 33 | F 1 "RJHSE-538x" H 3850 1050 50 0000 L CNN 34 | F 2 "agg:RJHSE-538X" H 3850 950 50 0001 L CNN 35 | F 3 "http://www.farnell.com/cad/2167247.pdf" H 3850 850 50 0001 L CNN 36 | F 4 "1462758" H 3850 750 50 0001 L CNN "Farnell" 37 | 1 4250 1550 38 | -1 0 0 -1 39 | $EndComp 40 | $Comp 41 | L agg:GND #PWR? 42 | U 1 1 5C33D9B3 43 | P 3600 1150 44 | F 0 "#PWR?" H 3470 1190 50 0001 L CNN 45 | F 1 "GND" H 3600 1050 50 0000 C CNN 46 | F 2 "" H 3600 1150 50 0001 C CNN 47 | F 3 "" H 3600 1150 50 0001 C CNN 48 | 1 3600 1150 49 | 0 1 1 0 50 | $EndComp 51 | Wire Wire Line 52 | 3600 1150 3700 1150 53 | Wire Wire Line 54 | 3750 1250 3700 1250 55 | Wire Wire Line 56 | 3700 1250 3700 1150 57 | Connection ~ 3700 1150 58 | Wire Wire Line 59 | 3700 1150 3750 1150 60 | NoConn ~ 4750 1750 61 | $Comp 62 | L agg:GND #PWR? 63 | U 1 1 5C33D9BF 64 | P 5000 1150 65 | F 0 "#PWR?" H 4870 1190 50 0001 L CNN 66 | F 1 "GND" H 5000 1050 50 0000 C CNN 67 | F 2 "" H 5000 1150 50 0001 C CNN 68 | F 3 "" H 5000 1150 50 0001 C CNN 69 | 1 5000 1150 70 | 0 -1 -1 0 71 | $EndComp 72 | Wire Wire Line 73 | 4850 1150 4750 1150 74 | Wire Wire Line 75 | 4950 1150 5000 1150 76 | $Comp 77 | L agg:R R? 78 | U 1 1 5C33D9C7 79 | P 4850 1450 80 | F 0 "R?" H 4900 1500 50 0000 C CNN 81 | F 1 "R" H 4900 1400 50 0000 C CNN 82 | F 2 "agg:0402" H 4850 1450 50 0001 C CNN 83 | F 3 "" H 4850 1450 50 0001 C CNN 84 | 1 4850 1450 85 | 1 0 0 -1 86 | $EndComp 87 | $Comp 88 | L agg:GND #PWR? 89 | U 1 1 5C33D9CD 90 | P 5000 1450 91 | F 0 "#PWR?" H 4870 1490 50 0001 L CNN 92 | F 1 "GND" H 5000 1350 50 0000 C CNN 93 | F 2 "" H 5000 1450 50 0001 C CNN 94 | F 3 "" H 5000 1450 50 0001 C CNN 95 | 1 5000 1450 96 | 0 -1 -1 0 97 | $EndComp 98 | Wire Wire Line 99 | 4850 1450 4750 1450 100 | Wire Wire Line 101 | 4950 1450 5000 1450 102 | Wire Wire Line 103 | 4750 1250 5250 1250 104 | Wire Wire Line 105 | 4750 1550 5250 1550 106 | Text Label 5250 1250 0 50 ~ 0 107 | LED1_1 108 | Text Label 5250 1550 0 50 ~ 0 109 | LED1_2 110 | Wire Wire Line 111 | 3750 1750 3650 1750 112 | Wire Wire Line 113 | 3750 1850 3650 1850 114 | Wire Wire Line 115 | 3750 1650 3650 1650 116 | Wire Wire Line 117 | 3750 1450 3700 1450 118 | Wire Wire Line 119 | 3750 1550 3700 1550 120 | Wire Wire Line 121 | 3700 1550 3700 1450 122 | Text Label 3150 1800 0 50 ~ 0 123 | TX1+ 124 | Text Label 3150 1700 0 50 ~ 0 125 | TX1- 126 | $Comp 127 | L agg:R R? 128 | U 1 1 5C33D9E1 129 | P 1950 1850 130 | F 0 "R?" H 2000 1900 50 0000 C CNN 131 | F 1 "R" H 2000 1800 50 0000 C CNN 132 | F 2 "agg:0402" H 1950 1850 50 0001 C CNN 133 | F 3 "" H 1950 1850 50 0001 C CNN 134 | 1 1950 1850 135 | 0 1 -1 0 136 | $EndComp 137 | $Comp 138 | L agg:R R? 139 | U 1 1 5C33D9E7 140 | P 1800 1900 141 | F 0 "R?" H 1850 1950 50 0000 C CNN 142 | F 1 "R" H 1850 1850 50 0000 C CNN 143 | F 2 "agg:0402" H 1800 1900 50 0001 C CNN 144 | F 3 "" H 1800 1900 50 0001 C CNN 145 | 1 1800 1900 146 | -1 0 0 1 147 | $EndComp 148 | $Comp 149 | L agg:R R? 150 | U 1 1 5C33D9ED 151 | P 1800 1700 152 | F 0 "R?" H 1850 1750 50 0000 C CNN 153 | F 1 "R" H 1850 1650 50 0000 C CNN 154 | F 2 "agg:0402" H 1800 1700 50 0001 C CNN 155 | F 3 "" H 1800 1700 50 0001 C CNN 156 | 1 1800 1700 157 | -1 0 0 1 158 | $EndComp 159 | Wire Wire Line 160 | 1800 1700 1950 1700 161 | Wire Wire Line 162 | 1950 1750 1950 1700 163 | Wire Wire Line 164 | 1800 1900 1950 1900 165 | Wire Wire Line 166 | 1950 1850 1950 1900 167 | Wire Wire Line 168 | 1700 1700 1550 1700 169 | Wire Wire Line 170 | 1700 1900 1550 1900 171 | Text Label 1550 1900 2 50 ~ 0 172 | TD1+ 173 | Text Label 1550 1700 2 50 ~ 0 174 | TD1- 175 | Text Label 3150 1500 0 50 ~ 0 176 | RX1+ 177 | Text Label 3150 1400 0 50 ~ 0 178 | RX1- 179 | $Comp 180 | L agg:R R? 181 | U 1 1 5C33D9FD 182 | P 1950 1450 183 | F 0 "R?" H 2000 1500 50 0000 C CNN 184 | F 1 "R" H 2000 1400 50 0000 C CNN 185 | F 2 "agg:0402" H 1950 1450 50 0001 C CNN 186 | F 3 "" H 1950 1450 50 0001 C CNN 187 | 1 1950 1450 188 | 0 1 -1 0 189 | $EndComp 190 | Wire Wire Line 191 | 1950 1300 1950 1350 192 | Wire Wire Line 193 | 1950 1450 1950 1500 194 | Wire Wire Line 195 | 1950 1300 1550 1300 196 | Wire Wire Line 197 | 1950 1500 1550 1500 198 | Text Label 1550 1300 2 50 ~ 0 199 | RD1- 200 | Text Label 1550 1500 2 50 ~ 0 201 | RD1+ 202 | Wire Notes Line 203 | 5600 2200 5600 950 204 | Wire Notes Line 205 | 5600 950 1250 950 206 | Wire Notes Line 207 | 1250 950 1250 2200 208 | Wire Notes Line 209 | 1250 2200 5600 2200 210 | Text Label 2300 1900 0 12 ~ 0 211 | TD1ESD+ 212 | Text Label 2300 1700 0 12 ~ 0 213 | TD1ESD- 214 | $Comp 215 | L agg:ECMF04-4HSM10 IC? 216 | U 1 1 5C33DA10 217 | P 2750 1700 218 | F 0 "IC?" H 2550 2100 50 0000 L CNN 219 | F 1 "ECMF04-4HSM10" H 2350 1300 50 0000 L CNN 220 | F 2 "agg:uQFN-10L" H 2550 1200 50 0001 L CNN 221 | F 3 "https://www.st.com/resource/en/datasheet/ecmf04-4hsm10.pdf" H 2550 1100 50 0001 L CNN 222 | F 4 "2462664" H 2550 1000 50 0001 L CNN "Farnell" 223 | 1 2750 1700 224 | -1 0 0 -1 225 | $EndComp 226 | $Comp 227 | L agg:GND #PWR? 228 | U 1 1 5C33DA16 229 | P 3150 2000 230 | F 0 "#PWR?" H 3020 2040 50 0001 L CNN 231 | F 1 "GND" H 3150 1900 50 0000 C CNN 232 | F 2 "" H 3150 2000 50 0001 C CNN 233 | F 3 "" H 3150 2000 50 0001 C CNN 234 | 1 3150 2000 235 | 0 -1 -1 0 236 | $EndComp 237 | Wire Wire Line 238 | 3150 2000 3050 2000 239 | $Comp 240 | L agg:GND #PWR? 241 | U 1 1 5C33DA1D 242 | P 2400 2050 243 | F 0 "#PWR?" H 2270 2090 50 0001 L CNN 244 | F 1 "GND" H 2400 1950 50 0000 C CNN 245 | F 2 "" H 2400 2050 50 0001 C CNN 246 | F 3 "" H 2400 2050 50 0001 C CNN 247 | 1 2400 2050 248 | 1 0 0 -1 249 | $EndComp 250 | Wire Wire Line 251 | 2450 2000 2400 2000 252 | Wire Wire Line 253 | 2400 2000 2400 2050 254 | Wire Wire Line 255 | 2400 1300 2400 1400 256 | Wire Wire Line 257 | 2400 1400 2450 1400 258 | Wire Wire Line 259 | 2400 1900 2400 1800 260 | Wire Wire Line 261 | 2400 1800 2450 1800 262 | Wire Wire Line 263 | 1950 1300 2400 1300 264 | Connection ~ 1950 1300 265 | Wire Wire Line 266 | 2450 1500 1950 1500 267 | Connection ~ 1950 1500 268 | Wire Wire Line 269 | 1950 1700 2450 1700 270 | Connection ~ 1950 1700 271 | Wire Wire Line 272 | 2400 1900 1950 1900 273 | Connection ~ 1950 1900 274 | Wire Wire Line 275 | 3400 1400 3400 1350 276 | Wire Wire Line 277 | 3400 1350 3750 1350 278 | Wire Wire Line 279 | 3050 1400 3400 1400 280 | Wire Wire Line 281 | 3650 1500 3650 1650 282 | Wire Wire Line 283 | 3050 1500 3650 1500 284 | Wire Wire Line 285 | 3650 1700 3650 1750 286 | Wire Wire Line 287 | 3050 1700 3650 1700 288 | Wire Wire Line 289 | 3650 1800 3650 1850 290 | Wire Wire Line 291 | 3050 1800 3650 1800 292 | $EndSCHEMATC 293 | -------------------------------------------------------------------------------- /hardware/proto-switch/proto-switch.bom: -------------------------------------------------------------------------------- 1 | Bill Of Materials 2 | ================= 3 | 4 | Source file: proto-switch.xml 5 | Date: 2018-11-29T20:34:26.684704 6 | 7 | Parts Missing Footprints 8 | ------------------------ 9 | 10 | 11 | Parts Missing Order Codes 12 | ------------------------- 13 | X101 M3_MOUNT agg:M3_MOUNT 14 | X102 M3_MOUNT agg:M3_MOUNT 15 | X104 M3_MOUNT agg:M3_MOUNT 16 | X103 M3_MOUNT agg:M3_MOUNT 17 | J202 UART agg:SM04B-PASS 18 | C309 DNF agg:0805 19 | R312 DNF agg:0603 20 | C310 DNF agg:0805 21 | R313 DNF agg:0603 22 | C311 DNF agg:0805 23 | R314 DNF agg:0603 24 | C312 DNF agg:0805 25 | R315 DNF agg:0603 26 | TP503 TESTPAD agg:TESTPAD 27 | J501 GND agg:SIL-254P-01 28 | TP502 TESTPAD agg:TESTPAD 29 | TP501 TESTPAD agg:TESTPAD 30 | TP505 TESTPAD agg:TESTPAD 31 | TP504 TESTPAD agg:TESTPAD 32 | 33 | Inconsistent Order Codes 34 | ------------------------ 35 | Voltage 36 | ~~~~~~~ 37 | 50: 38 | R205 100 agg:0402 39 | R207 10k agg:0402 40 | R206 10k agg:0402 41 | R211 10k agg:0402 42 | C207 10n agg:0402 43 | C206 10n agg:0402 44 | C213 10n agg:0402 45 | C214 10n agg:0402 46 | C215 10n agg:0402 47 | C216 10n agg:0402 48 | R208 1k agg:0402 49 | R209 1k agg:0402 50 | R210 1k agg:0402 51 | C208 10n agg:0402 52 | R202 10k agg:0402 53 | R201 10k agg:0402 54 | R212 1k agg:0402 55 | R213 1k agg:0402 56 | C307 100n agg:0603 57 | C308 100n agg:0603 58 | R316 24k9 agg:0402 59 | R317 619 agg:0402 60 | R301 33 agg:0402 61 | R302 33 agg:0402 62 | R303 33 agg:0402 63 | R304 33 agg:0402 64 | R308 1k agg:0402 65 | R309 6k49 agg:0402 66 | R311 10k agg:0402 67 | R310 1k agg:0402 68 | R305 33 agg:0402 69 | R306 33 agg:0402 70 | R307 33 agg:0402 71 | R318 1k agg:0402 72 | R417 1k agg:0402 73 | R418 1k agg:0402 74 | R402 140 agg:0402 75 | R401 140 agg:0402 76 | R409 140 agg:0402 77 | R419 1k agg:0402 78 | R420 1k agg:0402 79 | R404 140 agg:0402 80 | R403 140 agg:0402 81 | R411 140 agg:0402 82 | R421 1k agg:0402 83 | R422 1k agg:0402 84 | R406 140 agg:0402 85 | R405 140 agg:0402 86 | R413 140 agg:0402 87 | R423 1k agg:0402 88 | R424 1k agg:0402 89 | R408 140 agg:0402 90 | R407 140 agg:0402 91 | R415 140 agg:0402 92 | R501 1k agg:0402 93 | R502 1k agg:0402 94 | R503 1k agg:0402 95 | 16: 96 | C222 100n agg:0402 97 | C301 22µ agg:1206 98 | C303 22µ agg:1206 99 | 10: 100 | C305 2µ2 agg:0603 101 | C504 1µ agg:0402 102 | 103 | Vendor Specific BOMs 104 | -------------------- 105 | Farnell 106 | ~~~~~~~ 107 | 2810260,18,18x 100n 0402 108 | 2611921,5,5x 10µ 0603 109 | 9239111,6,6x 100 0402 110 | 2302739,6,6x 10k 0402 111 | 2470416,7,7x 10n 0402 112 | 2290328,3,3x LED 0603-LED 113 | 2331474,19,19x 1k 0402 114 | 2290329,1,1x LED 0603-LED 115 | 2856426,1,1x ~ FTSH-105-01-F-D-K 116 | 2849479,2,2x 25M XTAL-25x20 117 | 2845744,1,1x ~ KSR232G 118 | 2368169,2,2x ESD_DIODE 0402 119 | 1462758,1,1x RJHSE-538x RJHSE-538X 120 | 2422553,1,1x 749013011A 749010012A 121 | 9550003,2,2x MB2S TO-269AA 122 | 431989,2,2x 100n 0603 123 | 2514586,1,1x MAX5969x DFN-10-EP-MAX 124 | 1469699,1,1x 24k9 0402 125 | 2302613,1,1x 619 0402 126 | 1899460,1,1x SMAJ58A DO-214AC-SMA 127 | 2496941,1,1x 100n 60V 0805 128 | 2320923,2,2x 22µ 1206 129 | 1463451,2,2x FB 0603 130 | 2320817,1,1x 2µ2 0603 131 | 2302472,7,7x 33 0402 132 | 2302722,1,1x 6k49 0402 133 | 2509802,1,1x KSZ8081RNA QFN-24-EP-MICREL 134 | 2302541,12,12x 140 0402 135 | 2462664,4,4x ECMF04-4HSM10 uQFN-10L 136 | 1860606,1,1x RJHSE-538x-04 RJHSE-538X-04 137 | 1851940,1,1x MCP1700 SOT-23 138 | 1458896,1,1x 1µ 0402 139 | 2854900,1,1x TEC 2-4810 SIP-8-DCDC 140 | 2854905,1,1x TEC 2-4815 SIP-8-DCDC 141 | 2469398,2,2x 10µ 0603 142 | 143 | 144 | Voltage 145 | ~~~~~~~ 146 | 16,20,20x C222 C219 C203 C202 C211 C209 C212 C210 C204 C205 C220 C201 C217 C301 C302 C303 C304 C306 C314 C503 0402,1206 147 | 6.3,5,5x C221 C218 C223 C224 C501 0603 148 | 50,62,62x R205 R204 R207 R206 R211 C207 C206 C213 C214 C215 C216 R208 R209 R210 C208 R202 R201 R212 R213 C307 C308 R316 R317 R301 R302 R303 R304 R308 R309 R311 R310 R305 R306 R307 R318 R417 R418 R410 R402 R401 R409 R419 R420 R412 R404 R403 R411 R421 R422 R414 R406 R405 R413 R423 R424 R416 R408 R407 R415 R501 R502 R503 0402,0603 149 | 10,2,2x C305 C504 0402,0603 150 | 25,2,2x C502 C505 0603 151 | 152 | 153 | DigiKey 154 | ~~~~~~~ 155 | 1,W25Q80DVUXIECT-ND,1x W25Q80 UFDFN-8 IC201 156 | 1,220-2148-ND,1x iCE40HX8K-BG121 Lattice-BG121 IC202 157 | 158 | 159 | Assembly BOM 160 | ------------ 161 | 2810260 18 100n 0402 C201 C202 C203 C204 C205 C209 C210 C211 C212 C217 C219 C220 C222 C302 C304 C306 C314 C503 162 | 2611921 5 10µ 0603 C218 C221 C223 C224 C501 163 | 9239111 6 100 0402 R204 R205 R410 R412 R414 R416 164 | 2302739 6 10k 0402 R201 R202 R206 R207 R211 R311 165 | 2470416 7 10n 0402 C206 C207 C208 C213 C214 C215 C216 166 | 2290328 3 LED 0603-LED D201 D202 D501 167 | 2331474 19 1k 0402 R208 R209 R210 R212 R213 R308 R310 R318 R417 R418 R419 R420 R421 R422 R423 R424 R501 R502 R503 168 | 2290329 1 LED 0603-LED D203 169 | 2856426 1 ~ FTSH-105-01-F-D-K J201 170 | 2849479 2 25M XTAL-25x20 Y201 Y301 171 | 2845744 1 ~ KSR232G SW201 172 | 2368169 2 ESD_DIODE 0402 D204 D205 173 | 1462758 1 RJHSE-538x RJHSE-538X J302 174 | 2422553 1 749013011A 749010012A T301 175 | 9550003 2 MB2S TO-269AA D302 D303 176 | 431989 2 100n 0603 C307 C308 177 | 2514586 1 MAX5969x DFN-10-EP-MAX IC303 178 | 1469699 1 24k9 0402 R316 179 | 2302613 1 619 0402 R317 180 | 1899460 1 SMAJ58A DO-214AC-SMA D301 181 | 2496941 1 100n 60V 0805 C313 182 | 2320923 2 22µ 1206 C301 C303 183 | 1463451 2 FB 0603 L301 L302 184 | 2320817 1 2µ2 0603 C305 185 | 2302472 7 33 0402 R301 R302 R303 R304 R305 R306 R307 186 | 2302722 1 6k49 0402 R309 187 | 2509802 1 KSZ8081RNA QFN-24-EP-MICREL IC301 188 | 2302541 12 140 0402 R401 R402 R403 R404 R405 R406 R407 R408 R409 R411 R413 R415 189 | 2462664 4 ECMF04-4HSM10 uQFN-10L IC401 IC402 IC403 IC404 190 | 1860606 1 RJHSE-538x-04 RJHSE-538X-04 J401 191 | 1851940 1 MCP1700 SOT-23 IC502 192 | 1458896 1 1µ 0402 C504 193 | 2854900 1 TEC 2-4810 SIP-8-DCDC IC501 194 | 2854905 1 TEC 2-4815 SIP-8-DCDC IC503 195 | 2469398 2 10µ 0603 C502 C505 196 | 16 20 22µ,100n 0402,1206 C201 C202 C203 C204 C205 C209 C210 C211 C212 C217 C219 C220 C222 C301 C302 C303 C304 C306 C314 C503 197 | 6.3 5 10µ 0603 C218 C221 C223 C224 C501 198 | 50 62 33,140,1k,100n,10n,6k49,10k,100,619,24k9 0402,0603 C206 C207 C208 C213 C214 C215 C216 C307 C308 R201 R202 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 R311 R316 R317 R318 R401 R402 R403 R404 R405 R406 R407 R408 R409 R410 R411 R412 R413 R414 R415 R416 R417 R418 R419 R420 R421 R422 R423 R424 R501 R502 R503 199 | 10 2 1µ,2µ2 0402,0603 C305 C504 200 | 25 2 10µ 0603 C502 C505 201 | W25Q80DVUXIECT-ND 1 W25Q80 UFDFN-8 IC201 202 | 220-2148-ND 1 iCE40HX8K-BG121 Lattice-BG121 IC202 203 | 204 | -------------------------------------------------------------------------------- /hardware/proto-switch/proto-switch.pro: -------------------------------------------------------------------------------- 1 | update=Tue 15 Jan 2019 20:24:45 GMT 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [pcbnew] 16 | version=1 17 | PageLayoutDescrFile= 18 | LastNetListRead= 19 | CopperLayerCount=4 20 | BoardThickness=1.6 21 | AllowMicroVias=0 22 | AllowBlindVias=0 23 | RequireCourtyardDefinitions=0 24 | ProhibitOverlappingCourtyards=1 25 | MinTrackWidth=0.127 26 | MinViaDiameter=0.4572 27 | MinViaDrill=0.254 28 | MinMicroViaDiameter=0.2 29 | MinMicroViaDrill=0.09999999999999999 30 | MinHoleToHole=0.25 31 | TrackWidth1=0.15 32 | TrackWidth2=0.127 33 | TrackWidth3=0.15 34 | TrackWidth4=0.2 35 | TrackWidth5=0.4 36 | TrackWidth6=0.6 37 | TrackWidth7=1 38 | ViaDiameter1=0.6 39 | ViaDrill1=0.3 40 | ViaDiameter2=0.4572 41 | ViaDrill2=0.254 42 | ViaDiameter3=0.6 43 | ViaDrill3=0.3 44 | ViaDiameter4=0.8 45 | ViaDrill4=0.4 46 | dPairWidth1=0.15 47 | dPairGap1=0.15 48 | dPairViaGap1=0.25 49 | dPairWidth2=0.15 50 | dPairGap2=0.15 51 | dPairViaGap2=0 52 | SilkLineWidth=0.15 53 | SilkTextSizeV=1 54 | SilkTextSizeH=1 55 | SilkTextSizeThickness=0.15 56 | SilkTextItalic=0 57 | SilkTextUpright=1 58 | CopperLineWidth=0.2 59 | CopperTextSizeV=1.5 60 | CopperTextSizeH=1.5 61 | CopperTextThickness=0.3 62 | CopperTextItalic=0 63 | CopperTextUpright=1 64 | EdgeCutLineWidth=0.05 65 | CourtyardLineWidth=0.05 66 | OthersLineWidth=0.15 67 | OthersTextSizeV=1 68 | OthersTextSizeH=1 69 | OthersTextSizeThickness=0.15 70 | OthersTextItalic=0 71 | OthersTextUpright=1 72 | SolderMaskClearance=0.02 73 | SolderMaskMinWidth=0.05 74 | SolderPasteClearance=0 75 | SolderPasteRatio=-0 76 | [pcbnew/Layer.In1.Cu] 77 | Name=In1.Cu 78 | Type=1 79 | [pcbnew/Layer.In2.Cu] 80 | Name=In2.Cu 81 | Type=1 82 | -------------------------------------------------------------------------------- /hardware/proto-switch/proto-switch.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:proto-switch-cache 3 | EELAYER 29 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 1 5 8 | Title "DAQnet Switch Prototype" 9 | Date "2018-11-24" 10 | Rev "1" 11 | Comp "" 12 | Comment1 "Drawn by: Adam Greig" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | $Sheet 18 | S 4550 3000 850 2650 19 | U 5C2ED715 20 | F0 "iCE40" 50 21 | F1 "ice40.sch" 50 22 | F2 "RD1+" I L 4550 3050 50 23 | F3 "RD1-" I L 4550 3150 50 24 | F4 "TD1+" O L 4550 3250 50 25 | F5 "TD1-" O L 4550 3350 50 26 | F6 "TD2+" O L 4550 3700 50 27 | F7 "TD2-" O L 4550 3800 50 28 | F8 "TD3+" O L 4550 4350 50 29 | F9 "TD3-" O L 4550 4450 50 30 | F10 "TD4+" O L 4550 5000 50 31 | F11 "TD4-" O L 4550 5100 50 32 | F12 "RD2+" O L 4550 3900 50 33 | F13 "RD2-" O L 4550 4000 50 34 | F14 "RD3+" O L 4550 4550 50 35 | F15 "RD3-" O L 4550 4650 50 36 | F16 "RD4+" O L 4550 5200 50 37 | F17 "RD4-" O L 4550 5300 50 38 | F18 "P1_LED1" O L 4550 3450 50 39 | F19 "P1_LED2" O L 4550 3550 50 40 | F20 "P2_LED1" O L 4550 4100 50 41 | F21 "P2_LED2" O L 4550 4200 50 42 | F22 "P3_LED1" O L 4550 4750 50 43 | F23 "P3_LED2" O L 4550 4850 50 44 | F24 "P4_LED1" O L 4550 5400 50 45 | F25 "P4_LED2" O L 4550 5500 50 46 | F26 "RXD0" I R 5400 3200 50 47 | F27 "RXD1" I R 5400 3300 50 48 | F28 "CRS_DV" I R 5400 3400 50 49 | F29 "REF_CLK" I R 5400 3500 50 50 | F30 "TXEN" O R 5400 3650 50 51 | F31 "TXD0" O R 5400 3750 50 52 | F32 "TXD1" O R 5400 3850 50 53 | F33 "MDIO" B R 5400 4000 50 54 | F34 "MDC" O R 5400 4100 50 55 | F35 "PHY_~RST" O R 5400 4250 50 56 | F36 "ETH_LED" O R 5400 4350 50 57 | $EndSheet 58 | $Sheet 59 | S 5950 3000 900 1450 60 | U 5C2ED784 61 | F0 "Ethernet" 50 62 | F1 "ethernet.sch" 50 63 | F2 "RXD1" O L 5950 3300 50 64 | F3 "RXD0" O L 5950 3200 50 65 | F4 "CRS_DV" O L 5950 3400 50 66 | F5 "REF_CLK" O L 5950 3500 50 67 | F6 "TXEN" I L 5950 3650 50 68 | F7 "TXD0" I L 5950 3750 50 69 | F8 "TXD1" I L 5950 3850 50 70 | F9 "MDIO" B L 5950 4000 50 71 | F10 "MDC" I L 5950 4100 50 72 | F11 "~RST" I L 5950 4250 50 73 | F12 "48VDC" O R 6850 3050 50 74 | F13 "PG" O R 6850 3250 50 75 | F14 "0VDC" O R 6850 3150 50 76 | F15 "LED" I L 5950 4350 50 77 | $EndSheet 78 | $Sheet 79 | S 3200 3000 900 2650 80 | U 5C2ED83C 81 | F0 "DAQnet Ports" 50 82 | F1 "daqnet.sch" 50 83 | F2 "P1_LED1" I R 4100 3450 50 84 | F3 "P1_LED2" I R 4100 3550 50 85 | F4 "TD1-" I R 4100 3350 50 86 | F5 "TD1+" I R 4100 3250 50 87 | F6 "RD1-" O R 4100 3150 50 88 | F7 "RD1+" O R 4100 3050 50 89 | F8 "P2_LED1" I R 4100 4100 50 90 | F9 "P2_LED2" I R 4100 4200 50 91 | F10 "TD2-" I R 4100 3800 50 92 | F11 "TD2+" I R 4100 3700 50 93 | F12 "RD2-" O R 4100 4000 50 94 | F13 "RD2+" O R 4100 3900 50 95 | F14 "P3_LED1" I R 4100 4750 50 96 | F15 "P3_LED2" I R 4100 4850 50 97 | F16 "TD3-" I R 4100 4450 50 98 | F17 "TD3+" I R 4100 4350 50 99 | F18 "RD3-" O R 4100 4650 50 100 | F19 "RD3+" O R 4100 4550 50 101 | F20 "P4_LED1" I R 4100 5400 50 102 | F21 "P4_LED2" I R 4100 5500 50 103 | F22 "TD4-" I R 4100 5100 50 104 | F23 "TD4+" I R 4100 5000 50 105 | F24 "RD4-" O R 4100 5300 50 106 | F25 "RD4+" O R 4100 5200 50 107 | $EndSheet 108 | $Sheet 109 | S 7450 3000 900 600 110 | U 5C2ED962 111 | F0 "Power" 50 112 | F1 "power.sch" 50 113 | F2 "48VIN+" I L 7450 3050 50 114 | F3 "48VIN-" I L 7450 3150 50 115 | F4 "48VPG" I L 7450 3250 50 116 | $EndSheet 117 | Text Notes 8300 3550 2 50 ~ 0 118 | 48v in\nIsolated:\n24v 83mA out\n3v3 500mA out\n1v2 200mA out 119 | Wire Wire Line 120 | 5400 3200 5950 3200 121 | Wire Wire Line 122 | 5950 3300 5400 3300 123 | Wire Wire Line 124 | 5400 3400 5950 3400 125 | Wire Wire Line 126 | 5950 3500 5400 3500 127 | Wire Wire Line 128 | 5400 3650 5950 3650 129 | Wire Wire Line 130 | 5950 3750 5400 3750 131 | Wire Wire Line 132 | 5400 3850 5950 3850 133 | Wire Wire Line 134 | 5950 4000 5400 4000 135 | Wire Wire Line 136 | 5400 4100 5950 4100 137 | Wire Wire Line 138 | 5950 4250 5400 4250 139 | Wire Wire Line 140 | 5400 4350 5950 4350 141 | Wire Wire Line 142 | 6850 3250 7450 3250 143 | Wire Wire Line 144 | 6850 3150 7450 3150 145 | Wire Wire Line 146 | 6850 3050 7450 3050 147 | Wire Wire Line 148 | 4100 3050 4550 3050 149 | Wire Wire Line 150 | 4100 3150 4550 3150 151 | Wire Wire Line 152 | 4100 3250 4550 3250 153 | Wire Wire Line 154 | 4550 3350 4100 3350 155 | Wire Wire Line 156 | 4100 3450 4550 3450 157 | Wire Wire Line 158 | 4550 3550 4100 3550 159 | Wire Wire Line 160 | 4100 3700 4550 3700 161 | Wire Wire Line 162 | 4550 3800 4100 3800 163 | Wire Wire Line 164 | 4100 3900 4550 3900 165 | Wire Wire Line 166 | 4550 4000 4100 4000 167 | Wire Wire Line 168 | 4100 4100 4550 4100 169 | Wire Wire Line 170 | 4550 4200 4100 4200 171 | Wire Wire Line 172 | 4100 4350 4550 4350 173 | Wire Wire Line 174 | 4550 4450 4100 4450 175 | Wire Wire Line 176 | 4100 4550 4550 4550 177 | Wire Wire Line 178 | 4550 4650 4100 4650 179 | Wire Wire Line 180 | 4100 4750 4550 4750 181 | Wire Wire Line 182 | 4550 4850 4100 4850 183 | Wire Wire Line 184 | 4100 5000 4550 5000 185 | Wire Wire Line 186 | 4550 5100 4100 5100 187 | Wire Wire Line 188 | 4100 5200 4550 5200 189 | Wire Wire Line 190 | 4550 5300 4100 5300 191 | Wire Wire Line 192 | 4100 5400 4550 5400 193 | Wire Wire Line 194 | 4550 5500 4100 5500 195 | $Comp 196 | L agg:PART X101 197 | U 1 1 5C8667E8 198 | P 6950 5600 199 | F 0 "X101" H 7000 5700 50 0000 L CNN 200 | F 1 "M3_MOUNT" H 7000 5600 50 0000 L CNN 201 | F 2 "agg:M3_MOUNT" H 6950 5600 50 0001 C CNN 202 | F 3 "" H 6950 5600 50 0001 C CNN 203 | 1 6950 5600 204 | 1 0 0 -1 205 | $EndComp 206 | $Comp 207 | L agg:PART X102 208 | U 1 1 5C8675C5 209 | P 7550 5600 210 | F 0 "X102" H 7600 5700 50 0000 L CNN 211 | F 1 "M3_MOUNT" H 7600 5600 50 0000 L CNN 212 | F 2 "agg:M3_MOUNT" H 7550 5600 50 0001 C CNN 213 | F 3 "" H 7550 5600 50 0001 C CNN 214 | 1 7550 5600 215 | 1 0 0 -1 216 | $EndComp 217 | $Comp 218 | L agg:PART X104 219 | U 1 1 5C867961 220 | P 7550 5900 221 | F 0 "X104" H 7600 6000 50 0000 L CNN 222 | F 1 "M3_MOUNT" H 7600 5900 50 0000 L CNN 223 | F 2 "agg:M3_MOUNT" H 7550 5900 50 0001 C CNN 224 | F 3 "" H 7550 5900 50 0001 C CNN 225 | 1 7550 5900 226 | 1 0 0 -1 227 | $EndComp 228 | $Comp 229 | L agg:PART X103 230 | U 1 1 5C867C8A 231 | P 6950 5900 232 | F 0 "X103" H 7000 6000 50 0000 L CNN 233 | F 1 "M3_MOUNT" H 7000 5900 50 0000 L CNN 234 | F 2 "agg:M3_MOUNT" H 6950 5900 50 0001 C CNN 235 | F 3 "" H 6950 5900 50 0001 C CNN 236 | 1 6950 5900 237 | 1 0 0 -1 238 | $EndComp 239 | $EndSCHEMATC 240 | -------------------------------------------------------------------------------- /hardware/proto-switch/proto-switch_bom.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/proto-switch/proto-switch_bom.pdf -------------------------------------------------------------------------------- /hardware/proto-switch/stm32.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | LIBS:proto-switch-cache 3 | EELAYER 29 0 4 | EELAYER END 5 | $Descr A4 11693 8268 6 | encoding utf-8 7 | Sheet 1 5 8 | Title "" 9 | Date "" 10 | Rev "" 11 | Comp "" 12 | Comment1 "" 13 | Comment2 "" 14 | Comment3 "" 15 | Comment4 "" 16 | $EndDescr 17 | $EndSCHEMATC 18 | -------------------------------------------------------------------------------- /hardware/proto-switch/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name agg)(type Legacy)(uri "$(KIPRJMOD)/../agg-kicad/agg-kicad.lib")(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /hardware/rtm/20181127_bom.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/rtm/20181127_bom.ods -------------------------------------------------------------------------------- /hardware/rtm/gerber/agg-tbge-pr1-20181127.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/adamgreig/daqnet/49537e0e27c6bde231c725c304849674800ae5ee/hardware/rtm/gerber/agg-tbge-pr1-20181127.zip -------------------------------------------------------------------------------- /hardware/rtm/gerber/proto_switch_sensor_r1_panel-B.SilkS.gbo: -------------------------------------------------------------------------------- 1 | G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.1-33cea8e~66~ubuntu18.04.1* 2 | G04 #@! TF.CreationDate,2018-11-27T01:50:38+00:00* 3 | G04 #@! TF.ProjectId,proto_switch_sensor_r1_panel,70726F746F5F7377697463685F73656E,1* 4 | G04 #@! TF.SameCoordinates,Original* 5 | G04 #@! TF.FileFunction,Legend,Bot* 6 | G04 #@! TF.FilePolarity,Positive* 7 | %FSLAX46Y46*% 8 | G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* 9 | G04 Created by KiCad (PCBNEW 5.0.1-33cea8e~66~ubuntu18.04.1) date Tue 27 Nov 2018 01:50:38 GMT* 10 | %MOMM*% 11 | %LPD*% 12 | G01* 13 | G04 APERTURE LIST* 14 | %ADD10C,0.150000*% 15 | %ADD11C,1.440000*% 16 | %ADD12C,3.291200*% 17 | %ADD13C,2.580000*% 18 | %ADD14C,0.640000*% 19 | %ADD15C,6.300000*% 20 | %ADD16R,1.940000X1.940000*% 21 | %ADD17C,1.056000*% 22 | %ADD18C,1.540000*% 23 | %ADD19C,0.100000*% 24 | %ADD20C,1.040000*% 25 | %ADD21C,3.240000*% 26 | %ADD22C,2.040000*% 27 | G04 APERTURE END LIST* 28 | D10* 29 | X80960714Y-100190476D02* 30 | X81627380Y-100190476D01* 31 | X80579761Y-99952380D02* 32 | X81294047Y-99714285D01* 33 | X81294047Y-100333333D01* 34 | X81532142Y-100714285D02* 35 | X81579761Y-100761904D01* 36 | X81627380Y-100714285D01* 37 | X81579761Y-100666666D01* 38 | X81532142Y-100714285D01* 39 | X81627380Y-100714285D01* 40 | X80627380Y-101666666D02* 41 | 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X82610714Y-109333333D01* 204 | X82658333Y-109285714D01* 205 | X82705952Y-109190476D01* 206 | X82705952Y-109000000D01* 207 | X82753571Y-108904761D01* 208 | X82801190Y-108857142D01* 209 | X82896428Y-108809523D01* 210 | X83086904Y-108809523D01* 211 | X83182142Y-108857142D01* 212 | X83229761Y-108904761D01* 213 | X83277380Y-109000000D01* 214 | X83277380Y-109190476D01* 215 | X83229761Y-109285714D01* 216 | X83182142Y-109333333D01* 217 | X83086904Y-109380952D01* 218 | X82896428Y-109380952D01* 219 | X82801190Y-109333333D01* 220 | X82753571Y-109285714D01* 221 | X82705952Y-109190476D01* 222 | X83182142Y-109809523D02* 223 | X83229761Y-109857142D01* 224 | X83277380Y-109809523D01* 225 | X83229761Y-109761904D01* 226 | X83182142Y-109809523D01* 227 | X83277380Y-109809523D01* 228 | X82658333Y-109809523D02* 229 | X82705952Y-109857142D01* 230 | X82753571Y-109809523D01* 231 | X82705952Y-109761904D01* 232 | X82658333Y-109809523D01* 233 | X82753571Y-109809523D01* 234 | X82896428Y-111047619D02* 235 | X82896428Y-111809523D01* 236 | %LPC*% 237 | D11* 238 | G04 #@! TO.C,J302* 239 | X169544000Y-150182000D03* 240 | X171576000Y-150182000D03* 241 | X173608000Y-150182000D03* 242 | X175640000Y-150182000D03* 243 | X170560000Y-151960000D03* 244 | X172592000Y-151960000D03* 245 | X174624000Y-151960000D03* 246 | X176656000Y-151960000D03* 247 | X166242000Y-145356000D03* 248 | X179958000Y-145356000D03* 249 | X168528000Y-145356000D03* 250 | X177672000Y-145356000D03* 251 | D12* 252 | X166750000Y-154500000D03* 253 | X179450000Y-154500000D03* 254 | D13* 255 | X164972000Y-151071000D03* 256 | X181228000Y-151071000D03* 257 | G04 #@! TD* 258 | G04 #@! TO.C,J401* 259 | X129378000Y-144340000D03* 260 | X113628000Y-144340000D03* 261 | D12* 262 | X151468000Y-154500000D03* 263 | D13* 264 | X153250000Y-151071000D03* 265 | D11* 266 | X146652000Y-151960000D03* 267 | X130902000Y-151960000D03* 268 | X115152000Y-151960000D03* 269 | X138270000Y-145356000D03* 270 | X122520000Y-145356000D03* 271 | X106770000Y-145356000D03* 272 | X140556000Y-145356000D03* 273 | X124806000Y-145356000D03* 274 | X109056000Y-145356000D03* 275 | X149700000Y-145356000D03* 276 | X133950000Y-145356000D03* 277 | X118200000Y-145356000D03* 278 | X142588000Y-151960000D03* 279 | X126838000Y-151960000D03* 280 | X111088000Y-151960000D03* 281 | X144620000Y-151960000D03* 282 | X128870000Y-151960000D03* 283 | X113120000Y-151960000D03* 284 | X151986000Y-145356000D03* 285 | X136236000Y-145356000D03* 286 | X120486000Y-145356000D03* 287 | X141572000Y-150182000D03* 288 | X125822000Y-150182000D03* 289 | X110072000Y-150182000D03* 290 | X143604000Y-150182000D03* 291 | X127854000Y-150182000D03* 292 | X112104000Y-150182000D03* 293 | X148684000Y-151960000D03* 294 | X132934000Y-151960000D03* 295 | X117184000Y-151960000D03* 296 | X145636000Y-150182000D03* 297 | X129886000Y-150182000D03* 298 | X114136000Y-150182000D03* 299 | X147668000Y-150182000D03* 300 | X131918000Y-150182000D03* 301 | X116168000Y-150182000D03* 302 | X94322000Y-150182000D03* 303 | X96354000Y-150182000D03* 304 | X98386000Y-150182000D03* 305 | X100418000Y-150182000D03* 306 | X95338000Y-151960000D03* 307 | X97370000Y-151960000D03* 308 | X99402000Y-151960000D03* 309 | X101434000Y-151960000D03* 310 | X91020000Y-145356000D03* 311 | X104736000Y-145356000D03* 312 | X93306000Y-145356000D03* 313 | X102450000Y-145356000D03* 314 | D12* 315 | X91528000Y-154500000D03* 316 | D13* 317 | X89750000Y-151071000D03* 318 | G04 #@! TD* 319 | D14* 320 | G04 #@! TO.C,X104* 321 | X85800000Y-157800000D03* 322 | X82200000Y-157800000D03* 323 | X85800000Y-154200000D03* 324 | X82200000Y-154200000D03* 325 | X81500000Y-156000000D03* 326 | X84000000Y-158500000D03* 327 | X86500000Y-156000000D03* 328 | X84000000Y-153500000D03* 329 | D15* 330 | X84000000Y-156000000D03* 331 | G04 #@! TD* 332 | D14* 333 | G04 #@! TO.C,X103* 334 | X189800000Y-157800000D03* 335 | X186200000Y-157800000D03* 336 | X189800000Y-154200000D03* 337 | X186200000Y-154200000D03* 338 | X185500000Y-156000000D03* 339 | X188000000Y-158500000D03* 340 | X190500000Y-156000000D03* 341 | X188000000Y-153500000D03* 342 | D15* 343 | X188000000Y-156000000D03* 344 | G04 #@! TD* 345 | D14* 346 | G04 #@! TO.C,X102* 347 | X189800000Y-123800000D03* 348 | X186200000Y-123800000D03* 349 | X189800000Y-120200000D03* 350 | X186200000Y-120200000D03* 351 | X185500000Y-122000000D03* 352 | X188000000Y-124500000D03* 353 | X190500000Y-122000000D03* 354 | X188000000Y-119500000D03* 355 | D15* 356 | X188000000Y-122000000D03* 357 | G04 #@! TD* 358 | D14* 359 | G04 #@! TO.C,X101* 360 | X85800000Y-123800000D03* 361 | X82200000Y-123800000D03* 362 | X85800000Y-120200000D03* 363 | X82200000Y-120200000D03* 364 | X81500000Y-122000000D03* 365 | X84000000Y-124500000D03* 366 | X86500000Y-122000000D03* 367 | X84000000Y-119500000D03* 368 | D15* 369 | X84000000Y-122000000D03* 370 | G04 #@! TD* 371 | D16* 372 | G04 #@! TO.C,J501* 373 | X82500000Y-150500000D03* 374 | G04 #@! TD* 375 | D17* 376 | G04 #@! TO.C,J201* 377 | X134410000Y-122000000D03* 378 | X134410000Y-120730000D03* 379 | X135680000Y-122000000D03* 380 | X135680000Y-120730000D03* 381 | X136950000Y-122000000D03* 382 | X136950000Y-120730000D03* 383 | X138220000Y-122000000D03* 384 | X138220000Y-120730000D03* 385 | X139490000Y-122000000D03* 386 | X139490000Y-120730000D03* 387 | G04 #@! TD* 388 | D18* 389 | G04 #@! TO.C,IC503* 390 | X146110000Y-131750000D03* 391 | X148650000Y-131750000D03* 392 | X151190000Y-131750000D03* 393 | X153730000Y-131750000D03* 394 | X158810000Y-131750000D03* 395 | X161350000Y-131750000D03* 396 | D19* 397 | G36* 398 | X164312737Y-130981854D02* 399 | X164350110Y-130987398D01* 400 | X164386760Y-130996578D01* 401 | X164422333Y-131009306D01* 402 | X164456488Y-131025460D01* 403 | X164488895Y-131044884D01* 404 | X164519241Y-131067391D01* 405 | X164547236Y-131092764D01* 406 | X164572609Y-131120759D01* 407 | X164595116Y-131151105D01* 408 | X164614540Y-131183512D01* 409 | X164630694Y-131217667D01* 410 | X164643422Y-131253240D01* 411 | X164652602Y-131289890D01* 412 | X164658146Y-131327263D01* 413 | X164660000Y-131365000D01* 414 | X164660000Y-132135000D01* 415 | X164658146Y-132172737D01* 416 | X164652602Y-132210110D01* 417 | X164643422Y-132246760D01* 418 | X164630694Y-132282333D01* 419 | X164614540Y-132316488D01* 420 | X164595116Y-132348895D01* 421 | X164572609Y-132379241D01* 422 | X164547236Y-132407236D01* 423 | X164519241Y-132432609D01* 424 | X164488895Y-132455116D01* 425 | X164456488Y-132474540D01* 426 | X164422333Y-132490694D01* 427 | X164386760Y-132503422D01* 428 | X164350110Y-132512602D01* 429 | X164312737Y-132518146D01* 430 | X164275000Y-132520000D01* 431 | X163505000Y-132520000D01* 432 | X163467263Y-132518146D01* 433 | X163429890Y-132512602D01* 434 | X163393240Y-132503422D01* 435 | X163357667Y-132490694D01* 436 | X163323512Y-132474540D01* 437 | X163291105Y-132455116D01* 438 | X163260759Y-132432609D01* 439 | X163232764Y-132407236D01* 440 | X163207391Y-132379241D01* 441 | X163184884Y-132348895D01* 442 | X163165460Y-132316488D01* 443 | X163149306Y-132282333D01* 444 | X163136578Y-132246760D01* 445 | X163127398Y-132210110D01* 446 | X163121854Y-132172737D01* 447 | X163120000Y-132135000D01* 448 | X163120000Y-131365000D01* 449 | X163121854Y-131327263D01* 450 | X163127398Y-131289890D01* 451 | X163136578Y-131253240D01* 452 | X163149306Y-131217667D01* 453 | X163165460Y-131183512D01* 454 | X163184884Y-131151105D01* 455 | X163207391Y-131120759D01* 456 | X163232764Y-131092764D01* 457 | X163260759Y-131067391D01* 458 | X163291105Y-131044884D01* 459 | X163323512Y-131025460D01* 460 | X163357667Y-131009306D01* 461 | X163393240Y-130996578D01* 462 | X163429890Y-130987398D01* 463 | X163467263Y-130981854D01* 464 | X163505000Y-130980000D01* 465 | X164275000Y-130980000D01* 466 | X164312737Y-130981854D01* 467 | X164312737Y-130981854D01* 468 | G37* 469 | D18* 470 | X163890000Y-131750000D03* 471 | G04 #@! TD* 472 | G04 #@! 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| X5.8661Y-3.8189 282 | X5.8661Y-3.8976 283 | X5.8661Y-3.9764 284 | X5.8661Y-4.0551 285 | X5.8661Y-4.1339 286 | X5.8661Y-4.2126 287 | X5.8661Y-4.2913 288 | X5.8661Y-4.3701 289 | X5.8661Y-4.4488 290 | X5.8661Y-4.5276 291 | X5.9173Y-5.6339 292 | X6.1457Y-5.1575 293 | X6.3031Y-5.1654 294 | X6.6732Y-4.815 295 | X6.6732Y-5.063 296 | X6.6969Y-5.1614 297 | X6.7441Y-4.9449 298 | X6.7441Y-5.0315 299 | X6.7677Y-4.9213 300 | X6.878Y-4.7992 301 | X6.8799Y-4.8976 302 | X6.9724Y-4.9882 303 | X7.Y-4.9724 304 | X7.Y-5.1339 305 | X7.0197Y-4.8976 306 | X7.0787Y-4.9134 307 | X7.1024Y-4.9724 308 | X7.1024Y-5.0197 309 | X7.1102Y-5.0827 310 | X7.2008Y-5.4724 311 | X7.3425Y-5.0591 312 | T3 313 | X6.8268Y-4.9961 314 | X6.8268Y-5.0433 315 | X6.874Y-4.9961 316 | X6.874Y-5.0433 317 | T4 318 | X3.189Y-5. 319 | X3.189Y-5.1969 320 | X3.189Y-5.3937 321 | X3.189Y-5.5906 322 | X3.4252Y-4.685 323 | X3.4646Y-6.2598 324 | X3.5236Y-5.7913 325 | X3.6614Y-6.2598 326 | X3.7362Y-4.0591 327 | X3.748Y-4.748 328 | X3.7953Y-5.5276 329 | X3.7992Y-3.9488 330 | X3.8189Y-5.1575 331 | X3.8583Y-6.2598 332 | X3.8976Y-5.4173 333 | X3.9567Y-5.5709 334 | X4.0157Y-5.1575 335 | X4.0551Y-6.0039 336 | X4.0551Y-6.2598 337 | X4.0748Y-4.0079 338 | X4.1102Y-5.4173 339 | X4.2126Y-5.1575 340 | X4.252Y-6.2598 341 | X4.3071Y-4.748 342 | X4.3228Y-5.4173 343 | X4.4134Y-5.1417 344 | X4.4134Y-5.315 345 | X4.4488Y-6.2598 346 | X4.4882Y-5.3346 347 | X4.5236Y-5.5354 348 | X4.6457Y-6.2598 349 | X4.6772Y-6. 350 | X4.7638Y-5.4331 351 | X4.8425Y-6.2598 352 | X4.8937Y-5.5591 353 | X5.0394Y-6.2598 354 | X5.1339Y-5.4213 355 | X5.2362Y-4.685 356 | X5.2362Y-6.2598 357 | X5.2953Y-5.1772 358 | X5.2953Y-6.0039 359 | X5.4331Y-4.685 360 | X5.4331Y-6.2598 361 | X5.5709Y-5.4213 362 | X5.6299Y-6.2598 363 | X5.6496Y-5.563 364 | X5.7402Y-5.4488 365 | X5.8268Y-4.685 366 | X5.8268Y-6.2598 367 | X6.0236Y-6.2598 368 | X6.4449Y-5.7677 369 | X6.4449Y-5.8504 370 | X6.5394Y-5.0984 371 | X6.6339Y-4.7717 372 | X6.685Y-5.6417 373 | X6.8937Y-4.7087 374 | X6.937Y-5.6417 375 | X7.0945Y-4.7087 376 | X7.1024Y-5.1772 377 | X7.189Y-5.5866 378 | X7.189Y-5.689 379 | X7.189Y-5.7992 380 | X7.2047Y-4.7244 381 | X7.2165Y-5.185 382 | X7.2165Y-5.2992 383 | X7.2402Y-5.9488 384 | X7.4843Y-5.6299 385 | X7.4843Y-5.7598 386 | T5 387 | X3.3268Y-4.6063 388 | X3.3665Y-4.6063 389 | X4.1535Y-4.6063 390 | X4.1933Y-4.6063 391 | X4.9016Y-4.6063 392 | X4.9413Y-4.6063 393 | X5.7283Y-4.6063 394 | X5.7681Y-4.6063 395 | T6 396 | X4.8803Y-3.8687 397 | X4.8803Y-3.9187 398 | X4.9303Y-3.8687 399 | X4.9303Y-3.9187 400 | X4.9803Y-3.8687 401 | X4.9803Y-3.9187 402 | X5.0303Y-3.8687 403 | X5.0303Y-3.9187 404 | X5.0803Y-3.8687 405 | X5.0803Y-3.9187 406 | X5.2917Y-4.7531 407 | X5.2917Y-4.8031 408 | X5.3417Y-4.7531 409 | X5.3417Y-4.8031 410 | X5.3917Y-4.7531 411 | X5.3917Y-4.8031 412 | X5.4417Y-4.7531 413 | X5.4417Y-4.8031 414 | X5.4917Y-4.7531 415 | X5.4917Y-4.8031 416 | T7 417 | X5.7524Y-4.7933 418 | X5.8524Y-4.7933 419 | X5.9524Y-4.7933 420 | X6.0524Y-4.7933 421 | X6.2524Y-4.7933 422 | X6.3524Y-4.7933 423 | X6.4524Y-4.7933 424 | X5.7524Y-5.187 425 | X5.8524Y-5.187 426 | X5.9524Y-5.187 427 | X6.0524Y-5.187 428 | X6.2524Y-5.187 429 | X6.3524Y-5.187 430 | X6.4524Y-5.187 431 | T8 432 | X3.4465Y-4.0732 433 | X3.4465Y-4.1532 434 | X3.4465Y-4.2332 435 | X3.4465Y-4.3132 436 | X3.5165Y-4.0332 437 | X3.5165Y-4.1132 438 | X3.5165Y-4.1932 439 | X3.5165Y-4.2732 440 | X3.7065Y-3.9032 441 | X3.7065Y-3.9932 442 | X3.7065Y-4.3532 443 | X3.7065Y-4.4432 444 | X3.5835Y-5.7227 445 | X3.6735Y-5.7227 446 | X3.7135Y-5.9127 447 | X3.7535Y-5.9827 448 | X3.7935Y-5.9127 449 | X3.8335Y-5.9827 450 | X3.8735Y-5.9127 451 | X3.9135Y-5.9827 452 | X3.9535Y-5.9127 453 | X3.9935Y-5.9827 454 | X4.0335Y-5.7227 455 | X4.1235Y-5.7227 456 | X4.2035Y-5.7227 457 | X4.2935Y-5.7227 458 | X4.3335Y-5.9127 459 | X4.3735Y-5.9827 460 | X4.4135Y-5.9127 461 | X4.4535Y-5.9827 462 | X4.4935Y-5.9127 463 | X4.5335Y-5.9827 464 | X4.5735Y-5.9127 465 | X4.6135Y-5.9827 466 | X4.6535Y-5.7227 467 | X4.7435Y-5.7227 468 | X4.8236Y-5.7227 469 | X4.9136Y-5.7227 470 | X4.9536Y-5.9127 471 | X4.9936Y-5.9827 472 | X5.0336Y-5.9127 473 | X5.0736Y-5.9827 474 | X5.1136Y-5.9127 475 | X5.1536Y-5.9827 476 | X5.1936Y-5.9127 477 | X5.2336Y-5.9827 478 | X5.2736Y-5.7227 479 | X5.3636Y-5.7227 480 | X5.4437Y-5.7227 481 | X5.5337Y-5.7227 482 | X5.5737Y-5.9127 483 | X5.6137Y-5.9827 484 | X5.6537Y-5.9127 485 | X5.6937Y-5.9827 486 | X5.7337Y-5.9127 487 | X5.7737Y-5.9827 488 | X5.8137Y-5.9127 489 | X5.8537Y-5.9827 490 | X5.8937Y-5.7227 491 | X5.9837Y-5.7227 492 | X6.545Y-5.7227 493 | X6.635Y-5.7227 494 | X6.675Y-5.9127 495 | X6.715Y-5.9827 496 | X6.755Y-5.9127 497 | X6.795Y-5.9827 498 | X6.835Y-5.9127 499 | X6.875Y-5.9827 500 | X6.915Y-5.9127 501 | X6.955Y-5.9827 502 | X6.995Y-5.7227 503 | X7.085Y-5.7227 504 | T9 505 | X3.878Y-4.5059 506 | X3.248Y-5.9252 507 | T10 508 | X5.5906Y-4.1732 509 | T11 510 | X3.4815Y-3.8532 511 | X3.4815Y-4.4932 512 | X3.5335Y-5.9477 513 | X4.4735Y-5.6827 514 | X5.0936Y-5.6827 515 | X6.0335Y-5.9477 516 | X6.495Y-5.9477 517 | X7.135Y-5.9477 518 | T12 519 | X5.4606Y-4.0433 520 | X5.4606Y-4.3031 521 | X5.7205Y-4.0433 522 | X5.7205Y-4.3031 523 | T13 524 | X3.2087Y-6.1417 525 | X3.2362Y-6.0709 526 | X3.2362Y-6.2126 527 | X3.3071Y-6.0433 528 | X3.3071Y-6.2402 529 | X3.378Y-6.0709 530 | X3.378Y-6.2126 531 | X3.4055Y-6.1417 532 | X3.2087Y-4.8031 533 | X3.2362Y-4.7323 534 | X3.2362Y-4.874 535 | X3.3071Y-4.7047 536 | X3.3071Y-4.9016 537 | X3.378Y-4.7323 538 | X3.378Y-4.874 539 | X3.4055Y-4.8031 540 | X7.3031Y-6.1417 541 | X7.3307Y-6.0709 542 | X7.3307Y-6.2126 543 | X7.4016Y-6.0433 544 | X7.4016Y-6.2402 545 | X7.4724Y-6.0709 546 | X7.4724Y-6.2126 547 | X7.5Y-6.1417 548 | X7.3031Y-4.8031 549 | X7.3307Y-4.7323 550 | X7.3307Y-4.874 551 | X7.4016Y-4.7047 552 | X7.4016Y-4.9016 553 | X7.4724Y-4.7323 554 | X7.4724Y-4.874 555 | X7.5Y-4.8031 556 | T14 557 | X4.8094Y-4.0543 558 | X4.8094Y-4.1343 559 | X5.0094Y-4.0943 560 | T15 561 | X3.3465Y-3.9232 562 | X3.3465Y-4.4232 563 | X3.6035Y-6.0827 564 | X5.9633Y-6.0827 565 | X6.565Y-6.0827 566 | X7.065Y-6.0827 567 | T16 568 | X3.3071Y-6.1417 569 | X3.3071Y-4.8031 570 | X7.4016Y-6.1417 571 | X7.4016Y-4.8031 572 | T0 573 | M30 574 | -------------------------------------------------------------------------------- /software/scripts/plot.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | import matplotlib.pyplot as plt 3 | import serial 4 | 5 | 6 | def main(): 7 | ser = serial.Serial("/dev/ttyUSB0", 1000000) 8 | raw_data = ser.read(10000) 9 | data = np.frombuffer(raw_data, dtype=np.uint8) 10 | plt.plot(data, '.') 11 | plt.show() 12 | 13 | 14 | if __name__ == "__main__": 15 | main() 16 | -------------------------------------------------------------------------------- /software/scripts/run_leds.py: -------------------------------------------------------------------------------- 1 | import time 2 | import socket 3 | import struct 4 | import argparse 5 | 6 | 7 | def get_args(): 8 | parser = argparse.ArgumentParser() 9 | parser.add_argument("address") 10 | parser.add_argument("port") 11 | return parser.parse_args() 12 | 13 | 14 | def set_leds(s, led1, led2): 15 | data = int(led1) | (int(led2) << 1) 16 | s.send(struct.pack("B", data) + b"\x00"*15) 17 | 18 | 19 | def main(): 20 | args = get_args() 21 | s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM, 0) 22 | s.connect((args.address, int(args.port))) 23 | while True: 24 | for x in range(4): 25 | set_leds(s, x & 1 == 1, x & 2 == 2) 26 | time.sleep(0.2) 27 | 28 | 29 | if __name__ == "__main__": 30 | main() 31 | -------------------------------------------------------------------------------- /software/scripts/user.py: -------------------------------------------------------------------------------- 1 | import socket 2 | import struct 3 | import argparse 4 | 5 | 6 | def get_args(): 7 | parser = argparse.ArgumentParser() 8 | parser.add_argument("address") 9 | parser.add_argument("port") 10 | parser.add_argument("data") 11 | return parser.parse_args() 12 | 13 | 14 | def main(): 15 | args = get_args() 16 | s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM, 0) 17 | s.connect((args.address, int(args.port))) 18 | s.send(struct.pack("B", int(args.data, 0)) + b"\x00"*15) 19 | s.close() 20 | 21 | 22 | if __name__ == "__main__": 23 | main() 24 | --------------------------------------------------------------------------------