├── AUTHORS ├── TODO ├── README ├── testbench └── intrCntrl_tb.v ├── src └── intrCntrl.v └── COPYING /AUTHORS: -------------------------------------------------------------------------------- 1 | Aditya Shevade 2 | 3 | -------------------------------------------------------------------------------- /TODO: -------------------------------------------------------------------------------- 1 | TODO 2 | =============================================================================== 3 | 4 | Interrupt Controller 5 | -------------------- 6 | 7 | 1. Make the interrupts positive or negative edge triggered depending 8 | on the status of a status register. 9 | 2. Add vectored interrupts depending on status register. Add more 10 | states to get vectoring information. 11 | 12 | Testbench 13 | --------- 14 | 15 | 1. Convert to system verilog. Add assertions and randomization. 16 | Add coverage to make sure all priority combintations are tested. 17 | 18 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | Simple Interrupt Controller 2 | Author: Aditya Shevade 3 | =============================================================================== 4 | 5 | This is a simple 8 input interrupt controller. 6 | Written in verilog. 7 | 8 | Currently it supports two modes, polling and custom priority. 9 | 10 | In polling, there are no priorities. All the interrupts are 11 | checked periodically and if any one of them is active then it 12 | is serviced. 13 | 14 | In the custom priority mode, the priorities are set during the 15 | initialization phase. The controller then polls the sources in 16 | this custom order. 17 | 18 | Operation 19 | =============================================================================== 20 | After Reset, the controller waits for commands from the master 21 | (processor) on the bus. The lowest 2 bits determine the mode of 22 | operation. 23 | 24 | 01 - Polling mode 25 | 10 - Priority mode. 26 | 27 | It keeps waiting for valid input mode. 28 | 29 | Polling 30 | =============================================================================== 31 | The bus is driven as xxxx_xx01 for exactly 1 clock by processor. 32 | Controller knows this is the polling mode. It then enters the 33 | polling state where it keeps checkig for all interrupt sources 34 | in cycle. 35 | 36 | If any interrupt is found active then intr_out is set to 1. 37 | After that, the controller waits for an acknowledgement from 38 | the processor. 39 | 40 | Once the processor gives acknowledgement, exactly for 1 clock 41 | cycle on intr_in by a high -> low -> high transition, the 42 | controller starts driving the bus with the condition code of 43 | 01011_intrID. The intrID part is the ID of the source currently 44 | being serviced. 45 | 46 | Controller keeps this data on the bus it it receives another 47 | acknowledgement from the processor on the intr_in pin in the 48 | same mannter (High -> Low -> High). 49 | 50 | After that, the controller waits for the confirmation from the 51 | processor that the interrupt has been serviced. Processor, once 52 | done, sends another acknowledgement on the intr_in pin in the 53 | same mannter (High -> Low -> High) along with the condition 54 | code of 10100_intrID on the bus. This interrupt ID must match 55 | the one sent last by the controller. 56 | 57 | If either the condition code or the intrID does not match then 58 | the controller goes to reset state. Else it just checks (polls) 59 | the next source and continues in this cycle unless reset. 60 | 61 | 62 | Custom Priority 63 | =============================================================================== 64 | Working of this mode is exactly similar to the polling exept 65 | that it does not poll the sources in order. 66 | 67 | After reset, if the input is xxxyyy10 then the controller is 68 | in custom priority mode. xxx is the source ID of the highest 69 | interrupt and yyy is the ID of the second to highest. The 70 | processor needs to give 4 such cycles to and give the prio- 71 | -rities for all 8 sources. 72 | 73 | After that the controller goes on checking from the highest 74 | to lowest source to check if any of them is active. If it is 75 | then the operation continues similar to the polling mode. 76 | 77 | The only things that change are the condition codes that are 78 | sent to and from the processor. The controller sends 10011 79 | and the processor acknowledges with 01100. 80 | 81 | ------------------------------------------------------------------------------- 82 | TODO: Currently there is no way of checking if two (or more) of 83 | the sources are same. This can be good if you want to disable 84 | some interrupts. You can repeat the last priority till you 85 | have reached the total count of 8. 86 | ------------------------------------------------------------------------------- 87 | 88 | Timing Diagram 89 | =============================================================================== 90 | 91 | intr_out __________________ 92 | ____| |___________________________________________ 93 | 94 | intr_in __________________ ______________ ___________ _____ 95 | |____| |____| |____| 96 | 97 | data_bus _______________________|||||||||||||||||||||___________||||||_____ 98 | 99 | 100 | ------------------------------------------------------------------------------- 101 | Note - The first time the data_bus is active is when the controller 102 | drives the bus. Next time when it's active, the processor drives it. 103 | ------------------------------------------------------------------------------- 104 | Note - The timing diagram remains the same on both polling and custom 105 | priority modes. Only thing that changes is the ack data on the bus. 106 | ------------------------------------------------------------------------------- 107 | 108 | Condition Codes 109 | =============================================================================== 110 | 111 | Polling: 112 | From Controller - 01011 113 | From Processor - 10100 114 | 115 | Custom Priority 116 | From Controller - 10011 117 | From Processor - 01100 118 | 119 | =============================================================================== 120 | 121 | -------------------------------------------------------------------------------- /testbench/intrCntrl_tb.v: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Filename : intrCntrl_tb.v 4 | * 5 | * Description : Testbench for the interrupt controller. Currently supports 6 | polling and custom priority mode. 7 | * 8 | * Author : Aditya Shevade 9 | * 10 | * 11 | * Created : 12/04/2011 12 | * 13 | ****************************************************************************** 14 | */ 15 | 16 | module INTR_CNTRL_TB; 17 | 18 | reg clk_in; // Clock 19 | reg rst_in; // Reset 20 | reg [7:0] intr_rq; // Interrupt request 21 | reg [7:0] intr_bus_in; // Bidirectional data bus 22 | reg intr_in; // Ack from processor 23 | wire intr_out; // Interrupt to processor 24 | wire bus_oe; // High if controller drives the bus. 25 | 26 | wire [7:0] intr_bus_test; 27 | wire [7:0] intr_bus_out; 28 | INTR_CNTRL DUT ( 29 | .clk_in (clk_in ), 30 | .rst_in (rst_in ), 31 | .intr_rq (intr_rq ), 32 | .intr_bus (intr_bus_test ), 33 | .intr_in (intr_in ), 34 | .intr_out (intr_out ), 35 | .bus_oe (bus_oe ) 36 | ); 37 | 38 | assign intr_bus_test = (bus_oe == 0) ? intr_bus_in : 8'bz; 39 | assign intr_bus_out = (bus_oe == 1) ? intr_bus_test : 8'bz; 40 | 41 | reg [2:0] currentService; // Store the ID of interrupt currently being serviced. 42 | integer j; 43 | 44 | initial begin 45 | // Reset the system. 46 | clk_in = 1'b0; 47 | rst_in = 1'b1; 48 | intr_rq = 8'b0; 49 | intr_bus_in = 8'b0; 50 | intr_in = 1'b1; 51 | #20; 52 | rst_in = 1'b0; 53 | #20; 54 | intr_bus_in = 8'b0000_0001; // Test the polling mode. 55 | #40; // Wait random time. 56 | intr_rq = 8'b1010_1010; // Activate random interrupts. 57 | 58 | $display ("=================================================================="); 59 | $display ("======== Beginning Polling ========"); 60 | $display ("=================================================================="); 61 | 62 | for (j = 0; j < 8; j = j + 1) begin 63 | if (j == 4) begin // Change the sources after servicing the first 4. 64 | intr_rq = 8'b0101_0101; 65 | end 66 | $display ("=================================================================="); 67 | $display ("Servicing Interrupt Number %d / 8", (j+1)); 68 | $display ("=================================================================="); 69 | $display ("Interrupt Request = %b", intr_rq); 70 | 71 | $display ("Waiting for interrupt from controller"); 72 | wait(intr_out); // Wait till controller gives interrupt. 73 | #60; // Wait for random cycles. Then Acknowledge interrupt. 74 | intr_in = 1'b0; // Ack Start 75 | #10 // Active for 1 clock. 76 | intr_in = 1'b1; // Ack End 77 | $display ("Interrupt Acknowledged by processor."); 78 | $display("Currently servicing %b", intr_bus_out[2:0]); 79 | $display ("The controller is driving the bus, %b", intr_bus_out); 80 | currentService = intr_bus_out[2:0]; 81 | intr_rq[currentService] = 1'b0; // Disable the interrupt serviced. This will be done by the interrupt master. 82 | 83 | // INFO: This is is an explicit assertion in verilog. 84 | // Used instead of assert because no free compiler I know can simulate system verilog. 85 | if (intr_bus_out == {5'b01011, currentService}) begin 86 | $display ("Proper address on the bus"); 87 | end else begin 88 | $display ("ERROR: Wrong address on the bus"); 89 | $finish; 90 | end 91 | 92 | #60 // At this point controller sends the address on the bus. 93 | intr_in = 1'b0; // Ack Start 94 | #10 // Active for 1 clock. 95 | intr_in = 1'b1; // Ack End 96 | $display ("Address acknowledged by processor"); 97 | 98 | #60 // Wait for random time. Work on interrupt. 99 | intr_bus_in = {5'b10100, currentService}; // Send the ACK to controller. 100 | intr_in = 1'b0; // Let the controller know this is an Ack. 101 | #10 // Active for 1 clock. 102 | intr_in = 1'b1; // Ack ends. 103 | $display ("ISR Routine complete by processor"); 104 | $display ("The processor is driving the bus, %b", intr_bus_in); 105 | $display ("==================================================================\n\n\n"); 106 | #100; 107 | end 108 | 109 | #100; 110 | rst_in = 1'b1; 111 | intr_rq = 8'b0; 112 | intr_bus_in = 8'b0; 113 | intr_in = 1'b1; 114 | #50; 115 | rst_in = 1'b0; 116 | #50; 117 | 118 | // Set priorities => 5, 3, 7, 0, 4, 2, 6, 1. 119 | intr_bus_in = 8'b101_011_10; 120 | #10; 121 | intr_bus_in = 8'b111_000_10; 122 | #10; 123 | intr_bus_in = 8'b100_010_10; 124 | #10; 125 | intr_bus_in = 8'b110_001_10; 126 | #40; 127 | intr_rq = 8'b1111_1111; // Activate random interrupts. 128 | 129 | $display ("=================================================================="); 130 | $display ("======== Beginning Priority ========"); 131 | $display ("=================================================================="); 132 | $display ("=================================================================="); 133 | $display ("Proper Order - 5 -> 3 -> 7 -> 0 -> 4 -> 3 -> 2 -> 5 -> 6 -> 1"); 134 | $display ("=================================================================="); 135 | 136 | for (j = 0; j < 10; j = j + 1) begin 137 | if (j == 4) begin 138 | intr_rq [3] = 1'b1; 139 | end 140 | if (j == 6) begin 141 | intr_rq [5] = 1'b1; 142 | end 143 | $display ("=================================================================="); 144 | $display ("Servicing Interrupt Number %d / 10", (j+1)); 145 | $display ("=================================================================="); 146 | $display ("Interrupt Request = %b", intr_rq); 147 | 148 | $display ("Waiting for interrupt from controller"); 149 | wait(intr_out); // Wait till controller gives interrupt. 150 | #60; // Wait for random cycles. Then Acknowledge interrupt. 151 | intr_in = 1'b0; // Ack Start 152 | #10 // Active for 1 clock. 153 | intr_in = 1'b1; // Ack End 154 | $display ("Interrupt Acknowledged by processor."); 155 | $display("Currently servicing %b", intr_bus_out[2:0]); 156 | $display ("The controller is driving the bus, %b", intr_bus_out); 157 | currentService = intr_bus_out[2:0]; 158 | intr_rq[currentService] = 1'b0; // Disable the interrupt serviced. This will be done by the interrupt master. 159 | 160 | // INFO: This is is an explicit assertion in verilog. 161 | // Used instead of assert because no free compiler I know can simulate system verilog. 162 | if (intr_bus_out == {5'b10011, currentService}) begin 163 | $display ("Proper address on the bus"); 164 | end else begin 165 | $display ("ERROR: Wrong address on the bus"); 166 | $finish; 167 | end 168 | 169 | #60 // At this point controller sends the address on the bus. 170 | intr_in = 1'b0; // Ack Start 171 | #10 // Active for 1 clock. 172 | intr_in = 1'b1; // Ack End 173 | $display ("Address acknowledged by processor"); 174 | 175 | #60 // Wait for random time. Work on interrupt. 176 | intr_bus_in = {5'b01100, currentService}; // Send the ACK to controller. 177 | intr_in = 1'b0; // Let the controller know this is an Ack. 178 | #10 // Active for 1 clock. 179 | intr_in = 1'b1; // Ack ends. 180 | $display ("ISR Routine complete by processor"); 181 | $display ("The processor is driving the bus, %b", intr_bus_in); 182 | $display ("==================================================================\n\n\n"); 183 | #100; 184 | end 185 | #100; 186 | 187 | $display ("=================================================================="); 188 | $display ("======== All tests completed successfully ========"); 189 | $display ("=================================================================="); 190 | $finish; 191 | 192 | end 193 | 194 | always 195 | #5 clk_in = ~clk_in; 196 | 197 | endmodule // INTR_CNTRL_TB 198 | 199 | -------------------------------------------------------------------------------- /src/intrCntrl.v: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | * 4 | * Filename : intrCntrl.v 5 | * 6 | * Description : Simple programmable interrupt controller module. It has 8 inputs 7 | * and supports polling mode and a custom priority mode. Please 8 | * refer to the README file for more information. 9 | * 10 | * Author : Aditya Shevade 11 | * 12 | * 13 | * License : This program is free software: you can redistribute it and/or modify 14 | * it under the terms of the GNU General Public License as published by 15 | * the Free Software Foundation, either version 3 of the License, or 16 | * (at your option) any later version. 17 | * 18 | * This program is distributed in the hope that it will be useful, 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 | * GNU General Public License for more details. 22 | * 23 | * You should have received a copy of the GNU General Public License 24 | * along with this program. If not, see . 25 | * 26 | * Created : 07/20/2011 27 | * 28 | ****************************************************************************** 29 | */ 30 | 31 | module INTR_CNTRL ( 32 | input wire clk_in, // Clock 33 | input wire rst_in, // Reset 34 | input wire [7:0] intr_rq, // Interrupt request 35 | inout wire [7:0] intr_bus, // Bidirectional data bus 36 | input wire intr_in, // Ack from processor 37 | output wire intr_out, // Interrupt to processor 38 | output wire bus_oe // Bus output enable 39 | ); 40 | 41 | localparam [3:0] S_Reset = 4'b0000, // Reset or start state 42 | S_GetCommands = 4'b0001, // Command mode - set polling or priority mode 43 | S_JumpIntMethod = 4'b0010, // Determine which mode was selected 44 | S_StartPolling = 4'b0011, // Polling each interrupt source periodically 45 | S_TxIntInfoPolling = 4'b0100, // Assert intr_out if interrupt present and send source ID on intr_bus 46 | S_AckTxInfoRxPolling = 4'b0101, // Wait for intr_in to go high 47 | S_AckISRDonePolling = 4'b0110, // De-assert intr_out signal 48 | S_StartPriority = 4'b0111, // Start priority check 49 | S_TxIntInfoPriority = 4'b1000, // Assert intr_out if interrupt present and sent source ID on intr_bus 50 | S_AckTxInfoRxPriority = 4'b1001, // Wait for intr_in to go high 51 | S_AckISRDonePriority = 4'b1010, // De-assert intr_out signal 52 | S_Reserved1 = 4'b1011, // Optional - Transition to S_Reset 53 | S_Reserved2 = 4'b1100, // Optional - Transition to S_Reset 54 | S_Reserved3 = 4'b1101, // Optional - Transition to S_Reset 55 | S_Reserved4 = 4'b1110, // Optional - Transition to S_Reset 56 | S_Reserved5 = 4'b1111; // Optional - Transition to S_Reset 57 | 58 | 59 | reg [3:0] state_reg, state_next; // State registers 60 | reg [1:0] cmdMode_reg, cmdMode_next; // Interrupt mode 61 | reg [1:0] cmdCycle_reg, cmdCycle_next; // Machine cycle 62 | reg [2:0] intrIndex_reg, intrIndex_next; // Cycle through all 8 in polling 63 | reg [2:0] intrPtr_reg, intrPtr_next; // Interrupt pointer 64 | reg [2:0] prior_table_next [0:7]; 65 | reg [2:0] prior_table_reg [0:7]; 66 | reg oe_reg, oe_next; // Output enable for the bidirectional bus 67 | reg [7:0] intrBus_reg, intrBus_next; // Bus <= register if using bus as output 68 | reg intrOut_reg, intrOut_next; // Interrupt output 69 | 70 | integer i; 71 | 72 | // 73 | // Main FSM of the controller. The state machine is clocked. The output and next state logic 74 | // are purely combinational. 75 | // 76 | always @ (posedge clk_in or posedge rst_in) begin 77 | 78 | if (rst_in) begin 79 | state_reg <= S_Reset; 80 | cmdMode_reg <= 2'b00; 81 | cmdCycle_reg <= 2'b00; 82 | oe_reg <= 1'b0; 83 | intrBus_reg <= 8'bzzzzzzzz; 84 | intrOut_reg <= 1'b0; 85 | intrIndex_reg <= 3'b000; 86 | intrPtr_reg <= 3'b000; 87 | for (i = 0; i < 8; i = i + 1) begin 88 | prior_table_reg[i] <= 3'b000; 89 | end 90 | end 91 | 92 | else begin 93 | state_reg <= state_next; 94 | cmdMode_reg <= cmdMode_next; 95 | cmdCycle_reg <= cmdCycle_next; 96 | intrBus_reg <= intrBus_next; 97 | intrOut_reg <= intrOut_next; 98 | oe_reg <= oe_next; 99 | intrIndex_reg <= intrIndex_next; 100 | intrPtr_reg <= intrPtr_next; 101 | for (i = 0; i < 8; i = i + 1) begin 102 | prior_table_reg[i] <= prior_table_next[i]; 103 | end 104 | end 105 | end 106 | 107 | // 108 | // The next state logic and the output functions. 109 | // 110 | always @(*) begin 111 | 112 | state_next = state_reg; 113 | cmdMode_next = cmdMode_reg; 114 | cmdCycle_next = cmdCycle_reg; 115 | oe_next = oe_reg; 116 | intrOut_next = intrOut_reg; 117 | intrBus_next = intrBus_reg; 118 | intrIndex_next = intrIndex_reg; 119 | intrPtr_next = intrPtr_reg; 120 | for (i = 0; i < 8; i = i + 1) begin 121 | prior_table_next[i] = prior_table_reg[i]; 122 | end 123 | 124 | case (state_reg) 125 | // Reset state, every variable is set to zero and the bus is tristated. 126 | S_Reset: begin // 4'b0000 127 | cmdMode_next = 2'b00; 128 | cmdCycle_next = 2'b00; 129 | intrIndex_next = 3'b000; 130 | intrPtr_next = 3'b000; 131 | for (i = 0; i < 8; i = i + 1) begin 132 | prior_table_next[i] = 3'b000; 133 | end 134 | //intrBus_next = 8'bzzzzzzzz; 135 | oe_next = 1'b0; 136 | 137 | state_next = S_GetCommands; // Wait for commands. 138 | end 139 | 140 | // Wait for commands. The possible commands are, 141 | // 142 | // 01 - Polling mode where the priorities are fixed. 143 | // 10 - Priority mode. In this mode the controller receives the priorities 144 | // for 4 cycles starting from the 2 highest to the lowest ones. 145 | // 146 | // Then set proper mode internally and start executing that sequence. 147 | // 148 | S_GetCommands: begin // 4'b0001 149 | oe_next = 1'b0; 150 | case (intr_bus[1:0]) 151 | 2'b01: begin // Polling mode. 152 | cmdMode_next = 2'b01; // Set mode to polling (internal). 153 | state_next = S_JumpIntMethod; // Once done, start proper interrupt sequence. 154 | end 155 | 156 | 2'b10: begin // Priority mode. 157 | case (cmdCycle_reg) 158 | 2'b00: begin 159 | prior_table_next[0] = intr_bus[7:5]; // Priority 0, highest priority. 160 | prior_table_next[1] = intr_bus[4:2]; // Priority 1 161 | state_next = S_GetCommands; 162 | cmdCycle_next = cmdCycle_reg + 1'b1; 163 | end 164 | 2'b01: begin 165 | prior_table_next[2] = intr_bus[7:5]; // Priority 2 166 | prior_table_next[3] = intr_bus[4:2]; // Priority 3 167 | state_next = S_GetCommands; 168 | cmdCycle_next = cmdCycle_reg + 1'b1; 169 | end 170 | 2'b10: begin 171 | prior_table_next[4] = intr_bus[7:5]; // Priority 4 172 | prior_table_next[5] = intr_bus[4:2]; // Priority 5 173 | state_next = S_GetCommands; 174 | cmdCycle_next = cmdCycle_reg + 1'b1; 175 | end 176 | 2'b11: begin 177 | prior_table_next[6] = intr_bus[7:5]; // Priority 6 178 | prior_table_next[7] = intr_bus[4:2]; // Priority 7, lowest priority. 179 | state_next = S_JumpIntMethod; // Once done, start proper interrupt sequence. 180 | cmdCycle_next = cmdCycle_reg + 1'b1; 181 | cmdMode_next = 2'b10; // Set mode to priority (internal). 182 | end 183 | default: begin 184 | state_next = S_GetCommands; // IMPORTANT: If there is any interruption in receiving 185 | cmdCycle_next = 2'b00; // priorities then the controller is reset. 186 | cmdMode_next = 2'b00; // Entire sequence must be restarted. 187 | end 188 | endcase 189 | 190 | end 191 | default: begin // Stay in the state till valid commands are entered. 192 | state_next = S_GetCommands; 193 | end 194 | endcase 195 | end 196 | 197 | // Command mode is set to either polling or priority in the last state. 198 | // Depending on that value, either the polling routine begins or the 199 | // priority routine begins. 200 | // 201 | S_JumpIntMethod: begin // 4'b0010 202 | intrIndex_next = 3'b000; 203 | intrPtr_next = 3'b000; 204 | 205 | case (cmdMode_reg) 206 | 2'b01: begin // Start polling. 207 | state_next = S_StartPolling; 208 | end 209 | 2'b10: begin // State priority. 210 | state_next = S_StartPriority; 211 | end 212 | default: begin // Invalid mode - reset the controller. 213 | state_next = S_Reset; 214 | end 215 | endcase 216 | 217 | //intrBus_next = 8'bzzzzzzzz; // The bus is tristated. 218 | oe_next = 1'b0; // Controller is not driving the bus. 219 | end 220 | 221 | // If the mode is polling then the controller enters this state. 222 | // The priorities are fixed in this mode. 223 | // It checks one source every clock cycle. If an interrupt input is active then 224 | // the output is set high and then the controller waits for an acknowledgement from the processor. 225 | // 226 | S_StartPolling: begin // 4'b0011 227 | if (intr_rq[intrIndex_reg]) begin // If the current interrupt source is active. 228 | intrOut_next = 1'b1; // Set the interrupt output bit to 1. 229 | state_next = S_TxIntInfoPolling; // Transmit the information about this interrupt. 230 | end 231 | else begin // If the current interrupt source is not active. 232 | intrOut_next = 1'b0; // Make sure interrupt output is zero, redundant. 233 | intrIndex_next = intrIndex_reg + 1; // Check the next interrupt source. 234 | end 235 | 236 | //intrBus_next = 8'bzzzzzzzz; // The bus is tristated. 237 | oe_next = 1'b0; // Controller is not driving the bus. 238 | end 239 | 240 | // If the interrupt is active then we next send the information about it to the processor. 241 | // This information is sent on the bidirectional bus. It is sent after the interrupt has been acknowledged. 242 | // 243 | // The processor receives the request, processes it and returns acknowledgement on intr_in. (High to Low). 244 | // Upon receiving this acknowledgement, the controller sends the information about the interrupt on the bus. 245 | // Processor then sends the acknowlegement back to the controller. This is checked in the S_AckTxInfoRxPolling state. 246 | // 247 | S_TxIntInfoPolling: begin // 4'b0100 248 | if (~intr_in) begin // intr_in is from the processor to the controller. 249 | intrOut_next = 1'b0; // If processor has acknowledged the interrupt, lower it. 250 | intrBus_next = {5'b01011, intrIndex_reg}; // 01011 is the control code that the lower 3 bits are the interrupt ID. 251 | oe_next = 1'b1; // Controller will drive the bus with this data. 252 | state_next = S_AckTxInfoRxPolling; // Go to acknowledge state and wait for the acknowledge. 253 | end // Wait until processor acknowledges the interrupt. Keep output high till that time. 254 | else 255 | state_next = S_TxIntInfoPolling; 256 | end 257 | 258 | // In the previous state, the processor had acknowledged the interrupt and the controller had sent the interrupt ID 259 | // to the processor. Upon receiving it, the processor again acknowledges it on the intr_in pin. (High to Low). 260 | // Once the processor acknowledges the address, the controller stops driving the bus and tristates it. 261 | // Then it waits for the processor to return when the interrupt is serviced. 262 | // 263 | S_AckTxInfoRxPolling: begin // 4'b0101 264 | if (~intr_in) begin // The processor has acknowledged the interrupt address. 265 | //intrBus_next = 8'bzzzzzzzz; // Tristate the bus. 266 | oe_next = 1'b0; // Controller no longer drives the bus. 267 | state_next = S_AckISRDonePolling; // Go do polling done state. 268 | end // Wait until processor acknowledges the address. Keep bus active till that time. 269 | end 270 | 271 | // Once the processor has acknowledged the interrupt and the address of the interrupt, 272 | // It will send the acknowledge on the bus once the interrupt has been serviced. 273 | // Wait till that information is received and then go back to poll next source. 274 | // 275 | S_AckISRDonePolling: begin // 4'b0110 276 | // If the proper source and condition has been acknowleged, check next interrupt. 277 | if ((~intr_in) && (intr_bus[7:3] == 5'b10100) && (intr_bus[2:0] == intrIndex_reg)) begin 278 | state_next = S_StartPolling; 279 | end 280 | // If the acknowledgement did not have proper condition codes then that is an error and 281 | // controller goes back to reset. 282 | else if ((~intr_in) && (intr_bus[7:3] != 5'b10100) && (intr_bus[2:0] != intrIndex_reg)) begin 283 | state_next = S_Reset; 284 | end 285 | else begin 286 | state_next = S_AckISRDonePolling; // Else wait in the current state. 287 | end 288 | end 289 | 290 | // If the mode is priority mode then the controller enters this state. 291 | // The priorities are decided by the 4 cycles received during initialization. 292 | // It checks one source every clock cycle. If an interrupt input is active then 293 | // the output is set high and then the controller waits for an acknowledgement from the processor. 294 | // 295 | // Instead of checking the sources from 0 to 7, it checks the internal storage sorted according to 296 | // the priorities received during the initialization. 297 | // 298 | S_StartPriority: begin // 4'b0111 299 | if (intr_rq[prior_table_reg[0]]) begin // Check if the highest priority source is active. 300 | intrPtr_next = prior_table_reg[0]; // If the highest priority interrupt is active, 301 | intrOut_next = 1'b1; // set the output high. 302 | state_next = S_TxIntInfoPriority; // Go wait for acknowledgement. 303 | end 304 | 305 | else if (intr_rq[prior_table_reg[1]]) begin // Else check the next highest priority. 306 | intrPtr_next = prior_table_reg[1]; // Continue as above. 307 | intrOut_next = 1'b1; 308 | state_next = S_TxIntInfoPriority; 309 | end 310 | 311 | else if (intr_rq[prior_table_reg[2]]) begin 312 | intrPtr_next = prior_table_reg[2]; 313 | intrOut_next = 1'b1; 314 | state_next = S_TxIntInfoPriority; 315 | end 316 | 317 | else if (intr_rq[prior_table_reg[3]]) begin 318 | intrPtr_next = prior_table_reg[3]; 319 | intrOut_next = 1'b1; 320 | state_next = S_TxIntInfoPriority; 321 | end 322 | 323 | else if (intr_rq[prior_table_reg[4]]) begin 324 | intrPtr_next = prior_table_reg[4]; 325 | intrOut_next = 1'b1; 326 | state_next = S_TxIntInfoPriority; 327 | end 328 | 329 | else if (intr_rq[prior_table_reg[5]]) begin 330 | intrPtr_next = prior_table_reg[5]; 331 | intrOut_next = 1'b1; 332 | state_next = S_TxIntInfoPriority; 333 | end 334 | 335 | else if (intr_rq[prior_table_reg[6]]) begin 336 | intrPtr_next = prior_table_reg[6]; 337 | intrOut_next = 1'b1; 338 | state_next = S_TxIntInfoPriority; 339 | end 340 | 341 | else if (intr_rq[prior_table_reg[7]]) begin 342 | intrPtr_next = prior_table_reg[7]; 343 | intrOut_next = 1'b1; 344 | state_next = S_TxIntInfoPriority; 345 | end 346 | 347 | else begin // If none of the sources is active, then wait 348 | state_next = S_StartPriority; // till one of them is active. 349 | end 350 | 351 | //intrBus_next = 8'bzzzzzzzz; // The bus is tristated. 352 | oe_next = 1'b0; // Controller is not driving the bus. 353 | end 354 | 355 | // Once the interrupt output is set active, the controller then waits for an acknowledgement from the processor. 356 | // The processor acknowledges the interrupt by the intr_in pin (High to Low). 357 | // 358 | // Once the interrupt is acknowledged, we have to send the information about the interrupt to the processor. 359 | // It's sent on the bidirectional bus along with some condition code bits. 360 | // 361 | S_TxIntInfoPriority: begin // 4'b1000 362 | if (~intr_in) begin // If the processor has acknowledged the interrupt. 363 | intrOut_next = 1'b0; // Make the interrupt output low. 364 | intrBus_next = {5'b10011, intrPtr_reg}; // Send the address and the condition codes. 365 | oe_next = 1'b1; // Controller is driving the bus. 366 | state_next = S_AckTxInfoRxPriority; // Wait for address acknowledgement from the processor. 367 | end // Else wait till interrupt is acknowledged. 368 | end 369 | 370 | // After the address is sent to the processor, the controller again waits for an acknowledgement from the processor. 371 | // It's again given on the intr_in pin (High to Low). 372 | // 373 | // After receiving this acknowledgement, the controller then waits for the processor to finish executing the 374 | // interrupt service routine. 375 | // 376 | S_AckTxInfoRxPriority: begin // 4'b1001 377 | if (~intr_in) begin // Address has been acknowledged. 378 | //intrBus_next = 8'bzzzzzzzz; // The bus is tristated. 379 | oe_next = 1'b0; // Controller no longer drives the bus. 380 | state_next = S_AckISRDonePriority; // Go and wait for interrupt to be serviced. 381 | end 382 | end 383 | 384 | // Once the processor acknowledges that the interrupt has been serviced, it sends condition codes 385 | // along with the interrupt priority to the controller. 386 | // 387 | // It also acknowledges this on the intr_in pin (High to Low). 388 | // Once this has been acknowledged, the controller returns to check the interrrupt sources. 389 | S_AckISRDonePriority: begin // 4'b1010 390 | // If the proper source and condition has been acknowleged, check next interrupt. 391 | if ((~intr_in) && (intr_bus[7:3] == 5'b01100) && (intr_bus[2:0] == intrPtr_reg)) begin 392 | state_next = S_StartPriority; 393 | end 394 | // Else, the controller assumes this to be an error. (If the condition codes are wrong). 395 | // In that case it returns to reset state. 396 | else if ((~intr_in) && (intr_bus[7:3] != 5'b01100) && (intr_bus[2:0] != intrPtr_reg)) begin 397 | state_next = S_Reset; 398 | end 399 | else begin 400 | state_next = S_AckISRDonePriority; // Else wait in the current state. 401 | end 402 | end 403 | 404 | // If the state bits are invalid then go to reset. 405 | default: begin 406 | state_next = S_Reset; 407 | //intrBus_next = 8'bzzzzzzzz; 408 | oe_next = 1'b0; 409 | end 410 | endcase 411 | end 412 | 413 | // Interrupt output. It's the same as the intrOut_reg but done like this for clarity. 414 | assign intr_out = intrOut_reg; 415 | // Bus is bidirectional. oe (output enable) decides if the controller is driving it 416 | // or is expecting input on it. 417 | assign intr_bus = (oe_reg) ? intrBus_reg : 8'bzzzzzzzz; 418 | // Used by the testbench. This signal tells the processor if the bus is being actively 419 | // driven by the controller. 420 | assign bus_oe = oe_reg; 421 | 422 | endmodule // INTR_CNTRL 423 | 424 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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To "grant" such a patent license to a 496 | party means to make such an agreement or commitment not to enforce a 497 | patent against the party. 498 | 499 | If you convey a covered work, knowingly relying on a patent license, 500 | and the Corresponding Source of the work is not available for anyone 501 | to copy, free of charge and under the terms of this License, through a 502 | publicly available network server or other readily accessible means, 503 | then you must either (1) cause the Corresponding Source to be so 504 | available, or (2) arrange to deprive yourself of the benefit of the 505 | patent license for this particular work, or (3) arrange, in a manner 506 | consistent with the requirements of this License, to extend the patent 507 | license to downstream recipients. "Knowingly relying" means you have 508 | actual knowledge that, but for the patent license, your conveying the 509 | covered work in a country, or your recipient's use of the covered work 510 | in a country, would infringe one or more identifiable patents in that 511 | country that you have reason to believe are valid. 512 | 513 | If, pursuant to or in connection with a single transaction or 514 | arrangement, you convey, or propagate by procuring conveyance of, a 515 | covered work, and grant a patent license to some of the parties 516 | receiving the covered work authorizing them to use, propagate, modify 517 | or convey a specific copy of the covered work, then the patent license 518 | you grant is automatically extended to all recipients of the covered 519 | work and works based on it. 520 | 521 | A patent license is "discriminatory" if it does not include within 522 | the scope of its coverage, prohibits the exercise of, or is 523 | conditioned on the non-exercise of one or more of the rights that are 524 | specifically granted under this License. You may not convey a covered 525 | work if you are a party to an arrangement with a third party that is 526 | in the business of distributing software, under which you make payment 527 | to the third party based on the extent of your activity of conveying 528 | the work, and under which the third party grants, to any of the 529 | parties who would receive the covered work from you, a discriminatory 530 | patent license (a) in connection with copies of the covered work 531 | conveyed by you (or copies made from those copies), or (b) primarily 532 | for and in connection with specific products or compilations that 533 | contain the covered work, unless you entered into that arrangement, 534 | or that patent license was granted, prior to 28 March 2007. 535 | 536 | Nothing in this License shall be construed as excluding or limiting 537 | any implied license or other defenses to infringement that may 538 | otherwise be available to you under applicable patent law. 539 | 540 | 12. No Surrender of Others' Freedom. 541 | 542 | If conditions are imposed on you (whether by court order, agreement or 543 | otherwise) that contradict the conditions of this License, they do not 544 | excuse you from the conditions of this License. If you cannot convey a 545 | covered work so as to satisfy simultaneously your obligations under this 546 | License and any other pertinent obligations, then as a consequence you may 547 | not convey it at all. For example, if you agree to terms that obligate you 548 | to collect a royalty for further conveying from those to whom you convey 549 | the Program, the only way you could satisfy both those terms and this 550 | License would be to refrain entirely from conveying the Program. 551 | 552 | 13. Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | 676 | --------------------------------------------------------------------------------