├── IntelMausiEthernet.xcodeproj ├── project.pbxproj ├── project.xcworkspace │ ├── contents.xcworkspacedata │ └── xcshareddata │ │ ├── IDEWorkspaceChecks.plist │ │ ├── IntelMausiEthernet.xccheckout │ │ └── IntelMausiEthernet.xcscmblueprint └── xcuserdata │ ├── dany.xcuserdatad │ ├── xcdebugger │ │ └── Breakpoints_v2.xcbkptlist │ └── xcschemes │ │ └── xcschememanagement.plist │ └── laura.xcuserdatad │ ├── xcdebugger │ └── Breakpoints_v2.xcbkptlist │ └── xcschemes │ ├── IntelMausiEthernet.xcscheme │ ├── IntelMausiEthernetV2.xcscheme │ └── xcschememanagement.plist ├── IntelMausiEthernet ├── APPLE_LICENSE ├── IONetworkController.h ├── IONetworkInterface.h ├── IntelMausiEthernet (original 2).cpp ├── IntelMausiEthernet (original).cpp ├── IntelMausiEthernet-Info.plist ├── IntelMausiEthernet.cpp ├── IntelMausiEthernet.h ├── IntelMausiEthernetV2-Prefix.pch ├── IntelMausiHardware.cpp ├── IntelMausiSetup.cpp ├── defines.h ├── e1000.h ├── en.lproj │ └── InfoPlist.strings ├── ethtool.c ├── ethtool.h ├── gpl.txt ├── hw.h ├── ich8lan.c ├── ich8lan.h ├── if_ether.h ├── linux.h ├── mac.c ├── mac.h ├── manage.c ├── manage.h ├── mdio.h ├── mii.h ├── netdev.c ├── nvm.c ├── nvm.h ├── param.c ├── phy.c ├── phy.h ├── ptp.c ├── regs.h ├── uapi-ethtool.h ├── uapi-ip.h ├── uapi-mdio.h ├── uapi-mii.h └── uapi-pci_regs.h ├── README.md ├── build └── Products │ ├── .DS_Store │ ├── Debug │ ├── .DS_Store │ └── IntelMausiEthernet.kext │ │ └── Contents │ │ ├── Info.plist │ │ └── MacOS │ │ └── IntelMausiEthernet │ ├── IntelMausiEthernet.build │ └── Debug │ │ └── IntelMausiEthernet.build │ │ ├── DerivedSources │ │ └── IntelMausiEthernet_info.c │ │ ├── IntelMausiEthernet-all-non-framework-target-headers.hmap │ │ ├── IntelMausiEthernet-all-target-headers.hmap │ │ ├── IntelMausiEthernet-generated-files.hmap │ │ ├── IntelMausiEthernet-own-target-headers.hmap │ │ ├── IntelMausiEthernet-project-headers.hmap │ │ ├── IntelMausiEthernet.hmap │ │ ├── Objects-normal │ │ └── x86_64 │ │ │ ├── IntelMausiEthernet.LinkFileList │ │ │ ├── IntelMausiEthernet.d │ │ │ ├── IntelMausiEthernet.dia │ │ │ ├── IntelMausiEthernet.o │ │ │ ├── IntelMausiEthernet_dependency_info.dat │ │ │ ├── IntelMausiEthernet_info.d │ │ │ ├── IntelMausiEthernet_info.dia │ │ │ ├── IntelMausiEthernet_info.o │ │ │ ├── IntelMausiHardware.d │ │ │ ├── IntelMausiHardware.dia │ │ │ ├── IntelMausiHardware.o │ │ │ ├── IntelMausiSetup.d │ │ │ ├── IntelMausiSetup.dia │ │ │ ├── IntelMausiSetup.o │ │ │ ├── ich8lan.d │ │ │ ├── ich8lan.dia │ │ │ ├── ich8lan.o │ │ │ ├── mac.d │ │ │ ├── mac.dia │ │ │ ├── mac.o │ │ │ ├── manage.d │ │ │ ├── manage.dia │ │ │ ├── manage.o │ │ │ ├── netdev.d │ │ │ ├── netdev.dia │ │ │ ├── netdev.o │ │ │ ├── nvm.d │ │ │ ├── nvm.dia │ │ │ ├── nvm.o │ │ │ ├── phy.d │ │ │ ├── phy.dia │ │ │ └── phy.o │ │ ├── dgph │ │ └── dgph~ │ └── SharedPrecompiledHeaders │ ├── IntelMausiEthernetV2-Prefix-aehmnbmscxgyxrghbcixnnfupoxa │ ├── IntelMausiEthernetV2-Prefix.pch.d │ ├── IntelMausiEthernetV2-Prefix.pch.data │ ├── IntelMausiEthernetV2-Prefix.pch.dia │ ├── IntelMausiEthernetV2-Prefix.pch.pch │ └── IntelMausiEthernetV2-Prefix.pch.pch.hash-criteria │ └── IntelMausiEthernetV2-Prefix-ahdzbwmvtwqyajdaicnychgmvcqv │ ├── IntelMausiEthernetV2-Prefix.pch.d │ ├── IntelMausiEthernetV2-Prefix.pch.data │ ├── IntelMausiEthernetV2-Prefix.pch.dia │ ├── IntelMausiEthernetV2-Prefix.pch.pch │ └── IntelMausiEthernetV2-Prefix.pch.pch.hash-criteria ├── makefile └── print_version.sh /IntelMausiEthernet.xcodeproj/project.xcworkspace/contents.xcworkspacedata: -------------------------------------------------------------------------------- 1 | 2 | 4 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/project.xcworkspace/xcshareddata/IDEWorkspaceChecks.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | IDEDidComputeMac32BitWarning 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/project.xcworkspace/xcshareddata/IntelMausiEthernet.xccheckout: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | IDESourceControlProjectFavoriteDictionaryKey 6 | 7 | IDESourceControlProjectIdentifier 8 | 33F44C10-D9E7-4DC9-A94F-028739655760 9 | IDESourceControlProjectName 10 | IntelMausiEthernet 11 | IDESourceControlProjectOriginsDictionary 12 | 13 | 322B76FC62564D70D3D2B79682113A4F1191D2DD 14 | https://github.com/Mieze/IntelMausiEthernet.git 15 | 52FD44A8D7C2885B44C325DC0C12115B6E4CC996 16 | https://github.com/Mieze/RTL8111_driver_for_OS_X.git 17 | CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E 18 | https://github.com/Mieze/AtherosE2200Ethernet.git 19 | 20 | IDESourceControlProjectPath 21 | IntelMausiEthernet.xcodeproj 22 | IDESourceControlProjectRelativeInstallPathDictionary 23 | 24 | 322B76FC62564D70D3D2B79682113A4F1191D2DD 25 | ../.. 26 | 52FD44A8D7C2885B44C325DC0C12115B6E4CC996 27 | ../../../RealtekRTL8111 28 | CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E 29 | ../../../AtherosE2200Ethernet 30 | 31 | IDESourceControlProjectURL 32 | https://github.com/Mieze/IntelMausiEthernet.git 33 | IDESourceControlProjectVersion 34 | 111 35 | IDESourceControlProjectWCCIdentifier 36 | 322B76FC62564D70D3D2B79682113A4F1191D2DD 37 | IDESourceControlProjectWCConfigurations 38 | 39 | 40 | IDESourceControlRepositoryExtensionIdentifierKey 41 | public.vcs.git 42 | IDESourceControlWCCIdentifierKey 43 | CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E 44 | IDESourceControlWCCName 45 | AtherosE2200Ethernet 46 | 47 | 48 | IDESourceControlRepositoryExtensionIdentifierKey 49 | public.vcs.git 50 | IDESourceControlWCCIdentifierKey 51 | 322B76FC62564D70D3D2B79682113A4F1191D2DD 52 | IDESourceControlWCCName 53 | IntelMausiEthernet 54 | 55 | 56 | IDESourceControlRepositoryExtensionIdentifierKey 57 | public.vcs.git 58 | IDESourceControlWCCIdentifierKey 59 | 52FD44A8D7C2885B44C325DC0C12115B6E4CC996 60 | IDESourceControlWCCName 61 | RealtekRTL8111 62 | 63 | 64 | 65 | 66 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/project.xcworkspace/xcshareddata/IntelMausiEthernet.xcscmblueprint: -------------------------------------------------------------------------------- 1 | { 2 | "DVTSourceControlWorkspaceBlueprintPrimaryRemoteRepositoryKey" : "322B76FC62564D70D3D2B79682113A4F1191D2DD", 3 | "DVTSourceControlWorkspaceBlueprintWorkingCopyRepositoryLocationsKey" : { 4 | 5 | }, 6 | "DVTSourceControlWorkspaceBlueprintWorkingCopyStatesKey" : { 7 | "CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E" : 0, 8 | "322B76FC62564D70D3D2B79682113A4F1191D2DD" : 0, 9 | "52FD44A8D7C2885B44C325DC0C12115B6E4CC996" : 0 10 | }, 11 | "DVTSourceControlWorkspaceBlueprintIdentifierKey" : "33F44C10-D9E7-4DC9-A94F-028739655760", 12 | "DVTSourceControlWorkspaceBlueprintWorkingCopyPathsKey" : { 13 | "CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E" : "AtherosE2200Ethernet\/", 14 | "322B76FC62564D70D3D2B79682113A4F1191D2DD" : "IntelMausiEthernet\/", 15 | "52FD44A8D7C2885B44C325DC0C12115B6E4CC996" : "RealtekRTL8111\/" 16 | }, 17 | "DVTSourceControlWorkspaceBlueprintNameKey" : "IntelMausiEthernet", 18 | "DVTSourceControlWorkspaceBlueprintVersion" : 204, 19 | "DVTSourceControlWorkspaceBlueprintRelativePathToProjectKey" : "IntelMausiEthernet.xcodeproj", 20 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoriesKey" : [ 21 | { 22 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryURLKey" : "https:\/\/github.com\/Mieze\/IntelMausiEthernet.git", 23 | "DVTSourceControlWorkspaceBlueprintRemoteRepositorySystemKey" : "com.apple.dt.Xcode.sourcecontrol.Git", 24 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryIdentifierKey" : "322B76FC62564D70D3D2B79682113A4F1191D2DD" 25 | }, 26 | { 27 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryURLKey" : "https:\/\/github.com\/Mieze\/RTL8111_driver_for_OS_X.git", 28 | "DVTSourceControlWorkspaceBlueprintRemoteRepositorySystemKey" : "com.apple.dt.Xcode.sourcecontrol.Git", 29 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryIdentifierKey" : "52FD44A8D7C2885B44C325DC0C12115B6E4CC996" 30 | }, 31 | { 32 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryURLKey" : "https:\/\/github.com\/Mieze\/AtherosE2200Ethernet.git", 33 | "DVTSourceControlWorkspaceBlueprintRemoteRepositorySystemKey" : "com.apple.dt.Xcode.sourcecontrol.Git", 34 | "DVTSourceControlWorkspaceBlueprintRemoteRepositoryIdentifierKey" : "CDCA2184861B0BBA9C5ECB0C5CE4459094A5CB2E" 35 | } 36 | ] 37 | } -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/dany.xcuserdatad/xcdebugger/Breakpoints_v2.xcbkptlist: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/dany.xcuserdatad/xcschemes/xcschememanagement.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | SchemeUserState 6 | 7 | IntelMausiEthernet.xcscheme 8 | 9 | orderHint 10 | 0 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/laura.xcuserdatad/xcdebugger/Breakpoints_v2.xcbkptlist: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/laura.xcuserdatad/xcschemes/IntelMausiEthernet.xcscheme: -------------------------------------------------------------------------------- 1 | 2 | 5 | 8 | 9 | 15 | 21 | 22 | 23 | 24 | 25 | 30 | 31 | 32 | 33 | 34 | 35 | 45 | 46 | 52 | 53 | 54 | 55 | 56 | 57 | 63 | 64 | 66 | 67 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/laura.xcuserdatad/xcschemes/IntelMausiEthernetV2.xcscheme: -------------------------------------------------------------------------------- 1 | 2 | 5 | 8 | 9 | 15 | 21 | 22 | 23 | 24 | 25 | 30 | 31 | 32 | 33 | 34 | 35 | 45 | 46 | 52 | 53 | 54 | 55 | 56 | 57 | 63 | 64 | 70 | 71 | 72 | 73 | 75 | 76 | 79 | 80 | 81 | -------------------------------------------------------------------------------- /IntelMausiEthernet.xcodeproj/xcuserdata/laura.xcuserdatad/xcschemes/xcschememanagement.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | SchemeUserState 6 | 7 | IntelMausiEthernet.xcscheme 8 | 9 | orderHint 10 | 0 11 | 12 | IntelMausiEthernetV2.xcscheme 13 | 14 | orderHint 15 | 1 16 | 17 | 18 | SuppressBuildableAutocreation 19 | 20 | D3CB5B751A4394A800A37FAA 21 | 22 | primary 23 | 24 | 25 | D3F3189D1AB3B0E300DA9D9A 26 | 27 | primary 28 | 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /IntelMausiEthernet/IntelMausiEthernet-Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | CFBundleDevelopmentRegion 6 | English 7 | CFBundleExecutable 8 | ${EXECUTABLE_NAME} 9 | CFBundleIconFile 10 | 11 | CFBundleIdentifier 12 | $(PRODUCT_BUNDLE_IDENTIFIER) 13 | CFBundleInfoDictionaryVersion 14 | 6.0 15 | CFBundleName 16 | ${PRODUCT_NAME} 17 | CFBundlePackageType 18 | KEXT 19 | CFBundleShortVersionString 20 | $MODULE_VERSION 21 | CFBundleSignature 22 | ???? 23 | CFBundleVersion 24 | $MODULE_VERSION 25 | IOKitPersonalities 26 | 27 | IntelMausi 28 | 29 | CFBundleIdentifier 30 | com.insanelymac.${PRODUCT_NAME:rfc1034identifier} 31 | Driver_Version 32 | $MODULE_VERSION 33 | IOClass 34 | IntelMausi 35 | IOPCIMatch 36 | 0x10EA8086 0x10EB8086 0x10EF8086 0x10F08086 0x15028086 0x15038086 0x153A8086 0x153B8086 0x155A8086 0x15598086 0x15A08086 0x15A18086 0x15A28086 0x15A38086 0x156F8086 0x15708086 0x15B78086 0x15B88086 0x15D78086 0x15D88086 0x15E38086 0x15D68086 0x15BD8086 0x15BE8086 0x15BB8086 0x15BC8086 0x15DF8086 0x15E08086 0x15E18086 0x15E28086 37 | IOProbeScore 38 | 1000 39 | IOProviderClass 40 | IOPCIDevice 41 | enableCSO6 42 | 43 | enableTSO4 44 | 45 | enableTSO6 46 | 47 | maxIntrRate 48 | 7000 49 | 50 | 51 | NSHumanReadableCopyright 52 | Copyright © 2014 Laura Müller. All rights reserved. 53 | OSBundleLibraries 54 | 55 | com.apple.iokit.IONetworkingFamily 56 | 1.5.0 57 | com.apple.iokit.IOPCIFamily 58 | 1.7 59 | com.apple.kpi.bsd 60 | 8.10.0 61 | com.apple.kpi.iokit 62 | 8.10.0 63 | com.apple.kpi.libkern 64 | 8.10.0 65 | com.apple.kpi.mach 66 | 8.10.0 67 | 68 | OSBundleRequired 69 | Network-Root 70 | 71 | 72 | -------------------------------------------------------------------------------- /IntelMausiEthernet/IntelMausiEthernetV2-Prefix.pch: -------------------------------------------------------------------------------- 1 | // 2 | // Prefix header for all source files of the 'IntelMausi' target in the 'IntelMausiEthernet' project 3 | // 4 | 5 | #define __PRIVATE_SPI__ 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif // __cplusplus 10 | 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | 27 | #ifdef __cplusplus 28 | } 29 | #endif // __cplusplus 30 | 31 | #ifdef __cplusplus 32 | 33 | typedef u_int32_t ifnet_ctl_cmd_t; 34 | 35 | #include "IONetworkInterface.h" 36 | #include "IONetworkController.h" 37 | 38 | #include 39 | #include 40 | #include 41 | #include 42 | #include 43 | #include 44 | #include 45 | #include 46 | #include 47 | #include 48 | #include 49 | #include 50 | #include 51 | 52 | #endif // __cplusplus 53 | 54 | 55 | #include "linux.h" 56 | #include "if_ether.h" 57 | #include "uapi-ethtool.h" 58 | #include "ethtool.h" 59 | #include "uapi-mii.h" 60 | #include "mii.h" 61 | #include "uapi-mdio.h" 62 | #include "mdio.h" 63 | #include "uapi-ip.h" 64 | #include "uapi-pci_regs.h" 65 | -------------------------------------------------------------------------------- /IntelMausiEthernet/IntelMausiSetup.cpp: -------------------------------------------------------------------------------- 1 | /* IntelMausiSetup.cpp -- IntelMausi driver data structure setup. 2 | * 3 | * Copyright (c) 2014 Laura Müller 4 | * All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms of the GNU General Public License as published by the Free 8 | * Software Foundation; either version 2 of the License, or (at your option) 9 | * any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, but WITHOUT 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 | * more details. 15 | * 16 | * Driver for Intel PCIe gigabit ethernet controllers. 17 | * 18 | * This driver is based on Intel's E1000e driver for Linux. 19 | */ 20 | 21 | 22 | #include "IntelMausiEthernet.h" 23 | 24 | #pragma mark --- private data --- 25 | 26 | static IOMediumType mediumTypeArray[MEDIUM_INDEX_COUNT] = { 27 | kIOMediumEthernetAuto, 28 | (kIOMediumEthernet10BaseT | kIOMediumOptionHalfDuplex), 29 | (kIOMediumEthernet10BaseT | kIOMediumOptionFullDuplex), 30 | (kIOMediumEthernet100BaseTX | kIOMediumOptionHalfDuplex), 31 | (kIOMediumEthernet100BaseTX | kIOMediumOptionFullDuplex), 32 | (kIOMediumEthernet100BaseTX | kIOMediumOptionFullDuplex | kIOMediumOptionFlowControl), 33 | (kIOMediumEthernet1000BaseT | kIOMediumOptionFullDuplex), 34 | (kIOMediumEthernet1000BaseT | kIOMediumOptionFullDuplex | kIOMediumOptionFlowControl), 35 | (kIOMediumEthernet1000BaseT | kIOMediumOptionFullDuplex | kIOMediumOptionEEE), 36 | (kIOMediumEthernet1000BaseT | kIOMediumOptionFullDuplex | kIOMediumOptionFlowControl | kIOMediumOptionEEE), 37 | (kIOMediumEthernet100BaseTX | kIOMediumOptionFullDuplex | kIOMediumOptionEEE), 38 | (kIOMediumEthernet100BaseTX | kIOMediumOptionFullDuplex | kIOMediumOptionFlowControl | kIOMediumOptionEEE) 39 | }; 40 | 41 | static UInt32 mediumSpeedArray[MEDIUM_INDEX_COUNT] = { 42 | 0, 43 | 10 * MBit, 44 | 10 * MBit, 45 | 100 * MBit, 46 | 100 * MBit, 47 | 100 * MBit, 48 | 1000 * MBit, 49 | 1000 * MBit, 50 | 1000 * MBit, 51 | 1000 * MBit, 52 | 100 * MBit, 53 | 100 * MBit 54 | }; 55 | 56 | static const char *onName = "enabled"; 57 | static const char *offName = "disabled"; 58 | 59 | #pragma mark --- data structure initialization methods --- 60 | 61 | void IntelMausi::getParams() 62 | { 63 | OSString *versionString; 64 | OSNumber *intrRate; 65 | OSBoolean *tso4; 66 | OSBoolean *tso6; 67 | OSBoolean *csoV6; 68 | UInt32 newIntrRate; 69 | 70 | tso4 = OSDynamicCast(OSBoolean, getProperty(kEnableTSO4Name)); 71 | enableTSO4 = (tso4) ? tso4->getValue() : false; 72 | 73 | IOLog("Ethernet [IntelMausi]: TCP/IPv4 segmentation offload %s.\n", enableTSO4 ? onName : offName); 74 | 75 | tso6 = OSDynamicCast(OSBoolean, getProperty(kEnableTSO6Name)); 76 | enableTSO6 = (tso6) ? tso6->getValue() : false; 77 | 78 | IOLog("Ethernet [IntelMausi]: TCP/IPv6 segmentation offload %s.\n", enableTSO6 ? onName : offName); 79 | 80 | csoV6 = OSDynamicCast(OSBoolean, getProperty(kEnableCSO6Name)); 81 | enableCSO6 = (csoV6) ? csoV6->getValue() : false; 82 | 83 | IOLog("Ethernet [IntelMausi]: TCP/IPv6 checksum offload %s.\n", enableCSO6 ? onName : offName); 84 | 85 | intrRate = OSDynamicCast(OSNumber, getProperty(kIntrRateName)); 86 | newIntrRate = 5000; 87 | 88 | versionString = OSDynamicCast(OSString, getProperty(kDriverVersionName)); 89 | 90 | if (intrRate) 91 | newIntrRate = intrRate->unsigned32BitValue(); 92 | 93 | if (newIntrRate < 2500) 94 | newIntrRate = 2500; 95 | else if (newIntrRate > 10000) 96 | newIntrRate = 10000; 97 | 98 | intrThrValue = (3906250 / (newIntrRate + 1)); 99 | 100 | if (versionString) 101 | IOLog("Ethernet [IntelMausi]: Version %s using max interrupt rate %u.\n", versionString->getCStringNoCopy(), newIntrRate); 102 | else 103 | IOLog("Ethernet [IntelMausi]: Using max interrupt rate %u.\n", newIntrRate); 104 | 105 | DebugLog("Ethernet [IntelMausi]: intrThrValue=%u\n", intrThrValue); 106 | } 107 | 108 | bool IntelMausi::setupMediumDict() 109 | { 110 | IONetworkMedium *medium; 111 | UInt32 count; 112 | UInt32 i; 113 | bool result = false; 114 | 115 | if (adapterData.hw.phy.media_type == e1000_media_type_fiber) { 116 | count = 1; 117 | } else if (adapterData.flags2 & FLAG2_HAS_EEE) { 118 | count = MEDIUM_INDEX_COUNT; 119 | } else { 120 | count = MEDIUM_INDEX_COUNT - 4; 121 | } 122 | mediumDict = OSDictionary::withCapacity(count + 1); 123 | 124 | if (mediumDict) { 125 | for (i = MEDIUM_INDEX_AUTO; i < count; i++) { 126 | medium = IONetworkMedium::medium(mediumTypeArray[i], mediumSpeedArray[i], 0, i); 127 | 128 | if (!medium) 129 | goto error1; 130 | 131 | result = IONetworkMedium::addMedium(mediumDict, medium); 132 | medium->release(); 133 | 134 | if (!result) 135 | goto error1; 136 | 137 | mediumTable[i] = medium; 138 | } 139 | } 140 | result = publishMediumDictionary(mediumDict); 141 | 142 | if (!result) 143 | goto error1; 144 | 145 | done: 146 | return result; 147 | 148 | error1: 149 | IOLog("Ethernet [IntelMausi]: Error creating medium dictionary.\n"); 150 | mediumDict->release(); 151 | 152 | for (i = MEDIUM_INDEX_AUTO; i < MEDIUM_INDEX_COUNT; i++) 153 | mediumTable[i] = NULL; 154 | 155 | goto done; 156 | } 157 | 158 | bool IntelMausi::initEventSources(IOService *provider) 159 | { 160 | IOReturn intrResult; 161 | int msiIndex = -1; 162 | int intrIndex = 0; 163 | int intrType = 0; 164 | bool result = false; 165 | 166 | txQueue = reinterpret_cast(getOutputQueue()); 167 | 168 | if (txQueue == NULL) { 169 | IOLog("Ethernet [IntelMausi]: Failed to get output queue.\n"); 170 | goto done; 171 | } 172 | txQueue->retain(); 173 | 174 | while ((intrResult = pciDevice->getInterruptType(intrIndex, &intrType)) == kIOReturnSuccess) { 175 | if (intrType & kIOInterruptTypePCIMessaged){ 176 | msiIndex = intrIndex; 177 | break; 178 | } 179 | intrIndex++; 180 | } 181 | if (msiIndex != -1) { 182 | DebugLog("Ethernet [IntelMausi]: MSI interrupt index: %d\n", msiIndex); 183 | 184 | interruptSource = IOInterruptEventSource::interruptEventSource(this, OSMemberFunctionCast(IOInterruptEventSource::Action, this, &IntelMausi::interruptOccurred), provider, msiIndex); 185 | } 186 | if (!interruptSource) { 187 | IOLog("Ethernet [IntelMausi]: MSI interrupt could not be enabled.\n"); 188 | goto error1; 189 | } 190 | workLoop->addEventSource(interruptSource); 191 | 192 | timerSource = IOTimerEventSource::timerEventSource(this, OSMemberFunctionCast(IOTimerEventSource::Action, this, &IntelMausi::timerAction)); 193 | 194 | if (!timerSource) { 195 | IOLog("Ethernet [IntelMausi]: Failed to create IOTimerEventSource.\n"); 196 | goto error2; 197 | } 198 | workLoop->addEventSource(timerSource); 199 | 200 | result = true; 201 | 202 | done: 203 | return result; 204 | 205 | error2: 206 | workLoop->removeEventSource(interruptSource); 207 | RELEASE(interruptSource); 208 | 209 | error1: 210 | IOLog("Ethernet [IntelMausi]: Error initializing event sources.\n"); 211 | txQueue->release(); 212 | txQueue = NULL; 213 | goto done; 214 | } 215 | 216 | bool IntelMausi::setupDMADescriptors() 217 | { 218 | IODMACommand::Segment64 seg; 219 | IOPhysicalSegment rxSegment; 220 | mbuf_t spareMbuf[kRxNumSpareMbufs]; 221 | mbuf_t m; 222 | UInt64 offset = 0; 223 | UInt32 numSegs = 1; 224 | UInt32 i; 225 | UInt32 n; 226 | bool result = false; 227 | 228 | /* Create transmitter descriptor array. */ 229 | txBufDesc = IOBufferMemoryDescriptor::inTaskWithPhysicalMask(kernel_task, (kIODirectionInOut | kIOMemoryPhysicallyContiguous | kIOMapInhibitCache), kTxDescSize, 0xFFFFFFFFFFFFF000ULL); 230 | 231 | if (!txBufDesc) { 232 | IOLog("Ethernet [IntelMausi]: Couldn't alloc txBufDesc.\n"); 233 | goto done; 234 | } 235 | if (txBufDesc->prepare() != kIOReturnSuccess) { 236 | IOLog("Ethernet [IntelMausi]: txBufDesc->prepare() failed.\n"); 237 | goto error1; 238 | } 239 | txDescArray = (struct e1000_data_desc *)txBufDesc->getBytesNoCopy(); 240 | 241 | /* I don't know if it's really necessary but the documenation says so and Apple's drivers are also doing it this way. */ 242 | txDescDmaCmd = IODMACommand::withSpecification(kIODMACommandOutputHost64, 64, 0, IODMACommand::kMapped, 0, 1); 243 | 244 | if (!txDescDmaCmd) { 245 | IOLog("Ethernet [IntelMausi]: Couldn't alloc txDescDmaCmd.\n"); 246 | goto error2; 247 | } 248 | 249 | if (txDescDmaCmd->setMemoryDescriptor(txBufDesc) != kIOReturnSuccess) { 250 | IOLog("Ethernet [IntelMausi]: setMemoryDescriptor() failed.\n"); 251 | goto error3; 252 | } 253 | 254 | if (txDescDmaCmd->gen64IOVMSegments(&offset, &seg, &numSegs) != kIOReturnSuccess) { 255 | IOLog("Ethernet [IntelMausi]: gen64IOVMSegments() failed.\n"); 256 | goto error4; 257 | } 258 | /* Now get tx ring's physical address. */ 259 | txPhyAddr = seg.fIOVMAddr; 260 | 261 | /* Initialize txDescArray. */ 262 | bzero(txDescArray, kTxDescSize); 263 | 264 | for (i = 0; i < kNumTxDesc; i++) { 265 | txBufArray[i].mbuf = NULL; 266 | txBufArray[i].numDescs = 0; 267 | txBufArray[i].pad = 0; 268 | } 269 | txNextDescIndex = txDirtyIndex = txCleanBarrierIndex = 0; 270 | txNumFreeDesc = kNumTxDesc; 271 | txMbufCursor = IOMbufNaturalMemoryCursor::withSpecification(0x4000, kMaxSegs); 272 | 273 | if (!txMbufCursor) { 274 | IOLog("Ethernet [IntelMausi]: Couldn't create txMbufCursor.\n"); 275 | goto error4; 276 | } 277 | 278 | /* Create receiver descriptor array. */ 279 | rxBufDesc = IOBufferMemoryDescriptor::inTaskWithPhysicalMask(kernel_task, (kIODirectionInOut | kIOMemoryPhysicallyContiguous | kIOMapInhibitCache), kRxDescSize, 0xFFFFFFFFFFFFF000ULL); 280 | 281 | if (!rxBufDesc) { 282 | IOLog("Ethernet [IntelMausi]: Couldn't alloc rxBufDesc.\n"); 283 | goto error5; 284 | } 285 | 286 | if (rxBufDesc->prepare() != kIOReturnSuccess) { 287 | IOLog("Ethernet [IntelMausi]: rxBufDesc->prepare() failed.\n"); 288 | goto error6; 289 | } 290 | rxDescArray = (union e1000_rx_desc_extended *)rxBufDesc->getBytesNoCopy(); 291 | 292 | /* I don't know if it's really necessary but the documenation says so and Apple's drivers are also doing it this way. */ 293 | rxDescDmaCmd = IODMACommand::withSpecification(kIODMACommandOutputHost64, 64, 0, IODMACommand::kMapped, 0, 1); 294 | 295 | if (!rxDescDmaCmd) { 296 | IOLog("Ethernet [IntelMausi]: Couldn't alloc rxDescDmaCmd.\n"); 297 | goto error7; 298 | } 299 | 300 | if (rxDescDmaCmd->setMemoryDescriptor(rxBufDesc) != kIOReturnSuccess) { 301 | IOLog("Ethernet [IntelMausi]: setMemoryDescriptor() failed.\n"); 302 | goto error8; 303 | } 304 | offset = 0; 305 | numSegs = 1; 306 | 307 | if (rxDescDmaCmd->gen64IOVMSegments(&offset, &seg, &numSegs) != kIOReturnSuccess) { 308 | IOLog("Ethernet [IntelMausi]: gen64IOVMSegments() failed.\n"); 309 | goto error9; 310 | } 311 | /* And the rx ring's physical address too. */ 312 | rxPhyAddr = seg.fIOVMAddr; 313 | 314 | /* Initialize rxDescArray. */ 315 | bzero((void *)rxDescArray, kRxDescSize); 316 | 317 | for (i = 0; i < kNumRxDesc; i++) { 318 | rxBufArray[i].mbuf = NULL; 319 | rxBufArray[i].phyAddr = 0; 320 | } 321 | rxCleanedCount = rxNextDescIndex = 0; 322 | 323 | rxMbufCursor = IOMbufNaturalMemoryCursor::withSpecification(PAGE_SIZE, 1); 324 | 325 | if (!rxMbufCursor) { 326 | IOLog("Ethernet [IntelMausi]: Couldn't create rxMbufCursor.\n"); 327 | goto error9; 328 | } 329 | /* Alloc receive buffers. */ 330 | for (i = 0; i < kNumRxDesc; i++) { 331 | m = allocatePacket(kRxBufferPktSize); 332 | 333 | if (!m) { 334 | IOLog("Ethernet [IntelMausi]: Couldn't alloc receive buffer.\n"); 335 | goto error10; 336 | } 337 | rxBufArray[i].mbuf = m; 338 | 339 | n = rxMbufCursor->getPhysicalSegments(m, &rxSegment, 1); 340 | 341 | if ((n != 1) || (rxSegment.location & 0x07ff)) { 342 | IOLog("Ethernet [IntelMausi]: getPhysicalSegments() for receive buffer failed.\n"); 343 | goto error10; 344 | } 345 | /* We have to keep the physical address of the buffer too 346 | * as descriptor write back overwrites it in the descriptor 347 | * so that it must be refreshed when the descriptor is 348 | * prepared for reuse. 349 | */ 350 | rxBufArray[i].phyAddr = rxSegment.location; 351 | 352 | rxDescArray[i].read.buffer_addr = OSSwapHostToLittleInt64(rxSegment.location); 353 | rxDescArray[i].read.reserved = 0; 354 | } 355 | /* Allocate some spare mbufs and free them in order to increase the buffer pool. 356 | * This seems to avoid the replaceOrCopyPacket() errors under heavy load. 357 | */ 358 | for (i = 0; i < kRxNumSpareMbufs; i++) 359 | spareMbuf[i] = allocatePacket(kRxBufferPktSize); 360 | 361 | for (i = 0; i < kRxNumSpareMbufs; i++) { 362 | if (spareMbuf[i]) 363 | freePacket(spareMbuf[i]); 364 | } 365 | result = true; 366 | 367 | done: 368 | return result; 369 | 370 | error10: 371 | for (i = 0; i < kNumRxDesc; i++) { 372 | if (rxBufArray[i].mbuf) { 373 | freePacket(rxBufArray[i].mbuf); 374 | rxBufArray[i].mbuf = NULL; 375 | } 376 | } 377 | RELEASE(rxMbufCursor); 378 | 379 | error9: 380 | rxDescDmaCmd->clearMemoryDescriptor(); 381 | 382 | error8: 383 | RELEASE(rxDescDmaCmd); 384 | 385 | error7: 386 | rxBufDesc->complete(); 387 | 388 | error6: 389 | rxBufDesc->release(); 390 | rxBufDesc = NULL; 391 | 392 | error5: 393 | RELEASE(txMbufCursor); 394 | 395 | error4: 396 | txDescDmaCmd->clearMemoryDescriptor(); 397 | 398 | error3: 399 | RELEASE(txDescDmaCmd); 400 | 401 | error2: 402 | txBufDesc->complete(); 403 | 404 | error1: 405 | txBufDesc->release(); 406 | txBufDesc = NULL; 407 | goto done; 408 | } 409 | 410 | void IntelMausi::freeDMADescriptors() 411 | { 412 | UInt32 i; 413 | 414 | if (txBufDesc) { 415 | txBufDesc->complete(); 416 | txBufDesc->release(); 417 | txBufDesc = NULL; 418 | txPhyAddr = NULL; 419 | } 420 | if (txDescDmaCmd) { 421 | txDescDmaCmd->clearMemoryDescriptor(); 422 | txDescDmaCmd->release(); 423 | txDescDmaCmd = NULL; 424 | } 425 | RELEASE(txMbufCursor); 426 | 427 | if (rxBufDesc) { 428 | rxBufDesc->complete(); 429 | rxBufDesc->release(); 430 | rxBufDesc = NULL; 431 | rxPhyAddr = NULL; 432 | } 433 | if (rxDescDmaCmd) { 434 | rxDescDmaCmd->clearMemoryDescriptor(); 435 | rxDescDmaCmd->release(); 436 | rxDescDmaCmd = NULL; 437 | } 438 | RELEASE(rxMbufCursor); 439 | 440 | for (i = 0; i < kNumRxDesc; i++) { 441 | if (rxBufArray[i].mbuf) { 442 | freePacket(rxBufArray[i].mbuf); 443 | rxBufArray[i].mbuf = NULL; 444 | } 445 | } 446 | } 447 | 448 | void IntelMausi::clearDescriptors() 449 | { 450 | mbuf_t m; 451 | UInt32 i; 452 | 453 | DebugLog("clearDescriptors() ===>\n"); 454 | 455 | /* First cleanup the tx descriptor ring. */ 456 | for (i = 0; i < kNumTxDesc; i++) { 457 | m = txBufArray[i].mbuf; 458 | 459 | if (m) { 460 | freePacket(m); 461 | txBufArray[i].mbuf = NULL; 462 | txBufArray[i].numDescs = 0; 463 | } 464 | } 465 | txNextDescIndex = txDirtyIndex = txCleanBarrierIndex = 0; 466 | txNumFreeDesc = kNumTxDesc; 467 | 468 | /* On descriptor writeback the buffer addresses are overwritten so that 469 | * we must restore them in order to make sure that we leave the ring in 470 | * a usable state. 471 | */ 472 | if (rxDescArray) { 473 | for (i = 0; i < kNumRxDesc; i++) { 474 | rxDescArray[i].read.buffer_addr = OSSwapHostToLittleInt64(rxBufArray[i].phyAddr); 475 | rxDescArray[i].read.reserved = 0; 476 | } 477 | } 478 | rxCleanedCount = rxNextDescIndex = 0; 479 | 480 | /* Free packet fragments which haven't been upstreamed yet. */ 481 | discardPacketFragment(); 482 | 483 | DebugLog("clearDescriptors() <===\n"); 484 | } 485 | 486 | void IntelMausi::discardPacketFragment() 487 | { 488 | /* 489 | * In case there is a packet fragment which hasn't been enqueued yet 490 | * we have to free it in order to prevent a memory leak. 491 | */ 492 | if (rxPacketHead) 493 | freePacket(rxPacketHead); 494 | 495 | rxPacketHead = rxPacketTail = NULL; 496 | rxPacketSize = 0; 497 | } 498 | -------------------------------------------------------------------------------- /IntelMausiEthernet/en.lproj/InfoPlist.strings: -------------------------------------------------------------------------------- 1 | /* Localized versions of Info.plist keys */ 2 | 3 | -------------------------------------------------------------------------------- /IntelMausiEthernet/ich8lan.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_ICH8LAN_H_ 23 | #define _E1000E_ICH8LAN_H_ 24 | 25 | #define ICH_FLASH_GFPREG 0x0000 26 | #define ICH_FLASH_HSFSTS 0x0004 27 | #define ICH_FLASH_HSFCTL 0x0006 28 | #define ICH_FLASH_FADDR 0x0008 29 | #define ICH_FLASH_FDATA0 0x0010 30 | #define ICH_FLASH_PR0 0x0074 31 | 32 | /* Requires up to 10 seconds when MNG might be accessing part. */ 33 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 34 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 35 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 36 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 37 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 38 | 39 | #define ICH_CYCLE_READ 0 40 | #define ICH_CYCLE_WRITE 2 41 | #define ICH_CYCLE_ERASE 3 42 | 43 | #define FLASH_GFPREG_BASE_MASK 0x1FFF 44 | #define FLASH_SECTOR_ADDR_SHIFT 12 45 | 46 | #define ICH_FLASH_SEG_SIZE_256 256 47 | #define ICH_FLASH_SEG_SIZE_4K 4096 48 | #define ICH_FLASH_SEG_SIZE_8K 8192 49 | #define ICH_FLASH_SEG_SIZE_64K 65536 50 | 51 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 52 | /* FW established a valid mode */ 53 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 54 | #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 55 | #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 56 | 57 | #define E1000_ICH_MNG_IAMT_MODE 0x2 58 | 59 | #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 60 | #define E1000_FWSM_WLOCK_MAC_SHIFT 7 61 | #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ 62 | 63 | /* Shared Receive Address Registers */ 64 | #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 65 | #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 66 | 67 | #define E1000_H2ME 0x05B50 /* Host to ME */ 68 | #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ 69 | #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ 70 | 71 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 72 | (ID_LED_OFF1_OFF2 << 8) | \ 73 | (ID_LED_OFF1_ON2 << 4) | \ 74 | (ID_LED_DEF1_DEF2)) 75 | 76 | #define E1000_ICH_NVM_SIG_WORD 0x13u 77 | #define E1000_ICH_NVM_SIG_MASK 0xC000u 78 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0u 79 | #define E1000_ICH_NVM_SIG_VALUE 0x80u 80 | 81 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 82 | 83 | /* FEXT register bit definition */ 84 | #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 85 | 86 | #define E1000_FEXTNVM_SW_CONFIG 1 87 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ 88 | 89 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 90 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 91 | 92 | #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 93 | #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 94 | #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 95 | 96 | #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 97 | #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 98 | #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000 99 | /* bit for disabling packet buffer read */ 100 | #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 101 | #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 102 | #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 103 | #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 104 | #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 105 | #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200 106 | #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 107 | 108 | /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ 109 | #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000 110 | 111 | #define K1_ENTRY_LATENCY 0 112 | #define K1_MIN_TIME 1 113 | #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */ 114 | #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */ 115 | #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ 116 | #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000 117 | #define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000 118 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 119 | 120 | #define E1000_ICH_RAR_ENTRIES 7 121 | #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 122 | #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 123 | 124 | #define PHY_PAGE_SHIFT 5 125 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 126 | ((reg) & MAX_PHY_REG_ADDRESS)) 127 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 128 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 129 | 130 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 131 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 132 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 133 | 134 | /* PHY Wakeup Registers and defines */ 135 | #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 136 | #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 137 | #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 138 | #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 139 | #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 140 | #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 141 | #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 142 | #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 143 | #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 144 | #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 145 | 146 | #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 147 | #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 148 | #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 149 | #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 150 | #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 151 | #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 152 | #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 153 | 154 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 155 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 156 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 157 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 158 | #define HV_STATS_PAGE 778 159 | /* Half-duplex collision counts */ 160 | #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ 161 | #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 162 | #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ 163 | #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 164 | #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ 165 | #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 166 | #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ 167 | #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 168 | #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ 169 | #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 170 | #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 171 | #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 172 | #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ 173 | #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 174 | 175 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 176 | 177 | #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 178 | #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 179 | 180 | /* SMBus Control Phy Register */ 181 | #define CV_SMB_CTRL PHY_REG(769, 23) 182 | #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 183 | 184 | /* I218 Ultra Low Power Configuration 1 Register */ 185 | #define I218_ULP_CONFIG1 PHY_REG(779, 16) 186 | #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 187 | #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 188 | #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 189 | #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 190 | #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 191 | #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ 192 | /* enable ULP even if when phy powered down via lanphypc */ 193 | #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 194 | /* disable clear of sticky ULP on PERST */ 195 | #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 196 | #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 197 | 198 | /* SMBus Address Phy Register */ 199 | #define HV_SMB_ADDR PHY_REG(768, 26) 200 | #define HV_SMB_ADDR_MASK 0x007F 201 | #define HV_SMB_ADDR_PEC_EN 0x0200 202 | #define HV_SMB_ADDR_VALID 0x0080 203 | #define HV_SMB_ADDR_FREQ_MASK 0x1100 204 | #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 205 | #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 206 | 207 | /* Strapping Option Register - RO */ 208 | #define E1000_STRAP 0x0000C 209 | #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 210 | #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 211 | #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 212 | #define E1000_STRAP_SMT_FREQ_SHIFT 12 213 | 214 | /* OEM Bits Phy Register */ 215 | #define HV_OEM_BITS PHY_REG(768, 25) 216 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 217 | #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 218 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 219 | 220 | /* KMRN Mode Control */ 221 | #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 222 | #define HV_KMRN_MDIO_SLOW 0x0400 223 | 224 | /* KMRN FIFO Control and Status */ 225 | #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 226 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 227 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 228 | 229 | /* PHY Power Management Control */ 230 | #define HV_PM_CTRL PHY_REG(770, 17) 231 | #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 232 | #define HV_PM_CTRL_K1_ENABLE 0x4000 233 | 234 | #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) 235 | #define I217_PLL_CLOCK_GATE_MASK 0x07FF 236 | 237 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 238 | 239 | /* Inband Control */ 240 | #define I217_INBAND_CTRL PHY_REG(770, 18) 241 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 242 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 243 | 244 | /* Low Power Idle GPIO Control */ 245 | #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) 246 | #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 247 | 248 | /* PHY Low Power Idle Control */ 249 | #define I82579_LPI_CTRL PHY_REG(772, 20) 250 | #define I82579_LPI_CTRL_100_ENABLE 0x2000 251 | #define I82579_LPI_CTRL_1000_ENABLE 0x4000 252 | #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 253 | #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 254 | 255 | /* Extended Management Interface (EMI) Registers */ 256 | #define I82579_EMI_ADDR 0x10 257 | #define I82579_EMI_DATA 0x11 258 | #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 259 | #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 260 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 261 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 262 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 263 | #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ 264 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ 265 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 266 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 267 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 268 | #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ 269 | #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ 270 | #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ 271 | #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 272 | #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 273 | #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 274 | #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 275 | #define I217_RX_CONFIG 0xB20C /* Receive configuration */ 276 | 277 | #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 278 | #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 279 | 280 | /* Intel Rapid Start Technology Support */ 281 | #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 282 | #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 283 | #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 284 | #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 285 | #define I217_CGFREG PHY_REG(772, 29) 286 | #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 287 | #define I217_MEMPWR PHY_REG(772, 26) 288 | #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 289 | 290 | /* Receive Address Initial CRC Calculation */ 291 | #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 292 | 293 | /* Latency Tolerance Reporting */ 294 | #define E1000_LTRV 0x000F8 295 | #define E1000_LTRV_SCALE_MAX 5 296 | #define E1000_LTRV_SCALE_FACTOR 5 297 | #define E1000_LTRV_REQ_SHIFT 15 298 | #define E1000_LTRV_NOSNOOP_SHIFT 16 299 | #define E1000_LTRV_SEND (1 << 30) 300 | 301 | /* Proprietary Latency Tolerance Reporting PCI Capability */ 302 | #define E1000_PCI_LTR_CAP_LPT 0xA8 303 | 304 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); 305 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 306 | bool state); 307 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 308 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 309 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 310 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 311 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 312 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 313 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 314 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 315 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); 316 | s32 e1000_set_eee_pchlan(struct e1000_hw *hw); 317 | s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); 318 | #endif /* _E1000E_ICH8LAN_H_ */ 319 | -------------------------------------------------------------------------------- /IntelMausiEthernet/if_ether.h: -------------------------------------------------------------------------------- 1 | /* 2 | * INET An implementation of the TCP/IP protocol suite for the LINUX 3 | * operating system. INET is implemented using the BSD Socket 4 | * interface as the means of communication with the user level. 5 | * 6 | * Global definitions for the Ethernet IEEE 802.3 interface. 7 | * 8 | * Version: @(#)if_ether.h 1.0.1a 02/08/94 9 | * 10 | * Author: Fred N. van Kempen, 11 | * Donald Becker, 12 | * Alan Cox, 13 | * Steve Whitehouse, 14 | * 15 | * This program is free software; you can redistribute it and/or 16 | * modify it under the terms of the GNU General Public License 17 | * as published by the Free Software Foundation; either version 18 | * 2 of the License, or (at your option) any later version. 19 | */ 20 | 21 | #ifndef _UAPI_LINUX_IF_ETHER_H 22 | #define _UAPI_LINUX_IF_ETHER_H 23 | 24 | #if DISABLED_CODE 25 | 26 | #include 27 | 28 | #endif /* DISABLED_CODE */ 29 | 30 | /* 31 | * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble 32 | * and FCS/CRC (frame check sequence). 33 | */ 34 | 35 | #define ETH_ALEN 6 /* Octets in one ethernet addr */ 36 | #define ETH_HLEN 14 /* Total octets in header. */ 37 | #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ 38 | #define ETH_DATA_LEN 1500 /* Max. octets in payload */ 39 | #define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ 40 | #define ETH_FCS_LEN 4 /* Octets in the FCS */ 41 | 42 | /* 43 | * These are the defined Ethernet Protocol ID's. 44 | */ 45 | 46 | #define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ 47 | #define ETH_P_PUP 0x0200 /* Xerox PUP packet */ 48 | #define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ 49 | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ 50 | #define ETH_P_X25 0x0805 /* CCITT X.25 */ 51 | #define ETH_P_ARP 0x0806 /* Address Resolution packet */ 52 | #define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ 53 | #define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ 54 | #define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ 55 | #define ETH_P_BATMAN 0x4305 /* B.A.T.M.A.N.-Advanced packet [ NOT AN OFFICIALLY REGISTERED ID ] */ 56 | #define ETH_P_DEC 0x6000 /* DEC Assigned proto */ 57 | #define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ 58 | #define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ 59 | #define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ 60 | #define ETH_P_LAT 0x6004 /* DEC LAT */ 61 | #define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ 62 | #define ETH_P_CUST 0x6006 /* DEC Customer use */ 63 | #define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ 64 | #define ETH_P_TEB 0x6558 /* Trans Ether Bridging */ 65 | #define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ 66 | #define ETH_P_ATALK 0x809B /* Appletalk DDP */ 67 | #define ETH_P_AARP 0x80F3 /* Appletalk AARP */ 68 | #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 69 | #define ETH_P_IPX 0x8137 /* IPX over DIX */ 70 | #define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ 71 | #define ETH_P_PAUSE 0x8808 /* IEEE Pause frames. See 802.3 31B */ 72 | #define ETH_P_SLOW 0x8809 /* Slow Protocol. See 802.3ad 43B */ 73 | #define ETH_P_WCCP 0x883E /* Web-cache coordination protocol 74 | * defined in draft-wilson-wrec-wccp-v2-00.txt */ 75 | #define ETH_P_MPLS_UC 0x8847 /* MPLS Unicast traffic */ 76 | #define ETH_P_MPLS_MC 0x8848 /* MPLS Multicast traffic */ 77 | #define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ 78 | #define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ 79 | #define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ 80 | #define ETH_P_LINK_CTL 0x886c /* HPNA, wlan link local tunnel */ 81 | #define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport 82 | * over Ethernet 83 | */ 84 | #define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ 85 | #define ETH_P_AOE 0x88A2 /* ATA over Ethernet */ 86 | #define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN */ 87 | #define ETH_P_802_EX1 0x88B5 /* 802.1 Local Experimental 1. */ 88 | #define ETH_P_TIPC 0x88CA /* TIPC */ 89 | #define ETH_P_8021AH 0x88E7 /* 802.1ah Backbone Service Tag */ 90 | #define ETH_P_MVRP 0x88F5 /* 802.1Q MVRP */ 91 | #define ETH_P_1588 0x88F7 /* IEEE 1588 Timesync */ 92 | #define ETH_P_PRP 0x88FB /* IEC 62439-3 PRP/HSRv0 */ 93 | #define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */ 94 | #define ETH_P_TDLS 0x890D /* TDLS */ 95 | #define ETH_P_FIP 0x8914 /* FCoE Initialization Protocol */ 96 | #define ETH_P_80221 0x8917 /* IEEE 802.21 Media Independent Handover Protocol */ 97 | #define ETH_P_LOOPBACK 0x9000 /* Ethernet loopback packet, per IEEE 802.3 */ 98 | #define ETH_P_QINQ1 0x9100 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */ 99 | #define ETH_P_QINQ2 0x9200 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */ 100 | #define ETH_P_QINQ3 0x9300 /* deprecated QinQ VLAN [ NOT AN OFFICIALLY REGISTERED ID ] */ 101 | #define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ 102 | #define ETH_P_AF_IUCV 0xFBFB /* IBM af_iucv [ NOT AN OFFICIALLY REGISTERED ID ] */ 103 | 104 | #define ETH_P_802_3_MIN 0x0600 /* If the value in the ethernet type is less than this value 105 | * then the frame is Ethernet II. Else it is 802.3 */ 106 | 107 | /* 108 | * Non DIX types. Won't clash for 1500 types. 109 | */ 110 | 111 | #define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ 112 | #define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ 113 | #define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ 114 | #define ETH_P_802_2 0x0004 /* 802.2 frames */ 115 | #define ETH_P_SNAP 0x0005 /* Internal only */ 116 | #define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ 117 | #define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ 118 | #define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ 119 | #define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ 120 | #define ETH_P_CAN 0x000C /* CAN: Controller Area Network */ 121 | #define ETH_P_CANFD 0x000D /* CANFD: CAN flexible data rate*/ 122 | #define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ 123 | #define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ 124 | #define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */ 125 | #define ETH_P_CONTROL 0x0016 /* Card specific control frames */ 126 | #define ETH_P_IRDA 0x0017 /* Linux-IrDA */ 127 | #define ETH_P_ECONET 0x0018 /* Acorn Econet */ 128 | #define ETH_P_HDLC 0x0019 /* HDLC frames */ 129 | #define ETH_P_ARCNET 0x001A /* 1A for ArcNet :-) */ 130 | #define ETH_P_DSA 0x001B /* Distributed Switch Arch. */ 131 | #define ETH_P_TRAILER 0x001C /* Trailer switch tagging */ 132 | #define ETH_P_PHONET 0x00F5 /* Nokia Phonet frames */ 133 | #define ETH_P_IEEE802154 0x00F6 /* IEEE802.15.4 frame */ 134 | #define ETH_P_CAIF 0x00F7 /* ST-Ericsson CAIF protocol */ 135 | 136 | /* 137 | * This is an Ethernet frame header. 138 | */ 139 | 140 | struct ethhdr { 141 | unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ 142 | unsigned char h_source[ETH_ALEN]; /* source ether addr */ 143 | __be16 h_proto; /* packet type ID field */ 144 | } __attribute__((packed)); 145 | 146 | 147 | #endif /* _UAPI_LINUX_IF_ETHER_H */ 148 | -------------------------------------------------------------------------------- /IntelMausiEthernet/linux.h: -------------------------------------------------------------------------------- 1 | /* linux.h -- Definitions to make the linux code compile under OS X. 2 | * 3 | * Copyright (c) 2014 Laura Müller 4 | * All rights reserved. 5 | * 6 | * This program is free software; you can redistribute it and/or modify it 7 | * under the terms of the GNU General Public License as published by the Free 8 | * Software Foundation; either version 2 of the License, or (at your option) 9 | * any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, but WITHOUT 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 | * more details. 15 | * 16 | * Driver Intel Gigabit PCIe ethernet controllers. 17 | * 18 | * This driver is based on Intel's E1000e driver for Linux. 19 | */ 20 | 21 | #ifndef AtherosE2200_linux_h 22 | #define AtherosE2200_linux_h 23 | 24 | #include 25 | 26 | /******************************************************************************/ 27 | #pragma mark - 28 | #pragma mark Debugging 29 | #pragma mark - 30 | /******************************************************************************/ 31 | 32 | #define printk(args...) IOLog(args) 33 | /******************************************************************************/ 34 | #pragma mark - 35 | #pragma mark Bits and Bytes 36 | #pragma mark - 37 | /******************************************************************************/ 38 | 39 | #define HZ 1000 // Milliseconds. 40 | 41 | #if defined(__LITTLE_ENDIAN__) 42 | #define __LITTLE_ENDIAN 1234 43 | #define __LITTLE_ENDIAN_BITFIELD 44 | 45 | #elif defined(__BIG_ENDIAN__) 46 | #define __BIG_ENDIAN 4321 47 | #define __BIG_ENDIAN_BITFIELD 48 | 49 | #endif // ENDIAN 50 | 51 | #define u8 UInt8 52 | #define u16 UInt16 53 | #define u32 UInt32 54 | #define u64 UInt64 55 | #define s32 SInt32 56 | #define s64 SInt64 57 | #define __be16 SInt16 58 | #define __be32 SInt32 59 | #define __be64 SInt64 60 | #define __le16 SInt16 61 | #define __le32 SInt32 62 | #define __le64 SInt64 63 | #define __s8 SInt8 64 | #define __s16 SInt16 65 | #define __s32 SInt32 66 | #define __s64 SInt64 67 | #define __u8 UInt8 68 | #define __u16 UInt16 69 | #define __u32 UInt32 70 | #define __u64 UInt64 71 | 72 | #define __sum16 UInt16 73 | 74 | #define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) 75 | #define ALIGN(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1) 76 | 77 | #define cpu_to_le16(x) OSSwapHostToLittleInt16(x) 78 | #define cpu_to_le32(x) OSSwapHostToLittleInt32(x) 79 | #define cpu_to_le64(x) OSSwapHostToLittleInt64(x) 80 | #define le16_to_cpu(x) OSSwapLittleToHostInt16(x) 81 | #define le32_to_cpu(x) OSSwapLittleToHostInt32(x) 82 | #define le64_to_cpu(x) OSSwapLittleToHostInt64(x) 83 | 84 | #define cpu_to_be16(x) OSSwapHostToBigInt16(x) 85 | #define cpu_to_be32(x) OSSwapHostToBigInt32(x) 86 | #define cpu_to_be64(x) OSSwapHostToBigInt64(x) 87 | #define be16_to_cpu(x) OSSwapBigToHostInt16(x) 88 | #define be32_to_cpu(x) OSSwapBigToHostInt32(x) 89 | #define be64_to_cpu(x) OSSwapBigToHostInt64(x) 90 | 91 | #define le16_to_cpus(x) ((*x) = OSSwapLittleToHostInt16((*x))) 92 | #define le32_to_cpus(x) ((*x) = OSSwapLittleToHostInt32((*x))) 93 | #define le64_to_cpus(x) ((*x) = OSSwapLittleToHostInt64((*x))) 94 | 95 | #define container_of(ptr, type, member) ({ \ 96 | const typeof( ((type *)0)->member ) *__mptr = (ptr); \ 97 | (type *)( (char *)__mptr - offsetof(type,member) );}) 98 | 99 | #define BITS_PER_LONG LONG_BIT 100 | #define BIT(nr) (1UL << (nr)) 101 | #define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) 102 | #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 103 | #define BITS_PER_BYTE 8 104 | #define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG) 105 | 106 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 107 | 108 | #define min_t(type,x,y) \ 109 | ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 110 | 111 | #define max_t(type, x, y) \ 112 | ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) 113 | 114 | #if 0 115 | enum bool_t 116 | { 117 | false = 0, 118 | true = 1 119 | }; 120 | typedef enum bool_t bool; 121 | #endif 122 | 123 | #define dma_addr_t IOPhysicalAddress64 124 | 125 | #define likely(x) __builtin_expect(!!(x), 1) 126 | #define unlikely(x) __builtin_expect(!!(x), 0) 127 | 128 | static inline int atomic_dec_and_test(volatile SInt32 * addr) 129 | { 130 | return ((OSDecrementAtomic(addr) == 1) ? 1 : 0); 131 | } 132 | 133 | static inline int atomic_inc_and_test(volatile SInt32 * addr) 134 | { 135 | return ((OSIncrementAtomic(addr) == -1) ? 1 : 0); 136 | } 137 | 138 | #define atomic_inc(v) OSIncrementAtomic(v) 139 | #define atomic_dec(v) OSDecrementAtomic(v) 140 | 141 | static inline int 142 | test_bit(int nr, const volatile unsigned long *addr) 143 | { 144 | return (OSAddAtomic(0, addr) & (1 << nr)) != 0; 145 | } 146 | 147 | static inline void 148 | set_bit(unsigned int nr, volatile unsigned long *addr) 149 | { 150 | OSTestAndSet(nr, (volatile UInt8 *)addr); 151 | } 152 | 153 | static inline void 154 | clear_bit(unsigned int nr, volatile unsigned long *addr) 155 | { 156 | OSTestAndClear(nr, (volatile UInt8 *)addr); 157 | } 158 | 159 | static inline int 160 | test_and_clear_bit(unsigned int nr, volatile unsigned long *addr) 161 | { 162 | return !OSTestAndClear(nr, (volatile UInt8 *)addr); 163 | } 164 | 165 | static inline int 166 | test_and_set_bit(unsigned int nr, volatile unsigned long *addr) 167 | { 168 | return OSTestAndSet(nr, (volatile UInt8 *)addr); 169 | } 170 | 171 | /******************************************************************************/ 172 | #pragma mark - 173 | #pragma mark Read/Write Registers 174 | #pragma mark - 175 | /******************************************************************************/ 176 | 177 | OS_INLINE 178 | void 179 | _OSWriteInt8( 180 | volatile void * base, 181 | uintptr_t byteOffset, 182 | uint16_t data 183 | ) 184 | { 185 | *(volatile uint8_t *)((uintptr_t)base + byteOffset) = data; 186 | } 187 | 188 | OS_INLINE 189 | uint8_t 190 | _OSReadInt8( 191 | const volatile void * base, 192 | uintptr_t byteOffset 193 | ) 194 | { 195 | return *(volatile uint8_t *)((uintptr_t)base + byteOffset); 196 | } 197 | 198 | #define OSWriteLittleInt8(base, byteOffset, data) \ 199 | _OSWriteInt8((base), (byteOffset), (data)) 200 | #define OSReadLittleInt8(base, byteOffset) \ 201 | _OSReadInt8((base), (byteOffset)) 202 | 203 | #define writew(hw, reg, val16) OSWriteLittleInt16((hw->hw_addr), (reg), (val16)) 204 | #define writel(hw, reg, val32) OSWriteLittleInt32((hw->hw_addr), (reg), (val32)) 205 | 206 | #define readw(hw, reg) OSReadLittleInt16((hw->hw_addr), (reg)) 207 | #define readl(hw, reg) OSReadLittleInt32((hw->hw_addr), (reg)) 208 | 209 | #define __er32(hw, reg) OSReadLittleInt32((hw->hw_addr), (reg)) 210 | 211 | #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 212 | (OSWriteLittleInt32((hw->hw_addr), (reg + ((offset) << 2)), (value))) 213 | 214 | #define E1000_READ_REG_ARRAY(a, reg, offset) \ 215 | (OSReadLittleInt32((hw->hw_addr), (reg + ((offset) << 2)))) 216 | 217 | #define wmb() OSSynchronizeIO() 218 | 219 | #define __er16flash(hw, reg) \ 220 | OSReadLittleInt16((hw->flash_address), (reg)) 221 | 222 | #define __er32flash(hw, reg) \ 223 | OSReadLittleInt32((hw->flash_address), (reg)) 224 | 225 | #define __ew16flash(hw, reg, val) \ 226 | OSWriteLittleInt16((hw->flash_address), (reg), (val)) 227 | 228 | #define __ew32flash(hw, reg, val) \ 229 | OSWriteLittleInt32((hw->flash_address), (reg), (val)) 230 | 231 | /******************************************************************************/ 232 | #pragma mark - 233 | #pragma mark Locks 234 | #pragma mark - 235 | /******************************************************************************/ 236 | 237 | #define spinlock_t IOSimpleLock * 238 | #define atomic_t volatile SInt32 239 | 240 | 241 | #define spin_lock_init(slock) \ 242 | do \ 243 | { \ 244 | if (*slock == NULL) \ 245 | { \ 246 | *(slock) = IOSimpleLockAlloc(); \ 247 | } \ 248 | } while (0) 249 | 250 | #define spin_lock(lock) 251 | 252 | #define spin_unlock(lock) 253 | 254 | #define spin_lock_irqsave(lock,flags) 255 | 256 | #define spin_trylock_irqsave(lock,flags) 257 | 258 | #define spin_unlock_irqrestore(lock,flags) 259 | 260 | #define usec_delay(x) IODelay(x) 261 | #define msec_delay(x) IOSleep(x) 262 | #define udelay(x) IODelay(x) 263 | #define mdelay(x) IODelay(1000*(x)) 264 | #define msleep(x) IOSleep(x) 265 | 266 | #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 267 | #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000)) 268 | 269 | enum 270 | { 271 | GFP_KERNEL, 272 | GFP_ATOMIC, 273 | }; 274 | 275 | #define __iomem volatile 276 | #define __devinit 277 | 278 | #define LINUX_VERSION_CODE 30000 279 | #define KERNEL_VERSION(x,y,z) (x*10000+100*y+z) 280 | 281 | #define irqreturn_t int 282 | 283 | #define WARN_ON_ONCE(x) 284 | 285 | #define __always_unused 286 | 287 | #define DISABLED_CODE 0 288 | 289 | struct pci_dev { 290 | UInt16 vendor; 291 | UInt16 device; 292 | UInt16 subsystem_vendor; 293 | UInt16 subsystem_device; 294 | UInt16 maxSnoop; 295 | UInt16 maxNoSnoop; 296 | UInt8 revision; 297 | }; 298 | 299 | #define dev_err(x,y,z) 300 | 301 | /** 302 | * is_zero_ether_addr - Determine if give Ethernet address is all zeros. 303 | * @addr: Pointer to a six-byte array containing the Ethernet address 304 | * 305 | * Return true if the address is all zeroes. 306 | * 307 | * Please note: addr must be aligned to u16. 308 | */ 309 | static inline bool is_zero_ether_addr(const u8 *addr) 310 | { 311 | #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) 312 | return ((*(const u32 *)addr) | (*(const u16 *)(addr + 4))) == 0; 313 | #else 314 | return (*(const u16 *)(addr + 0) | 315 | *(const u16 *)(addr + 2) | 316 | *(const u16 *)(addr + 4)) == 0; 317 | #endif 318 | } 319 | 320 | /** 321 | * is_multicast_ether_addr - Determine if the Ethernet address is a multicast. 322 | * @addr: Pointer to a six-byte array containing the Ethernet address 323 | * 324 | * Return true if the address is a multicast address. 325 | * By definition the broadcast address is also a multicast address. 326 | */ 327 | static inline bool is_multicast_ether_addr(const u8 *addr) 328 | { 329 | return 0x01 & addr[0]; 330 | } 331 | 332 | /** 333 | * is_valid_ether_addr - Determine if the given Ethernet address is valid 334 | * @addr: Pointer to a six-byte array containing the Ethernet address 335 | * 336 | * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not 337 | * a multicast address, and is not FF:FF:FF:FF:FF:FF. 338 | * 339 | * Return true if the address is valid. 340 | * 341 | * Please note: addr must be aligned to u16. 342 | */ 343 | static inline bool is_valid_ether_addr(const u8 *addr) 344 | { 345 | /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to 346 | * explicitly check for it here. */ 347 | return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); 348 | } 349 | 350 | #define e_dbg(format, arg...) 351 | #define e_err(format, arg...) 352 | #define e_info(format, arg...) 353 | #define e_warn(format, arg...) 354 | #define e_notice(format, arg...) 355 | 356 | #define DEFINE_MUTEX(x) void x##_dummy(){} 357 | #define mutex_lock(x) 358 | #define mutex_unlock(x) 359 | 360 | #define net_device e1000_adapter 361 | #define netdev_priv(x) ((struct e1000_adapter *)x) 362 | 363 | #define do_div(lat_ns, speed) \ 364 | (lat_ns) = (UInt64)(lat_ns) / (speed) 365 | 366 | #define ether_crc_le(length, data) _kc_ether_crc_le(length, data) 367 | 368 | static inline unsigned int _kc_ether_crc_le(int length, unsigned char *data) 369 | { 370 | unsigned int crc = 0xffffffff; /* Initial value. */ 371 | while(--length >= 0) { 372 | unsigned char current_octet = *data++; 373 | int bit; 374 | for (bit = 8; --bit >= 0; current_octet >>= 1) { 375 | if ((crc ^ current_octet) & 1) { 376 | crc >>= 1; 377 | crc ^= 0xedb88320U; 378 | } else 379 | crc >>= 1; 380 | } 381 | } 382 | return crc; 383 | } 384 | 385 | #define VLAN_ETH_FRAME_LEN 1518 /* Max. octets in frame sans FCS */ 386 | 387 | #endif 388 | -------------------------------------------------------------------------------- /IntelMausiEthernet/mac.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_MAC_H_ 23 | #define _E1000E_MAC_H_ 24 | 25 | s32 e1000e_blink_led_generic(struct e1000_hw *hw); 26 | s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 27 | s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 28 | s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 29 | s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 30 | s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 31 | s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 32 | s32 e1000e_force_mac_fc(struct e1000_hw *hw); 33 | s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 34 | s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 35 | void e1000_set_lan_id_single_port(struct e1000_hw *hw); 36 | s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 37 | s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 38 | u16 *duplex); 39 | s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, 40 | u16 *speed, u16 *duplex); 41 | s32 e1000e_id_led_init_generic(struct e1000_hw *hw); 42 | s32 e1000e_led_on_generic(struct e1000_hw *hw); 43 | s32 e1000e_led_off_generic(struct e1000_hw *hw); 44 | void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 45 | u8 *mc_addr_list, u32 mc_addr_count); 46 | s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 47 | s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 48 | s32 e1000e_setup_led_generic(struct e1000_hw *hw); 49 | s32 e1000e_setup_link_generic(struct e1000_hw *hw); 50 | s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw); 51 | s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw); 52 | 53 | void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 54 | void e1000_clear_vfta_generic(struct e1000_hw *hw); 55 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 56 | void e1000e_put_hw_semaphore(struct e1000_hw *hw); 57 | s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 58 | void e1000e_reset_adaptive(struct e1000_hw *hw); 59 | void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 60 | void e1000e_update_adaptive(struct e1000_hw *hw); 61 | void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 62 | 63 | void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 64 | u32 e1000e_rar_get_count_generic(struct e1000_hw *hw); 65 | int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 66 | void e1000e_config_collision_dist_generic(struct e1000_hw *hw); 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /IntelMausiEthernet/manage.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #include "e1000.h" 23 | 24 | /** 25 | * e1000_calculate_checksum - Calculate checksum for buffer 26 | * @buffer: pointer to EEPROM 27 | * @length: size of EEPROM to calculate a checksum for 28 | * 29 | * Calculates the checksum for some buffer on a specified length. The 30 | * checksum calculated is returned. 31 | **/ 32 | static u8 e1000_calculate_checksum(u8 *buffer, u32 length) 33 | { 34 | u32 i; 35 | u8 sum = 0; 36 | 37 | if (!buffer) 38 | return 0; 39 | 40 | for (i = 0; i < length; i++) 41 | sum += buffer[i]; 42 | 43 | return (u8)(0 - sum); 44 | } 45 | 46 | /** 47 | * e1000_mng_enable_host_if - Checks host interface is enabled 48 | * @hw: pointer to the HW structure 49 | * 50 | * Returns 0 upon success, else -E1000_ERR_HOST_INTERFACE_COMMAND 51 | * 52 | * This function checks whether the HOST IF is enabled for command operation 53 | * and also checks whether the previous command is completed. It busy waits 54 | * in case of previous command is not completed. 55 | **/ 56 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) 57 | { 58 | u32 hicr; 59 | u8 i; 60 | 61 | if (!hw->mac.arc_subsystem_valid) { 62 | e_dbg("ARC subsystem not valid.\n"); 63 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 64 | } 65 | 66 | /* Check that the host interface is enabled. */ 67 | hicr = er32(HICR); 68 | if (!(hicr & E1000_HICR_EN)) { 69 | e_dbg("E1000_HOST_EN bit disabled.\n"); 70 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 71 | } 72 | /* check the previous command is completed */ 73 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 74 | hicr = er32(HICR); 75 | if (!(hicr & E1000_HICR_C)) 76 | break; 77 | mdelay(1); 78 | } 79 | 80 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 81 | e_dbg("Previous command timeout failed.\n"); 82 | return -E1000_ERR_HOST_INTERFACE_COMMAND; 83 | } 84 | 85 | return 0; 86 | } 87 | 88 | /** 89 | * e1000e_check_mng_mode_generic - Generic check management mode 90 | * @hw: pointer to the HW structure 91 | * 92 | * Reads the firmware semaphore register and returns true (>0) if 93 | * manageability is enabled, else false (0). 94 | **/ 95 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw) 96 | { 97 | u32 fwsm = er32(FWSM); 98 | 99 | return (fwsm & E1000_FWSM_MODE_MASK) == 100 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 101 | } 102 | 103 | /** 104 | * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx 105 | * @hw: pointer to the HW structure 106 | * 107 | * Enables packet filtering on transmit packets if manageability is enabled 108 | * and host interface is enabled. 109 | **/ 110 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) 111 | { 112 | struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; 113 | u32 *buffer = (u32 *)&hw->mng_cookie; 114 | u32 offset; 115 | s32 ret_val, hdr_csum, csum; 116 | u8 i, len; 117 | 118 | hw->mac.tx_pkt_filtering = true; 119 | 120 | /* No manageability, no filtering */ 121 | if (!hw->mac.ops.check_mng_mode(hw)) { 122 | hw->mac.tx_pkt_filtering = false; 123 | return hw->mac.tx_pkt_filtering; 124 | } 125 | 126 | /* If we can't read from the host interface for whatever 127 | * reason, disable filtering. 128 | */ 129 | ret_val = e1000_mng_enable_host_if(hw); 130 | if (ret_val) { 131 | hw->mac.tx_pkt_filtering = false; 132 | return hw->mac.tx_pkt_filtering; 133 | } 134 | 135 | /* Read in the header. Length and offset are in dwords. */ 136 | len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; 137 | offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; 138 | for (i = 0; i < len; i++) 139 | *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, 140 | offset + i); 141 | hdr_csum = hdr->checksum; 142 | hdr->checksum = 0; 143 | csum = e1000_calculate_checksum((u8 *)hdr, 144 | E1000_MNG_DHCP_COOKIE_LENGTH); 145 | /* If either the checksums or signature don't match, then 146 | * the cookie area isn't considered valid, in which case we 147 | * take the safe route of assuming Tx filtering is enabled. 148 | */ 149 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { 150 | hw->mac.tx_pkt_filtering = true; 151 | return hw->mac.tx_pkt_filtering; 152 | } 153 | 154 | /* Cookie area is valid, make the final check for filtering. */ 155 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) 156 | hw->mac.tx_pkt_filtering = false; 157 | 158 | return hw->mac.tx_pkt_filtering; 159 | } 160 | 161 | /** 162 | * e1000_mng_write_cmd_header - Writes manageability command header 163 | * @hw: pointer to the HW structure 164 | * @hdr: pointer to the host interface command header 165 | * 166 | * Writes the command header after does the checksum calculation. 167 | **/ 168 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, 169 | struct e1000_host_mng_command_header *hdr) 170 | { 171 | u16 i, length = sizeof(struct e1000_host_mng_command_header); 172 | 173 | /* Write the whole command header structure with new checksum. */ 174 | 175 | hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); 176 | 177 | length >>= 2; 178 | /* Write the relevant command block into the ram area. */ 179 | for (i = 0; i < length; i++) { 180 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i)); 181 | e1e_flush(); 182 | } 183 | 184 | return 0; 185 | } 186 | 187 | /** 188 | * e1000_mng_host_if_write - Write to the manageability host interface 189 | * @hw: pointer to the HW structure 190 | * @buffer: pointer to the host interface buffer 191 | * @length: size of the buffer 192 | * @offset: location in the buffer to write to 193 | * @sum: sum of the data (not checksum) 194 | * 195 | * This function writes the buffer content at the offset given on the host if. 196 | * It also does alignment considerations to do the writes in most efficient 197 | * way. Also fills up the sum of the buffer in *buffer parameter. 198 | **/ 199 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, 200 | u16 length, u16 offset, u8 *sum) 201 | { 202 | u8 *tmp; 203 | u8 *bufptr = buffer; 204 | u32 data = 0; 205 | u16 remaining, i, j, prev_bytes; 206 | 207 | /* sum = only sum of the data and it is not checksum */ 208 | 209 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) 210 | return -E1000_ERR_PARAM; 211 | 212 | tmp = (u8 *)&data; 213 | prev_bytes = offset & 0x3; 214 | offset >>= 2; 215 | 216 | if (prev_bytes) { 217 | data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); 218 | for (j = prev_bytes; j < sizeof(u32); j++) { 219 | *(tmp + j) = *bufptr++; 220 | *sum += *(tmp + j); 221 | } 222 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); 223 | length -= j - prev_bytes; 224 | offset++; 225 | } 226 | 227 | remaining = length & 0x3; 228 | length -= remaining; 229 | 230 | /* Calculate length in DWORDs */ 231 | length >>= 2; 232 | 233 | /* The device driver writes the relevant command block into the 234 | * ram area. 235 | */ 236 | for (i = 0; i < length; i++) { 237 | for (j = 0; j < sizeof(u32); j++) { 238 | *(tmp + j) = *bufptr++; 239 | *sum += *(tmp + j); 240 | } 241 | 242 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); 243 | } 244 | if (remaining) { 245 | for (j = 0; j < sizeof(u32); j++) { 246 | if (j < remaining) 247 | *(tmp + j) = *bufptr++; 248 | else 249 | *(tmp + j) = 0; 250 | 251 | *sum += *(tmp + j); 252 | } 253 | E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); 254 | } 255 | 256 | return 0; 257 | } 258 | 259 | /** 260 | * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface 261 | * @hw: pointer to the HW structure 262 | * @buffer: pointer to the host interface 263 | * @length: size of the buffer 264 | * 265 | * Writes the DHCP information to the host interface. 266 | **/ 267 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) 268 | { 269 | struct e1000_host_mng_command_header hdr; 270 | s32 ret_val; 271 | u32 hicr; 272 | 273 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; 274 | hdr.command_length = length; 275 | hdr.reserved1 = 0; 276 | hdr.reserved2 = 0; 277 | hdr.checksum = 0; 278 | 279 | /* Enable the host interface */ 280 | ret_val = e1000_mng_enable_host_if(hw); 281 | if (ret_val) 282 | return ret_val; 283 | 284 | /* Populate the host interface with the contents of "buffer". */ 285 | ret_val = e1000_mng_host_if_write(hw, buffer, length, 286 | sizeof(hdr), &(hdr.checksum)); 287 | if (ret_val) 288 | return ret_val; 289 | 290 | /* Write the manageability command header */ 291 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); 292 | if (ret_val) 293 | return ret_val; 294 | 295 | /* Tell the ARC a new command is pending. */ 296 | hicr = er32(HICR); 297 | ew32(HICR, hicr | E1000_HICR_C); 298 | 299 | return 0; 300 | } 301 | 302 | #if DISABLED_CODE 303 | 304 | /** 305 | * e1000e_enable_mng_pass_thru - Check if management passthrough is needed 306 | * @hw: pointer to the HW structure 307 | * 308 | * Verifies the hardware needs to leave interface enabled so that frames can 309 | * be directed to and from the management interface. 310 | **/ 311 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) 312 | { 313 | u32 manc; 314 | u32 fwsm, factps; 315 | 316 | manc = er32(MANC); 317 | 318 | if (!(manc & E1000_MANC_RCV_TCO_EN)) 319 | return false; 320 | 321 | if (hw->mac.has_fwsm) { 322 | fwsm = er32(FWSM); 323 | factps = er32(FACTPS); 324 | 325 | if (!(factps & E1000_FACTPS_MNGCG) && 326 | ((fwsm & E1000_FWSM_MODE_MASK) == 327 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) 328 | return true; 329 | } else if ((hw->mac.type == e1000_82574) || 330 | (hw->mac.type == e1000_82583)) { 331 | u16 data; 332 | s32 ret_val; 333 | 334 | factps = er32(FACTPS); 335 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 336 | if (ret_val) 337 | return false; 338 | 339 | if (!(factps & E1000_FACTPS_MNGCG) && 340 | ((data & E1000_NVM_INIT_CTRL2_MNGM) == 341 | (e1000_mng_mode_pt << 13))) 342 | return true; 343 | } else if ((manc & E1000_MANC_SMBUS_EN) && 344 | !(manc & E1000_MANC_ASF_EN)) { 345 | return true; 346 | } 347 | 348 | return false; 349 | } 350 | 351 | #endif /* DISABLED_CODE */ 352 | -------------------------------------------------------------------------------- /IntelMausiEthernet/manage.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_MANAGE_H_ 23 | #define _E1000E_MANAGE_H_ 24 | 25 | bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 26 | bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 27 | s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 28 | bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 29 | 30 | enum e1000_mng_mode { 31 | e1000_mng_mode_none = 0, 32 | e1000_mng_mode_asf, 33 | e1000_mng_mode_pt, 34 | e1000_mng_mode_ipmi, 35 | e1000_mng_mode_host_if_only 36 | }; 37 | 38 | #define E1000_FACTPS_MNGCG 0x20000000 39 | 40 | #define E1000_FWSM_MODE_MASK 0xE 41 | #define E1000_FWSM_MODE_SHIFT 1 42 | 43 | #define E1000_MNG_IAMT_MODE 0x3 44 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 45 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 46 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 47 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 48 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 49 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 50 | 51 | #define E1000_VFTA_ENTRY_SHIFT 5 52 | #define E1000_VFTA_ENTRY_MASK 0x7F 53 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 54 | 55 | #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 56 | /* Driver sets this bit when done to put command in RAM */ 57 | #define E1000_HICR_C 0x02 58 | #define E1000_HICR_SV 0x04 /* Status Validity */ 59 | #define E1000_HICR_FW_RESET_ENABLE 0x40 60 | #define E1000_HICR_FW_RESET 0x80 61 | 62 | /* Intel(R) Active Management Technology signature */ 63 | #define E1000_IAMT_SIGNATURE 0x544D4149 64 | 65 | #endif 66 | -------------------------------------------------------------------------------- /IntelMausiEthernet/mdio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * linux/mdio.h: definitions for MDIO (clause 45) transceivers 3 | * Copyright 2006-2009 Solarflare Communications Inc. 4 | * 5 | * This program is free software; you can redistribute it and/or modify it 6 | * under the terms of the GNU General Public License version 2 as published 7 | * by the Free Software Foundation, incorporated herein by reference. 8 | */ 9 | #ifndef __LINUX_MDIO_H__ 10 | #define __LINUX_MDIO_H__ 11 | 12 | #if DISABLED_CODE 13 | 14 | #include 15 | 16 | #endif /* DISABLED_CODE */ 17 | 18 | static inline bool mdio_phy_id_is_c45(int phy_id) 19 | { 20 | return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK); 21 | } 22 | 23 | static inline __u16 mdio_phy_id_prtad(int phy_id) 24 | { 25 | return (phy_id & MDIO_PHY_ID_PRTAD) >> 5; 26 | } 27 | 28 | static inline __u16 mdio_phy_id_devad(int phy_id) 29 | { 30 | return phy_id & MDIO_PHY_ID_DEVAD; 31 | } 32 | 33 | /** 34 | * struct mdio_if_info - Ethernet controller MDIO interface 35 | * @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown) 36 | * @mmds: Mask of MMDs expected to be present in the PHY. This must be 37 | * non-zero unless @prtad = %MDIO_PRTAD_NONE. 38 | * @mode_support: MDIO modes supported. If %MDIO_SUPPORTS_C22 is set then 39 | * MII register access will be passed through with @devad = 40 | * %MDIO_DEVAD_NONE. If %MDIO_EMULATE_C22 is set then access to 41 | * commonly used clause 22 registers will be translated into 42 | * clause 45 registers. 43 | * @dev: Net device structure 44 | * @mdio_read: Register read function; returns value or negative error code 45 | * @mdio_write: Register write function; returns 0 or negative error code 46 | */ 47 | struct mdio_if_info { 48 | int prtad; 49 | u32 mmds; 50 | unsigned mode_support; 51 | 52 | struct net_device *dev; 53 | int (*mdio_read)(struct net_device *dev, int prtad, int devad, 54 | u16 addr); 55 | int (*mdio_write)(struct net_device *dev, int prtad, int devad, 56 | u16 addr, u16 val); 57 | }; 58 | 59 | #define MDIO_PRTAD_NONE (-1) 60 | #define MDIO_DEVAD_NONE (-1) 61 | #define MDIO_SUPPORTS_C22 1 62 | #define MDIO_SUPPORTS_C45 2 63 | #define MDIO_EMULATE_C22 4 64 | 65 | struct ethtool_cmd; 66 | struct ethtool_pauseparam; 67 | extern int mdio45_probe(struct mdio_if_info *mdio, int prtad); 68 | extern int mdio_set_flag(const struct mdio_if_info *mdio, 69 | int prtad, int devad, u16 addr, int mask, 70 | bool sense); 71 | extern int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmds); 72 | extern int mdio45_nway_restart(const struct mdio_if_info *mdio); 73 | extern void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio, 74 | struct ethtool_cmd *ecmd, 75 | u32 npage_adv, u32 npage_lpa); 76 | 77 | /** 78 | * mdio45_ethtool_gset - get settings for ETHTOOL_GSET 79 | * @mdio: MDIO interface 80 | * @ecmd: Ethtool request structure 81 | * 82 | * Since the CSRs for auto-negotiation using next pages are not fully 83 | * standardised, this function does not attempt to decode them. Use 84 | * mdio45_ethtool_gset_npage() to specify advertisement bits from next 85 | * pages. 86 | */ 87 | static inline void mdio45_ethtool_gset(const struct mdio_if_info *mdio, 88 | struct ethtool_cmd *ecmd) 89 | { 90 | mdio45_ethtool_gset_npage(mdio, ecmd, 0, 0); 91 | } 92 | 93 | extern int mdio_mii_ioctl(const struct mdio_if_info *mdio, 94 | struct mii_ioctl_data *mii_data, int cmd); 95 | 96 | /** 97 | * mmd_eee_cap_to_ethtool_sup_t 98 | * @eee_cap: value of the MMD EEE Capability register 99 | * 100 | * A small helper function that translates MMD EEE Capability (3.20) bits 101 | * to ethtool supported settings. 102 | */ 103 | static inline u32 mmd_eee_cap_to_ethtool_sup_t(u16 eee_cap) 104 | { 105 | u32 supported = 0; 106 | 107 | if (eee_cap & MDIO_EEE_100TX) 108 | supported |= SUPPORTED_100baseT_Full; 109 | if (eee_cap & MDIO_EEE_1000T) 110 | supported |= SUPPORTED_1000baseT_Full; 111 | if (eee_cap & MDIO_EEE_10GT) 112 | supported |= SUPPORTED_10000baseT_Full; 113 | if (eee_cap & MDIO_EEE_1000KX) 114 | supported |= SUPPORTED_1000baseKX_Full; 115 | if (eee_cap & MDIO_EEE_10GKX4) 116 | supported |= SUPPORTED_10000baseKX4_Full; 117 | if (eee_cap & MDIO_EEE_10GKR) 118 | supported |= SUPPORTED_10000baseKR_Full; 119 | 120 | return supported; 121 | } 122 | 123 | /** 124 | * mmd_eee_adv_to_ethtool_adv_t 125 | * @eee_adv: value of the MMD EEE Advertisement/Link Partner Ability registers 126 | * 127 | * A small helper function that translates the MMD EEE Advertisment (7.60) 128 | * and MMD EEE Link Partner Ability (7.61) bits to ethtool advertisement 129 | * settings. 130 | */ 131 | static inline u32 mmd_eee_adv_to_ethtool_adv_t(u16 eee_adv) 132 | { 133 | u32 adv = 0; 134 | 135 | if (eee_adv & MDIO_EEE_100TX) 136 | adv |= ADVERTISED_100baseT_Full; 137 | if (eee_adv & MDIO_EEE_1000T) 138 | adv |= ADVERTISED_1000baseT_Full; 139 | if (eee_adv & MDIO_EEE_10GT) 140 | adv |= ADVERTISED_10000baseT_Full; 141 | if (eee_adv & MDIO_EEE_1000KX) 142 | adv |= ADVERTISED_1000baseKX_Full; 143 | if (eee_adv & MDIO_EEE_10GKX4) 144 | adv |= ADVERTISED_10000baseKX4_Full; 145 | if (eee_adv & MDIO_EEE_10GKR) 146 | adv |= ADVERTISED_10000baseKR_Full; 147 | 148 | return adv; 149 | } 150 | 151 | /** 152 | * ethtool_adv_to_mmd_eee_adv_t 153 | * @adv: the ethtool advertisement settings 154 | * 155 | * A small helper function that translates ethtool advertisement settings 156 | * to EEE advertisements for the MMD EEE Advertisement (7.60) and 157 | * MMD EEE Link Partner Ability (7.61) registers. 158 | */ 159 | static inline u16 ethtool_adv_to_mmd_eee_adv_t(u32 adv) 160 | { 161 | u16 reg = 0; 162 | 163 | if (adv & ADVERTISED_100baseT_Full) 164 | reg |= MDIO_EEE_100TX; 165 | if (adv & ADVERTISED_1000baseT_Full) 166 | reg |= MDIO_EEE_1000T; 167 | if (adv & ADVERTISED_10000baseT_Full) 168 | reg |= MDIO_EEE_10GT; 169 | if (adv & ADVERTISED_1000baseKX_Full) 170 | reg |= MDIO_EEE_1000KX; 171 | if (adv & ADVERTISED_10000baseKX4_Full) 172 | reg |= MDIO_EEE_10GKX4; 173 | if (adv & ADVERTISED_10000baseKR_Full) 174 | reg |= MDIO_EEE_10GKR; 175 | 176 | return reg; 177 | } 178 | 179 | #endif /* __LINUX_MDIO_H__ */ 180 | -------------------------------------------------------------------------------- /IntelMausiEthernet/mii.h: -------------------------------------------------------------------------------- 1 | /* 2 | * linux/mii.h: definitions for MII-compatible transceivers 3 | * Originally drivers/net/sunhme.h. 4 | * 5 | * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 6 | */ 7 | #ifndef __LINUX_MII_H__ 8 | #define __LINUX_MII_H__ 9 | 10 | #if DISABLED_CODE 11 | 12 | #include 13 | #include 14 | 15 | #endif /* DISABLED_CODE */ 16 | 17 | struct ethtool_cmd; 18 | 19 | struct mii_if_info { 20 | int phy_id; 21 | int advertising; 22 | int phy_id_mask; 23 | int reg_num_mask; 24 | 25 | unsigned int full_duplex : 1; /* is full duplex? */ 26 | unsigned int force_media : 1; /* is autoneg. disabled? */ 27 | unsigned int supports_gmii : 1; /* are GMII registers supported? */ 28 | 29 | struct net_device *dev; 30 | int (*mdio_read) (struct net_device *dev, int phy_id, int location); 31 | void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); 32 | }; 33 | 34 | extern int mii_link_ok (struct mii_if_info *mii); 35 | extern int mii_nway_restart (struct mii_if_info *mii); 36 | extern int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd); 37 | extern int mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd); 38 | extern int mii_check_gmii_support(struct mii_if_info *mii); 39 | extern void mii_check_link (struct mii_if_info *mii); 40 | extern unsigned int mii_check_media (struct mii_if_info *mii, 41 | unsigned int ok_to_print, 42 | unsigned int init_media); 43 | extern int generic_mii_ioctl(struct mii_if_info *mii_if, 44 | struct mii_ioctl_data *mii_data, int cmd, 45 | unsigned int *duplex_changed); 46 | 47 | 48 | static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) 49 | { 50 | return (struct mii_ioctl_data *) &rq->ifr_ifru; 51 | } 52 | 53 | /** 54 | * mii_nway_result 55 | * @negotiated: value of MII ANAR and'd with ANLPAR 56 | * 57 | * Given a set of MII abilities, check each bit and returns the 58 | * currently supported media, in the priority order defined by 59 | * IEEE 802.3u. We use LPA_xxx constants but note this is not the 60 | * value of LPA solely, as described above. 61 | * 62 | * The one exception to IEEE 802.3u is that 100baseT4 is placed 63 | * between 100T-full and 100T-half. If your phy does not support 64 | * 100T4 this is fine. If your phy places 100T4 elsewhere in the 65 | * priority order, you will need to roll your own function. 66 | */ 67 | static inline unsigned int mii_nway_result (unsigned int negotiated) 68 | { 69 | unsigned int ret; 70 | 71 | if (negotiated & LPA_100FULL) 72 | ret = LPA_100FULL; 73 | else if (negotiated & LPA_100BASE4) 74 | ret = LPA_100BASE4; 75 | else if (negotiated & LPA_100HALF) 76 | ret = LPA_100HALF; 77 | else if (negotiated & LPA_10FULL) 78 | ret = LPA_10FULL; 79 | else 80 | ret = LPA_10HALF; 81 | 82 | return ret; 83 | } 84 | 85 | /** 86 | * mii_duplex 87 | * @duplex_lock: Non-zero if duplex is locked at full 88 | * @negotiated: value of MII ANAR and'd with ANLPAR 89 | * 90 | * A small helper function for a common case. Returns one 91 | * if the media is operating or locked at full duplex, and 92 | * returns zero otherwise. 93 | */ 94 | static inline unsigned int mii_duplex (unsigned int duplex_lock, 95 | unsigned int negotiated) 96 | { 97 | if (duplex_lock) 98 | return 1; 99 | if (mii_nway_result(negotiated) & LPA_DUPLEX) 100 | return 1; 101 | return 0; 102 | } 103 | 104 | /** 105 | * ethtool_adv_to_mii_adv_t 106 | * @ethadv: the ethtool advertisement settings 107 | * 108 | * A small helper function that translates ethtool advertisement 109 | * settings to phy autonegotiation advertisements for the 110 | * MII_ADVERTISE register. 111 | */ 112 | static inline u32 ethtool_adv_to_mii_adv_t(u32 ethadv) 113 | { 114 | u32 result = 0; 115 | 116 | if (ethadv & ADVERTISED_10baseT_Half) 117 | result |= ADVERTISE_10HALF; 118 | if (ethadv & ADVERTISED_10baseT_Full) 119 | result |= ADVERTISE_10FULL; 120 | if (ethadv & ADVERTISED_100baseT_Half) 121 | result |= ADVERTISE_100HALF; 122 | if (ethadv & ADVERTISED_100baseT_Full) 123 | result |= ADVERTISE_100FULL; 124 | if (ethadv & ADVERTISED_Pause) 125 | result |= ADVERTISE_PAUSE_CAP; 126 | if (ethadv & ADVERTISED_Asym_Pause) 127 | result |= ADVERTISE_PAUSE_ASYM; 128 | 129 | return result; 130 | } 131 | 132 | /** 133 | * mii_adv_to_ethtool_adv_t 134 | * @adv: value of the MII_ADVERTISE register 135 | * 136 | * A small helper function that translates MII_ADVERTISE bits 137 | * to ethtool advertisement settings. 138 | */ 139 | static inline u32 mii_adv_to_ethtool_adv_t(u32 adv) 140 | { 141 | u32 result = 0; 142 | 143 | if (adv & ADVERTISE_10HALF) 144 | result |= ADVERTISED_10baseT_Half; 145 | if (adv & ADVERTISE_10FULL) 146 | result |= ADVERTISED_10baseT_Full; 147 | if (adv & ADVERTISE_100HALF) 148 | result |= ADVERTISED_100baseT_Half; 149 | if (adv & ADVERTISE_100FULL) 150 | result |= ADVERTISED_100baseT_Full; 151 | if (adv & ADVERTISE_PAUSE_CAP) 152 | result |= ADVERTISED_Pause; 153 | if (adv & ADVERTISE_PAUSE_ASYM) 154 | result |= ADVERTISED_Asym_Pause; 155 | 156 | return result; 157 | } 158 | 159 | /** 160 | * ethtool_adv_to_mii_ctrl1000_t 161 | * @ethadv: the ethtool advertisement settings 162 | * 163 | * A small helper function that translates ethtool advertisement 164 | * settings to phy autonegotiation advertisements for the 165 | * MII_CTRL1000 register when in 1000T mode. 166 | */ 167 | static inline u32 ethtool_adv_to_mii_ctrl1000_t(u32 ethadv) 168 | { 169 | u32 result = 0; 170 | 171 | if (ethadv & ADVERTISED_1000baseT_Half) 172 | result |= ADVERTISE_1000HALF; 173 | if (ethadv & ADVERTISED_1000baseT_Full) 174 | result |= ADVERTISE_1000FULL; 175 | 176 | return result; 177 | } 178 | 179 | /** 180 | * mii_ctrl1000_to_ethtool_adv_t 181 | * @adv: value of the MII_CTRL1000 register 182 | * 183 | * A small helper function that translates MII_CTRL1000 184 | * bits, when in 1000Base-T mode, to ethtool 185 | * advertisement settings. 186 | */ 187 | static inline u32 mii_ctrl1000_to_ethtool_adv_t(u32 adv) 188 | { 189 | u32 result = 0; 190 | 191 | if (adv & ADVERTISE_1000HALF) 192 | result |= ADVERTISED_1000baseT_Half; 193 | if (adv & ADVERTISE_1000FULL) 194 | result |= ADVERTISED_1000baseT_Full; 195 | 196 | return result; 197 | } 198 | 199 | /** 200 | * mii_lpa_to_ethtool_lpa_t 201 | * @adv: value of the MII_LPA register 202 | * 203 | * A small helper function that translates MII_LPA 204 | * bits, when in 1000Base-T mode, to ethtool 205 | * LP advertisement settings. 206 | */ 207 | static inline u32 mii_lpa_to_ethtool_lpa_t(u32 lpa) 208 | { 209 | u32 result = 0; 210 | 211 | if (lpa & LPA_LPACK) 212 | result |= ADVERTISED_Autoneg; 213 | 214 | return result | mii_adv_to_ethtool_adv_t(lpa); 215 | } 216 | 217 | /** 218 | * mii_stat1000_to_ethtool_lpa_t 219 | * @adv: value of the MII_STAT1000 register 220 | * 221 | * A small helper function that translates MII_STAT1000 222 | * bits, when in 1000Base-T mode, to ethtool 223 | * advertisement settings. 224 | */ 225 | static inline u32 mii_stat1000_to_ethtool_lpa_t(u32 lpa) 226 | { 227 | u32 result = 0; 228 | 229 | if (lpa & LPA_1000HALF) 230 | result |= ADVERTISED_1000baseT_Half; 231 | if (lpa & LPA_1000FULL) 232 | result |= ADVERTISED_1000baseT_Full; 233 | 234 | return result; 235 | } 236 | 237 | /** 238 | * ethtool_adv_to_mii_adv_x 239 | * @ethadv: the ethtool advertisement settings 240 | * 241 | * A small helper function that translates ethtool advertisement 242 | * settings to phy autonegotiation advertisements for the 243 | * MII_CTRL1000 register when in 1000Base-X mode. 244 | */ 245 | static inline u32 ethtool_adv_to_mii_adv_x(u32 ethadv) 246 | { 247 | u32 result = 0; 248 | 249 | if (ethadv & ADVERTISED_1000baseT_Half) 250 | result |= ADVERTISE_1000XHALF; 251 | if (ethadv & ADVERTISED_1000baseT_Full) 252 | result |= ADVERTISE_1000XFULL; 253 | if (ethadv & ADVERTISED_Pause) 254 | result |= ADVERTISE_1000XPAUSE; 255 | if (ethadv & ADVERTISED_Asym_Pause) 256 | result |= ADVERTISE_1000XPSE_ASYM; 257 | 258 | return result; 259 | } 260 | 261 | /** 262 | * mii_adv_to_ethtool_adv_x 263 | * @adv: value of the MII_CTRL1000 register 264 | * 265 | * A small helper function that translates MII_CTRL1000 266 | * bits, when in 1000Base-X mode, to ethtool 267 | * advertisement settings. 268 | */ 269 | static inline u32 mii_adv_to_ethtool_adv_x(u32 adv) 270 | { 271 | u32 result = 0; 272 | 273 | if (adv & ADVERTISE_1000XHALF) 274 | result |= ADVERTISED_1000baseT_Half; 275 | if (adv & ADVERTISE_1000XFULL) 276 | result |= ADVERTISED_1000baseT_Full; 277 | if (adv & ADVERTISE_1000XPAUSE) 278 | result |= ADVERTISED_Pause; 279 | if (adv & ADVERTISE_1000XPSE_ASYM) 280 | result |= ADVERTISED_Asym_Pause; 281 | 282 | return result; 283 | } 284 | 285 | /** 286 | * mii_lpa_to_ethtool_lpa_x 287 | * @adv: value of the MII_LPA register 288 | * 289 | * A small helper function that translates MII_LPA 290 | * bits, when in 1000Base-X mode, to ethtool 291 | * LP advertisement settings. 292 | */ 293 | static inline u32 mii_lpa_to_ethtool_lpa_x(u32 lpa) 294 | { 295 | u32 result = 0; 296 | 297 | if (lpa & LPA_LPACK) 298 | result |= ADVERTISED_Autoneg; 299 | 300 | return result | mii_adv_to_ethtool_adv_x(lpa); 301 | } 302 | 303 | /** 304 | * mii_advertise_flowctrl - get flow control advertisement flags 305 | * @cap: Flow control capabilities (FLOW_CTRL_RX, FLOW_CTRL_TX or both) 306 | */ 307 | static inline u16 mii_advertise_flowctrl(int cap) 308 | { 309 | u16 adv = 0; 310 | 311 | if (cap & FLOW_CTRL_RX) 312 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 313 | if (cap & FLOW_CTRL_TX) 314 | adv ^= ADVERTISE_PAUSE_ASYM; 315 | 316 | return adv; 317 | } 318 | 319 | /** 320 | * mii_resolve_flowctrl_fdx 321 | * @lcladv: value of MII ADVERTISE register 322 | * @rmtadv: value of MII LPA register 323 | * 324 | * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3 325 | */ 326 | static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv) 327 | { 328 | u8 cap = 0; 329 | 330 | if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) { 331 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; 332 | } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) { 333 | if (lcladv & ADVERTISE_PAUSE_CAP) 334 | cap = FLOW_CTRL_RX; 335 | else if (rmtadv & ADVERTISE_PAUSE_CAP) 336 | cap = FLOW_CTRL_TX; 337 | } 338 | 339 | return cap; 340 | } 341 | 342 | #endif /* __LINUX_MII_H__ */ 343 | -------------------------------------------------------------------------------- /IntelMausiEthernet/nvm.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_NVM_H_ 23 | #define _E1000E_NVM_H_ 24 | 25 | s32 e1000e_acquire_nvm(struct e1000_hw *hw); 26 | 27 | s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); 28 | s32 e1000_read_mac_addr_generic(struct e1000_hw *hw); 29 | s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 30 | u32 pba_num_size); 31 | s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 32 | s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); 33 | s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); 34 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 35 | s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); 36 | void e1000e_release_nvm(struct e1000_hw *hw); 37 | 38 | #define E1000_STM_OPCODE 0xDB00 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /IntelMausiEthernet/param.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #include 23 | #include 24 | #include 25 | 26 | #include "e1000.h" 27 | 28 | /* This is the only thing that needs to be changed to adjust the 29 | * maximum number of ports that the driver can manage. 30 | */ 31 | #define E1000_MAX_NIC 32 32 | 33 | #define OPTION_UNSET -1 34 | #define OPTION_DISABLED 0 35 | #define OPTION_ENABLED 1 36 | 37 | #define COPYBREAK_DEFAULT 256 38 | unsigned int copybreak = COPYBREAK_DEFAULT; 39 | module_param(copybreak, uint, 0644); 40 | MODULE_PARM_DESC(copybreak, 41 | "Maximum size of packet that is copied to a new buffer on receive"); 42 | 43 | /* All parameters are treated the same, as an integer array of values. 44 | * This macro just reduces the need to repeat the same declaration code 45 | * over and over (plus this helps to avoid typo bugs). 46 | */ 47 | #define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 48 | #define E1000_PARAM(X, desc) \ 49 | static int X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 50 | static unsigned int num_##X; \ 51 | module_param_array_named(X, X, int, &num_##X, 0); \ 52 | MODULE_PARM_DESC(X, desc); 53 | 54 | /* Transmit Interrupt Delay in units of 1.024 microseconds 55 | * Tx interrupt delay needs to typically be set to something non-zero 56 | * 57 | * Valid Range: 0-65535 58 | */ 59 | E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay"); 60 | #define DEFAULT_TIDV 8 61 | #define MAX_TXDELAY 0xFFFF 62 | #define MIN_TXDELAY 0 63 | 64 | /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds 65 | * 66 | * Valid Range: 0-65535 67 | */ 68 | E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay"); 69 | #define DEFAULT_TADV 32 70 | #define MAX_TXABSDELAY 0xFFFF 71 | #define MIN_TXABSDELAY 0 72 | 73 | /* Receive Interrupt Delay in units of 1.024 microseconds 74 | * hardware will likely hang if you set this to anything but zero. 75 | * 76 | * Burst variant is used as default if device has FLAG2_DMA_BURST. 77 | * 78 | * Valid Range: 0-65535 79 | */ 80 | E1000_PARAM(RxIntDelay, "Receive Interrupt Delay"); 81 | #define DEFAULT_RDTR 0 82 | #define BURST_RDTR 0x20 83 | #define MAX_RXDELAY 0xFFFF 84 | #define MIN_RXDELAY 0 85 | 86 | /* Receive Absolute Interrupt Delay in units of 1.024 microseconds 87 | * 88 | * Burst variant is used as default if device has FLAG2_DMA_BURST. 89 | * 90 | * Valid Range: 0-65535 91 | */ 92 | E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay"); 93 | #define DEFAULT_RADV 8 94 | #define BURST_RADV 0x20 95 | #define MAX_RXABSDELAY 0xFFFF 96 | #define MIN_RXABSDELAY 0 97 | 98 | /* Interrupt Throttle Rate (interrupts/sec) 99 | * 100 | * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative 101 | */ 102 | E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 103 | #define DEFAULT_ITR 3 104 | #define MAX_ITR 100000 105 | #define MIN_ITR 100 106 | 107 | /* IntMode (Interrupt Mode) 108 | * 109 | * Valid Range: varies depending on kernel configuration & hardware support 110 | * 111 | * legacy=0, MSI=1, MSI-X=2 112 | * 113 | * When MSI/MSI-X support is enabled in kernel- 114 | * Default Value: 2 (MSI-X) when supported by hardware, 1 (MSI) otherwise 115 | * When MSI/MSI-X support is not enabled in kernel- 116 | * Default Value: 0 (legacy) 117 | * 118 | * When a mode is specified that is not allowed/supported, it will be 119 | * demoted to the most advanced interrupt mode available. 120 | */ 121 | E1000_PARAM(IntMode, "Interrupt Mode"); 122 | #define MAX_INTMODE 2 123 | #define MIN_INTMODE 0 124 | 125 | /* Enable Smart Power Down of the PHY 126 | * 127 | * Valid Range: 0, 1 128 | * 129 | * Default Value: 0 (disabled) 130 | */ 131 | E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); 132 | 133 | /* Enable Kumeran Lock Loss workaround 134 | * 135 | * Valid Range: 0, 1 136 | * 137 | * Default Value: 1 (enabled) 138 | */ 139 | E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); 140 | 141 | /* Write Protect NVM 142 | * 143 | * Valid Range: 0, 1 144 | * 145 | * Default Value: 1 (enabled) 146 | */ 147 | E1000_PARAM(WriteProtectNVM, 148 | "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]"); 149 | 150 | /* Enable CRC Stripping 151 | * 152 | * Valid Range: 0, 1 153 | * 154 | * Default Value: 1 (enabled) 155 | */ 156 | E1000_PARAM(CrcStripping, 157 | "Enable CRC Stripping, disable if your BMC needs the CRC"); 158 | 159 | struct e1000_option { 160 | enum { enable_option, range_option, list_option } type; 161 | const char *name; 162 | const char *err; 163 | int def; 164 | union { 165 | /* range_option info */ 166 | struct { 167 | int min; 168 | int max; 169 | } r; 170 | /* list_option info */ 171 | struct { 172 | int nr; 173 | struct e1000_opt_list { 174 | int i; 175 | char *str; 176 | } *p; 177 | } l; 178 | } arg; 179 | }; 180 | 181 | static int e1000_validate_option(unsigned int *value, 182 | const struct e1000_option *opt, 183 | struct e1000_adapter *adapter) 184 | { 185 | if (*value == OPTION_UNSET) { 186 | *value = opt->def; 187 | return 0; 188 | } 189 | 190 | switch (opt->type) { 191 | case enable_option: 192 | switch (*value) { 193 | case OPTION_ENABLED: 194 | dev_info(&adapter->pdev->dev, "%s Enabled\n", 195 | opt->name); 196 | return 0; 197 | case OPTION_DISABLED: 198 | dev_info(&adapter->pdev->dev, "%s Disabled\n", 199 | opt->name); 200 | return 0; 201 | } 202 | break; 203 | case range_option: 204 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { 205 | dev_info(&adapter->pdev->dev, "%s set to %i\n", 206 | opt->name, *value); 207 | return 0; 208 | } 209 | break; 210 | case list_option: { 211 | int i; 212 | struct e1000_opt_list *ent; 213 | 214 | for (i = 0; i < opt->arg.l.nr; i++) { 215 | ent = &opt->arg.l.p[i]; 216 | if (*value == ent->i) { 217 | if (ent->str[0] != '\0') 218 | dev_info(&adapter->pdev->dev, "%s\n", 219 | ent->str); 220 | return 0; 221 | } 222 | } 223 | } 224 | break; 225 | default: 226 | BUG(); 227 | } 228 | 229 | dev_info(&adapter->pdev->dev, "Invalid %s value specified (%i) %s\n", 230 | opt->name, *value, opt->err); 231 | *value = opt->def; 232 | return -1; 233 | } 234 | 235 | /** 236 | * e1000e_check_options - Range Checking for Command Line Parameters 237 | * @adapter: board private structure 238 | * 239 | * This routine checks all command line parameters for valid user 240 | * input. If an invalid value is given, or if no user specified 241 | * value exists, a default value is used. The final value is stored 242 | * in a variable in the adapter structure. 243 | **/ 244 | void e1000e_check_options(struct e1000_adapter *adapter) 245 | { 246 | struct e1000_hw *hw = &adapter->hw; 247 | int bd = adapter->bd_number; 248 | 249 | if (bd >= E1000_MAX_NIC) { 250 | dev_notice(&adapter->pdev->dev, 251 | "Warning: no configuration for board #%i\n", bd); 252 | dev_notice(&adapter->pdev->dev, 253 | "Using defaults for all values\n"); 254 | } 255 | 256 | /* Transmit Interrupt Delay */ 257 | { 258 | static const struct e1000_option opt = { 259 | .type = range_option, 260 | .name = "Transmit Interrupt Delay", 261 | .err = "using default of " 262 | __MODULE_STRING(DEFAULT_TIDV), 263 | .def = DEFAULT_TIDV, 264 | .arg = { .r = { .min = MIN_TXDELAY, 265 | .max = MAX_TXDELAY } } 266 | }; 267 | 268 | if (num_TxIntDelay > bd) { 269 | adapter->tx_int_delay = TxIntDelay[bd]; 270 | e1000_validate_option(&adapter->tx_int_delay, &opt, 271 | adapter); 272 | } else { 273 | adapter->tx_int_delay = opt.def; 274 | } 275 | } 276 | /* Transmit Absolute Interrupt Delay */ 277 | { 278 | static const struct e1000_option opt = { 279 | .type = range_option, 280 | .name = "Transmit Absolute Interrupt Delay", 281 | .err = "using default of " 282 | __MODULE_STRING(DEFAULT_TADV), 283 | .def = DEFAULT_TADV, 284 | .arg = { .r = { .min = MIN_TXABSDELAY, 285 | .max = MAX_TXABSDELAY } } 286 | }; 287 | 288 | if (num_TxAbsIntDelay > bd) { 289 | adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 290 | e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 291 | adapter); 292 | } else { 293 | adapter->tx_abs_int_delay = opt.def; 294 | } 295 | } 296 | /* Receive Interrupt Delay */ 297 | { 298 | static struct e1000_option opt = { 299 | .type = range_option, 300 | .name = "Receive Interrupt Delay", 301 | .err = "using default of " 302 | __MODULE_STRING(DEFAULT_RDTR), 303 | .def = DEFAULT_RDTR, 304 | .arg = { .r = { .min = MIN_RXDELAY, 305 | .max = MAX_RXDELAY } } 306 | }; 307 | 308 | if (adapter->flags2 & FLAG2_DMA_BURST) 309 | opt.def = BURST_RDTR; 310 | 311 | if (num_RxIntDelay > bd) { 312 | adapter->rx_int_delay = RxIntDelay[bd]; 313 | e1000_validate_option(&adapter->rx_int_delay, &opt, 314 | adapter); 315 | } else { 316 | adapter->rx_int_delay = opt.def; 317 | } 318 | } 319 | /* Receive Absolute Interrupt Delay */ 320 | { 321 | static struct e1000_option opt = { 322 | .type = range_option, 323 | .name = "Receive Absolute Interrupt Delay", 324 | .err = "using default of " 325 | __MODULE_STRING(DEFAULT_RADV), 326 | .def = DEFAULT_RADV, 327 | .arg = { .r = { .min = MIN_RXABSDELAY, 328 | .max = MAX_RXABSDELAY } } 329 | }; 330 | 331 | if (adapter->flags2 & FLAG2_DMA_BURST) 332 | opt.def = BURST_RADV; 333 | 334 | if (num_RxAbsIntDelay > bd) { 335 | adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 336 | e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 337 | adapter); 338 | } else { 339 | adapter->rx_abs_int_delay = opt.def; 340 | } 341 | } 342 | /* Interrupt Throttling Rate */ 343 | { 344 | static const struct e1000_option opt = { 345 | .type = range_option, 346 | .name = "Interrupt Throttling Rate (ints/sec)", 347 | .err = "using default of " 348 | __MODULE_STRING(DEFAULT_ITR), 349 | .def = DEFAULT_ITR, 350 | .arg = { .r = { .min = MIN_ITR, 351 | .max = MAX_ITR } } 352 | }; 353 | 354 | if (num_InterruptThrottleRate > bd) { 355 | adapter->itr = InterruptThrottleRate[bd]; 356 | 357 | /* Make sure a message is printed for non-special 358 | * values. And in case of an invalid option, display 359 | * warning, use default and go through itr/itr_setting 360 | * adjustment logic below 361 | */ 362 | if ((adapter->itr > 4) && 363 | e1000_validate_option(&adapter->itr, &opt, adapter)) 364 | adapter->itr = opt.def; 365 | } else { 366 | /* If no option specified, use default value and go 367 | * through the logic below to adjust itr/itr_setting 368 | */ 369 | adapter->itr = opt.def; 370 | 371 | /* Make sure a message is printed for non-special 372 | * default values 373 | */ 374 | if (adapter->itr > 4) 375 | dev_info(&adapter->pdev->dev, 376 | "%s set to default %d\n", opt.name, 377 | adapter->itr); 378 | } 379 | 380 | adapter->itr_setting = adapter->itr; 381 | switch (adapter->itr) { 382 | case 0: 383 | dev_info(&adapter->pdev->dev, "%s turned off\n", 384 | opt.name); 385 | break; 386 | case 1: 387 | dev_info(&adapter->pdev->dev, 388 | "%s set to dynamic mode\n", opt.name); 389 | adapter->itr = 20000; 390 | break; 391 | case 2: 392 | dev_info(&adapter->pdev->dev, 393 | "%s Invalid mode - setting default\n", 394 | opt.name); 395 | adapter->itr_setting = opt.def; 396 | /* fall-through */ 397 | case 3: 398 | dev_info(&adapter->pdev->dev, 399 | "%s set to dynamic conservative mode\n", 400 | opt.name); 401 | adapter->itr = 20000; 402 | break; 403 | case 4: 404 | dev_info(&adapter->pdev->dev, 405 | "%s set to simplified (2000-8000 ints) mode\n", 406 | opt.name); 407 | break; 408 | default: 409 | /* Save the setting, because the dynamic bits 410 | * change itr. 411 | * 412 | * Clear the lower two bits because 413 | * they are used as control. 414 | */ 415 | adapter->itr_setting &= ~3; 416 | break; 417 | } 418 | } 419 | /* Interrupt Mode */ 420 | { 421 | static struct e1000_option opt = { 422 | .type = range_option, 423 | .name = "Interrupt Mode", 424 | #ifndef CONFIG_PCI_MSI 425 | .err = "defaulting to 0 (legacy)", 426 | .def = E1000E_INT_MODE_LEGACY, 427 | .arg = { .r = { .min = 0, 428 | .max = 0 } } 429 | #endif 430 | }; 431 | 432 | #ifdef CONFIG_PCI_MSI 433 | if (adapter->flags & FLAG_HAS_MSIX) { 434 | opt.err = kstrdup("defaulting to 2 (MSI-X)", 435 | GFP_KERNEL); 436 | opt.def = E1000E_INT_MODE_MSIX; 437 | opt.arg.r.max = E1000E_INT_MODE_MSIX; 438 | } else { 439 | opt.err = kstrdup("defaulting to 1 (MSI)", GFP_KERNEL); 440 | opt.def = E1000E_INT_MODE_MSI; 441 | opt.arg.r.max = E1000E_INT_MODE_MSI; 442 | } 443 | 444 | if (!opt.err) { 445 | dev_err(&adapter->pdev->dev, 446 | "Failed to allocate memory\n"); 447 | return; 448 | } 449 | #endif 450 | 451 | if (num_IntMode > bd) { 452 | unsigned int int_mode = IntMode[bd]; 453 | 454 | e1000_validate_option(&int_mode, &opt, adapter); 455 | adapter->int_mode = int_mode; 456 | } else { 457 | adapter->int_mode = opt.def; 458 | } 459 | 460 | #ifdef CONFIG_PCI_MSI 461 | kfree(opt.err); 462 | #endif 463 | } 464 | /* Smart Power Down */ 465 | { 466 | static const struct e1000_option opt = { 467 | .type = enable_option, 468 | .name = "PHY Smart Power Down", 469 | .err = "defaulting to Disabled", 470 | .def = OPTION_DISABLED 471 | }; 472 | 473 | if (num_SmartPowerDownEnable > bd) { 474 | unsigned int spd = SmartPowerDownEnable[bd]; 475 | 476 | e1000_validate_option(&spd, &opt, adapter); 477 | if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && spd) 478 | adapter->flags |= FLAG_SMART_POWER_DOWN; 479 | } 480 | } 481 | /* CRC Stripping */ 482 | { 483 | static const struct e1000_option opt = { 484 | .type = enable_option, 485 | .name = "CRC Stripping", 486 | .err = "defaulting to Enabled", 487 | .def = OPTION_ENABLED 488 | }; 489 | 490 | if (num_CrcStripping > bd) { 491 | unsigned int crc_stripping = CrcStripping[bd]; 492 | 493 | e1000_validate_option(&crc_stripping, &opt, adapter); 494 | if (crc_stripping == OPTION_ENABLED) { 495 | adapter->flags2 |= FLAG2_CRC_STRIPPING; 496 | adapter->flags2 |= FLAG2_DFLT_CRC_STRIPPING; 497 | } 498 | } else { 499 | adapter->flags2 |= FLAG2_CRC_STRIPPING; 500 | adapter->flags2 |= FLAG2_DFLT_CRC_STRIPPING; 501 | } 502 | } 503 | /* Kumeran Lock Loss Workaround */ 504 | { 505 | static const struct e1000_option opt = { 506 | .type = enable_option, 507 | .name = "Kumeran Lock Loss Workaround", 508 | .err = "defaulting to Enabled", 509 | .def = OPTION_ENABLED 510 | }; 511 | bool enabled = opt.def; 512 | 513 | if (num_KumeranLockLoss > bd) { 514 | unsigned int kmrn_lock_loss = KumeranLockLoss[bd]; 515 | 516 | e1000_validate_option(&kmrn_lock_loss, &opt, adapter); 517 | enabled = kmrn_lock_loss; 518 | } 519 | 520 | if (hw->mac.type == e1000_ich8lan) 521 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 522 | enabled); 523 | } 524 | /* Write-protect NVM */ 525 | { 526 | static const struct e1000_option opt = { 527 | .type = enable_option, 528 | .name = "Write-protect NVM", 529 | .err = "defaulting to Enabled", 530 | .def = OPTION_ENABLED 531 | }; 532 | 533 | if (adapter->flags & FLAG_IS_ICH) { 534 | if (num_WriteProtectNVM > bd) { 535 | unsigned int write_protect_nvm = 536 | WriteProtectNVM[bd]; 537 | e1000_validate_option(&write_protect_nvm, &opt, 538 | adapter); 539 | if (write_protect_nvm) 540 | adapter->flags |= FLAG_READ_ONLY_NVM; 541 | } else { 542 | if (opt.def) 543 | adapter->flags |= FLAG_READ_ONLY_NVM; 544 | } 545 | } 546 | } 547 | } 548 | -------------------------------------------------------------------------------- /IntelMausiEthernet/phy.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_PHY_H_ 23 | #define _E1000E_PHY_H_ 24 | 25 | s32 e1000e_check_downshift(struct e1000_hw *hw); 26 | s32 e1000_check_polarity_m88(struct e1000_hw *hw); 27 | s32 e1000_check_polarity_igp(struct e1000_hw *hw); 28 | s32 e1000_check_polarity_ife(struct e1000_hw *hw); 29 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 30 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 31 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 32 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 33 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 34 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 35 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 36 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 37 | s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); 38 | s32 e1000e_get_phy_id(struct e1000_hw *hw); 39 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 40 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 41 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 42 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw); 43 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 44 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 45 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 46 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 47 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 48 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 49 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 50 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 51 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 52 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 53 | s32 e1000e_setup_copper_link(struct e1000_hw *hw); 54 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 55 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 56 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 57 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 58 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 59 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 60 | u32 usec_interval, bool *success); 61 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 62 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 63 | s32 e1000e_determine_phy_address(struct e1000_hw *hw); 64 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 65 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 66 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 67 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 68 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 69 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 70 | void e1000_power_up_phy_copper(struct e1000_hw *hw); 71 | void e1000_power_down_phy_copper(struct e1000_hw *hw); 72 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 73 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 74 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 75 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 76 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 77 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 78 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 79 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 80 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 81 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 82 | s32 e1000_check_polarity_82577(struct e1000_hw *hw); 83 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 84 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 85 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 86 | 87 | #define E1000_MAX_PHY_ADDR 8 88 | 89 | /* IGP01E1000 Specific Registers */ 90 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 91 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 92 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 93 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 94 | #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 95 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 96 | #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 97 | #define IGP_PAGE_SHIFT 5 98 | #define PHY_REG_MASK 0x1F 99 | 100 | /* BM/HV Specific Registers */ 101 | #define BM_PORT_CTRL_PAGE 769 102 | #define BM_WUC_PAGE 800 103 | #define BM_WUC_ADDRESS_OPCODE 0x11 104 | #define BM_WUC_DATA_OPCODE 0x12 105 | #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 106 | #define BM_WUC_ENABLE_REG 17 107 | #define BM_WUC_ENABLE_BIT BIT(2) 108 | #define BM_WUC_HOST_WU_BIT BIT(4) 109 | #define BM_WUC_ME_WU_BIT BIT(5) 110 | 111 | #define PHY_UPPER_SHIFT 21 112 | #define BM_PHY_REG(page, reg) \ 113 | (((reg) & MAX_PHY_REG_ADDRESS) |\ 114 | (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 115 | (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 116 | #define BM_PHY_REG_PAGE(offset) \ 117 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 118 | #define BM_PHY_REG_NUM(offset) \ 119 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 120 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 121 | ~MAX_PHY_REG_ADDRESS))) 122 | 123 | #define HV_INTC_FC_PAGE_START 768 124 | #define I82578_ADDR_REG 29 125 | #define I82577_ADDR_REG 16 126 | #define I82577_CFG_REG 22 127 | #define I82577_CFG_ASSERT_CRS_ON_TX BIT(15) 128 | #define I82577_CFG_ENABLE_DOWNSHIFT (3u << 10) /* auto downshift */ 129 | #define I82577_CTRL_REG 23 130 | 131 | /* 82577 specific PHY registers */ 132 | #define I82577_PHY_CTRL_2 18 133 | #define I82577_PHY_LBK_CTRL 19 134 | #define I82577_PHY_STATUS_2 26 135 | #define I82577_PHY_DIAG_STATUS 31 136 | 137 | /* I82577 PHY Status 2 */ 138 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 139 | #define I82577_PHY_STATUS2_MDIX 0x0800 140 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 141 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 142 | 143 | /* I82577 PHY Control 2 */ 144 | #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 145 | #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 146 | #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 147 | 148 | /* I82577 PHY Diagnostics Status */ 149 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 150 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 151 | 152 | /* BM PHY Copper Specific Control 1 */ 153 | #define BM_CS_CTRL1 16 154 | 155 | /* BM PHY Copper Specific Status */ 156 | #define BM_CS_STATUS 17 157 | #define BM_CS_STATUS_LINK_UP 0x0400 158 | #define BM_CS_STATUS_RESOLVED 0x0800 159 | #define BM_CS_STATUS_SPEED_MASK 0xC000 160 | #define BM_CS_STATUS_SPEED_1000 0x8000 161 | 162 | /* 82577 Mobile Phy Status Register */ 163 | #define HV_M_STATUS 26 164 | #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 165 | #define HV_M_STATUS_SPEED_MASK 0x0300 166 | #define HV_M_STATUS_SPEED_1000 0x0200 167 | #define HV_M_STATUS_SPEED_100 0x0100 168 | #define HV_M_STATUS_LINK_UP 0x0040 169 | 170 | #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 171 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 172 | 173 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 174 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 175 | 176 | #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 177 | 178 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 179 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 180 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 181 | 182 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 183 | 184 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 185 | #define IGP01E1000_PSSR_MDIX 0x0800 186 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 187 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 188 | 189 | #define IGP02E1000_PHY_CHANNEL_NUM 4 190 | #define IGP02E1000_PHY_AGC_A 0x11B1 191 | #define IGP02E1000_PHY_AGC_B 0x12B1 192 | #define IGP02E1000_PHY_AGC_C 0x14B1 193 | #define IGP02E1000_PHY_AGC_D 0x18B1 194 | 195 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 196 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F 197 | #define IGP02E1000_AGC_RANGE 15 198 | 199 | #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 200 | 201 | #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 202 | #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 203 | #define E1000_KMRNCTRLSTA_REN 0x00200000 204 | #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 205 | #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 206 | #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 207 | #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 208 | #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 209 | #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 210 | #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 211 | #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 212 | #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 213 | 214 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 215 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 216 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 217 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 218 | 219 | /* IFE PHY Extended Status Control */ 220 | #define IFE_PESC_POLARITY_REVERSED 0x0100 221 | 222 | /* IFE PHY Special Control */ 223 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 224 | #define IFE_PSC_FORCE_POLARITY 0x0020 225 | 226 | /* IFE PHY Special Control and LED Control */ 227 | #define IFE_PSCL_PROBE_MODE 0x0020 228 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 229 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 230 | 231 | /* IFE PHY MDIX Control */ 232 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 233 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 234 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 235 | 236 | #endif 237 | -------------------------------------------------------------------------------- /IntelMausiEthernet/ptp.c: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | /* PTP 1588 Hardware Clock (PHC) 23 | * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb) 24 | * Copyright (C) 2011 Richard Cochran 25 | */ 26 | 27 | #include "e1000.h" 28 | 29 | #ifdef CONFIG_E1000E_HWTS 30 | #include 31 | #include 32 | #include 33 | #endif 34 | 35 | /** 36 | * e1000e_phc_adjfreq - adjust the frequency of the hardware clock 37 | * @ptp: ptp clock structure 38 | * @delta: Desired frequency change in parts per billion 39 | * 40 | * Adjust the frequency of the PHC cycle counter by the indicated delta from 41 | * the base frequency. 42 | **/ 43 | static int e1000e_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta) 44 | { 45 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 46 | ptp_clock_info); 47 | struct e1000_hw *hw = &adapter->hw; 48 | bool neg_adj = false; 49 | unsigned long flags; 50 | u64 adjustment; 51 | u32 timinca, incvalue; 52 | s32 ret_val; 53 | 54 | if ((delta > ptp->max_adj) || (delta <= -1000000000)) 55 | return -EINVAL; 56 | 57 | if (delta < 0) { 58 | neg_adj = true; 59 | delta = -delta; 60 | } 61 | 62 | /* Get the System Time Register SYSTIM base frequency */ 63 | ret_val = e1000e_get_base_timinca(adapter, &timinca); 64 | if (ret_val) 65 | return ret_val; 66 | 67 | spin_lock_irqsave(&adapter->systim_lock, flags); 68 | 69 | incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK; 70 | 71 | adjustment = incvalue; 72 | adjustment *= delta; 73 | adjustment = div_u64(adjustment, 1000000000); 74 | 75 | incvalue = neg_adj ? (incvalue - adjustment) : (incvalue + adjustment); 76 | 77 | timinca &= ~E1000_TIMINCA_INCVALUE_MASK; 78 | timinca |= incvalue; 79 | 80 | ew32(TIMINCA, timinca); 81 | 82 | adapter->ptp_delta = delta; 83 | 84 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 85 | 86 | return 0; 87 | } 88 | 89 | /** 90 | * e1000e_phc_adjtime - Shift the time of the hardware clock 91 | * @ptp: ptp clock structure 92 | * @delta: Desired change in nanoseconds 93 | * 94 | * Adjust the timer by resetting the timecounter structure. 95 | **/ 96 | static int e1000e_phc_adjtime(struct ptp_clock_info *ptp, s64 delta) 97 | { 98 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 99 | ptp_clock_info); 100 | unsigned long flags; 101 | 102 | spin_lock_irqsave(&adapter->systim_lock, flags); 103 | timecounter_adjtime(&adapter->tc, delta); 104 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 105 | 106 | return 0; 107 | } 108 | 109 | #ifdef CONFIG_E1000E_HWTS 110 | #define MAX_HW_WAIT_COUNT (3) 111 | 112 | /** 113 | * e1000e_phc_get_syncdevicetime - Callback given to timekeeping code reads system/device registers 114 | * @device: current device time 115 | * @system: system counter value read synchronously with device time 116 | * @ctx: context provided by timekeeping code 117 | * 118 | * Read device and system (ART) clock simultaneously and return the corrected 119 | * clock values in ns. 120 | **/ 121 | static int e1000e_phc_get_syncdevicetime(ktime_t *device, 122 | struct system_counterval_t *system, 123 | void *ctx) 124 | { 125 | struct e1000_adapter *adapter = (struct e1000_adapter *)ctx; 126 | struct e1000_hw *hw = &adapter->hw; 127 | unsigned long flags; 128 | int i; 129 | u32 tsync_ctrl; 130 | u64 dev_cycles; 131 | u64 sys_cycles; 132 | 133 | tsync_ctrl = er32(TSYNCTXCTL); 134 | tsync_ctrl |= E1000_TSYNCTXCTL_START_SYNC | 135 | E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK; 136 | ew32(TSYNCTXCTL, tsync_ctrl); 137 | for (i = 0; i < MAX_HW_WAIT_COUNT; ++i) { 138 | udelay(1); 139 | tsync_ctrl = er32(TSYNCTXCTL); 140 | if (tsync_ctrl & E1000_TSYNCTXCTL_SYNC_COMP) 141 | break; 142 | } 143 | 144 | if (i == MAX_HW_WAIT_COUNT) 145 | return -ETIMEDOUT; 146 | 147 | dev_cycles = er32(SYSSTMPH); 148 | dev_cycles <<= 32; 149 | dev_cycles |= er32(SYSSTMPL); 150 | spin_lock_irqsave(&adapter->systim_lock, flags); 151 | *device = ns_to_ktime(timecounter_cyc2time(&adapter->tc, dev_cycles)); 152 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 153 | 154 | sys_cycles = er32(PLTSTMPH); 155 | sys_cycles <<= 32; 156 | sys_cycles |= er32(PLTSTMPL); 157 | *system = convert_art_to_tsc(sys_cycles); 158 | 159 | return 0; 160 | } 161 | 162 | /** 163 | * e1000e_phc_getsynctime - Reads the current system/device cross timestamp 164 | * @ptp: ptp clock structure 165 | * @cts: structure containing timestamp 166 | * 167 | * Read device and system (ART) clock simultaneously and return the scaled 168 | * clock values in ns. 169 | **/ 170 | static int e1000e_phc_getcrosststamp(struct ptp_clock_info *ptp, 171 | struct system_device_crosststamp *xtstamp) 172 | { 173 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 174 | ptp_clock_info); 175 | 176 | return get_device_system_crosststamp(e1000e_phc_get_syncdevicetime, 177 | adapter, NULL, xtstamp); 178 | } 179 | #endif/*CONFIG_E1000E_HWTS*/ 180 | 181 | /** 182 | * e1000e_phc_gettime - Reads the current time from the hardware clock 183 | * @ptp: ptp clock structure 184 | * @ts: timespec structure to hold the current time value 185 | * 186 | * Read the timecounter and return the correct value in ns after converting 187 | * it into a struct timespec. 188 | **/ 189 | static int e1000e_phc_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 190 | { 191 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 192 | ptp_clock_info); 193 | unsigned long flags; 194 | u64 ns; 195 | 196 | spin_lock_irqsave(&adapter->systim_lock, flags); 197 | ns = timecounter_read(&adapter->tc); 198 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 199 | 200 | *ts = ns_to_timespec64(ns); 201 | 202 | return 0; 203 | } 204 | 205 | /** 206 | * e1000e_phc_settime - Set the current time on the hardware clock 207 | * @ptp: ptp clock structure 208 | * @ts: timespec containing the new time for the cycle counter 209 | * 210 | * Reset the timecounter to use a new base value instead of the kernel 211 | * wall timer value. 212 | **/ 213 | static int e1000e_phc_settime(struct ptp_clock_info *ptp, 214 | const struct timespec64 *ts) 215 | { 216 | struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, 217 | ptp_clock_info); 218 | unsigned long flags; 219 | u64 ns; 220 | 221 | ns = timespec64_to_ns(ts); 222 | 223 | /* reset the timecounter */ 224 | spin_lock_irqsave(&adapter->systim_lock, flags); 225 | timecounter_init(&adapter->tc, &adapter->cc, ns); 226 | spin_unlock_irqrestore(&adapter->systim_lock, flags); 227 | 228 | return 0; 229 | } 230 | 231 | /** 232 | * e1000e_phc_enable - enable or disable an ancillary feature 233 | * @ptp: ptp clock structure 234 | * @request: Desired resource to enable or disable 235 | * @on: Caller passes one to enable or zero to disable 236 | * 237 | * Enable (or disable) ancillary features of the PHC subsystem. 238 | * Currently, no ancillary features are supported. 239 | **/ 240 | static int e1000e_phc_enable(struct ptp_clock_info __always_unused *ptp, 241 | struct ptp_clock_request __always_unused *request, 242 | int __always_unused on) 243 | { 244 | return -EOPNOTSUPP; 245 | } 246 | 247 | static void e1000e_systim_overflow_work(struct work_struct *work) 248 | { 249 | struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, 250 | systim_overflow_work.work); 251 | struct e1000_hw *hw = &adapter->hw; 252 | struct timespec64 ts; 253 | 254 | adapter->ptp_clock_info.gettime64(&adapter->ptp_clock_info, &ts); 255 | 256 | e_dbg("SYSTIM overflow check at %lld.%09lu\n", 257 | (long long) ts.tv_sec, ts.tv_nsec); 258 | 259 | schedule_delayed_work(&adapter->systim_overflow_work, 260 | E1000_SYSTIM_OVERFLOW_PERIOD); 261 | } 262 | 263 | static const struct ptp_clock_info e1000e_ptp_clock_info = { 264 | .owner = THIS_MODULE, 265 | .n_alarm = 0, 266 | .n_ext_ts = 0, 267 | .n_per_out = 0, 268 | .n_pins = 0, 269 | .pps = 0, 270 | .adjfreq = e1000e_phc_adjfreq, 271 | .adjtime = e1000e_phc_adjtime, 272 | .gettime64 = e1000e_phc_gettime, 273 | .settime64 = e1000e_phc_settime, 274 | .enable = e1000e_phc_enable, 275 | }; 276 | 277 | /** 278 | * e1000e_ptp_init - initialize PTP for devices which support it 279 | * @adapter: board private structure 280 | * 281 | * This function performs the required steps for enabling PTP support. 282 | * If PTP support has already been loaded it simply calls the cyclecounter 283 | * init routine and exits. 284 | **/ 285 | void e1000e_ptp_init(struct e1000_adapter *adapter) 286 | { 287 | struct e1000_hw *hw = &adapter->hw; 288 | 289 | adapter->ptp_clock = NULL; 290 | 291 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 292 | return; 293 | 294 | adapter->ptp_clock_info = e1000e_ptp_clock_info; 295 | 296 | snprintf(adapter->ptp_clock_info.name, 297 | sizeof(adapter->ptp_clock_info.name), "%pm", 298 | adapter->netdev->perm_addr); 299 | 300 | switch (hw->mac.type) { 301 | case e1000_pch2lan: 302 | case e1000_pch_lpt: 303 | case e1000_pch_spt: 304 | case e1000_pch_cnp: 305 | if ((hw->mac.type < e1000_pch_lpt) || 306 | (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { 307 | adapter->ptp_clock_info.max_adj = 24000000 - 1; 308 | break; 309 | } 310 | /* fall-through */ 311 | case e1000_82574: 312 | case e1000_82583: 313 | adapter->ptp_clock_info.max_adj = 600000000 - 1; 314 | break; 315 | default: 316 | break; 317 | } 318 | 319 | #ifdef CONFIG_E1000E_HWTS 320 | /* CPU must have ART and GBe must be from Sunrise Point or greater */ 321 | if (hw->mac.type >= e1000_pch_spt && boot_cpu_has(X86_FEATURE_ART)) 322 | adapter->ptp_clock_info.getcrosststamp = 323 | e1000e_phc_getcrosststamp; 324 | #endif/*CONFIG_E1000E_HWTS*/ 325 | 326 | INIT_DELAYED_WORK(&adapter->systim_overflow_work, 327 | e1000e_systim_overflow_work); 328 | 329 | schedule_delayed_work(&adapter->systim_overflow_work, 330 | E1000_SYSTIM_OVERFLOW_PERIOD); 331 | 332 | adapter->ptp_clock = ptp_clock_register(&adapter->ptp_clock_info, 333 | &adapter->pdev->dev); 334 | if (IS_ERR(adapter->ptp_clock)) { 335 | adapter->ptp_clock = NULL; 336 | e_err("ptp_clock_register failed\n"); 337 | } else if (adapter->ptp_clock) { 338 | e_info("registered PHC clock\n"); 339 | } 340 | } 341 | 342 | /** 343 | * e1000e_ptp_remove - disable PTP device and stop the overflow check 344 | * @adapter: board private structure 345 | * 346 | * Stop the PTP support, and cancel the delayed work. 347 | **/ 348 | void e1000e_ptp_remove(struct e1000_adapter *adapter) 349 | { 350 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) 351 | return; 352 | 353 | cancel_delayed_work_sync(&adapter->systim_overflow_work); 354 | 355 | if (adapter->ptp_clock) { 356 | ptp_clock_unregister(adapter->ptp_clock); 357 | adapter->ptp_clock = NULL; 358 | e_info("removed PHC\n"); 359 | } 360 | } 361 | -------------------------------------------------------------------------------- /IntelMausiEthernet/regs.h: -------------------------------------------------------------------------------- 1 | /* Intel PRO/1000 Linux driver 2 | * Copyright(c) 1999 - 2015 Intel Corporation. 3 | * 4 | * This program is free software; you can redistribute it and/or modify it 5 | * under the terms and conditions of the GNU General Public License, 6 | * version 2, as published by the Free Software Foundation. 7 | * 8 | * This program is distributed in the hope it will be useful, but WITHOUT 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 | * more details. 12 | * 13 | * The full GNU General Public License is included in this distribution in 14 | * the file called "COPYING". 15 | * 16 | * Contact Information: 17 | * Linux NICS 18 | * e1000-devel Mailing List 19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 | */ 21 | 22 | #ifndef _E1000E_REGS_H_ 23 | #define _E1000E_REGS_H_ 24 | 25 | #define E1000_CTRL 0x00000 /* Device Control - RW */ 26 | #define E1000_STATUS 0x00008 /* Device Status - RO */ 27 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 28 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 29 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 30 | #define E1000_FLA 0x0001C /* Flash Access - RW */ 31 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ 32 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 33 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 34 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 35 | #define E1000_FEXT 0x0002C /* Future Extended - RW */ 36 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 37 | #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 38 | #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 39 | #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 40 | #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 41 | #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ 42 | #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ 43 | #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ 44 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 45 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 46 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 47 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 48 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 49 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 50 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 51 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 52 | #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 53 | #define E1000_SVCR 0x000F0 54 | #define E1000_SVT 0x000F4 55 | #define E1000_LPIC 0x000FC /* Low Power IDLE control */ 56 | #define E1000_RCTL 0x00100 /* Rx Control - RW */ 57 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 58 | #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 59 | #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 60 | #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 61 | #define E1000_TCTL 0x00400 /* Tx Control - RW */ 62 | #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ 63 | #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ 64 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 65 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 66 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 67 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 68 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 69 | #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ 70 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 71 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ 72 | #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 73 | #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ 74 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 75 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 76 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 77 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 78 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 79 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 80 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 81 | #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ 82 | #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ 83 | #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ 84 | #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ 85 | #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ 86 | /* Split and Replication Rx Control - RW */ 87 | #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 88 | #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 89 | /* Convenience macros 90 | * 91 | * Note: "_n" is the queue number of the register to be written to. 92 | * 93 | * Example usage: 94 | * E1000_RDBAL_REG(current_rx_queue) 95 | */ 96 | #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 97 | (0x0C000 + ((_n) * 0x40))) 98 | #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 99 | (0x0C004 + ((_n) * 0x40))) 100 | #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 101 | (0x0C008 + ((_n) * 0x40))) 102 | #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 103 | (0x0C010 + ((_n) * 0x40))) 104 | #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 105 | (0x0C018 + ((_n) * 0x40))) 106 | #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 107 | (0x0C028 + ((_n) * 0x40))) 108 | #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 109 | (0x0E000 + ((_n) * 0x40))) 110 | #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 111 | (0x0E004 + ((_n) * 0x40))) 112 | #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 113 | (0x0E008 + ((_n) * 0x40))) 114 | #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 115 | (0x0E010 + ((_n) * 0x40))) 116 | #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 117 | (0x0E018 + ((_n) * 0x40))) 118 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 119 | (0x0E028 + ((_n) * 0x40))) 120 | #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) 121 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 122 | #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 123 | (0x054E0 + ((_i - 16) * 8))) 124 | #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 125 | (0x054E4 + ((_i - 16) * 8))) 126 | #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 127 | #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 128 | #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 129 | #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 130 | #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 131 | #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 132 | #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 133 | #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ 134 | #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ 135 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 136 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 137 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 138 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 139 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 140 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 141 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 142 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 143 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 144 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 145 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ 146 | #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ 147 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 148 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 149 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 150 | #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ 151 | #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ 152 | #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ 153 | #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ 154 | #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ 155 | #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ 156 | #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ 157 | #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ 158 | #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ 159 | #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ 160 | #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ 161 | #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ 162 | #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ 163 | #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ 164 | #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ 165 | #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ 166 | #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ 167 | #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ 168 | #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ 169 | #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ 170 | #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ 171 | #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ 172 | #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ 173 | #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ 174 | #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ 175 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 176 | #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ 177 | #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ 178 | #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ 179 | #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ 180 | #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ 181 | #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ 182 | #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ 183 | #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ 184 | #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ 185 | #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ 186 | #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ 187 | #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ 188 | #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ 189 | #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ 190 | #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ 191 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ 192 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ 193 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 194 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 195 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 196 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 197 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 198 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 199 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 200 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 201 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 202 | #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 203 | 204 | #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 205 | #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 206 | #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 207 | #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 208 | #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ 209 | #define E1000_RFCTL 0x05008 /* Receive Filter Control */ 210 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 211 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ 212 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 213 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 214 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 215 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 216 | #define E1000_MANC 0x05820 /* Management Control - RW */ 217 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 218 | #define E1000_HOST_IF 0x08800 /* Host Interface */ 219 | 220 | #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 221 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 222 | /* Management Decision Filters */ 223 | #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 224 | #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ 225 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 226 | #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 227 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 228 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ 229 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ 230 | /* Driver-only SW semaphore (not used by BOOT agents) */ 231 | #define E1000_SWSM2 0x05B58 232 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 233 | #define E1000_HICR 0x08F00 /* Host Interface Control */ 234 | 235 | /* RSS registers */ 236 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 237 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ 238 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ 239 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 240 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 241 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 242 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 243 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 244 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 245 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 246 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 247 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 248 | #define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ 249 | #define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ 250 | #define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ 251 | #define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ 252 | #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 253 | #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 254 | 255 | #endif 256 | -------------------------------------------------------------------------------- /IntelMausiEthernet/uapi-ip.h: -------------------------------------------------------------------------------- 1 | /* 2 | * INET An implementation of the TCP/IP protocol suite for the LINUX 3 | * operating system. INET is implemented using the BSD Socket 4 | * interface as the means of communication with the user level. 5 | * 6 | * Definitions for the IP protocol. 7 | * 8 | * Version: @(#)ip.h 1.0.2 04/28/93 9 | * 10 | * Authors: Fred N. van Kempen, 11 | * 12 | * This program is free software; you can redistribute it and/or 13 | * modify it under the terms of the GNU General Public License 14 | * as published by the Free Software Foundation; either version 15 | * 2 of the License, or (at your option) any later version. 16 | */ 17 | #ifndef _UAPI_LINUX_IP_H 18 | #define _UAPI_LINUX_IP_H 19 | 20 | #if DISABLED_CODE 21 | 22 | #include 23 | #include 24 | 25 | #endif /* DISABLED_CODE */ 26 | 27 | #define IPTOS_TOS_MASK 0x1E 28 | #define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) 29 | #define IPTOS_LOWDELAY 0x10 30 | #define IPTOS_THROUGHPUT 0x08 31 | #define IPTOS_RELIABILITY 0x04 32 | #define IPTOS_MINCOST 0x02 33 | 34 | #define IPTOS_PREC_MASK 0xE0 35 | #define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) 36 | #define IPTOS_PREC_NETCONTROL 0xe0 37 | #define IPTOS_PREC_INTERNETCONTROL 0xc0 38 | #define IPTOS_PREC_CRITIC_ECP 0xa0 39 | #define IPTOS_PREC_FLASHOVERRIDE 0x80 40 | #define IPTOS_PREC_FLASH 0x60 41 | #define IPTOS_PREC_IMMEDIATE 0x40 42 | #define IPTOS_PREC_PRIORITY 0x20 43 | #define IPTOS_PREC_ROUTINE 0x00 44 | 45 | #if DISABLED_CODE 46 | 47 | /* IP options */ 48 | #define IPOPT_COPY 0x80 49 | #define IPOPT_CLASS_MASK 0x60 50 | #define IPOPT_NUMBER_MASK 0x1f 51 | 52 | #define IPOPT_COPIED(o) ((o)&IPOPT_COPY) 53 | #define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) 54 | #define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) 55 | 56 | #define IPOPT_CONTROL 0x00 57 | #define IPOPT_RESERVED1 0x20 58 | #define IPOPT_MEASUREMENT 0x40 59 | #define IPOPT_RESERVED2 0x60 60 | 61 | #define IPOPT_END (0 |IPOPT_CONTROL) 62 | #define IPOPT_NOOP (1 |IPOPT_CONTROL) 63 | #define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY) 64 | #define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY) 65 | #define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT) 66 | #define IPOPT_CIPSO (6 |IPOPT_CONTROL|IPOPT_COPY) 67 | #define IPOPT_RR (7 |IPOPT_CONTROL) 68 | #define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY) 69 | #define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY) 70 | #define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY) 71 | 72 | #define IPVERSION 4 73 | #define MAXTTL 255 74 | #define IPDEFTTL 64 75 | 76 | #define IPOPT_OPTVAL 0 77 | #define IPOPT_OLEN 1 78 | #define IPOPT_OFFSET 2 79 | #define IPOPT_MINOFF 4 80 | #define MAX_IPOPTLEN 40 81 | #define IPOPT_NOP IPOPT_NOOP 82 | #define IPOPT_EOL IPOPT_END 83 | #define IPOPT_TS IPOPT_TIMESTAMP 84 | 85 | #define IPOPT_TS_TSONLY 0 /* timestamps only */ 86 | #define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ 87 | #define IPOPT_TS_PRESPEC 3 /* specified modules only */ 88 | 89 | #define IPV4_BEET_PHMAXLEN 8 90 | 91 | #endif /* DISABLED_CODE */ 92 | 93 | struct iphdr { 94 | #if defined(__LITTLE_ENDIAN_BITFIELD) 95 | __u8 ihl:4, 96 | version:4; 97 | #elif defined (__BIG_ENDIAN_BITFIELD) 98 | __u8 version:4, 99 | ihl:4; 100 | #else 101 | #error "Please fix " 102 | #endif 103 | __u8 tos; 104 | __be16 tot_len; 105 | __be16 id; 106 | __be16 frag_off; 107 | __u8 ttl; 108 | __u8 protocol; 109 | __sum16 check; 110 | __be32 saddr; 111 | __be32 daddr; 112 | /*The options start here. */ 113 | }; 114 | 115 | 116 | struct ip_auth_hdr { 117 | __u8 nexthdr; 118 | __u8 hdrlen; /* This one is measured in 32 bit units! */ 119 | __be16 reserved; 120 | __be32 spi; 121 | __be32 seq_no; /* Sequence number */ 122 | __u8 auth_data[0]; /* Variable len but >=4. Mind the 64 bit alignment! */ 123 | }; 124 | 125 | struct ip_esp_hdr { 126 | __be32 spi; 127 | __be32 seq_no; /* Sequence number */ 128 | __u8 enc_data[0]; /* Variable len but >=8. Mind the 64 bit alignment! */ 129 | }; 130 | 131 | struct ip_comp_hdr { 132 | __u8 nexthdr; 133 | __u8 flags; 134 | __be16 cpi; 135 | }; 136 | 137 | struct ip_beet_phdr { 138 | __u8 nexthdr; 139 | __u8 hdrlen; 140 | __u8 padlen; 141 | __u8 reserved; 142 | }; 143 | 144 | /* index values for the variables in ipv4_devconf */ 145 | enum 146 | { 147 | IPV4_DEVCONF_FORWARDING=1, 148 | IPV4_DEVCONF_MC_FORWARDING, 149 | IPV4_DEVCONF_PROXY_ARP, 150 | IPV4_DEVCONF_ACCEPT_REDIRECTS, 151 | IPV4_DEVCONF_SECURE_REDIRECTS, 152 | IPV4_DEVCONF_SEND_REDIRECTS, 153 | IPV4_DEVCONF_SHARED_MEDIA, 154 | IPV4_DEVCONF_RP_FILTER, 155 | IPV4_DEVCONF_ACCEPT_SOURCE_ROUTE, 156 | IPV4_DEVCONF_BOOTP_RELAY, 157 | IPV4_DEVCONF_LOG_MARTIANS, 158 | IPV4_DEVCONF_TAG, 159 | IPV4_DEVCONF_ARPFILTER, 160 | IPV4_DEVCONF_MEDIUM_ID, 161 | IPV4_DEVCONF_NOXFRM, 162 | IPV4_DEVCONF_NOPOLICY, 163 | IPV4_DEVCONF_FORCE_IGMP_VERSION, 164 | IPV4_DEVCONF_ARP_ANNOUNCE, 165 | IPV4_DEVCONF_ARP_IGNORE, 166 | IPV4_DEVCONF_PROMOTE_SECONDARIES, 167 | IPV4_DEVCONF_ARP_ACCEPT, 168 | IPV4_DEVCONF_ARP_NOTIFY, 169 | IPV4_DEVCONF_ACCEPT_LOCAL, 170 | IPV4_DEVCONF_SRC_VMARK, 171 | IPV4_DEVCONF_PROXY_ARP_PVLAN, 172 | IPV4_DEVCONF_ROUTE_LOCALNET, 173 | IPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL, 174 | IPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL, 175 | __IPV4_DEVCONF_MAX 176 | }; 177 | 178 | #define IPV4_DEVCONF_MAX (__IPV4_DEVCONF_MAX - 1) 179 | 180 | #endif /* _UAPI_LINUX_IP_H */ 181 | -------------------------------------------------------------------------------- /IntelMausiEthernet/uapi-mdio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * linux/mdio.h: definitions for MDIO (clause 45) transceivers 3 | * Copyright 2006-2009 Solarflare Communications Inc. 4 | * 5 | * This program is free software; you can redistribute it and/or modify it 6 | * under the terms of the GNU General Public License version 2 as published 7 | * by the Free Software Foundation, incorporated herein by reference. 8 | */ 9 | 10 | #ifndef _UAPI__LINUX_MDIO_H__ 11 | #define _UAPI__LINUX_MDIO_H__ 12 | 13 | #if DISABLED_CODE 14 | 15 | #include 16 | #include 17 | 18 | #endif /* DISABLED_CODE */ 19 | 20 | /* MDIO Manageable Devices (MMDs). */ 21 | #define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/ 22 | * Physical Medium Dependent */ 23 | #define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */ 24 | #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ 25 | #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */ 26 | #define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */ 27 | #define MDIO_MMD_TC 6 /* Transmission Convergence */ 28 | #define MDIO_MMD_AN 7 /* Auto-Negotiation */ 29 | #define MDIO_MMD_C22EXT 29 /* Clause 22 extension */ 30 | #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ 31 | #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ 32 | 33 | /* Generic MDIO registers. */ 34 | #define MDIO_CTRL1 MII_BMCR 35 | #define MDIO_STAT1 MII_BMSR 36 | #define MDIO_DEVID1 MII_PHYSID1 37 | #define MDIO_DEVID2 MII_PHYSID2 38 | #define MDIO_SPEED 4 /* Speed ability */ 39 | #define MDIO_DEVS1 5 /* Devices in package */ 40 | #define MDIO_DEVS2 6 41 | #define MDIO_CTRL2 7 /* 10G control 2 */ 42 | #define MDIO_STAT2 8 /* 10G status 2 */ 43 | #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */ 44 | #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */ 45 | #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */ 46 | #define MDIO_PKGID1 14 /* Package identifier */ 47 | #define MDIO_PKGID2 15 48 | #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */ 49 | #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */ 50 | #define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */ 51 | #define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */ 52 | #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */ 53 | #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */ 54 | #define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */ 55 | 56 | /* Media-dependent registers. */ 57 | #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */ 58 | #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */ 59 | #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A. 60 | * Lanes B-D are numbered 134-136. */ 61 | #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */ 62 | #define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */ 63 | #define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */ 64 | #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ 65 | #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ 66 | #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ 67 | 68 | /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ 69 | #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ 70 | #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */ 71 | #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */ 72 | #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */ 73 | #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */ 74 | #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */ 75 | 76 | /* Control register 1. */ 77 | /* Enable extended speed selection */ 78 | #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 79 | /* All speed selection bits */ 80 | #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 81 | #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 82 | #define MDIO_CTRL1_LPOWER BMCR_PDOWN 83 | #define MDIO_CTRL1_RESET BMCR_RESET 84 | #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 85 | #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 86 | #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 87 | #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 88 | #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 89 | #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 90 | #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 91 | #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */ 92 | #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */ 93 | 94 | /* 10 Gb/s */ 95 | #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 96 | /* 10PASS-TS/2BASE-TL */ 97 | #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 98 | 99 | /* Status register 1. */ 100 | #define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */ 101 | #define MDIO_STAT1_LSTATUS BMSR_LSTATUS 102 | #define MDIO_STAT1_FAULT 0x0080 /* Fault */ 103 | #define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */ 104 | #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 105 | #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 106 | #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 107 | #define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */ 108 | #define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */ 109 | 110 | /* Speed register. */ 111 | #define MDIO_SPEED_10G 0x0001 /* 10G capable */ 112 | #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */ 113 | #define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */ 114 | #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ 115 | #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ 116 | #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ 117 | #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ 118 | 119 | /* Device present registers. */ 120 | #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) 121 | #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 122 | #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 123 | #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 124 | #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 125 | #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 126 | #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 127 | #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 128 | #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 129 | 130 | /* Control register 2. */ 131 | #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */ 132 | #define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */ 133 | #define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */ 134 | #define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */ 135 | #define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */ 136 | #define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */ 137 | #define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */ 138 | #define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */ 139 | #define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */ 140 | #define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */ 141 | #define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */ 142 | #define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */ 143 | #define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */ 144 | #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */ 145 | #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */ 146 | #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */ 147 | #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */ 148 | #define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */ 149 | #define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */ 150 | #define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */ 151 | #define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */ 152 | #define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */ 153 | 154 | /* Status register 2. */ 155 | #define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */ 156 | #define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */ 157 | #define MDIO_STAT2_DEVPRST 0xc000 /* Device present */ 158 | #define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */ 159 | #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */ 160 | #define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */ 161 | #define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */ 162 | #define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */ 163 | #define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */ 164 | #define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */ 165 | #define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */ 166 | #define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */ 167 | #define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */ 168 | #define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */ 169 | #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 170 | #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 171 | #define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */ 172 | #define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */ 173 | #define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */ 174 | #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */ 175 | #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */ 176 | 177 | /* Transmit disable register. */ 178 | #define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */ 179 | #define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */ 180 | #define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */ 181 | #define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */ 182 | #define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */ 183 | 184 | /* Receive signal detect register. */ 185 | #define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */ 186 | #define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */ 187 | #define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */ 188 | #define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */ 189 | #define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */ 190 | 191 | /* Extended abilities register. */ 192 | #define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */ 193 | #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */ 194 | #define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */ 195 | #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */ 196 | #define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */ 197 | #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */ 198 | #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */ 199 | #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */ 200 | #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */ 201 | 202 | /* PHY XGXS lane state register. */ 203 | #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 204 | #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 205 | #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 206 | #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 207 | #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 208 | 209 | /* PMA 10GBASE-T pair swap & polarity */ 210 | #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */ 211 | #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */ 212 | #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */ 213 | #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */ 214 | #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */ 215 | #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */ 216 | 217 | /* PMA 10GBASE-T TX power register. */ 218 | #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */ 219 | 220 | /* PMA 10GBASE-T SNR registers. */ 221 | /* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */ 222 | #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 223 | #define MDIO_PMA_10GBT_SNR_MAX 127 224 | 225 | /* PMA 10GBASE-R FEC ability register. */ 226 | #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */ 227 | #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */ 228 | 229 | /* PCS 10GBASE-R/-T status register 1. */ 230 | #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */ 231 | 232 | /* PCS 10GBASE-R/-T status register 2. */ 233 | #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 234 | #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 235 | 236 | /* AN 10GBASE-T control register. */ 237 | #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */ 238 | 239 | /* AN 10GBASE-T status register. */ 240 | #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */ 241 | #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */ 242 | #define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */ 243 | #define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */ 244 | #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */ 245 | #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ 246 | #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ 247 | 248 | /* EEE Supported/Advertisement/LP Advertisement registers. 249 | * 250 | * EEE capability Register (3.20), Advertisement (7.60) and 251 | * Link partner ability (7.61) registers have and can use the same identical 252 | * bit masks. 253 | */ 254 | #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */ 255 | #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */ 256 | /* Note: the two defines above can be potentially used by the user-land 257 | * and cannot remove them now. 258 | * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros 259 | * using the previous ones (that can be considered obsolete). 260 | */ 261 | #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */ 262 | #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */ 263 | #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */ 264 | #define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */ 265 | #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */ 266 | #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */ 267 | 268 | /* LASI RX_ALARM control/status registers. */ 269 | #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ 270 | #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ 271 | #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */ 272 | #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */ 273 | #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */ 274 | 275 | /* LASI TX_ALARM control/status registers. */ 276 | #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */ 277 | #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */ 278 | #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */ 279 | #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */ 280 | #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */ 281 | #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */ 282 | 283 | /* LASI control/status registers. */ 284 | #define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */ 285 | #define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */ 286 | #define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */ 287 | 288 | /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */ 289 | 290 | #define MDIO_PHY_ID_C45 0x8000 291 | #define MDIO_PHY_ID_PRTAD 0x03e0 292 | #define MDIO_PHY_ID_DEVAD 0x001f 293 | #define MDIO_PHY_ID_C45_MASK \ 294 | (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 295 | 296 | static inline __u16 mdio_phy_id_c45(int prtad, int devad) 297 | { 298 | return MDIO_PHY_ID_C45 | (prtad << 5) | devad; 299 | } 300 | 301 | #endif /* _UAPI__LINUX_MDIO_H__ */ 302 | -------------------------------------------------------------------------------- /IntelMausiEthernet/uapi-mii.h: -------------------------------------------------------------------------------- 1 | /* 2 | * linux/mii.h: definitions for MII-compatible transceivers 3 | * Originally drivers/net/sunhme.h. 4 | * 5 | * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) 6 | */ 7 | 8 | #ifndef _UAPI__LINUX_MII_H__ 9 | #define _UAPI__LINUX_MII_H__ 10 | 11 | #if DISABLED_CODE 12 | 13 | #include 14 | #include 15 | 16 | #endif /* DISABLED_CODE */ 17 | 18 | /* Generic MII registers. */ 19 | #define MII_BMCR 0x00 /* Basic mode control register */ 20 | #define MII_BMSR 0x01 /* Basic mode status register */ 21 | #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 22 | #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 23 | #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 24 | #define MII_LPA 0x05 /* Link partner ability reg */ 25 | #define MII_EXPANSION 0x06 /* Expansion register */ 26 | #define MII_CTRL1000 0x09 /* 1000BASE-T control */ 27 | #define MII_STAT1000 0x0a /* 1000BASE-T status */ 28 | #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 29 | #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 30 | #define MII_ESTATUS 0x0f /* Extended Status */ 31 | #define MII_DCOUNTER 0x12 /* Disconnect counter */ 32 | #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 33 | #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 34 | #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 35 | #define MII_SREVISION 0x16 /* Silicon revision */ 36 | #define MII_RESV1 0x17 /* Reserved... */ 37 | #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 38 | #define MII_PHYADDR 0x19 /* PHY address */ 39 | #define MII_RESV2 0x1a /* Reserved... */ 40 | #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 41 | #define MII_NCONFIG 0x1c /* Network interface config */ 42 | 43 | /* Basic mode control register. */ 44 | #define BMCR_RESV 0x003f /* Unused... */ 45 | #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ 46 | #define BMCR_CTST 0x0080 /* Collision test */ 47 | #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 48 | #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 49 | #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ 50 | #define BMCR_PDOWN 0x0800 /* Enable low power state */ 51 | #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 52 | #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 53 | #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 54 | #define BMCR_RESET 0x8000 /* Reset to default state */ 55 | 56 | /* Basic mode status register. */ 57 | #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 58 | #define BMSR_JCD 0x0002 /* Jabber detected */ 59 | #define BMSR_LSTATUS 0x0004 /* Link status */ 60 | #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 61 | #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 62 | #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 63 | #define BMSR_RESV 0x00c0 /* Unused... */ 64 | #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ 65 | #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ 66 | #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ 67 | #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 68 | #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 69 | #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 70 | #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 71 | #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 72 | 73 | /* Advertisement control register. */ 74 | #define ADVERTISE_SLCT 0x001f /* Selector bits */ 75 | #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 76 | #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 77 | #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ 78 | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 79 | #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ 80 | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 81 | #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ 82 | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 83 | #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ 84 | #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 85 | #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 86 | #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 87 | #define ADVERTISE_RESV 0x1000 /* Unused... */ 88 | #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 89 | #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 90 | #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 91 | 92 | #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 93 | ADVERTISE_CSMA) 94 | #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 95 | ADVERTISE_100HALF | ADVERTISE_100FULL) 96 | 97 | /* Link partner ability register. */ 98 | #define LPA_SLCT 0x001f /* Same as advertise selector */ 99 | #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 100 | #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ 101 | #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 102 | #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ 103 | #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 104 | #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ 105 | #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 106 | #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ 107 | #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 108 | #define LPA_PAUSE_CAP 0x0400 /* Can pause */ 109 | #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 110 | #define LPA_RESV 0x1000 /* Unused... */ 111 | #define LPA_RFAULT 0x2000 /* Link partner faulted */ 112 | #define LPA_LPACK 0x4000 /* Link partner acked us */ 113 | #define LPA_NPAGE 0x8000 /* Next page bit */ 114 | 115 | #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 116 | #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 117 | 118 | /* Expansion register for auto-negotiation. */ 119 | #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ 120 | #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ 121 | #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ 122 | #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ 123 | #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ 124 | #define EXPANSION_RESV 0xffe0 /* Unused... */ 125 | 126 | #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ 127 | #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ 128 | 129 | /* N-way test register. */ 130 | #define NWAYTEST_RESV1 0x00ff /* Unused... */ 131 | #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ 132 | #define NWAYTEST_RESV2 0xfe00 /* Unused... */ 133 | 134 | /* 1000BASE-T Control register */ 135 | #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ 136 | #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ 137 | #define CTL1000_AS_MASTER 0x0800 138 | #define CTL1000_ENABLE_MASTER 0x1000 139 | 140 | /* 1000BASE-T Status register */ 141 | #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ 142 | #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ 143 | #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ 144 | #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ 145 | 146 | /* Flow control flags */ 147 | #define FLOW_CTRL_TX 0x01 148 | #define FLOW_CTRL_RX 0x02 149 | 150 | /* MMD Access Control register fields */ 151 | #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 152 | #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 153 | #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 154 | #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 155 | #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 156 | 157 | /* This structure is used in all SIOCxMIIxxx ioctl calls */ 158 | struct mii_ioctl_data { 159 | __u16 phy_id; 160 | __u16 reg_num; 161 | __u16 val_in; 162 | __u16 val_out; 163 | }; 164 | 165 | #endif /* _UAPI__LINUX_MII_H__ */ 166 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## Fork Intel Mausi Network Driver by RehabMan 2 | 3 | I added the implementation of IOKernelDebugger with IOKDP 4 | 5 | So anyone use these NIC can do the kernel debugging between two real machine. 6 | 7 | Details about how to make this happen. please refer https://www.tonymacx86.com/threads/discussion-about-how-to-make-nvidia-web-driver-works-in-macos-10-14-mojave.265813/#post-1863247 8 | 9 | 10 | 11 | 12 | ### How to Install: 13 | copy the /Volume/EFI/EFI/CLOVER/kexts/Other 14 | 15 | 16 | ### How to debug: 17 | 18 | Install the KDK from developer.apple.com 19 | 20 | Please follow the KDK readme.html. 21 | 22 | lldb will search /Library/Developer/KDKs/ as well as any local directories indexed by Spotlight. 23 | 24 | You invoke lldb by the simple command: 25 | 26 | lldb 27 | 28 | Alternatively, you can specify the kernel file on the command line. 29 | 30 | lldb /Library/Developer/KDKs//System/Library/Kernels/kernel 31 | 32 | To attach, you either use kdp-remote for a live connection, or file -c for a coredump. 33 | 34 | kdp-remote {name_or_ip_address} 35 | file -c {path_to_coredump} 36 | 37 | Two machine debugging is not supported via USB Ethernet. 38 | Two machine debugging is not supported via wireless. 39 | 40 | Network Debugging 41 | 42 | The default setting for two machine debugging is as follows: 43 | 44 | sudo nvram boot-args="debug=0x146" 45 | sudo reboot 46 | 47 | 48 | 49 | You can raise the debug event after network is initialized using the combo key : 50 | 51 | shift + ctrl + option + comand + esc 52 | 53 | 54 | 55 | 56 | ### Original README follows: 57 | 58 | # IntelMausiEthernet 59 | OS X driver for Intel onboard LAN 60 | 61 | A few days before Christmas I started my latest project, a new driver for recent Intel onboard LAN controllers. My intention was not to replace hnak's AppleIntelE1000e.kext completely but to deliver best performance and stability on recent hardware. That's why I dropped support for a number of older NICs. Currently the driver supports: 62 | 63 | - 5 Series 64 | - 82578LM 65 | - 82578LC 66 | - 82578DM 67 | - 82578DC 68 | - 6 and 7 Series 69 | - 82579LM 70 | - 82579V 71 | - 8 and 9 Series 72 | - I217LM 73 | - I217V 74 | - I218LM 75 | - I218V 76 | - I218LM2 77 | - I218V2 78 | - I218LM3 79 | - 100 Series 80 | - I219V 81 | - I219LM 82 | - I219V2 83 | - I219LM2 84 | - I219LM3 85 | 86 | Key Features of the Driver 87 | - Support for multisegment packets relieving the network stack of unnecessary copy operations when assembling packets for transmission. 88 | - No-copy receive and transmit. Only small packets are copied on reception because creating a copy is more efficient than allocating a new buffer. 89 | - TCP, UDP and IPv4 checksum offload (receive and transmit). 90 | - Support for TCP/IPv6 and UDP/IPv6 checksum offload. 91 | - Makes use of the chip's TCP Segmentation Offload (TSO) feature with IPv4 and IPv6 in order to reduce CPU load while sending large amounts of data. 92 | - Fully optimized for Yosemite and Mavericks (64bit architecture) but should work with Mountain Lion and Lion too, provided you build from source with the 10.8 or 10.7 SDK. 93 | - Support for Energy Efficient Ethernet (EEE). 94 | - VLAN support is implemented but untested as I have no need for it. 95 | - The driver is published under GPLv2. 96 | -------------------------------------------------------------------------------- /build/Products/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aerror2/IntelMausiEthernetWithKernelDebugger/027cc348fbc0b466042c2650395d90bec45acd45/build/Products/.DS_Store -------------------------------------------------------------------------------- /build/Products/Debug/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aerror2/IntelMausiEthernetWithKernelDebugger/027cc348fbc0b466042c2650395d90bec45acd45/build/Products/Debug/.DS_Store -------------------------------------------------------------------------------- /build/Products/Debug/IntelMausiEthernet.kext/Contents/Info.plist: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | BuildMachineOSBuild 6 | 18B75 7 | CFBundleDevelopmentRegion 8 | English 9 | CFBundleExecutable 10 | IntelMausiEthernet 11 | CFBundleIdentifier 12 | com.insanelymac.IntelMausiEthernet 13 | CFBundleInfoDictionaryVersion 14 | 6.0 15 | CFBundleName 16 | IntelMausiEthernet 17 | CFBundlePackageType 18 | KEXT 19 | CFBundleShortVersionString 20 | 2.4.1d1 21 | CFBundleSignature 22 | ???? 23 | CFBundleSupportedPlatforms 24 | 25 | MacOSX 26 | 27 | CFBundleVersion 28 | 2.4.1d1 29 | DTCompiler 30 | com.apple.compilers.llvm.clang.1_0 31 | DTPlatformBuild 32 | 9E145 33 | DTPlatformVersion 34 | GM 35 | DTSDKBuild 36 | 17E189 37 | DTSDKName 38 | macosx10.13 39 | DTXcode 40 | 0930 41 | DTXcodeBuild 42 | 9E145 43 | IOKitPersonalities 44 | 45 | IntelMausi 46 | 47 | CFBundleIdentifier 48 | com.insanelymac.IntelMausiEthernet 49 | Driver_Version 50 | 2.4.1d1 51 | IOClass 52 | IntelMausi 53 | IOPCIMatch 54 | 0x10EA8086 0x10EB8086 0x10EF8086 0x10F08086 0x15028086 0x15038086 0x153A8086 0x153B8086 0x155A8086 0x15598086 0x15A08086 0x15A18086 0x15A28086 0x15A38086 0x156F8086 0x15708086 0x15B78086 0x15B88086 0x15D78086 0x15D88086 0x15E38086 0x15D68086 0x15BD8086 0x15BE8086 0x15BB8086 0x15BC8086 0x15DF8086 0x15E08086 0x15E18086 0x15E28086 55 | IOProbeScore 56 | 1000 57 | IOProviderClass 58 | IOPCIDevice 59 | enableCSO6 60 | 61 | enableTSO4 62 | 63 | enableTSO6 64 | 65 | maxIntrRate 66 | 7000 67 | 68 | 69 | NSHumanReadableCopyright 70 | Copyright © 2014 Laura Müller. All rights reserved. 71 | OSBundleLibraries 72 | 73 | com.apple.iokit.IONetworkingFamily 74 | 1.5.0 75 | com.apple.iokit.IOPCIFamily 76 | 1.7 77 | com.apple.kpi.bsd 78 | 8.10.0 79 | com.apple.kpi.iokit 80 | 8.10.0 81 | com.apple.kpi.libkern 82 | 8.10.0 83 | com.apple.kpi.mach 84 | 8.10.0 85 | 86 | OSBundleRequired 87 | Network-Root 88 | 89 | 90 | -------------------------------------------------------------------------------- /build/Products/Debug/IntelMausiEthernet.kext/Contents/MacOS/IntelMausiEthernet: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/aerror2/IntelMausiEthernetWithKernelDebugger/027cc348fbc0b466042c2650395d90bec45acd45/build/Products/Debug/IntelMausiEthernet.kext/Contents/MacOS/IntelMausiEthernet -------------------------------------------------------------------------------- /build/Products/IntelMausiEthernet.build/Debug/IntelMausiEthernet.build/DerivedSources/IntelMausiEthernet_info.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | extern kern_return_t _start(kmod_info_t *ki, void *data); 4 | extern kern_return_t _stop(kmod_info_t *ki, void *data); 5 | 6 | __attribute__((visibility("default"))) KMOD_EXPLICIT_DECL(com.insanelymac.IntelMausiEthernet, "2.4.1d1", _start, _stop) 7 | __private_extern__ kmod_start_func_t *_realmain = 0; 8 | __private_extern__ kmod_stop_func_t *_antimain = 0; 9 | __private_extern__ int _kext_apple_cc = __APPLE_CC__ ; 10 | -------------------------------------------------------------------------------- /build/Products/IntelMausiEthernet.build/Debug/IntelMausiEthernet.build/IntelMausiEthernet-all-non-framework-target-headers.hmap: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /build/Products/IntelMausiEthernet.build/Debug/IntelMausiEthernet.build/Objects-normal/x86_64/IntelMausiEthernet_dependency_info.dat: -------------------------------------------------------------------------------- 1 | @(#)PROGRAM:ld PROJECT:ld64-351.8 2 | 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-DKERNEL_PRIVATE 18 | -DDRIVER_PRIVATE 19 | -DAPPLE 20 | -DNeXT 21 | -isysroot 22 | /Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk 23 | -mmacosx-version-min=10.11 24 | -g 25 | -iquote 26 | -iquote 27 | -I/Volumes/evo/crack/RehabMan-os-x-intel-network-be6e695b4112/build/Products/Debug/include 28 | -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk/System/Library/Frameworks/Kernel.framework/PrivateHeaders 29 | -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk/System/Library/Frameworks/Kernel.framework/Headers 30 | -F/Volumes/evo/crack/RehabMan-os-x-intel-network-be6e695b4112/build/Products/Debug 31 | x86_64-apple-darwin17.7.0 32 | "4.2.1 Compatible Apple LLVM 9.1.0 (clang-902.0.39.1)" 33 | SDK_PRODUCT_BUILD_VERSION=17E189 34 | 17E189 35 | -------------------------------------------------------------------------------- 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/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk 25 | -fapple-kext 26 | -mmacosx-version-min=10.11 27 | -g 28 | -iquote 29 | -iquote 30 | -I/Volumes/evo/crack/RehabMan-os-x-intel-network-be6e695b4112/build/Products/Debug/include 31 | -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk/System/Library/Frameworks/Kernel.framework/PrivateHeaders 32 | -I/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.13.sdk/System/Library/Frameworks/Kernel.framework/Headers 33 | -F/Volumes/evo/crack/RehabMan-os-x-intel-network-be6e695b4112/build/Products/Debug 34 | x86_64-apple-darwin17.7.0 35 | "4.2.1 Compatible Apple LLVM 9.1.0 (clang-902.0.39.1)" 36 | SDK_PRODUCT_BUILD_VERSION=17E189 37 | 17E189 38 | -------------------------------------------------------------------------------- /makefile: -------------------------------------------------------------------------------- 1 | KEXT=IntelMausiEthernet.kext 2 | DIST=RehabMan-IntelMausiEthernet-v2 3 | BUILDDIR=./Build/Products 4 | 5 | VERSION_ERA=$(shell ./print_version.sh) 6 | ifeq "$(VERSION_ERA)" "10.10-" 7 | INSTDIR=/System/Library/Extensions 8 | else 9 | INSTDIR=/Library/Extensions 10 | endif 11 | 12 | OPTIONS:=$(OPTIONS) -scheme IntelMausiEthernet 13 | 14 | ifeq ($(findstring 32,$(BITS)),32) 15 | OPTIONS:=$(OPTIONS) -arch i386 16 | endif 17 | 18 | ifeq ($(findstring 64,$(BITS)),64) 19 | OPTIONS:=$(OPTIONS) -arch x86_64 20 | endif 21 | 22 | .PHONY: all 23 | all: 24 | xcodebuild build $(OPTIONS) -configuration Debug 25 | xcodebuild build $(OPTIONS) -configuration Release 26 | 27 | .PHONY: clean 28 | clean: 29 | xcodebuild clean $(OPTIONS) -configuration Debug 30 | xcodebuild clean $(OPTIONS) -configuration Release 31 | 32 | .PHONY: update_kernelcache 33 | update_kernelcache: 34 | sudo touch /System/Library/Extensions 35 | sudo kextcache -update-volume / 36 | 37 | .PHONY: install_debug 38 | install_debug: 39 | sudo cp -R $(BUILDDIR)/Debug/$(KEXT) $(INSTDIR) 40 | if [ "`which tag`" != "" ]; then sudo tag -a Purple $(INSTDIR)/$(KEXT); fi 41 | make update_kernelcache 42 | 43 | .PHONY: install 44 | install: 45 | sudo cp -R $(BUILDDIR)/Release/$(KEXT) $(INSTDIR) 46 | if [ "`which tag`" != "" ]; then sudo tag -a Blue $(INSTDIR)/$(KEXT); fi 47 | make update_kernelcache 48 | 49 | .PHONY: distribute 50 | distribute: 51 | if [ -e ./Distribute ]; then rm -r ./Distribute; fi 52 | mkdir ./Distribute 53 | cp -R $(BUILDDIR)/Debug ./Distribute 54 | cp -R $(BUILDDIR)/Release ./Distribute 55 | find ./Distribute -path *.DS_Store -delete 56 | find ./Distribute -path *.dSYM -exec echo rm -r {} \; >/tmp/org.voodoo.rm.dsym.sh 57 | chmod +x /tmp/org.voodoo.rm.dsym.sh 58 | /tmp/org.voodoo.rm.dsym.sh 59 | rm /tmp/org.voodoo.rm.dsym.sh 60 | ditto -c -k --sequesterRsrc --zlibCompressionLevel 9 ./Distribute ./Archive.zip 61 | mv ./Archive.zip ./Distribute/`date +$(DIST)-%Y-%m%d.zip` 62 | -------------------------------------------------------------------------------- /print_version.sh: -------------------------------------------------------------------------------- 1 | #set -x 2 | 3 | # extract minor version (eg. 10.9 vs. 10.10 vs. 10.11) 4 | MINOR_VER=$([[ "$(sw_vers -productVersion)" =~ [0-9]+\.([0-9]+) ]] && echo ${BASH_REMATCH[1]}) 5 | if [[ $MINOR_VER -ge 11 ]]; then 6 | echo 10.11+ 7 | else 8 | echo 10.10- 9 | fi 10 | --------------------------------------------------------------------------------