├── .gitignore ├── .mxproject ├── Inc ├── main.h ├── stm32f4xx_hal_conf.h └── stm32f4xx_it.h ├── LICENSE ├── Lib ├── r820t2.c └── r820t2.h ├── Makefile ├── README.md ├── STM32F405RGTx_FLASH.ld ├── Src ├── gpio.tmp ├── license.tmp ├── main.c ├── stm32f4xx_hal_msp.c ├── stm32f4xx_it.c ├── system.tmp └── system_stm32f4xx.c ├── cubefix.sh ├── main.ioc ├── mx.scratch └── startup_stm32f405xx.s /.gitignore: -------------------------------------------------------------------------------- 1 | build 2 | *.backup 3 | -------------------------------------------------------------------------------- /.mxproject: -------------------------------------------------------------------------------- 1 | [PreviousGenFiles] 2 | HeaderPath=/home/eax/projects/sandbox/stm32/stm32-r820t2/Inc 3 | HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; 4 | SourcePath=/home/eax/projects/sandbox/stm32/stm32-r820t2/Src 5 | SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; 6 | 7 | [PreviousLibFiles] 8 | LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/cmsis_armcc.h; 9 | 10 | [PreviousUsedMakefileFiles] 11 | SourceFiles=Src/main.c;Src/stm32f4xx_it.c;Src/stm32f4xx_hal_msp.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Src/system_stm32f4xx.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s; 12 | HeaderPath=/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Inc;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Device/ST/STM32F4xx/Include;/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Include;Inc; 13 | 14 | -------------------------------------------------------------------------------- /Inc/main.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * File Name : main.hpp 4 | * Description : This file contains the common defines of the application 5 | ****************************************************************************** 6 | ** This notice applies to any and all portions of this file 7 | * that are not between comment pairs USER CODE BEGIN and 8 | * USER CODE END. Other portions of this file, whether 9 | * inserted by the user or by software development tools 10 | * are owned by their respective copyright owners. 11 | * 12 | * COPYRIGHT(c) 2018 STMicroelectronics 13 | * 14 | * Redistribution and use in source and binary forms, with or without modification, 15 | * are permitted provided that the following conditions are met: 16 | * 1. Redistributions of source code must retain the above copyright notice, 17 | * this list of conditions and the following disclaimer. 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 22 | * may be used to endorse or promote products derived from this software 23 | * without specific prior written permission. 24 | * 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 | * 36 | ****************************************************************************** 37 | */ 38 | /* Define to prevent recursive inclusion -------------------------------------*/ 39 | #ifndef __MAIN_H 40 | #define __MAIN_H 41 | /* Includes ------------------------------------------------------------------*/ 42 | 43 | /* Includes ------------------------------------------------------------------*/ 44 | /* USER CODE BEGIN Includes */ 45 | 46 | /* USER CODE END Includes */ 47 | 48 | /* Private define ------------------------------------------------------------*/ 49 | 50 | #define ULED_Pin GPIO_PIN_2 51 | #define ULED_GPIO_Port GPIOD 52 | 53 | /* ########################## Assert Selection ############################## */ 54 | /** 55 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 56 | * HAL drivers code 57 | */ 58 | /* #define USE_FULL_ASSERT 1U */ 59 | 60 | /* USER CODE BEGIN Private defines */ 61 | 62 | /* USER CODE END Private defines */ 63 | 64 | #ifdef __cplusplus 65 | extern "C" { 66 | #endif 67 | void _Error_Handler(char *, int); 68 | 69 | #define Error_Handler() _Error_Handler(__FILE__, __LINE__) 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | #endif /* __MAIN_H */ 83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 84 | -------------------------------------------------------------------------------- /Inc/stm32f4xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_hal_conf.h 4 | * @brief HAL configuration file. 5 | ****************************************************************************** 6 | * @attention 7 | * 8 | *

© COPYRIGHT(c) 2018 STMicroelectronics

9 | * 10 | * Redistribution and use in source and binary forms, with or without modification, 11 | * are permitted provided that the following conditions are met: 12 | * 1. Redistributions of source code must retain the above copyright notice, 13 | * this list of conditions and the following disclaimer. 14 | * 2. Redistributions in binary form must reproduce the above copyright notice, 15 | * this list of conditions and the following disclaimer in the documentation 16 | * and/or other materials provided with the distribution. 17 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 18 | * may be used to endorse or promote products derived from this software 19 | * without specific prior written permission. 20 | * 21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 25 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | * 32 | ****************************************************************************** 33 | */ 34 | 35 | /* Define to prevent recursive inclusion -------------------------------------*/ 36 | #ifndef __STM32F4xx_HAL_CONF_H 37 | #define __STM32F4xx_HAL_CONF_H 38 | 39 | #ifdef __cplusplus 40 | extern "C" { 41 | #endif 42 | 43 | #include "main.h" 44 | /* Exported types ------------------------------------------------------------*/ 45 | /* Exported constants --------------------------------------------------------*/ 46 | 47 | /* ########################## Module Selection ############################## */ 48 | /** 49 | * @brief This is the list of modules to be used in the HAL driver 50 | */ 51 | #define HAL_MODULE_ENABLED 52 | 53 | /* #define HAL_ADC_MODULE_ENABLED */ 54 | /* #define HAL_CRYP_MODULE_ENABLED */ 55 | /* #define HAL_CAN_MODULE_ENABLED */ 56 | /* #define HAL_CRC_MODULE_ENABLED */ 57 | /* #define HAL_CRYP_MODULE_ENABLED */ 58 | /* #define HAL_DAC_MODULE_ENABLED */ 59 | /* #define HAL_DCMI_MODULE_ENABLED */ 60 | /* #define HAL_DMA2D_MODULE_ENABLED */ 61 | /* #define HAL_ETH_MODULE_ENABLED */ 62 | /* #define HAL_NAND_MODULE_ENABLED */ 63 | /* #define HAL_NOR_MODULE_ENABLED */ 64 | /* #define HAL_PCCARD_MODULE_ENABLED */ 65 | /* #define HAL_SRAM_MODULE_ENABLED */ 66 | /* #define HAL_SDRAM_MODULE_ENABLED */ 67 | /* #define HAL_HASH_MODULE_ENABLED */ 68 | #define HAL_I2C_MODULE_ENABLED 69 | /* #define HAL_I2S_MODULE_ENABLED */ 70 | /* #define HAL_IWDG_MODULE_ENABLED */ 71 | /* #define HAL_LTDC_MODULE_ENABLED */ 72 | /* #define HAL_RNG_MODULE_ENABLED */ 73 | /* #define HAL_RTC_MODULE_ENABLED */ 74 | /* #define HAL_SAI_MODULE_ENABLED */ 75 | /* #define HAL_SD_MODULE_ENABLED */ 76 | /* #define HAL_MMC_MODULE_ENABLED */ 77 | /* #define HAL_SPI_MODULE_ENABLED */ 78 | /* #define HAL_TIM_MODULE_ENABLED */ 79 | #define HAL_UART_MODULE_ENABLED 80 | /* #define HAL_USART_MODULE_ENABLED */ 81 | /* #define HAL_IRDA_MODULE_ENABLED */ 82 | /* #define HAL_SMARTCARD_MODULE_ENABLED */ 83 | /* #define HAL_WWDG_MODULE_ENABLED */ 84 | /* #define HAL_PCD_MODULE_ENABLED */ 85 | /* #define HAL_HCD_MODULE_ENABLED */ 86 | /* #define HAL_DSI_MODULE_ENABLED */ 87 | /* #define HAL_QSPI_MODULE_ENABLED */ 88 | /* #define HAL_QSPI_MODULE_ENABLED */ 89 | /* #define HAL_CEC_MODULE_ENABLED */ 90 | /* #define HAL_FMPI2C_MODULE_ENABLED */ 91 | /* #define HAL_SPDIFRX_MODULE_ENABLED */ 92 | /* #define HAL_DFSDM_MODULE_ENABLED */ 93 | /* #define HAL_LPTIM_MODULE_ENABLED */ 94 | #define HAL_GPIO_MODULE_ENABLED 95 | #define HAL_DMA_MODULE_ENABLED 96 | #define HAL_RCC_MODULE_ENABLED 97 | #define HAL_FLASH_MODULE_ENABLED 98 | #define HAL_PWR_MODULE_ENABLED 99 | #define HAL_CORTEX_MODULE_ENABLED 100 | 101 | /* ########################## HSE/HSI Values adaptation ##################### */ 102 | /** 103 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 104 | * This value is used by the RCC HAL module to compute the system frequency 105 | * (when HSE is used as system clock source, directly or through the PLL). 106 | */ 107 | #if !defined (HSE_VALUE) 108 | #define HSE_VALUE ((uint32_t)16000000U) /*!< Value of the External oscillator in Hz */ 109 | #endif /* HSE_VALUE */ 110 | 111 | #if !defined (HSE_STARTUP_TIMEOUT) 112 | #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ 113 | #endif /* HSE_STARTUP_TIMEOUT */ 114 | 115 | /** 116 | * @brief Internal High Speed oscillator (HSI) value. 117 | * This value is used by the RCC HAL module to compute the system frequency 118 | * (when HSI is used as system clock source, directly or through the PLL). 119 | */ 120 | #if !defined (HSI_VALUE) 121 | #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ 122 | #endif /* HSI_VALUE */ 123 | 124 | /** 125 | * @brief Internal Low Speed oscillator (LSI) value. 126 | */ 127 | #if !defined (LSI_VALUE) 128 | #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ 129 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 130 | The real value may vary depending on the variations 131 | in voltage and temperature.*/ 132 | /** 133 | * @brief External Low Speed oscillator (LSE) value. 134 | */ 135 | #if !defined (LSE_VALUE) 136 | #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ 137 | #endif /* LSE_VALUE */ 138 | 139 | #if !defined (LSE_STARTUP_TIMEOUT) 140 | #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ 141 | #endif /* LSE_STARTUP_TIMEOUT */ 142 | 143 | /** 144 | * @brief External clock source for I2S peripheral 145 | * This value is used by the I2S HAL module to compute the I2S clock source 146 | * frequency, this source is inserted directly through I2S_CKIN pad. 147 | */ 148 | #if !defined (EXTERNAL_CLOCK_VALUE) 149 | #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ 150 | #endif /* EXTERNAL_CLOCK_VALUE */ 151 | 152 | /* Tip: To avoid modifying this file each time you need to use different HSE, 153 | === you can define the HSE value in your toolchain compiler preprocessor. */ 154 | 155 | /* ########################### System Configuration ######################### */ 156 | /** 157 | * @brief This is the HAL system configuration section 158 | */ 159 | #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ 160 | #define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ 161 | #define USE_RTOS 0U 162 | #define PREFETCH_ENABLE 1U 163 | #define INSTRUCTION_CACHE_ENABLE 1U 164 | #define DATA_CACHE_ENABLE 1U 165 | 166 | /* ########################## Assert Selection ############################## */ 167 | /** 168 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 169 | * HAL drivers code 170 | */ 171 | /* #define USE_FULL_ASSERT 1U */ 172 | 173 | /* ################## Ethernet peripheral configuration ##################### */ 174 | 175 | /* Section 1 : Ethernet peripheral configuration */ 176 | 177 | /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ 178 | #define MAC_ADDR0 2U 179 | #define MAC_ADDR1 0U 180 | #define MAC_ADDR2 0U 181 | #define MAC_ADDR3 0U 182 | #define MAC_ADDR4 0U 183 | #define MAC_ADDR5 0U 184 | 185 | /* Definition of the Ethernet driver buffers size and count */ 186 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ 187 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ 188 | #define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ 189 | #define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ 190 | 191 | /* Section 2: PHY configuration section */ 192 | 193 | /* DP83848_PHY_ADDRESS Address*/ 194 | #define DP83848_PHY_ADDRESS 0x01U 195 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 196 | #define PHY_RESET_DELAY ((uint32_t)0x000000FFU) 197 | /* PHY Configuration delay */ 198 | #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) 199 | 200 | #define PHY_READ_TO ((uint32_t)0x0000FFFFU) 201 | #define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) 202 | 203 | /* Section 3: Common PHY Registers */ 204 | 205 | #define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ 206 | #define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ 207 | 208 | #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ 209 | #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ 210 | #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ 211 | #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ 212 | #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ 213 | #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ 214 | #define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ 215 | #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ 216 | #define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ 217 | #define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ 218 | 219 | #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ 220 | #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ 221 | #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ 222 | 223 | /* Section 4: Extended PHY Registers */ 224 | #define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ 225 | 226 | #define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ 227 | #define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ 228 | 229 | /* ################## SPI peripheral configuration ########################## */ 230 | 231 | /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver 232 | * Activated: CRC code is present inside driver 233 | * Deactivated: CRC code cleaned from driver 234 | */ 235 | 236 | #define USE_SPI_CRC 0U 237 | 238 | /* Includes ------------------------------------------------------------------*/ 239 | /** 240 | * @brief Include module's header file 241 | */ 242 | 243 | #ifdef HAL_RCC_MODULE_ENABLED 244 | #include "stm32f4xx_hal_rcc.h" 245 | #endif /* HAL_RCC_MODULE_ENABLED */ 246 | 247 | #ifdef HAL_GPIO_MODULE_ENABLED 248 | #include "stm32f4xx_hal_gpio.h" 249 | #endif /* HAL_GPIO_MODULE_ENABLED */ 250 | 251 | #ifdef HAL_DMA_MODULE_ENABLED 252 | #include "stm32f4xx_hal_dma.h" 253 | #endif /* HAL_DMA_MODULE_ENABLED */ 254 | 255 | #ifdef HAL_CORTEX_MODULE_ENABLED 256 | #include "stm32f4xx_hal_cortex.h" 257 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 258 | 259 | #ifdef HAL_ADC_MODULE_ENABLED 260 | #include "stm32f4xx_hal_adc.h" 261 | #endif /* HAL_ADC_MODULE_ENABLED */ 262 | 263 | #ifdef HAL_CAN_MODULE_ENABLED 264 | #include "stm32f4xx_hal_can.h" 265 | #endif /* HAL_CAN_MODULE_ENABLED */ 266 | 267 | #ifdef HAL_CRC_MODULE_ENABLED 268 | #include "stm32f4xx_hal_crc.h" 269 | #endif /* HAL_CRC_MODULE_ENABLED */ 270 | 271 | #ifdef HAL_CRYP_MODULE_ENABLED 272 | #include "stm32f4xx_hal_cryp.h" 273 | #endif /* HAL_CRYP_MODULE_ENABLED */ 274 | 275 | #ifdef HAL_DMA2D_MODULE_ENABLED 276 | #include "stm32f4xx_hal_dma2d.h" 277 | #endif /* HAL_DMA2D_MODULE_ENABLED */ 278 | 279 | #ifdef HAL_DAC_MODULE_ENABLED 280 | #include "stm32f4xx_hal_dac.h" 281 | #endif /* HAL_DAC_MODULE_ENABLED */ 282 | 283 | #ifdef HAL_DCMI_MODULE_ENABLED 284 | #include "stm32f4xx_hal_dcmi.h" 285 | #endif /* HAL_DCMI_MODULE_ENABLED */ 286 | 287 | #ifdef HAL_ETH_MODULE_ENABLED 288 | #include "stm32f4xx_hal_eth.h" 289 | #endif /* HAL_ETH_MODULE_ENABLED */ 290 | 291 | #ifdef HAL_FLASH_MODULE_ENABLED 292 | #include "stm32f4xx_hal_flash.h" 293 | #endif /* HAL_FLASH_MODULE_ENABLED */ 294 | 295 | #ifdef HAL_SRAM_MODULE_ENABLED 296 | #include "stm32f4xx_hal_sram.h" 297 | #endif /* HAL_SRAM_MODULE_ENABLED */ 298 | 299 | #ifdef HAL_NOR_MODULE_ENABLED 300 | #include "stm32f4xx_hal_nor.h" 301 | #endif /* HAL_NOR_MODULE_ENABLED */ 302 | 303 | #ifdef HAL_NAND_MODULE_ENABLED 304 | #include "stm32f4xx_hal_nand.h" 305 | #endif /* HAL_NAND_MODULE_ENABLED */ 306 | 307 | #ifdef HAL_PCCARD_MODULE_ENABLED 308 | #include "stm32f4xx_hal_pccard.h" 309 | #endif /* HAL_PCCARD_MODULE_ENABLED */ 310 | 311 | #ifdef HAL_SDRAM_MODULE_ENABLED 312 | #include "stm32f4xx_hal_sdram.h" 313 | #endif /* HAL_SDRAM_MODULE_ENABLED */ 314 | 315 | #ifdef HAL_HASH_MODULE_ENABLED 316 | #include "stm32f4xx_hal_hash.h" 317 | #endif /* HAL_HASH_MODULE_ENABLED */ 318 | 319 | #ifdef HAL_I2C_MODULE_ENABLED 320 | #include "stm32f4xx_hal_i2c.h" 321 | #endif /* HAL_I2C_MODULE_ENABLED */ 322 | 323 | #ifdef HAL_I2S_MODULE_ENABLED 324 | #include "stm32f4xx_hal_i2s.h" 325 | #endif /* HAL_I2S_MODULE_ENABLED */ 326 | 327 | #ifdef HAL_IWDG_MODULE_ENABLED 328 | #include "stm32f4xx_hal_iwdg.h" 329 | #endif /* HAL_IWDG_MODULE_ENABLED */ 330 | 331 | #ifdef HAL_LTDC_MODULE_ENABLED 332 | #include "stm32f4xx_hal_ltdc.h" 333 | #endif /* HAL_LTDC_MODULE_ENABLED */ 334 | 335 | #ifdef HAL_PWR_MODULE_ENABLED 336 | #include "stm32f4xx_hal_pwr.h" 337 | #endif /* HAL_PWR_MODULE_ENABLED */ 338 | 339 | #ifdef HAL_RNG_MODULE_ENABLED 340 | #include "stm32f4xx_hal_rng.h" 341 | #endif /* HAL_RNG_MODULE_ENABLED */ 342 | 343 | #ifdef HAL_RTC_MODULE_ENABLED 344 | #include "stm32f4xx_hal_rtc.h" 345 | #endif /* HAL_RTC_MODULE_ENABLED */ 346 | 347 | #ifdef HAL_SAI_MODULE_ENABLED 348 | #include "stm32f4xx_hal_sai.h" 349 | #endif /* HAL_SAI_MODULE_ENABLED */ 350 | 351 | #ifdef HAL_SD_MODULE_ENABLED 352 | #include "stm32f4xx_hal_sd.h" 353 | #endif /* HAL_SD_MODULE_ENABLED */ 354 | 355 | #ifdef HAL_MMC_MODULE_ENABLED 356 | #include "stm32f4xx_hal_mmc.h" 357 | #endif /* HAL_MMC_MODULE_ENABLED */ 358 | 359 | #ifdef HAL_SPI_MODULE_ENABLED 360 | #include "stm32f4xx_hal_spi.h" 361 | #endif /* HAL_SPI_MODULE_ENABLED */ 362 | 363 | #ifdef HAL_TIM_MODULE_ENABLED 364 | #include "stm32f4xx_hal_tim.h" 365 | #endif /* HAL_TIM_MODULE_ENABLED */ 366 | 367 | #ifdef HAL_UART_MODULE_ENABLED 368 | #include "stm32f4xx_hal_uart.h" 369 | #endif /* HAL_UART_MODULE_ENABLED */ 370 | 371 | #ifdef HAL_USART_MODULE_ENABLED 372 | #include "stm32f4xx_hal_usart.h" 373 | #endif /* HAL_USART_MODULE_ENABLED */ 374 | 375 | #ifdef HAL_IRDA_MODULE_ENABLED 376 | #include "stm32f4xx_hal_irda.h" 377 | #endif /* HAL_IRDA_MODULE_ENABLED */ 378 | 379 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 380 | #include "stm32f4xx_hal_smartcard.h" 381 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 382 | 383 | #ifdef HAL_WWDG_MODULE_ENABLED 384 | #include "stm32f4xx_hal_wwdg.h" 385 | #endif /* HAL_WWDG_MODULE_ENABLED */ 386 | 387 | #ifdef HAL_PCD_MODULE_ENABLED 388 | #include "stm32f4xx_hal_pcd.h" 389 | #endif /* HAL_PCD_MODULE_ENABLED */ 390 | 391 | #ifdef HAL_HCD_MODULE_ENABLED 392 | #include "stm32f4xx_hal_hcd.h" 393 | #endif /* HAL_HCD_MODULE_ENABLED */ 394 | 395 | #ifdef HAL_DSI_MODULE_ENABLED 396 | #include "stm32f4xx_hal_dsi.h" 397 | #endif /* HAL_DSI_MODULE_ENABLED */ 398 | 399 | #ifdef HAL_QSPI_MODULE_ENABLED 400 | #include "stm32f4xx_hal_qspi.h" 401 | #endif /* HAL_QSPI_MODULE_ENABLED */ 402 | 403 | #ifdef HAL_CEC_MODULE_ENABLED 404 | #include "stm32f4xx_hal_cec.h" 405 | #endif /* HAL_CEC_MODULE_ENABLED */ 406 | 407 | #ifdef HAL_FMPI2C_MODULE_ENABLED 408 | #include "stm32f4xx_hal_fmpi2c.h" 409 | #endif /* HAL_FMPI2C_MODULE_ENABLED */ 410 | 411 | #ifdef HAL_SPDIFRX_MODULE_ENABLED 412 | #include "stm32f4xx_hal_spdifrx.h" 413 | #endif /* HAL_SPDIFRX_MODULE_ENABLED */ 414 | 415 | #ifdef HAL_DFSDM_MODULE_ENABLED 416 | #include "stm32f4xx_hal_dfsdm.h" 417 | #endif /* HAL_DFSDM_MODULE_ENABLED */ 418 | 419 | #ifdef HAL_LPTIM_MODULE_ENABLED 420 | #include "stm32f4xx_hal_lptim.h" 421 | #endif /* HAL_LPTIM_MODULE_ENABLED */ 422 | 423 | /* Exported macro ------------------------------------------------------------*/ 424 | #ifdef USE_FULL_ASSERT 425 | /** 426 | * @brief The assert_param macro is used for function's parameters check. 427 | * @param expr: If expr is false, it calls assert_failed function 428 | * which reports the name of the source file and the source 429 | * line number of the call that failed. 430 | * If expr is true, it returns no value. 431 | * @retval None 432 | */ 433 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 434 | /* Exported functions ------------------------------------------------------- */ 435 | void assert_failed(uint8_t* file, uint32_t line); 436 | #else 437 | #define assert_param(expr) ((void)0U) 438 | #endif /* USE_FULL_ASSERT */ 439 | 440 | #ifdef __cplusplus 441 | } 442 | #endif 443 | 444 | #endif /* __STM32F4xx_HAL_CONF_H */ 445 | 446 | 447 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 448 | -------------------------------------------------------------------------------- /Inc/stm32f4xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_it.h 4 | * @brief This file contains the headers of the interrupt handlers. 5 | ****************************************************************************** 6 | * 7 | * COPYRIGHT(c) 2018 STMicroelectronics 8 | * 9 | * Redistribution and use in source and binary forms, with or without modification, 10 | * are permitted provided that the following conditions are met: 11 | * 1. Redistributions of source code must retain the above copyright notice, 12 | * this list of conditions and the following disclaimer. 13 | * 2. Redistributions in binary form must reproduce the above copyright notice, 14 | * this list of conditions and the following disclaimer in the documentation 15 | * and/or other materials provided with the distribution. 16 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 17 | * may be used to endorse or promote products derived from this software 18 | * without specific prior written permission. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ****************************************************************************** 32 | */ 33 | 34 | /* Define to prevent recursive inclusion -------------------------------------*/ 35 | #ifndef __STM32F4xx_IT_H 36 | #define __STM32F4xx_IT_H 37 | 38 | #ifdef __cplusplus 39 | extern "C" { 40 | #endif 41 | 42 | /* Includes ------------------------------------------------------------------*/ 43 | #include "stm32f4xx_hal.h" 44 | #include "main.h" 45 | /* Exported types ------------------------------------------------------------*/ 46 | /* Exported constants --------------------------------------------------------*/ 47 | /* Exported macro ------------------------------------------------------------*/ 48 | /* Exported functions ------------------------------------------------------- */ 49 | 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* __STM32F4xx_IT_H */ 65 | 66 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 67 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Aleksander Alekseev 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Lib/r820t2.c: -------------------------------------------------------------------------------- 1 | /* vim: set ai et ts=4 sw=4: */ 2 | /* 3 | * R820T2 downconverter driver by Eric Brombaugh, 2017 4 | * Ported to HAL and refactored by Aleksander Alekseev, 2018 5 | */ 6 | 7 | #include "r820t2.h" 8 | 9 | #define R820T2_I2C_ADDRESS ((0x1A)<<1) 10 | 11 | /* 12 | * Freq calcs 13 | */ 14 | #define XTAL_FREQ 28800000 15 | #define IF_FREQ 5000000 16 | #define CALIBRATION_LO 88000 17 | 18 | #define R820T2_WRITE_START 5 19 | 20 | /* initial values from airspy */ 21 | /* initial freq @ 128MHz -> ~5MHz IF due to xtal mismatch */ 22 | static const uint8_t regs_init_array[R820T2_NUM_REGS] = { 23 | 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 to 04 */ 24 | /* 05 */ 0x90, // LNA manual gain mode, init to 0 25 | /* 06 */ 0x80, 26 | /* 07 */ 0x60, 27 | /* 08 */ 0x80, // Image Gain Adjustment 28 | /* 09 */ 0x40, // Image Phase Adjustment 29 | /* 0A */ 0xA8, // Channel filter [0..3]: 0 = widest, f = narrowest - Optimal. Don't touch! 30 | /* 0B */ 0x0F, // High pass filter - Optimal. Don't touch! 31 | /* 0C */ 0x40, // VGA control by code, init at 0 32 | /* 0D */ 0x63, // LNA AGC settings: [0..3]: Lower threshold; [4..7]: High threshold 33 | /* 0E */ 0x75, 34 | /* 0F */ 0xF8, // Filter Widest, LDO_5V OFF, clk out OFF, 35 | /* 10 */ 0x7C, 36 | /* 11 */ 0x83, 37 | /* 12 */ 0x80, 38 | /* 13 */ 0x00, 39 | /* 14 */ 0x0F, 40 | /* 15 */ 0x00, 41 | /* 16 */ 0xC0, 42 | /* 17 */ 0x30, 43 | /* 18 */ 0x48, 44 | /* 19 */ 0xCC, 45 | /* 1A */ 0x60, 46 | /* 1B */ 0x00, 47 | /* 1C */ 0x54, 48 | /* 1D */ 0xAE, 49 | /* 1E */ 0x0A, 50 | /* 1F */ 0xC0 51 | }; 52 | 53 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 54 | 55 | /* 56 | * Tuner frequency ranges 57 | * Kanged & modified from airspy firmware to include freq for scanning table 58 | * "Copyright (C) 2013 Mauro Carvalho Chehab" 59 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 60 | */ 61 | struct r820t2_freq_range { 62 | uint16_t freq; 63 | uint8_t open_d; 64 | uint8_t rf_mux_ploy; 65 | uint8_t tf_c; 66 | }; 67 | 68 | const struct r820t2_freq_range freq_ranges[] = { 69 | { 70 | /* 0 MHz */ 0, 71 | /* .open_d = */ 0x08, /* low */ 72 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 73 | /* .tf_c = */ 0xDF, /* R27[7:0] band2,band0 */ 74 | }, { 75 | /* 50 MHz */ 50, 76 | /* .open_d = */ 0x08, /* low */ 77 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 78 | /* .tf_c = */ 0xBE, /* R27[7:0] band4,band1 */ 79 | }, { 80 | /* 55 MHz */ 55, 81 | /* .open_d = */ 0x08, /* low */ 82 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 83 | /* .tf_c = */ 0x8B, /* R27[7:0] band7,band4 */ 84 | }, { 85 | /* 60 MHz */ 60, 86 | /* .open_d = */ 0x08, /* low */ 87 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 88 | /* .tf_c = */ 0x7B, /* R27[7:0] band8,band4 */ 89 | }, { 90 | /* 65 MHz */ 65, 91 | /* .open_d = */ 0x08, /* low */ 92 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 93 | /* .tf_c = */ 0x69, /* R27[7:0] band9,band6 */ 94 | }, { 95 | /* 70 MHz */ 70, 96 | /* .open_d = */ 0x08, /* low */ 97 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 98 | /* .tf_c = */ 0x58, /* R27[7:0] band10,band7 */ 99 | }, { 100 | /* 75 MHz */ 75, 101 | /* .open_d = */ 0x00, /* high */ 102 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 103 | /* .tf_c = */ 0x44, /* R27[7:0] band11,band11 */ 104 | }, { 105 | /* 80 MHz */ 80, 106 | /* .open_d = */ 0x00, /* high */ 107 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 108 | /* .tf_c = */ 0x44, /* R27[7:0] band11,band11 */ 109 | }, { 110 | /* 90 MHz */ 90, 111 | /* .open_d = */ 0x00, /* high */ 112 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 113 | /* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */ 114 | }, { 115 | /* 100 MHz */ 100, 116 | /* .open_d = */ 0x00, /* high */ 117 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 118 | /* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */ 119 | }, { 120 | /* 110 MHz */ 110, 121 | /* .open_d = */ 0x00, /* high */ 122 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 123 | /* .tf_c = */ 0x24, /* R27[7:0] band13,band11 */ 124 | }, { 125 | /* 120 MHz */ 120, 126 | /* .open_d = */ 0x00, /* high */ 127 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 128 | /* .tf_c = */ 0x24, /* R27[7:0] band13,band11 */ 129 | }, { 130 | /* 140 MHz */ 140, 131 | /* .open_d = */ 0x00, /* high */ 132 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 133 | /* .tf_c = */ 0x14, /* R27[7:0] band14,band11 */ 134 | }, { 135 | /* 180 MHz */ 180, 136 | /* .open_d = */ 0x00, /* high */ 137 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 138 | /* .tf_c = */ 0x13, /* R27[7:0] band14,band12 */ 139 | }, { 140 | /* 220 MHz */ 220, 141 | /* .open_d = */ 0x00, /* high */ 142 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 143 | /* .tf_c = */ 0x13, /* R27[7:0] band14,band12 */ 144 | }, { 145 | /* 250 MHz */ 250, 146 | /* .open_d = */ 0x00, /* high */ 147 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 148 | /* .tf_c = */ 0x11, /* R27[7:0] highest,highest */ 149 | }, { 150 | /* 280 MHz */ 280, 151 | /* .open_d = */ 0x00, /* high */ 152 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 153 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 154 | }, { 155 | /* 310 MHz */ 310, 156 | /* .open_d = */ 0x00, /* high */ 157 | /* .rf_mux_ploy = */ 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 158 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 159 | }, { 160 | /* 450 MHz */ 450, 161 | /* .open_d = */ 0x00, /* high */ 162 | /* .rf_mux_ploy = */ 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 163 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 164 | }, { 165 | /* 588 MHz */ 588, 166 | /* .open_d = */ 0x00, /* high */ 167 | /* .rf_mux_ploy = */ 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 168 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 169 | }, { 170 | /* 650 MHz */ 650, 171 | /* .open_d = */ 0x00, /* high */ 172 | /* .rf_mux_ploy = */ 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 173 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 174 | } 175 | }; 176 | 177 | // Cached register values are used in R820T2_write_cache_mask 178 | uint8_t regs_cache[R820T2_NUM_REGS]; 179 | 180 | // Note: apparently R820T2 allows to read only from address 0x00 181 | void R820T2_read(uint8_t addr, uint8_t *data, uint8_t num) { 182 | static const uint8_t reverse_table[] = { 183 | 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 184 | 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF 185 | }; 186 | 187 | HAL_I2C_Mem_Read(&R820T2_I2C_PORT, R820T2_I2C_ADDRESS, addr, I2C_MEMADD_SIZE_8BIT, 188 | data, num, HAL_MAX_DELAY); 189 | 190 | // During reading bits are transfered in reverse order, 191 | // thus we have to restore original bit order. 192 | for(uint16_t i = 0; i < num; i++) { 193 | uint8_t val = data[i]; 194 | data[i] = (reverse_table[val & 0xF] << 4) | reverse_table[val >> 4]; 195 | } 196 | } 197 | 198 | void R820T2_write(uint8_t addr, uint8_t *data, uint8_t num) { 199 | HAL_I2C_Mem_Write(&R820T2_I2C_PORT, R820T2_I2C_ADDRESS, addr, I2C_MEMADD_SIZE_8BIT, 200 | data, num, HAL_MAX_DELAY); 201 | } 202 | 203 | uint8_t R820T2_read_reg(uint8_t n) { 204 | if(n >= R820T2_NUM_REGS) 205 | return 0; 206 | 207 | uint8_t regs[R820T2_NUM_REGS]; 208 | R820T2_read(0x00, regs, sizeof(regs)); 209 | return regs[n]; 210 | } 211 | 212 | void R820T2_write_reg(uint8_t n, uint8_t data) { 213 | if(n >= R820T2_NUM_REGS) 214 | return; 215 | regs_cache[n] = data; 216 | R820T2_write(n, ®s_cache[n], 1); 217 | } 218 | 219 | /* 220 | * Write single R820T2 reg via I2C with mask vs cached 221 | */ 222 | void R820T2_write_cache_mask(uint8_t reg, uint8_t data, uint8_t mask) { 223 | /* check for legal reg */ 224 | if(reg>=R820T2_NUM_REGS) 225 | return; 226 | 227 | /* mask vs cached reg */ 228 | data = (data & mask) | (regs_cache[reg] & ~mask); 229 | regs_cache[reg] = data; 230 | 231 | /* send via I2C */ 232 | R820T2_write(reg, ®s_cache[reg], 1); 233 | } 234 | 235 | /* 236 | * Update Tracking Filter 237 | * Kanged & Modified from airspy firmware 238 | * 239 | * "inspired by Mauro Carvalho Chehab set_mux technique" 240 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 241 | * part of r820t_set_mux() (set tracking filter) 242 | */ 243 | static void R820T2_set_tf(uint32_t freq) { 244 | const struct r820t2_freq_range *range; 245 | unsigned int i; 246 | 247 | /* Get Freq in MHz */ 248 | freq = (uint32_t)((uint64_t)freq * 4295 >> 32); // fast approach 249 | 250 | /* Scan array for proper range */ 251 | for(i = 0; i < ARRAY_SIZE(freq_ranges)-1; i++) { 252 | if(freq < freq_ranges[i + 1].freq) 253 | break; 254 | } 255 | range = &freq_ranges[i]; 256 | 257 | /* Open Drain */ 258 | R820T2_write_cache_mask(0x17, range->open_d, 0x08); 259 | 260 | /* RF_MUX,Polymux */ 261 | R820T2_write_cache_mask(0x1A, range->rf_mux_ploy, 0xC3); 262 | 263 | /* TF BAND */ 264 | R820T2_write_reg(0x1B, range->tf_c); 265 | 266 | /* XTAL CAP & Drive */ 267 | R820T2_write_cache_mask(0x10, 0x08, 0x0b); 268 | 269 | R820T2_write_cache_mask(0x08, 0x00, 0x3F); 270 | 271 | R820T2_write_cache_mask(0x09, 0x00, 0x3F); 272 | } 273 | 274 | /* 275 | * Update LO PLL 276 | */ 277 | void R820T2_set_pll(uint32_t freq) { 278 | const uint32_t vco_min = 1770000000; 279 | const uint32_t vco_max = 3900000000; 280 | uint32_t pll_ref = (XTAL_FREQ >> 1); 281 | uint32_t pll_ref_2x = XTAL_FREQ; 282 | 283 | uint32_t vco_exact; 284 | uint32_t vco_frac; 285 | uint32_t con_frac; 286 | uint32_t div_num; 287 | uint32_t n_sdm; 288 | uint16_t sdm; 289 | uint8_t ni; 290 | uint8_t si; 291 | uint8_t nint; 292 | 293 | /* Calculate VCO output divider */ 294 | for(div_num = 0; div_num < 5; div_num++) { 295 | vco_exact = freq << (div_num + 1); 296 | if(vco_exact >= vco_min && vco_exact <= vco_max) { 297 | break; 298 | } 299 | } 300 | 301 | /* Calculate the integer PLL feedback divider */ 302 | vco_exact = freq << (div_num + 1); 303 | nint = (uint8_t) ((vco_exact + (pll_ref >> 16)) / pll_ref_2x); 304 | vco_frac = vco_exact - pll_ref_2x * nint; 305 | 306 | nint -= 13; 307 | ni = (nint >> 2); 308 | si = nint - (ni << 2); 309 | 310 | /* Set the vco output divider */ 311 | R820T2_write_cache_mask(0x10, (uint8_t) (div_num << 5), 0xE0); 312 | 313 | /* Set the PLL Feedback integer divider */ 314 | R820T2_write_reg(0x14, (uint8_t) (ni + (si << 6))); 315 | 316 | /* Update Fractional PLL */ 317 | if(vco_frac == 0) { 318 | /* Disable frac pll */ 319 | R820T2_write_cache_mask(0x12, 0x08, 0x08); 320 | } else { 321 | /* Compute the Sigma-Delta Modulator */ 322 | vco_frac += pll_ref >> 16; 323 | sdm = 0; 324 | for(n_sdm = 0; n_sdm < 16; n_sdm++) { 325 | con_frac = pll_ref >> n_sdm; 326 | if (vco_frac >= con_frac) { 327 | sdm |= (uint16_t) (0x8000 >> n_sdm); 328 | vco_frac -= con_frac; 329 | if (vco_frac == 0) 330 | break; 331 | } 332 | } 333 | 334 | /* Update Sigma-Delta Modulator */ 335 | R820T2_write_reg(0x15, (uint8_t)(sdm & 0xFF)); 336 | R820T2_write_reg(0x16, (uint8_t)(sdm >> 8)); 337 | 338 | /* Enable frac pll */ 339 | R820T2_write_cache_mask(0x12, 0x00, 0x08); 340 | } 341 | } 342 | 343 | /* 344 | * Update Tracking Filter and LO to frequency 345 | */ 346 | void R820T2_set_frequency(uint32_t freq) { 347 | R820T2_set_tf(freq); 348 | R820T2_set_pll(freq + IF_FREQ); 349 | } 350 | 351 | /* 352 | * Set IF Bandwidth [0-15] 353 | */ 354 | void R820T2_set_bandwidth(uint8_t bw) { 355 | const uint8_t modes[] = { 0xE0, 0x80, 0x60, 0x00 }; 356 | uint8_t a = 0xB0 | (0x0F-(bw & 0x0F)); 357 | uint8_t b = 0x0F | modes[(bw & 0x3) >> 4]; 358 | R820T2_write_reg(0x0A, a); 359 | R820T2_write_reg(0x0B, b); 360 | } 361 | 362 | /* 363 | * Set gain of LNA [0-15] 364 | */ 365 | void R820T2_set_lna_gain(uint8_t gain_index) { 366 | R820T2_write_cache_mask(0x05, gain_index, 0x0F); 367 | } 368 | 369 | /* 370 | * Set gain of mixer [0-15] 371 | */ 372 | void R820T2_set_mixer_gain(uint8_t gain_index) { 373 | R820T2_write_cache_mask(0x07, gain_index, 0x0F); 374 | } 375 | 376 | /* 377 | * Set gain of VGA [0-15] 378 | */ 379 | void R820T2_set_vga_gain(uint8_t gain_index) { 380 | R820T2_write_cache_mask(0x0C, gain_index, 0x0F); 381 | } 382 | 383 | /* 384 | * Enable/Disable LNA AGC [0 / 1] 385 | */ 386 | void R820T2_set_lna_agc(uint8_t value) { 387 | value = value != 0 ? 0x00 : 0x10; 388 | R820T2_write_cache_mask(0x05, value, 0x10); 389 | } 390 | 391 | /* 392 | * Enable/Disable Mixer AGC [0 / 1] 393 | */ 394 | void R820T2_set_mixer_agc(uint8_t value) { 395 | value = value != 0 ? 0x10 : 0x00; 396 | R820T2_write_cache_mask(0x07, value, 0x10); 397 | } 398 | 399 | /* 400 | * Calibrate 401 | * Kanged from airspy firmware 402 | * "inspired by Mauro Carvalho Chehab calibration technique" 403 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 404 | */ 405 | int32_t R820T2_calibrate() { 406 | int32_t i, cal_code; 407 | 408 | for(i = 0; i < 5; i++) { 409 | /* Set filt_cap */ 410 | R820T2_write_cache_mask(0x0B, 0x08, 0x60); 411 | 412 | /* set cali clk =on */ 413 | R820T2_write_cache_mask(0x0F, 0x04, 0x04); 414 | 415 | /* X'tal cap 0pF for PLL */ 416 | R820T2_write_cache_mask(0x10, 0x00, 0x03); 417 | 418 | /* freq used for calibration */ 419 | R820T2_set_pll(CALIBRATION_LO * 1000); 420 | 421 | /* Start Trigger */ 422 | R820T2_write_cache_mask(0x0B, 0x10, 0x10); 423 | 424 | HAL_Delay(2); 425 | 426 | /* Stop Trigger */ 427 | R820T2_write_cache_mask(0x0B, 0x00, 0x10); 428 | 429 | /* set cali clk =off */ 430 | R820T2_write_cache_mask(0x0F, 0x00, 0x04); 431 | 432 | /* Check if calibration worked */ 433 | cal_code = R820T2_read_reg(0x04) & 0x0F; 434 | if(cal_code && cal_code != 0x0F) 435 | return 0; 436 | } 437 | 438 | /* cal failed */ 439 | return -1; 440 | } 441 | 442 | /* 443 | * Initialize the R820T2 444 | */ 445 | void R820T2_init() { 446 | for(uint8_t i = R820T2_WRITE_START; i < R820T2_NUM_REGS; i++) { 447 | // R820T2_write_reg is used instead of R820T2_write 448 | // to initialize regs_cache properly 449 | R820T2_write_reg(i, regs_init_array[i]); 450 | } 451 | } 452 | 453 | -------------------------------------------------------------------------------- /Lib/r820t2.h: -------------------------------------------------------------------------------- 1 | /* vim: set ai et ts=4 sw=4: */ 2 | /* 3 | * R820T2 downconverter driver by Eric Brombaugh, 2017 4 | * Ported to HAL and refactored by Aleksander Alekseev, 2018 5 | */ 6 | 7 | #ifndef __r820t2__ 8 | #define __r820t2__ 9 | 10 | #include "stm32f4xx.h" 11 | 12 | #define R820T2_I2C_PORT hi2c1 13 | extern I2C_HandleTypeDef R820T2_I2C_PORT; 14 | 15 | #define R820T2_NUM_REGS 0x20 16 | 17 | void R820T2_read(uint8_t addr, uint8_t *data, uint8_t num); 18 | void R820T2_write(uint8_t addr, uint8_t *data, uint8_t num); 19 | uint8_t R820T2_read_reg(uint8_t n); 20 | void R820T2_write_reg(uint8_t n, uint8_t data); 21 | void R820T2_init(void); 22 | int32_t R820T2_calibrate(void); 23 | void R820T2_set_frequency(uint32_t freq); 24 | void R820T2_set_bandwidth(uint8_t bw); 25 | void R820T2_set_lna_gain(uint8_t gain_index); 26 | void R820T2_set_mixer_gain(uint8_t gain_index); 27 | void R820T2_set_vga_gain(uint8_t gain_index); 28 | void R820T2_set_lna_agc(uint8_t value); 29 | void R820T2_set_mixer_agc(uint8_t value); 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ########################################################################################################################## 2 | # File automatically-generated by tool: [projectgenerator] version: [2.26.0] date: [Thu Jan 04 15:34:05 MSK 2018] 3 | ########################################################################################################################## 4 | 5 | # ------------------------------------------------ 6 | # Generic Makefile (based on gcc) 7 | # 8 | # ChangeLog : 9 | # 2017-02-10 - Several enhancements + project update mode 10 | # 2015-07-22 - first version 11 | # ------------------------------------------------ 12 | 13 | ###################################### 14 | # target 15 | ###################################### 16 | TARGET = main 17 | FIRMWARE = $(HOME)/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0 18 | 19 | 20 | ###################################### 21 | # building variables 22 | ###################################### 23 | # debug build? 24 | DEBUG = 1 25 | # optimization 26 | OPT = -Og -Wall 27 | 28 | 29 | ####################################### 30 | # paths 31 | ####################################### 32 | # source path 33 | SOURCES_DIR = \ 34 | Drivers/STM32F4xx_HAL_Driver \ 35 | Application/User/Src/stm32f4xx_it.c \ 36 | Application/User/Src/main.c \ 37 | Drivers \ 38 | Application \ 39 | Application/User \ 40 | Application/MAKEFILE \ 41 | Drivers/CMSIS \ 42 | Application/User/Src/stm32f4xx_hal_msp.c \ 43 | Application/User/Src 44 | 45 | # firmware library path 46 | PERIFLIB_PATH = 47 | 48 | # Build path 49 | BUILD_DIR = build 50 | 51 | ###################################### 52 | # source 53 | ###################################### 54 | # C sources 55 | C_SOURCES = \ 56 | Src/main.c \ 57 | Src/stm32f4xx_it.c \ 58 | Src/system_stm32f4xx.c \ 59 | Src/stm32f4xx_hal_msp.c \ 60 | Lib/r820t2.c \ 61 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ 62 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ 63 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ 64 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ 65 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ 66 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ 67 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ 68 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ 69 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ 70 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ 71 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ 72 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ 73 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ 74 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ 75 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ 76 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ 77 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ 78 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ 79 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c \ 80 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c \ 81 | $(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c 82 | 83 | # ASM sources 84 | ASM_SOURCES = \ 85 | startup_stm32f405xx.s 86 | 87 | 88 | ###################################### 89 | # firmware library 90 | ###################################### 91 | PERIFLIB_SOURCES = 92 | 93 | 94 | ####################################### 95 | # binaries 96 | ####################################### 97 | BINPATH=/usr/bin 98 | PREFIX=arm-none-eabi- 99 | CC = $(BINPATH)/$(PREFIX)gcc 100 | AS = $(BINPATH)/$(PREFIX)gcc -x assembler-with-cpp 101 | CP = $(BINPATH)/$(PREFIX)objcopy 102 | AR = $(BINPATH)/$(PREFIX)ar 103 | SZ = $(BINPATH)/$(PREFIX)size 104 | HEX = $(CP) -O ihex 105 | BIN = $(CP) -O binary -S 106 | 107 | ####################################### 108 | # CFLAGS 109 | ####################################### 110 | # cpu 111 | CPU = -mcpu=cortex-m4 112 | 113 | # fpu 114 | FPU = -mfpu=fpv4-sp-d16 115 | 116 | # float-abi 117 | FLOAT-ABI = -mfloat-abi=hard 118 | 119 | # mcu 120 | MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) 121 | 122 | # macros for gcc 123 | # AS defines 124 | AS_DEFS = 125 | 126 | # C defines 127 | C_DEFS = \ 128 | -DUSE_HAL_DRIVER \ 129 | -DSTM32F405xx 130 | 131 | 132 | # AS includes 133 | AS_INCLUDES = 134 | 135 | # C includes 136 | C_INCLUDES = \ 137 | -IInc \ 138 | -ILib \ 139 | -I$(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Inc \ 140 | -I$(FIRMWARE)/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy \ 141 | -I$(FIRMWARE)/Drivers/CMSIS/Device/ST/STM32F4xx/Include \ 142 | -I$(FIRMWARE)/Drivers/CMSIS/Include 143 | 144 | 145 | # compile gcc flags 146 | ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 147 | 148 | CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections 149 | 150 | ifeq ($(DEBUG), 1) 151 | CFLAGS += -g -gdwarf-2 152 | endif 153 | 154 | 155 | # Generate dependency information 156 | CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" 157 | 158 | 159 | ####################################### 160 | # LDFLAGS 161 | ####################################### 162 | # link script 163 | LDSCRIPT = STM32F405RGTx_FLASH.ld 164 | 165 | # libraries 166 | LIBS = -lc -lm -lnosys 167 | LIBDIR = 168 | LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections 169 | 170 | # default action: build all 171 | all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin 172 | 173 | 174 | ####################################### 175 | # build the application 176 | ####################################### 177 | # list of objects 178 | OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) 179 | vpath %.c $(sort $(dir $(C_SOURCES))) 180 | # list of ASM program objects 181 | OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) 182 | vpath %.s $(sort $(dir $(ASM_SOURCES))) 183 | 184 | $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 185 | $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ 186 | 187 | $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) 188 | $(AS) -c $(CFLAGS) $< -o $@ 189 | 190 | $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile 191 | $(CC) $(OBJECTS) $(LDFLAGS) -o $@ 192 | $(SZ) $@ 193 | 194 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 195 | $(HEX) $< $@ 196 | 197 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) 198 | $(BIN) $< $@ 199 | 200 | $(BUILD_DIR): 201 | mkdir $@ 202 | 203 | ####################################### 204 | # clean up 205 | ####################################### 206 | clean: 207 | -rm -fR .dep $(BUILD_DIR) 208 | 209 | flash: all 210 | st-flash --reset write build/$(TARGET).bin 0x8000000 211 | 212 | erase: 213 | st-flash --reset erase 214 | 215 | uart: 216 | screen /dev/ttyACM0 217 | 218 | ####################################### 219 | # dependencies 220 | ####################################### 221 | -include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) 222 | 223 | # *** EOF *** 224 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # stm32-r820t2 2 | 3 | STM32: example of usage of R820T2 tuner. 4 | 5 | Based on IceRadio project by Eric Brombaugh ([@emeb][u1]). The code was ported to HAL 6 | and refactored a little bit. 7 | 8 | See also: 9 | 10 | * https://github.com/emeb/iceRadio 11 | * https://github.com/emeb/r820t2/ 12 | * http://ebrombaugh.studionebula.com/radio/iceRadio/index.html 13 | 14 | [u1]: https://github.com/emeb 15 | -------------------------------------------------------------------------------- /STM32F405RGTx_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ***************************************************************************** 3 | ** 4 | 5 | ** File : LinkerScript.ld 6 | ** 7 | ** Abstract : Linker script for STM32F405RGTx Device with 8 | ** 1024KByte FLASH, 128KByte RAM 9 | ** 10 | ** Set heap size, stack size and stack location according 11 | ** to application requirements. 12 | ** 13 | ** Set memory bank area and size if external memory is used. 14 | ** 15 | ** Target : STMicroelectronics STM32 16 | ** 17 | ** 18 | ** Distribution: The file is distributed as is, without any warranty 19 | ** of any kind. 20 | ** 21 | ** (c)Copyright Ac6. 22 | ** You may use this file as-is or modify it according to the needs of your 23 | ** project. Distribution of this file (unmodified or modified) is not 24 | ** permitted. Ac6 permit registered System Workbench for MCU users the 25 | ** rights to distribute the assembled, compiled & linked contents of this 26 | ** file as part of an application binary file, provided that it is built 27 | ** using the System Workbench for MCU toolchain. 28 | ** 29 | ***************************************************************************** 30 | */ 31 | 32 | /* Entry Point */ 33 | ENTRY(Reset_Handler) 34 | 35 | /* Highest address of the user mode stack */ 36 | _estack = 0x20020000; /* end of RAM */ 37 | /* Generate a link error if heap and stack don't fit into RAM */ 38 | _Min_Heap_Size = 0x200; /* required amount of heap */ 39 | _Min_Stack_Size = 0x400; /* required amount of stack */ 40 | 41 | /* Specify the memory areas */ 42 | MEMORY 43 | { 44 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K 45 | CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K 46 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K 47 | } 48 | 49 | /* Define output sections */ 50 | SECTIONS 51 | { 52 | /* The startup code goes first into FLASH */ 53 | .isr_vector : 54 | { 55 | . = ALIGN(4); 56 | KEEP(*(.isr_vector)) /* Startup code */ 57 | . = ALIGN(4); 58 | } >FLASH 59 | 60 | /* The program code and other data goes into FLASH */ 61 | .text : 62 | { 63 | . = ALIGN(4); 64 | *(.text) /* .text sections (code) */ 65 | *(.text*) /* .text* sections (code) */ 66 | *(.glue_7) /* glue arm to thumb code */ 67 | *(.glue_7t) /* glue thumb to arm code */ 68 | *(.eh_frame) 69 | 70 | KEEP (*(.init)) 71 | KEEP (*(.fini)) 72 | 73 | . = ALIGN(4); 74 | _etext = .; /* define a global symbols at end of code */ 75 | } >FLASH 76 | 77 | /* Constant data goes into FLASH */ 78 | .rodata : 79 | { 80 | . = ALIGN(4); 81 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 82 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 83 | . = ALIGN(4); 84 | } >FLASH 85 | 86 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH 87 | .ARM : { 88 | __exidx_start = .; 89 | *(.ARM.exidx*) 90 | __exidx_end = .; 91 | } >FLASH 92 | 93 | .preinit_array : 94 | { 95 | PROVIDE_HIDDEN (__preinit_array_start = .); 96 | KEEP (*(.preinit_array*)) 97 | PROVIDE_HIDDEN (__preinit_array_end = .); 98 | } >FLASH 99 | .init_array : 100 | { 101 | PROVIDE_HIDDEN (__init_array_start = .); 102 | KEEP (*(SORT(.init_array.*))) 103 | KEEP (*(.init_array*)) 104 | PROVIDE_HIDDEN (__init_array_end = .); 105 | } >FLASH 106 | .fini_array : 107 | { 108 | PROVIDE_HIDDEN (__fini_array_start = .); 109 | KEEP (*(SORT(.fini_array.*))) 110 | KEEP (*(.fini_array*)) 111 | PROVIDE_HIDDEN (__fini_array_end = .); 112 | } >FLASH 113 | 114 | /* used by the startup to initialize data */ 115 | _sidata = LOADADDR(.data); 116 | 117 | /* Initialized data sections goes into RAM, load LMA copy after code */ 118 | .data : 119 | { 120 | . = ALIGN(4); 121 | _sdata = .; /* create a global symbol at data start */ 122 | *(.data) /* .data sections */ 123 | *(.data*) /* .data* sections */ 124 | 125 | . = ALIGN(4); 126 | _edata = .; /* define a global symbol at data end */ 127 | } >RAM AT> FLASH 128 | 129 | _siccmram = LOADADDR(.ccmram); 130 | 131 | /* CCM-RAM section 132 | * 133 | * IMPORTANT NOTE! 134 | * If initialized variables will be placed in this section, 135 | * the startup code needs to be modified to copy the init-values. 136 | */ 137 | .ccmram : 138 | { 139 | . = ALIGN(4); 140 | _sccmram = .; /* create a global symbol at ccmram start */ 141 | *(.ccmram) 142 | *(.ccmram*) 143 | 144 | . = ALIGN(4); 145 | _eccmram = .; /* create a global symbol at ccmram end */ 146 | } >CCMRAM AT> FLASH 147 | 148 | 149 | /* Uninitialized data section */ 150 | . = ALIGN(4); 151 | .bss : 152 | { 153 | /* This is used by the startup in order to initialize the .bss secion */ 154 | _sbss = .; /* define a global symbol at bss start */ 155 | __bss_start__ = _sbss; 156 | *(.bss) 157 | *(.bss*) 158 | *(COMMON) 159 | 160 | . = ALIGN(4); 161 | _ebss = .; /* define a global symbol at bss end */ 162 | __bss_end__ = _ebss; 163 | } >RAM 164 | 165 | /* User_heap_stack section, used to check that there is enough RAM left */ 166 | ._user_heap_stack : 167 | { 168 | . = ALIGN(8); 169 | PROVIDE ( end = . ); 170 | PROVIDE ( _end = . ); 171 | . = . + _Min_Heap_Size; 172 | . = . + _Min_Stack_Size; 173 | . = ALIGN(8); 174 | } >RAM 175 | 176 | 177 | 178 | /* Remove information from the standard libraries */ 179 | /DISCARD/ : 180 | { 181 | libc.a ( * ) 182 | libm.a ( * ) 183 | libgcc.a ( * ) 184 | } 185 | 186 | .ARM.attributes 0 : { *(.ARM.attributes) } 187 | } 188 | 189 | 190 | -------------------------------------------------------------------------------- /Src/gpio.tmp: -------------------------------------------------------------------------------- 1 | 2 | #n/** Configure pins as #n #t#t #t* Analog #n #t#t #t* Input #n #t#t #t* Output#n #t#t #t* EVENT_OUT#n #t#t #t* EXTI 3 | */ 4 | static void MX_GPIO_Init(void) 5 | { 6 | #n 7 | #tGPIO_InitTypeDef GPIO_InitStruct; 8 | #n#t/* GPIO Ports Clock Enable */ 9 | #t__HAL_RCC_GPIOC_CLK_ENABLE(); 10 | #t__HAL_RCC_GPIOH_CLK_ENABLE(); 11 | #t__HAL_RCC_GPIOA_CLK_ENABLE(); 12 | #t__HAL_RCC_GPIOD_CLK_ENABLE(); 13 | #t__HAL_RCC_GPIOB_CLK_ENABLE(); 14 | #n#t/*Configure GPIO pin Output Level */ 15 | #tHAL_GPIO_WritePin(ULED_GPIO_Port, ULED_Pin, GPIO_PIN_RESET); 16 | #n#t/*Configure GPIO pin : ULED_Pin */ 17 | #tGPIO_InitStruct.Pin = ULED_Pin; 18 | #tGPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 19 | #tGPIO_InitStruct.Pull = GPIO_NOPULL; 20 | #tGPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 21 | #tHAL_GPIO_Init(ULED_GPIO_Port, &GPIO_InitStruct); 22 | #n 23 | } 24 | #n 25 | -------------------------------------------------------------------------------- /Src/license.tmp: -------------------------------------------------------------------------------- 1 | ** This notice applies to any and all portions of this file 2 | * that are not between comment pairs USER CODE BEGIN and 3 | * USER CODE END. Other portions of this file, whether 4 | * inserted by the user or by software development tools 5 | * are owned by their respective copyright owners. 6 | * 7 | * COPYRIGHT(c) 2018 STMicroelectronics 8 | * 9 | * Redistribution and use in source and binary forms, with or without modification, 10 | * are permitted provided that the following conditions are met: 11 | * 1. Redistributions of source code must retain the above copyright notice, 12 | * this list of conditions and the following disclaimer. 13 | * 2. Redistributions in binary form must reproduce the above copyright notice, 14 | * this list of conditions and the following disclaimer in the documentation 15 | * and/or other materials provided with the distribution. 16 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 17 | * may be used to endorse or promote products derived from this software 18 | * without specific prior written permission. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | -------------------------------------------------------------------------------- /Src/main.c: -------------------------------------------------------------------------------- 1 | 2 | /* Includes ------------------------------------------------------------------*/ 3 | #include "main.h" 4 | #include "stm32f4xx_hal.h" 5 | 6 | /* USER CODE BEGIN Includes */ 7 | /* vim: set ai et ts=4 sw=4: */ 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include "r820t2.h" 13 | 14 | /* USER CODE END Includes */ 15 | 16 | /* Private variables ---------------------------------------------------------*/ 17 | I2C_HandleTypeDef hi2c1; 18 | 19 | UART_HandleTypeDef huart1; 20 | 21 | /* USER CODE BEGIN PV */ 22 | /* Private variables ---------------------------------------------------------*/ 23 | 24 | /* USER CODE END PV */ 25 | 26 | /* Private function prototypes -----------------------------------------------*/ 27 | void SystemClock_Config(void); 28 | static void MX_GPIO_Init(void); 29 | static void MX_USART1_UART_Init(void); 30 | static void MX_I2C1_Init(void); 31 | 32 | /* USER CODE BEGIN PFP */ 33 | /* Private function prototypes -----------------------------------------------*/ 34 | 35 | /* USER CODE END PFP */ 36 | 37 | /* USER CODE BEGIN 0 */ 38 | 39 | void UART_Printf(const char* fmt, ...) { 40 | char buff[256]; 41 | va_list args; 42 | va_start(args, fmt); 43 | vsnprintf(buff, sizeof(buff), fmt, args); 44 | HAL_UART_Transmit(&huart1, (uint8_t*)buff, strlen(buff), 45 | HAL_MAX_DELAY); 46 | va_end(args); 47 | } 48 | 49 | HAL_StatusTypeDef UART_ReceiveString( 50 | UART_HandleTypeDef *huart, uint8_t *pData, 51 | uint16_t Size, uint32_t Timeout) { 52 | const char newline[] = "\r\n"; 53 | const char delete[] = "\x08 \x08"; 54 | HAL_StatusTypeDef status; 55 | 56 | if(Size == 0) 57 | return HAL_ERROR; 58 | 59 | int i = 0; 60 | for(;;) { 61 | status = HAL_UART_Receive(huart, &pData[i], 1, Timeout); 62 | if(status != HAL_OK) 63 | return status; 64 | 65 | if((pData[i] == '\x08')||(pData[i] == '\x7F')) { // backspace 66 | if(i > 0) { 67 | status = HAL_UART_Transmit(huart, (uint8_t*)delete, 68 | sizeof(delete)-1, Timeout); 69 | if(status != HAL_OK) 70 | return status; 71 | i--; 72 | } 73 | continue; 74 | } 75 | 76 | if((pData[i] == '\r') || (pData[i] == '\n')) { 77 | pData[i] = '\0'; 78 | status = HAL_UART_Transmit(huart, (uint8_t*)newline, 79 | sizeof(newline)-1, Timeout); 80 | if(status != HAL_OK) 81 | return status; 82 | break; 83 | } 84 | 85 | // last character is reserved for '\0' 86 | if(i == (Size-1)) { 87 | continue; // buffer is full, ignore any input 88 | } 89 | 90 | status = HAL_UART_Transmit(huart, &pData[i], 1, Timeout); 91 | if(status != HAL_OK) 92 | return status; 93 | i++; 94 | } 95 | 96 | return HAL_OK; 97 | } 98 | 99 | void init() { 100 | /* do nothing */ 101 | } 102 | 103 | void cmd_help() { 104 | UART_Printf("help - show this message\r\n"); 105 | UART_Printf("scan - perform I2C scan\r\n"); 106 | UART_Printf("dump - read all registers\r\n"); 107 | UART_Printf("read - read given register value\r\n" 108 | " (e.g `read 0A`)\r\n"); 109 | UART_Printf("write - write to register \r\n" 110 | " (e.g. `write 0A E1`)\r\n"); 111 | UART_Printf("init - initialize R820T2\r\n"); 112 | UART_Printf("calibrate - calibrate R820T2\r\n"); 113 | UART_Printf("frequency - set frequency to \r\n" 114 | " (e.g. `frequency 144000000`)\r\n"); 115 | UART_Printf("bandwidth - Set IF bandwidth [0-15]\r\n"); 116 | UART_Printf("lna_gain - Set gain of LNA [0-15]\r\n"); 117 | UART_Printf("vga_gain - Set gain of VGA [0-15]\r\n"); 118 | UART_Printf("mixer_gain - Set gain Mixer [0-15]\r\n"); 119 | UART_Printf("lna_agc - Enable/disable LNA AGC [0-1]\r\n"); 120 | UART_Printf("mixer_agc - Enable/disable Mixer AGC [0-1]\r\n"); 121 | } 122 | 123 | void cmd_scan() { 124 | HAL_StatusTypeDef res; 125 | for(uint16_t i = 0; i < 128; i++) { 126 | res = HAL_I2C_IsDeviceReady(&hi2c1, i << 1, 1, 10); 127 | if(res == HAL_OK) { 128 | UART_Printf("0x%02X ", i); 129 | } else { 130 | UART_Printf("."); 131 | } 132 | } 133 | UART_Printf("\r\n"); 134 | } 135 | 136 | void cmd_dump() { 137 | uint8_t regs[R820T2_NUM_REGS]; 138 | R820T2_read(0x00, regs, sizeof(regs)); 139 | for(uint8_t i = 0; i < R820T2_NUM_REGS; i++) { 140 | UART_Printf("%02X ", regs[i]); 141 | if((i & 0x7) == 0x7) { 142 | UART_Printf(" "); 143 | } 144 | if((i & 0xF) == 0xF) { 145 | UART_Printf("\r\n"); 146 | } 147 | } 148 | } 149 | 150 | void cmd_read(uint8_t reg) { 151 | if(reg >= R820T2_NUM_REGS) { 152 | UART_Printf("Out of bound: 0x00-0x%02X\r\n", R820T2_NUM_REGS); 153 | return; 154 | } 155 | 156 | uint8_t val = R820T2_read_reg(reg); 157 | UART_Printf("%02X\r\n", val); 158 | } 159 | 160 | void cmd_write(uint8_t reg, uint8_t val) { 161 | if(reg >= R820T2_NUM_REGS) { 162 | UART_Printf("Out of bound: 0x00-0x%02X\r\n", R820T2_NUM_REGS); 163 | return; 164 | } 165 | 166 | R820T2_write_reg(reg, val); 167 | } 168 | 169 | void cmd_init() { 170 | R820T2_init(); 171 | } 172 | 173 | void cmd_calibrate() { 174 | int32_t res = R820T2_calibrate(); 175 | if(res != 0) { 176 | UART_Printf("Calibration failed, res = %d\r\n", res); 177 | } 178 | } 179 | 180 | void cmd_frequency(uint32_t val) { 181 | if((val < 24000000) || (val > 1766000000)) { 182 | UART_Printf("Out of bound: 24000000-1766000000\r\n"); 183 | return; 184 | } 185 | R820T2_set_frequency(val); 186 | } 187 | 188 | void cmd_bandwidth(uint32_t val) { 189 | if(val > 15) { 190 | UART_Printf("Out of bound: 0-15\r\n"); 191 | return; 192 | } 193 | 194 | R820T2_set_bandwidth(val); 195 | } 196 | 197 | void cmd_lna_gain(uint32_t val) { 198 | if(val > 15) { 199 | UART_Printf("Out of bound: 0-15\r\n"); 200 | return; 201 | } 202 | 203 | R820T2_set_lna_gain(val); 204 | } 205 | 206 | void cmd_vga_gain(uint32_t val) { 207 | if(val > 15) { 208 | UART_Printf("Out of bound: 0-15\r\n"); 209 | return; 210 | } 211 | 212 | R820T2_set_vga_gain(val); 213 | } 214 | 215 | void cmd_mixer_gain(uint32_t val) { 216 | if(val > 15) { 217 | UART_Printf("Out of bound: 0-15\r\n"); 218 | return; 219 | } 220 | 221 | R820T2_set_mixer_gain(val); 222 | } 223 | 224 | void cmd_lna_agc(uint32_t val) { 225 | if(val > 1) { 226 | UART_Printf("Out of bound: 0-15\r\n"); 227 | return; 228 | } 229 | 230 | R820T2_set_lna_agc(val); 231 | } 232 | 233 | void cmd_mixer_agc(uint32_t val) { 234 | if(val > 1) { 235 | UART_Printf("Out of bound: 0-1\r\n"); 236 | return; 237 | } 238 | 239 | R820T2_set_mixer_agc(val); 240 | } 241 | 242 | void loop() { 243 | unsigned int uint1, uint2; 244 | char cmd[128]; 245 | UART_Printf("r820t2> "); 246 | UART_ReceiveString(&huart1, (uint8_t*)cmd, sizeof(cmd), HAL_MAX_DELAY); 247 | 248 | if(strcmp(cmd, "") == 0) { 249 | /* empty command - do nothing */ 250 | } else if(strcmp(cmd, "help") == 0) { 251 | cmd_help(); 252 | } else if(strcmp(cmd, "scan") == 0) { 253 | cmd_scan(); 254 | } else if(strcmp(cmd, "init") == 0) { 255 | cmd_init(); 256 | } else if(strcmp(cmd, "calibrate") == 0) { 257 | cmd_calibrate(); 258 | } else if(strcmp(cmd, "dump") == 0) { 259 | cmd_dump(); 260 | } else if(sscanf(cmd, "frequency %u", &uint1) == 1) { 261 | cmd_frequency((uint32_t)uint1); 262 | } else if(sscanf(cmd, "bandwidth %u", &uint1) == 1) { 263 | cmd_bandwidth((uint32_t)uint1); 264 | } else if(sscanf(cmd, "lna_gain %u", &uint1) == 1) { 265 | cmd_lna_gain((uint32_t)uint1); 266 | } else if(sscanf(cmd, "vga_gain %u", &uint1) == 1) { 267 | cmd_vga_gain((uint32_t)uint1); 268 | } else if(sscanf(cmd, "mixer_gain %u", &uint1) == 1) { 269 | cmd_mixer_gain((uint32_t)uint1); 270 | } else if(sscanf(cmd, "lna_agc %u", &uint1) == 1) { 271 | cmd_lna_agc((uint32_t)uint1); 272 | } else if(sscanf(cmd, "mixer_agc %u", &uint1) == 1) { 273 | cmd_mixer_agc((uint32_t)uint1); 274 | } else if(sscanf(cmd, "read %02x", &uint1) == 1) { 275 | cmd_read((uint8_t)uint1); 276 | } else if(sscanf(cmd, "write %02x %02x", &uint1, &uint2) == 2) { 277 | cmd_write((uint8_t)uint1, (uint8_t)uint2); 278 | } else { 279 | UART_Printf("Unknown command, try `help`\r\n"); 280 | } 281 | } 282 | 283 | /* USER CODE END 0 */ 284 | 285 | int main(void) 286 | { 287 | 288 | /* USER CODE BEGIN 1 */ 289 | 290 | /* USER CODE END 1 */ 291 | 292 | /* MCU Configuration----------------------------------------------------------*/ 293 | 294 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 295 | HAL_Init(); 296 | 297 | /* USER CODE BEGIN Init */ 298 | 299 | /* USER CODE END Init */ 300 | 301 | /* Configure the system clock */ 302 | SystemClock_Config(); 303 | 304 | /* USER CODE BEGIN SysInit */ 305 | 306 | /* USER CODE END SysInit */ 307 | 308 | /* Initialize all configured peripherals */ 309 | MX_GPIO_Init(); 310 | MX_USART1_UART_Init(); 311 | MX_I2C1_Init(); 312 | 313 | /* USER CODE BEGIN 2 */ 314 | 315 | /* USER CODE END 2 */ 316 | 317 | /* Infinite loop */ 318 | /* USER CODE BEGIN WHILE */ 319 | init(); 320 | while (1) 321 | { 322 | loop(); 323 | /* USER CODE END WHILE */ 324 | 325 | /* USER CODE BEGIN 3 */ 326 | 327 | } 328 | /* USER CODE END 3 */ 329 | 330 | } 331 | 332 | /** System Clock Configuration 333 | */ 334 | void SystemClock_Config(void) 335 | { 336 | 337 | RCC_OscInitTypeDef RCC_OscInitStruct; 338 | RCC_ClkInitTypeDef RCC_ClkInitStruct; 339 | 340 | /**Configure the main internal regulator output voltage 341 | */ 342 | __HAL_RCC_PWR_CLK_ENABLE(); 343 | 344 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 345 | 346 | /**Initializes the CPU, AHB and APB busses clocks 347 | */ 348 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 349 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; 350 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 351 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 352 | RCC_OscInitStruct.PLL.PLLM = 16; 353 | RCC_OscInitStruct.PLL.PLLN = 168; 354 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 355 | RCC_OscInitStruct.PLL.PLLQ = 4; 356 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 357 | { 358 | _Error_Handler(__FILE__, __LINE__); 359 | } 360 | 361 | /**Initializes the CPU, AHB and APB busses clocks 362 | */ 363 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 364 | |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 365 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 366 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 367 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 368 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 369 | 370 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 371 | { 372 | _Error_Handler(__FILE__, __LINE__); 373 | } 374 | 375 | /**Configure the Systick interrupt time 376 | */ 377 | HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); 378 | 379 | /**Configure the Systick 380 | */ 381 | HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); 382 | 383 | /* SysTick_IRQn interrupt configuration */ 384 | HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); 385 | } 386 | 387 | /* I2C1 init function */ 388 | static void MX_I2C1_Init(void) 389 | { 390 | 391 | hi2c1.Instance = I2C1; 392 | hi2c1.Init.ClockSpeed = 100000; 393 | hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; 394 | hi2c1.Init.OwnAddress1 = 0; 395 | hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 396 | hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 397 | hi2c1.Init.OwnAddress2 = 0; 398 | hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 399 | hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 400 | if (HAL_I2C_Init(&hi2c1) != HAL_OK) 401 | { 402 | _Error_Handler(__FILE__, __LINE__); 403 | } 404 | 405 | } 406 | 407 | /* USART1 init function */ 408 | static void MX_USART1_UART_Init(void) 409 | { 410 | 411 | huart1.Instance = USART1; 412 | huart1.Init.BaudRate = 9600; 413 | huart1.Init.WordLength = UART_WORDLENGTH_8B; 414 | huart1.Init.StopBits = UART_STOPBITS_1; 415 | huart1.Init.Parity = UART_PARITY_NONE; 416 | huart1.Init.Mode = UART_MODE_TX_RX; 417 | huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 418 | huart1.Init.OverSampling = UART_OVERSAMPLING_16; 419 | if (HAL_UART_Init(&huart1) != HAL_OK) 420 | { 421 | _Error_Handler(__FILE__, __LINE__); 422 | } 423 | 424 | } 425 | 426 | /** Configure pins as 427 | * Analog 428 | * Input 429 | * Output 430 | * EVENT_OUT 431 | * EXTI 432 | */ 433 | static void MX_GPIO_Init(void) 434 | { 435 | 436 | GPIO_InitTypeDef GPIO_InitStruct; 437 | 438 | /* GPIO Ports Clock Enable */ 439 | __HAL_RCC_GPIOC_CLK_ENABLE(); 440 | __HAL_RCC_GPIOH_CLK_ENABLE(); 441 | __HAL_RCC_GPIOA_CLK_ENABLE(); 442 | __HAL_RCC_GPIOD_CLK_ENABLE(); 443 | __HAL_RCC_GPIOB_CLK_ENABLE(); 444 | 445 | /*Configure GPIO pin Output Level */ 446 | HAL_GPIO_WritePin(ULED_GPIO_Port, ULED_Pin, GPIO_PIN_RESET); 447 | 448 | /*Configure GPIO pin : ULED_Pin */ 449 | GPIO_InitStruct.Pin = ULED_Pin; 450 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 451 | GPIO_InitStruct.Pull = GPIO_NOPULL; 452 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 453 | HAL_GPIO_Init(ULED_GPIO_Port, &GPIO_InitStruct); 454 | 455 | } 456 | 457 | /* USER CODE BEGIN 4 */ 458 | 459 | /* USER CODE END 4 */ 460 | 461 | /** 462 | * @brief This function is executed in case of error occurrence. 463 | * @param None 464 | * @retval None 465 | */ 466 | void _Error_Handler(char * file, int line) 467 | { 468 | /* USER CODE BEGIN Error_Handler_Debug */ 469 | /* User can add his own implementation to report the HAL error return state */ 470 | while(1) 471 | { 472 | } 473 | /* USER CODE END Error_Handler_Debug */ 474 | } 475 | 476 | #ifdef USE_FULL_ASSERT 477 | 478 | /** 479 | * @brief Reports the name of the source file and the source line number 480 | * where the assert_param error has occurred. 481 | * @param file: pointer to the source file name 482 | * @param line: assert_param error line source number 483 | * @retval None 484 | */ 485 | void assert_failed(uint8_t* file, uint32_t line) 486 | { 487 | /* USER CODE BEGIN 6 */ 488 | /* User can add his own implementation to report the file name and line number, 489 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 490 | /* USER CODE END 6 */ 491 | 492 | } 493 | 494 | #endif 495 | 496 | /** 497 | * @} 498 | */ 499 | 500 | /** 501 | * @} 502 | */ 503 | 504 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 505 | -------------------------------------------------------------------------------- /Src/stm32f4xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * File Name : stm32f4xx_hal_msp.c 4 | * Description : This file provides code for the MSP Initialization 5 | * and de-Initialization codes. 6 | ****************************************************************************** 7 | ** This notice applies to any and all portions of this file 8 | * that are not between comment pairs USER CODE BEGIN and 9 | * USER CODE END. Other portions of this file, whether 10 | * inserted by the user or by software development tools 11 | * are owned by their respective copyright owners. 12 | * 13 | * COPYRIGHT(c) 2018 STMicroelectronics 14 | * 15 | * Redistribution and use in source and binary forms, with or without modification, 16 | * are permitted provided that the following conditions are met: 17 | * 1. Redistributions of source code must retain the above copyright notice, 18 | * this list of conditions and the following disclaimer. 19 | * 2. Redistributions in binary form must reproduce the above copyright notice, 20 | * this list of conditions and the following disclaimer in the documentation 21 | * and/or other materials provided with the distribution. 22 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 23 | * may be used to endorse or promote products derived from this software 24 | * without specific prior written permission. 25 | * 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 30 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 33 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 34 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 | * 37 | ****************************************************************************** 38 | */ 39 | /* Includes ------------------------------------------------------------------*/ 40 | #include "stm32f4xx_hal.h" 41 | 42 | extern void _Error_Handler(char *, int); 43 | /* USER CODE BEGIN 0 */ 44 | 45 | /* USER CODE END 0 */ 46 | /** 47 | * Initializes the Global MSP. 48 | */ 49 | void HAL_MspInit(void) 50 | { 51 | /* USER CODE BEGIN MspInit 0 */ 52 | 53 | /* USER CODE END MspInit 0 */ 54 | 55 | HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 56 | 57 | /* System interrupt init*/ 58 | /* MemoryManagement_IRQn interrupt configuration */ 59 | HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); 60 | /* BusFault_IRQn interrupt configuration */ 61 | HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); 62 | /* UsageFault_IRQn interrupt configuration */ 63 | HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); 64 | /* SVCall_IRQn interrupt configuration */ 65 | HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); 66 | /* DebugMonitor_IRQn interrupt configuration */ 67 | HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); 68 | /* PendSV_IRQn interrupt configuration */ 69 | HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); 70 | /* SysTick_IRQn interrupt configuration */ 71 | HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); 72 | 73 | /* USER CODE BEGIN MspInit 1 */ 74 | 75 | /* USER CODE END MspInit 1 */ 76 | } 77 | 78 | void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) 79 | { 80 | 81 | GPIO_InitTypeDef GPIO_InitStruct; 82 | if(hi2c->Instance==I2C1) 83 | { 84 | /* USER CODE BEGIN I2C1_MspInit 0 */ 85 | 86 | /* USER CODE END I2C1_MspInit 0 */ 87 | 88 | /**I2C1 GPIO Configuration 89 | PB8 ------> I2C1_SCL 90 | PB9 ------> I2C1_SDA 91 | */ 92 | GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 93 | GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 94 | GPIO_InitStruct.Pull = GPIO_PULLUP; 95 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 96 | GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; 97 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 98 | 99 | /* Peripheral clock enable */ 100 | __HAL_RCC_I2C1_CLK_ENABLE(); 101 | /* USER CODE BEGIN I2C1_MspInit 1 */ 102 | 103 | /* USER CODE END I2C1_MspInit 1 */ 104 | } 105 | 106 | } 107 | 108 | void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) 109 | { 110 | 111 | if(hi2c->Instance==I2C1) 112 | { 113 | /* USER CODE BEGIN I2C1_MspDeInit 0 */ 114 | 115 | /* USER CODE END I2C1_MspDeInit 0 */ 116 | /* Peripheral clock disable */ 117 | __HAL_RCC_I2C1_CLK_DISABLE(); 118 | 119 | /**I2C1 GPIO Configuration 120 | PB8 ------> I2C1_SCL 121 | PB9 ------> I2C1_SDA 122 | */ 123 | HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); 124 | 125 | /* USER CODE BEGIN I2C1_MspDeInit 1 */ 126 | 127 | /* USER CODE END I2C1_MspDeInit 1 */ 128 | } 129 | 130 | } 131 | 132 | void HAL_UART_MspInit(UART_HandleTypeDef* huart) 133 | { 134 | 135 | GPIO_InitTypeDef GPIO_InitStruct; 136 | if(huart->Instance==USART1) 137 | { 138 | /* USER CODE BEGIN USART1_MspInit 0 */ 139 | 140 | /* USER CODE END USART1_MspInit 0 */ 141 | /* Peripheral clock enable */ 142 | __HAL_RCC_USART1_CLK_ENABLE(); 143 | 144 | /**USART1 GPIO Configuration 145 | PA9 ------> USART1_TX 146 | PA10 ------> USART1_RX 147 | */ 148 | GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 149 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 150 | GPIO_InitStruct.Pull = GPIO_PULLUP; 151 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 152 | GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 153 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 154 | 155 | /* USER CODE BEGIN USART1_MspInit 1 */ 156 | 157 | /* USER CODE END USART1_MspInit 1 */ 158 | } 159 | 160 | } 161 | 162 | void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) 163 | { 164 | 165 | if(huart->Instance==USART1) 166 | { 167 | /* USER CODE BEGIN USART1_MspDeInit 0 */ 168 | 169 | /* USER CODE END USART1_MspDeInit 0 */ 170 | /* Peripheral clock disable */ 171 | __HAL_RCC_USART1_CLK_DISABLE(); 172 | 173 | /**USART1 GPIO Configuration 174 | PA9 ------> USART1_TX 175 | PA10 ------> USART1_RX 176 | */ 177 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); 178 | 179 | /* USER CODE BEGIN USART1_MspDeInit 1 */ 180 | 181 | /* USER CODE END USART1_MspDeInit 1 */ 182 | } 183 | 184 | } 185 | 186 | /* USER CODE BEGIN 1 */ 187 | 188 | /* USER CODE END 1 */ 189 | 190 | /** 191 | * @} 192 | */ 193 | 194 | /** 195 | * @} 196 | */ 197 | 198 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 199 | -------------------------------------------------------------------------------- /Src/stm32f4xx_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f4xx_it.c 4 | * @brief Interrupt Service Routines. 5 | ****************************************************************************** 6 | * 7 | * COPYRIGHT(c) 2018 STMicroelectronics 8 | * 9 | * Redistribution and use in source and binary forms, with or without modification, 10 | * are permitted provided that the following conditions are met: 11 | * 1. Redistributions of source code must retain the above copyright notice, 12 | * this list of conditions and the following disclaimer. 13 | * 2. Redistributions in binary form must reproduce the above copyright notice, 14 | * this list of conditions and the following disclaimer in the documentation 15 | * and/or other materials provided with the distribution. 16 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 17 | * may be used to endorse or promote products derived from this software 18 | * without specific prior written permission. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ****************************************************************************** 32 | */ 33 | /* Includes ------------------------------------------------------------------*/ 34 | #include "stm32f4xx_hal.h" 35 | #include "stm32f4xx.h" 36 | #include "stm32f4xx_it.h" 37 | 38 | /* USER CODE BEGIN 0 */ 39 | extern void change_column(void); 40 | extern void row_callback(uint8_t row_number); 41 | /* USER CODE END 0 */ 42 | 43 | /* External variables --------------------------------------------------------*/ 44 | 45 | /******************************************************************************/ 46 | /* Cortex-M4 Processor Interruption and Exception Handlers */ 47 | /******************************************************************************/ 48 | 49 | /** 50 | * @brief This function handles Non maskable interrupt. 51 | */ 52 | void NMI_Handler(void) 53 | { 54 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 55 | 56 | /* USER CODE END NonMaskableInt_IRQn 0 */ 57 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 58 | 59 | /* USER CODE END NonMaskableInt_IRQn 1 */ 60 | } 61 | 62 | /** 63 | * @brief This function handles Hard fault interrupt. 64 | */ 65 | void HardFault_Handler(void) 66 | { 67 | /* USER CODE BEGIN HardFault_IRQn 0 */ 68 | 69 | /* USER CODE END HardFault_IRQn 0 */ 70 | while (1) 71 | { 72 | } 73 | /* USER CODE BEGIN HardFault_IRQn 1 */ 74 | 75 | /* USER CODE END HardFault_IRQn 1 */ 76 | } 77 | 78 | /** 79 | * @brief This function handles Memory management fault. 80 | */ 81 | void MemManage_Handler(void) 82 | { 83 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 84 | 85 | /* USER CODE END MemoryManagement_IRQn 0 */ 86 | while (1) 87 | { 88 | } 89 | /* USER CODE BEGIN MemoryManagement_IRQn 1 */ 90 | 91 | /* USER CODE END MemoryManagement_IRQn 1 */ 92 | } 93 | 94 | /** 95 | * @brief This function handles Pre-fetch fault, memory access fault. 96 | */ 97 | void BusFault_Handler(void) 98 | { 99 | /* USER CODE BEGIN BusFault_IRQn 0 */ 100 | 101 | /* USER CODE END BusFault_IRQn 0 */ 102 | while (1) 103 | { 104 | } 105 | /* USER CODE BEGIN BusFault_IRQn 1 */ 106 | 107 | /* USER CODE END BusFault_IRQn 1 */ 108 | } 109 | 110 | /** 111 | * @brief This function handles Undefined instruction or illegal state. 112 | */ 113 | void UsageFault_Handler(void) 114 | { 115 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 116 | 117 | /* USER CODE END UsageFault_IRQn 0 */ 118 | while (1) 119 | { 120 | } 121 | /* USER CODE BEGIN UsageFault_IRQn 1 */ 122 | 123 | /* USER CODE END UsageFault_IRQn 1 */ 124 | } 125 | 126 | /** 127 | * @brief This function handles System service call via SWI instruction. 128 | */ 129 | void SVC_Handler(void) 130 | { 131 | /* USER CODE BEGIN SVCall_IRQn 0 */ 132 | 133 | /* USER CODE END SVCall_IRQn 0 */ 134 | /* USER CODE BEGIN SVCall_IRQn 1 */ 135 | 136 | /* USER CODE END SVCall_IRQn 1 */ 137 | } 138 | 139 | /** 140 | * @brief This function handles Debug monitor. 141 | */ 142 | void DebugMon_Handler(void) 143 | { 144 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 145 | 146 | /* USER CODE END DebugMonitor_IRQn 0 */ 147 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 148 | 149 | /* USER CODE END DebugMonitor_IRQn 1 */ 150 | } 151 | 152 | /** 153 | * @brief This function handles Pendable request for system service. 154 | */ 155 | void PendSV_Handler(void) 156 | { 157 | /* USER CODE BEGIN PendSV_IRQn 0 */ 158 | 159 | /* USER CODE END PendSV_IRQn 0 */ 160 | /* USER CODE BEGIN PendSV_IRQn 1 */ 161 | 162 | /* USER CODE END PendSV_IRQn 1 */ 163 | } 164 | 165 | /** 166 | * @brief This function handles System tick timer. 167 | */ 168 | void SysTick_Handler(void) 169 | { 170 | /* USER CODE BEGIN SysTick_IRQn 0 */ 171 | 172 | /* USER CODE END SysTick_IRQn 0 */ 173 | HAL_IncTick(); 174 | HAL_SYSTICK_IRQHandler(); 175 | /* USER CODE BEGIN SysTick_IRQn 1 */ 176 | 177 | /* USER CODE END SysTick_IRQn 1 */ 178 | } 179 | 180 | /******************************************************************************/ 181 | /* STM32F4xx Peripheral Interrupt Handlers */ 182 | /* Add here the Interrupt Handlers for the used peripherals. */ 183 | /* For the available peripheral interrupt handler names, */ 184 | /* please refer to the startup file (startup_stm32f4xx.s). */ 185 | /******************************************************************************/ 186 | 187 | /* USER CODE BEGIN 1 */ 188 | 189 | /* USER CODE END 1 */ 190 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 191 | -------------------------------------------------------------------------------- /Src/system.tmp: -------------------------------------------------------------------------------- 1 | #n 2 | #n 3 | #tHAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);#n 4 | #t/* System interrupt init*/ 5 | #t/* MemoryManagement_IRQn interrupt configuration */ 6 | #tNVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 7 | #t/* BusFault_IRQn interrupt configuration */ 8 | #tNVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 9 | #t/* UsageFault_IRQn interrupt configuration */ 10 | #tNVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 11 | #t/* SVCall_IRQn interrupt configuration */ 12 | #tNVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 13 | #t/* DebugMonitor_IRQn interrupt configuration */ 14 | #tNVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 15 | #t/* PendSV_IRQn interrupt configuration */ 16 | #tNVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 17 | #t/* SysTick_IRQn interrupt configuration */ 18 | #tNVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); 19 | #n 20 | #n 21 | -------------------------------------------------------------------------------- /Src/system_stm32f4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f4xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | *

© COPYRIGHT 2017 STMicroelectronics

26 | * 27 | * Redistribution and use in source and binary forms, with or without modification, 28 | * are permitted provided that the following conditions are met: 29 | * 1. Redistributions of source code must retain the above copyright notice, 30 | * this list of conditions and the following disclaimer. 31 | * 2. Redistributions in binary form must reproduce the above copyright notice, 32 | * this list of conditions and the following disclaimer in the documentation 33 | * and/or other materials provided with the distribution. 34 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 35 | * may be used to endorse or promote products derived from this software 36 | * without specific prior written permission. 37 | * 38 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | * 49 | ****************************************************************************** 50 | */ 51 | 52 | /** @addtogroup CMSIS 53 | * @{ 54 | */ 55 | 56 | /** @addtogroup stm32f4xx_system 57 | * @{ 58 | */ 59 | 60 | /** @addtogroup STM32F4xx_System_Private_Includes 61 | * @{ 62 | */ 63 | 64 | 65 | #include "stm32f4xx.h" 66 | 67 | #if !defined (HSE_VALUE) 68 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ 69 | #endif /* HSE_VALUE */ 70 | 71 | #if !defined (HSI_VALUE) 72 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 73 | #endif /* HSI_VALUE */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @addtogroup STM32F4xx_System_Private_Defines 88 | * @{ 89 | */ 90 | 91 | /************************* Miscellaneous Configuration ************************/ 92 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 93 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 94 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 95 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 96 | /* #define DATA_IN_ExtSRAM */ 97 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ 98 | STM32F412Zx || STM32F412Vx */ 99 | 100 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 101 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 102 | /* #define DATA_IN_ExtSDRAM */ 103 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ 104 | STM32F479xx */ 105 | 106 | /*!< Uncomment the following line if you need to relocate your vector Table in 107 | Internal SRAM. */ 108 | /* #define VECT_TAB_SRAM */ 109 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 110 | This value must be a multiple of 0x200. */ 111 | /******************************************************************************/ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @addtogroup STM32F4xx_System_Private_Macros 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @addtogroup STM32F4xx_System_Private_Variables 126 | * @{ 127 | */ 128 | /* This variable is updated in three ways: 129 | 1) by calling CMSIS function SystemCoreClockUpdate() 130 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 131 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 132 | Note: If you use this function to configure the system clock; then there 133 | is no need to call the 2 first functions listed above, since SystemCoreClock 134 | variable is updated automatically. 135 | */ 136 | uint32_t SystemCoreClock = 16000000; 137 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 138 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 144 | * @{ 145 | */ 146 | 147 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 148 | static void SystemInit_ExtMemCtl(void); 149 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /** @addtogroup STM32F4xx_System_Private_Functions 156 | * @{ 157 | */ 158 | 159 | /** 160 | * @brief Setup the microcontroller system 161 | * Initialize the FPU setting, vector table location and External memory 162 | * configuration. 163 | * @param None 164 | * @retval None 165 | */ 166 | void SystemInit(void) 167 | { 168 | /* FPU settings ------------------------------------------------------------*/ 169 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 170 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 171 | #endif 172 | /* Reset the RCC clock configuration to the default reset state ------------*/ 173 | /* Set HSION bit */ 174 | RCC->CR |= (uint32_t)0x00000001; 175 | 176 | /* Reset CFGR register */ 177 | RCC->CFGR = 0x00000000; 178 | 179 | /* Reset HSEON, CSSON and PLLON bits */ 180 | RCC->CR &= (uint32_t)0xFEF6FFFF; 181 | 182 | /* Reset PLLCFGR register */ 183 | RCC->PLLCFGR = 0x24003010; 184 | 185 | /* Reset HSEBYP bit */ 186 | RCC->CR &= (uint32_t)0xFFFBFFFF; 187 | 188 | /* Disable all interrupts */ 189 | RCC->CIR = 0x00000000; 190 | 191 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 192 | SystemInit_ExtMemCtl(); 193 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 194 | 195 | /* Configure the Vector Table location add offset address ------------------*/ 196 | #ifdef VECT_TAB_SRAM 197 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 198 | #else 199 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 200 | #endif 201 | } 202 | 203 | /** 204 | * @brief Update SystemCoreClock variable according to Clock Register Values. 205 | * The SystemCoreClock variable contains the core clock (HCLK), it can 206 | * be used by the user application to setup the SysTick timer or configure 207 | * other parameters. 208 | * 209 | * @note Each time the core clock (HCLK) changes, this function must be called 210 | * to update SystemCoreClock variable value. Otherwise, any configuration 211 | * based on this variable will be incorrect. 212 | * 213 | * @note - The system frequency computed by this function is not the real 214 | * frequency in the chip. It is calculated based on the predefined 215 | * constant and the selected clock source: 216 | * 217 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 218 | * 219 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 220 | * 221 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 222 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 223 | * 224 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 225 | * 16 MHz) but the real value may vary depending on the variations 226 | * in voltage and temperature. 227 | * 228 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value 229 | * depends on the application requirements), user has to ensure that HSE_VALUE 230 | * is same as the real frequency of the crystal used. Otherwise, this function 231 | * may have wrong result. 232 | * 233 | * - The result of this function could be not correct when using fractional 234 | * value for HSE crystal. 235 | * 236 | * @param None 237 | * @retval None 238 | */ 239 | void SystemCoreClockUpdate(void) 240 | { 241 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 242 | 243 | /* Get SYSCLK source -------------------------------------------------------*/ 244 | tmp = RCC->CFGR & RCC_CFGR_SWS; 245 | 246 | switch (tmp) 247 | { 248 | case 0x00: /* HSI used as system clock source */ 249 | SystemCoreClock = HSI_VALUE; 250 | break; 251 | case 0x04: /* HSE used as system clock source */ 252 | SystemCoreClock = HSE_VALUE; 253 | break; 254 | case 0x08: /* PLL used as system clock source */ 255 | 256 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 257 | SYSCLK = PLL_VCO / PLL_P 258 | */ 259 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 260 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 261 | 262 | if (pllsource != 0) 263 | { 264 | /* HSE used as PLL clock source */ 265 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 266 | } 267 | else 268 | { 269 | /* HSI used as PLL clock source */ 270 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 271 | } 272 | 273 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 274 | SystemCoreClock = pllvco/pllp; 275 | break; 276 | default: 277 | SystemCoreClock = HSI_VALUE; 278 | break; 279 | } 280 | /* Compute HCLK frequency --------------------------------------------------*/ 281 | /* Get HCLK prescaler */ 282 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 283 | /* HCLK frequency */ 284 | SystemCoreClock >>= tmp; 285 | } 286 | 287 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) 288 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 289 | || defined(STM32F469xx) || defined(STM32F479xx) 290 | /** 291 | * @brief Setup the external memory controller. 292 | * Called in startup_stm32f4xx.s before jump to main. 293 | * This function configures the external memories (SRAM/SDRAM) 294 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 295 | * @param None 296 | * @retval None 297 | */ 298 | void SystemInit_ExtMemCtl(void) 299 | { 300 | __IO uint32_t tmp = 0x00; 301 | 302 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 303 | register __IO uint32_t index; 304 | 305 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ 306 | RCC->AHB1ENR |= 0x000001F8; 307 | 308 | /* Delay after an RCC peripheral clock enabling */ 309 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 310 | 311 | /* Connect PDx pins to FMC Alternate function */ 312 | GPIOD->AFR[0] = 0x00CCC0CC; 313 | GPIOD->AFR[1] = 0xCCCCCCCC; 314 | /* Configure PDx pins in Alternate function mode */ 315 | GPIOD->MODER = 0xAAAA0A8A; 316 | /* Configure PDx pins speed to 100 MHz */ 317 | GPIOD->OSPEEDR = 0xFFFF0FCF; 318 | /* Configure PDx pins Output type to push-pull */ 319 | GPIOD->OTYPER = 0x00000000; 320 | /* No pull-up, pull-down for PDx pins */ 321 | GPIOD->PUPDR = 0x00000000; 322 | 323 | /* Connect PEx pins to FMC Alternate function */ 324 | GPIOE->AFR[0] = 0xC00CC0CC; 325 | GPIOE->AFR[1] = 0xCCCCCCCC; 326 | /* Configure PEx pins in Alternate function mode */ 327 | GPIOE->MODER = 0xAAAA828A; 328 | /* Configure PEx pins speed to 100 MHz */ 329 | GPIOE->OSPEEDR = 0xFFFFC3CF; 330 | /* Configure PEx pins Output type to push-pull */ 331 | GPIOE->OTYPER = 0x00000000; 332 | /* No pull-up, pull-down for PEx pins */ 333 | GPIOE->PUPDR = 0x00000000; 334 | 335 | /* Connect PFx pins to FMC Alternate function */ 336 | GPIOF->AFR[0] = 0xCCCCCCCC; 337 | GPIOF->AFR[1] = 0xCCCCCCCC; 338 | /* Configure PFx pins in Alternate function mode */ 339 | GPIOF->MODER = 0xAA800AAA; 340 | /* Configure PFx pins speed to 50 MHz */ 341 | GPIOF->OSPEEDR = 0xAA800AAA; 342 | /* Configure PFx pins Output type to push-pull */ 343 | GPIOF->OTYPER = 0x00000000; 344 | /* No pull-up, pull-down for PFx pins */ 345 | GPIOF->PUPDR = 0x00000000; 346 | 347 | /* Connect PGx pins to FMC Alternate function */ 348 | GPIOG->AFR[0] = 0xCCCCCCCC; 349 | GPIOG->AFR[1] = 0xCCCCCCCC; 350 | /* Configure PGx pins in Alternate function mode */ 351 | GPIOG->MODER = 0xAAAAAAAA; 352 | /* Configure PGx pins speed to 50 MHz */ 353 | GPIOG->OSPEEDR = 0xAAAAAAAA; 354 | /* Configure PGx pins Output type to push-pull */ 355 | GPIOG->OTYPER = 0x00000000; 356 | /* No pull-up, pull-down for PGx pins */ 357 | GPIOG->PUPDR = 0x00000000; 358 | 359 | /* Connect PHx pins to FMC Alternate function */ 360 | GPIOH->AFR[0] = 0x00C0CC00; 361 | GPIOH->AFR[1] = 0xCCCCCCCC; 362 | /* Configure PHx pins in Alternate function mode */ 363 | GPIOH->MODER = 0xAAAA08A0; 364 | /* Configure PHx pins speed to 50 MHz */ 365 | GPIOH->OSPEEDR = 0xAAAA08A0; 366 | /* Configure PHx pins Output type to push-pull */ 367 | GPIOH->OTYPER = 0x00000000; 368 | /* No pull-up, pull-down for PHx pins */ 369 | GPIOH->PUPDR = 0x00000000; 370 | 371 | /* Connect PIx pins to FMC Alternate function */ 372 | GPIOI->AFR[0] = 0xCCCCCCCC; 373 | GPIOI->AFR[1] = 0x00000CC0; 374 | /* Configure PIx pins in Alternate function mode */ 375 | GPIOI->MODER = 0x0028AAAA; 376 | /* Configure PIx pins speed to 50 MHz */ 377 | GPIOI->OSPEEDR = 0x0028AAAA; 378 | /* Configure PIx pins Output type to push-pull */ 379 | GPIOI->OTYPER = 0x00000000; 380 | /* No pull-up, pull-down for PIx pins */ 381 | GPIOI->PUPDR = 0x00000000; 382 | 383 | /*-- FMC Configuration -------------------------------------------------------*/ 384 | /* Enable the FMC interface clock */ 385 | RCC->AHB3ENR |= 0x00000001; 386 | /* Delay after an RCC peripheral clock enabling */ 387 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 388 | 389 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 390 | FMC_Bank5_6->SDTR[0] = 0x01115351; 391 | 392 | /* SDRAM initialization sequence */ 393 | /* Clock enable command */ 394 | FMC_Bank5_6->SDCMR = 0x00000011; 395 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 396 | while((tmpreg != 0) && (timeout-- > 0)) 397 | { 398 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 399 | } 400 | 401 | /* Delay */ 402 | for (index = 0; index<1000; index++); 403 | 404 | /* PALL command */ 405 | FMC_Bank5_6->SDCMR = 0x00000012; 406 | timeout = 0xFFFF; 407 | while((tmpreg != 0) && (timeout-- > 0)) 408 | { 409 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 410 | } 411 | 412 | /* Auto refresh command */ 413 | FMC_Bank5_6->SDCMR = 0x00000073; 414 | timeout = 0xFFFF; 415 | while((tmpreg != 0) && (timeout-- > 0)) 416 | { 417 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 418 | } 419 | 420 | /* MRD register program */ 421 | FMC_Bank5_6->SDCMR = 0x00046014; 422 | timeout = 0xFFFF; 423 | while((tmpreg != 0) && (timeout-- > 0)) 424 | { 425 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 426 | } 427 | 428 | /* Set refresh count */ 429 | tmpreg = FMC_Bank5_6->SDRTR; 430 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 431 | 432 | /* Disable write protection */ 433 | tmpreg = FMC_Bank5_6->SDCR[0]; 434 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 435 | 436 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 437 | /* Configure and enable Bank1_SRAM2 */ 438 | FMC_Bank1->BTCR[2] = 0x00001011; 439 | FMC_Bank1->BTCR[3] = 0x00000201; 440 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 441 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 442 | #if defined(STM32F469xx) || defined(STM32F479xx) 443 | /* Configure and enable Bank1_SRAM2 */ 444 | FMC_Bank1->BTCR[2] = 0x00001091; 445 | FMC_Bank1->BTCR[3] = 0x00110212; 446 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 447 | #endif /* STM32F469xx || STM32F479xx */ 448 | 449 | (void)(tmp); 450 | } 451 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 452 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 453 | /** 454 | * @brief Setup the external memory controller. 455 | * Called in startup_stm32f4xx.s before jump to main. 456 | * This function configures the external memories (SRAM/SDRAM) 457 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 458 | * @param None 459 | * @retval None 460 | */ 461 | void SystemInit_ExtMemCtl(void) 462 | { 463 | __IO uint32_t tmp = 0x00; 464 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 465 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 466 | #if defined (DATA_IN_ExtSDRAM) 467 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 468 | register __IO uint32_t index; 469 | 470 | #if defined(STM32F446xx) 471 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface 472 | clock */ 473 | RCC->AHB1ENR |= 0x0000007D; 474 | #else 475 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 476 | clock */ 477 | RCC->AHB1ENR |= 0x000001F8; 478 | #endif /* STM32F446xx */ 479 | /* Delay after an RCC peripheral clock enabling */ 480 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 481 | 482 | #if defined(STM32F446xx) 483 | /* Connect PAx pins to FMC Alternate function */ 484 | GPIOA->AFR[0] |= 0xC0000000; 485 | GPIOA->AFR[1] |= 0x00000000; 486 | /* Configure PDx pins in Alternate function mode */ 487 | GPIOA->MODER |= 0x00008000; 488 | /* Configure PDx pins speed to 50 MHz */ 489 | GPIOA->OSPEEDR |= 0x00008000; 490 | /* Configure PDx pins Output type to push-pull */ 491 | GPIOA->OTYPER |= 0x00000000; 492 | /* No pull-up, pull-down for PDx pins */ 493 | GPIOA->PUPDR |= 0x00000000; 494 | 495 | /* Connect PCx pins to FMC Alternate function */ 496 | GPIOC->AFR[0] |= 0x00CC0000; 497 | GPIOC->AFR[1] |= 0x00000000; 498 | /* Configure PDx pins in Alternate function mode */ 499 | GPIOC->MODER |= 0x00000A00; 500 | /* Configure PDx pins speed to 50 MHz */ 501 | GPIOC->OSPEEDR |= 0x00000A00; 502 | /* Configure PDx pins Output type to push-pull */ 503 | GPIOC->OTYPER |= 0x00000000; 504 | /* No pull-up, pull-down for PDx pins */ 505 | GPIOC->PUPDR |= 0x00000000; 506 | #endif /* STM32F446xx */ 507 | 508 | /* Connect PDx pins to FMC Alternate function */ 509 | GPIOD->AFR[0] = 0x000000CC; 510 | GPIOD->AFR[1] = 0xCC000CCC; 511 | /* Configure PDx pins in Alternate function mode */ 512 | GPIOD->MODER = 0xA02A000A; 513 | /* Configure PDx pins speed to 50 MHz */ 514 | GPIOD->OSPEEDR = 0xA02A000A; 515 | /* Configure PDx pins Output type to push-pull */ 516 | GPIOD->OTYPER = 0x00000000; 517 | /* No pull-up, pull-down for PDx pins */ 518 | GPIOD->PUPDR = 0x00000000; 519 | 520 | /* Connect PEx pins to FMC Alternate function */ 521 | GPIOE->AFR[0] = 0xC00000CC; 522 | GPIOE->AFR[1] = 0xCCCCCCCC; 523 | /* Configure PEx pins in Alternate function mode */ 524 | GPIOE->MODER = 0xAAAA800A; 525 | /* Configure PEx pins speed to 50 MHz */ 526 | GPIOE->OSPEEDR = 0xAAAA800A; 527 | /* Configure PEx pins Output type to push-pull */ 528 | GPIOE->OTYPER = 0x00000000; 529 | /* No pull-up, pull-down for PEx pins */ 530 | GPIOE->PUPDR = 0x00000000; 531 | 532 | /* Connect PFx pins to FMC Alternate function */ 533 | GPIOF->AFR[0] = 0xCCCCCCCC; 534 | GPIOF->AFR[1] = 0xCCCCCCCC; 535 | /* Configure PFx pins in Alternate function mode */ 536 | GPIOF->MODER = 0xAA800AAA; 537 | /* Configure PFx pins speed to 50 MHz */ 538 | GPIOF->OSPEEDR = 0xAA800AAA; 539 | /* Configure PFx pins Output type to push-pull */ 540 | GPIOF->OTYPER = 0x00000000; 541 | /* No pull-up, pull-down for PFx pins */ 542 | GPIOF->PUPDR = 0x00000000; 543 | 544 | /* Connect PGx pins to FMC Alternate function */ 545 | GPIOG->AFR[0] = 0xCCCCCCCC; 546 | GPIOG->AFR[1] = 0xCCCCCCCC; 547 | /* Configure PGx pins in Alternate function mode */ 548 | GPIOG->MODER = 0xAAAAAAAA; 549 | /* Configure PGx pins speed to 50 MHz */ 550 | GPIOG->OSPEEDR = 0xAAAAAAAA; 551 | /* Configure PGx pins Output type to push-pull */ 552 | GPIOG->OTYPER = 0x00000000; 553 | /* No pull-up, pull-down for PGx pins */ 554 | GPIOG->PUPDR = 0x00000000; 555 | 556 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 557 | || defined(STM32F469xx) || defined(STM32F479xx) 558 | /* Connect PHx pins to FMC Alternate function */ 559 | GPIOH->AFR[0] = 0x00C0CC00; 560 | GPIOH->AFR[1] = 0xCCCCCCCC; 561 | /* Configure PHx pins in Alternate function mode */ 562 | GPIOH->MODER = 0xAAAA08A0; 563 | /* Configure PHx pins speed to 50 MHz */ 564 | GPIOH->OSPEEDR = 0xAAAA08A0; 565 | /* Configure PHx pins Output type to push-pull */ 566 | GPIOH->OTYPER = 0x00000000; 567 | /* No pull-up, pull-down for PHx pins */ 568 | GPIOH->PUPDR = 0x00000000; 569 | 570 | /* Connect PIx pins to FMC Alternate function */ 571 | GPIOI->AFR[0] = 0xCCCCCCCC; 572 | GPIOI->AFR[1] = 0x00000CC0; 573 | /* Configure PIx pins in Alternate function mode */ 574 | GPIOI->MODER = 0x0028AAAA; 575 | /* Configure PIx pins speed to 50 MHz */ 576 | GPIOI->OSPEEDR = 0x0028AAAA; 577 | /* Configure PIx pins Output type to push-pull */ 578 | GPIOI->OTYPER = 0x00000000; 579 | /* No pull-up, pull-down for PIx pins */ 580 | GPIOI->PUPDR = 0x00000000; 581 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 582 | 583 | /*-- FMC Configuration -------------------------------------------------------*/ 584 | /* Enable the FMC interface clock */ 585 | RCC->AHB3ENR |= 0x00000001; 586 | /* Delay after an RCC peripheral clock enabling */ 587 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 588 | 589 | /* Configure and enable SDRAM bank1 */ 590 | #if defined(STM32F446xx) 591 | FMC_Bank5_6->SDCR[0] = 0x00001954; 592 | #else 593 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 594 | #endif /* STM32F446xx */ 595 | FMC_Bank5_6->SDTR[0] = 0x01115351; 596 | 597 | /* SDRAM initialization sequence */ 598 | /* Clock enable command */ 599 | FMC_Bank5_6->SDCMR = 0x00000011; 600 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 601 | while((tmpreg != 0) && (timeout-- > 0)) 602 | { 603 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 604 | } 605 | 606 | /* Delay */ 607 | for (index = 0; index<1000; index++); 608 | 609 | /* PALL command */ 610 | FMC_Bank5_6->SDCMR = 0x00000012; 611 | timeout = 0xFFFF; 612 | while((tmpreg != 0) && (timeout-- > 0)) 613 | { 614 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 615 | } 616 | 617 | /* Auto refresh command */ 618 | #if defined(STM32F446xx) 619 | FMC_Bank5_6->SDCMR = 0x000000F3; 620 | #else 621 | FMC_Bank5_6->SDCMR = 0x00000073; 622 | #endif /* STM32F446xx */ 623 | timeout = 0xFFFF; 624 | while((tmpreg != 0) && (timeout-- > 0)) 625 | { 626 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 627 | } 628 | 629 | /* MRD register program */ 630 | #if defined(STM32F446xx) 631 | FMC_Bank5_6->SDCMR = 0x00044014; 632 | #else 633 | FMC_Bank5_6->SDCMR = 0x00046014; 634 | #endif /* STM32F446xx */ 635 | timeout = 0xFFFF; 636 | while((tmpreg != 0) && (timeout-- > 0)) 637 | { 638 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 639 | } 640 | 641 | /* Set refresh count */ 642 | tmpreg = FMC_Bank5_6->SDRTR; 643 | #if defined(STM32F446xx) 644 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); 645 | #else 646 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 647 | #endif /* STM32F446xx */ 648 | 649 | /* Disable write protection */ 650 | tmpreg = FMC_Bank5_6->SDCR[0]; 651 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 652 | #endif /* DATA_IN_ExtSDRAM */ 653 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 654 | 655 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 656 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 657 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 658 | 659 | #if defined(DATA_IN_ExtSRAM) 660 | /*-- GPIOs Configuration -----------------------------------------------------*/ 661 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 662 | RCC->AHB1ENR |= 0x00000078; 663 | /* Delay after an RCC peripheral clock enabling */ 664 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 665 | 666 | /* Connect PDx pins to FMC Alternate function */ 667 | GPIOD->AFR[0] = 0x00CCC0CC; 668 | GPIOD->AFR[1] = 0xCCCCCCCC; 669 | /* Configure PDx pins in Alternate function mode */ 670 | GPIOD->MODER = 0xAAAA0A8A; 671 | /* Configure PDx pins speed to 100 MHz */ 672 | GPIOD->OSPEEDR = 0xFFFF0FCF; 673 | /* Configure PDx pins Output type to push-pull */ 674 | GPIOD->OTYPER = 0x00000000; 675 | /* No pull-up, pull-down for PDx pins */ 676 | GPIOD->PUPDR = 0x00000000; 677 | 678 | /* Connect PEx pins to FMC Alternate function */ 679 | GPIOE->AFR[0] = 0xC00CC0CC; 680 | GPIOE->AFR[1] = 0xCCCCCCCC; 681 | /* Configure PEx pins in Alternate function mode */ 682 | GPIOE->MODER = 0xAAAA828A; 683 | /* Configure PEx pins speed to 100 MHz */ 684 | GPIOE->OSPEEDR = 0xFFFFC3CF; 685 | /* Configure PEx pins Output type to push-pull */ 686 | GPIOE->OTYPER = 0x00000000; 687 | /* No pull-up, pull-down for PEx pins */ 688 | GPIOE->PUPDR = 0x00000000; 689 | 690 | /* Connect PFx pins to FMC Alternate function */ 691 | GPIOF->AFR[0] = 0x00CCCCCC; 692 | GPIOF->AFR[1] = 0xCCCC0000; 693 | /* Configure PFx pins in Alternate function mode */ 694 | GPIOF->MODER = 0xAA000AAA; 695 | /* Configure PFx pins speed to 100 MHz */ 696 | GPIOF->OSPEEDR = 0xFF000FFF; 697 | /* Configure PFx pins Output type to push-pull */ 698 | GPIOF->OTYPER = 0x00000000; 699 | /* No pull-up, pull-down for PFx pins */ 700 | GPIOF->PUPDR = 0x00000000; 701 | 702 | /* Connect PGx pins to FMC Alternate function */ 703 | GPIOG->AFR[0] = 0x00CCCCCC; 704 | GPIOG->AFR[1] = 0x000000C0; 705 | /* Configure PGx pins in Alternate function mode */ 706 | GPIOG->MODER = 0x00085AAA; 707 | /* Configure PGx pins speed to 100 MHz */ 708 | GPIOG->OSPEEDR = 0x000CAFFF; 709 | /* Configure PGx pins Output type to push-pull */ 710 | GPIOG->OTYPER = 0x00000000; 711 | /* No pull-up, pull-down for PGx pins */ 712 | GPIOG->PUPDR = 0x00000000; 713 | 714 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ 715 | /* Enable the FMC/FSMC interface clock */ 716 | RCC->AHB3ENR |= 0x00000001; 717 | 718 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 719 | /* Delay after an RCC peripheral clock enabling */ 720 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 721 | /* Configure and enable Bank1_SRAM2 */ 722 | FMC_Bank1->BTCR[2] = 0x00001011; 723 | FMC_Bank1->BTCR[3] = 0x00000201; 724 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 725 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 726 | #if defined(STM32F469xx) || defined(STM32F479xx) 727 | /* Delay after an RCC peripheral clock enabling */ 728 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 729 | /* Configure and enable Bank1_SRAM2 */ 730 | FMC_Bank1->BTCR[2] = 0x00001091; 731 | FMC_Bank1->BTCR[3] = 0x00110212; 732 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 733 | #endif /* STM32F469xx || STM32F479xx */ 734 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 735 | || defined(STM32F412Zx) || defined(STM32F412Vx) 736 | /* Delay after an RCC peripheral clock enabling */ 737 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 738 | /* Configure and enable Bank1_SRAM2 */ 739 | FSMC_Bank1->BTCR[2] = 0x00001011; 740 | FSMC_Bank1->BTCR[3] = 0x00000201; 741 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; 742 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ 743 | 744 | #endif /* DATA_IN_ExtSRAM */ 745 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 746 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ 747 | (void)(tmp); 748 | } 749 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ 750 | /** 751 | * @} 752 | */ 753 | 754 | /** 755 | * @} 756 | */ 757 | 758 | /** 759 | * @} 760 | */ 761 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 762 | -------------------------------------------------------------------------------- /cubefix.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Fix project after updating it with STM32CubeMX 4 | 5 | set -e 6 | 7 | cp Makefile.backup Makefile 8 | dos2unix Src/main.c 9 | sed -i -e '1,37d' Src/main.c 10 | -------------------------------------------------------------------------------- /main.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | File.Version=6 3 | KeepUserPlacement=false 4 | Mcu.Family=STM32F4 5 | Mcu.IP0=I2C1 6 | Mcu.IP1=NVIC 7 | Mcu.IP2=RCC 8 | Mcu.IP3=SYS 9 | Mcu.IP4=USART1 10 | Mcu.IPNb=5 11 | Mcu.Name=STM32F405RGTx 12 | Mcu.Package=LQFP64 13 | Mcu.Pin0=PC14-OSC32_IN 14 | Mcu.Pin1=PC15-OSC32_OUT 15 | Mcu.Pin10=PB9 16 | Mcu.Pin11=VP_SYS_VS_Systick 17 | Mcu.Pin2=PH0-OSC_IN 18 | Mcu.Pin3=PH1-OSC_OUT 19 | Mcu.Pin4=PA9 20 | Mcu.Pin5=PA10 21 | Mcu.Pin6=PA13 22 | Mcu.Pin7=PA14 23 | Mcu.Pin8=PD2 24 | Mcu.Pin9=PB8 25 | Mcu.PinsNb=12 26 | Mcu.UserConstants= 27 | Mcu.UserName=STM32F405RGTx 28 | MxCube.Version=4.23.0 29 | MxDb.Version=DB.4.0.230 30 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false 31 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false 32 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false 33 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false 34 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false 35 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false 36 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 37 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false 38 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false 39 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false 40 | PA10.Mode=Asynchronous 41 | PA10.Signal=USART1_RX 42 | PA13.Mode=Serial_Wire 43 | PA13.Signal=SYS_JTMS-SWDIO 44 | PA14.Mode=Serial_Wire 45 | PA14.Signal=SYS_JTCK-SWCLK 46 | PA9.Mode=Asynchronous 47 | PA9.Signal=USART1_TX 48 | PB8.Locked=true 49 | PB8.Mode=I2C 50 | PB8.Signal=I2C1_SCL 51 | PB9.Locked=true 52 | PB9.Mode=I2C 53 | PB9.Signal=I2C1_SDA 54 | PC14-OSC32_IN.Locked=true 55 | PC14-OSC32_IN.Mode=LSE-External-Oscillator 56 | PC14-OSC32_IN.Signal=RCC_OSC32_IN 57 | PC15-OSC32_OUT.Locked=true 58 | PC15-OSC32_OUT.Mode=LSE-External-Oscillator 59 | PC15-OSC32_OUT.Signal=RCC_OSC32_OUT 60 | PCC.Checker=false 61 | PCC.Line=STM32F405/415 62 | PCC.MCU=STM32F405RGTx 63 | PCC.PartNumber=STM32F405RGTx 64 | PCC.Seq0=0 65 | PCC.Series=STM32F4 66 | PCC.Temperature=25 67 | PCC.Vdd=3.3 68 | PD2.GPIOParameters=GPIO_Label 69 | PD2.GPIO_Label=ULED 70 | PD2.Locked=true 71 | PD2.Signal=GPIO_Output 72 | PH0-OSC_IN.Locked=true 73 | PH0-OSC_IN.Mode=HSE-External-Oscillator 74 | PH0-OSC_IN.Signal=RCC_OSC_IN 75 | PH1-OSC_OUT.Locked=true 76 | PH1-OSC_OUT.Mode=HSE-External-Oscillator 77 | PH1-OSC_OUT.Signal=RCC_OSC_OUT 78 | PinOutPanel.RotationAngle=0 79 | ProjectManager.AskForMigrate=true 80 | ProjectManager.BackupPrevious=false 81 | ProjectManager.CompilerOptimize=2 82 | ProjectManager.ComputerToolchain=false 83 | ProjectManager.CoupleFile=false 84 | ProjectManager.CustomerFirmwarePackage=/home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0 85 | ProjectManager.DefaultFWLocation=true 86 | ProjectManager.DeletePrevious=true 87 | ProjectManager.DeviceId=STM32F405RGTx 88 | ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.18.0 89 | ProjectManager.FreePins=false 90 | ProjectManager.HalAssertFull=false 91 | ProjectManager.HeapSize=0x200 92 | ProjectManager.KeepUserCode=true 93 | ProjectManager.LastFirmware=true 94 | ProjectManager.LibraryCopy=2 95 | ProjectManager.PreviousToolchain= 96 | ProjectManager.ProjectBuild=false 97 | ProjectManager.ProjectFileName=main.ioc 98 | ProjectManager.ProjectName=main 99 | ProjectManager.StackSize=0x400 100 | ProjectManager.TargetToolchain=Makefile 101 | ProjectManager.ToolChainLocation= 102 | ProjectManager.UnderRoot=false 103 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL,2-SystemClock_Config-RCC-false-HAL,3-MX_USART1_UART_Init-USART1-false-HAL,4-MX_I2C1_Init-I2C1-false-HAL 104 | RCC.48MHZClocksFreq_Value=42000000 105 | RCC.AHBFreq_Value=84000000 106 | RCC.APB1CLKDivider=RCC_HCLK_DIV2 107 | RCC.APB1Freq_Value=42000000 108 | RCC.APB1TimFreq_Value=84000000 109 | RCC.APB2Freq_Value=84000000 110 | RCC.APB2TimFreq_Value=84000000 111 | RCC.CortexFreq_Value=84000000 112 | RCC.EthernetFreq_Value=84000000 113 | RCC.FCLKCortexFreq_Value=84000000 114 | RCC.FamilyName=M 115 | RCC.HCLKFreq_Value=84000000 116 | RCC.HSE_VALUE=16000000 117 | RCC.HSI_VALUE=16000000 118 | RCC.I2SClocksFreq_Value=96000000 119 | RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S 120 | RCC.LSI_VALUE=32000 121 | RCC.MCO2PinFreq_Value=84000000 122 | RCC.PLLCLKFreq_Value=84000000 123 | RCC.PLLN=168 124 | RCC.PLLQCLKFreq_Value=42000000 125 | RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE 126 | RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE 127 | RCC.RTCFreq_Value=32768 128 | RCC.RTCHSEDivFreq_Value=8000000 129 | RCC.SYSCLKFreq_VALUE=84000000 130 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK 131 | RCC.VCOI2SOutputFreq_Value=192000000 132 | RCC.VCOInputFreq_Value=1000000 133 | RCC.VCOOutputFreq_Value=168000000 134 | RCC.VcooutputI2S=96000000 135 | USART1.BaudRate=9600 136 | USART1.IPParameters=VirtualMode,BaudRate 137 | USART1.VirtualMode=VM_ASYNC 138 | VP_SYS_VS_Systick.Mode=SysTick 139 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 140 | board=main 141 | -------------------------------------------------------------------------------- /mx.scratch: -------------------------------------------------------------------------------- 1 | 2 | 3 | /home/eax/projects/sandbox/stm32/stm32-r820t2/\main 4 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS 5 | /home/eax/STM32Cube/Repository//STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS 6 | 7 | Makefile 8 | 0 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | main 26 | STM32F405RGTx 27 | 0x200 28 | 0x400 29 | 30 | custom 31 | 32 | true 33 | swd 34 | 35 | 0 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | USE_FULL_LL_DRIVER 54 | MBEDTLS_CONFIG_FILE="mbedtls_config.h" 55 | _TIMEVAL_DEFINED 56 | _SYS_TIME_H_ 57 | 58 | 59 | 60 | 61 | Inc 62 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Inc 63 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy 64 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Device/ST/STM32F4xx/Include 65 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/CMSIS/Include 66 | 67 | 68 | 69 | 70 | 71 | false 72 | 73 | 74 | Drivers 75 | 76 | STM32F4xx_HAL_Driver 77 | 78 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c 79 | 80 | 81 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c 82 | 83 | 84 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c 85 | 86 | 87 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c 88 | 89 | 90 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c 91 | 92 | 93 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c 94 | 95 | 96 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c 97 | 98 | 99 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c 100 | 101 | 102 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c 103 | 104 | 105 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c 106 | 107 | 108 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c 109 | 110 | 111 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c 112 | 113 | 114 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c 115 | 116 | 117 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c 118 | 119 | 120 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c 121 | 122 | 123 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c 124 | 125 | 126 | /home/eax/STM32Cube/Repository/STM32Cube_FW_F4_V1.18.0/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c 127 | 128 | 129 | 130 | CMSIS 131 | 132 | Src/system_stm32f4xx.c 133 | 134 | 135 | 136 | 137 | Application 138 | 139 | User 140 | 141 | Src/main.c 142 | 143 | 144 | 145 | Src/stm32f4xx_it.c 146 | 147 | 148 | 149 | Src/stm32f4xx_hal_msp.c 150 | 151 | 152 | 153 | 154 | 155 | Src 156 | 157 | main.c 158 | 159 | Src/main.c 160 | 161 | 162 | 163 | 164 | Src 165 | 166 | stm32f4xx_hal_msp.c 167 | 168 | Src/stm32f4xx_hal_msp.c 169 | 170 | 171 | 172 | 173 | Src 174 | 175 | stm32f4xx_it.c 176 | 177 | Src/stm32f4xx_it.c 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | -------------------------------------------------------------------------------- /startup_stm32f405xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f405xx.s 4 | * @author MCD Application Team 5 | * @brief STM32F405xx Devices vector table for GCC based toolchains. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M4 processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | *

© COPYRIGHT 2017 STMicroelectronics

18 | * 19 | * Redistribution and use in source and binary forms, with or without modification, 20 | * are permitted provided that the following conditions are met: 21 | * 1. Redistributions of source code must retain the above copyright notice, 22 | * this list of conditions and the following disclaimer. 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, 24 | * this list of conditions and the following disclaimer in the documentation 25 | * and/or other materials provided with the distribution. 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 27 | * may be used to endorse or promote products derived from this software 28 | * without specific prior written permission. 29 | * 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 | * 41 | ****************************************************************************** 42 | */ 43 | 44 | .syntax unified 45 | .cpu cortex-m4 46 | .fpu softvfp 47 | .thumb 48 | 49 | .global g_pfnVectors 50 | .global Default_Handler 51 | 52 | /* start address for the initialization values of the .data section. 53 | defined in linker script */ 54 | .word _sidata 55 | /* start address for the .data section. defined in linker script */ 56 | .word _sdata 57 | /* end address for the .data section. defined in linker script */ 58 | .word _edata 59 | /* start address for the .bss section. defined in linker script */ 60 | .word _sbss 61 | /* end address for the .bss section. defined in linker script */ 62 | .word _ebss 63 | /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 64 | 65 | /** 66 | * @brief This is the code that gets called when the processor first 67 | * starts execution following a reset event. Only the absolutely 68 | * necessary set is performed, after which the application 69 | * supplied main() routine is called. 70 | * @param None 71 | * @retval : None 72 | */ 73 | 74 | .section .text.Reset_Handler 75 | .weak Reset_Handler 76 | .type Reset_Handler, %function 77 | Reset_Handler: 78 | ldr sp, =_estack /* set stack pointer */ 79 | 80 | /* Copy the data segment initializers from flash to SRAM */ 81 | movs r1, #0 82 | b LoopCopyDataInit 83 | 84 | CopyDataInit: 85 | ldr r3, =_sidata 86 | ldr r3, [r3, r1] 87 | str r3, [r0, r1] 88 | adds r1, r1, #4 89 | 90 | LoopCopyDataInit: 91 | ldr r0, =_sdata 92 | ldr r3, =_edata 93 | adds r2, r0, r1 94 | cmp r2, r3 95 | bcc CopyDataInit 96 | ldr r2, =_sbss 97 | b LoopFillZerobss 98 | /* Zero fill the bss segment. */ 99 | FillZerobss: 100 | movs r3, #0 101 | str r3, [r2], #4 102 | 103 | LoopFillZerobss: 104 | ldr r3, = _ebss 105 | cmp r2, r3 106 | bcc FillZerobss 107 | 108 | /* Call the clock system intitialization function.*/ 109 | bl SystemInit 110 | /* Call static constructors */ 111 | bl __libc_init_array 112 | /* Call the application's entry point.*/ 113 | bl main 114 | bx lr 115 | .size Reset_Handler, .-Reset_Handler 116 | 117 | /** 118 | * @brief This is the code that gets called when the processor receives an 119 | * unexpected interrupt. This simply enters an infinite loop, preserving 120 | * the system state for examination by a debugger. 121 | * @param None 122 | * @retval None 123 | */ 124 | .section .text.Default_Handler,"ax",%progbits 125 | Default_Handler: 126 | Infinite_Loop: 127 | b Infinite_Loop 128 | .size Default_Handler, .-Default_Handler 129 | /****************************************************************************** 130 | * 131 | * The minimal vector table for a Cortex M3. Note that the proper constructs 132 | * must be placed on this to ensure that it ends up at physical address 133 | * 0x0000.0000. 134 | * 135 | *******************************************************************************/ 136 | .section .isr_vector,"a",%progbits 137 | .type g_pfnVectors, %object 138 | .size g_pfnVectors, .-g_pfnVectors 139 | 140 | 141 | 142 | g_pfnVectors: 143 | .word _estack 144 | .word Reset_Handler 145 | 146 | .word NMI_Handler 147 | .word HardFault_Handler 148 | .word MemManage_Handler 149 | .word BusFault_Handler 150 | .word UsageFault_Handler 151 | .word 0 152 | .word 0 153 | .word 0 154 | .word 0 155 | .word SVC_Handler 156 | .word DebugMon_Handler 157 | .word 0 158 | .word PendSV_Handler 159 | .word SysTick_Handler 160 | 161 | /* External Interrupts */ 162 | .word WWDG_IRQHandler /* Window WatchDog */ 163 | .word PVD_IRQHandler /* PVD through EXTI Line detection */ 164 | .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ 165 | .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ 166 | .word FLASH_IRQHandler /* FLASH */ 167 | .word RCC_IRQHandler /* RCC */ 168 | .word EXTI0_IRQHandler /* EXTI Line0 */ 169 | .word EXTI1_IRQHandler /* EXTI Line1 */ 170 | .word EXTI2_IRQHandler /* EXTI Line2 */ 171 | .word EXTI3_IRQHandler /* EXTI Line3 */ 172 | .word EXTI4_IRQHandler /* EXTI Line4 */ 173 | .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ 174 | .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ 175 | .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ 176 | .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ 177 | .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ 178 | .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ 179 | .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ 180 | .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 181 | .word CAN1_TX_IRQHandler /* CAN1 TX */ 182 | .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ 183 | .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 184 | .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 185 | .word EXTI9_5_IRQHandler /* External Line[9:5]s */ 186 | .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ 187 | .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ 188 | .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ 189 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 190 | .word TIM2_IRQHandler /* TIM2 */ 191 | .word TIM3_IRQHandler /* TIM3 */ 192 | .word TIM4_IRQHandler /* TIM4 */ 193 | .word I2C1_EV_IRQHandler /* I2C1 Event */ 194 | .word I2C1_ER_IRQHandler /* I2C1 Error */ 195 | .word I2C2_EV_IRQHandler /* I2C2 Event */ 196 | .word I2C2_ER_IRQHandler /* I2C2 Error */ 197 | .word SPI1_IRQHandler /* SPI1 */ 198 | .word SPI2_IRQHandler /* SPI2 */ 199 | .word USART1_IRQHandler /* USART1 */ 200 | .word USART2_IRQHandler /* USART2 */ 201 | .word USART3_IRQHandler /* USART3 */ 202 | .word EXTI15_10_IRQHandler /* External Line[15:10]s */ 203 | .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ 204 | .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ 205 | .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ 206 | .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ 207 | .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ 208 | .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ 209 | .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ 210 | .word FSMC_IRQHandler /* FSMC */ 211 | .word SDIO_IRQHandler /* SDIO */ 212 | .word TIM5_IRQHandler /* TIM5 */ 213 | .word SPI3_IRQHandler /* SPI3 */ 214 | .word UART4_IRQHandler /* UART4 */ 215 | .word UART5_IRQHandler /* UART5 */ 216 | .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ 217 | .word TIM7_IRQHandler /* TIM7 */ 218 | .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ 219 | .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ 220 | .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ 221 | .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ 222 | .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ 223 | .word 0 /* Reserved */ 224 | .word 0 /* Reserved */ 225 | .word CAN2_TX_IRQHandler /* CAN2 TX */ 226 | .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ 227 | .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ 228 | .word CAN2_SCE_IRQHandler /* CAN2 SCE */ 229 | .word OTG_FS_IRQHandler /* USB OTG FS */ 230 | .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ 231 | .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ 232 | .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ 233 | .word USART6_IRQHandler /* USART6 */ 234 | .word I2C3_EV_IRQHandler /* I2C3 event */ 235 | .word I2C3_ER_IRQHandler /* I2C3 error */ 236 | .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ 237 | .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ 238 | .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ 239 | .word OTG_HS_IRQHandler /* USB OTG HS */ 240 | .word 0 /* Reserved */ 241 | .word 0 /* Reserved */ 242 | .word HASH_RNG_IRQHandler /* Hash and Rng */ 243 | .word FPU_IRQHandler /* FPU */ 244 | 245 | 246 | /******************************************************************************* 247 | * 248 | * Provide weak aliases for each Exception handler to the Default_Handler. 249 | * As they are weak aliases, any function with the same name will override 250 | * this definition. 251 | * 252 | *******************************************************************************/ 253 | .weak NMI_Handler 254 | .thumb_set NMI_Handler,Default_Handler 255 | 256 | .weak HardFault_Handler 257 | .thumb_set HardFault_Handler,Default_Handler 258 | 259 | .weak MemManage_Handler 260 | .thumb_set MemManage_Handler,Default_Handler 261 | 262 | .weak BusFault_Handler 263 | .thumb_set BusFault_Handler,Default_Handler 264 | 265 | .weak UsageFault_Handler 266 | .thumb_set UsageFault_Handler,Default_Handler 267 | 268 | .weak SVC_Handler 269 | .thumb_set SVC_Handler,Default_Handler 270 | 271 | .weak DebugMon_Handler 272 | .thumb_set DebugMon_Handler,Default_Handler 273 | 274 | .weak PendSV_Handler 275 | .thumb_set PendSV_Handler,Default_Handler 276 | 277 | .weak SysTick_Handler 278 | .thumb_set SysTick_Handler,Default_Handler 279 | 280 | .weak WWDG_IRQHandler 281 | .thumb_set WWDG_IRQHandler,Default_Handler 282 | 283 | .weak PVD_IRQHandler 284 | .thumb_set PVD_IRQHandler,Default_Handler 285 | 286 | .weak TAMP_STAMP_IRQHandler 287 | .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 288 | 289 | .weak RTC_WKUP_IRQHandler 290 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler 291 | 292 | .weak FLASH_IRQHandler 293 | .thumb_set FLASH_IRQHandler,Default_Handler 294 | 295 | .weak RCC_IRQHandler 296 | .thumb_set RCC_IRQHandler,Default_Handler 297 | 298 | .weak EXTI0_IRQHandler 299 | .thumb_set EXTI0_IRQHandler,Default_Handler 300 | 301 | .weak EXTI1_IRQHandler 302 | .thumb_set EXTI1_IRQHandler,Default_Handler 303 | 304 | .weak EXTI2_IRQHandler 305 | .thumb_set EXTI2_IRQHandler,Default_Handler 306 | 307 | .weak EXTI3_IRQHandler 308 | .thumb_set EXTI3_IRQHandler,Default_Handler 309 | 310 | .weak EXTI4_IRQHandler 311 | .thumb_set EXTI4_IRQHandler,Default_Handler 312 | 313 | .weak DMA1_Stream0_IRQHandler 314 | .thumb_set DMA1_Stream0_IRQHandler,Default_Handler 315 | 316 | .weak DMA1_Stream1_IRQHandler 317 | .thumb_set DMA1_Stream1_IRQHandler,Default_Handler 318 | 319 | .weak DMA1_Stream2_IRQHandler 320 | .thumb_set DMA1_Stream2_IRQHandler,Default_Handler 321 | 322 | .weak DMA1_Stream3_IRQHandler 323 | .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 324 | 325 | .weak DMA1_Stream4_IRQHandler 326 | .thumb_set DMA1_Stream4_IRQHandler,Default_Handler 327 | 328 | .weak DMA1_Stream5_IRQHandler 329 | .thumb_set DMA1_Stream5_IRQHandler,Default_Handler 330 | 331 | .weak DMA1_Stream6_IRQHandler 332 | .thumb_set DMA1_Stream6_IRQHandler,Default_Handler 333 | 334 | .weak ADC_IRQHandler 335 | .thumb_set ADC_IRQHandler,Default_Handler 336 | 337 | .weak CAN1_TX_IRQHandler 338 | .thumb_set CAN1_TX_IRQHandler,Default_Handler 339 | 340 | .weak CAN1_RX0_IRQHandler 341 | .thumb_set CAN1_RX0_IRQHandler,Default_Handler 342 | 343 | .weak CAN1_RX1_IRQHandler 344 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 345 | 346 | .weak CAN1_SCE_IRQHandler 347 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 348 | 349 | .weak EXTI9_5_IRQHandler 350 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 351 | 352 | .weak TIM1_BRK_TIM9_IRQHandler 353 | .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler 354 | 355 | .weak TIM1_UP_TIM10_IRQHandler 356 | .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler 357 | 358 | .weak TIM1_TRG_COM_TIM11_IRQHandler 359 | .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler 360 | 361 | .weak TIM1_CC_IRQHandler 362 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 363 | 364 | .weak TIM2_IRQHandler 365 | .thumb_set TIM2_IRQHandler,Default_Handler 366 | 367 | .weak TIM3_IRQHandler 368 | .thumb_set TIM3_IRQHandler,Default_Handler 369 | 370 | .weak TIM4_IRQHandler 371 | .thumb_set TIM4_IRQHandler,Default_Handler 372 | 373 | .weak I2C1_EV_IRQHandler 374 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 375 | 376 | .weak I2C1_ER_IRQHandler 377 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 378 | 379 | .weak I2C2_EV_IRQHandler 380 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 381 | 382 | .weak I2C2_ER_IRQHandler 383 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 384 | 385 | .weak SPI1_IRQHandler 386 | .thumb_set SPI1_IRQHandler,Default_Handler 387 | 388 | .weak SPI2_IRQHandler 389 | .thumb_set SPI2_IRQHandler,Default_Handler 390 | 391 | .weak USART1_IRQHandler 392 | .thumb_set USART1_IRQHandler,Default_Handler 393 | 394 | .weak USART2_IRQHandler 395 | .thumb_set USART2_IRQHandler,Default_Handler 396 | 397 | .weak USART3_IRQHandler 398 | .thumb_set USART3_IRQHandler,Default_Handler 399 | 400 | .weak EXTI15_10_IRQHandler 401 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 402 | 403 | .weak RTC_Alarm_IRQHandler 404 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 405 | 406 | .weak OTG_FS_WKUP_IRQHandler 407 | .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler 408 | 409 | .weak TIM8_BRK_TIM12_IRQHandler 410 | .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler 411 | 412 | .weak TIM8_UP_TIM13_IRQHandler 413 | .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler 414 | 415 | .weak TIM8_TRG_COM_TIM14_IRQHandler 416 | .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler 417 | 418 | .weak TIM8_CC_IRQHandler 419 | .thumb_set TIM8_CC_IRQHandler,Default_Handler 420 | 421 | .weak DMA1_Stream7_IRQHandler 422 | .thumb_set DMA1_Stream7_IRQHandler,Default_Handler 423 | 424 | .weak FSMC_IRQHandler 425 | .thumb_set FSMC_IRQHandler,Default_Handler 426 | 427 | .weak SDIO_IRQHandler 428 | .thumb_set SDIO_IRQHandler,Default_Handler 429 | 430 | .weak TIM5_IRQHandler 431 | .thumb_set TIM5_IRQHandler,Default_Handler 432 | 433 | .weak SPI3_IRQHandler 434 | .thumb_set SPI3_IRQHandler,Default_Handler 435 | 436 | .weak UART4_IRQHandler 437 | .thumb_set UART4_IRQHandler,Default_Handler 438 | 439 | .weak UART5_IRQHandler 440 | .thumb_set UART5_IRQHandler,Default_Handler 441 | 442 | .weak TIM6_DAC_IRQHandler 443 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 444 | 445 | .weak TIM7_IRQHandler 446 | .thumb_set TIM7_IRQHandler,Default_Handler 447 | 448 | .weak DMA2_Stream0_IRQHandler 449 | .thumb_set DMA2_Stream0_IRQHandler,Default_Handler 450 | 451 | .weak DMA2_Stream1_IRQHandler 452 | .thumb_set DMA2_Stream1_IRQHandler,Default_Handler 453 | 454 | .weak DMA2_Stream2_IRQHandler 455 | .thumb_set DMA2_Stream2_IRQHandler,Default_Handler 456 | 457 | .weak DMA2_Stream3_IRQHandler 458 | .thumb_set DMA2_Stream3_IRQHandler,Default_Handler 459 | 460 | .weak DMA2_Stream4_IRQHandler 461 | .thumb_set DMA2_Stream4_IRQHandler,Default_Handler 462 | 463 | .weak CAN2_TX_IRQHandler 464 | .thumb_set CAN2_TX_IRQHandler,Default_Handler 465 | 466 | .weak CAN2_RX0_IRQHandler 467 | .thumb_set CAN2_RX0_IRQHandler,Default_Handler 468 | 469 | .weak CAN2_RX1_IRQHandler 470 | .thumb_set CAN2_RX1_IRQHandler,Default_Handler 471 | 472 | .weak CAN2_SCE_IRQHandler 473 | .thumb_set CAN2_SCE_IRQHandler,Default_Handler 474 | 475 | .weak OTG_FS_IRQHandler 476 | .thumb_set OTG_FS_IRQHandler,Default_Handler 477 | 478 | .weak DMA2_Stream5_IRQHandler 479 | .thumb_set DMA2_Stream5_IRQHandler,Default_Handler 480 | 481 | .weak DMA2_Stream6_IRQHandler 482 | .thumb_set DMA2_Stream6_IRQHandler,Default_Handler 483 | 484 | .weak DMA2_Stream7_IRQHandler 485 | .thumb_set DMA2_Stream7_IRQHandler,Default_Handler 486 | 487 | .weak USART6_IRQHandler 488 | .thumb_set USART6_IRQHandler,Default_Handler 489 | 490 | .weak I2C3_EV_IRQHandler 491 | .thumb_set I2C3_EV_IRQHandler,Default_Handler 492 | 493 | .weak I2C3_ER_IRQHandler 494 | .thumb_set I2C3_ER_IRQHandler,Default_Handler 495 | 496 | .weak OTG_HS_EP1_OUT_IRQHandler 497 | .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler 498 | 499 | .weak OTG_HS_EP1_IN_IRQHandler 500 | .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler 501 | 502 | .weak OTG_HS_WKUP_IRQHandler 503 | .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler 504 | 505 | .weak OTG_HS_IRQHandler 506 | .thumb_set OTG_HS_IRQHandler,Default_Handler 507 | 508 | .weak HASH_RNG_IRQHandler 509 | .thumb_set HASH_RNG_IRQHandler,Default_Handler 510 | 511 | .weak FPU_IRQHandler 512 | .thumb_set FPU_IRQHandler,Default_Handler 513 | 514 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 515 | 516 | 517 | --------------------------------------------------------------------------------