├── .github └── FUNDING.yml ├── .gitignore ├── LICENSE ├── README.md ├── assets └── arduboy_platform_icon.aseprite ├── dist ├── Assets │ └── arduboy │ │ └── common │ │ └── .gitkeep ├── Cores │ └── agg23.Arduboy │ │ ├── arduboy.rev │ │ ├── audio.json │ │ ├── core.json │ │ ├── data.json │ │ ├── icon.bin │ │ ├── info.txt │ │ ├── input.json │ │ ├── interact.json │ │ ├── variants.json │ │ └── video.json └── Platforms │ ├── _images │ └── arduboy.bin │ └── arduboy.json └── src ├── fpga ├── .gitignore ├── ap_core.qpf ├── ap_core.qsf ├── ap_core_assignment_defaults.qdf ├── apf │ ├── apf.qip │ ├── apf_constraints.sdc │ ├── apf_top.v │ ├── build_id_gen.tcl │ ├── common.v │ ├── io_bridge_peripheral.v │ ├── io_pad_controller.v │ ├── mf_datatable.qip │ ├── mf_datatable.v │ ├── mf_ddio_bidir_12.qip │ └── mf_ddio_bidir_12.v └── core │ ├── core_bridge_cmd.v │ ├── core_constraints.sdc │ ├── core_top.sv │ ├── mf_pllbase.bsf │ ├── mf_pllbase.ppf │ ├── mf_pllbase.qip │ ├── mf_pllbase.sip │ ├── mf_pllbase.spd │ ├── mf_pllbase.v │ ├── mf_pllbase │ ├── mf_pllbase_0002.qip │ └── mf_pllbase_0002.v │ ├── mf_pllbase_sim.f │ ├── mf_pllbase_sim │ ├── aldec │ │ └── rivierapro_setup.tcl │ ├── cadence │ │ ├── cds.lib │ │ ├── hdl.var │ │ └── ncsim_setup.sh │ ├── mentor │ │ └── msim_setup.tcl │ ├── mf_pllbase.vo │ └── synopsys │ │ ├── vcs │ │ └── vcs_setup.sh │ │ └── vcsmx │ │ ├── synopsys_sim.setup │ │ └── vcsmx_setup.sh │ ├── pin_ddio_clk.ppf │ ├── pin_ddio_clk.qip │ ├── pin_ddio_clk.v │ ├── rtl │ ├── avr │ │ ├── atmega-eep.v │ │ ├── atmega-pio.v │ │ ├── atmega-pll.v │ │ ├── atmega-rng-as-adc.v │ │ ├── atmega-rtc.v │ │ ├── atmega-spi-m.v │ │ ├── atmega-tim-10bit.v │ │ ├── atmega-tim-16bit.v │ │ ├── atmega-tim-8bit.v │ │ ├── atmega-twi_s_h.v │ │ ├── atmega-uart.v │ │ ├── atmega32u4_arduboy.v │ │ ├── atmega_twi.v │ │ ├── atmega_twi_s.v │ │ ├── io-dmux.v │ │ ├── mega-alu.v │ │ ├── mega-core.v │ │ ├── mega-def.v │ │ ├── mega-ram.v │ │ ├── mega-reg.v │ │ └── mega-rom.v │ ├── data_loader_8.v │ ├── rom_loader.v │ ├── video.sv │ └── video │ │ ├── spi-slave.v │ │ └── ssd1306-to-vga.v │ └── stp1.stp └── sim ├── core_test.sv ├── core_test_hex.sv ├── core_test_hex_tb.vhd ├── core_test_tb.vhd ├── inferred.sv ├── rom_inferred_tb.vhd ├── rom_loader_tb.vhd ├── rom_tb.vhd ├── sim.cr.mti ├── sim.mpf └── vsim.wlf /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | github: agg23 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.rbf_r 2 | src/sim/work/ 3 | src/sim/*.hex 4 | src/sim/*.mem 5 | src/sim/*.bin -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Arduboy for Analogue Pocket 2 | 3 | A highly modified port of [Arduboy_MiSTer](https://github.com/MiSTer-devel/Arduboy_MiSTer) by uXeBoy. This core has been updated to the latest Atmega core created by [Iulian Gheorghiu](https://github.com/dev-board-tech). 4 | 5 | Unlike the MiSTer port, this core can directly use `hex` ROMs that are typically provided for use on [Arduboy](https://www.arduboy.com/). 6 | 7 | ## Usage 8 | 9 | ROMs should be placed in `/Assets/arduboy/common` 10 | 11 | ## Limitations 12 | 13 | The core currently does not have EEPROM or save state support, so there is no persistence. This will be coming in a future update. 14 | 15 | Core may exhibit strange audio behavior on a few games. The cause of this issue is unknown at this time. Settings are provided to tweak the audio output to make it more agreeable. 16 | 17 | As far as we can tell, any tearing shown by this core is also presented on device. If you can prove this is not the case, please let me know. 18 | 19 | ## Settings 20 | 21 | The Arduboy has a unique sound production system, in that it uses a piezoelectric buzzer to produce sound. This buzzer is wired between two pins (_not_ to ground), so games have some additional flexibility in how they produce sounds. 22 | 23 | | Setting | Action | 24 | |-----------------|---------------------------------------------------------------------------------------------------------------------| 25 | | Load ROM | Opens the file browser to select a new hex file, and restarts the core | 26 | | Enable Buzzer 1 | Enables the use of buzzer pin 1 (Recommended) | 27 | | Enable Buzzer 2 | Enables the use of buzzer pin 2 (Recommended). If you are experiencing strange sounds, you may want to disable this | 28 | | Limit Volume | Decreases the output volume (Recommended). The Arduboy doesn't use a speaker, so it sounds quite loud using one | -------------------------------------------------------------------------------- /assets/arduboy_platform_icon.aseprite: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/agg23/openfpga-arduboy/25a4b981059172f488cbc345fe3a76af72f34b83/assets/arduboy_platform_icon.aseprite -------------------------------------------------------------------------------- /dist/Assets/arduboy/common/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/agg23/openfpga-arduboy/25a4b981059172f488cbc345fe3a76af72f34b83/dist/Assets/arduboy/common/.gitkeep -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/arduboy.rev: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/agg23/openfpga-arduboy/25a4b981059172f488cbc345fe3a76af72f34b83/dist/Cores/agg23.Arduboy/arduboy.rev -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/audio.json: -------------------------------------------------------------------------------- 1 | { 2 | "audio": { 3 | "magic": "APF_VER_1" 4 | } 5 | } 6 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/core.json: -------------------------------------------------------------------------------- 1 | { 2 | "core": { 3 | "magic": "APF_VER_1", 4 | "metadata": { 5 | "platform_ids": ["arduboy"], 6 | "shortname": "Arduboy", 7 | "description": "A small, portable Arduino console.", 8 | "author": "agg23", 9 | "url": "https://github.com/agg23/analogue-arduboy/", 10 | "version": "0.9.0", 11 | "date_release": "2022-09-03" 12 | }, 13 | "framework": { 14 | "target_product": "Analogue Pocket", 15 | "version_required": "1.1", 16 | "sleep_supported": false, 17 | "dock": { 18 | "supported": true, 19 | "analog_output": false 20 | }, 21 | "hardware": { 22 | "link_port": false, 23 | "cartridge_adapter": -1 24 | } 25 | }, 26 | "cores": [ 27 | { 28 | "name": "default", 29 | "id": 0, 30 | "filename": "arduboy.rev" 31 | } 32 | ] 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/data.json: -------------------------------------------------------------------------------- 1 | { 2 | "data": { 3 | "magic": "APF_VER_1", 4 | "data_slots": [ 5 | { 6 | "name": "HEX", 7 | "required": true, 8 | "parameters": 257, 9 | "extensions": ["hex"], 10 | "address": "0x00000000" 11 | } 12 | ] 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/icon.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/agg23/openfpga-arduboy/25a4b981059172f488cbc345fe3a76af72f34b83/dist/Cores/agg23.Arduboy/icon.bin -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/info.txt: -------------------------------------------------------------------------------- 1 | Port by agg23. MiSTer port by uXeBoy. Atmega core by Iulian Gheorghiu. 2 | 3 | Arduboy is an open source video game console around the size of a credit card. Based on an Arduino core and a 128x64 OLED display, the system packs impressive games into a very small and simple formfactor. 4 | 5 | Core may exibit strange audio behavior on a few games. The cause of this issue is unknown at this time. Settings are provided to tweak the audio output to make it more agreeable. -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/input.json: -------------------------------------------------------------------------------- 1 | { 2 | "input": { 3 | "magic": "APF_VER_1", 4 | "controllers": [ 5 | { 6 | "type": "default", 7 | "mappings": [ 8 | { 9 | "id": 0, 10 | "name": "A Button", 11 | "key": "pad_btn_a" 12 | }, 13 | { 14 | "id": 1, 15 | "name": "B Button", 16 | "key": "pad_btn_b" 17 | } 18 | ] 19 | } 20 | ] 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/interact.json: -------------------------------------------------------------------------------- 1 | { 2 | "interact": { 3 | "magic": "APF_VER_1", 4 | "variables": [ 5 | { 6 | "name": "Enable Buzzer 1", 7 | "id": 10, 8 | "type": "check", 9 | "enabled": true, 10 | "address": "0x10000000", 11 | "persist": true, 12 | "writeonly": true, 13 | "defaultval": 1, 14 | "value": 1 15 | }, 16 | { 17 | "name": "Enable Buzzer 2", 18 | "id": 11, 19 | "type": "check", 20 | "enabled": true, 21 | "address": "0x10000004", 22 | "persist": true, 23 | "writeonly": true, 24 | "defaultval": 1, 25 | "value": 1 26 | }, 27 | { 28 | "name": "Limit Volume", 29 | "id": 12, 30 | "type": "check", 31 | "enabled": true, 32 | "address": "0x10000008", 33 | "persist": true, 34 | "writeonly": true, 35 | "defaultval": 1, 36 | "value": 1 37 | } 38 | ], 39 | "messages": [] 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/variants.json: -------------------------------------------------------------------------------- 1 | { 2 | "variants": { 3 | "magic": "APF_VER_1", 4 | "variant_list": [] 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /dist/Cores/agg23.Arduboy/video.json: -------------------------------------------------------------------------------- 1 | { 2 | "video": { 3 | "magic": "APF_VER_1", 4 | "scaler_modes": [ 5 | { 6 | "width": 800, 7 | "height": 720, 8 | "aspect_w": 800, 9 | "aspect_h": 720, 10 | "rotation": 0, 11 | "mirror": 0 12 | } 13 | ] 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /dist/Platforms/_images/arduboy.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/agg23/openfpga-arduboy/25a4b981059172f488cbc345fe3a76af72f34b83/dist/Platforms/_images/arduboy.bin -------------------------------------------------------------------------------- /dist/Platforms/arduboy.json: -------------------------------------------------------------------------------- 1 | { 2 | "platform": { 3 | "category": "Handheld", 4 | "name": "Arduboy", 5 | "manufacturer": "Arduboy", 6 | "year": 2016 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/fpga/.gitignore: -------------------------------------------------------------------------------- 1 | */db/ 2 | */incremental_db/ 3 | */simulation/ 4 | */greybox_tmp/ 5 | incremental_db/ 6 | db/ 7 | output_files/ 8 | apf/build_id.mif 9 | PLLJ_PLLSPE_INFO.txt 10 | c5_pin_model_dump.txt 11 | cr_ie_info.json 12 | *.pin 13 | *.pof 14 | *.ptf.* 15 | *.qar 16 | *.qarlog 17 | *.qws 18 | *.rpt 19 | *.smsg 20 | *.sof 21 | *.sopc_builder 22 | *.summary 23 | *.txt 24 | *.bak 25 | *.cmp 26 | *.done 27 | *.xml 28 | *.sld 29 | *.cdf 30 | -------------------------------------------------------------------------------- /src/fpga/ap_core.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition 22 | # Date created = 21:31:36 January 22, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "18.1" 27 | DATE = "21:31:36 January 22, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "ap_core" 32 | -------------------------------------------------------------------------------- /src/fpga/apf/apf.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] 5 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] 6 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] 7 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] 8 | -------------------------------------------------------------------------------- /src/fpga/apf/apf_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # APF constraints 3 | # Do not edit this file. 4 | # 5 | # Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. 6 | 7 | create_clock -name clk_74a -period 13.468 [get_ports clk_74a] 8 | create_clock -name clk_74b -period 13.468 [get_ports clk_74b] 9 | create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] 10 | 11 | # autogenerate PLL clock names for use down below 12 | derive_pll_clocks 13 | 14 | 15 | # io constraints go here 16 | # 17 | 18 | 19 | # load in user constraints 20 | read_sdc "core/core_constraints.sdc" -------------------------------------------------------------------------------- /src/fpga/apf/build_id_gen.tcl: -------------------------------------------------------------------------------- 1 | # ================================================================================ 2 | # (c) 2011 Altera Corporation. All rights reserved. 3 | # Altera products are protected under numerous U.S. and foreign patents, maskwork 4 | # rights, copyrights and other intellectual property laws. 5 | # 6 | # This reference design file, and your use thereof, is subject to and governed 7 | # by the terms and conditions of the applicable Altera Reference Design License 8 | # Agreement (either as signed by you, agreed by you upon download or as a 9 | # "click-through" agreement upon installation andor found at www.altera.com). 10 | # By using this reference design file, you indicate your acceptance of such terms 11 | # and conditions between you and Altera Corporation. In the event that you do 12 | # not agree with such terms and conditions, you may not use the reference design 13 | # file and please promptly destroy any copies you have made. 14 | # 15 | # This reference design file is being provided on an "as-is" basis and as an 16 | # accommodation and therefore all warranties, representations or guarantees of 17 | # any kind (whether express, implied or statutory) including, without limitation, 18 | # warranties of merchantability, non-infringement, or fitness for a particular 19 | # purpose, are specifically disclaimed. By making this reference design file 20 | # available, Altera expressly does not recommend, suggest or require that this 21 | # reference design file be used in combination with any other product not 22 | # provided by Altera. 23 | # ================================================================================ 24 | # 25 | # Build ID Verilog Module Script 26 | # Jeff Wiencrot - 8/1/2011 27 | # 28 | # Generates a Verilog module that contains a timestamp, physical address, and host name 29 | # from the current build. These values are available from the build_date, build_time, 30 | # physical_address, and host_name output ports of the build_id module in the build_id.v 31 | # Verilog source file. 32 | # 33 | # The format for each value is as follows: 34 | # Date - 32-bit decimal number of the format mmddyyyy 35 | # Time - 32-bit decimal number of the format hhmmss 36 | # Phyiscal Address - 48-bit hexadecimal number 37 | # Host name - 120-bit hexadecimal number with pairs of digits equal to the 38 | # hexadecimal code for the first 15 ASCII characters of the host 39 | # name. For added clarity, host names that have fewer than 30 40 | # hexadecimal digits (15 characters) are padded on the left with 41 | # zeros. 42 | # 43 | # Usage: 44 | # 45 | # To manually execute this script, source this file using the following Tcl commands: 46 | # source build_id_verilog.tcl 47 | # 48 | # To have this script automatically execute each time your project is built, use the 49 | # following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): 50 | # set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id_verilog.tcl 51 | # 52 | # Comment out the last line to prevent the process from automatically executing when 53 | # the file is sourced. The process can then be executed with the following command: 54 | # generateBuildID_Verilog 55 | # 56 | # 57 | # For more information, see "build_identification.pdf" 58 | # 59 | # ================================================================================ 60 | # 61 | # 2021-01-21 Analogue 62 | # 63 | # Only care about generating build date/time, so the rest was removed. 64 | # The original can be downloaded from the Intel resource page 65 | # 66 | 67 | proc generateBuildID_Verilog {} { 68 | 69 | # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) 70 | set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] 71 | set buildTime [ clock format [ clock seconds ] -format %H%M%S ] 72 | 73 | # Create a Verilog file for output 74 | set outputFileName "apf/build_id.v" 75 | set outputFile [open $outputFileName "w"] 76 | 77 | # Output the Verilog source 78 | puts $outputFile "// Build ID Verilog Module" 79 | puts $outputFile "//" 80 | puts $outputFile "// Note - these are stored as binary coded decimal" 81 | puts $outputFile "// Date: $buildDate" 82 | puts $outputFile "// Time: $buildTime" 83 | puts $outputFile "" 84 | puts $outputFile "module build_id" 85 | puts $outputFile "(" 86 | puts $outputFile " output \[31:0\] build_date," 87 | puts $outputFile " output \[31:0\] build_time" 88 | puts $outputFile ");" 89 | puts $outputFile "" 90 | puts $outputFile " assign build_date = 32'h$buildDate;" 91 | puts $outputFile " assign build_time = 32'h$buildTime;" 92 | puts $outputFile "" 93 | puts $outputFile "endmodule" 94 | close $outputFile 95 | 96 | 97 | 98 | # Send confirmation message to the Messages window 99 | #post_message "APF core build date/time generated: [pwd]/$outputFileName" 100 | #post_message "Date: $buildDate" 101 | #post_message "Time: $buildTime" 102 | } 103 | 104 | 105 | proc generateBuildID_MIF {} { 106 | 107 | # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) 108 | set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] 109 | set buildTime [ clock format [ clock seconds ] -format %H%M%S ] 110 | set buildUnique [expr {int(rand()*(4294967295))}] 111 | 112 | set buildDateNoLeadingZeros [string trimleft $buildDate "0"] 113 | set buildTimeNoLeadingZeros [string trimleft $buildTime "0"] 114 | set buildDate4Byte [format "%08d" $buildDateNoLeadingZeros] 115 | set buildTime4Byte [format "%08d" $buildTimeNoLeadingZeros] 116 | set buildUnique4Byte [format "%08x" $buildUnique] 117 | 118 | #set buildDate4Byte \ 119 | [concat [string range $buildDate 0 1] \ 120 | [string range $buildDate 2 3] \ 121 | [string range $buildDate 4 5] \ 122 | [string range $buildDate 6 7] ] 123 | 124 | 125 | set buildDateNumBytes 4 126 | set buildTimeNumBytes 4 127 | 128 | # Calculate depth of the memory (8-bit) words 129 | set memoryDepth [expr $buildDateNumBytes + $buildTimeNumBytes] 130 | 131 | # Create a Memory Initialization File for output 132 | set outputFileName "apf/build_id.mif" 133 | set outputFile [open $outputFileName "w"] 134 | 135 | # Output the MIF header (see: http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_mif.htm) 136 | puts $outputFile "-- Build ID Memory Initialization File" 137 | puts $outputFile "--" 138 | puts $outputFile "" 139 | puts $outputFile "DEPTH = 256;" 140 | puts $outputFile "WIDTH = 32;" 141 | puts $outputFile "ADDRESS_RADIX = HEX;" 142 | puts $outputFile "DATA_RADIX = HEX;" 143 | puts $outputFile "" 144 | puts $outputFile "CONTENT" 145 | puts $outputFile "BEGIN" 146 | puts $outputFile "" 147 | puts $outputFile " 0E0 : $buildDate4Byte;" 148 | puts $outputFile " 0E1 : $buildTime4Byte;" 149 | puts $outputFile " 0E2 : $buildUnique4Byte;" 150 | puts $outputFile "" 151 | puts $outputFile "END;" 152 | 153 | # Close file to complete write 154 | close $outputFile 155 | 156 | # Send confirmation message to the Messages window 157 | post_message "APF core build date/time generated: [pwd]/$outputFileName" 158 | } 159 | 160 | generateBuildID_MIF 161 | 162 | # 2021-01-21 Analogue 163 | # 164 | # There are some circumstances where you want all parts of a FPGA flow to be deterministic, especially 165 | # when trying to hash out timing issues. 166 | # You should comment this line out and temporarily bypass buildid generation so that synthesis/par 167 | # have consistent working input. MIF bram contents like above won't affect the random seed or trigger 168 | # recompilation. 169 | # Don't forget to re-enable before you release. 170 | # 171 | # generateBuildID_Verilog 172 | -------------------------------------------------------------------------------- /src/fpga/apf/common.v: -------------------------------------------------------------------------------- 1 | // Software License Agreement 2 | 3 | // The software supplied herewith by Analogue Enterprises Limited (the "Company”), 4 | // the Analogue Pocket Framework (“APF”), is provided and licensed to you, the 5 | // Company's customer, solely for use in designing, testing and creating 6 | // applications for use with Company's Products or Services. The software is 7 | // owned by the Company and/or its licensors, and is protected under applicable 8 | // laws, including, but not limited to, U.S. copyright law. All rights are 9 | // reserved. By using the APF code you are agreeing to the terms of the End User 10 | // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] 11 | // and incorporated herein by reference. To the extent any use of the APF requires 12 | // application of the MIT License or the GNU General Public License and terms of 13 | // this APF Software License Agreement and EULA are inconsistent with such license, 14 | // the applicable terms of the MIT License or the GNU General Public License, as 15 | // applicable, will prevail. 16 | 17 | // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED 18 | // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, 19 | // ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR 20 | // NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM 21 | // DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE 22 | // MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, 23 | // THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND 24 | // DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING 25 | // THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR 26 | // ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY 27 | // INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, 28 | // INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR 29 | // INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY 30 | // OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY 31 | // CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, 32 | // WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU 33 | // TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH 34 | // YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE 35 | // FULLEST EXTENT PERMITTED BY APPLICABLE LAW. 36 | // 37 | // 2-stage synchronizer 38 | // 39 | module synch_2 #(parameter WIDTH = 1) ( 40 | input wire [WIDTH-1:0] i, // input signal 41 | output reg [WIDTH-1:0] o, // synchronized output 42 | input wire clk, // clock to synchronize on 43 | output wire rise, // one-cycle rising edge pulse 44 | output wire fall // one-cycle falling edge pulse 45 | ); 46 | 47 | reg [WIDTH-1:0] stage_1; 48 | reg [WIDTH-1:0] stage_2; 49 | reg [WIDTH-1:0] stage_3; 50 | 51 | assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; 52 | assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; 53 | always @(posedge clk) 54 | {stage_2, o, stage_1} <= {o, stage_1, i}; 55 | 56 | endmodule 57 | 58 | 59 | // 60 | // 3-stage synchronizer 61 | // 62 | module synch_3 #(parameter WIDTH = 1) ( 63 | input wire [WIDTH-1:0] i, // input signal 64 | output reg [WIDTH-1:0] o, // synchronized output 65 | input wire clk, // clock to synchronize on 66 | output wire rise, // one-cycle rising edge pulse 67 | output wire fall // one-cycle falling edge pulse 68 | ); 69 | 70 | reg [WIDTH-1:0] stage_1; 71 | reg [WIDTH-1:0] stage_2; 72 | reg [WIDTH-1:0] stage_3; 73 | 74 | assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; 75 | assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; 76 | always @(posedge clk) 77 | {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; 78 | 79 | endmodule 80 | 81 | 82 | module bram_block_dp #( 83 | parameter DATA = 32, 84 | parameter ADDR = 7 85 | ) ( 86 | input wire a_clk, 87 | input wire a_wr, 88 | input wire [ADDR-1:0] a_addr, 89 | input wire [DATA-1:0] a_din, 90 | output reg [DATA-1:0] a_dout, 91 | 92 | input wire b_clk, 93 | input wire b_wr, 94 | input wire [ADDR-1:0] b_addr, 95 | input wire [DATA-1:0] b_din, 96 | output reg [DATA-1:0] b_dout 97 | ); 98 | 99 | reg [DATA-1:0] mem [(2**ADDR)-1:0]; 100 | 101 | always @(posedge a_clk) begin 102 | if(a_wr) begin 103 | a_dout <= a_din; 104 | mem[a_addr] <= a_din; 105 | end else 106 | a_dout <= mem[a_addr]; 107 | end 108 | 109 | always @(posedge b_clk) begin 110 | if(b_wr) begin 111 | b_dout <= b_din; 112 | mem[b_addr] <= b_din; 113 | end else 114 | b_dout <= mem[b_addr]; 115 | end 116 | 117 | endmodule 118 | 119 | 120 | module bram_block_dp_nonstd #( 121 | parameter DATA = 32, 122 | parameter ADDR = 7, 123 | parameter DEPTH = 128 124 | ) ( 125 | input wire a_clk, 126 | input wire a_wr, 127 | input wire [ADDR-1:0] a_addr, 128 | input wire [DATA-1:0] a_din, 129 | output reg [DATA-1:0] a_dout, 130 | 131 | input wire b_clk, 132 | input wire b_wr, 133 | input wire [ADDR-1:0] b_addr, 134 | input wire [DATA-1:0] b_din, 135 | output reg [DATA-1:0] b_dout 136 | ); 137 | 138 | reg [DATA-1:0] mem [DEPTH-1:0]; 139 | 140 | always @(posedge a_clk) begin 141 | if(a_wr) begin 142 | a_dout <= a_din; 143 | mem[a_addr] <= a_din; 144 | end else 145 | a_dout <= mem[a_addr]; 146 | end 147 | 148 | always @(posedge b_clk) begin 149 | if(b_wr) begin 150 | b_dout <= b_din; 151 | mem[b_addr] <= b_din; 152 | end else 153 | b_dout <= mem[b_addr]; 154 | end 155 | 156 | endmodule 157 | -------------------------------------------------------------------------------- /src/fpga/apf/io_pad_controller.v: -------------------------------------------------------------------------------- 1 | // Software License Agreement 2 | 3 | // The software supplied herewith by Analogue Enterprises Limited (the "Company”), 4 | // the Analogue Pocket Framework (“APF”), is provided and licensed to you, the 5 | // Company's customer, solely for use in designing, testing and creating 6 | // applications for use with Company's Products or Services. The software is 7 | // owned by the Company and/or its licensors, and is protected under applicable 8 | // laws, including, but not limited to, U.S. copyright law. All rights are 9 | // reserved. By using the APF code you are agreeing to the terms of the End User 10 | // License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] 11 | // and incorporated herein by reference. To the extent any use of the APF requires 12 | // application of the MIT License or the GNU General Public License and terms of 13 | // this APF Software License Agreement and EULA are inconsistent with such license, 14 | // the applicable terms of the MIT License or the GNU General Public License, as 15 | // applicable, will prevail. 16 | 17 | // THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED 18 | // WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, 19 | // ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR 20 | // NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM 21 | // DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE 22 | // MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, 23 | // THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND 24 | // DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING 25 | // THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR 26 | // ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY 27 | // INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, 28 | // INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR 29 | // INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY 30 | // OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY 31 | // CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, 32 | // WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU 33 | // TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH 34 | // YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE 35 | // FULLEST EXTENT PERMITTED BY APPLICABLE LAW. 36 | // 37 | // pad controller 38 | // 2020-08-17 Analogue 39 | // 40 | 41 | module io_pad_controller ( 42 | 43 | input wire clk, 44 | input wire reset_n, 45 | 46 | inout reg pad_1wire, 47 | 48 | output reg [15:0] cont1_key, 49 | output reg [15:0] cont2_key, 50 | output reg [15:0] cont3_key, 51 | output reg [15:0] cont4_key, 52 | output reg [31:0] cont1_joy, 53 | output reg [31:0] cont2_joy, 54 | output reg [31:0] cont3_joy, 55 | output reg [31:0] cont4_joy, 56 | output reg [15:0] cont1_trig, 57 | output reg [15:0] cont2_trig, 58 | output reg [15:0] cont3_trig, 59 | output reg [15:0] cont4_trig, 60 | 61 | output reg rx_timed_out 62 | ); 63 | 64 | wire reset_n_s; 65 | synch_3 s00(reset_n, reset_n_s, clk); 66 | 67 | wire pad_1wire_s, pad_1wire_r, pad_1wire_f; 68 | synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f); 69 | 70 | 71 | // 72 | // protocol fsm 73 | // 74 | 75 | reg [20:0] rx_timeout; // ~28ms 76 | 77 | reg [15:0] auto_poll_cnt; // 882us 78 | reg auto_poll_queue; 79 | 80 | reg [18:0] heartbeat_cnt; // 7ms 81 | reg heartbeat_queue; 82 | 83 | 84 | localparam ST_RESET = 'd0; 85 | localparam ST_IDLE = 'd1; 86 | localparam ST_RX_BUTTON_1 = 'd2; 87 | localparam ST_RX_BUTTON_2 = 'd3; 88 | localparam ST_TX_SCALER = 'd4; 89 | localparam ST_END_TX = 'd5; 90 | 91 | reg [3:0] state; 92 | reg [3:0] cnt; 93 | 94 | always @(posedge clk) begin 95 | tx_word_start <= 0; 96 | 97 | auto_poll_cnt <= auto_poll_cnt + 1'b1; 98 | heartbeat_cnt <= heartbeat_cnt + 1'b1; 99 | 100 | // increment rx timeout, override and reset when idle below 101 | rx_timeout <= rx_timeout + 1'b1; 102 | 103 | case(state) 104 | ST_RESET: begin 105 | reset_tr_n <= 0; 106 | rx_timed_out <= 0; 107 | 108 | if(&rx_timeout[19:0]) begin 109 | state <= ST_IDLE; 110 | end 111 | end 112 | ST_IDLE: begin 113 | // idle state 114 | reset_tr_n <= 1; 115 | rx_timeout <= 0; 116 | cnt <= 0; 117 | if(auto_poll_queue) begin 118 | auto_poll_queue <= 0; 119 | 120 | tx_word_start <= 1; 121 | tx_word <= 32'h4A10000C; 122 | 123 | state <= ST_RX_BUTTON_1; 124 | end else if(heartbeat_queue) begin 125 | heartbeat_queue <= 0; 126 | 127 | tx_word_start <= 1; 128 | tx_word <= 32'h4AFE0000; 129 | 130 | state <= ST_END_TX; 131 | end 132 | end 133 | // receive button words 134 | ST_RX_BUTTON_1: begin 135 | if(tx_word_done) begin 136 | state <= ST_RX_BUTTON_2; 137 | end 138 | end 139 | ST_RX_BUTTON_2: begin 140 | if(rx_word_done) begin 141 | cnt <= cnt + 1'b1; 142 | case(cnt) 143 | 0: cont1_key <= rx_word[15:0]; 144 | 1: cont1_joy <= rx_word; 145 | 2: cont1_trig <= rx_word[15:0]; 146 | 147 | 3: cont2_key <= rx_word[15:0]; 148 | 4: cont2_joy <= rx_word; 149 | 5: cont2_trig <= rx_word[15:0]; 150 | 151 | 6: cont3_key <= rx_word[15:0]; 152 | 7: cont3_joy <= rx_word; 153 | 8: cont3_trig <= rx_word[15:0]; 154 | 155 | 9: cont4_key <= rx_word[15:0]; 156 | 10: cont4_joy <= rx_word; 157 | 11: begin 158 | cont4_trig <= rx_word[15:0]; 159 | state <= ST_IDLE; 160 | end 161 | endcase 162 | end 163 | end 164 | // do nothing 165 | ST_END_TX: begin 166 | // done sending, idle again 167 | if(tx_word_done) begin 168 | state <= ST_IDLE; 169 | end 170 | end 171 | endcase 172 | 173 | 174 | if(&auto_poll_cnt) begin 175 | auto_poll_queue <= 1; 176 | end 177 | if(&heartbeat_cnt) begin 178 | heartbeat_queue <= 1; 179 | end 180 | 181 | if(&rx_timeout) begin 182 | // reset protocol FSM which will also reset t/r engine 183 | rx_timed_out <= 1; 184 | rx_timeout <= 0; 185 | state <= ST_RESET; 186 | end 187 | 188 | if(~reset_n_s) begin 189 | state <= ST_RESET; 190 | end 191 | end 192 | 193 | 194 | 195 | 196 | 197 | // 198 | // word receive/transmit engine 199 | // 200 | reg reset_tr_n; 201 | localparam BITLEN = 60; 202 | 203 | reg rx_word_done; 204 | reg [31:0] rx_word_shift; 205 | reg [31:0] rx_word; 206 | 207 | reg tx_word_start, tx_word_start_1; 208 | reg tx_word_done; 209 | reg [31:0] tx_word; 210 | reg [31:0] tx_word_shift; 211 | 212 | reg [7:0] tr_cnt; 213 | reg [5:0] tr_bit; 214 | 215 | localparam TR_IDLE = 'd1; 216 | localparam TR_TX_START = 'd2; 217 | localparam TR_TX_CONTINUE = 'd3; 218 | localparam TR_TX_DONE = 'd4; 219 | localparam TR_RX_START = 'd5; 220 | localparam TR_RX_WAITEDGE = 'd6; 221 | localparam TR_RX_DONE = 'd7; 222 | 223 | reg [3:0] tr_state; 224 | 225 | always @(posedge clk) begin 226 | 227 | rx_word_done <= 0; 228 | tx_word_done <= 0; 229 | 230 | tx_word_start_1 <= tx_word_start; 231 | 232 | case(tr_state) 233 | TR_IDLE: begin 234 | tr_bit <= 0; 235 | tr_cnt <= 0; 236 | 237 | pad_1wire <= 1'bZ; 238 | 239 | if(tx_word_start & ~tx_word_start_1) begin 240 | // transmit word 241 | tx_word_shift <= tx_word; 242 | tr_state <= TR_TX_START; 243 | end 244 | 245 | if(pad_1wire_f) begin 246 | // receive word 247 | tr_state <= TR_RX_START; 248 | end 249 | end 250 | 251 | // transmit 32bit 252 | TR_TX_START: begin 253 | // insert delay 254 | tr_cnt <= tr_cnt + 1'b1; 255 | if(&tr_cnt) begin 256 | // drive from tristate(high) to explicitly high to prevent glitching 257 | pad_1wire <= 1'b1; 258 | tr_state <= TR_TX_CONTINUE; 259 | end 260 | end 261 | TR_TX_CONTINUE: begin 262 | tr_cnt <= tr_cnt + 1'b1; 263 | case(tr_cnt) 264 | 0: begin 265 | pad_1wire <= 1'b0; 266 | end 267 | (BITLEN/3): begin 268 | pad_1wire <= tx_word_shift[31]; 269 | end 270 | (BITLEN*2/3): begin 271 | pad_1wire <= 1'b1; 272 | end 273 | (BITLEN-1): begin 274 | tr_cnt <= 0; 275 | tx_word_shift <= {tx_word_shift[30:0], 1'b1}; 276 | 277 | tr_bit <= tr_bit + 1'b1; 278 | if(tr_bit == 31) begin 279 | tr_state <= TR_TX_DONE; 280 | end 281 | end 282 | endcase 283 | end 284 | TR_TX_DONE: begin 285 | tx_word_done <= 1; 286 | tr_state <= TR_IDLE; 287 | end 288 | 289 | // receive 32bit 290 | TR_RX_START: begin 291 | tr_cnt <= tr_cnt + 1'b1; 292 | case(tr_cnt) 293 | (BITLEN/2-4): begin 294 | rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s}; 295 | end 296 | (BITLEN*5/6): begin 297 | tr_cnt <= 0; 298 | 299 | // wait for next falling edge 300 | tr_state <= TR_RX_WAITEDGE; 301 | tr_bit <= tr_bit + 1'b1; 302 | if(tr_bit == 31) begin 303 | // if this is bit32, don't wait and finish 304 | tr_state <= TR_RX_DONE; 305 | end 306 | end 307 | endcase 308 | end 309 | TR_RX_WAITEDGE: begin 310 | if(pad_1wire_f) begin 311 | tr_state <= TR_RX_START; 312 | end 313 | end 314 | TR_RX_DONE: begin 315 | rx_word <= rx_word_shift; 316 | rx_word_done <= 1; 317 | tr_state <= TR_IDLE; 318 | end 319 | 320 | default: begin 321 | tr_state <= TR_IDLE; 322 | end 323 | endcase 324 | 325 | if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE; 326 | end 327 | 328 | endmodule 329 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_datatable.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] 5 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "18.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] 6 | -------------------------------------------------------------------------------- /src/fpga/apf/mf_ddio_bidir_12.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTDDIO_BIDIR% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTDDIO_BIDIR 5 | 6 | // ============================================================ 7 | // File Name: mf_ddio_bidir_12.v 8 | // Megafunction Name(s): 9 | // ALTDDIO_BIDIR 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.1.1 Build 646 04/11/2019 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2019 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and any partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details, at 34 | //https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module mf_ddio_bidir_12 ( 41 | datain_h, 42 | datain_l, 43 | inclock, 44 | oe, 45 | outclock, 46 | dataout_h, 47 | dataout_l, 48 | padio); 49 | 50 | input [11:0] datain_h; 51 | input [11:0] datain_l; 52 | input inclock; 53 | input oe; 54 | input outclock; 55 | output [11:0] dataout_h; 56 | output [11:0] dataout_l; 57 | inout [11:0] padio; 58 | 59 | wire [11:0] sub_wire0; 60 | wire [11:0] sub_wire1; 61 | wire [11:0] dataout_h = sub_wire0[11:0]; 62 | wire [11:0] dataout_l = sub_wire1[11:0]; 63 | 64 | altddio_bidir ALTDDIO_BIDIR_component ( 65 | .datain_h (datain_h), 66 | .datain_l (datain_l), 67 | .inclock (inclock), 68 | .oe (oe), 69 | .outclock (outclock), 70 | .padio (padio), 71 | .dataout_h (sub_wire0), 72 | .dataout_l (sub_wire1), 73 | .aclr (1'b0), 74 | .aset (1'b0), 75 | .combout (), 76 | .dqsundelayedout (), 77 | .inclocken (1'b1), 78 | .oe_out (), 79 | .outclocken (1'b1), 80 | .sclr (1'b0), 81 | .sset (1'b0)); 82 | defparam 83 | ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", 84 | ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", 85 | ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", 86 | ALTDDIO_BIDIR_component.invert_output = "OFF", 87 | ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", 88 | ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", 89 | ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", 90 | ALTDDIO_BIDIR_component.power_up_high = "OFF", 91 | ALTDDIO_BIDIR_component.width = 12; 92 | 93 | 94 | endmodule 95 | 96 | // ============================================================ 97 | // CNX file retrieval info 98 | // ============================================================ 99 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 100 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 101 | // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" 102 | // Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" 103 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 104 | // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" 105 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 106 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" 107 | // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" 108 | // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" 109 | // Retrieval info: CONSTANT: WIDTH NUMERIC "12" 110 | // Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" 111 | // Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 112 | // Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" 113 | // Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 114 | // Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" 115 | // Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 116 | // Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" 117 | // Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 118 | // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" 119 | // Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 120 | // Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" 121 | // Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 122 | // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" 123 | // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 124 | // Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" 125 | // Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE 128 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE 129 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE 130 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE 131 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE 132 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE 133 | // Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE 134 | // Retrieval info: LIB_FILE: altera_mf 135 | -------------------------------------------------------------------------------- /src/fpga/core/core_constraints.sdc: -------------------------------------------------------------------------------- 1 | # 2 | # user core constraints 3 | # 4 | # put your clock groups in here as well as any net assignments 5 | # 6 | 7 | set_clock_groups -asynchronous \ 8 | -group { bridge_spiclk } \ 9 | -group { clk_74a } \ 10 | -group { clk_74b } \ 11 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ 12 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ 13 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ 14 | -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } 15 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2022 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and any partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details, at 20 | https://fpgasoftware.intel.com/eula. 21 | */ 22 | (header "symbol" (version "1.1")) 23 | (symbol 24 | (rect 0 0 160 224) 25 | (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) 26 | (text "inst" (rect 8 208 20 220)(font "Arial" )) 27 | (port 28 | (pt 0 72) 29 | (input) 30 | (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) 31 | (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) 32 | (line (pt 0 72)(pt 48 72)(line_width 1)) 33 | ) 34 | (port 35 | (pt 0 112) 36 | (input) 37 | (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) 38 | (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) 39 | (line (pt 0 112)(pt 48 112)(line_width 1)) 40 | ) 41 | (port 42 | (pt 160 72) 43 | (output) 44 | (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) 45 | (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) 46 | (line (pt 160 72)(pt 112 72)(line_width 1)) 47 | ) 48 | (port 49 | (pt 160 112) 50 | (output) 51 | (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) 52 | (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) 53 | (line (pt 160 112)(pt 112 112)(line_width 1)) 54 | ) 55 | (port 56 | (pt 160 152) 57 | (output) 58 | (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) 59 | (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) 60 | (line (pt 160 152)(pt 112 152)(line_width 1)) 61 | ) 62 | (port 63 | (pt 160 192) 64 | (output) 65 | (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) 66 | (text "locked" (rect 127 181 163 192)(font "Arial" (font_size 8))) 67 | (line (pt 160 192)(pt 112 192)(line_width 1)) 68 | ) 69 | (drawing 70 | (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) 71 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 72 | (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) 73 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 74 | (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) 75 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 76 | (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) 77 | (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) 78 | (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) 79 | (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) 80 | (text "locked" (rect 113 163 262 339)(font "Arial" (color 128 0 0)(font_size 9))) 81 | (text "export" (rect 82 187 200 384)(font "Arial" (color 0 0 0))) 82 | (text " altera_pll " (rect 118 208 308 426)(font "Arial" )) 83 | (line (pt 48 32)(pt 112 32)(line_width 1)) 84 | (line (pt 112 32)(pt 112 208)(line_width 1)) 85 | (line (pt 48 208)(pt 112 208)(line_width 1)) 86 | (line (pt 48 32)(pt 48 208)(line_width 1)) 87 | (line (pt 49 52)(pt 49 76)(line_width 1)) 88 | (line (pt 50 52)(pt 50 76)(line_width 1)) 89 | (line (pt 49 92)(pt 49 116)(line_width 1)) 90 | (line (pt 50 92)(pt 50 116)(line_width 1)) 91 | (line (pt 111 52)(pt 111 76)(line_width 1)) 92 | (line (pt 110 52)(pt 110 76)(line_width 1)) 93 | (line (pt 111 92)(pt 111 116)(line_width 1)) 94 | (line (pt 110 92)(pt 110 116)(line_width 1)) 95 | (line (pt 111 132)(pt 111 156)(line_width 1)) 96 | (line (pt 110 132)(pt 110 156)(line_width 1)) 97 | (line (pt 111 172)(pt 111 196)(line_width 1)) 98 | (line (pt 110 172)(pt 110 196)(line_width 1)) 99 | (line (pt 0 0)(pt 160 0)(line_width 1)) 100 | (line (pt 160 0)(pt 160 224)(line_width 1)) 101 | (line (pt 0 224)(pt 160 224)(line_width 1)) 102 | (line (pt 0 0)(pt 0 224)(line_width 1)) 103 | ) 104 | ) 105 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_VERSION "21.1" 3 | set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_mf_pllbase" -name SPD_FILE [file join $::quartus(sip_path) "mf_pllbase.spd"] 5 | 6 | set_global_assignment -library "lib_mf_pllbase" -name MISC_FILE [file join $::quartus(sip_path) "mf_pllbase_sim/mf_pllbase.vo"] 7 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase/mf_pllbase_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module mf_pllbase_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'outclk2' 17 | output wire outclk_2, 18 | 19 | // interface 'locked' 20 | output wire locked 21 | ); 22 | 23 | altera_pll #( 24 | .fractional_vco_multiplier("true"), 25 | .reference_clock_frequency("74.25 MHz"), 26 | .operation_mode("normal"), 27 | .number_of_clocks(3), 28 | .output_clock_frequency0("15.999999 MHz"), 29 | .phase_shift0("0 ps"), 30 | .duty_cycle0(50), 31 | .output_clock_frequency1("46.476188 MHz"), 32 | .phase_shift1("0 ps"), 33 | .duty_cycle1(50), 34 | .output_clock_frequency2("46.476187 MHz"), 35 | .phase_shift2("0 ps"), 36 | .duty_cycle2(50), 37 | .output_clock_frequency3("0 MHz"), 38 | .phase_shift3("0 ps"), 39 | .duty_cycle3(50), 40 | .output_clock_frequency4("0 MHz"), 41 | .phase_shift4("0 ps"), 42 | .duty_cycle4(50), 43 | .output_clock_frequency5("0 MHz"), 44 | .phase_shift5("0 ps"), 45 | .duty_cycle5(50), 46 | .output_clock_frequency6("0 MHz"), 47 | .phase_shift6("0 ps"), 48 | .duty_cycle6(50), 49 | .output_clock_frequency7("0 MHz"), 50 | .phase_shift7("0 ps"), 51 | .duty_cycle7(50), 52 | .output_clock_frequency8("0 MHz"), 53 | .phase_shift8("0 ps"), 54 | .duty_cycle8(50), 55 | .output_clock_frequency9("0 MHz"), 56 | .phase_shift9("0 ps"), 57 | .duty_cycle9(50), 58 | .output_clock_frequency10("0 MHz"), 59 | .phase_shift10("0 ps"), 60 | .duty_cycle10(50), 61 | .output_clock_frequency11("0 MHz"), 62 | .phase_shift11("0 ps"), 63 | .duty_cycle11(50), 64 | .output_clock_frequency12("0 MHz"), 65 | .phase_shift12("0 ps"), 66 | .duty_cycle12(50), 67 | .output_clock_frequency13("0 MHz"), 68 | .phase_shift13("0 ps"), 69 | .duty_cycle13(50), 70 | .output_clock_frequency14("0 MHz"), 71 | .phase_shift14("0 ps"), 72 | .duty_cycle14(50), 73 | .output_clock_frequency15("0 MHz"), 74 | .phase_shift15("0 ps"), 75 | .duty_cycle15(50), 76 | .output_clock_frequency16("0 MHz"), 77 | .phase_shift16("0 ps"), 78 | .duty_cycle16(50), 79 | .output_clock_frequency17("0 MHz"), 80 | .phase_shift17("0 ps"), 81 | .duty_cycle17(50), 82 | .pll_type("General"), 83 | .pll_subtype("General") 84 | ) altera_pll_i ( 85 | .rst (rst), 86 | .outclk ({outclk_2, outclk_1, outclk_0}), 87 | .locked (locked), 88 | .fboutclk ( ), 89 | .fbclk (1'b0), 90 | .refclk (refclk) 91 | ); 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim.f: -------------------------------------------------------------------------------- 1 | mf_pllbase_sim/mf_pllbase.vo 2 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera_ver ./libraries/altera_ver/ 13 | DEFINE lpm_ver ./libraries/lpm_ver/ 14 | DEFINE sgate_ver ./libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 17 | DEFINE cyclonev_ver ./libraries/cyclonev_ver/ 18 | DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/ 19 | DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/ 20 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2022 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 21.1 850 win32 2022.09.02.18:32:10 16 | 17 | # ---------------------------------------- 18 | # ncsim - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script provides commands to simulate the following IP detected in 22 | # your Quartus project: 23 | # mf_pllbase 24 | # 25 | # Altera recommends that you source this Quartus-generated IP simulation 26 | # script from your own customized top-level script, and avoid editing this 27 | # generated script. 28 | # 29 | # To write a top-level shell script that compiles Altera simulation libraries 30 | # and the Quartus-generated IP in your project, along with your design and 31 | # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below 32 | # into a new file, e.g. named "ncsim.sh", and modify text as directed. 33 | # 34 | # You can also modify the simulation flow to suit your needs. Set the 35 | # following variables to 1 to disable their corresponding processes: 36 | # - SKIP_FILE_COPY: skip copying ROM/RAM initialization files 37 | # - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library 38 | # - SKIP_COM: skip compiling Quartus-generated IP simulation files 39 | # - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation 40 | # 41 | # ---------------------------------------- 42 | # # TOP-LEVEL TEMPLATE - BEGIN 43 | # # 44 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to 45 | # # construct paths to the files required to simulate the IP in your Quartus 46 | # # project. By default, the IP script assumes that you are launching the 47 | # # simulator from the IP script location. If launching from another 48 | # # location, set QSYS_SIMDIR to the output directory you specified when you 49 | # # generated the IP script, relative to the directory from which you launch 50 | # # the simulator. In this case, you must also copy the generated files 51 | # # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 52 | # # into the location from which you launch the simulator, or incorporate 53 | # # into any existing library setup. 54 | # # 55 | # # Run Quartus-generated IP simulation script once to compile Quartus EDA 56 | # # simulation libraries and Quartus-generated IP simulation files, and copy 57 | # # any ROM/RAM initialization files to the simulation directory. 58 | # # - If necessary, specify any compilation options: 59 | # # USER_DEFINED_COMPILE_OPTIONS 60 | # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler 61 | # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler 62 | # # 63 | # source