├── README.md ├── _config.yml ├── arithmetic-circuits ├── 1-2-adders.md ├── 11-wallace-tree-multiplier.md ├── 12-dadda-multiplier.md ├── 13-14-booth-recoding.md ├── 3-generate-propagate-logic.md ├── 4-carry-bypass-adder.md ├── 5-carry-select-adder.md ├── 6-look-ahead-adder.md ├── 7-group-generate-propagate.md ├── 8-parallel-prefix-adders.md ├── 9-10-multipliers.md ├── README.md └── imgs │ ├── adders │ ├── N-bit-adder.png │ ├── cmos-half-adder.png │ ├── full-adder-cmos-carry.png │ ├── full-adder-cmos-sum.png │ ├── full-adder-kmap-truth-table.png │ ├── half-full-adders.png │ ├── ripple-carry-adder-delay-slope.png │ └── ripple-carry-adder.png │ ├── booth-recoding │ ├── booth-recoding-all-ones-example.png │ ├── booth-recoding-middle-ones-example.png │ ├── booth-recoding-systematically-example.png │ ├── booth-recoding-worst-case.png │ ├── modified-booth-recoding-example.png │ └── radix-4-example.png │ ├── carry-bypass-adder │ ├── carry_bypass_N-bit.png │ ├── carry_bypass_critical_path.png │ ├── carry_bypass_critical_path_delay.png │ ├── carry_bypass_delay_slope.png │ ├── carry_bypass_mux.png │ └── carry_bypass_optimal_delay.png │ ├── carry-select-adder │ ├── carry-select-adder-delay.png │ ├── carry-select-adder-diagram.png │ ├── carry-select-blocks-delays.png │ ├── carry-select-unequal-blocks-diff-tmux.png │ └── carry-select-unequal-blocks.png │ ├── dadda-multiplier │ ├── dadda-multiplier-8x8-example.png │ └── dadda-multipliers-sequence-equation.png │ ├── generate-propagate │ ├── full-adder-generate-propagate-truth-table.png │ ├── full-adder-generate-propagate.png │ └── manchester-carry-chain.png │ ├── group-generate-propagate │ ├── carryout-expressions-pattern.png │ ├── group-generate-propagate-dot-operator.png │ ├── group-generate.png │ └── group-propagate.png │ ├── look-ahead-adder │ ├── all-carry-out-expressions-from-carry-in.png │ ├── lookahead-adder-cmos.png │ ├── lookahead-in-large-adders.png │ └── lookahead-manchester-chain-dynamic-cmos.png │ ├── multipliers │ ├── binary-long-multiplication-example.png │ ├── general-multiplication.png │ ├── hardware-4-by-4-multiplier.png │ └── multiplier-delay.png │ ├── parallel-prefix-adders │ ├── brent-kunge-adder-8-bit.png │ ├── brent-kunge-fan-out-16-bit.png │ ├── group-generate-propagate.png │ ├── kogge-stone-adder-4-bit.png │ ├── kogge-stone-adder-8-16-bit.png │ ├── kogge-stone-delay-order.png │ ├── modified-ks-8-bit-2x2-combination.png │ └── modified-ks-8-bit.png │ └── wallace-tree-multiplier │ ├── partial-product-summation.png │ ├── wallace-tree-4x4-multiplier.png │ ├── wallace-tree-5x5-multiplier.png │ ├── wallace-tree-6x6-multiplier.png │ └── wallace-tree-delay-equation.png ├── design-flow ├── 1-layout.md ├── 10-asic-design-flow.md ├── 11-fpga.md ├── 2-stick-diagram.md ├── 3-std-cell-library.md ├── 4-routing-and-power.md ├── 5-design-rules.md ├── 6-fixed-point.md ├── 7-synthesis.md ├── 8-place-and-route.md ├── 9-drc-lvs.md ├── README.md └── imgs │ ├── asic-design-flow │ └── asic-std-design-flow.jpg │ ├── design-rules │ ├── antenna-design-rules.jpg │ ├── antenna-effect-sol-stacked-vias.jpg │ ├── antenna-effect-sol.jpg │ ├── design-rules-example.jpg │ ├── minimum-density-rule.jpg │ ├── overglass-layer.jpg │ └── process-variation.jpg │ ├── fixed-point │ ├── fixed-point-quantization-error.jpg │ └── integer-instead-of-float.jpg │ ├── fpga │ ├── fpga-design-flow.jpg │ ├── fpga-library-entry.jpg │ ├── fpga-logic-cell.jpg │ └── fpga-place-and-route.jpg │ ├── layout │ ├── layout.jpg │ ├── reading-layout-vs-circuit.jpg │ └── reading-layout.jpg │ ├── routing-and-power │ ├── distributing-supply-and-ground.jpg │ ├── inter-cell-connection.jpg │ ├── routing-between-cells.jpg │ ├── routing-gap.jpg │ └── routing-supply-and-ground.jpg │ ├── std-cells │ ├── library-entry.jpg │ ├── std-cell-inverter.jpg │ └── std-cell-nor.jpg │ └── stick-diagram │ ├── drawing-steps.jpg │ ├── eular-path-example.jpg │ ├── eular-path-example2.jpg │ ├── eular-path.jpg │ ├── inverter-example.jpg │ ├── layers-colors.jpg │ ├── nand-example.jpg │ └── nor-example.jpg ├── design-optimization └── design-optimization.md ├── memories ├── 1-2-memories.md ├── 11-12-sram.md ├── 13-sense-amplifier.md ├── 14-self-timing-in-sram.md ├── 15-16-17-dram.md ├── 18-19-column-decoder.md ├── 20-21-row-decoder.md ├── 3-4-nor-roms.md ├── 5-6-nand-roms.md ├── 7-non-volatile-memories.md ├── 8-eprom-eeprom.md ├── 9-10-flash.md ├── README.md └── imgs │ ├── column-decoder │ ├── column-8-1-multiplexer.png │ ├── drive-buffer.png │ ├── drive-inverter-chain.png │ ├── memory-auxiliary-circuits.png │ └── predecode-multiplex-architecure.png │ ├── dram │ ├── dram-array-sense-amplifier-circuit.png │ ├── dram-array-sense-amplifier-folded.png │ ├── dram-read-delay.png │ ├── dram-refresh-overhead.png │ ├── four-transistor-dram-cell-working.png │ ├── four-transistor-dram-cell.png │ ├── one-transistor-dram-Vout-equations.png │ ├── one-transistor-dram-cell.png │ ├── one-transistor-dram-layout-std-cmos.png │ ├── one-transistor-dram-layout-with-linear-capacitor.png │ ├── one-transistor-dram-reading-zero.png │ ├── three-transistor-dram-cell-layout.png │ └── three-transistor-dram-cell.png │ ├── eprom-eeprom │ ├── eeprom-array.png │ ├── eeprom-cell-erasing.png │ ├── eeprom-cell.png │ ├── eeprom-programming.png │ ├── eeprom-signle-cell-programming-erasure.png │ └── eprom-cell.png │ ├── flash │ ├── flash-double-gate-cell.png │ ├── nand-flash-array.png │ ├── nand-flash-characteristics.png │ ├── nand-flash-erasing.png │ ├── nand-flash-programming.png │ ├── nor-flash-array.png │ ├── nor-flash-erasing.png │ └── nor-flash-programming.png │ ├── memories │ ├── memory-classification.png │ ├── memory-multiple-port.png │ ├── memory-port.png │ ├── memory-square-array-banks.png │ ├── memory-square-array.png │ └── time-sharing-example.png │ ├── nand-roms │ ├── nand-roms-cell-delay.png │ ├── nand-roms-delays.png │ ├── nand-roms-dynamic-circuit.png │ ├── nand-roms-layout-threshold-lowering-implant.png │ ├── nand-roms-layout.png │ ├── nand-roms-precharge-delay-equation.png │ ├── nand-roms-precharge-delay.png │ ├── nand-roms-vs-nor-nmos-cells.png │ └── nand-roms-wave-form.png │ ├── non-volatile-memories │ ├── nvms-F-N-tunneling.png │ ├── nvms-avalanche-breakdown.png │ ├── nvms-double-gate-mosfet.png │ ├── nvms-hot-carrier-effect.png │ ├── nvms-transistor-characteristics.png │ └── nvms-types.png │ ├── nor-roms │ ├── nor-rom-array.png │ ├── nor-rom-cell-delay.png │ ├── nor-rom-delays.png │ ├── nor-rom-dynamic-cmos.png │ ├── nor-rom-layout-threshold-raising-implant.png │ ├── nor-rom-layout.png │ ├── nor-rom-precharge-delay-CBL.png │ ├── nor-rom-pseudo-active-bit-zero.png │ ├── nor-rom-pseudo-nmos-active-bit.png │ ├── nor-rom-pseudo-nmos.png │ ├── nor-rom-word-line-delay-ellmore-time-constant.png │ ├── nor-rom-word-line-delay-equivalent-circuit-2.png │ └── nor-rom-word-line-delay-equivalent-circuit.png │ ├── row-decoder │ ├── decoder.png │ ├── predecoder-finaldecoder-circuit.png │ ├── predecoder-finaldecoder-path.png │ ├── row-decoder-circuit-and-gates.png │ ├── row-decoder-logical-effort.png │ ├── row-decoder-predecoder-capacitance-circuit.png │ ├── row-decoder-predecoder-capacitance-delay-expression-diff.png │ ├── row-decoder-predecoder-capacitance-delay-expression1.png │ ├── row-decoder-predecoder-capacitance.png │ ├── row-decoder-predecoder-finaldecoder-circuit.png │ ├── row-decoder-predecoder-finaldecoder-tradeoffs.png │ ├── row-decoder-predecoder-finaldecoder.png │ └── row-decoder-word-line-pi-section-RC.png │ ├── self-timing-sram │ ├── cell-delay-replica.png │ ├── memory-deltaVBL-equalization.png │ ├── memory-read-address-change-control.png │ ├── memory-read-sequence-waveform.png │ ├── memory-read-timeline.png │ ├── memory-sense-amplifier-signal-delay.png │ └── row-decoder-replica.png │ ├── sense-amplifier │ ├── sense-amplifier-differentail-amplifier.png │ ├── sense-amplifier-positive-feedback-equation.png │ ├── sense-amplifier-positive-feedback-metastability.png │ ├── sense-amplifier-sram-array.png │ └── sram-with-sense-amplifier-circuit-and-waveforms.png │ └── sram │ ├── sram-cell-array.png │ ├── sram-cell-layout.png │ ├── sram-cell-read-operation.png │ ├── sram-cell-read-problem-cell-flip.png │ ├── sram-cell-read-wave-form.png │ ├── sram-cell-write-operation.png │ └── sram-cell.png ├── rtl ├── README.md ├── general-rtl.md ├── imgs │ └── y-chart │ │ ├── blocking-non-blocking.png │ │ ├── checklist-of-rtl-code.png │ │ ├── comb-loop.png │ │ ├── fsm-deadlock.png │ │ ├── implicit-latches.png │ │ ├── linting.png │ │ ├── multiple-drivers.png │ │ ├── rtl-vs-behav-model.png │ │ └── y-chart.png └── y-chart.md ├── testing ├── 1-design-for-testability.md ├── 11-12-testing-memories.md ├── 13-14-ic-packaging.md ├── 15-pcb-design-fabrication.md ├── 16-boundry-scan-jtag.md ├── 17-glitches-logical-hazards.md ├── 18-19-20-21-static-hazards.md ├── 18-19-static-hazards.md ├── 2-defects-faults-errors.md ├── 23-dynamic-hazards.md ├── 24-25-reliability-of-vlsi-systems.md ├── 3-test-design-fault-coverage.md ├── 4-yield-defect-level-fault-coverage.md ├── 5-stuck-at-fault-model.md ├── 6-stuck-open-short-fault-model.md ├── 7-8-scan-technique.md ├── 9-10-built-in-self-tests.md ├── README.md └── imgs │ ├── boundry-scan-jtag │ ├── bst-chip-boundry-pcb.png │ ├── bst-multi-chip-pcb.png │ └── chip-boundry-pcb.png │ ├── built-in-self-tests │ ├── BIST-LFSR-truth-table.png │ ├── BIST-signature-analyzer-setup.png │ ├── BIST-signature-analyzer-truth-table.png │ ├── automatic-test-pattern-generation-LFSR.png │ ├── built-in-self-test-setup.png │ └── linear-feedback-shift-register-ex.png │ ├── defect-fault-error │ ├── two-input-nor-gate-defected-no-error.png │ ├── two-input-nor-gate-defected.png │ └── two-input-nor-gate-std-cell-entry.png │ ├── design-for-testability │ ├── DFT-internal-nodes-issue.png │ ├── DFT-internal-nodes-mux.png │ ├── test-observation-gold-std.png │ └── testable-circuit.png │ ├── glitches-logical-hazards │ ├── combinational-logic-example.png │ ├── inertial-transport-delay-example.png │ ├── logical-hazards-types.png │ └── sync-pipeline-clock.png │ ├── ic-packaging │ ├── bga_mounting_technique.png │ ├── bga_packages.png │ ├── dip_packages.png │ ├── ic-package-bottom.png │ ├── ic-package-top.png │ ├── pga_packages.png │ └── surface_mount_packages.png │ ├── pcb-design-fabrication │ ├── pcb-example.png │ ├── pcb-fabrication-flow.png │ ├── pcb-multi-layer.png │ ├── pcb-two-layers.png │ └── pcb.png │ ├── reliability-of-vlsi-systems │ ├── failure-rate.png │ ├── weibull-beta-1-MTBF.png │ ├── weibull-beta-1.png │ └── weibull-distribution.png │ ├── scan-technique │ ├── internal-nodes-mux-pins.png │ ├── internal-nodes.png │ ├── scan-flipflop.png │ ├── scan-register-modes.png │ ├── scan-register.png │ ├── scannable-register-chip-example-operation.png │ ├── scannable-register-chip-example.png │ ├── scannable-register-chip-subsystems.png │ └── sync-pipeline-block.png │ ├── static-hazards │ ├── complex-circuit-example-glitch-values.png │ ├── complex-circuit-example-sol.png │ ├── complex-circuit-example.png │ ├── static-0-hazarad-example.png │ ├── static-0-hazarad-form.png │ ├── static-0-hazarad-kmap-sol.png │ ├── static-0-hazarad-kmap.png │ ├── static-1-hazarad-example-kmap-sol.png │ ├── static-1-hazarad-example-kmap.png │ ├── static-1-hazarad-example-solution-comb-delay.png │ ├── static-1-hazarad-example.png │ ├── static-1-hazarad-form.png │ ├── static-1-hazarad-kmap-circuit-example.png │ └── static-hazard-expression.png │ ├── stuck-at-fault-model │ ├── or-gate-stuck-at-model-example.png │ └── stuck-at-zero-example.png │ ├── stuck-open-short-fault-model │ ├── two-input-nand-M2sO-fault.png │ ├── two-input-nand-M2sS-fault.png │ ├── two-input-nand-example.png │ └── two-input-nand-fault-truth-table.png │ ├── test-design-fault-coverage │ ├── design-flow-dft.png │ ├── fault-coverage-graph.png │ ├── nand-gate-test-time.png │ └── testing-flow.png │ └── yield-defect-level-fault-coverage │ ├── defect-level-yield-fault-coverage-relations.png │ ├── defect-level-yield-fault-coverage-table.png │ └── defects-distribution.png ├── timing-analysis ├── README.md ├── cmos-timing.md ├── imgs │ ├── cmos-timing │ │ ├── dynamic-cmos-registers.png │ │ ├── holdtime-violation.png │ │ ├── inverters-in-dynamic-cmos.png │ │ ├── negative-slack-and-setuptime-violation.png │ │ ├── static-cmos-registers-holdtime.png │ │ └── static-cmos-registers.png │ ├── sta │ │ ├── clocks-delays.png │ │ ├── ex-holdtime-sol.png │ │ ├── ex-holdtime.png │ │ ├── ex-setuptime-sol.png │ │ ├── ex-setuptime.png │ │ ├── hold-setup-time.png │ │ ├── holdtime.png │ │ ├── problem-detection.png │ │ ├── setup-hold-checks.png │ │ ├── setuptime.png │ │ ├── timing-exceptions.png │ │ ├── timing-exceptions2.png │ │ ├── timing-exceptions3.png │ │ ├── timing-exceptions4.png │ │ ├── timing-paths.png │ │ └── timing-simulation.png │ └── testing │ │ └── golden-model-verification.png ├── static-timing-analysis.md └── timing-and-verification.md ├── verilog ├── README.md ├── imgs │ ├── blocking-assignment.png │ └── non-blocking-assignment.png ├── sequential-logic.md └── verilog-notes.md └── vhdl ├── 1-design-philosophy.md ├── 10-process-transactions-events.md ├── 11-Wait-statement.md ├── 12-mux-vhdl.md ├── 13-14-15-latches.md ├── 16-Registers-in-VHDL.md ├── 17-pipelining-in-VHDL.md ├── 18-variables-and-signals.md ├── 19-Counters.md ├── 2-entities-and-architecture.md ├── 20-Memories-in-VHDL.md ├── 21-fsm.md ├── 23-loops.md ├── 24-software-testbench.md ├── 25-file-io.md ├── 26-functions.md ├── 27-procedures-and-overloading.md ├── 28-configurations.md ├── 29-Packages.md ├── 3-IEEE-library-and-std-logic.md ├── 30-good-design-practices.md ├── 4-User-defined-types.md ├── 5-operators.md ├── 6-attributes.md ├── 7-hierarchical-design.md ├── 8-special-port-mapping.md ├── 9-constants-and-generics.md ├── README.md └── imgs ├── configuration ├── configuration-example.png ├── hierarachical-configuration-example.png └── port-renaming.png ├── file-io ├── file-test-vector-dump-memory.png ├── file-test-vector-online-testbench.png └── file-test-vector-simulation-test.png ├── fsm ├── data-path-controller.png ├── fsm-flow.png └── fsm.png ├── hierarchical-design └── component-arch-use.png ├── lateches ├── implicit-latch-3-inputs.png ├── implicit-latch-4-inputs.png ├── latch-borrow-time-equation.png ├── latch-loop.png ├── latch-pipeline-timing.png ├── latch-setup-time.png └── latch-timing-waveform.png ├── mux └── with-select-when-else-mux.png ├── pipelining └── fully-pipelined-three-multiplier-cascade.png ├── process-transaction-event ├── fully-populated-senstivity-list.png ├── process-end-wait-statement-code-pulses.png ├── process-wait-statement-code-pulses.png └── transaction-to-event.png ├── special-port-mapping └── trimmed-circuits.png └── testbench └── testbench-setup.png /README.md: -------------------------------------------------------------------------------- 1 | # vlsi-notes 2 | Digital IC design and vlsi notes 3 | - Notes I took during my study from different sources in digital integrated circuit design and very large scale integrated circuits. 4 | - The source will be included in each file. 5 | 6 | ## Contents 7 | - [Timing analysis](timing-analysis) 8 | - [Design flow](design-flow) 9 | - [VHDL](vhdl) 10 | - [Arithmetic circuits](arithmetic-circuits) 11 | - [Memories](memories) 12 | - [Testing and Design for testability](testing) 13 | - [Verilog](verilog) 14 | - [RTL](rtl) 15 | - [Design optimization](design-optimization/design-optimization.md) 16 | 17 | ## Contribution 18 | - If you found any mistake you can report it by opening an issue 19 | - You can modify, add anything and create a pull request 20 | -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-tactile -------------------------------------------------------------------------------- /arithmetic-circuits/1-2-adders.md: -------------------------------------------------------------------------------- 1 | # Half adders and Full adders 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16qnuE-nw0RkUq0IwRkzqyhD) playlist on arithmetic circuits. 3 | 4 | ## Intro 5 | - Building blocks for larger adders 6 | - Half adders accepts two input bits, and produceses two output bits, called 2:2 compressor 7 | - Full adders accepts three input bits, and produceses two output bits, called 3:2 compressor 8 | - All other arithmatics are built using adders so if you can build fast adders, you can build fast arithmatic circuits in general 9 | 10 | ![half-full-adders](imgs/adders/half-full-adders.png) 11 | 12 | ## Half adder 13 | - Half adders are more important in multiplier than they are in N-bit adders 14 | - sum gate is more complicated than the carry gate 15 | - The internsic time constant for the sum gate is double the time constant for the carry gate 16 | 17 | ![half-full-adders](imgs/adders/cmos-half-adder.png) 18 | 19 | ## Full adder 20 | - most of the building blocks use full adders rather than half adders 21 | - In N-bit adders even though the sum gate itself is more complicated than the carry gate, it's the carry that matters the most, it's the carry that scales the delay of the adder the most. 22 | - The internsic time constant for the sum gate is double the time constant for the carry gate 23 | 24 | ![full-adder-kmap-truth-table](imgs/adders/full-adder-kmap-truth-table.png) 25 | 26 | ![full-adder-cmos-sum](imgs/adders/full-adder-cmos-sum.png) 27 | ![full-adder-cmos-carry](imgs/adders/full-adder-cmos-carry.png) 28 | 29 | ## N-bit adders 30 | - For N-bit input we need N+1 bit output 31 | - first it needs half adder, rest of the bits needs full adder 32 | - we gonna assume there is a carry in coming from the outside, cause this N-bit adder can be used to build larger adders. 33 | - use full adder for the first bit 34 | 35 | ![N-bit-adder](imgs/adders/N-bit-adder.png) 36 | 37 | - For arithmatic circutis what we care about the most is speed and delay not area, not power dissipation 38 | - What we care about the most is how the delay behave as the number of bits increases 39 | 40 | - we assume there are registers at every input and output 41 | - assume all inputs are ready at time 0 42 | - Tc is the propagation delay for the carry gate, and Ts is the propagation delay for the sum gate 43 | - get the critical path (the longest delay between any input register and any output register) 44 | 45 | ### Ripple carry adders 46 | 47 | - For a 5-bit ripple carry adder S4 is ready the last 48 | 49 | ![ripple-carry-adder](imgs/adders/ripple-carry-adder.png) 50 | 51 | - delay = (N-1)*Tc + Ts 52 | - Its delay is pretty good for small inputs but it starts to increase for larger inputs and it increases linearly 53 | - Even though Tsum is larger than Tcarry, Tcarry is more important cause Tcarry represents the slope of delay curve when drawn againts input bits 54 | - So for a very large number of input bits which is the case in modern processers which uses wide buses the carry delay is gonna dominate 55 | 56 | ![ripple-carry-adder](imgs/adders/ripple-carry-adder-delay-slope.png) 57 | 58 | -------------------------------------------------------------------------------- /arithmetic-circuits/11-wallace-tree-multiplier.md: -------------------------------------------------------------------------------- 1 | # Wallace tree mutliplier 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16qnuE-nw0RkUq0IwRkzqyhD) playlist on arithmetic circuits. 3 | 4 | ## Introduction 5 | - Majority of effort expanded in multipliers is expanded in combining the summands to produces the product 6 | - partial products have to be combined at every bit position using either half adder or full adder 7 | - It doesn't matter the order of combining the bits in every bit position, you should add all the bits in the current bit position and that's all that we care about 8 | - How can we combine all of these bits so we can end up with one product word at the end in the least number of steps possible 9 | - using the only two available tools the half adder (2:2 compressor) and the full adder a (3:2 compressor) 10 | - so you can restate the mutliplication operation in terms of how to achieve maximum coverage of partial products inorder to reach a final product 11 | - the labeling on the partial products is not important 12 | - solid dots either present partial products or carry outs that came from previous bit positions 13 | 14 | ![partial-product-summation](imgs/wallace-tree-multiplier/partial-product-summation.png) 15 | 16 | ## Wallace tree 17 | - Approach to combine the bits to combining the bits which gives a fast multiplier, faster than the array multiplier 18 | - At every step it's gonna use the maximum number compressors to cover the maximum number of bits that it can cover 19 | - if it has 2 bits available it's gonna use a half adder 20 | - 3 bits available it's gonna use a full adder 21 | - 5 bits, a half adder and a full adder and so on 22 | - it'll only stop once every position has only two bits remaining 23 | 24 | ### Example 25 | - If we have 2 bits and everything before it only has 1 bit we don't use an adder. 26 | - If we have 3 bits and everything before it only 1 or 2 bits we use half adder 27 | - the reason why we didn't use HA or FA in some location is that it would have been redundant, as at the end all the results is gonna be fed to a fast adder so we keep 2 bits every operation 28 | 29 | ![wallace-tree-4x4-multiplier](imgs/wallace-tree-multiplier/wallace-tree-4x4-multiplier.png) 30 | 31 | ![wallace-tree-5x5-multiplier](imgs/wallace-tree-multiplier/wallace-tree-5x5-multiplier.png) 32 | 33 | ![wallace-tree-6x6-multiplier](imgs/wallace-tree-multiplier/wallace-tree-6x6-multiplier.png) 34 | 35 | ## Delay 36 | - The delay is controlled by the number of steps we have to go through before we endup with only two bits in every bit position 37 | - All these compression operations are being done in parallel, so the only the number of steps that really matter 38 | - we start with r0=number of bits of the multiplier r0=N 39 | - then we start calculating rj+1, r1,r2 and so on 40 | - we stop when r=2, at that point j is the number of steps we have to take 41 | - for r0=4, r1=3, r2=2, then we have two steps which can be confirmed from the figure 42 | - the delay grows logarithmically but it's not log base 2 43 | - it's not linear, and it's not log2(n) 44 | - but it's definitely faster than an array multiplier 45 | 46 | ![wallace-tree-delay-equation](imgs/wallace-tree-multiplier/wallace-tree-delay-equation.png) 47 | -------------------------------------------------------------------------------- /arithmetic-circuits/12-dadda-multiplier.md: -------------------------------------------------------------------------------- 1 | # Dadda multipliers 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16qnuE-nw0RkUq0IwRkzqyhD) playlist on arithmetic circuits. 3 | 4 | ## Introduction 5 | - One major critisim of [wallace tree mutlipliers](11-wallace-tree-multiplier.md) is area, 6 | - cause it tends to cover as many bits as possible at every single step without any attention to area or the number of full adders and half adders used. 7 | - which tends to produce very large multipliers 8 | - Dadda multipliers are a similar alternative which don't aim to cover the maximum number of bits at a single step, so they might leave some possibility uncovered 9 | - It's aim is to preserve the same number of steps as the wallace tree multipliers while reducing the number of full adders and half adders used 10 | - The algorithm in determening the number of half adders and full adders is alot more complicated 11 | - It's alot more complicated to determine how to perform coverage 12 | 13 | ## Dadda mutliplier 14 | - It begins with a certain sequence of integers that can be determined using 15 | - `dk+1 = floor( (3/2) dk)` , and `d1 = 2` 16 | - similar to wallace tree multipliers sequence because both have to do with the full adders being 3:2 compressors 17 | - Fixed number of sequence that don't have to be calculated everytime and can be stored 18 | - For an NxM multipliers we choose d 3 | * represents the masks that’ll be used in the fabrication, color coded masks 4 | * It’s a top view of the design 5 | * It’s the input to the fabrication 6 | ## reading layouts 7 | * Diffusion or active layers color coded in green (thin oxide). 8 | - Define areas where the wafer will be covered in a thin oxide in the locos process, where the sources and drains are 9 | - Intersection of n+ and p+ select masks with the active areas are the areas where we implant heavy donors or acceptors 10 | 11 | ![layout](imgs/layout/layout.jpg) 12 | * Poly layer (gate) color coded in red 13 | * Intersection between poly track and a diffusion or active track this is a transistor 14 | - In the self aligning process of LOCOS we fabricate poly silicon first (gate) and then we implant the sources and the drain 15 | - If this interaction happens outside the n-well in a single well process then that’s an n-mos 16 | - If this interaction happens inside the n-well in a single well process then that’s a p-mos 17 | * Look at how polysilicon and metal lines of the layout are used to connect nodes to make intelligent conclusions to determine the terminals of the mosfet (sources and drains) then determine where the supply and ground are. 18 | 19 | ![reading-layout](imgs/layout/reading-layout.jpg) 20 | ![reading-layout-vs-circuit](imgs/layout/reading-layout-vs-circuit.jpg) 21 | 22 | 23 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/10-asic-design-flow.md: -------------------------------------------------------------------------------- 1 | # Asic design flow 2 | source: [this](https://www.youtube.com/watch?v=e8rD04mBgtk&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=15&t=0s) video from the series on ASIC design flow 3 | 4 | ## ASIC design flow 5 | 6 | ![asic-std-design-flow](imgs/asic-design-flow/asic-std-design-flow.jpg) 7 | 8 | ## Exceptions to constraints 9 | - Sometimes there are paths in a circuit that stops the PAR tool from achieving closure, yet these paths are not true paths 10 | 11 | ### Multicycle path 12 | - Multi cycle paths are paths that exists between a register pairs, however the values that are supposed to be stored in the output registers aren’t supposed to be stored in one cycle, they can take multi cycle to settle 13 | - The case for configuration registers, sometimes set then we don’t reset them for a very long number of cycles. 14 | - if we insist that this path needs to be updated every cycle that’s gonna impose a condition on the PAR tool that does not need to be there 15 | 16 | ### False paths 17 | - False paths are paths that exist but any time (setup, hold) violations should be ignored because these paths don’t actually exist 18 | - The case in synchronizers that are used to synch data that comes from a clock domain to data that come to another clock domain 19 | - The intermediate path between those two registers which form a synchronizer is a false path, it doesn’t do anything, it’s expected and normal at this point for the data to be corrupt (metastability) 20 | 21 | 22 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/11-fpga.md: -------------------------------------------------------------------------------- 1 | # FPGA 2 | source: [this](https://www.youtube.com/watch?v=ysGYXWeA61I&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=16&t=0s) and [this](https://www.youtube.com/watch?v=isBQ4Icn3Gk&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=17&t=0s) video from the series on ASIC design flow 3 | 4 | ## FPGA 5 | - Array of cells like a standard cell library, but the difference is that all cells are identical in the FPGA, an FGPA cell is called a logic cell. 6 | - Each of these cells are reconfigurable, so that we can reconfigure the hardware to do something different 7 | 8 | ## Logic cells 9 | - A sample logic cell consists of lookup table, DFF, full adder, multiplexers, 10 | - Multiplexers reconfigure the cell 11 | - DFF, FA, LUT allow us to perform a bunch of functions based on multiplexers arranging 12 | - LUT allow you to perform any kind of combinational logic you want 13 | 14 | ![fpga-logic-cell](imgs/fpga/fpga-logic-cell.jpg) 15 | 16 | ## FPGA design flow 17 | - FPGA design flow is similar to ASIC design flow because FPGA have the same concept of a library 18 | - FPGA library is a library of configuration of logic cells, provided by the vendor, each entry describes a way to reconfigure the logic cell, or a bunch of logic cell and connect them together to perform a certain function 19 | - Logical model: truth table of the ip/ops 20 | - Programming model corresponds to the layout in std cell lib, the bits that we provide to the select lines of the MUXs so that we achieve the logic function in the truth table 21 | - Delay model: transition from each input changing to each output changing 22 | 23 | ![fpga-library-entry](imgs/fpga/fpga-library-entry.jpg) 24 | 25 | 26 | ## Tools flow 27 | - Utilization report: tells how many cells we used from FPGA 28 | - Synthesizer adds the multiplexer settings for each of the logic cells to the programming file 29 | - Programming file: bits we need to provide the FPGA to perform the function 30 | 31 | ![fpga-design-flow](imgs/fpga/fpga-design-flow.jpg) 32 | 33 | ## Place and route 34 | - FPGA consists of sub arrays called islands, connected by local switches 35 | - Logic cells in FPGA are arranged in the islands, communications between the cell in the same array is through local switch network (bunch of multiplexers) 36 | - Communication between different islands is through global switch (horizontal and vertical lines usually done by pass transistors enabled/disabled) 37 | - So the placement and routing tool will add to the programming file the controls that we need to provide to the switch fabric inorder to connect logic cells together 38 | - Once placement and routing done, we can do a post PAR simulation which is gonna include interconnect delays and we also have the programming file. 39 | 40 | ![fpga-place-and-route](imgs/fpga/fpga-place-and-route.jpg) 41 | 42 | ## Modern FPGAs 43 | - Most modern FPGA includes 44 | - specialized logic cells like multipliers 45 | - specialized rams to create large register files or large memories to avoid the use of distributed memory which is created by using only the FF in a logic cell 46 | - This increases the efficiency of the FPGA 47 | - Placement and routing in FPGA are not done with very tough constraints 48 | 49 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/3-std-cell-library.md: -------------------------------------------------------------------------------- 1 | # Standard cell library 2 | source: [this](https://www.youtube.com/watch?v=bmfOQSyVUWM&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=5&t=0s) video from the series on ASIC design flow 3 | 4 | ## standard cell library 5 | - Hand drawn layouts are usually used to create full custom asics and they are usually used in analog circuits, in digital circuits they are used in really critical parts of the circuits to speed them up, majority of digital circuits are of a category called standard cell asics. 6 | - They arrange the layout of std cells in neat rows 7 | - Standard cells are many layouts of basic building blocks (logic, arithmetic) 8 | - Have the same height so when arranged next to each other, they will fit in rows 9 | - Designer doesn’t specify the standard cell to use, he writes the description of the circuit in an HDL, and intermediate cad tools gonna translate this into the necessary std cells, once picked, the std cells need to be arranged and connected to each other. 10 | - CAN tools picks the std cells from a library which is a collection of std cells, the library is vendor specific (fabricator). 11 | - The std cell in the lib will be an entry that contains information about the std cell, about the logic function, a truth table for comb circuits and state transition table* for sequential circuits, and the layout and standard delay information (propagation delays) and information about parasitics 12 | - a state-transition table is a table showing what stat a finite-state machine will move to, based on the current state and other inputs 13 | 14 | 15 | ### Rules about std cells 16 | - Height of the cells constant and it’s called the pitch 17 | - So that when arranged in rows they will make neat rows 18 | - Metal 1 wire at the top for VDD and another one at the bottom for GND, both of a specific width 19 | - N-well (for pmos) needs to cover the top half of the std cell 20 | - Inputs and outputs in metal 1 21 | - The more complex the std cell the wider it would be, but height has to be the same 22 | - Example of an inverter 23 | 24 | ![std-cell-inverter](imgs/std-cells/std-cell-inverter.jpg) 25 | 26 | - Example of a two input nor gate 27 | 28 | ![std-cell-nor](imgs/std-cells/std-cell-nor.jpg) 29 | 30 | - Entry for an inverter library 31 | 32 | ![library-entry](imgs/std-cells/library-entry.jpg) 33 | 34 | 35 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/4-routing-and-power.md: -------------------------------------------------------------------------------- 1 | # Routing and power in standard cells 2 | source: [this](https://www.youtube.com/watch?v=9RLP8_WZNX8&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=6&t=0s) video from the series on ASIC design flow 3 | 4 | ## routing and power 5 | - Cells are arranged in rows that wouldn’t the same number of cells as their width differ depending on complexity, but their height (pitch) is the same 6 | - Cells ground and supply rails will abutt, and they form a complete ground and supply rail that runs across the entire standard cell row, same happens for the wells, they join together and form a big well together 7 | - Around the perimeter of the ASIC we have an empty piece of interior state which will be used to form ponding pads for the pins of the chip 8 | - In Between the rows of std cells we have metal tracks usually in the metal 1 layer used to do horizontal routing 9 | - When cells are arranged next to each other, sometimes the routing tool needs to leave an opening between the cells often used for routing 10 | - In such case the tool can needs to make a decision about how to handle the wells and the power supply and ground rails, either by completing them or routing them from both sides 11 | 12 | ![routing-gap](imgs/routing-and-power/routing-gap.jpg) 13 | 14 | ### Connecting cells together after arranged in the rows 15 | - Layers available for routing 16 | - Diffusion layer: not used for long range routing because of its resistance, can be used to create single diffusion strips as with the euler path within the cell 17 | - Poly silicon: used within the cell to connect the gates of transistors to save space, sometimes used for routing between cells in the same row only done with processes less than 3 metal layers otherwise we will never use polysilicon for routing outside the cell 18 | - Metal 1: used to route supply and ground, horizontal metal tracks between rows of std cells, and within the cell to connect circuits within the cell, inputs and outputs of the cell 19 | - Metal 2: local connection within the row when more than 3 metal layers are available, otherwise used for vertical connections inter-row (between rows) 20 | - Metal 3-N: generalized routing, long range routing, higher the layer longer the routing normally vertical 21 | - Highest metal layer used to distribute supply and ground. 22 | 23 | ![inter-cell-connection](imgs/routing-and-power/inter-cell-connection.jpg) 24 | 25 | ### Routing between cells 26 | When cells not in the same row using vertical tracks of metal, as well as the horizontal tracks available between cell rows using higher metal layers for vertical routing 27 | 28 | ![routing-between-cells](imgs/routing-and-power/routing-between-cells.jpg) 29 | 30 | ### Routing supply and ground 31 | - When we abutt cells together we expect them to form continues supply and ground rail which they do 32 | - However if we have a longer row of std cells the tool has to thicken the supply and ground rails for that row so the longer row the thicker the supply and ground rails because metal lines will have a resistive drop because of length of the rails and the current drawn from them, so the last cell in the row will see a lower value of the supply then the 1st cell of the row and a higher value of ground unless we make the wire wider 33 | 34 | ![routing-supply-and-ground](imgs/routing-and-power/routing-supply-and-ground.jpg) 35 | 36 | - Supply and ground are distributed using horizontal and vertical metal layers, the farthest point will see the lowest supply and highest ground, and highest drop so different organizations are made to guarantee minimum drop 37 | 38 | ![distributing-supply-and-ground](imgs/routing-and-power/distributing-supply-and-ground.jpg) 39 | 40 | 41 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/6-fixed-point.md: -------------------------------------------------------------------------------- 1 | # Fixed point 2 | source: [this](https://www.youtube.com/watch?v=HBQ9yjPS84A&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=10&t=0s) and [this](https://www.youtube.com/watch?v=v_E9IJ5EONg&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=11&t=0s) video from the series on ASIC design flow 3 | 4 | ## fixed point registers 5 | - System engineer that creates the application simulation on matlab, C have an infinite floating point (word length) arithmetic availability on general purpose processors, this isn’t the case for the asic or fpga, so we need to transform the floating point to fixed point 6 | - This transformation will produce a penalty that needs to be taken into consideration, so we need to simulate the system again using fixed point numbers and operations to know the impact of quantizing the floating point 7 | - In floating point the position of the fraction point is variable (floating) and determined based on the exponent, in the fixed point case it’s fixed so the integer part and the fraction part are fixed length 8 | ## generating a fixed point in a floating point machine 9 | - Use integer instead of float multiplying each number by the location of the fixed point (2^n) and after finishing the arithmetics divide by the (2^n) 10 | 11 | ![integer-instead-of-float](imgs/fixed-point/integer-instead-of-float.jpg) 12 | 13 | ## fixed point operations 14 | - Adding two N bits numbers might require N+1 bit to store the result 15 | - Adding M N-bits numbers requires additional log2(M) bits to store the result 16 | - So down the line we will need wider registers, and wider adders (slowers) 17 | - Solution to this is to use only N bits to store the result removing the MSB allowing the result to overflow, this is not viable cause it changes the result totally, it’s used in floating point arithmetics because it’s registers are huge so it will overflow only in extreme numbers 18 | - Another option is to accept that it needs N+1 bits this is viable but we have to understand that adders down the line are gonna need to be larger 19 | - Another solution is to remove the LSB but this will lead to quantization noise for odd numbers (1101) > (110) when restored (1100) this option is viable and used largely in multipliers 20 | ### quantization error (quantization noise) 21 | - Noise that results from truncating the result to a smaller register than the noiseless register 22 | - Much more apparent when dealing with multipliers, because a noiseless result in (N*N) bits multiplier needs 2N bits so the multipliers will keep growing down the line, the area grows quadratically with the number of input bits so this option is not viable 23 | - The metric used to calculate the noise is quantization signal to noise ratio (QSNR), it’s the power of the floating point number to the difference between fixed and floating power 24 | 25 | ![fixed-point-quantization-error](imgs/fixed-point/fixed-point-quantization-error.jpg) 26 | 27 | - P (the number of bit to truncate ) is chosen based on the application and the performance metrics 28 | 29 | 30 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/7-synthesis.md: -------------------------------------------------------------------------------- 1 | # Synthesis 2 | source: [this](https://www.youtube.com/watch?v=IxcAvkb2EoY&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=12&t=0s) video from the series on ASIC design flow 3 | 4 | # Synthesis 5 | - Step at which the design starts to become hardware 6 | 7 | ## Design flow 8 | - High level modeling 9 | - Fixed point modeling --> Fixed point simulation 10 | 11 | ### RTL modeling --> behavioural simulation 12 | - Behavioural simulation is bit-accurate and cycle-accurate 13 | - Functional checking. 14 | - Missing timing information (delays) 15 | - Output from behavioural simulation should match the output from fixed point simulation bit-by-bit 16 | 17 | ### Synthesis --> post synthesis simulation 18 | - Synthesizer uses the library and the VHDL model 19 | - Interprets the VHDL model in terms of building blocks exists in the library 20 | - Its output is still a vhdl file called a netlist, contains instantiations of standard cell that exist in the library and the connections of these files with each other 21 | - Synthesis (behavioural VHDL to structural VHDL derived entirely from the library) 22 | - Output have information from the library about delays so this allows the synthesizer to calculate critical path delay, and delays of all paths 23 | - post synthesis simulation is simulation like behavioural simulation but contains information about gate delays 24 | 25 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/8-place-and-route.md: -------------------------------------------------------------------------------- 1 | # Place and route 2 | source: [this](https://www.youtube.com/watch?v=8w0UEjMBYT8&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=13&t=0s) video from the series on ASIC design flow 3 | 4 | ## place and route 5 | - Most critical step in the design flow 6 | - After synthesis we have a netlist (vhdl file consists of structural connection of standrad cells from the library) 7 | 8 | ## Next steps 9 | ### Partitioning and floorplanning 10 | - Partitioning: Is the design a singular unity or can be partitioned into blocks that are logically connected to each other 11 | - Floorplanning: Once we have decided on the partitions we have the real state of the asic and we have to decide which areas of the asic are dedicated to which partitions 12 | - Whether partitioning and floorplanning makes sense is related to the next step place and route 13 | 14 | ### Place and route --> Post PAR(place and route) simulation 15 | - Take the layouts of each of the standard cells we are using, then place them in a specific locations in the asic, then route them to each other using metal layers so that we have the overall layout of the entire circuit 16 | - Placement and routing are inseparable and iterative operations 17 | - The tool function in constraints 18 | - Pin placement constraints 19 | - Aspect ratio of the chip 20 | - Area and speed 21 | - Tool keeps trying (depending on the optimization effort specified) to find a layout that gives a positive or zero slacks on all paths to report closure 22 | - If the tools gives up it’ll report failure to close for the designer and It’ll report all the slacks in the circuits specifically the -ve slacks 23 | - Outputs can be: closure, failure (setup time violations, -ve slacks). 24 | - If there is a hold time violation tool usually solve it by adding buffers 25 | - Failure can be solved by relaxing the constraints, increasing the optimization effort, revisiting the design 26 | - Post PAR simulation is bit-accurate, cycle-accurate, models gate delays and interconnect delays 27 | 28 | 29 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/9-drc-lvs.md: -------------------------------------------------------------------------------- 1 | # DRC and LVS 2 | source: [this](https://www.youtube.com/watch?v=9t0xb5TmIs0&list=PLyWAP9QBe16qWQzq_IQtGKO9Yz8QvCWvY&index=14&t=0s) video from the series on ASIC design flow 3 | 4 | ## DRC and LVS 5 | - After placement and routing we end up with a design that has achieved closure, then we have a layout that reading for taking out (sent to fabrication facility) 6 | ## Parasitic extraction 7 | - Extract the effects of parasitics on delay from the overall layout once everything is connected together. 8 | - the impact of these parasitics on delay is gonna be stored on a file called standard delay format file, it’s then fed back to the post PAR simulation to do post layout simulation 9 | - Post layout simulation is basically post PAR simulation with the enclosure of parasitics (capacitances) extracted after parasitic extraction, this is the simulation that gives the best estimate of delays that we can see, if this passes then it’s unlikely the chip would get back 10 | ## Design rules check 11 | - Once parasitic extraction is done we have to do DRC (design rules check), automatic process done by the tool and checks whether every single layer in the layout obeys every single rules in the design rules, if found violation, reports to the designer 12 | 13 | ### Design rule violation in std cells 14 | - Why design rule violations might found while the layout consists of standard cells? 15 | - std cells come from the vendor that makes the design rules, so they won’t have violations 16 | - When you attach cells together, there can be desgin rule violations. 17 | - can be due to abutment of the cells to each other 18 | - Usually results from the distribution of power, and from routing and from the clock network 19 | - More likely to be found in the metal layers than in the lower layers 20 | 21 | ## layout versus schematic 22 | - Final step is LVS (layout versus schematic) 23 | - Does the layout does the function that we intended to do in the first place 24 | - All previous simulations are performed on the vhdl netlist, we don’t know if the layout corresponds to the vhdl that we are simulating 25 | - Lvs ensure that it does the function 26 | - It scans the layout, whenever it finds and intersection for diffusion or body for example it judges that there is a transistor, so it’ll map where the transistors are, which transistors are connected to which and form these into logic gates 27 | - Then it’ll break down everything into logic equations, simplify these logic equations, so that it has equations that describes how the circuit functions 28 | - Then it’ll take the reference vhdl netlist, simplify its logic equations 29 | - Compare the result logic equations, if both match then lvs passes, if it doesn't then there is a problem, and lvs will tell you where the problems are 30 | - Finally if all tests pass, then the design is ready for tapeout, send the files to the fab facility. 31 | - usually design is sent in the form of GDS 2 files (graphical database system), simple format, text file has head of a certain format 32 | - Bulk of the gds2 file is a set of vertices of where every block starts and ends, automatically generated from the layout (gds2 <--> 3d layout) 33 | 34 | 35 | > *last modified 15/04/2020* -------------------------------------------------------------------------------- /design-flow/README.md: -------------------------------------------------------------------------------- 1 | # Design Flow 2 | 1. [Layout](1-layout.md) 3 | 2. [Stick diagram](2-stick-diagram.md) 4 | 3. [standard cell library](3-std-cell-library.md) 5 | 4. [Routing and power](4-routing-and-power.md) 6 | 5. [Design rules](5-design-rules.md) 7 | 6. [Fixed point](6-fixed-point.md) 8 | 7. [Synthesis](7-synthesis.md) 9 | 8. [Place and route](8-place-and-route.md) 10 | 9. [Design rule check and layout vs schematic](9-drc-lvs.md) 11 | 10. [Asic design flow](10-asic-design-flow.md) 12 | 11. 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(area or circuit complexity [gate equivalent] ) 6 | 2. cycles per data item Γ (# of computation cycles separates releasing/accepting 2 data items) 7 | 3. Longest path delay tlp (time required for data to propagate along longest ocmbinational path) (circuit should settle to steady state withing single computation period tcp ) (tlp <= tcp) (tcp=tclk) 8 | 4. Time per data item T (time between releasing 2 data items) (T = Γ * tcp) 9 | 5. Data throughput Θ = 1/T (data items process per time unit) 10 | 6. Size–time product AT (H.W resources spent to obtain certain throughput) 11 | 7. Latency L (number of computation cycles from a data item being entered into a circuit until the pertaining result becomes available at the output) 12 | 8. Energy per data item E (amount of energy dissipated in carrying out some given computation on a data item.) 13 | 14 | ## DDG (Data dependency graph) 15 | 1. Decomposing function f into a sequence of subfunctions that get executed 16 | - one after the other in order to reuse the same hardware as much as possible. 17 | - iterative decomposition: resource sharing through step-by-step execution. 18 | - The computation of function f is broken up into a sequence of d subtasks which are carried out one after the other. (effective when f can be separated into multiple nearly identical subfunctions) 19 | 2. Pipelining of the functional unit for f to improve computation rate by cutting down combinational depth and by working on multiple consecutive data items simultaneously. 20 | - cutting combinational depth into several separate stages of approximately uniform computational delays by inserting registers in between, The combinational logic between two subsequent pipeline registers is designed and optimized to compute one 21 | specific subfunction. 22 | - shimming registers: registers used to add latency in one of the pathes for multiple feedforward path pipelining 23 | - coarse grain: complex fn, better performance in pipelining - fine grain 24 | 3. Replicating the functional unit for f and having all units work concurrently. 25 | - Concurrency is obtained from providing q instances of identical functional units 26 | for f and from having each of them process one out of q data items in a cyclic manner. To that end, two synchronous q-way switches distribute and recollect data at the chunk’s input and output respectively. 27 | 4. Time sharing: parallel data streams undrgo processing, pool hardware by having a single functional unit process the parallel data streams one after the other in a cyclic manner (referred to as multiplexing or as resource sharing in the context of 28 | circuit design) 29 | 5. Associativity transform (Algebric transform) depends on the operation 30 | 31 | -------------------------------------------------------------------------------- /memories/README.md: -------------------------------------------------------------------------------- 1 | # Memories 2 | 3 | 1. [Memories](1-2-memories.md) 4 | 2. [NOR roms](3-4-nor-roms.md) 5 | 3. [NAND roms](5-6-nand-roms.md) 6 | 4. [Non volatile memories](7-non-volatile-memories.md) 7 | 5. [EPROM and EEPROM](8-eprom-eeprom.md) 8 | 6. [Flash](9-10-flash.md) 9 | 7. [SRAM](11-12-sram.md) 10 | 8. [Sense amplifier](13-sense-amplifier.md) 11 | 9. [Self timing in sram](14-self-timing-in-sram.md) 12 | 10. [DRAM](15-16-17-dram.md) 13 | 11. [Column decoders](18-19-column-decoder.md) 14 | 12. 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[General RTL notes](general-rtl.md) 3 | 2. [Y Chart](y-chart.md) 4 | 5 | -------------------------------------------------------------------------------- /rtl/general-rtl.md: -------------------------------------------------------------------------------- 1 | # General RTL advice 2 | source: multiple sources 3 | 4 | ## Tips 5 | - no feedback from a combinational circuit, put a register w clock and feedback it 6 | 7 | - don't use a gate output as a clock (clock skew, affected by gates propagation delays), same clock for all (synchronization)-> use MUX in the data path 8 | 9 | - don't generate a pulse using gate delays (don't cascade buffers/not gates to get a pulse after a certain amount of time ), ->use clocked flipflops instead to get output after # of clocks 10 | 11 | - use synchronous circuits to eliminate glitches, unwanted narrow pulse caused by propagation delays of circuits, ->use a clocked flipflop at the output to get the output depending on the clock. 12 | 13 | - use only synchronous counters and not ripple counters. 14 | 15 | - It is illegal to nest modules, i.e., write module within a module. (compilation error), instead call a module within a module 16 | 17 | ``` 18 | module module_1 (// List the first module I/Os here) ; 19 | 20 | // Declare the first module I/Os, wires, and registers. 21 | 22 | // Write the required combination and sequential 23 | 24 | // logic for the first module. 25 | 26 | module_2 U1 (// List second module I/Os here, calling ports by name) ; 27 | 28 | module_3 U2 (// List third module I/Os here, calling ports by name) ; 29 | 30 | // Call other modules, if any. U1, U2, etc. are instantiations. 31 | 32 | // Note the presence of ‘;’ at the end of each of the statements. 33 | 34 | endmodule // This signifies the end of module_1. Note that there is no space between ‘end’ and ‘module’. 35 | ``` 36 | 37 | - separate combinational and sequential circuits, for ex: always block for AND gate depending on A,B (always @(A or B)), and another clocked always block for the D flip flop to output the output 38 | 39 | - for a flipflop if you set Q = d, Q_n = !d; this will produce two flipflops instead,use inverter: assign Q_n = ! Q; !d 40 | 41 | - Whatever signals are used in an ‘always’ block, they are declared as registers. 42 | 43 | - if statement is a MUX, if else is not specified, a latch is created to hold the previous value (latch i/p: signal, clock:SEL). Latches are inferred unless all signals are assigned in all branches. 44 | 45 | - Avoid all latches in your design since they pass on glitches in the circuit. 46 | 47 | - it would be advisable to restrict the number of ‘if–elseif–else’ statements to four or five based on experience. In designs, where this thumb-rule is exceeded, one may explore the possibility of using ‘case’ statements in lieu of ‘if–else if’ statements. 48 | 49 | - ‘case’ statements must be used if conditions are mutually exclusive. (uses a signle redundant variable) 50 | 51 | ## Tools directives 52 | - full_case , parallel_case directives 53 | - When adding "full_case" or "parallel_case" directives to a case statement, 54 | - the directives are added as a comment immediately following the case expression at the end of the case statement header and before any of the case items on subsequent lines of code. 55 | 56 | ### full_case 57 | `case (SELECT) // synopsys full_case;` 58 | - indicates that all cases are specified even if they don’t consider all possibilities. 59 | - one-hot assignment (i.e., only one ‘1’ entry in the signal such as SELECT = 010) is shown first, change only 1 bit 60 | 61 | ### parallel_case 62 | `case (SELECT) // synopsys parallel_case;` 63 | - indicates that all cases listed are mutually exclusive to prevent priority encoded logic.(latches created) 64 | 65 | ### combination 66 | `case (SELECT) // synopsys parallel_case full_case` 67 | - latches may be eliminated and a MUX created instead,The chip area is considerably lower in this case. 68 | 69 | 70 | -------------------------------------------------------------------------------- /rtl/imgs/y-chart/blocking-non-blocking.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/blocking-non-blocking.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/checklist-of-rtl-code.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/checklist-of-rtl-code.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/comb-loop.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/comb-loop.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/fsm-deadlock.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/fsm-deadlock.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/implicit-latches.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/implicit-latches.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/linting.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/linting.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/multiple-drivers.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/multiple-drivers.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/rtl-vs-behav-model.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/rtl-vs-behav-model.png -------------------------------------------------------------------------------- /rtl/imgs/y-chart/y-chart.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/rtl/imgs/y-chart/y-chart.png -------------------------------------------------------------------------------- /rtl/y-chart.md: -------------------------------------------------------------------------------- 1 | # Y-chart and RTL tips 2 | source: [this](https://www.youtube.com/watch?v=voi0oZI5Tug&list=PLFhizsGPFKt8gz-bYlKMDCgBKwxMc33H2&index=20&t=0s) video 3 | 4 | ## Gajski-Kuhn chart 5 | 6 | ![y-chart](imgs/y-chart/y-chart.png) 7 | 8 | ![rtl-vs-behav-model](imgs/y-chart/rtl-vs-behav-model.png) 9 | 10 | ## Linting 11 | - After writing RTL code, run a linting tool on the code to check for RTL style checks 12 | - Synopsys spyGlass, Mentor Autocheck, questasim 13 | 14 | ![linting](imgs/y-chart/linting.png) 15 | 16 | ## Points to check in RTL code 17 | 18 | ![checklist-of-rtl-code](imgs/y-chart/checklist-of-rtl-code.png) 19 | 20 | ## Blocking and non blocking assignments 21 | - DONOT MIX BLOCKING AND NON BLOCKING WITHIN SAME ALWAYS BLOCK 22 | 23 | ![blocking-non-blocking](imgs/y-chart/blocking-non-blocking.png) 24 | 25 | ## COMB_LOOP 26 | - feedback in combinational logic 27 | 28 | ![comb-loop](imgs/y-chart/comb-loop.png) 29 | 30 | ## INFERRED LATCHES (implicit) 31 | - Latches makes problems in timing constraints 32 | 33 | ![implicit-latches](imgs/y-chart/implicit-latches.png) 34 | 35 | ## Multiple Drivers 36 | 37 | ![multiple-drivers](imgs/y-chart/multiple-drivers.png) 38 | 39 | ## FSM DEADLOCK 40 | - Fsm is stuck in one state 41 | 42 | ![fsm-deadlock](imgs/y-chart/fsm-deadlock.png) 43 | -------------------------------------------------------------------------------- /testing/5-stuck-at-fault-model.md: -------------------------------------------------------------------------------- 1 | # Stuck at fault model 2 | - Source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16qiSMkBcAnUMxFagLIJzmv1) playlist on Testing. 3 | 4 | ## Introduction 5 | - Fault model applied at the logic level 6 | - Allows us to design test vectors 7 | - Allows us to determine wether the test pattern is sufficient to detect all the possible faults 8 | - Allows us to project fault coverage statistics 9 | 10 | ## Model 11 | - It looks at every single node of the circuit and says that said node could have three state 12 | - normal 13 | - stuck at logic zero 14 | - stuck at logic one 15 | - In the example node `F` is stuck at logic zero 16 | 17 | ![stuck-at-zero-example](imgs/stuck-at-fault-model/stuck-at-zero-example.png) 18 | 19 | - When we say that a node in a logic circuit is stuck at zero or one we aren't actually implying anything about the underlying defect that caused the fault 20 | - node `F` stuck at zero doesn't mean that `F` is shorted to ground 21 | - It's just a way to represent defects, and it could represent alot of defects, and it doesn't imply anything about actual connections that happen in the finished chips 22 | 23 | ## Example 24 | - OR gate with 2 inputs and 1 output, It has `N=3` nodes 25 | - Number of faults that can occur = `K*N` where `K` is the number of faults that can occur at every node 26 | - In stuck at fault model we have 2 faults per node `K=2` 27 | - six possible faults that can occur for this circuit 28 | - We will assume that there is only one stuck-at fault happening 29 | - depends on the fact that the probability of a single fault occuring is much higher than the probability of multiple faults happen 30 | - The table contains the normal output, and the output when each of the faults occur 31 | - This table allows us to see which inputs can be used to detect which faults 32 | - This can be done be comparing each of the columns of the table with the correct output of the circuit 33 | - Applying inputs `A=0,B=0` isn't useful in trying to identify the presence of `F` stuck at zero because the correct output matches the output when stuck 34 | - on the other hand applying any of the other three inputs of the truth table is gonna expose `F` stuck at zero because the output deviates from the true output in all three cases 35 | - This is called an [error](2-defects-faults-errors.md) because it's an observation that deviates from the true output and it exposes an underlying fault 36 | - `A` stuck at zero will only be exposed when applying the inputs `A=1,B=0` 37 | - It's useful to look at the minimum set of test vectors which can expose all the possible faults that can occur in the circuit 38 | - This is not necessarily the entirety of the truth table 39 | - When we try to get the minimum set that exposes all the faults we start by faults that are uncovered by only a single test `F fault at one` then we start to move to faults that are uncovered by more 40 | - In the example test vector `T={00,10,01}` we don't need to apply input `11` because the only fault exposed by applying input `11` is `F stuck at zero` which is also exposed by applying `{01,10}` 41 | - Distinguishing which fault occured through the test vector is possible in some cases and isn't possible in others 42 | - If we applied test vector `01` and a fault occured this can be due to `F stuck at zero` or `B stuck at one`, this can be known by applying test `10` if a fault happens then it's `F stuck at zero`, if no fault happens then it's `B stuck at one` 43 | - Faults `F, A, B stuck at one` have the same observation so they can't be distinguished if a fault happens 44 | 45 | ![or-gate-stuck-at-model-example](imgs/stuck-at-fault-model/or-gate-stuck-at-model-example.png) 46 | -------------------------------------------------------------------------------- /testing/README.md: -------------------------------------------------------------------------------- 1 | # Testing and Design for Testabiltiy 2 | 3 | 1. [Design for testability](1-design-for-testability.md) 4 | 2. [Defects, faults and errors](2-defects-faults-errors.md) 5 | 3. [Test design and fault coverage](3-test-design-fault-coverage.md) 6 | 5. [Stuck at fault model](5-stuck-at-fault-model.md) 7 | 6. [Stuck open/short fault model](6-stuck-open-short-fault-model.md) 8 | 7. [Scan Technique](7-8-scan-technique.md) 9 | 8. [Built-in self test](9-10-built-in-self-tests.md) 10 | 9. [Testing memories](11-12-testing-memories.md) 11 | 10. [IC packaing](13-14-ic-packaging.md) 12 | 11. [PCB design fabrication](15-pcb-design-fabrication.md) 13 | 12. [Boundry scan and JTAG](16-boundry-scan-jtag.md) 14 | 13. [Glitches and logical hazards](17-glitches-logical-hazards.md) 15 | 14. [Static Hazarads](18-19-20-21-static-hazards.md) 16 | 15. [Dynamic Hazarads](23-dynamic-hazards.md) 17 | 16. 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[this](https://www.youtube.com/watch?v=hFGq3XdtgeM&list=PLFhizsGPFKt8gz-bYlKMDCgBKwxMc33H2&index=19&t=0s) tutorial on static timing analysis 3 | 4 | ## hold and setup time 5 | - setup time is associated with the clock 6 | - hold time is associated with the data 7 | - if hold time isn't satisfied (violated) insert buffers 8 | - hold time violations must be fixed 9 | 10 | ![hold and setup times](imgs/sta/hold-setup-time.png) 11 | 12 | ![setup time](imgs/sta/setuptime.png) 13 | 14 | ![hold time](imgs/sta/holdtime.png) 15 | 16 | 17 | ## Detecting problems in design flow 18 | 19 | ![IC Design problem detection](imgs/sta/problem-detection.png) 20 | 21 | ![Timing simulation](imgs/sta/timing-simulation.png) 22 | 23 | ## static timing analysis 24 | 25 | - Timing Paths 26 | - Blue: data path 1,2 Asynchronized, 3 synchronized 27 | - Crayn: clock path (clock with combinational logic) 28 | - violet : reset path 29 | 30 | ![Timing paths](imgs/sta/timing-paths.png) 31 | 32 | ## Example 33 | ### 1) Setup Time (max delays) 34 | - Clk delays = 0, 35 | - FF1 propagation delay =0.68 (for d to get to q it needs 0.68time) ->total path till now d->q=0.68 36 | - G2 propagation delay=4.68(from i/p start to get result)-> total path till now=4.68+0.68=5.36 37 | - So input at FF2 d will arrive at 5.36 time, 38 | - F2clock arrives at 5, and its setup time(time required for the input to be present before the clock) is -0.56 (input should be present before the clock arrives by0.56), 39 | - So input at d should be present at 5-0.56=4.44 40 | - But it is present at 5.36, so we have setup time violation (slack) by 4.44-5.36=-0.92 41 | 42 | ![STA example setup time violation](imgs/sta/ex-setuptime.png) 43 | 44 | #### Solution: 45 | 1- setup time violations associated with the clock, so we can increase F2 clock time 46 | 2- change G2 cell, it takes most of the time, replace it with another cell with less max delay 47 | 48 | ![STA example setup time violation fix](imgs/sta/ex-setuptime-sol.png) 49 | 50 | ### 2)Hold Time(min delays) 51 | - FF1 minimum time d->q, (minimum possible time for the data to change)=0.28 52 | - G2 minimum time i/p->Y,=0.28 ->total minimum path time till now=0.56 53 | - So data at FF2 input minimum hold time required = 0.96 54 | - But minimum possible arrival time (minimum time data could change in) is 0.56 55 | - So we have a hold time violation 56 | 57 | ![STA example hold time violation](imgs/sta/ex-setuptime.png) 58 | 59 | #### Solution: 60 | - Add a buffer to add more delays at the FF2 input 61 | - But this may corrupt setup time check so do it again and repeat 62 | - Then do equivalence and functional checks again and repeat 63 | 64 | ![STA example hold time violation fix](imgs/sta/ex-holdtime-sol.png) 65 | 66 | -------------------------------------------------------------------------------- /verilog/README.md: -------------------------------------------------------------------------------- 1 | # Verilog 2 | 3 | 1. [Verilog notes](verilog-notes.md) 4 | 2. [Sequential logic](sequential-logic.md) 5 | -------------------------------------------------------------------------------- /verilog/imgs/blocking-assignment.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/verilog/imgs/blocking-assignment.png -------------------------------------------------------------------------------- /verilog/imgs/non-blocking-assignment.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ahegazy/vlsi-notes/ea75f670c2ece49113a22caaae41852db166c474/verilog/imgs/non-blocking-assignment.png -------------------------------------------------------------------------------- /verilog/sequential-logic.md: -------------------------------------------------------------------------------- 1 | # sequential circuits 2 | 3 | source : [Lecture 7](https://www.youtube.com/watch?v=NfqgM3QbiVk&list=PL5Q2soXY2Zi8J58xLKBNFQFHRO3GrXxA9&index=7)- Design of Digital Circuits 4 | 5 | 6 | ## Blocking and non Blocking assignment 7 | - the symbol ‘<=’ is used. It is known as a non-blocking statement, whereas in ‘assign’ statements, we use ‘=’ symbol called the blocking statement. 8 | - In an ‘always’ block, if we use ‘=’ instead of ‘<=’, the compiler tool will complain. 9 | - '<=' non-blocking statement, to indicate a register sequential circuit 10 | - '=' blocking statement, to indicate a combinational circuit 11 | 12 | 13 | ### Non-blocking (<=) 14 | ``` 15 | always @ (a) 16 | begin 17 | a <= 2’b01; 18 | b <= a; 19 | // all assignments are made here 20 | // b is not (yet) 2’b01 21 | end 22 | ``` 23 | - All assignments are made at the end of the block 24 | - All assignments are made in parallel, process flow is not-blocked 25 | 26 | ![Non blocking assignment](imgs/non-blocking-assignment.png) 27 | 28 | ### Blocking (=) 29 | ``` 30 | always @ (a) 31 | begin 32 | a = 2’b01; 33 | // a is 2’b01 34 | b = a; 35 | // b is now 2’b01 as well 36 | end 37 | ``` 38 | 39 | - Each assignment is made immediately 40 | - Process waits until the first assignment is complete, it blocks progress 41 | 42 | ![blocking assignment](imgs/blocking-assignment.png) 43 | 44 | 45 | ### Why use (Non)-Blocking Statements 46 | - There are technical reasons why both are required 47 | - It is out of the scope of this course to discuss these 48 | 49 | - Blocking statements allow sequential descriptions, more like a programming language 50 | 51 | - If the sensitivity list is correct, blocks with non-blocking statements will always evaluate to the same result 52 | - This may require some additional iterations 53 | 54 | ### Rules for Signal Assignment 55 | 1- Use always `@(posedge clk)` and non-blocking assignments (<=) to model synchronous sequential logic 56 | ```always @ (posedge clk) 57 | q <= d; // non-blocking``` 58 | 59 | 2- Use continuous assignments (assign) to model simple combinational logic. 60 | `assign y = a & b;` 61 | 62 | 3- Use `always @ (*)` and blocking assignments (=) to model more complicated combinational logic. 63 | 64 | 4- You cannot make assignments to the same signal in more than one always block or in a continuous assignment 65 | 66 | ------ 67 | 68 | ## Notes 69 | - each of the ‘if’ or ‘else if’ statements would create a nested two input multiplexer and, thereby, slowing the system operation. From experience, we suggest that you don’t exceed four or five such nesting. Smaller 70 | 71 | - If you have many signal outputs (registers) in one sequential ‘always’ block, debugging the code will be a frustrating experience. It is, therefore, highly recommended that one should have only one register in one ‘always’ block pipelining 72 | 73 | - The logic must normally be put outside the always block using ‘assign’ statements for improving the speed of operation 74 | 75 | ``` 76 | `define S0 3'd0 // Define a macro 77 | case(state) 78 | `S0: 79 | begin 80 | // 81 | end 82 | default: 83 | // 84 | end // end case 85 | ``` -------------------------------------------------------------------------------- /verilog/verilog-notes.md: -------------------------------------------------------------------------------- 1 | # verilog random notes 2 | - source: different sources 3 | 4 | ## Combinational and sequential circuits 5 | - Combinational circuit 6 | - AND, OR , etc ... immediate response, propagation delay 7 | - Sequential circuit 8 | - combinaltional + registers : flip flops 9 | - op = fn(input, previous state) 10 | - synchronous circuits 11 | 12 | ## assign 13 | - assign x = y ; //buffer 14 | - assign x = a&b ; //and gate 15 | - ! : inversion (NOT) 16 | - ~ : multi-bit inversion bitwise (NOT) 17 | 18 | ## always block 19 | ``` 20 | always @(A or B or C or F10) // whenever A,B,C or F10 change, go down 21 | begin 22 | F9 = (A&B)|(B&C)|(C&A) ; //AB+BC+CA // brackets () guide the synthesis tool 23 | F10 = {A, B, C} ; //concatenation , A: MSB, C: LSB 24 | F10 = {A,B,C, 3{0}}; // same as ^ but add 3 zeros at LSB 25 | F12 = F10 << 2; left shift, put 2 zeros at LSB 26 | end // concurrent statements 27 | ``` 28 | 29 | ## Eight input MUX 30 | - code using ‘always’ and ‘case’ statements. 31 | 32 | ``` 33 | // Fastest possible hardware implementation. 34 | always @ (A or B or C or I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7) 35 | begin 36 | case ({A, B, C}) 37 | 3'b000: mux8 = I0 ; // Read the input addressed by ABC 38 | 3'b001: mux8 = I1 ; // and output the same to mux8. 39 | 3'b010: mux8 = I2 ; 40 | 3'b011: mux8 = I3 ; 41 | 3'b100: mux8 = I4 ; 42 | 3'b101: mux8 = I5 ; 43 | 3'b110: mux8 = I6 ; 44 | 3'b111: mux8 = I7 ; 45 | default: mux8 = 0 ; // The value can be I0 or any other. 46 | endcase 47 | end 48 | ``` 49 | 50 | ## FULL ADDER 51 | - Behavioral realization 52 | 53 | ``` 54 | assign sum_total = (A + B) + C; // parenthesis: synthesis tool efficient optimization 55 | ``` 56 | - Data flow structure 57 | ``` 58 | assign sum = (A^B) ^C ; // Realize sum. 59 | assign carryo = (A&B)|(B&C)|(C&A) ; // Realize carry out, AB + BC + CA. 60 | ``` 61 | 62 | ## Misc 63 | - Gates that can be used in a structural design are ‘nand’, ‘nor’, ‘xor’, ‘xnor’, ‘buf’, and ‘not’. 64 | - this structure can be effectively used for the implementation of tri-state buffers/inverters such as the following: 65 | 66 | - bufif0 u1 (out, in, sel) ; // out = in if sel = 0, otherwise out is tri-stated 67 | - bufif1 u2 (out, in, sel) ; // out = in if sel = 1, otherwise out is tri-stated 68 | - notif0 u3 (out, in, sel) ; // out = ! in if sel = 0, otherwise out is tri-stated 69 | - notif1 u4 (out, in, sel) ; // out = ! in if sel = 1, otherwise out is tri-stated 70 | 71 | -------------------------------------------------------------------------------- /vhdl/1-design-philosophy.md: -------------------------------------------------------------------------------- 1 | # Design philosophy 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Hardware design philosophy 5 | - VHDL describes hardware, it contains alot of syntax that looks alot like programming 6 | - It’s not a programming paradigm, it’s a description of hardware connections, where it’s and where it lies 7 | 8 | ## Programmnig vs hardware wires connection 9 | - `T=A;A=B;B=T` VS `T<=A;A<=B;B<=T` 10 | - In programming this implemented sequentially 11 | - In hdl this describes a short circuits between three nodes A,B,T, the three statements are implemented concurrently 12 | 13 | ## Sequence 14 | - Sequence in VHDL is the exception not the rule, used to create registers, memories, and we deal with it very carefully 15 | - Everything is implemented in hierarchical fashion in vhdl, and using (instantiating) modules multiple times are very important parts of the design philosophy 16 | 17 | ## Design wrapper 18 | - The highest level of the design (wrapper) should include subdesigns or modules only, it should contain instantiations of big modules or big blocks only. 19 | - A glue logic (wrapper contains subsystems and random small logic between them) is a bad design. 20 | - A better approach is to gather the glue logic on its own subsystem, or to fold it in the subsystems. 21 | 22 | ## Synthesizability and good code/design 23 | - Synthesizable code is code that passes through the synthesis without errors 24 | - Alot of the vhdl syntax is unsynthesizable, it’s easy to pinpoint and tools catch it 25 | - The problem is not with synthesizability, the problem is with the bad code that passes through the synthesis and gives you bad results 26 | - Good code is not only code that’ll pass synthesis, but also will produce predictable results after synthesis 27 | - When we write VHDL the main thing to think about is do we know what kind of hardware would result from the code we are writing? If we can guess then it's a good code. 28 | - Even Though the syntax allows you to code hardware you don’t know you shouldn’t do it 29 | 30 | ## up next 31 | Next modules are about understanding how to use the syntax safely and efficiently. -------------------------------------------------------------------------------- /vhdl/10-process-transactions-events.md: -------------------------------------------------------------------------------- 1 | # process, transactions and events 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Process 5 | - Process allows executing sequence of events so you can have memory elements 6 | - Statements within processes execute in sequence. 7 | - Their main use is to declare registers and latches and memories 8 | - When the simulation starts, any process will execute at least once 9 | - There are different ways to control how often a process is executed like sensitivity list and wait statement 10 | 11 | ### Sensitivity list 12 | - A sensitivity list is a list of signals that lie in the parenthesis after the process statement, it’s a list of signals that sensitize the process, cause the process to execute whenever they change, so a process will execute once after simulation starts, and not gonna execute again until a change happens on a signal of the sensitivity list 13 | - In the example, R2 doesn’t take the current value of R1, it takes the previous value, because when R0 is assigned to R1 a transaction happened not an event 14 | 15 | ``` 16 | process_label: process(R0) -- R0 is in the sensitivity list 17 | begin 18 | R1 <= R0; 19 | R2 <= R1; 20 | R3 <= R2; 21 | end process; -- change happens here 22 | ``` 23 | ![transaction-to-event](imgs/process-transaction-event/transaction-to-event.png) 24 | 25 | ## Transactions and events 26 | - Event is an actual change in the value of the signal 27 | - When the value of a signal changes, in a register, of a wire that’s an event 28 | - Transaction is just a scheduling of an event, an intend to change the value of a signal 29 | - Whenever you make a signal assignment in a process that causes a transaction not an event, so the value of the signal doesn’t change. 30 | - A transaction turn into an event at the end of the process -for now- 31 | - Updating transactions to events takes zero times, it takes a nominal delay which is delay that takes place within the simulator, it doesn’t take any real delay, it’s an artifact of the simulator but it’s necessary because without having a distinction between transactions and events you can't have registers and latches 32 | ## fully populated sensitivity list 33 | - If the sensitivity list of the process is fully populated, having (R0, R1, R2), when R0 is changed, the process is called -with 0 delay- and an event happens on R1, so the process is called again immediately -with 0 delay- so the value of R1 will update with the value of R0 which hasn’t changed, and the value of R2 will update with the new value of R1, and a new event of R2 happens and the process is called again and this all happens with 0 delay 34 | - So when we have a fully populated sensitivity list, the code within the process became compinational 35 | - A process with a deficient sensitivity list will be used to declare registers, A process with a complete sensitivity list will be used to declare complicated combinational blocks like state machines. 36 | 37 | ![fully-populated-senstivity-list](imgs/process-transaction-event/fully-populated-senstivity-list.png) -------------------------------------------------------------------------------- /vhdl/12-mux-vhdl.md: -------------------------------------------------------------------------------- 1 | # Multiplexing in VHDL 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Mux outside process 5 | - `When .. else` , `with .. select` 6 | - Concurrent code that can be written in the body of an architecture outside the process statement 7 | - Used to describe multiplexer and they are very safe to use 8 | - The last else statement is else not else if and the last condition in with .. select is when others 9 | - Cause the type is std_logic_vector can take values of 0,1,x, .. and values other than 0 and 1 so there is other possibilities for a 2 bit mux 10 | - The synthesizer has to know what to do when other possibilities happen therefore the last statement has to include everything else, otherwise the synthesizer gonna give you an error because it doesn’t know what to do when the select line is at these other values 11 | - So it’s important to remember that std_logic types has other values, it’s safe in this case cause the synthesizer gonna give you an error, but it’s not the case in the process 12 | 13 | ``` 14 | signout <= A when sel="00" else 15 | B when S="01" else 16 | C when S="10" else 17 | D; 18 | ``` 19 | 20 | ``` 21 | with sel select 22 | signout <= A when "00" 23 | B when "01" 24 | C when "10" 25 | D when others; 26 | ``` 27 | 28 | ![with-select-when-else-mux](imgs/mux/with-select-when-else-mux.png) 29 | 30 | ## Mux inside a process 31 | - Process statement allows us to use a host of a very flexible syntax 32 | - `if .. else` , and `case` statements, very similar to programming languages and behaves the same way 33 | - Multiplexers are combinational logic, so when implemented in a process we have to have a fully populated sensitivity list 34 | - Look at the right side of the statements, any signal used in assignment, put it in the list 35 | - Last statement is else not elsif cause the same reason of std_logic can take other values than 0, 1 36 | - The problem is that you can write if .. else structure that is missing some of the conditions cause having this option is necessary to be able to declare memory statements. 37 | - latches, registers require you to declare if … else statements with some missing conditions 38 | - Same with the last case in case statement, it has to be when others 39 | - Difference between mux using if .. else in process and outside is that in process it’s a priority encoder, the order of conditions matter 40 | - You can mix ifs and case statements as you like as long as you make sure there is always an exhaustive list of conditions, and fully populated sensitivity list 41 | 42 | ``` 43 | process(sel, A, B, C, D) 44 | begin 45 | if sel="00" then 46 | sigout <= A; 47 | elsif sel="01" then 48 | sigout <= B; 49 | elsif sel="10" then 50 | sigout <= C; 51 | else 52 | sigout <= D; 53 | end if; 54 | end process; 55 | ``` 56 | 57 | ``` 58 | process(sel, A, B, C, D) 59 | begin 60 | case sel is 61 | when "00" => 62 | sigout <= A; 63 | when "01" => 64 | sigout <= B; 65 | when "10" => 66 | sigout <= C; 67 | when OTHERS => 68 | sigout <= D; 69 | end case; 70 | end process; 71 | ``` -------------------------------------------------------------------------------- /vhdl/16-Registers-in-VHDL.md: -------------------------------------------------------------------------------- 1 | # Registers in VHDL 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Registers declaration 5 | - delcared in processes by chaning a signal D on a clk'event positive edge or negative edge 6 | - Process sensitivity list doesn’t include D, if you put D, it won’t make any difference for the synthesis as the Q value doesn’t change unless there is a positive edge on clk 7 | - For latches we had to put D in the sensitivity list because the condition was true for a long time (half clock cycle) so if D change during the positive cycle we need to update Q 8 | 9 | ``` 10 | entity DFF is 11 | port( 12 | D: in std_logic; 13 | clk: in std_logic; 14 | Q: out std_logic 15 | ); 16 | end entity; 17 | 18 | architecture structural of DFF is 19 | 20 | process(clk) 21 | begin 22 | if clk'event and clk = '1' then 23 | Q <= D; 24 | end if; 25 | end process; 26 | 27 | end architecture; 28 | ``` 29 | 30 | ## Synchronous and Asynchronous signal 31 | - In asynch signal the signal has to be added to the sensitivity list. 32 | - In sycnh signal the clock masks its function, it won’t function without a clock edge 33 | - Asic tools recognise the form of asynch reset and replace it with a scan register which is helpful in design testability 34 | - Having an asynch reset is very useful, because in state machines it’s always good to have, a state to which you can go back when something goes wrong and that’s the reset state to override anything that could have gone wrong with the clock, pipeline etc 35 | 36 | ### Synchronous enable 37 | 38 | ``` 39 | process(clk) 40 | begin 41 | if clk'event and clk = '1' then 42 | if enable='1' then 43 | Q <= D; 44 | end if; 45 | end if; 46 | end process; 47 | ``` 48 | ### Asynchronous enable 49 | 50 | ``` 51 | process(clk, enable) 52 | begin 53 | if enable='1' then 54 | if clk'event and clk = '1' then 55 | Q <= D; 56 | end if; 57 | end if; 58 | end process; 59 | ``` 60 | 61 | 62 | ## Registers usage 63 | - Two reasons to declare registers 64 | - Use it in a pipeline 65 | - Use it as a general storage in a register file 66 | -------------------------------------------------------------------------------- /vhdl/17-pipelining-in-VHDL.md: -------------------------------------------------------------------------------- 1 | # Pipelining in VHDL 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | 5 | ## Pipelining 6 | - Strongly recommend against mixing positive and negative edge triggered registers at least in the same module, 7 | - some synthesis tool will refuse to synthesize a design with two clock edge, others will end up reducing frequency of operation by half 8 | - Separating combinational and sequential logic, separating processing and registering 9 | - Mixing them would result in an unreadable code, you have to think about which value is being processed 10 | 11 | ``` 12 | process(clk, reset) 13 | begin 14 | if reset='1' then 15 | ap <= (others=>'0'); 16 | bp <= (others=>'0'); 17 | cp <= (others=>'0'); 18 | dp <= (others=>'0'); 19 | m1pp <= (others=>'0'); 20 | m2ppp <= (others=>'0'); 21 | m3 <= (others=>'0'); 22 | cpp <= (others=>'0'); 23 | dpp <= (others=>'0'); 24 | dppp <= (others=>'0'); 25 | elsif clk'event and clk = '0' then 26 | ap <= a; bp <= b; 27 | cp <= c; 28 | m1pp <= m1p; cpp <= cp; 29 | m2ppp <= m2pp;dp <= d; 30 | dpp <= dp; dppp <= dpp; 31 | m3 <= m3ppp; 32 | end if; 33 | end process; 34 | 35 | m1p <= ap * bp; 36 | m2pp <= cpp * m1pp; 37 | m3ppp <= dppp * m2ppp; 38 | 39 | ``` 40 | 41 | ![fully-pipelined-three-multiplier-cascade](imgs/pipelining/fully-pipelined-three-multiplier-cascade.png) 42 | -------------------------------------------------------------------------------- /vhdl/18-variables-and-signals.md: -------------------------------------------------------------------------------- 1 | # Variables and signals 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | 5 | ## Signals vs variables 6 | - Signals are real physical electrical nodes in a circuit 7 | - Variable is a temporary storage location that exists only within a process 8 | 9 | ## variable usage 10 | - Useful in multiport memory, loops, counters 11 | - Should be careful about how they are used, and should be aware of what they synthesize into 12 | - They can be initialized to an initial value in the first process call, then they update their value each process call 13 | - There is also global variables 14 | - Unlike signals variables update immediately after they are assigned, they don’t get scheduled to update at the end of the process, there is no distinction between transactions and events in variables 15 | - A signal assignment is a transaction, and it becomes an actual change or an event when we meet a wait statement 16 | -------------------------------------------------------------------------------- /vhdl/19-Counters.md: -------------------------------------------------------------------------------- 1 | # Counters 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Counters 5 | - A counter consists of a Register and an adder 6 | - Counters are one of the main exceptions of the rule about not mixing arithmetic and registering in the same process because we know what they do and look like and it’s predictable 7 | - In the example If you hardwire the count_up signal to 1 the synthesizer will know you want an up counter only and it’ll replace it with a standard cell that’ll only count up, same goes for other signals 8 | - So you don’t need to change the syntax if you want different hardware behaviour, you can hardwire signals and the synthesizer is smart enough to detect what you mean by this 9 | 10 | ``` 11 | process(clk, reset) 12 | begin 13 | if reset='1' then 14 | counter_out <= (others => '0'); 15 | elsif clk'event and clk = '1' then 16 | if enable_counter = '1' then 17 | if count_up = '1' then 18 | counter_out <= counter_out + 1; 19 | else 20 | counter_out <= counter_out - 1; 21 | end if; 22 | end if; 23 | end if; 24 | end process; 25 | ``` 26 | 27 | ## Counters using variables 28 | - Counters can and often are declared using variables, 29 | - One of the ways in which variables can be safely used and the results of synthesis are very predictable 30 | - One problem is that the variable exists only within the process, so if you need this value of the counter to be used somewhere else, with concurrent statements outside processes for example, you are better off declaring the counter using signals 31 | 32 | ``` 33 | process(clk, load_counter) 34 | variable counter_out : integer range 0 to 7 := 0; 35 | begin 36 | if clk'event and clk='1' then 37 | counter_out := (counter+1) mod 5; 38 | end if; 39 | end process; 40 | ``` 41 | -------------------------------------------------------------------------------- /vhdl/2-entities-and-architecture.md: -------------------------------------------------------------------------------- 1 | # Entities and architecture 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## design construction 5 | - A vhdl design consists of at least two parts one entity and at least one architecture 6 | 7 | ## Entity 8 | - Entity describes that there is a building block 9 | - It gives it a name 10 | - Defines the ports of this block (names, directions, sizes) 11 | - Does not indicate how this entity is implemented on the inside or how many times it’s used 12 | ## Architecture 13 | - Architecture describe how the entity is implemented on the inside 14 | - architecture arch-name of entity’s-name is 15 | - Declaration of internal signals of the architecture, components used inside, constants used 16 | - Begin 17 | - Design implementation 18 | - End architecture 19 | 20 | ## Relationship between entity and architecture 21 | - Entity could have multiple architectures, when entity is instantiated, we can specify which architecture to use 22 | - By default all instantiations will use the last declared architectures unless otherwise stated. 23 | -------------------------------------------------------------------------------- /vhdl/23-loops.md: -------------------------------------------------------------------------------- 1 | # Loops 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## For generate statement 5 | - It is different than loops 6 | - It’s is a structure that is used in concurrent vhdl outside the process, 7 | - Doesn’t describe a loop, it describes a repeated component instantiations 8 | - There is usually something that binds those instationations together like having input or outputs coming from the same bus 9 | - This is particularly true when the number of instantiations is generic 10 | - It can always replaced by multiple instantiations 11 | ## loops 12 | - Used in the sameway like programming languages 13 | - Can only be used in process statement, and happens in sequence 14 | 15 | ### For loops 16 | - Variable is implicitly declared, sensitivity list is full, but an implicit latch is created because the if statement has no else 17 | 18 | ``` 19 | process(Din) 20 | begin 21 | for loop_condition in 0 to 9 loop -- loop condition is a variable 22 | if conv_integer(Din) = loop_condition then 23 | flag <= '1'; 24 | end if; 25 | end loop; 26 | end process; 27 | ``` 28 | 29 | ### While loops 30 | - A more complicated conditions can be used in while loops, increment can be more than one unlike for loops 31 | - Any variable has to be explicitly declared in the process declarations section 32 | 33 | ``` 34 | process(Din) 35 | variable loop_condition : integer; 36 | begin 37 | loop_condition := 0; 38 | while loop_condition < 10 39 | if conv_integer(Din) = loop_condition then 40 | flag <= '1'; 41 | end if; 42 | loop_condition := loop_condition + 1; 43 | end loop; 44 | end process; 45 | 46 | ``` 47 | 48 | ### loops execution time 49 | - It takes zero time to execute the loop, everytime the process is called the loop executes once instantaneously 50 | - Exit or break and next or continue statements can be used in loops 51 | 52 | ``` 53 | process(Din) 54 | begin 55 | for loop_condition in 0 to 9 loop 56 | if conv_integer(Din) = loop_condition then 57 | flag <= '1'; 58 | end if; 59 | if conv_integer(Din) = 5 then 60 | exit 61 | end if; 62 | if conv_integer(Din) = 3 then 63 | next 64 | end if; 65 | end loop; 66 | end process; 67 | ``` 68 | ## loops synthesises 69 | - Loops in general are synthesizable 70 | - Problem with some loops is that you can't guess what kind of hardware the synthesizer is gonna replace the loop with 71 | - This is particularly true with very complicated loops with next or exit statements, or loops embedded in conditions 72 | - Advice about loops if you can guess the hardware will result from using the loops then use it, 73 | - If you find yourself using the loops the same way as in programming languages then you probably need to step back and guess what kind of hardware would result from the description you are using 74 | - Example of using loops in shift registers 75 | -------------------------------------------------------------------------------- /vhdl/24-software-testbench.md: -------------------------------------------------------------------------------- 1 | # VHDL software testbenches 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Testbench 5 | - Testing is a whole different science and will be covered in a later module 6 | - At its core at least functional testing and verification of the design means that you wanna ensure that a design is performing the function you want it to perform 7 | - You apply inputs to the unit under test, observe the outputs and compare them with the outputs you know are true 8 | - It’s a vhdl design but its entity doesn’t have any ports, only an architecture with a single component the unit under test 9 | 10 | ## software testbench 11 | - Software testbench means it’ll be used only in software and not gonna pass through synthesis so it doesn’t need to be synthesizable so they allow you programming flexibility to generate inputs and assess the outputs 12 | 13 | ![testbench-setup](imgs/testbench/testbench-setup.png) 14 | 15 | ``` 16 | process 17 | begin 18 | Din <= conv_std_logic_vector(1,4) after 10ns; 19 | conv_std_logic_vector(2,4) after 100ns; 20 | Q <= conv_std_logic_vector(3,4) after 100ns; 21 | wait; 22 | end process; 23 | ``` 24 | ### assert statements 25 | - They look at a condition and if it’s met, they perform a certain assertion 26 | - Can be used concurrently or sequentially 27 | - Assert condition report “message” severity severityLevel 28 | - Severity levels: note, warning, error, and failure 29 | - Note, warning, error are quantitative statements about what has happened 30 | - Failure will cause the simulation to halt 31 | - Everything is optional the condition, report, severity level if not existent the condition will be assument always true, the default report string is displayed, and default severity of error is assumed by default 32 | 33 | ``` 34 | A <= B+C; 35 | Aout <= A(15 downto 0); 36 | -- B and C are 16 bits each 37 | assert A(16) = '1' report "overflow has occured" severity error; 38 | ``` 39 | 40 | #### Assert in processes 41 | - assert statement will be implemented sequentially cause it’s in a process 42 | - The image attribute will return the string equivalent of the integer value within the parenthesis 43 | - At the positive edge of the clock when Dout changes, a transaction happens and the assert will print the previous value, 44 | - At the negative edge the transaction would have been turned into an event and the current value of Dout will be displyed 45 | ``` 46 | process(clk) 47 | begin 48 | if clk'event and clk='1' then 49 | D1 <= D; 50 | D2 <= D1; 51 | D3 <= D2; 52 | Dout <= D3; 53 | end if; 54 | assert report "Value of Dout is" & integer'image(conv_integer(Dout)); 55 | end process; 56 | ``` 57 | 58 | ### Assert synthesis 59 | - Synthesis tool will ignore assert statements if used in the design 60 | 61 | ## hardware testbenches 62 | - Software testbenches are software constructs that only run in simulation to verify the design 63 | - Hardware testbenches are design that contain the unit under test as well as the test circuitry and its supposed to pass through synthesis 64 | - They are used because of speed, as they run as fast as the underline unit under test, software simulations takes a lot longer than the uut 65 | - Hardware testbenches are usually done are FPGAs not on ASICs 66 | - When used on ASICs this is called design for testability, and that testing hardware is usually expected to be part of a finished product not a prototype 67 | -------------------------------------------------------------------------------- /vhdl/26-functions.md: -------------------------------------------------------------------------------- 1 | # Functions in VHDL 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Functions 5 | - Same as in programming language, but we have to know how they are synthesized 6 | - Declared in the architecture declaration body, if it needs to be used multiple times, it has to be declared in a package 7 | - Can only use variable assignment, cannot use signals within a function 8 | - Function can accept any number of arguments, has to be declared as inputs 9 | - Can have one return value 10 | - Functions can be called as a concurrent or sequential statements 11 | - Function body can be written using any statement that can be used within a process statement and execution of statements within a function happen sequentially 12 | - Values of variables or constants within a function can exist only within a function call and will reset between different calls 13 | - You cannot use wait statement in functions 14 | 15 | ``` 16 | function quad_calc(a,b,c,x : integer) return std_logic_vector(16 downto 0) is 17 | variable power1 : integer := 2; 18 | variable power2 : integer := 1; 19 | variable power3 : integer := 0; 20 | variable return_value : integer ; 21 | begin 22 | return_value := a*x**power1+b*x**power2+c*x**power3; 23 | return conv_std_logic_vector(return_value,17); 24 | end quad_calc; 25 | ``` 26 | 27 | ## pure and impure functions 28 | - Functions can be declared a pure or impure, majority are pure 29 | - Pure functions are functions whose return value is defined exclusively through its input arguments and its impact on the world happens only by its return value 30 | - Impure functions are functions whose return value depends on other variables outside the function 31 | 32 | ``` 33 | impure function raise_to_power(constant x : integer) return integer is 34 | return x**global_power; 35 | end raise_to_power; 36 | ``` 37 | 38 | ## synthesis 39 | - Functions are generally synthesizable 40 | - The only problem is what results from the synthesis cause functions can use very flexible syntax and tend to use a lot of arithmetic 41 | - Rule of thumb: if you use a function whose return value will reduce to a number at synthesis time then feel free to use anything within it -------------------------------------------------------------------------------- /vhdl/27-procedures-and-overloading.md: -------------------------------------------------------------------------------- 1 | # Procedures and overloading 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Procedure 5 | - Similar to functions with two differences 6 | - Procedures can use signal assignments 7 | - Procedures can have arguments that are input, output or inout direction and doesn’t have a return cause it can return values as output signals 8 | - Procedures ins and outs are similar to entity’s ports in a way, they are the bridge between entities and functions in a way 9 | 10 | ``` 11 | procedure batch_calculate( 12 | a, b, c : in integer; 13 | signal d, e, f: out integer; 14 | signal g : inout integer) is 15 | begin 16 | d <= a*a; 17 | e <= b*b; 18 | f <= c*c; 19 | g <= g*g; 20 | end batch_calculate; 21 | ``` 22 | 23 | ## overloading 24 | - Common in programming languages 25 | - Redefining a function multiple times with different arguments lists 26 | - It’s legal and useful, the synthesizer look at the argument list used when the function is called and determine the definition 27 | - Operators are special functions, operators in vhdl are overloaded cause you can say a+b with any type std_logic_vector, integer, and it’ll use the + with the different data types differently 28 | ## predefined functions in std packages 29 | - Conversion functions in std packages convert a type to another type, usually used to move between std_logic_vector and integers 30 | 31 | ### conv_integer 32 | - conv_integer(std_logic_vector) 33 | - Converts std_logic_vector into integers 34 | - Has to be used either after defining either std_logic_signed or std_logic_unsigned packages, they’ll redefine the function for signed or unsigned numbers 35 | 36 | ### conv_std_logic_vector 37 | - conv_std_logic_vector(integer, size of the bus) 38 | - Has to be defined either for signed or unsigned numbers 39 | 40 | ### conv_signed and conv_unsigned 41 | - conv_signed(), conv_unsiged() 42 | - used to convert std_logic_vector types 43 | - they can accept integer numbers 44 | - Convert between unsigned and signed types and used when we mix between them in operation 45 | - If you are unsure of using signed or unsigned number it’s safer to use signed numbers cause you don’t know if you have negative numbers 46 | -------------------------------------------------------------------------------- /vhdl/29-Packages.md: -------------------------------------------------------------------------------- 1 | # Packages in VHDL 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Packages 5 | - Packages are collections of named items that can be reused across multiple designs across the same work library 6 | - Collections of named items: types, subtypes, functions, procedures, components, attributes, constants, files and so on 7 | - Can be used to centralize the location where any of these things are declared 8 | - Using package: use work.my_synth_package.all 9 | 10 | ``` 11 | package my_synth_package is 12 | constant bus_width : integer := 16; 13 | component full_add is 14 | port (a, b, cin: in std_logic; 15 | s, cout : out std_logic); 16 | type state_machine_type is (reset, wait, operate); 17 | end my_synth_package; 18 | ``` 19 | ### Hardware cost 20 | - Declare a package or declare use of it does not have an impact on resource usage unless you actually call it in a design 21 | - Packages are synthesizable if all of its constituents are synthesizable so it’s generally useful to split your packages to synthesizable packages and unsynthesizable 22 | - Packages can be separated into package declaration and package body, everything within the package must be declared in the declaration section, but things can be relegated to the body of the package like constants values, or function declarations 23 | 24 | ``` 25 | package my_synth_package is 26 | constant bus_width : integer; 27 | component full_add is 28 | port (a, b, cin: in std_logic; 29 | s, cout : out std_logic); 30 | 31 | function linear_combine(combine_vector: in std_logic_vector (2 downto 0)); 32 | return std_logic; 33 | end my_synth_package; 34 | 35 | package body my_synth_package is 36 | constant bus_width : integer := 16; 37 | function linear_combine(combine_vector: in std_logic_vector (2 downto 0)); 38 | return std_logic is 39 | begin 40 | return (combine_vector(0) xor combine_vector(1) xor combine_vector(2)); 41 | end; 42 | 43 | end my_synth_package; 44 | 45 | ``` 46 | 47 | -------------------------------------------------------------------------------- /vhdl/3-IEEE-library-and-std-logic.md: -------------------------------------------------------------------------------- 1 | # IEEE library and std logic 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Libraries 5 | - Any vhdl design is dependent on the presence of libraries. 6 | - libraries are collections of entities, components and functions that we have already added to the design 7 | - Any library contains a number of packages, each package contains functions, types, subtypes. 8 | 9 | ### Two important libraries 10 | - Work library, used by default, no need to indicate using it, it’s the library that contains everything that you have designed so far 11 | - IEEE library, almost always used, it contains a set of data types, functions, operations that are very commonly used and very useful 12 | 13 | ### IEEE library 14 | - IEEE library contains five major packages. 15 | - most important package ieee.std_logic_1164, 16 | - this package opens up the standard logic data types for use 17 | - A value of 0 and 1 indicate that the node is strongly driven towards ground or supply from a low impedance path of an uncontested logic gate 18 | - Allows us to define different values for signals other than 0,1: X, U, Z, -, H, L, W 19 | - It’s extremely important to remember that std logic can have more values then 0 and 1, cause when we design we are mostly concerned with 0 and 1, cause they are meaningful values, but the synthesizer doesn't really know that they are just 0 and 1, it knows that they can be something else. 20 | - If we forget this fact, we can end up adding latches where we don’t want them to exist. 21 | 22 | ### Other packages 23 | - std_logic_arith, contains description of all arithmetic operators, a redefinition of them which are defined by default in vhdl in bit type 24 | - std_logic_signed, std_logic_unsiged mutually exclusive, you cannot declare using both because these two packages declare that the numbers in the registers are either signed two’s complement numbers or unsigned positive numbers, so they augment the arithmetic package but indicating the kind of numbers in the regs 25 | - std_logic_textio allows us to use files inputs and outputs to write and read data from files, four functions and data types. 26 | -------------------------------------------------------------------------------- /vhdl/30-good-design-practices.md: -------------------------------------------------------------------------------- 1 | # Good design practices in vhdl 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Good practices in code 5 | - Synthesizable 6 | - Predictable the kind of hardware that results from synthesizing the code is something you can foresee in advance 7 | - When sometimes it’s safe to let the synthesizer figure out how to implement the behavioural code you write, sometimes you really wouldn’t like to see what comes out on the other end 8 | - Readability 9 | - Portability among different platforms 10 | - Scalability adaptable bus width 11 | ## Synchronous pipeline 12 | - Use single clock and only the positive edge of the clock 13 | - Don’t ever depend on the two edges of a clock 14 | - If you need to use multiple clocks which are not harmonics of each other, then you need to use some synchronization techniques to allow data to pass between clock domains 15 | - Use registers, don’t use latches 16 | - You can use latches to design high speed latch loops, but that should only be used in small circuits and only on ASICs not FPGAs 17 | - Once you finished your code, you should look for implicit latches and remove them, they usually show on the warning report of the synthesis 18 | - DSP blocks between registers should be written using concurrent statements, you can also use processes which have complete sensitivity list and shouldn’t any unspecified conditions for conditional statements 19 | - Separate sequential processes from combinational logic processes 20 | - For all registers have a global asynchronous reset 21 | - Registers only used for pipelining, any need for mass storage use memories rams 22 | - Every single number that you use like bus widths, all numbers have to be written in terms of generics 23 | - When you declare a component and use a port map for it be sure to use a generic map and a port map, and make the connection explicitly 24 | - Keep using generics in all levels of instantiations till you reach the top wrapper module 25 | - The wrapper module shouldn’t have any logic in it, only instantiations of all big modules and define all the generics and all the ports of the top level design 26 | ## libraries 27 | - Should include IEEE library and std_logic_1164 package 28 | - Declare the use of std_logic_arith package which open the use of operators 29 | - Declare either the std_logic_signed or unsigned with std_arith package 30 | ## Things that might cause issues during synthesis 31 | - Functions and procedures 32 | - often synthesizable, for very complicated functions you can’t always decide what kind of hardware will result from this 33 | - Rule of thumb: if you use a function whose return value will reduce to a number at synthesis time then feel free to use anything within it 34 | - Packages 35 | - Really good because they make code readable, easily modifiable, portable 36 | - You should separate your packages to fully synthesizable packages and fully unsynthesizable for use with testbenches 37 | - Variables 38 | - Generally synthesizable 39 | - Can sometimes be confusing in terms of how they update within a process because they are counter intuitive once you have digested how signal transactions turn into signal events 40 | - There are cases when we have to use variables like in multiport memories and counters 41 | - Attributes 42 | - Some of them are synthesizable, some are absolutely not, some aren’t but you have to know what you are doing 43 | - Files 44 | - All forms of files access aren’t synthesizable, and usually will not cause synthesis error cause the synthesizer will ignore them 45 | - One exception when you initialize the values of a rom 46 | - Wait statements 47 | - Complicated, synthesizability of process with wait statements can vary 48 | - wait on signal variable and wait until are generally synthesizable 49 | - wait for and wait are generally unsynthesizable 50 | - Generally any wait statement or attribute that mentions value of time is not synthesizable -------------------------------------------------------------------------------- /vhdl/4-User-defined-types.md: -------------------------------------------------------------------------------- 1 | # User defined types 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Types and subtypes 5 | - User defined types and subtypes are good practice that improve code readability without impacting synthesizability in any way 6 | - A port is declared in the entity and it describes input/output signals 7 | - A signal is a node, or wire, internal connection, not a register, declared in the arch 8 | - Enumeration when translated to hardware they will be translated into registers carrying bits, useful in a state machines 9 | - Array are important, used extensively when describing memories 10 | - Subtypes, subsets of the types 11 | - Types and subtypes only materialize +when used to declare a signal, declaring a type doesn’t indicate a signal declaration 12 | 13 | ``` 14 | type my_list is (orange, apples, fifteen, seventy, John); 15 | --Usage: signal a1 : mylist; 16 | 17 | type register_file is array(array_length-1 downto 0) of std_logic_vector(entry_size-1 downto 0); 18 | 19 | subtype short_vector is std_logic_vector(3 downto 0); 20 | subtype eight_bit_int is integer range 0 to 255; 21 | ``` -------------------------------------------------------------------------------- /vhdl/5-operators.md: -------------------------------------------------------------------------------- 1 | # operators 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | - When using operators in vhdl, you have to make sure that the signal that is used to store the result is wide enough to allow the storage of the result noiselessly 5 | - An adder of two N bits wide operands, requires N+1 bits for the result 6 | - A multiplier of M and N bits wide operands, requires M+N bits wide result 7 | - Then you can perform truncation of the result if you want 8 | - Comparison operators act on integers or std_logic types, and produce a boolean or logical result either 0 or 1 but they are not binary values or bits, they are true and false results 9 | - They will generally be implemented in hardware using subtractors then will look at the sign bit of the result to find out if the operand greater or not 10 | - add, subtract, shift, concatenation, comparison operators are safe operations, hardware cost is very low and the synthesizer is really good at producing good hardware out of them. 11 | - Caution with multiply operator, cause they are relatively slow, gotta be careful about the width of the output which require performing fixed point simulation before vhdl, and the number of multipliers used and if you could timeshare some of multipliers do so. 12 | - In a good hardware implementation the critical path will usually be the path with multipliers 13 | - Suggest never use exponentiation, division, remainder, quotient operators because it’s really hard to predict how this would get translated into hardware depends on the vendor and the synthesizer, but anyway the resulting hardware is gonna be really bad, slow, and power hungry 14 | - Mostly division can be replaced by multiplication somewhere else in the logic 15 | - Shift operators are preference and they’ll produce predictable hardware but it’s more readable and easier to write shifting using the concatenation operator 16 | -------------------------------------------------------------------------------- /vhdl/6-attributes.md: -------------------------------------------------------------------------------- 1 | # attributes 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Attributes 5 | - Special way to extract information about named object (signal, component, instance, entity, data type) in vhdl 6 | - Their position regarding synthesizability is a question 7 | - Useful in scalable code with generics, and it’s a very good practice to do so 8 | - Ex. define a signal with a range same as another signal’s length s2 : std_logic_vector(s1’length-1 downto 0) 9 | 10 | ## Attrbiutes Synthesizability 11 | - Some attributes are safe to use in a synthesizable code, others are not 12 | - Any attribute that creates a copy of a signal, or deals with time as an operand or as a return that attribute should never be used in the design, it should be used in the test bench to do testing 13 | - Attributes that act on data types or gives you information about data types are generally safe to use, if they are used in a correct way so that return a value that is constant at synthesis time they can be perfectly safe to use 14 | - Attributes that deals with entities and entities name are usually used in assert statements in order to aid in debugging, this means they’ll normally ignored in synthesis so it doesn’t matter if used or not 15 | - General advice, use attributes carefully 16 | 17 | ## User defined attributes 18 | - Only useful for very large designs involves many design teams that need to move information between designs and work libraries 19 | 20 | ``` 21 | attribute state_encoding of state_type: type is "01 11 10 00"; 22 | attribute sizeadder of adder1: component is very_big; 23 | attribute sizeadder of adder2: component is very_small; 24 | ``` -------------------------------------------------------------------------------- /vhdl/7-hierarchical-design.md: -------------------------------------------------------------------------------- 1 | # Hierarchical design 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Components 5 | - A component is a design that exists in the work library, declared somewhere else as an entity with its architecture so its a complete design available for use in the current desgin because it belongs to the work library 6 | - Component entityName is ... port declaration of entity ... end component 7 | - It does not indicate how many instantiations of the entity gonna be used in the architecture or how they’ll be connected, it just indicates our intention to use this entity in our architecture, so far we haven’t actually used it and it would not be added to our hardware cost. 8 | 9 | ## Components in hardware 10 | - Hardware cost, critical path, everything is dependant upon the part after begin keyword of the architecture 11 | 12 | ## Component instantiation 13 | - Instantiating a component after begin 14 | - Optional_label_name(recommended) : component_name/entity’s_name 15 | - Port map(Listing of input and output ports of the instance); 16 | - Each port of any instance has to be connected to either an internal signal or one of the input output ports of the layered design 17 | 18 | ## Example 19 | 20 | - Declaring a component 21 | 22 | ``` 23 | architecture hierarchical of layered_adder is 24 | 25 | component sixteen_bit_adder is 26 | port( 27 | input_a: in std_logic_vector (16-1 downto 0); 28 | input_b: in std_logic_vector (16-1 downto 0); 29 | add_output: out std_logic_vector (17-1 downto 0) 30 | ); 31 | end component; 32 | 33 | component seventeen_bit_adder is 34 | port( 35 | input_a: in std_logic_vector (17-1 downto 0); 36 | input_b: in std_logic_vector (17-1 downto 0); 37 | add_output: out std_logic_vector (18-1 downto 0) 38 | ); 39 | end component; 40 | 41 | signal internal_inputa: std_logic_vector(17-1 downto 0); 42 | signal internal_inputb: std_logic_vector(17-1 downto 0); 43 | ``` 44 | 45 | - Using a component/instantiating an entity 46 | 47 | ``` 48 | beign 49 | 50 | adder1: sixteen_bit_adder 51 | port( 52 | input_a => external_inputa, 53 | input_b => external_inputb, 54 | add_output => internal_inputa); 55 | 56 | adder2: sixteen_bit_adder 57 | port( 58 | input_a => external_inputc, 59 | input_b => external_inputd, 60 | add_output => internal_inputb); 61 | 62 | adder3: seventeen_bit_adder 63 | port( 64 | input_a => internal_inputa, 65 | input_b => internal_inputb, 66 | add_output => external_output); 67 | ``` 68 | 69 | ![component-arch-use](imgs/hierarchical-design/component-arch-use.png) -------------------------------------------------------------------------------- /vhdl/8-special-port-mapping.md: -------------------------------------------------------------------------------- 1 | # special port mapping 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Port mapping 5 | - All ports have to be connected, even inputs that are don't care, even outputs that are not used have to be connecte, maybe to an open circuit. 6 | - input_a => (others => ‘0’), connect input a to a (bus, register, locations) carrying all zeros, it’s better to use this cause it makes code scalable 7 | - others syntax is useful when you want to concatenate a string of ones or zeros to complete a certain port or a certain register 8 | - Input_b => external_input(8 downto 0) & (others => ‘1’), 9 | - output_a => open, connects the output to an open circuit 10 | - Input_c => conv_std_logic_vector(9,16), this function converts the integer number 9 to a standard logic vector of width 16 11 | 12 | ## unconnected ports 13 | - When inputs are left open or connected to constant value 14 | - It allows the synthesizer to trim a lot of circuitry 15 | - It trims or remove every logic in the component that is connected to an open circuit or unconnected output 16 | - It’s a good practice to do so cause it allows it to minimize the resource usage 17 | - This is the case with constant inputs, if for example an adder or multiplier have two constant inputs, the synthesizer will remove the hardware, and replace it with a constant value which is the result of the process. 18 | 19 | ![trimmed-circuits](imgs/special-port-mapping/trimmed-circuits.png) 20 | 21 | ## For generate 22 | - for generate syntax to generate a bunch of instances 23 | - It’s not a loop, it’s a way of indicating that we are generating a very large number of the same component 24 | 25 | ``` 26 | gen_reg: for generation_index int 0 to 15 generate 27 | 28 | DFFX : DFF 29 | port map( 30 | D => D(generation_index), 31 | Q => Q(generation_index), 32 | clk => clk); 33 | 34 | end generate; 35 | ``` 36 | 37 | ## Binding architecture to a component 38 | - Binding a certain architecture to a component while instantiating 39 | - Any instantiation will assume the last entity’s architecture unless otherwise stated 40 | - To choose other architecture, when declaring an instance write the architecture name between () after the entity’s name 41 | 42 | ``` 43 | Add1: entity word.sixteen_bit_add(behavioral1) 44 | port map(input_a => external_inputa, 45 | input_b => external_inputb, 46 | add_output => internal_inputa); 47 | Add2: entity word.sixteen_bit_add(behavioral2) 48 | port map(input_a => external_inputc, 49 | input_b => external_inputd, 50 | add_output => internal_inputb); 51 | ``` 52 | -------------------------------------------------------------------------------- /vhdl/9-constants-and-generics.md: -------------------------------------------------------------------------------- 1 | # Constants and generics 2 | source [this](https://www.youtube.com/playlist?list=PLyWAP9QBe16p2HXVcyEgGAFicXJI797jK) playlist on VHDL design. 3 | 4 | ## Constants 5 | - Constants same as programming languages constant, declared in the architecture using constant keyword, 6 | - can be used to declare other constants or signals, widths. 7 | - it’s a good practice because they help centralize numbers 8 | 9 | ## Generics 10 | - generics used exactly the same way as constants, 11 | - they are labels that have constant numbers attached to them, 12 | - the only difference is that generic is declared in the entity not in the architecture. 13 | - Generics can be used in the port declaration and desgin’s architecture 14 | - Generic map is optional in instantiation, 15 | - you can declare some generics and leave others to get the default value, 16 | - if there is no default value this is an error 17 | 18 | ## Difference between them 19 | - Difference between constants and generics is that 20 | - generics can be left without a default value, 21 | - constants must have a value. 22 | 23 | ## Good practice 24 | - Good practice in layered design is to use generics for all layers’ instantiations except the top layer you assign a value to this top layer’s generics cause this gives you scalable designs 25 | -------------------------------------------------------------------------------- /vhdl/README.md: -------------------------------------------------------------------------------- 1 | # VHDL 2 | 3 | 1. [design-philosophy](1-design-philosophy.md) 4 | 2. [entities-and-architecture](2-entities-and-architecture.md) 5 | 3. [IEEE-library-and-std-logic](3-IEEE-library-and-std-logic.md) 6 | 4. [User-defined-types](4-User-defined-types.md) 7 | 5. [operators](5-operators.md) 8 | 6. [attributes](6-attributes.md) 9 | 7. [hierarchical-design](7-hierarchical-design.md) 10 | 8. [special-port-mapping](8-special-port-mapping.md) 11 | 9. [constants-and-generics](9-constants-and-generics.md) 12 | 10. [process-transactions-events](10-process-transactions-events.md) 13 | 11. [Wait-statement](11-Wait-statement.md) 14 | 12. [mux-vhdl](12-mux-vhdl.md) 15 | 13. [latches](13-14-15-latches.md) 16 | 16. [Registers-in-VHDL](16-Registers-in-VHDL.md) 17 | 17. [pipelining-in-VHDL](17-pipelining-in-VHDL.md) 18 | 18. [variables-and-signals](18-variables-and-signals.md) 19 | 19. [Counters](19-Counters.md) 20 | 20. [Memories-in-VHDL](20-Memories-in-VHDL.md) 21 | 21. [fsm](21-fsm.md) 22 | 23. [loops](23-loops.md) 23 | 24. [software-testbench](24-software-testbench.md) 24 | 25. [file-io](25-file-io.md) 25 | 26. [functions](26-functions.md) 26 | 27. [procedures-and-overloading](27-procedures-and-overloading.md) 27 | 28. [configurations](28-configurations.md) 28 | 29. [Packages](29-Packages.md) 29 | 30. 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